ST STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines Reference Manual
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RM0031
Reference manual
STM8L050J3, STM8L051F3, STM8L052C6, STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines
Introduction
This reference manual targets application developers. It provides complete information on how to use memory and peripherals on STM8L050J3, STM8L051F3, STM8L052C6,
STM8L052R8 MCUs and STM8L151/L152, STM8L162, STM8AL31, STM8AL3L lines.
STM8Lxxx and STM8ALxx microcontrollers lines include families with different memory densities, packages and peripherals. These products are designed for ultra-low-power applications. Refer to the product datasheets for the complete list of available peripherals.
For ordering information, pin description, mechanical and electrical device characteristics, refer to the product datasheets. For information on the STM8 SWIM communication protocol and debug module refer to the user manual (UM0470). For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044). For information on programming, erasing and protection of the internal Flash memory refer to the STM8L Flash programming manual (PM0054).
This document covers:
Value line low-density STM8L05xx devices: STM8L050J3 and STM8L051F3 microcontrollers with 8-Kbyte Flash.
Value line medium-density STM8L05xx devices: STM8L052C6 microcontrollers with
32-Kbyte Flash.
Value line high-density STM8L05xx devices: STM8L052R8 microcontrollers with
64-Kbyte Flash.
Low-density STM8L15x devices: STM8L151C2/K2/G2/F2, STM8L151C3/K3/G3/F3 microcontrollers with 4-Kbyte or 8-Kbyte Flash.
Medium-density STM8L15xx devices: STM8L151C4/K4/G4, STM8L151C6/K6/G6,
STM8L152C4/K4 and STM8L152C6/K6 microcontrollers with 16-Kbyte or 32-Kbyte Flash.
Medium-density STM8AL313x/4x/6x and STM8AL3L4x/6x devices: STM8AL3168,
STM8AL3166, STM8AL3148,STM8AL3146, STM8AL3138, STM8AL3136, STM8AL3L68,
STM8AL3L66, STM8AL3L48, STM8AL3L46 microcontrollers with 8-Kbyte, 16-KBbyte or
32-Kbyte Flash.
Medium+ density STM8L15xx devices: STM8L151R6 and STM8L152R6 microcontrollers with 32-Kbyte Flash (Wider range of peripherals than medium-density devices).
High-density STM8AL318x and STM8AL3L8x devices: STM8AL318AT, STM8AL3189,
STM8AL3188, STM8AL3L8A, STM8AL3L89, STM8AL3L88 microcontrollers with 64-Kbyte
Flash.
High-density STM8AL31E88 and STM8AL3LE88 devices: STM8AL31E88,
STM8AL3LE88 microcontrollers with 64-Kbyte Flash (same peripheral set as high-density
STM8AL318x and STM8AL3L8x plus the AES hardware accelerator).
High-density STM8L15xx devices: STM8L151C8/M8/R8 and the STM8L152C8/M8/R8 microcontrollers with 64-Kbyte Flash (Same peripheral set as medium+).
High-density STM8L16xx devices: STM8L162M8/R8 microcontrollers with 64-Kbyte
Flash (same peripheral set as high-density STM8L152 devices plus the AES hardware accelerator).
July 2019 RM0031 Rev 15
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Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 34
Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 35
Global configuration register map and reset values . . . . . . . . . . . . . . . 35
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . 37
Flash and EEPROM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flash and EEPROM glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Main Flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Low-density device memory organization . . . . . . . . . . . . . . . . . . . . . . . 39
Medium-density device memory organization . . . . . . . . . . . . . . . . . . . . 40
Medium+ density device memory organization . . . . . . . . . . . . . . . . . . . 41
High-density device memory organization . . . . . . . . . . . . . . . . . . . . . . . 42
Proprietary code area (PCODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Memory access security system (MASS) . . . . . . . . . . . . . . . . . . . . . . . 47
Enabling write access to option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Word programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Flash low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ICP (in-circuit programming) and IAP (in-application programming) . . . . 52
Flash control register 1 (FLASH_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 57
Flash control register 2 (FLASH_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash program memory unprotecting key register (FLASH_PUKR) . . . 58
Data EEPROM unprotection key register (FLASH_DUKR) . . . . . . . . . . 59
Flash status register (FLASH_IAPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Flash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Single wire interface module (SWIM) and debug module (DM) . . . . . 61
SWIM and DM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Register description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . . 65
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power control and status register 1 (PWR_CSR1) . . . . . . . . . . . . . . . . 70
PWR control and status register 2 (PWR_CSR2) . . . . . . . . . . . . . . . . . 71
PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Slowing down the system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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Peripheral clock gating (PCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Wait mode (WFI or WFE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Wait for interrupt (WFI) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Wait for event (WFE) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
WFE register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Entering Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Exiting Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Reset (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
“Reset state” and “under reset” definitions . . . . . . . . . . . . . . . . . . . . . . . . 84
External reset (NRST pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Asynchronous external reset description . . . . . . . . . . . . . . . . . . . . . . . . 84
Configuring NRST/PA1 pin as general purpose output . . . . . . . . . . . . . 85
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Independent watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Window watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Reset pin configuration register (RST_CR) . . . . . . . . . . . . . . . . . . . . . . 86
Reset status register (RST_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RST register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clock control (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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System clock switching procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Peripheral clock gating (PCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clock security system on HSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CSS on LSE control and status register (CSSLSE_CSR) . . . . . . . . . . . 98
CSS on LSE register map and reset values . . . . . . . . . . . . . . . . . . . . . 99
Configurable clock output capability (CCO) . . . . . . . . . . . . . . . . . . . . . . 100
Clock-independent system clock sources for TIM2/TIM3 . . . . . . . . . . . . 100
System clock divider register (CLK_CKDIVR) . . . . . . . . . . . . . . . . . . . 101
Clock RTC register (CLK_CRTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal clock register (CLK_ICKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Peripheral clock gating register 1 (CLK_PCKENR1) . . . . . . . . . . . . . . 105
Peripheral clock gating register 2 (CLK_PCKENR2) . . . . . . . . . . . . . . 106
Peripheral clock gating register 3 (CLK_PCKENR3) . . . . . . . . . . . . . . 107
Configurable clock output register (CLK_CCOR) . . . . . . . . . . . . . . . . 108
External clock register (CLK_ECKCR) . . . . . . . . . . . . . . . . . . . . . . . . 109
System clock status register (CLK_SCSR) . . . . . . . . . . . . . . . . . . . . . 110
9.14.10 System clock switch register (CLK_SWR) . . . . . . . . . . . . . . . . . . . . . . 111
9.14.11 Switch control register (CLK_SWCR) . . . . . . . . . . . . . . . . . . . . . . . . . 111
9.14.12 Clock security system register (CLK_CSSR) . . . . . . . . . . . . . . . . . . . . 112
9.14.13 Clock BEEP register (CLK_CBEEPR) . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.14.14 HSI calibration register (CLK_HSICALR) . . . . . . . . . . . . . . . . . . . . . . 113
9.14.15 HSI clock calibration trimming register (CLK_HSITRIMR) . . . . . . . . . . 114
9.14.16 HSI unlock register (CLK_HSIUNLCKR) . . . . . . . . . . . . . . . . . . . . . . . 114
9.14.17 Main regulator control status register (CLK_REGCSR) . . . . . . . . . . . . 115
9.14.18 CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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General purpose I/O ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Port configuration and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Alternate function input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Alternate function output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Port x output data register (Px_ODR) . . . . . . . . . . . . . . . . . . . . . . . . . 123
Port x pin input register (Px_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Port x data direction register (Px_DDR) . . . . . . . . . . . . . . . . . . . . . . . 124
Port x control register 1 (Px_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Port x control register 2 (Px_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Peripheral alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 125
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Routing interface (RI) and system configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RI and SYSCFG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
TIM1 input capture routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
TIM2 & TIM3 routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Comparator routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Internal reference voltage routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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Timer input capture routing register 1 (RI_ICR1) . . . . . . . . . . . . . . . . . 135
Timer input capture routing register 2 (RI_ICR2) . . . . . . . . . . . . . . . . . 136
I/O input register 1 (RI_IOIR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
I/O input register 2 (RI_IOIR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
I/O input register 3 (RI_IOIR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I/O control mode register 1 (RI_IOCMR1) . . . . . . . . . . . . . . . . . . . . . . 137
I/O control mode register 2 (RI_IOCMR2) . . . . . . . . . . . . . . . . . . . . . . 137
I/O control mode register 3 (RI_IOCMR3) . . . . . . . . . . . . . . . . . . . . . . 138
I/O switch register 1 (RI_IOSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
11.4.12 IO group control register (RI_IOGCR) . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.4.13 Analog switch register 1 (RI_ASCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.4.14 Analog switch register 2 (RI_ASCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.4.15 Resistor control register (RI_RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.4.22 I/O control mode register 4 (RI_IOCMR4) . . . . . . . . . . . . . . . . . . . . . . 150
SYSCFG remap control register 1 (SYSCFG_RMPCR1) . . . . . . . . . . 154
SYSCFG remap control register 2 (SYSCFG_RMPCR2) . . . . . . . . . . 155
SYSCFG remap control register 3 (SYSCFG_RMPCR3) . . . . . . . . . . 156
SYSCFG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . 157
Interrupt controller (ITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Interrupt masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Activation level/low power mode control . . . . . . . . . . . . . . . . . . . . . . . . 162
Concurrent and nested interrupt management . . . . . . . . . . . . . . . . . . . . 162
Concurrent interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . 163
Nested interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . . . . 163
CPU condition code register interrupt bits (CCR) . . . . . . . . . . . . . . . . 167
Software priority register x (ITC_SPRx) . . . . . . . . . . . . . . . . . . . . . . . . 168
External interrupt control register 1 (EXTI_CR1) . . . . . . . . . . . . . . . . . 168
External interrupt control register 2 (EXTI_CR2) . . . . . . . . . . . . . . . . . 170
External interrupt control register 3 (EXTI_CR3) . . . . . . . . . . . . . . . . . 171
External interrupt control register 4 (EXTI_CR4) . . . . . . . . . . . . . . . . . 172
External interrupt status register 1 (EXTI_SR1) . . . . . . . . . . . . . . . . . 172
External interrupt status register 2 (EXTI_SR2) . . . . . . . . . . . . . . . . . 173
External interrupt port select register (EXTI_CONF1) . . . . . . . . . . . . . 173
12.9.10 External interrupt port select register (EXTI_CONF2) . . . . . . . . . . . . . 175
12.9.11 ITC and EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . 176
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 178
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
DMA hardware request description . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
DMA low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
DMA global configuration & status register (DMA_GCSR) . . . . . . . . . 193
DMA global interrupt register 1 (DMA_GIR1) . . . . . . . . . . . . . . . . . . . 193
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DMA channel configuration register (DMA_CxCR) . . . . . . . . . . . . . . . 194
DMA channel status & priority register (DMA_CxSPR) . . . . . . . . . . . . 195
DMA number of data to transfer register (DMA_CxNDTR) . . . . . . . . . 196
DMA peripheral address high register (DMA_CxPARH) . . . . . . . . . . . 196
DMA peripheral address low register (DMA_CxPARL) . . . . . . . . . . . . 197
13.6.10 DMA memory 0 address high register (DMA_CxM0ARH) . . . . . . . . . . 199
13.6.11 DMA memory 0 address low register (DMA_CxM0ARL) . . . . . . . . . . . 199
13.6.12 DMA channel 3 memory 0 extended address register
(DMA_C3M0EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.6.13 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Number of analog channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Channel selection (Scan mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
14.3.14 Programmable sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
14.3.17 Internal reference voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . 212
ADC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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ADC configuration register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . 213
ADC configuration register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . 215
ADC configuration register 3 (ADC_CR3) . . . . . . . . . . . . . . . . . . . . . . 216
ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
ADC data register high (ADC_DRH) . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ADC data register low (ADC_DRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
ADC high threshold register high (ADC_HTRH) . . . . . . . . . . . . . . . . . 219
ADC high threshold register low (ADC_HTRL) . . . . . . . . . . . . . . . . . . 219
ADC low threshold register high (ADC_LTRH) . . . . . . . . . . . . . . . . . . 219
14.6.10 ADC low threshold register low (ADC_LTRL) . . . . . . . . . . . . . . . . . . . 220
14.6.11 ADC channel sequence 1 register (ADC_SQR1) . . . . . . . . . . . . . . . . 220
14.6.12 ADC channel sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . 221
14.6.13 ADC channel select scan 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . . . . . . 221
14.6.14 ADC channel select scan 4 (ADC_SQR4) . . . . . . . . . . . . . . . . . . . . . . 222
14.6.15 ADC trigger disable 1 (ADC_TRIGR1) . . . . . . . . . . . . . . . . . . . . . . . . 222
14.6.16 ADC trigger disable 2 (ADC_TRIGR2) . . . . . . . . . . . . . . . . . . . . . . . . 223
14.6.17 ADC trigger disable 3 (ADC_TRIGR3) . . . . . . . . . . . . . . . . . . . . . . . . 223
14.6.18 ADC trigger disable 4 (ADC_TRIGR4) . . . . . . . . . . . . . . . . . . . . . . . . 223
14.6.19 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DAC channel x enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DAC output switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DAC conversion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
DAC DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
DAC DMA underrun interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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DAC channel x control register 1 (DAC_CHxCR1) . . . . . . . . . . . . . . . 236
DAC channel x control register 2 (DAC_CHxCR2) . . . . . . . . . . . . . . . 237
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . 238
DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
DAC channel x right aligned data holding register high
(DAC_RDHRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DAC channel x right aligned data holding register low
(DAC_CHxRDHRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DAC channel x left aligned data holding register high
(DAC_CHxLDHRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DAC channel x left aligned data holding register low
(DAC_CHxLDHRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
DAC channel x 8-bit data holding register
(DAC_CHxDHR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
15.4.10 DAC channel x dual mode right aligned data holding register high
(DAC_DCHxRDHRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.4.11 DAC channel x dual mode right aligned data holding register low
(DAC_DCHxRDHRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
15.4.12 DAC channel x dual mode left aligned data holding register high
(DAC_DCHxLDHRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.4.13 DAC channel x left aligned data holding register low
(DAC_DCHxLDHRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
15.4.14 DAC channel x dual mode 8-bit data holding register
(DAC_DCHxDHR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.4.15 DAC channel x data output register high
(DAC_CHxDORH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.4.16 DAC channel x data output register low
(DAC_CHxDORL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
15.4.17 DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Comparator 1 (COMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Comparator 2 (COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Using the comparators in window mode . . . . . . . . . . . . . . . . . . . . . . . . 249
COMP low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
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Comparator control and status register 1 (COMP_CSR1) . . . . . . . . . . 251
Comparator control and status register 2 (COMP_CSR2) . . . . . . . . . . 253
Comparator control and status register 3 (COMP_CSR3) . . . . . . . . . . 254
Comparator control and status register 4 (COMP_CSR4) . . . . . . . . . . 255
Comparator control and status register 5 (COMP_CSR5) . . . . . . . . . . 255
COMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 256
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
LCD controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
LCD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Frequency generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Enabling a segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Multiplexing COM[7:4] and SEG[43:40], SEG[39:36], or SEG[31:28] . 272
Generation of LCD voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
LCD controller low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Control register 1 (LCD_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Control register 2 (LCD_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Control register 3 (LCD_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Frequency selection register (LCD_FRQ) . . . . . . . . . . . . . . . . . . . . . . 281
Port mask registers (LCD_PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Control register 4 (LCD_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
LCD display memory (LCD_RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
LCD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
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Glossary of timer signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Reading and writing to the 16-bit counter . . . . . . . . . . . . . . . . . . . . . . 295
Write sequence for 16-bit TIM1_ARR register . . . . . . . . . . . . . . . . . . . 295
Up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . 300
Repetition down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Prescaler clock (CK_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Internal clock source (fSYSCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Synchronization between timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
TIM1 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Write sequence for 16-bit TIM1_CCRi registers . . . . . . . . . . . . . . . . . 320
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Clearing the OCiREF signal on an external event . . . . . . . . . . . . . . . . 337
TIM1 wait-for-event capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
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DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . 347
External trigger register (TIM1_ETR) . . . . . . . . . . . . . . . . . . . . . . . . . . 348
DMA request enable register (TIM1_DER) . . . . . . . . . . . . . . . . . . . . . 350
Interrupt enable register (TIM1_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Status register 1 (TIM1_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Status register 2 (TIM1_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 354
19.8.10 Capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . . . . . . 355
19.8.11 Capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . . . . . . 359
19.8.12 Capture/compare mode register 3 (TIM1_CCMR3) . . . . . . . . . . . . . . . 360
19.8.13 Capture/compare mode register 4 (TIM1_CCMR4) . . . . . . . . . . . . . . . 361
19.8.14 Capture/compare enable register 1 (TIM1_CCER1) . . . . . . . . . . . . . . 362
19.8.15 Capture/compare enable register 2 (TIM1_CCER2) . . . . . . . . . . . . . . 365
19.8.16 Counter high (TIM1_CNTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
19.8.17 Counter low (TIM1_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
19.8.18 Prescaler high (TIM1_PSCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
19.8.19 Prescaler low (TIM1_PSCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
19.8.20 Auto-reload register high (TIM1_ARRH) . . . . . . . . . . . . . . . . . . . . . . . 367
19.8.21 Auto-reload register low (TIM1_ARRL) . . . . . . . . . . . . . . . . . . . . . . . . 367
19.8.22 Repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . . . . . 367
19.8.23 Capture/compare register 1 high (TIM1_CCR1H) . . . . . . . . . . . . . . . . 368
19.8.24 Capture/compare register 1 low (TIM1_CCR1L) . . . . . . . . . . . . . . . . . 368
19.8.25 Capture/compare register 2 high (TIM1_CCR2H) . . . . . . . . . . . . . . . . 369
19.8.26 Capture/compare register 2 low (TIM1_CCR2L) . . . . . . . . . . . . . . . . . 369
19.8.27 Capture/compare register 3 high (TIM1_CCR3H) . . . . . . . . . . . . . . . . 370
19.8.28 Capture/compare register 3 low (TIM1_CCR3L) . . . . . . . . . . . . . . . . . 370
19.8.29 Capture/compare register 4 high (TIM1_CCR4H) . . . . . . . . . . . . . . . . 371
19.8.30 Capture/compare register 4 low (TIM1_CCR4L) . . . . . . . . . . . . . . . . . 371
19.8.32 Deadtime register (TIM1_DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
19.8.33 Output idle state register (TIM1_OISR) . . . . . . . . . . . . . . . . . . . . . . . . 375
19.8.34 DMA control register 1 (TIM1_DCR1) . . . . . . . . . . . . . . . . . . . . . . . . . 376
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19.8.35 DMA control register 2 (TIM1_DCR2) . . . . . . . . . . . . . . . . . . . . . . . . . 376
19.8.36 DMA address for burst mode (TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . 377
19.8.37 TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 378
16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . 380
TIM2, TIM3 and TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . . . . . 389
External trigger register (TIMx_ETR) . . . . . . . . . . . . . . . . . . . . . . . . . . 390
DMA request enable register (TIMx_DER) . . . . . . . . . . . . . . . . . . . . . 391
Interrupt enable register (TIMx_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Status register 1 (TIMx_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Status register 2 (TIMx_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 395
20.5.10 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 396
20.5.11 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 399
20.5.12 Capture/compare enable register 1 (TIMx_CCER1) . . . . . . . . . . . . . . 400
20.5.13 Counter high (TIMx_CNTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
20.5.14 Counter low (TIMx_CNTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
20.5.15 Prescaler register (TIMx_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
20.5.16 Auto-reload register high (TIMx_ARRH) . . . . . . . . . . . . . . . . . . . . . . . 402
20.5.17 Auto-reload register low (TIMx_ARRL) . . . . . . . . . . . . . . . . . . . . . . . . 403
20.5.18 Capture/compare register 1 high (TIMx_CCR1H) . . . . . . . . . . . . . . . . 403
20.5.19 Capture/compare register 1 low (TIMx_CCR1L) . . . . . . . . . . . . . . . . . 404
20.5.20 Capture/compare register 2 high (TIMx_CCR2H) . . . . . . . . . . . . . . . . 404
20.5.21 Capture/compare register 2 low (TIMx_CCR2L) . . . . . . . . . . . . . . . . . 404
20.5.23 Output idle state register (TIMx_OISR) . . . . . . . . . . . . . . . . . . . . . . . . 407
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20.5.24 TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 407
8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Control register 1 (TIM4_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Control register 2 (TIM4_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Slave mode control register (TIM4_SMCR) . . . . . . . . . . . . . . . . . . . . . 412
DMA request enable register (TIM4_DER) . . . . . . . . . . . . . . . . . . . . . 414
Interrupt enable register (TIM4_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Status register 1 (TIM4_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Event generation register (TIM4_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 416
Counter (TIM4_CNTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Prescaler register (TIM4_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
21.5.10 Auto-reload register (TIM4_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
21.5.11 TIM4 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Infrared (IRTIM) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Control register (IR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
IRTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Beeper (BEEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
BEEP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
LSI clock frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
BEEP control/status register 1 (BEEP_CSR1) . . . . . . . . . . . . . . . . . . 422
BEEP control/status register 2 (BEEP_CSR2) . . . . . . . . . . . . . . . . . . 422
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BEEP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
RTC synchronization (low, medium+ and high-density devices only) . 432
24.3.10 Tamper detection (low, medium+ and high-density devices only) . . . . 435
RTC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Time register 1 (RTC_TR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Time register 2 (RTC_TR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Time register 3 (RTC_TR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Date register 1 (RTC_DR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Date register 2 (RTC_DR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Date register 3 (RTC_DR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Subsecond register high (RTC_SSRH) . . . . . . . . . . . . . . . . . . . . . . . . 440
Subsecond register low (RTC_SSRL) . . . . . . . . . . . . . . . . . . . . . . . . . 440
Control register 1 (RTC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
24.6.12 Initialization and status register 1 (RTC_ISR1) . . . . . . . . . . . . . . . . . . 444
24.6.13 Initialization and status register 2 (RTC_ISR2) . . . . . . . . . . . . . . . . . . 445
24.6.14 Synchronous prescaler register high (RTC_SPRERH) . . . . . . . . . . . . 446
24.6.15 Synchronous prescaler register low (RTC_SPRERL) . . . . . . . . . . . . . 447
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26
RM0031
24.6.16 Asynchronous prescaler register (RTC_APRER) . . . . . . . . . . . . . . . . 447
24.6.17 Wakeup timer register high (RTC_WUTRH) . . . . . . . . . . . . . . . . . . . . 448
24.6.18 Wakeup timer register low (RTC_WUTRL) . . . . . . . . . . . . . . . . . . . . . 448
24.6.19 Write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . . . . . 449
24.6.20 RTC shift control register high (RTC_SHIFTRH) . . . . . . . . . . . . . . . . . 449
24.6.21 RTC shift control register low (RTC_SHIFTRL) . . . . . . . . . . . . . . . . . . 450
24.6.22 Alarm A register 1 (RTC_ALRMAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 450
24.6.23 Alarm A register 2 (RTC_ALRMAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 451
24.6.24 Alarm A register 3 (RTC_ALRMAR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 451
24.6.25 Alarm A register 4 (RTC_ALRMAR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 452
24.6.26 Alarm A sub second register high (RTC_ALRMASSRH) . . . . . . . . . . . 452
24.6.27 Alarm A sub second register low (RTC_ALRMASSRL) . . . . . . . . . . . . 453
24.6.28 Alarm A subsecond masking register (RTC_ALRMASSMSKR) . . . . . 454
24.6.29 Calibration register high (RTC_CALRH) . . . . . . . . . . . . . . . . . . . . . . . 455
24.6.30 Calibration register low (RTC_CALRL) . . . . . . . . . . . . . . . . . . . . . . . . 456
24.6.31 Tamper control register 1 (RTC_TCR1) . . . . . . . . . . . . . . . . . . . . . . . . 456
24.6.32 Tamper control register 2 (RTC_TCR2) . . . . . . . . . . . . . . . . . . . . . . . . 458
24.6.33 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 467
WWDG low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
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Contents
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Window register (WWDG_WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Window watchdog register map and reset values . . . . . . . . . . . . . . . . . 469
AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Mode 2: Key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . 474
AES low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
27.10.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
27.10.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 480
27.10.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 480
27.10.5 AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 482
SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
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Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Frequency register (I2C_FREQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Own address register LSB (I2C_OAR1L) . . . . . . . . . . . . . . . . . . . . . . 508
Own address register MSB (I2C_OAR1H) . . . . . . . . . . . . . . . . . . . . . 508
Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
28.7.11 Interrupt and DMA register (I2C_ITR) . . . . . . . . . . . . . . . . . . . . . . . . . 515
28.7.12 Clock control register low (I2C_CCRL) . . . . . . . . . . . . . . . . . . . . . . . . 516
28.7.13 Clock control register high (I2C_CCRH) . . . . . . . . . . . . . . . . . . . . . . . 517
Universal synchronous/asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
High precision baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 534
Multi-processor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
USART synchronous communication . . . . . . . . . . . . . . . . . . . . . . . . . 537
Single wire half duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 540
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Contents
29.3.12 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 544
USART low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Baud rate register 1 (USART_BRR1) . . . . . . . . . . . . . . . . . . . . . . . . . 550
Baud rate register 2 (USART_BRR2) . . . . . . . . . . . . . . . . . . . . . . . . . 550
Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Control register 4 (USART_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Control register 5 (USART_CR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
29.6.10 Guard time register (USART_GTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
29.6.11 Prescaler register (USART_PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
29.6.12 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . 557
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
SPI general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Configuring the SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Configuring the SPI for simplex communications . . . . . . . . . . . . . . . . 564
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 564
SPI communication using DMA (direct memory addressing) . . . . . . . . 575
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SPI control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
SPI interrupt control register (SPI_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 582
SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
SPI CRC polynomial register (SPI_CRCPR) . . . . . . . . . . . . . . . . . . . . 584
SPI Rx CRC register (SPI_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 584
SPI Tx CRC register (SPI_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 585
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
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List of tables
List of tables
Memory access versus programming method(low-density devices) . . . . . . . . . . . . . . . . . 53
Memory access versus programming method (medium-density devices) . . . . . . . . . . . . . 54
Memory access versus programming method (medium+ and high-density devices) . . . . . 55
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List of tables RM0031
Sources of conversion trigger (medium, medium+ and high-density devices) . . . . . . . . . 229
Table 51.
Sources of conversion trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
DAC register map (medium, medium+ and high-density devices) . . . . . . . . . . . . . . . . . . 244
Output control for complementary OCi and OCiN channels with break
I2C_CCR values for SCL frequency table (fSYSCLK= 10 MHz or 16 MHz). . . . . . . . . . . 518
USART receiver’s tolerance when USART_DIV[3:0] is different from 0 . . . . . . . . . . . . . . 534
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25
List of figures
List of figures
RM0031
Low-density STM8L05xx/15xx Flash program and data EEPROM . . . . . . . . . . . . . . . . . . 39
Medium+ density STM8L05x/15x/16x Flash program and data EEPROM organization . . 41
High-density STM8L05xx/15xx/16xx Flash program and data EEPROMorganization . . . . 42
UBC area size definition for medium-density STM8L05xx/15xx devices . . . . . . . . . . . . . . 45
UBC area size definition for high-density STM8L05xx/15xx/16xx devices . . . . . . . . . . . . . 46
Routing interface (RI) block diagram (medium+ and high-density devices) . . . . . . . . . . . 127
Memory channel with MEM=0 (medium+ and high-density devices) . . . . . . . . . . . . . . . . 185
Memory channel with MEM=1 (medium+ and high-density devices) . . . . . . . . . . . . . . . . 186
DMA1 request mapping (medium+ and high-density devices) . . . . . . . . . . . . . . . . . . . . 189
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RM0031 List of figures
DAC channel block diagram (medium+ and high-density devices) . . . . . . . . . . . . . . . . . 227
Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 297
Counter update event when ARPE = 1 (TIM1_ARR preloaded). . . . . . . . . . . . . . . . . . . . 297
Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 . . . . . . . . . . . . 299
Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1 . . . . . . . . . . . . . . 299
CK_CNT
= f
CK_PSC
, TIM1_ARR = 06h, ARPE = 1 . . . . . . . . . . . 301
Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 303
Control circuit in normal mode, f
= f
SYSCLK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
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List of figures RM0031
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RM0031 List of figures
Figure 175. TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0).
Figure 176. TXE/RXNE/BSY behavior in slave / full duplex mode
Figure 177. TXE/BSY in master transmit-only mode
Figure 178. TXE/BSY in slave transmit-only mode (BDM = 0 and RXONLY = 0).
Figure 179. RXNE behavior in receive-only mode (BDM = 0 and RXONLY = 1).
Figure 180. TXE/BSY behavior when transmitting (BDM = 0 and RXLONY = 0).
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Central processing unit (CPU)
1 Central processing unit (CPU)
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The CPU has an 8-bit architecture. Six internal registers allow efficient data manipulations.
The CPU is able to execute 80 basic instructions. It features 20 addressing modes and can address six internal registers. For the complete description of the instruction set, refer to the
STM8 microcontroller family programming manual (PM0044).
1.2.1
The six CPU registers are shown in the programming model in Figure 1
. Following an interrupt, the registers are pushed onto the stack in the order shown in
popped from stack in the reverse order. The interrupt routine must therefore handle it, if needed, through the POP and PUSH instructions.
Description of CPU registers
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)
These are 16-bit registers used to create effective addresses. They may also be used as a temporary storage area for data manipulations and have an inherent use for some instructions (multiplication/division). In most cases, the cross assembler generates a
PRECODE instruction (PRE) to indicate that the following instruction refers to the Y register.
Program counter (PC)
The program counter is a 24-bit register used to store the address of the next instruction to be executed by the CPU. It is automatically refreshed after each processed instruction. As a result, the STM8 core can access up to 16 Mbytes of memory.
RM0031 Rev 15
RM0031 Central processing unit (CPU)
Figure 1. Programming model
Note:
Stack pointer (SP)
The stack pointer is a 16-bit register. It contains the address of the next free location of the stack. Depending on the product, the most significant bits can be forced to a preset value.
The stack is used to save the CPU context on subroutine calls or interrupts. The user can also directly use it through the POP and PUSH instructions.
The stack pointer can be initialized by the startup function provided with the C compiler. For applications written in C language, the initialization is then performed according to the address specified in the linker file for C users. If you use your own linker file or startup file, make sure the stack pointer is initialized properly (with the address given in the datasheets).
For applications written in assembler, you can use either the startup function provided by ST or write your own by initializing the stack pointer with the correct address.
The stack pointer is decremented after data has been pushed onto the stack and incremented after data is popped from the stack. It is up to the application to ensure that the lower limit is not exceeded.
A subroutine call occupies two or three locations. An interrupt occupies nine locations to
store all the internal registers (except SP). For more details refer to Figure 2
.
The WFI/HALT instructions save the context in advance. If an interrupt occurs while the
CPU is in one of these modes, the latency is reduced.
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Central processing unit (CPU)
Figure 2. Stacking order
RM0031
Condition code register (CC)
The condition code register is an 8-bit register which indicates the result of the instruction just executed as well as the state of the processor. The 6th bit (MSB) of this register is reserved. These bits can be individually tested by a program and specified action taken as a result of their state. The following paragraphs describe each bit:
• V: Overflow
When set, V indicates that an overflow occurred during the last signed arithmetic operation, on the MSB result bit. See the INC, INCW, DEC, DECW, NEG, NEGW, ADD, ADDW, ADC,
SUB, SUBW, SBC, CP, and CPW instructions.
• I1: Interrupt mask level 1
The I1 flag works in conjunction with the I0 flag to define the current interruptability level as
shown in Table 1 . These flags can be set and cleared by software through the RIM, SIM,
HALT, WFI, WFE, IRET, TRAP, and POP instructions and are automatically set by hardware when entering an interrupt service routine.
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RM0031 Central processing unit (CPU)
Interruptability
Interruptable main
Interruptable level 1
Interruptable level 2
Non interruptable
Table 1. Interrupt levels
Priority I1
Lowest
Highest
0
1
1
0
I0
0
1
0
1
• H: Half carry bit
The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines.
• I0: Interrupt mask level 0
See Flag I1.
• N: Negative
When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1).
• Z: Zero
When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
• C: Carry
When set, C indicates that a carry or borrow out of the ALU occurred during the last arithmetic operation on the MSB operation result bit. This bit is also affected during bit test, branch, shift, rotate and load instructions. See the ADD, ADC, SUB, and SBC instructions.
In a division operation, C indicates if trouble occurred during execution (quotient overflow or zero division). See the DIV instruction.
In bit test operations, C is the copy of the tested bit. See the BTJF and BTJT instructions.
In shift and rotate operations, the carry is updated. See the RRC, RLC, SRL, SLL, and SRA instructions.
This bit can be set, reset or complemented by software using the SCF, RCF, and CCF instructions.
Example: Addition
$B5 + $94 = "C" + $49 = $149
C
0
7 0
1 0 1 1 0 1 0 1
C
+ 0
C
= 1
7 0
1 0 0 1 0 1 0 0
7 0
0 1 0 0 1 0 0 1
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Central processing unit (CPU) RM0031
1.2.2
Address offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
STM8 CPU register map
The CPU registers are mapped in the STM8 address space as shown in Table 2 . These
registers can only be accessed by the debug module but not by memory access instructions executed in the core.
Register name 7
Table 2. CPU register map
6 5 4 3 2 1 0
A
PCE
PCH
PCL
XH
XL
YH
YL
SPH
SPL
CC
-
-
-
-
-
-
0
-
-
-
-
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
V
-
-
-
-
I1
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
-
-
-
-
-
-
-
-
-
N
-
-
-
-
-
-
-
-
-
-
I0
-
-
-
-
-
-
-
-
-
-
H
-
-
-
-
LSB
LSB
LSB
LSB
LSB
LSB
C
LSB
LSB
LSB
LSB
1.3 Global configuration register (CFG_GCR)
The MCU activation level is configured by programming the AL bit in the CFG_GCR register.
For information on the use of this bit refer to
Section 12.4: Activation level/low power mode control on page 162 .
By default, after an MCU reset, the SWIM pin is configured to allow communication with an external tool for debugging or Flash/EEPROM programming. This pin can be configured by the application for use as a general purpose I/O. This is done by setting the SWD bit in the
CFG_GCR register.
RM0031 Rev 15
RM0031 Central processing unit (CPU)
Address offset: 0x00
Reset value: 0x00
6 5 7
Reserved
4 3 2 1
AL rw
0
SWD rw
Bits 7:2 Reserved
Bit 1 AL : Activation level
This bit is set and cleared by software. It configures main or interrupt-only activation.
0: Main activation level. An IRET instruction causes the context to be retrieved from the stack and the main program continues after the WFI instruction.
1: Interrupt-only activation level. An IRET instruction causes the CPU to go back to WFI/Halt mode without restoring the context.
Bit 0 SWD : SWIM disable
0: SWIM mode enabled
1: SWIM mode disabled
When SWIM mode is enabled, the SWIM pin cannot be used as general purpose I/O.
1.3.4 Global configuration register map and reset values
The CFG_GCR is mapped in the STM8 address space. Refer to the corresponding datasheets for the base address.
Address offset
Register name
0x00
CFG_GCR
Reset value
-
0
7
Table 3. CFG_GCR register map
6 5 4 3
-
0
-
0
-
0
-
0
2
-
0
1
AL
0
0
SWD
0
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Boot ROM RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The internal 2 Kbyte boot ROM contains the bootloader code. Its main task is to download the application program to the internal Flash/EEPROM through the USART1, USART2,
USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces and program the code, data, option bytes and interrupt vectors in the internal Flash/EEPROM. Refer to product datasheets for details on available communication ports.
To perform bootlloading in LIN mode, a different bootloader communication protocol is implemented on UART2/UART3 and UART1.
The boot loader starts executing after reset. Refer to the STM8 bootloader user manual
(UM0560) for more details.
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Flash program memory and data EEPROM
Flash program memory and data EEPROM
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
3.1
3.2
Flash and EEPROM introduction
The embedded Flash program memory and data EEPROM memories are controlled by a common set of registers. Using these registers, the application can program or erase memory contents and set write protection. The application can also program the device option bytes.
Flash and EEPROM glossary
• Block
A block is a set of bytes that can be programmed or erased in one single programming operation. Operations that are performed at block level are faster than standard programming and erasing. Refer to
for the details on block size.
• Page
A page is a set of blocks.
Dedicated option bytes can be used to configure, by increments of one page, the size of the user boot code and proprietary code (when available).
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3.3 Main Flash memory features
RM0031
• Low-density STM8L05xx/15xx EEPROM is divided into three memory arrays (see
Section 3.4: Memory organization for details on the memory mapping):
– Up to 8 Kbytes of embedded Flash program
– 256 Bytes of data EEPROM
– Up to 64 option bytes (one block)
Flash program and data EEPROM areas are controlled by a common set of registers, allowing the memory content to be programmed or erased, and write protection to be activated.
No RWW is supported on those devices.
• Medium- and medium+ density STM8L05xx/15xx EEPROM is divided into three
memory arrays (see Section 3.4: Memory organization for details on the memory
mapping):
– Up to 32 Kbytes of embedded Flash program
– Up to 1 Kbyte of data EEPROM
– Up to 128 option bytes (one block)
Flash program and data EEPROM areas are controlled by a common set of registers, allowing the memory content to be programmed or erased, and write protection to be activated.
• High-density STM8L05xx/15xx/16xx EEPROM is divided into three memory arrays
(see Section 3.4: Memory organization
for details on the memory mapping):
– 64 Kbytes of embedded Flash program
– Up to 2 Kbyte of data EEPROM
– Up to 128 option bytes (one block)
Flash program and data EEPROM areas are controlled by a common set of registers, allowing the memory content to be programmed or erased, and write protection to be activated.
• Programming modes
– Byte programming and automatic fast byte programming (without erase operation)
– Word programming
– Block programming and fast block programming mode (without erase operation)
– Interrupt generation on end of program/erase operation and on illegal program operation.
• Read-while-write capability (RWW)
• In-application programming (IAP) and in-circuit programming (ICP) capabilities
• Protection features
– Memory readout protection (ROP)
– Program memory write protection with memory access security system (MASS keys)
– Data memory write protection with memory access security system (MASS keys)
– Programmable write protected user boot code area (UBC).
– Automatic readout protection of proprietary code area when available
• Memory state configurable to operating or power-down mode (I
DDQ power wait) and Run mode (Low power run)
) in wait mode (Low
RM0031 Rev 15
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3.4.1 Low-density device memory organization
Low-density STM8L05xx/15xx EEPROM is split into three memory arrays:
• Up to 8 Kbytes of Flash program memory divided into 128 pages of 64 bytes each. The memory array is organized in 32-bit words (4 bytes per word). It includes two areas:
– The user boot code area (UBC)
– The main program area
The first block (128 bytes) of the Flash program memory (starting from address 0x00 8000) contains the interrupt vectors.
• 256 bytes of data EEPROM organized in 4 pages of 64 bytes each.
• One block of option bytes (64 bytes) located in a separate memory array.
See the following figure for a description of the memory organization.
Figure 3. Low-density STM8L05xx/15xx Flash program and data EEPROM
1 page = 1 block = 128 bytes
0x00 1000
DATA EEPROM (DATA)
0x 00 10FF
0x00 4800
0x 00 487F
OPTION BYTES (128 bytes)
0x00 8000 Interrupt vectors (1 page)
Programmable size from 2 pages up to 64 pages
(1 page steps)
USER BOOT CODE (UBC)
(permanently write protected)
Up to 8 Kbytes of
FLASH PROGRAM
MEMORY
0x00 9FFF
MAIN PROGRAM
(write access possible for IAP
and using MASS mechanism)
MS19208V1
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3.4.2 Medium-density device memory organization
RM0031
Medium-density STM8L05xx/15xx EEPROM is split into three memory arrays:
• Up to 32 Kbytes of Flash program memory divided into 256 pages of 128 bytes each.
The memory array is organized in 32-bit words (4 bytes per word). It includes two areas:
– The user boot code area (UBC)
– The main program area
The first block (128 bytes) of the Flash program memory (starting from address
0x00 8000) contains the interrupt vectors.
• Up to 1 Kbyte of data EEPROM organized in 8 pages of 128 bytes each.
• One block of option bytes (128 bytes) located in a separate memory array.
See the following figure for a description of the memory organization.
Figure 4. Medium-density STM8L05xx/15xx Flash program and data EEPROM organization
1 page = 1 block = 128 bytes
0x00 1000
DATA EEPROM (DATA)
0x00 13FF
0x00 4800
0x00 487F
OPTION BYTES (128 bytes)
0x00 8000 Interrupt vectors (1 page)
Programmable size from 2 pages up to 255 pages
(1 page step)
USER BOOT CODE (UBC)
(permanently write protected)
Up to 32 Kbytes of
FLASH PROGRAM
MEMORY
0x00 FFFF
MAIN PROGRAM
(write access possible for IAP
and using MASS mechanism) ai17236b
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Medium+ density STM8L05xx/15xx EEPROM is split into three memory arrays:
• 32 Kbytes of Flash program memory divided into 128 pages of 256 bytes each. The memory array is organized in 32-bit words (4 bytes per word). It includes three areas:
– The user boot code area (UBC)
– The proprietary code area (PCODE)
– The main program area
The first block (128 bytes) of the Flash program memory (starting from address
0x00 8000) contains the interrupt vectors.
• Up to 1 Kbyte of data EEPROM organized in 4 pages of 256 bytes each.
• One block of option bytes (128 bytes) located in a separate memory array.
See
Figure 6 for a description of the memory organization.
Figure 5. Medium+ density STM8L05x/15x/16x Flash program and data EEPROM organization
1 block = 128 bytes
1 page = 2 blocks = 256 bytes
0x00 1000
DATA EEPROM (DATA)
0x00 13FF
0x00 4800
0x00 487F
OPTION BYTES (128 bytes)
Programmable size from 1 page up to 128 pages
(1 page step)
0x00 8000 Interrupt vectors (128 bytes)
PROPRIETARY CODE (PCODE)
(permanently readout protected)
Programmable size from 1 page up to 128 pages
(1 page step)
USER BOOT CODE (UBC)
(permanently write protected)
0x00 FFFF
MAIN PROGRAM
(write access possible for IAP
and using MASS mechanism)
32 Kbytes of
FLASH PROGRAM
MEMORY ai18261b
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High-density STM8L05xx/15xx/16xx EEPROM is split into three memory arrays:
• 64 Kbytes of Flash program memory divided into 256 pages of 256 bytes each. The memory array is organized in 32-bit words (4 bytes per word). It includes three areas:
– The user boot code area (UBC)
– The proprietary code area (PCODE)
– The main program area
The first block (128 bytes) of the Flash program memory (starting from address
0x00 8000) contains the interrupt vectors.
• Up to 2 Kbytes of data EEPROM organized in 8 pages of 256 bytes each.
• One block of option bytes (128 bytes) located in a separate memory array.
See
Figure 6 for a description of the memory organization.
Figure 6. High-density STM8L05xx/15xx/16xx Flash program and data
EEPROMorganization
1 block = 128 bytes
1 page = 2 blocks = 256 bytes
0x00 1000
DATA EEPROM (DATA)
Programmable size from 1 page up to 255 pages
(1 page step)
0x00 17FF
0x00 4800
0x00 487F
OPTION BYTES (128 bytes)
0x00 8000
Interrupt vectors (128 bytes)
PROPRIETARY CODE (PCODE)
(permanently readout protected)
Programmable size from 1 page up to 255 pages
(1 page step)
USER BOOT CODE (UBC)
(permanently write protected)
0x01 7FFF
MAIN PROGRAM
(write access possible for IAP
and using MASS mechanism)
64 Kbytes of
FLASH PROGRAM
MEMORY
AI15507b
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3.4.5
3.4.6
Note:
Flash program memory and data EEPROM
Proprietary code area (PCODE)
The proprietary code area (PCODE) can be used to protect proprietary software libraries used to drive peripherals. It is available only in low, medium + and high-density devices.
The size of the PCODE area can be configured through the PCODE option byte
(PCODESIZE) in ICP mode (using the SWIM interface). This option byte specifies the number of pages (256-byte granularity) allocated for the PCODE area starting from address
0x00 8000. Once programmed, the PCODE option byte cannot be erased, and the size of the PCODE area remains fixed.
The minimum meaningful size of the PCODE area is 1 page (256 bytes) of which 128 bytes are used to store the interrupt vectors.
While the PCODE is enabled the TRAP interrupt vector is write protected.
In medium+ density devices, the maximum size of the PCODE area is 128 pages ranging from address 0x00 8000 to 0x00 FFFF. In high-density devices, the maximum size of the
PCODE area is 255 pages ranging from address 0x00 8000 to 0x01 7EFF.
The PCODE area is automatically readout protected except for the TRAP interrupt vector
(see Section 3.5.1: Readout protection ,
Table 5: Memory access versus programming method(low-density devices) ,
Table 6: Memory access versus programming method
and Table 7: Memory access versus programming method
(medium+ and high-density devices)
). The readout protection cannot be disabled in this area. This means that the content of the PCODE area cannot be read or modified.
The PCODE area can be accessed only through the TRAP vector.
User boot area (UBC)
The user boot area (UBC) contains the reset and the interrupt vectors. It can be used to store the IAP and communication routines. The UBC area has a second level of protection to prevent unintentional erasing or modification during IAP programming. This means that it is always write protected and the write protection cannot be unlocked using the MASS keys.
The size of the UBC area can be obtained by reading the UBC option byte.
The size of the UBC area can be configured in ICP mode (using the SWIM interface) through the UBC option byte. The UBC option byte specifies the number of pages allocated for the UBC area starting from address 0x00 8000.
In medium-density STM8L05xx/15xx devices, the minimum meaningful size of the UBC area is of 2 pages of which 1 is used to store the interrupt vectors.
In low, medium+ and high-density devices, the minimum meaningful size of the UBC area is of 1 page of which 128 bytes are used to store the interrupt vectors.
When a PCODE area has been defined, the minimum size of the UBC should be
PCODESIZE+1. The portion of the UBC available to store the boot code is the area located between the end of the PCODE area and the end of the defined UBC area.
In high-density STM8L05xx/15xx/16xx devices, the maximum size of the boot area is 255 pages ranging from address 0x00 8000 to 0x01 7EFF (including the interrupt vectors).
In medium+ density STM8L05xx/15xx devices, the maximum size of the boot area is 128 pages ranging from address 0x00 8000 to 0x00 FFFF (including the interrupt vectors).
In medium-density STM8L05xx/15xx devices, the maximum size of the boot area is 255 pages ranging from address 0x00 8000 to 0x00 FF7F(including the interrupt vectors).
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,
and Figure 10 for a description of the UBC area
memory mapping and to the option byte section in the datasheets for more details on the
UBC option byte.
Figure 7. UBC area size definition for low-density STM8L05xx/15xx devices
0x00 8000
0x00 803F
0x00 807F
0x00 80BF
0x00 80FF
Interrupt vectors
Interrupt vectors
64 bytes
64 bytes
Page 0
Page 1
Page 2
Page 3
UBC[ 7:0]=0x01
(1 page)
UBC[ 7:0]=0x7F
(128 pages)
0x00 9EBF
0x00 9EFF
0x00 9F3F
0x00 9F7F
0x00 9FBF
0x00 9FFF
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
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Page 125
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Figure 8. UBC area size definition for medium-density STM8L05xx/15xx devices
0x00 8000
0x00 807F
0x00 80FF
0x00 817F
0x00 81FF
Interrupt vectors (1 page)
128 bytes
128 bytes
128 bytes
Page 0
Page 1
Page 2
Page 3
UBC[ 7:0]=0x01
(1 page)
UBC[ 7:0]=0xFF
(255 pages)
0x00 FD7F
0x00 FDFF
0x00 FE7F
0x00 FEFF
0x00 FF7F
0x00 FFFF
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
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1.
UBC[7:0]= 0x00 means no memory space is allocated for the UBC area.
Figure 9. UBC area size definition for medium + STM8L05xx/15xx devices
0x00 8000
Interrupt vectors (1 page)
0x00 807F
128 bytes
UBC[ 7:0]=0x01
(1 page)
0x00 80FF
Page 0
256 bytes Page 1
0x00 81FF
256 bytes Page 2
0x00 81FF
UBC[ 7:0]=0x80
(128 pages)
0x00 FAFF
0x00 FBFF
0x00 FCFF
0x00 FDFF
0x00 FEFF
0x00 FFFF
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
Page 123
Page 124
Page 125
Page 126
Page 127
1.
UBC[7:0]= 0x00 means no memory space is allocated for the UBC area.
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Flash program memory and data EEPROM RM0031
Figure 10. UBC area size definition for high-density STM8L05xx/15xx/16xx devices
0x00 8000
0x00 807F
0x00 80FF
0x00 81FF
0x00 81FF
Interrupt vectors (1 page)
128 bytes
256 bytes
256 bytes
Page 0
Page 1
Page 2
UBC[ 7:0]=0x01
(1 page)
UBC[ 7:0]=0xFF
(255 pages)
0x01 7AFF
0x01 7BFF
0x01 7CFF
0x01 7DFF
0x01 7EFF
0x01 7FFF
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
1.
UBC[7:0]= 0x00 means no memory space is allocated for the UBC area.
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3.4.8
The data EEPROM area can be used to store application data. By default, the DATA area is write protected to prevent unintentional modification when the main program is updated in
IAP mode. The write protection can be unlocked only by using a specific MASS key sequence (refer to
Enabling write access to the DATA area
).
The size of the DATA area is 256 bytes in low-density STM8L05xxx/STM8L15xxx, 1 Kbyte in medium and medium+ density STM8L15xxx devices and 2 Kbytes in high-density
STM8L15xxx/16xxx devices. It starts from address 0x00 1000 (see
Main program area
The main program is the area which starts at the end of the UBC or PCODE (when available) and ends at address 0x00 9FFF on low-density STM8L05xx/15xx devices,
0x00 FFFF on medium and medium+ density STM8L05xxx/15xxx devices and 0x01 7FFF on high-density STM8L05xxx/15xxx/16xxx devices. It is used to store the application code
,
The option bytes are used to configure device hardware features and memory protection.
They are located in a dedicated memory array of one block.
The option bytes can be modified both in ICP/SWIM and in IAP mode, except for ROP and
UBC and PCODESIZE (when available).
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Refer to the option byte section in the datasheet for more information on option bytes, and to the STM8 SWIM protocol and debug module user manual (UM0470) for details on how to program them.
Readout protection is removed by programming the ROP option byte to 0xAA. When readout protection is enabled, reading or modifying the Flash program memory and DATA area in ICP mode (using the SWIM interface) is forbidden, whatever the write protection settings.
Even if no protection can be considered as totally unbreakable, the readout feature provides a very high level of protection for a general purpose microcontroller.
The readout protection can be disabled on the program memory, UBC, PCODE (when available) and DATA areas, by reprogramming the ROP option byte in ICP mode. In this case, the Flash program memory, the DATA area and the option bytes are automatically erased and the device can be reprogrammed.
By default, the PCODE area is always readout protected except for the interrupt vector
TRAP (see Section 3.4.5: Proprietary code area (PCODE) ).
Refer to Table 6: Memory access versus programming method (medium-density devices)
for details on memory access when readout protection is enabled or disabled.
After reset, the main program and DATA areas are protected against unintentional write operations. They must be unlocked before attempting to modify their content. This unlock mechanism is managed by the memory access security system (MASS).
The UBC area specified in the UBC option byte is always write protected (see
Once the memory has been modified, it is recommended to enable the write protection again to protect the memory content against corruption.
Enabling write access to the main program memory
After a device reset, it is possible to disable the main program memory write protection by writing consecutively two values called MASS keys to the FLASH_PUKR register (see
Section 3.9.3: Flash program memory unprotecting key register (FLASH_PUKR) ). These
programmed keys are then compared to two hardware key values:
• First hardware key: 0b0101 0110 (0x56)
• Second hardware key: 0b1010 1110 (0xAE)
The following steps are required to disable write protection of the main program area:
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1.
Write a first 8-bit key into the FLASH_PUKR register. When this register is written for the first time after a reset, the data bus content is not latched into the register, but compared to the first hardware key value (0x56).
2. If the key available on the data bus is incorrect, the FLASH_PUKR register remains locked until the next reset. Any new write commands sent to this address are discarded.
3. If the first hardware key is correct when the FLASH_PUKR register is written for the second time, the data bus content is still not latched into the register, but compared to the second hardware key value (0xAE).
4. If the key available on the data bus is incorrect, the write protection on program memory remains locked until the next reset. Any new write commands sent to this address is discarded.
5. If the second hardware key is correct, the main program memory is write unprotected and the PUL bit of the FLASH_IAPSR is set (see
Section 3.9.5: Flash status register
) register.
Before starting programming, the application must verify that PUL bit is effectively set. The application can choose, at any time, to disable again write access to the Flash program memory by clearing the PUL bit.
Enabling write access to the DATA area
After a device reset, it is possible to disable the DATA area write protection by writing consecutively two values called MASS keys to the FLASH_DUKR register (see
Section 3.9.6: Flash register map and reset values
). These programmed keys are then compared to two hardware key values:
• First hardware key: 0b1010 1110 (0xAE)
• Second hardware key: 0b0101 0110 (0x56)
The following steps are required to disable write protection of the DATA area:
1.
Write a first 8-bit key into the FLASH_DUKR register. When this register is written for the first time after a reset, the data bus content is not latched into the register, but compared to the first hardware key value (0xAE).
2. If the key available on the data bus is incorrect, the application can re-enter two MASS keys to try unprotecting the DATA area.
3. If the first hardware key is correct, the FLASH_DUKR register is programmed with the second key. The data bus content is still not latched into the register, but compared to the second hardware key value (0x56).
4. If the key available on the data bus is incorrect, the data EEPROM area remains write protected until the next reset. Any new write command sent to this address is ignored.
5. If the second hardware key is correct, the DATA area is write unprotected and the DUL bit of the FLASH_IAPSR register is set (see
Section 3.9.5: Flash status register
).
Before starting programming, the application must verify that the DATA area is not write protected by checking that the DUL bit is effectively set. The application can choose, at any time, to disable again write access to the DATA area by clearing the DUL bit.
The write access to the option byte area can be enabled by setting the OPT bit in the
Flash control register 2 (FLASH_CR2)
.
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RM0031 Flash program memory and data EEPROM
Note:
The main program memory, and the DATA area must be unlocked before attempting to perform any program operation. The unlock mechanism depends on the memory area to be programmed as described in
Section 3.5.2: Memory access security system (MASS)
.
The PCODE area is always readout protected. The only way to reprogram it is to reset the
ROP option byte, thus erasing the Flash program memory, DATA area , and option bytes.
Note:
The RWW feature allows write operations to be performed on data EEPROM while reading and executing the program memory. Execution time is therefore optimized. The opposite operation is not allowed: Data memory cannot be read while writing to the program memory.
This RWW feature is always enabled and can be used at any time.
The RWW feature is not available on low-density devices. Refer to the datasheets for addition information.
The main program memory and the DATA area can be programmed at byte level. To program one byte, the application writes directly to the target address.
• In the main program memory:
The application stops for the duration of the byte program operation.
• In DATA area:
– Program execution stops during the “End of high voltage” operation, that is when the HVOFF flag is set, and the byte program operation is performed using the read-while-write (RWW) capability in IAP mode.
To erase a byte, simply write 0x00 at the corresponding address.
The application can read the FLASH_IAPSR register to verify that the programming or erasing operation has been correctly executed:
• EOP flag is set after a successful programming operation
• WR_PG_DIS is set when the software has tried to write to a protected page. In this case, the write procedure is not performed.
As soon as one of these flags are set, a Flash interrupt is generated if it has been previously enabled by setting the IE bit of the FLASH_CR1 register.
Automatic fast byte programming
The programming duration can vary according to the initial content of the target address. If the word (4 bytes) containing the byte to be programmed is not empty, the whole word is automatically erased before the program operation. On the contrary if the word is empty, no erase operation is performed and the programming time is shorter (see t
“Flash program memory” in the datasheet ).
PROG
in Table
However, the programming time can be fixed by setting the FIX bit of the FLASH_CR1 register to force the program operation to systematically erase the byte whatever its content
(see Section 3.9.1: Flash control register 1 (FLASH_CR1)
). The programming time is consequently fixed and equal to the sum of the erase and write time (see t
PROG
“Flash program memory” in the datasheet ).
in Table
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Note:
RM0031
To write a byte fast (no erase), the whole word (4 bytes) into which it is written must be erased beforehand. Consequently, It is not possible to do two fast writes to the same word
(without an erase before the second write): The first write will be fast but the second write to the other byte will require an erase.
A word write operation allows an entire 4-byte word to be programmed in one shot, thus minimizing the programming time.
As for byte programming, word operation is available both for the main program memory and data EEPROM. The read-while-write (RWW) capability is also available when a word programming operation is performed on the data EEPROM. Refer to the datasheets for additional information.
• In the main program memory:
The application stops for the duration of the byte program operation.
• In DATA area:
– Program execution does not stop, and the byte program operation is performed using the read-while-write (RWW) capability in IAP mode.
To program a word, the WPRG bit in the FLASH_CR2 register must be previously set to
enable word programming mode (see Section 3.9.2: Flash control register 2
(FLASH_CR2) ). Then, the 4 bytes of the word to be programmed must be loaded starting
with the first address. The programming cycle starts automatically when the 4 bytes have been written.
As for byte operation, the EOP and the WR_PG_DIS control flags of FLASH_IAPSR, together with the Flash interrupt, can be used to determine if the operation has been correctly completed.
Block program operations are much faster than byte or word program operations. In a block program operation, a whole block is programmed or erased in a single programming cycle.
for details on the block size according to the devices.
Block operations can be performed both to the main program memory and DATA area:
• In the main program memory:
Block program operations to the main program memory have to be executed totally from RAM.
• In the DATA area
– DATA block operations can be executed from the main program memory.
However, the data loading phase (see below) has to be executed from RAM.
There are three possible block operations:
• Block programming, also called standard block programming: The block is automatically erased before being programmed.
• Fast block programming: No previous erase operation is performed.
• Block erase
During block programming, interrupts are masked by hardware.
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Standard block programming
A standard block program operation allows a whole block to be written in one shot. The block is automatically erase before being programmed.
To program a whole block in standard mode, the PRG bit in the FLASH_CR2 register must be previously set to enable standard block programming (see
Section 3.9.2: Flash control register 2 (FLASH_CR2)
). Then, the block of data to be programmed must be loaded sequentially to the destination addresses in the main program memory or DATA area. This causes all the bytes of data to be latched. To start programming the whole block, all bytes of data must be written. All bytes written in a programming sequence must be in the same block. This means that they must have the same high address: Only the six least significant bits of the address can change. When the last byte of the target block is loaded, the programming starts automatically. It is preceded by an automatic erase operation of the whole block.
The EOP and the WR_PG_DIS control flags of the FLASH_IAPSR together with the Flash interrupt can be used to determine if the operation has been correctly completed.
Fast block programming
Fast block programming allows programming without first erasing the memory contents.
Fast block programming is therefore twice as fast as standard programming.
This mode is intended only for programming parts that have already been erased. It is very useful for programming blank parts with the complete application code, as the time saving is significant.
Fast block programming is performed by using the same sequence as standard block programming. To enable fast block programming mode, the FPRG bit of the FLASH_CR2 registers must be previously set.
The EOP and WR_PG_DIS bits of the FLASH_IAPSR register can be checked to determine if the fast block programming operation has been correctly completed.
Caution: The data programmed in the block are not guaranteed when the block is not blank before the fast block program operation.
Block erasing
A block erase allows a whole block to be erased.
To erase a whole block, the ERASE bit in the FLASH_CR2 register must be previously set to enable block erasing (see
Section 3.9.2: Flash control register 2 (FLASH_CR2) ). The block
is then erased by writing ‘0x00 00 00 00’ to any word inside the block. The word start address must end with ‘0’, ‘4’, ‘8’, or ‘C’.
The EOP and the WR_PG_DIS control flags of the FLASH_IAPSR together with the Flash interrupt can be used to determine if the operation has been correctly completed.
Table 4. Block size
STM8 microcontroller family
Low-density STM8L05xx/15xx
Medium-density STM8L05xx/15xx
Block size
64 bytes
128 bytes
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Flash program memory and data EEPROM
Table 4. Block size (continued)
STM8 microcontroller family
Medium+ density STM8L05xx/15xx
High-density STM8L05xx/15xx/16xx
Block size
128 bytes
128 bytes
RM0031
3.7
Option byte programming is very similar to data EEPROM byte programming.
The application writes directly to the target address. The program does not stop and the write operation is performed using the RWW capability.
Refer to the datasheet for details of the option byte contents.
Flash low-power modes
All STM8L05xx/15xx/16xx Flash program memory and data EEPROM have one low consumption mode, I
DDQ
. In I
DDQ
mode, the memory is switched off. It is used for any of the device low power modes: Halt, active-halt, low power wait, and low power run.
When the EEPM bit is set in FLASH_CR1 register, the Flash program memory and data
EEPROM automatically enter I
DDQ device is in Wait mode.
mode when the code is executed from RAM or when the
Refer to Section 3.9.1: Flash control register 1 (FLASH_CR1) for details on WAITM and
EEPM bits.
When the Flash program memory and data EEPROM exit from I
DDQ mode, the recovery time is lower than 2.8 µs and depends on supply voltage and temperature.
programming)
The in-circuit programming (ICP) method is used to update the entire content of the memory, using the SWIM interface to load the user application into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The SWIM interface (single wire interface module) uses the SWIM pin to connect to the programming tool.
In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (I/Os, I2C, SPI, USART...) to download the data to be programmed in the memory. IAP allows the Flash program memory content to be reprogrammed during application execution. Nevertheless, part of the application must have been previously programmed in the Flash program memory using ICP.
Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM protocol and debug manual (UM0470) for more information on programming procedures.
RM0031 Rev 15
RM0031 Flash program memory and data EEPROM
Table 5. Memory access versus programming method (1) (low-density devices)
Mode ROP
Readout protection enabled
Memory area
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
Main program
Data EEPROM area (DATA)
Access from core
R/W
(2)
/E
R/W
(3)
/E
R/E
R/W/E
(4)
R/W
(5)
User mode, IAP, and bootloader
Readout protection disabled
Option bytes
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
SWIM active
(ICP mode)
Readout protection enabled
TRAP
Proprietary code area (PCODE) when available
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
P
P
P/W
ROP
(8)
/E
Readout protection disabled
TRAP
Proprietary code area (PCODE) when available
Main program
Data EEPROM area (DATA)
Option bytes
R/W/E
R/W/E
1. R/W/E = Read, write, and execute
R/E = Read and execute (write operation forbidden)
R = Read (write and execute operations forbidden)
P = The area cannot be accessed (read, execute and write operations forbidden)
P/W
ROP
= Protected, write forbidden except for ROP option byte.
2. When no UBC area has been defined, the interrupt vectors, except for TRAP, can be modified in user/IAP mode.
3. If a PCODE area has been defined, the TRAP vector cannot be modified in user and IAP mode, otherwise TRAP follows the same rules as other interrupt vectors.
4. The Flash program memory is write protected (locked) until the correct MASS key is written in the FLASH_PUKR. It is possible to lock the memory again by resetting the PUL bit in the FLASH_IAPSR register. Unlocking can only be done once between two resets. If incorrect keys are provided, the device must be reset and new keys programmed.
5. The data memory is write protected (locked) until the correct MASS key is written in the FLASH_DUKR. It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
6. The PCODE area can be read and executed only in privileged mode through TRAP vectors. The PCODE cannot be directly accessed through the SWIM.
R
/E
/E
R/E (6)
R/W/E
R/W
(7)
P
P
P
RM0031 Rev 15
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Flash program memory and data EEPROM RM0031
7. The option bytes are write protected (locked) until the correct MASS key is written in the FLASH_DUKR (with OPT set to
1). It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
8. When ROP is removed, the whole memory is erased, including option bytes.
Table 6. Memory access versus programming method (1) (medium-density devices)
Mode ROP Memory area
Access from core
User mode, IAP, and bootloader
Readout protection enabled
Readout protection disabled
Interrupt vectors except for TRAP
TRAP
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
TRAP
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
TRAP
SWIM active
(ICP mode)
Readout protection enabled
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
P
P
P
P/W
ROP
(7)
/E
Readout protection disabled
TRAP
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
R/W/E
R/W/E
Option bytes
1. R/W/E = Read, write, and execute
R/E = Read and execute (write operation forbidden)
R = Read (write and execute operations forbidden)
P = The area cannot be accessed (read, execute and write operations forbidden)
P/W
ROP
= Protected, write forbidden except for ROP option byte.
2. When no UBC area has been defined, the interrupt vectors, except for TRAP, can be modified in user/IAP mode.
3. The Flash program memory is write protected (locked) until the correct MASS key is written in the FLASH_PUKR. It is possible to lock the memory again by resetting the PUL bit in the FLASH_IAPSR register. Unlocking can only be done once between two resets. If incorrect keys are provided, the device must be reset and new keys programmed.
R/W (2) /E
R/W/E
R/E
R/W/E
(3)
R/W
(4)
R
/E
R/W/E
R/E
(5)
R/W/E
R/W
(6)
P
P
RM0031 Rev 15
RM0031 Flash program memory and data EEPROM
4. The data memory is write protected (locked) until the correct MASS key is written in the FLASH_DUKR. It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
5. To program the UBC area the application must first clear the UBC option byte.
6. The option bytes are write protected (locked) until the correct MASS key is written in the FLASH_DUKR (with OPT set to
1). It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
7. When ROP is removed, the whole memory is erased, including option bytes.
Table 7. Memory access versus programming method (1) (medium+ and high-density devices)
Mode ROP Memory area
Access from core
User mode, IAP, and bootloader
SWIM active
(ICP mode)
Readout protection enabled
Readout protection disabled
Readout protection enabled
Readout protection disabled
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
Interrupt vectors except for TRAP
TRAP
Proprietary code area (PCODE) when available
User boot code area (UBC)
Main program
Data EEPROM area (DATA)
Option bytes
P
P
P
P
P
P/W
ROP
(9)
/E
R/W/E
R/W/E
R/W (2) /E
R/W
(3)
/E
R/E
R/W/E
(4)
R/W
(5)
R
/E
/E
R/E
(6)
R/E
(7)
R/W/E
R/W
(8)
P
RM0031 Rev 15
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Flash program memory and data EEPROM RM0031
1. R/W/E = Read, write, and execute
R/E = Read and execute (write operation forbidden)
R = Read (write and execute operations forbidden)
P = The area cannot be accessed (read, execute and write operations forbidden)
P/W
ROP
= Protected, write forbidden except for ROP option byte.
2. When no UBC area has been defined, the interrupt vectors, except for TRAP, can be modified in user/IAP mode.
3. If a PCODE area has been defined, the TRAP vector cannot be modified in user and IAP mode, otherwise TRAP follows the same rules as other interrupt vectors.
4. The Flash program memory is write protected (locked) until the correct MASS key is written in the FLASH_PUKR. It is possible to lock the memory again by resetting the PUL bit in the FLASH_IAPSR register. Unlocking can only be done once between two resets. If incorrect keys are provided, the device must be reset and new keys programmed.
5. The data memory is write protected (locked) until the correct MASS key is written in the FLASH_DUKR. It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
6. The PCODE area can be read and executed only in privileged mode through TRAP vectors. The PCODE cannot be directly accessed through the SWIM.
7. To program the UBC area the application must first clear the UBC option byte.
8. The option bytes are write protected (locked) until the correct MASS key is written in the FLASH_DUKR (with OPT set to
‘1’). It is possible to lock the memory again by resetting the DUL bit in the FLASH_IAPSR register. If incorrect keys are provided, another key program sequence can be performed without resetting the device.
9. When ROP is removed, the whole memory is erased, including option bytes.
RM0031 Rev 15
RM0031 Flash program memory and data EEPROM
3.9.1
7
Flash control register 1 (FLASH_CR1)
Address offset: 0x00
Reset value: 0x00
6
Reserved
5 4 3
EEPM rw
2
WAITM rw
1
IE rw
0
FIX rw
Bits 7: Reserved
Bit 3 EEPM : Flash program and data EEPROM I
DDQ low power wait mode
mode selection during run, low power run and
0: EEPM is cleared by hardware just after a Flash program or data EEPROM memory access. Clearing this bit by software does not exit the memory from I
DDQ
mode.
1: When the code is executed from RAM, setting of the EEPM bit force program Flash and data EEPROM into IDDQ mode.
This bit must not be set when the code is executed from program Flash.
Flash program and data EEPROM remain in I
DDQ mode till the next Flash program or data
EEPROM memory access.
Refer to
Section 7.6: Low power run mode on page 81 .
Bit 2 WAITM : Flash program and data EEPROM I
DDQ mode during wait mode
This bit is set and cleared by software.
0: Flash program and data EEPROM not in I
DDQ
1: Flash program and data EEPROM in I
DDQ
mode when the device is in wait mode
mode when the device is in wait mode.
Bit 1 IE : Flash Interrupt enable
This bit is set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled. An interrupt is generated if the EOP or WR_PG_DIS flag in the
FLASH_IAPSR register is set.
Bit 0 FIX : Fixed Byte programming time
This bit is set and cleared by software.
0: Standard programming time of (1/2 t otherwise. prog
) if the memory is already erased and t prog
1: Programming time fixed at t prog
.
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Flash program memory and data EEPROM RM0031
3.9.2
7
OPT rw
Flash control register 2 (FLASH_CR2)
Address offset: 0x01
Reset value: 0x00
6
WPRG rw
5
ERASE rw
4
FPRG rw
3 2
Reserved r
1 0
PRG rw
Bit 7 OPT : Write option bytes
This bit is set and cleared by software.
0: Write access to option bytes disabled
1: Write access to option bytes enabled
Bit 6 WPRG : Word programming
This bit is set by software and cleared by hardware when the operation is completed.
0: Word program operation disabled
1: Word program operation enabled
Bit 5 ERASE
(1)
: Block erasing
This bit is set by software and cleared by hardware when the operation is completed.
0: Block erase operation disabled
1: Block erase operation enabled
Bit 4
: Fast block programming
This bit is set by software and cleared by hardware when the operation is completed.
0: Fast block program operation disabled
1: Fast block program operation enabled
Bits 3:1 Reserved
Bit 0 PRG : Standard block programming
This bit is set by software and cleared by hardware when the operation is completed.
0: Standard block programming operation disabled
1: Standard block programming operation enabled (automatically first erasing)
1. The ERASE and FPRG bits are locked when the memory is busy.
3.9.3
7
Flash program memory unprotecting key register (FLASH_PUKR)
Address offset: 0x02
Reset value: 0x00
6 5 4 3
MASS_PRG KEYS rw
2 1 0
Bits 7:0 PUK [7:0] : Main program memory unlock keys
This byte is written by software (all modes). It returns 0x00 when read.
Refer to
Enabling write access to the main program memory on page 47
for the description of main program area write unprotection mechanism.
RM0031 Rev 15
RM0031 Flash program memory and data EEPROM
7
Address offset: 0x03
Reset value: 0x00
6 5 4 3
MASS_DATA KEYS rw
2 1 0
Bits 7:0 DUK[7:0] : Data EEPROM write unlock keys
This byte is written by software (all modes). It returns 0x00 when read.
Refer to
Enabling write access to the DATA area on page 48 for the description of main
program area write unprotection mechanism.
7
Reserved res.
Address offset: 0x04
Reset value: 0x40
6
HVOFF r
5
Reserved r
4 3
DUL rc_w0
2
EOP rc_r
1
PUL rc_w0
0
WR_PG_DIS rc_r
Bit 7 Reserved.
Bit 6 HVOFF : End of high voltage flag
This bit is set and cleared by hardware.
0: HV ON, start of actual programming
1: HV OFF, end of high voltage
Bits 5:4 Reserved, forced by hardware to 0.
Bit 3 DUL : Data EEPROM area unlocked flag
This bit is set by hardware and cleared by software by programming it to 0.
0: Data EEPROM area write protection enabled
1: Data EEPROM area write protection has been disabled by writing the correct MASS keys
RM0031 Rev 15
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Flash program memory and data EEPROM RM0031
Bit 2 EOP : End of programming (write or erase operation) flag
This bit is set by hardware. It is cleared by software by reading the register, or when a new write/erase operation starts.
0: No EOP event occurred
1: An EOP operation occurred. An interrupt is generated if the IE bit is set in the
FLASH_CR1 register.
Bit 1 PUL : Flash Program memory unlocked flag
This bit is set by hardware and cleared by software by programming it to 0.
0: Write protection of main Program area enabled
1: Write protection of main Program area has been disabled by writing the correct MASS keys.
Bit 0 WR_PG_DIS : Write attempted to protected page flag
This bit is set by hardware and cleared by software by reading the register.
0: No WR_PG_DIS event occurred
1: A write attempt to a write protected page occurred. An interrupt is generated if the IE bit is set in the FLASH_CR1 register.
3.9.6 Flash register map and reset values
For details on the Flash register boundary addresses, refer to the general hardware register map in the datasheets.
7
Table 8. Flash register map
6 5 4 3 2 1 0
Address offset
0x00
0x01
0x02
0x03
0x04
Register name
FLASH_CR1
Reset value
FLASH_CR2
Reset value
FLASH_PUKR
Reset value
FLASH_DUKR
Reset value
FLASH_IAPSR
Reset value
-
0
OPT
0
PUK7
0
DUK7
0
-
0
-
0
WPRG
0
PUK6
0
DUK6
0
HVOFF
1
-
0
ERASE
0
PUK5
0
DUK5
0
-
0
-
0
FPRG
0
PUK4
0
DUK4
0
-
0
EEPM
0
-
0
PUK3
0
DUK3
0
DUL
0
WAITM
0
-
0
PUK2
0
DUK2
0
EOP
0
IE
0
-
0
PUK1
0
DUK1
0
PUL
0
FIX
0
PRG
0
PUK0
0
DUK0
0
WR_PG_DIS
0
RM0031 Rev 15
RM0031
4
Single wire interface module (SWIM) and debug module (DM)
Single wire interface module (SWIM) and debug module (DM)
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
4.1 SWIM and DM introduction
In-circuit debugging mode or in-circuit programming mode are managed through a single wire hardware interface featuring ultrafast memory programming. Coupled with an in-circuit debugging module, it also offers a non-intrusive emulation mode, making the in-circuit debugger extremely powerful, close in performance to a full-featured emulator.
• Based on an asynchronous, high sink (8 mA), open-drain, bidirectional communication.
• Allows reading or writing any part of memory space.
• Access to CPU registers (A, X, Y, CC, SP). They are memory mapped for read or write access.
• Non intrusive read/write on the fly to the RAM and peripheral registers.
SWIM pin can be used as a standard I/O with some restrictions if you also want to use it for debug. The most secure way is to provide on the PCB a strap option.
Figure 11. SWIM pin connection
I/O for application
SWIM interface for tools
SWIM/PA0
MCU
Jumper selection for debug process
MSv17035V1
After a power-on reset, the SWIM is reset and enters OFF mode.
1.
OFF : Default state after power-on reset. The SWIM pin cannot be used by the application as an I/O.
2. I/O
. In this state, the SWIM pin can be used by the application as a standard I/O pin. In case of a reset, the SWIM goes back to OFF mode.
3. SWIM : This state is entered when a specific sequence is performed on the SWIM pin.
In this state, the SWIM pin is used by the host tool to control the STM8 with 3 commands (SRST system reset, ROTF read on the fly, WOTF write on the fly).
RM0031 Rev 15
62
Single wire interface module (SWIM) and debug module (DM)
Note:
RM0031
Refer to the STM8 SWIM communication Protocol and Debug Module User Manual for a description of the SWIM and Debug module (DM) registers.
There are two important considerations to highlight for the devices where the NRST pin is not present:
• If the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with
SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it will be locked forever (if the NRST pin is not available on the package). This initial delay can be removed in the final (locked) code.
• Their program memory must contain a valid program loop. If the device's memory is empty, the program continues into non-existing memory space and executes invalid opcode; this causes the device to reset (reading of non-existing memory is random content). This behavior might lead to periodic device resets and to a difficulty to connect to the device through the SWIM interface.
RM0031 Rev 15
RM0031
5 Memory and register map
Memory and register map
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
For details on the memory map, I/O port hardware register map and CPU/SWIM/debug module/interrupt controller registers, refer to the product datasheets.
5.1 Register description abbreviations
In the register descriptions of each chapter in this reference manual, the following abbreviations are used:
Abbreviation read/write (rw)
Table 9. List of abbreviations
Description
Software can read and write to these bits.
read-only (r) Software can only read these bits. write only (w) read/clear (rc_w1)
Software can only write to this bit. Reading the bit returns a meaningless value.
read/write once (rwo)
Software can only write once to this bit but can read it at any time. Only a reset can return this bit to its reset value.
Software can read and clear this bit by writing 1. Writing ‘0’ has no effect on the bit value.
read/clear (rc_w0)
Software can read and clear this bit by writing 0. Writing ‘1’ has no effect on the bit value.
read/set (rs) read/clear by read
(rc_r)
Software can read and set this bit. Writing ‘0’ has no effect on the bit value.
Software can read this bit. Reading this bit automatically clears it to ‘0’.
Writing ‘0’ has no effect on the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.
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63
Power control (PWR)
6 Power control (PWR)
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The device requires a 1.65 V to 3.6 V operating voltage supply (V
DD
) (1.8 V to 3.6 V for
STM8L05xx value line devices). An internal voltage regulator is used to supply V
CORE digital core, SRAM, Flash memory and data EEPROM.
to the
Figure 12. Power supply overview
Digital blocks
I/Os (V
DD
) V
DDIO
/
(V
SS
) V
SSIO
V
DD
/
V
SS
Analog blocks
Voltage regulator
- Main regulator mode (MVR)
- Ultra-low-power mode (ULP)
V
CORE
CPU
SRAM
Flash program memory
Data EEPROM
Digital peripherals
(V
DD
) V
DDA
/
(V
SS
) V
SSA
16 MHz RC oscillator (HSI)
38 kHz RC oscillator (LSI)
Power control (PWR)
Clock detector (CKD)
Comparators
DAC
12-bit ADC
Note:
(V
SSA
) V
REF-
(from 1.8 V to V
DDA
) V
REF+
In the above figure, the DAC is not available on low-density STM8L05xxx/STM8L15xxx devices.
RM0031 Rev 15
RM0031 Power control (PWR)
External power supply pins:
The external power supply pins must be connected as follows:
• V
SS
; V
DD
= 1.8 to 3.6 V, down to 1.65 V
at power-down: external power supply for
I/Os and for the internal regulator. Provided externally through V
DD corresponding ground pin is V
SS
.
pins, the
DDA
= 1.8 to 3.6 V, down to 1.65 V
at power-down: external power supplies • V
SSA;
V for analog peripherals (minimum voltage to be applied to V
DDA
must be connected to V
DD
and V
is 1.8 V when the ADC1 is used). V
DDA
and V
SSA
• V
SSIO
; V
DDIO
SS
, respectively.
= 1.8 to 3.6 V, down to 1.65 V
at power-down: external power supplies
for I/Os. V
DDIO
and V
SSIO
must be connected to V
DD
and V
SS
, respectively.
• V
REF+
; V
REF-
(for ADC1): external reference voltage for ADC1. Must be provided externally through V
REF+
and V
• V
REF+
: external voltage reference for DAC must be provided externally
through V
REF+
.
REF-
pin.
The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V typical.
During power-on, the device remains in Reset mode when V threshold, V
POR
DD
/V
DDA
is below a specified
, without the need for an external reset circuit. The POR feature is always enabled and the POR threshold is around 1.5 V. During power-down, the PDR keeps the device under reset when the supply voltage (V
DD
) drops below the V
PDR
threshold. The
PDR feature is always enabled and the PDR threshold is 1.5 V.
In low-density devices, medium-density devices and in the medium+ and high-density devices operating from 1.8V to 3.6V (device part numbers without "D" suffix), the BOR starts
to work above the POR threshold (see Section 6.3: Brownout reset (BOR) on page 66
). To ensure the minimum operating voltage (1.65 V), the BOR should be configured to BOR
Level 0.
When the BOR is disabled, a "grey zone" exists between the minimum operating voltage
(1.65 V) (a) and the V
POR
/V
PDR
threshold. This means that V
DD without device reset until the V
PDR
can be lower than 1.65 V
threshold is reached. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics of the datasheet. a. Not applicable on STM8L05xx value line devices. Refer to datasheets for more details.
RM0031 Rev 15
87
Power control (PWR)
Figure 13. Power on reset/power down reset waveform
V
DD
/V
DDA
POR
PDR
RM0031 t
Temporization
RSTTEMPO
Reset
6.3 Brownout reset (BOR)
For low-density devices, medium-density devices and for medium+ and high-density devices operating from 1.8 V to 3.6 V, the BOR is always active at power-on, keeping the
MCU under reset till the application operating threshold is reached.
At power-down, the BOR threshold is also used to generate a reset.
This BOR threshold (V
BOR
) can be configured using the option bytes. Five different levels can be selected, starting from 1.8 V to 3 V . If the BOR is disabled, the reset threshold is
V
PDR at power-down: this guarantees a V
DD min. value of 1.65 V
(a)
.
The power control unit (PWR) has an internal reference voltage which is used by the BOR or by other analog features.
To reduce the power consumption in Halt mode, it is possible to automatically switch off the internal voltage reference using the ULP bit in the PWR_CSR2 register. In this case, when the MCU wakes up from Halt mode there is an additional delay for the internal reference voltage startup. This delay can be configured using the FWU bit in the PWR_CSR2 register
).
Enabling the BOR guarantees that the MCU is safely used as it cannot run when V
DD below the operating range.
is
a. Not applicable on STM8L05xx value line devices. Refer to datasheets for more details.
RM0031 Rev 15
RM0031
V
DD/
V
DDIO
Power control (PWR)
Figure 14. V
DD
voltage detection: BOR threshold
V
BOR+
V
BOR-
1)
NRST
1. When BOR is disabled at power-down, this threshold is V
PDR
.
Note:
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold.
When V
DD the V
PVD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD/VDDA
rises higher than
threshold, the PVD output changes and a PVD event is generated. Every PVD event sets the interrupt flag (PVDIF) in the PWR_CSR1 register. The current state of the
PVD output can be monitored through the PVDOF flag status in the PWR_CSR1 register. If the PVDIEN bit in the PWR_CSR1 register is set, the PVD interrupt is enabled and is generated when the PVDIF flag is set. To prevent some spurious interrupts, as the PVDIF flag must be cleared by software, the user must make sure the PVDIF flag has been cleared before the PVD interrupt is enabled and before returning from the interrupt service. The
PVD is enabled by software by setting the PVDE bit in the PWR_CSR1 register.
This PVD has 7 different levels between 1.85 V and 3.05 V, selected by the PLS[2:0] bits in the PWR_CSR1 register, in steps of around 200 mV. Refer to the “Power-up / power-down operating conditions” section in the product datasheet.
The external reference voltage on the PVD_IN input pin can be selected by setting the
PLS[2:0] bits to 111.
The voltage injected on PVD_IN (PE6) is compared to the V
REFINT reference.
internal voltage
RM0031 Rev 15
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Power control (PWR) RM0031
Figure 15. PVD threshold
V DD / V DDA
PVD threshold
100 mV hysteresis
PVD event PVD event
6.5
PVD output
(PVDOF)
PVD interrupt
(PVDIF) ai17042c
Internal voltage reference (VREFINT)
The functions managed through the internal voltage reference (V
REFINT
) are BOR, PVD,
ADC, LCD internal VLCD booster and comparators. The internal voltage reference
(V
REFINT
) is always enabled. The internal voltage reference consumption is not negligible in
Halt and Active-halt mode. To reduce power consumption in these modes, the ULP bit (Ultra low power) in the PWR_CSR2 register can be set to disable the internal voltage reference during Halt and Active-halt modes. In this case, when exiting from these modes, the functions managed through the internal voltage reference are not reliable during the internal voltage reference startup time t
VREFINT
(up to 3 ms, refer to datasheet). To reduce the wakeup time, the device can exit from Halt/Active-halt mode without waiting for the internal voltage reference startup time. This is performed by setting the FWU bit (Fast wakeup) in the PWR_CSR2 register before entering halt/Active-halt mode. The V
REFINTF
flag in the
PWR_CSR register indicates that the internal voltage reference is ready. Consequently, the analog functions listed above can be used.
Table 10. Internal voltage reference status during Halt/Active-halt mode
(1)
ULP bit FWU bit Meaning
0
1
1 x
0
1
Internal reference voltage always on.
Internal reference voltage consumption (I
REFINT
) is added in
Halt/Active-halt mode.
(2)
Internal reference voltage stopped in
Halt/Active-halt mode
Internal reference voltage wakeup time t
VREFINT
is added to allow the internal
Fast wakeup time is forced without waiting the start of the internal reference voltage.
In this case, the analog features do not work immediately after wakeup.
RM0031 Rev 15
RM0031 Power control (PWR)
1. The FWU bit or the ULP bit must not be changed before the internal reference voltage is properly stabilized. The VREFINTF bit in the PWR_CSR2 register can be used to check the status of the internal reference voltage.
2. Refer to the product datasheet for the values of wakeup times.
The device has an internal voltage regulator for generating the 1.8 V power supply (V
CORE for the core and peripherals.
)
This regulator has two different modes:
• Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
• Ultra-low-power regulator mode (ULP) for Halt and Active-halt modes.
The regulator mode switches modes automatically, depending in some cases on some
register control bits. Refer to Table 13
.
Table 11. PWR interrupt requests
Interrupt event
PVD interrupt flag
Event flag
PVDIF
Enable control bit
PVDIEN
Exit from
Wait/Low power wait
Exit from
Halt/
Activehalt
No Yes
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Power control (PWR) RM0031
6.7.1
7
Reserved
Power control and status register 1 (PWR_CSR1)
Address offset: 0x00
Reset value after power-on Reset: 0x00
6
PVDOF r
5
PVDIF rc_w1
4
PVDIEN rw
3 rw
2
PLS[2:0] rw
1 rw
0
PVDE rc_w1
Bit 7 Reserved, must be kept cleared.
Bit 6 PVDOF : PVD output flag
This bit is set and cleared by hardware.
0: V
DD/
V
DDA
is above the V
PVD
threshold
1: V
DD/
V
DDA
is below the V
PVD
threshold
Bit 5 PVDIF : PVD interrupt flag
This bit is set by hardware and cleared by software writing “1”.
0: No PVD event occurred
1: PVD interrupt pending. This bit is set by hardware when a PVD event occurs.
Bit 4 PVDIEN : PVD interrupt enable
This bit is set and cleared by software.
0: PVD interrupt disabled
1: PVD interrupt enabled
Bits 3:1 PLS[2:0] : PVD level selection
These bits are set and cleared by software.
000: PVD threshold = 1.85 V typ.
001: PVD threshold = 2.05 V typ.
010: PVD threshold = 2.26 V typ.
011: PVD threshold = 2.45 V typ.
100: PVD threshold = 2.65 V typ.
101: PVD threshold = 2.85 V typ.
110: PVD Threshold = 3.05 V typ.
111: Threshold = PVD_IN input pin
For more details, refer to the “Power-up / power-down operating conditions” section in the product datasheet .
Bit 0 PVDE : Power voltage detector (PVD) enable
This bit is set by hardware and cleared by software writing “1”.
0: PVD off
1: PVD on
RM0031 Rev 15
RM0031 Power control (PWR)
6.7.2
7
PWR control and status register 2 (PWR_CSR2)
Address offset: 0x01
Reset value after power-on Reset: 0x00
6 5
Reserved r
4 3 2
FWU rw
1
ULP rw
0
VREFINTF r
Bits 7:3 Reserved, must be kept cleared.
Bit 2 FWU : Fast wake up configuration
Note: The FWU bit must not be changed before the internal reference voltage is properly stabilized.
The VREFINTF bit in the PWR_CSR2 register can be used to check the status of the internal reference voltage.
Bit 1 ULP : Ultra-low-power configuration
Note: The FWU bit must not be changed before the internal reference voltage is properly stabilized.
The VREFINTF bit in the PWR_CSR2 register can be used to check the status of the internal reference voltage.
Bit 0 VREFINTF : Internal reference voltage status flag
This bit is set and cleared by hardware
0: Internal reference voltage off or not yet stable
1: Internal reference voltage on
Table 12. PWR register map and reset values
Address offset
(1)
Register name 7 6 5 4 3 2 1
0x00
0x01
PWR_CSR1
Reset value
PWR_CSR2
Reset value
-
0
-
0
PVDOF
0
-
0
PVDIF
0
-
0
PVDIEN
0
-
0
PLS2
0
-
0
PLS1
0
FWU
0
PLS0
0
ULP
0
1. Please refer to the “general hardware register map” table in the datasheet for details on register addresses.
0
PVDE
0
VREFINTF
0
RM0031 Rev 15
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Low power modes
7 Low power modes
RM0031
Wait
By default, the microcontroller is in Run mode after a system or power reset. However the device supports five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
• Wait mode : The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt, event or Reset can be used to exit the microcontroller from Wait mode. Refer to
Section 7.3: Wait mode (WFI or WFE mode) on page 73
• Low power run mode : The CPU and the selected peripherals are running. Execution is done from RAM with a low speed oscillator (LSI or LSE). Flash and data EEPROM are stopped and the voltage regulator is configured in Ultra Low Power mode. The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.
• Low power wait mode: This mode is entered when executing a Wait for event in Low power run mode. It is similar to Low power run mode except that the CPU clock is stopped. The wakeup from this mode is triggered by a Reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, DMA controller, comparators and I/O ports). When the wakeup is triggered by an event, the system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this mode.
• Active-halt mode : The CPU and peripheral clocks are stopped, except the RTC. The wakeup can be triggered by RTC interrupts, external interrupts or reset.
• Halt mode : The CPU and peripheral clocks are stopped, the device remains powered on. The wakeup is triggered by an external interrupt or reset. A few peripherals also have wakeup from Halt capability. Switching off the internal reference voltage further reduces power consumption. Through software configuration (see
possible to have a fast wakeup time of 6 µs, without waiting for the internal reference voltage startup time.
Table 13. Low power mode summary
Peripheral Wakeup
Voltage regulator mode
WFI
WFE
On
On
Low power run mode
Software sequence
LSI or LSE clock
Low power wait mode
Software sequence
+WFE
LSI or LSE clock
Off
Off
On
Off
On
On
On
On
All internal or external interrupts, reset
All internal or external interrupts, wakeup events, reset
Software sequence, reset
Internal or external event, reset
MVR
MVR
ULP
ULP
RM0031 Rev 15
RM0031 Low power modes
Table 13. Low power mode summary (continued)
Peripheral Wakeup
Voltage regulator mode
Active-halt HALT
(1)
Off except
LSI or LSE clock
Off
Off except RTC and possibly LCD
External interrupts,
RTC interrupt, reset
MVR/ULP depending on CLK_ICKCR register
Halt HALT
Off Off Off
External interrupts, reset
ULP
1. Before executing the HALT instruction, the application must clear any pending peripheral interrupt by clearing the interrupt pending bit in the corresponding peripheral configuration register. Otherwise, the HALT instruction is not executed and program execution continues.
In addition, the power consumption in Run mode can be reduced by one of the following means:
• Slowing down the system clocks
• Gating the peripherals clocks when they are unused.
7.1
Note:
7.2
Slowing down the system clocks
In Run mode, choosing the clock frequency is very important to ensure the best compromise between performance and consumption. The selection is done by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering low power modes.
In applications where the MCU can be halted for certain periods, the power consumption can be minimized by keeping a fast clock (high performance execution) during active periods, in order to reduce the ratio between active periods and Halt (that is “zero”- consumption) periods.
Peripheral clock gating (PCG)
For additional power saving, you can use Peripheral Clock Gating (PCG). This can be done at any time by selectively enabling or disabling the SYSCLK clock connection to individual peripherals. These settings are effective in both Run and Wait modes.
Each PCG state represents a specific power or low power level. It is controlled by the
Peripheral clock enable registers (CLK_PCKENR1, CLK_PCKENR2 & CLK_PCKENR3).
7.3 Wait mode (WFI or WFE mode)
Wait mode is entered from Run mode by executing a WFI (Wait For Interrupt) or WFE (Wait
For Event) instruction: this stops the CPU but allows the other peripherals and interrupt controller to continue running. The consumption decreases accordingly. Wait mode can be combined with PCG to further reduce power consumption of the device.
In Wait mode, all the registers and RAM contents are preserved and the clock configuration selected through the Clock divider register (CLK_CKDIVR) remains unchanged.
RM0031 Rev 15
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Low power modes
7.4
Note:
Wait for interrupt (WFI) mode
RM0031
Wait for interrupt mode is entered from Run mode by executing a WFI (Wait For Interrupt) instruction.
When an internal or external interrupt request occurs, the CPU wakes up from WFI mode, serves the interrupt and resumes processing.
In an interrupt based application, where most of the processing is done through the interrupt routines, the main program may be suspended by setting the activation level bit (AL) in the
CFG_GCR register. Setting this bit causes the CPU to return to WFI mode without restoring the main execution context. This saves power by removing both the save/restore context activity and the need for a main software loop execution for power management (in order to return to WFI mode).
7.5 Wait for event (WFE) mode
Wait for event mode is entered from Run mode by executing a WFE instruction.
Interrupt requests during this mode are served normally, depending on the value of the I0 and I1 bits in the CPU_CC register.
Peripheral events can be generated by the timers, serial interfaces, DMA controller, comparators and I/O ports. These are enabled by the WFE_CRx registers.
When a peripheral event is enabled, the corresponding interrupts are not served and you have to clear the corresponding flag status.
There are two ways to wake up the CPU from WFE mode:
• Interrupts : when an interrupt occurs, the CPU wakes up from WFE mode and serves the interrupt. After processing the interrupt, the processor goes back to WFE mode.
• Wakeup events : when a wakeup event occurs, the CPU wakes up and resumes processing. As the processing resumes directly after the WFE instruction, there is no context save/restore activity (this saves time and power consumption).
Further power consumption reduction may be achieved using this mode together with execution from RAM. In some very low power applications, when the main software routine is short and has a low execution time, this routine can be moved to RAM and executed from
RAM. As the Flash program memory is not used at wakeup, the power consumption is then reduced during run time.
At any time, another routine (stored in the Flash program memory) can be executed by software by simply calling/jumping to this routine.
RM0031 Rev 15
RM0031 Low power modes
WFE control register 1 (WFE_CR1)
Address offset: 0x00
Reset value: 0x00
7
EXTI_EV3 rw
6
EXTI_EV2 rw
5
EXTI_EV1 rw
4
EXTI_EV0 rw
3
TIM1_EV1 rw
2
TIM1_EV0 rw
1
TIM2_EV1 rw
0
TIM2_EV0 rw
Bit 7 EXTI_EV3 : External interrupt event 3
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 3 of all ports
1: External interrupts from pin 3 of all ports configured to generate wakeup events
Bit 6 EXTI_EV2 : External interrupt event 2
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 2 of all ports
1: External interrupts from pin 2 of all ports configured to generate wakeup events
Bit 5 EXTI_EV1 : External interrupt event 1
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 1 of all ports
1: External interrupts from pin 1 of all ports configured to generate wakeup events
Bit 4 EXTI_EV0 : External interrupt event 0
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 0 of all ports
1: External interrupts from pin 0 of all ports configured to generate wakeup events
Bit 3 TIM1_EV1 : TIM1 interrupt event 1
This bit is written by software to configure the TIM1 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM1 capture and compare interrupts
1: TIM1 capture and compare interrupts logically ORed and configured to generate wakeup events
RM0031 Rev 15
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Low power modes RM0031
BIt 2 TIM1_EV0 : TIM1 interrupt event 0
This bit is written by software to configure the TIM1 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM1 update, trigger and break interrupts
1: TIM1 update, trigger and break interrupts logically ORed and configured to generate wakeup events
Bit 1 TIM2_EV1 : TIM2 interrupt event 1
This bit is written by software to configure the TIM2 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM2 capture and compare interrupts
1: TIM2 capture and compare interrupts logically ORed and configured to generate wakeup events
Bit 0 TIM2_EV0 : TIM2 interrupt event 0
This bit is written by software to configure the TIM2 interrupt sources used to wake up the CPU from
WFE mode
0: No wakeup event generated on TIM2 update, trigger and break interrupts
1: TIM2 update, trigger and break interrupts logically ORed and configured to generate wakeup events
WFE control register 2 (WFE_CR2)
Address offset: 0x01
Reset value: 0x00
7 6
ADC1_COMP_EV EXTI_EVE_F rw rw
5
EXTI_EVD_H rw
4
EXTI_EVB_G rw
3
EXTI_EV7 rw
2
EXTI_EV6 rw
1
EXTI_EV5 rw
0
EXTI_EV4 rw
Bit 7 ADC1_COMP_EV
This bit is written by software to select the interrupt sources from ADC1 and comparators used to wake up the CPU from WFE mode.
0: No wakeup event generated on interrupts from ADC1 and comparators
1: Interrupts from ADC1 and comparators are configured to generate wakeup events
Bit 6 EXTI_EVE_F : External interrupt event on Port E or Port F
This bit is written by software to select the external interrupt sources on Port E or Port F used to wake up the CPU from WFE mode.
0: No wakeup event generated on external interrupts from Port E or Port F
1: External interrupts from Port E or Port F configured to generate wakeup events
Bit 5 EXTI_EVD : External interrupt event on Port D or Port H
(1)
This bit is written by software to select the external interrupt sources on Port D or Port H
used to wake up the CPU from WFE mode.
0: No wakeup event generated on external interrupts from Port D or Port H (1)
1: External interrupts from Port D or Port H
(1) configured to generate wakeup events
Bit 4 EXTI_EVB : External interrupt event on Port B or Port G
(2)
This bit is written by software to select the external interrupt sources on Port B or Port G (2)
used to wake up the CPU from WFE mode.
0: No wakeup event generated on external interrupts from Port B or Port G
1: External interrupts from Port B or Port G
configured to generate wakeup events
RM0031 Rev 15
RM0031 Low power modes
Bit 3 EXTI_EV7 : External interrupt event 7
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 7 of all ports
1: External interrupts from pin 7 of all ports configured to generate wakeup events
Bit 2 EXTI_EV6 : External interrupt event 6
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 6 of all ports
1: External interrupts from pin 6 of all ports configured to generate wakeup events
Bit 1 EXTI_EV5 : External interrupt event 5
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 5 of all ports
1: External interrupts from pin 5 of all ports configured to generate wakeup events
Bit 0 EXTI_EV4 : External interrupt event 4
This bit is written by software to select the external interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on external interrupts from pin 4 of all ports
1: External interrupts from pin 4 of all ports configured to generate wakeup events
1. External interrupt on port D for medium-density devices and on port D or H for low, medium+ and high-density devices.
2. External interrupt on port B for medium-density devices and on port B or G for low, medium+ and high-density devices.
WFE control register 3 (WFE_CR3)
Address offset: 0x00
Reset value: 0x00
7 6
DMA1CH23_EV DMA1CH01_EV rw rw
5
USART1_EV rw
4
I2C1_EV rw
3
SPI1_EV rw
2
TIM4_EV rw
1
TIM3_EV1 rw
0
TIM3_EV0 rw
RM0031 Rev 15
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Low power modes RM0031
Bit 7 DMA1CH23_EV : DMA1 channel 2 and 3 interrupt event
This bit is written by software to select the DMA1 channel 2 and 3 interrupt sources used to wake up the CPU from WFE mode.
0: No wakeup event generated on DMA1 channel 2 and 3
1: DMA1 channel 2 and 3 interrupts configured to generate wakeup events
Bit 6 DMA1CH01_EV : DMA1 channel 0 and 1 interrupt event
This bit is written by software to select the DMA1 channel 0 and 1 interrupt sources used to wake up the CPU from WFE mode.
0: No wakeup event generated on DMA1 channel 0 and 1
1: DMA1 channel 0and 1interrupts configured to generate wakeup events
Bit 5 USART1_EV : USART1 Rx and Tx interrupt event
This bit is written by software to select the USART1 Rx and Tx interrupt sources used to wake up the
CPU from WFE mode
0: No wakeup event generated on USART1 Rx and Tx
1: USART1 Rx and Tx interrupts configured to generate wakeup events
Bit 4 I2C1_EV : I2C1 Rx and Tx interrupt event
This bit is written by software to select the I2C1 Rx and Tx interrupt sources used to wake up the CPU from WFE mode
0: No wakeup event generated on I2C1 Rx and Tx
1: I2C1 Rx and Tx interrupts configured to generate wakeup events
Bit 3 SPI1_EV : SPI1Rx and Tx interrupt event
This bit is written by software to select the SPI1Rx and Tx interrupt sources used to wake up the CPU from WFE mode
0: No wakeup event generated on SPI1Rx and Tx
1: SPI1Rx and Tx interrupts configured to generate wakeup events bit 2 TIM4_EV : TIM4 interrupt event
This bit is written by software to configure the TIM4 interrupt sources used to wake up the CPU from
WFE mode
0: No wakeup event generated on TIM4 update and trigger interrupts
1: TIM4 update and trigger interrupts logically ORed and configured to generate wakeup events
Bit 1 TIM3_EV1 : TIM3 interrupt event 1
This bit is written by software to configure the TIM3 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM3 capture and compare interrupts
1: TIM3 capture and compare interrupts logically ORed and configured to generate wakeup events
Bit 0 TIM3_EV0 : TIM3 interrupt event 0
This bit is written by software to configure the TIM3 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM3 update, trigger and break interrupts
1: TIM3 update, trigger and break interrupts logically ORed and configured to generate wakeup events
RM0031 Rev 15
RM0031 Low power modes
WFE control register 4 (WFE_CR4)
Address offset: 0x03
Reset value: 0x00
7
Reserved rw
6
AES_EV rw
5
TIM5_EV1 rw
4
TIM5_EV0 rw
3
USART3_EV rw
2 1
USART2_EV SPI2_EV rw rw
0
RTC_CSSLSE_EV rw
Bit 7 Reserved
Bit 6 AES_EV : AES interrupt event
This bit is written by software to configure the AES interrupt source used to wake up the CPU from
WFE mode.
0: No wakeup event generated from AES peripheral
1: AES interrupt configured to generate wakeup event
Bit 5 TIM5_EV1 : TIM5 interrupt event 1
This bit is written by software to configure the TIM5 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM5 capture and compare interrupts
1: TIM5 capture and compare interrupts logically ORed and configured to generate wakeup events
Bit 4 TIM5_EV0 : TIM5 interrupt event 0
This bit is written by software to configure the TIM5 interrupt sources used to wake up the CPU from
WFE mode.
0: No wakeup event generated on TIM5 update, trigger and break interrupts
1: TIM5 update, trigger and break interrupts logically ORed and configured to generate wakeup events
Bit 3 USART3_EV : USART3 Rx and Tx interrupt event
0: No wakeup event generated from USART3 Rx and Tx
1: USART3 Rx and Tx interrupts configured to generate wakeup events
Bit 2 USART2_EV : USART2 Rx and Tx interrupt event
This bit is written by software to select the USART2 Rx and Tx interrupt sources used to wake up the
CPU from WFE mode
0: No wakeup event generated from USART2 Rx and Tx
1: USART2 Rx and Tx interrupts configured to generate wakeup events
Bit 1 SPI2_EV: SPI2 Rx and Tx interrupt event
This bit is written by software to select the SPI2 Rx and Tx interrupt sources used to wake up the CPU from WFE mode.
0: No wakeup event generated from SPI2 Rx and Tx
1: SPI2 Rx and Tx interrupts configured to generate wakeup events
Bit 0 RTC_CSSLSE_EV : “RTC” or “CSS on LSE” interrupt event
This bit is written by software to select the interrupt source (“RTC” or “CSS on LSE”) used to wake up the CPU from WFE mode.
0: No wakeup event generated from RTC or CSS on LSE interrupt events
1: RTC or CSS on LSE interrupt events configured to generate wakeup events
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Low power modes RM0031
Table 14. WFE register map
Address offset
(1)
Register name
7 6 5 4 3 2 1 0
0x00
0x01
0x02
WFE_CR1
Reset value
WFE_CR3
Reset value
EXTI_EV3
0
WFE_CR2
Reset value
ADC1_COMP_EV
0
DMA1CH23_EV
0
EXTI_EV2
0
EXTI_EVE_F
0
DMA1CH01_EV
0
EXTI_EV1
0
EXTI_EVD
0
USART1_EV
0
EXTI_EV0
0
EXTI_EVB
0
I2C1_EV
0
TIM1_EV1
0
EXTI_EV7
0
SPI1_EV
0
TIM1_EV0
0
EXTI_EV6
0
TIM4_EV
0
TIM2_EV1
0
EXTI_EV5
0
TIM3_EV1
0
TIM2_EV0
0
EXTI_EV4
0
TIM3_EV0
0
0x03
(2)
WFE_CR4
Reset value
Reserved
AES_EV
0
TIM5_EV1
0
TIM5_EV0
0
USART3_EV
0
USART2_E
V
0
SPI2_EV
0
RTC_CSS
LSE_EV
0
1.
Please refer to the “general hardware register map” table in the datasheet for details on register addresses.
2.
Available on low, medium+ and high-density devices only. On low-density devices, only the RTC_CSSLSE_EV bit is available in this register.
RM0031 Rev 15
RM0031
7.6
Note:
7.6.1
Low power modes
Low power run mode
This mode is based on code fetch from RAM with the regulator in ultra-low-power mode
(ULP) and EEPROM in IDDQ.
While using this mode you have to switch from high speed clock sources to low speed clock sources.
The ADC cannot be used in Low Power Run mode and must be disabled.
Entering Low power run mode
This mode is entered by executing the following software sequence:
1.
Jump to RAM
2. Switch system clock to LSI or LSE clock sources
3. Switch off the high speed oscillators, the ADC and all unused peripherals
4. Mask all interrupts
5. Switch off the Flash/Data EEPROM by setting EEPM bit in FLASH_CR1 register
6. Add a software delay loop to ensure Flash/Data EEPROM off status
7. Configure the ultra-low-power mode for the regulator by setting the REGOFF bit in the
CLK_REGCSR register
7.7
The only way to exit this mode is to follow these steps:
1.
Switch on the main regulator by resetting the REGOFF bit in the CLK_REGCSR register. The REGREADY flag in the CLK_REGCSR register is set when the regulator is ready.
2. Switch on the Flash/Data EEPROM by resetting EEPM bit in FLASH_CR1 register. The
EEREADY flag in the CLK_REGCSR register is set when the Flash/Data EEPROM is ready.
4. Switch on what is necessary and jump to Flash/Data EEPROM if needed.
Low power wait mode
This mode is entered by executing a WFE instruction when the MCU is in Low power run mode. It can be exited only by means of an external or internal event. In this case the MCU returns to Low power run mode.
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Low power modes RM0031
7.8.1
Note:
7.8.2
In this mode the system clock is stopped. This means that the CPU and all the peripherals clocked by SYSCLK or by derived clocks are disabled, except for the following cases:
• The HSI clock is not stopped if used by SWIM
• The system clock source is not stopped if a Flash/Data EEPROM write operation is in progress
• The LSI clock is not stopped if used by the SWIM, the IWDG or if the “IWDG_HALT” option bit is disabled.
In Halt mode, none of the peripherals are clocked and the digital part of the MCU consumes almost no power.
Entering Halt mode
The MCU enters Halt mode when a HALT instruction is executed.
It is recommended not to enter Halt/Active-halt mode from the Low power run mode.
Otherwise, the only safe way to exit one of these two modes is to reset the MCU.
Before executing a HALT instruction, the application must clear all pending peripheral interrupts by clearing the interrupt pending bit in the corresponding peripheral configuration register. Otherwise, the HALT instruction is not executed and program execution continues.
However, the Halt procedure can be delayed if one of the following flags is set:
• SWBSY flag in the CLK_SWCR register
• EEBUSY flag in the CLK_CLK_REGCSR register
• RTCSWBSY flag in the CLK_CRTCR register
• BEEPSWBSY flag in the CLK_CBEEPR register when BEEP in Active-halt mode enabled.
If SAHALT bit is set in the CLK_ICKCR register the main regulator (MVR) will be switched off without taking into account that some high-speed clock may be used by the system.
Exiting Halt mode
Wakeup from Halt mode is triggered by an external interrupt sourced by a general purpose
I/O port configured as interrupt input or by an alternate function pin capable of triggering a peripheral interrupt.
The system clock is restarted with a frequency depending on the FHW bit in the
CLK_ICKCR register. If the FHW bit is set, HSI/8 is the system clock, otherwise the system clock is the last selected clock source before entering Halt mode.
In an interrupt based application, where most of the processing is done through the interrupt routines, the main program may be suspended by setting the activation level bit (AL) in the
CPU configuration register. Setting this bit causes the CPU to return to Halt mode when executing the return from interrupt, without restoring the main execution context.
Power consumption is reduced as there is no save/restore context activity and no need for a main software loop execution for power management (in order to return to WFI mode).
After a wake up from Halt mode, the LCD clock switches from RTCCLK to SYSCLK. To have a stable clock signal without glitches, 2 RTCCLK cycles are needed for
RM0031 Rev 15
RM0031 Low power modes synchronization reasons. Consequently, read/write access to LCD registers is not possible during this period.
Note:
Active-halt mode is similar to Halt mode.
It is recommended not to enter Halt/Active-Halt mode from the Low power run mode.
Otherwise, the only safe way to exit one of these two modes is to reset the MCU.
In Active-halt mode, the main oscillator, the CPU and almost all peripherals are stopped.
Only oscillator or the LSE crystal is running to drive the SWIM, beeper, IWDG, RTC and
LCD if enabled.
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Reset (RST) RM0031
8.1
There are 6 reset sources:
• External reset through the NRST pin (this pin can also be configured as general purpose output)
• Power-on reset (POR)/ power-down reset (PDR)
• Independent watchdog reset (IWDG)
• Window watchdog reset (WWDG)
• Illegal opcode reset (ILLOP)
• SWIM reset
These sources act on the NRST pin. The reset service routine vector is fixed at address
0x8000 in the memory map.
VDD
Figure 16. Reset circuit
RPU
External reset
NRST
Filter
System reset
Pulse generator
(min 20 μs )
WWDG reset
IWDG reset
SWIM reset
Illegal opcode reset
BOR/PDR ai17040c
“Reset state” and “under reset” definitions
When a reset occurs, there is a reset phase from the external pin pull-down to the internal reset signal release. During this phase, the microcontroller sets some hardware configurations before going to the reset vector.
At the end of this phase, most of the registers are configured with their “reset state” values.
During the reset phase, i.e. “under reset”, some pin configurations may be different from their “reset state” configuration.
The NRST pin is both an input and an open-drain output with an integrated R up resistor.
PU
weak pull-
A low pulse of minimum 300 ns on the NRST pin is needed to generate an external reset.
The reset detection is asynchronous and therefore the MCU can enter reset even in Halt mode.
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RM0031 Reset (RST)
The NRST pin also acts as an open-drain output for resetting external devices.
Any reset pulse from an internal reset source holds the NRST output low for at least 20 µs.
The internal R
PU forced low.
weak pull-up ensures a high level on the NRST pin when the reset is not
To optimize the number of available pins, the NRST pin (external reset) can be configured as a general purpose push-pull output (PA1).
For security, this configuration can be performed once only after reset, by writing a specified
key (0xD0) to the Reset pin configuration register (RST_CR) .
When the PA1 pin is configured as a general purpose output, the MCU can be reset only by a power-on reset (POR) or other internal reset source.
Note:
For internal reset sources, the NRST pin is kept low during the delay phase generated by the pulse generator.
Each internal reset source is linked to a specific flag bit in the Reset status register
. These flags are set at reset state depending on the given reset source.
Consequently, they can be used to identify the last reset source. They are cleared by software by writing the logic value ‘1’.
All flags besides the POR flag are reset at POR.
During power-on, the POR keeps the device in reset mode until V
DD
reaches a specified threshold. The POR reset is then held for a specified time to ensure that V
DD
has reached the minimum operating voltage. See Electrical parameters section in the datasheet for more details.
Refer to the independent watchdog chapter for details.
A reset can be triggered by the application software using the Independent watchdog.
Refer to the window watchdog chapter for details.
An external device connected to the SWIM interface can request the SWIM block to generate an MCU reset.
A system of illegal opcode detection is implemented to enhance device robustness against unexpected behaviors. If the code to be executed does not correspond to any opcode or
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Reset (RST) RM0031 prebyte value, a reset is generated. This, combined with the Watchdog, allows recovery from an unexpected fault or interference.
Address offset: 0x00
Reset value: 0x00
6 5 7 4 3 rwo
RSTPIN_KEY rwo
2 rwo rwo rwo rwo
Bits 7:0 RSTPIN_KEY[7:0] : Reset pin configuration key
0x00: NRST/PA1 configured as reset pin (default reset value)
0xD0: NRST/PA1 configured as general purpose output
These bits are write once only. They can also be read at any time.
Note: Writing any value beside 0xD0 is equivalent to writing 0x00.
8.4.2
7
Reset status register (RST_SR)
Address offset: 0x01
Reset value after power-on Reset: 0x01
Reserved
6 5
BORF rc_w1
4
WWDGF rc_w1
3
SWIMF rc_w1
2
ILLOPF rc_w1
Bits 7:6 Reserved, must be kept cleared.
Bit 5 BORF : Brownout reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No BOR reset occurred
1: An BOR reset occurred
Bit 4 WWDGF : Window Watchdog reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No WWDG reset occurred
1: A WWDG reset occurred
Bit 3 SWIMF : SWIM reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No SWIM reset occurred
1: A SWIM reset occurred
1 rwo
1
IWDGF rc_w1
0 rwo
0
PORF rc_w1
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RM0031 Reset (RST)
Bit 2 ILLOPF : Illegal opcode reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No ILLOP reset occurred
1: An ILLOP reset occurred
Bit 1 IWDGF : Independent Watchdog reset flag
This bit is set by hardware and cleared by software writing “1”.
0: No IWDG reset occurred
1: An IWDG reset occurred
Bit 0 PORF : Power-on Reset (POR) flag
This bit is set by hardware and cleared by software writing “1”.
0: No POR occurred
1: A POR occurred
8.4.3 RST register map and reset values
Table 15. RST register map and reset values
Address offset
(1)
Register name 7 6 5 4 3 2 1
0x00
0x01
RST_CR
Reset value
RST_SR
Reset value
RSTPIN
_KEY7
0
-
0
RSTPIN
_KEY6
0
-
0
RSTPIN
_KEY5
0
BORF
0
RSTPIN
_KEY4
0
WWDGF
0
RSTPIN
_KEY3
0
SWIMF
0
RSTPIN
_KEY2
0
ILLOPF
0
RSTPIN
_KEY1
0
IWDGF
0
1. Please refer to the “general hardware register map” table in the datasheet for details on register addresses.
0
RSTPIN
_KEY0
0
PORF
1
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Clock control (CLK)
9 Clock control (CLK)
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
9.1 Introduction
The clock controller is designed to be very robust and at the same time easy to use. Its purpose is to obtain the best performance in the application while at the same time get the full benefit of all the microcontroller power saving capabilities.
You can manage the clock distribution to the CPU and to the various peripherals, in order to optimize the power consumption.
A safe and glitch-free switch mechanism allows you to switch the system clock division factor on the fly, by means of clock prescaler.
Figure 17. Clock structure
CSS
OSC_OUT
OSC_IN
HSE OSC
1-16 MHz
HSI RC
16 MHz
HSE
HSI
LSI
LSE
S Y S C L K to core and memory
SYSCLK
Prescaler
/1;2;4;8;16;32;64;128
Peripheral
Clock enable (20 bits)
PCLK to peripherals
LSI RC
38kHz
LSE
LSI CLKBEEPSEL[1:0]
BEEPCLK to BEEP
IWDGCLK to IWDG
OSC32_OUT
OSC32_IN
CCO
RTCSEL[3:0]
RTC prescaler
/1;2;4;8;16;32;64
RTCCLK
RTCCLK to RTC
/ 2
LCD peripheral clock enable (1 bit)
RTCCLK/2 to LCD
LSE OSC
32.768 kHz
CSS_LSE Halt configurable clock output
CCO prescaler
/1;2;4;8;16;32;64
HSI
LSI
HSE
LSE
SYSCLK
LCDCLK to LCD
LCD peripheral clock enable (1 bit)
MSv43006V1
1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to
2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to
3. The Peripheral Clock Enable is 13 bits in low-density devices and 14 bits in medium-density devices and
20 bits in medium+ and high-density devices.
4. The CSS_LSE bit is available on low-density, medium+ and high-density devices only.
5. The CSS_LSE logic is connected to LSE OSC on low-density devices.
6. The CSS_LSE logic is connected to RTC prescaler output on medium+ and high-density devices.
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RM0031 Clock control (CLK)
Four different clock sources can be used to drive the system clock:
• 16 MHz high-speed internal (HSI) factory-trimmed RC clock
• 1 to 16 MHz high-speed external (HSE) oscillator clock
• 32.768 kHz low-speed external (LSE) oscillator clock
• 38 kHz low-speed internal (LSI) low-consumption clock
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
These four clocks can be used with a programmable prescaler (factor 1 to 128) to drive the system clock (SYSCLK). The SYSCLK is used to clock the core, memory and peripherals.
After reset, the device restarts by default with the HSI clock divided by 8. The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
All the peripheral clocks are derived from the system clock (SYSCLK) except:
• The BEEP clock which is derived from the LSE or LSI clocks. This selection is made by programming the CLKBEEPSEL[1:0] bits in the Clock BEEP register (CLK_CBEEPR).
• The RTC and the LCD clock which is derived from the LSE, LSI HSI or HSE (HSI and
HSE are divided by a programmable prescaler in CLK_CRTCR register). For more information about the RTC and LCD clock source configuration please refer to
Section 9.9: RTC and LCD clock
• The IWDG clock which is always the LSI clock.
Note:
The high-speed external clock signal (HSE) can be generated from two possible clock sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
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Clock control (CLK) RM0031
Figure 18. HSE clock sources
Hardware configuration
EXTERNAL
SOURCE
OSC_OUT
(I/O available)
OSC_IN OSC_OUT
C
L1
LOAD
CAPACITORS
C
L2
External crystal/ceramic resonator (HSE crystal)
The 1 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock with 50% duty cycle.
The associated hardware configuration is shown in
. Refer to the electrical characteristics section in the product datasheet for more details.
At start up the clock signal produced by the oscillator is not stable, and by default a delay of
1 oscillator cycle is inserted before the clock signal is released. You can program another stabilization time in the HSECNT option byte, please refer to option bytes section in the datasheet.
The HSERDY flag in the External clock register (CLK_ECKCR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
The HSE crystal can be switched on and off using the HSEON bit in the External clock register (CLK_ECKCR).
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency up to
16 MHz. The application can select this mode by setting the HSEBYP and HSEON bits in the External clock register CLK_ECKCR. The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin is available as standard I/O. See
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RM0031
Note:
Clock control (CLK)
Before selecting this mode, you have to make sure that the HSE clock source is not used by the RTC, output or involved in a switching operation.
Note:
The HSI clock signal is generated from an internal 16 MHz RC.
At startup the system clock source is automatically selected as HSI RC clock output divided by 8 (HSI/8).
The HSI RC oscillator has the advantage of providing a 16-MHz system clock source with
50% duty cycle at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.
Calibration
Each device is factory-calibrated. After reset, the factory calibration value is automatically loaded in the
HSI calibration register (CLK_HSICALR)
) and used for trimming the HSI oscillator. The read only content of the CLK_HSICALR register can be used as a reference for a calibration by the user.
If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the
HSI clock calibration trimming register (CLK_HSITRIMR)
. This register provides the internal HSI calibration register value.
Before writing to this register, you have to unlock the hardware write protection and then use the following procedure:
1.
Two consecutive write accesses to the HSI unlock register (CLK_HSIUNLCKR) , the
first one with the value 0xAC and the second one with the value 0x35.
2. Write the HSI trimming value to the HSI clock calibration trimming register
Any other attempt to read/write data from/to CLK registers breaks the unlocking process and the hardware protection is set again.
When this procedure is properly completed, register CLK_HSITRIMR is locked again and the written HSI trimming value is the calibration value used to trim the HSI oscillator.
Backup source
The HSI clock can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails. Refer to
Section 9.8: Clock security system (CSS) on page 96
.
Fast wakeup feature
If the FHWU bit in the Internal clock register (CLK_ICKCR)
is set, this automatically selects the HSI clock as system clock after the MCU wakeup from Halt or Active-halt mode.
Otherwise, the same clock source as that used before entering Halt or Active-halt mode is selected.
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Clock control (CLK) RM0031
Note:
Note:
The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the advantage of providing a low power and highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in the external clock register
(CLK_ECKCR). It is also automatically switched on when it is selected as RTC, CCO, Beep or system clock source. At startup, the LSE crystal output clock signal is transmitted to the
MCU after the LSERDY flag has been set by hardware in the external clock register
(CLK_ECKCR).
It is forbidden to enable CCO before the end of the LSE startup time t
SU(LSE)
.
It is also recommended to wait for this LSE startup time before enabling other features using the LSE, in order to have a stabilized frequency.
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. The application can select this mode by setting the LSEBYP and LSEON bits in the
External clock register (CLK_ECKCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin is available as standard I/O. See
Before selecting this mode, you have to make sure that the LSE clock source is not used by the RTC output or involved in a switching operation.
The LSI RC acts as a low power clock source that can be kept running in Active-halt and
Run modes for the independent watchdog (IWDG). The clock frequency is around 38 kHz.
For more details, refer to the electrical characteristics section in the product datasheet.
The LSI RC can be switched on and off using the LSION bit in the internal clock register
(CLK_ICKCR).
To detect a sequence of entry into SWIM mode, the LSI is automatically kept enabled in all modes except Halt and Active-halt modes. Consequently, the LSI can be switched off by clearing the LSION bit only if no peripheral is clocked by the LSI and after SWIM has been disabled by setting the SWD bit in the CFG_GCR register. The LSI is not kept ON by the
SWIM in Halt and Active-halt mode.
The LSIRDY flag in the Internal clock register (CLK_ICKCR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
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RM0031
9.6 System clock sources
Clock control (CLK)
9.6.2
For fast system startup, after a reset the clock controller configures the system clock source as HSI RC clock output divided by 8 (HSI/8). This is to take advantage of the short stabilization time of the HSI oscillator.
Once the system clock is released, the user program can switch the system clock to another clock source (LSI, HSE, or LSE) and/or modify the prescaler ratio.
System clock switching procedures
The clock switching feature provides an easy to use, fast and secure way for the application to switch from one system clock source to another.
To switch clock sources, you can proceed in one of two ways:
• Automatic switching
• Manual switching
Automatic switching
The automatic switching enables the user to launch a clock switch with a minimum number of instructions. The software can continue doing other operations without taking care of the switch event exact time.
Refer to the flowchart in Figure 19 .
Use the following procedure:
1.
Enable the switching mechanism by setting the SWEN bit in the Switch control register
.
2. Write the 8-bit value used to select the target clock source in the
System clock switch register (CLK_SWR)
. The SWBSY bit in the CLK_SWCR register is set by hardware, and the target source oscillator starts. The old clock source continues to drive the CPU and peripherals.
As soon as the target clock source is ready (stabilized), the content of the CLK_SWR register is copied to the
System clock status register (CLK_SCSR)
.
The SWBSY bit is cleared and the new clock source replaces the old one. If the SWIEN bit is set, the SWIF flag in the CLK_SWCR is set and an interrupt is generated.
Manual switching
The manual switching is not as immediate as the automatic switching but it offers to the user a precise control of the switch event time.
Refer to the flowchart in Figure 20 .
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Clock control (CLK)
Note:
RM0031
1.
Write the 8-bit value used to select the target clock source in the
System clock switch register (CLK_SWR)
. Then the SWBSY bit is set by hardware, and the target source oscillator starts. The old clock source continues to drive the CPU and peripherals.
2. The software has to wait until the target clock source is ready (stabilized). This is indicated by the SWIF flag in the CLK_SWCR register and by an interrupt if the SWIEN bit is set.
3. The final software action is to set, at the chosen time, the SWEN bit in the CLK_SWCR register to execute the switch.
In both manual and automatic switching modes, the old system clock source will not be powered off automatically in case it is required by other blocks (the LSI RC may be used to drive the independent watchdog for example). The clock source can be powered off using the bits in the Internal clock register (CLK_ICKCR) and the external clock register
(CLK_ECKCR).
If the clock switch does not work for any reason, software can reset the current switch operation by clearing the SWBSY flag. This will restore the CLK_SWR register to its previous content (old system clock).
After having reset a clock master switch procedure by clearing the SWBSY flag, the application must wait until a period of at least two clock cycles has elapsed before generating any new clock master switch request.
Figure 19. Clock switching flowchart (automatic mode example)
HARDWARE ACTION
Reset
SOFTWARE ACTION
MCU in Run mode with HSI/8
Set SWEN bit in CLK_SWCR
Set SWIEN bit in CLK_SWCR to enable interrupt if suitable
Write target clock source in CLK_SWR
Switch busy
SWBSY 1
Target clock source powered on
Target clock source ready after stabilization time
Update system clock status
CLK_SWR CLK_SCSR
Reset Switch busy flag
SWBSY 0
Poll
SWBSY 0
Interrupt if activated
Clear SWIF flag
MCU in Run mode with new system clock source
RM0031 Rev 15
RM0031 Clock control (CLK)
Figure 20. Clock switching flowchart (manual mode example without interrupt)
HARDWARE ACTION
Reset
SOFTWARE ACTION
MCU in Run mode with HSI/8
Write target clock source in CLK_SWR
Switch busy
SWBSY 1
Target clock source powered on
Poll the target clock
LSIRDY/LSERDY/HSERDY/HSIRDY
Set SWEN bit in CLK_SWCR to execute switch
Update system clock status
CLK_SWR CLK_SCSR
Reset Switch busy flag
SWBSY 0
MCU in Run mode with new system clock source
Figure 21. Clock switching flowchart (manual mode example with interrupt)
HARDWARE ACTION
Reset
SOFTWARE ACTION
MCU in Run mode with HSI/8
Set SWIEN bit in CLK_SWCR to enable interrupt if suitable
Write target clock source in CLK_SWR
Switch busy
SWBSY 1
Target clock source powered on
Target clock source ready after stabilization time
Interrupt
Clear SWIF flag
Set SWEN bit in CLK_SWCR to execute switch
Update system clock status
CLK_SWR CLK_SCSR
Reset Switch busy flag
SWBSY 0
MCU in Run mode with new system clock source
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Clock control (CLK)
9.7
Note:
Peripheral clock gating (PCG)
RM0031
Peripheral clock Gating (PCG) mode selectively enables or disables the system clock
(SYSCLK) connection to peripherals at any time in run or slow mode to optimize power consumption.
After a device reset, all peripheral clocks are disabled. The only bit which is enabled by default at reset state is PCKEN27 as it is used for the BootROM. Software has to be properly written to switch off the ROM clock after the Bootloader execution.
You can enable the clock to any peripheral by setting the corresponding PCKEN bit in the
CLK_PCKENRx peripheral clock gating registers.
• To enable a peripheral, first enable the corresponding PCKEN bit in the CLK_PCKENR registers and then set the peripheral enable bit in the peripheral control registers.
• To disable properly the peripheral, first disable the appropriate bit in the peripheral control registers and then stop the corresponding clock.
The beeper, RTC and LCD are fed by a specific clock different from SYSCLK, so that they continue to run even if the clock gating to the peripheral registers is asserted.
Note:
The clock security system (CSS) monitors HSE crystal clock source failures when HSE is used as the system clock. If the HSE clock fails due to a broken or disconnected resonator or any other reason, the clock controller activates a stall-safe recovery mechanism by automatically switching SYSCLK to the HSI with the same division factor as that used before the HSE clock failure. Once selected, the auxiliary clock source remains enabled until the microcontroller is reset. The application can enable the clock security system by setting the CSSEN bit in the
Clock security system register (CLK_CSSR)
. For safety reason, once CSS is enabled it cannot be disabled until the next device reset.
The following conditions must be met to detect HSE quartz crystal failures through the CSS:
• HSE on and stabilized (HSEON=1 and HSERDY=1 in the
• CSS function enabled (CSSEN=1 in the
Clock security system register (CLK_CSSR)
)
If HSE is the current system clock when a failure is detected, the CSS performs the following actions:
•
The HSI is switched on (if it was off) (HSION bit in Internal clock register (CLK_ICKCR)
register is set).
• The HSE is switched off (HSEON bit in the CLK_ECKCR register is reset)
• The AUX bit is set to indicate that the HSI is used as system clock source. The division factor of the system clock is not modified.
•
All CLK registers are write protected except the System clock divider register
(CLK_CKDIVR) . The application can still change the system clock prescaler.
• The CSSD bit is set in the CLK_CSSR register and an interrupt is generated if the
CSSDIE bit is set.
CSSD and AUX flags are cleared only by device reset.
RM0031 Rev 15
RM0031 Clock control (CLK)
If HSE is not the current system clock source when a failure is detected, the CSS performs the following actions:
• The HSE is switched off (HSEON bit in the CLK_ECKCR is reset)
• The CSSD bit is set in the CLK_CSSR register and an interrupt is generated if the
CSSDIE bit is set.
When the CSSDIE bit is set, if the HSE clock fails, the CSS interrupt is triggered and is executed indefinitely until the CSS interrupt enable bit is cleared. As a consequence, the application must clear the CSSDIE bit in CLK_CSSR register in the CLK interrupt service routine (ISR).
When the HSE is selected as system clock source, if the HSE fails before reaching the required stabilization time, it is not detected (CSSD equal to zero) and the system clock remains fed by the previous clock. In this case, the application must abort the clock
switching procedure by clearing the SWBSY bit in the Switch control register (CLK_SWCR) .
Note:
A second clock security system is implemented on low, medium+ and high-density devices to monitor LSE crystal clock source failures when LSE is used as RTC clock. The LSE failure detection is made through the LSI oscillator.
This feature is implemented externally to the RTC peripheral and has no impact on clock controller registers. To work properly, it requires an LSE clock frequency greater than LSI/4.
On medium+ and high-density devices, as the CSS_LSE is connected to RTC prescaler output, the CSS_LSE logic only works if RTC clock is > LSI/4. Also the CSS_LSE logic works only if the failure on LSE happens after RTC clock switching to LSE and enabling of
CSS_LSE feature.
Depending on the configuration of the SWITCHEN bit in the CSSLSE_CSR register, the
RTC clock can be automatically switched from LSE to LSI when a LSE failure is detected.
The application can enable the clock security system on LSE and switch to LSI by setting respectively the CSSEN bit and the SWITCHEN bit in the CSSLSE_CSR register.
For safety reason, once the CSS on LSE is enabled, it cannot be disabled until the next power-on reset.
The following conditions must be met to detect LSE quartz crystal failures through the CSS on LSE when LSE is used as RTC clock source:
• Enable the peripheral clock by setting the CSS_LSE bit in the CLK_PCKENR3 register
• Enable the LSI clock by setting the LSION bit in the CLK_ICKCR register
• Configure the LSE as RTC clock source through the CLK_CRTCR register.
If the CSS on LSE is enabled without configuring the LSE as RTC clock source, a false failure will be detected, due to the fact that the RTC clock is missing.
• Enable the CSS on LSE by setting the CSSEN bit in the CSSLSE_CSR register
RM0031 Rev 15
116
Clock control (CLK)
Note:
Note:
RM0031
Before enabling the CSS on LSE, the user must wait until the LSE startup time t
SU(LSE) elapsed
has
• If needed, enable the automatic clock switch from LSE to LSI on LSE failures by setting the SWITCHEN bit in the CSSLSE_CSR register.
• When an LSE failure is detected:
– The CSSF bit is set in the CSSLSE_CSR register and an interrupt is generated if the CSSIE bit is set.
– If the SWITCHEN bit is set : the RTC clock source is switched to LSI and the
SWITCHF bit is set in the CSSLSE_CSR register. The RTC clock source remains the LSI until the next power-on reset. The CLK_CRTCR register is not updated by the switch and cannot control the RTC clock until the next power-on.
Only the RTC peripheral is clocked by LSI instead of LSE when the SWITCHF bit is set.
– If the SWITCHEN bit is reset: the RTC clock source remains the LSE clock.
CSS on LSE low power modes
The following table describes the behavior of the CSS on LSE in low power modes.
Halt/ Active-halt
Table 16. CSS on LSE in low power modes
Mode Description
CSSF interrupts cause the device to exit from
Active-halt or Halt mode
9.8.3
7
CSS on LSE control and status register (CSSLSE_CSR)
Address offset: 0x00
Power-on reset value: 0x00
Reset value: 0xXX (the registers are not impacted by a system reset. They are reset at power-on).
5 6
Reserved r
4
SWITCHF r
3
CSSF rw
2
CSSIE rw
1
SWITCHEN rwo
0
CSSEN rwo
Bits 7:5 Reserved, must be kept cleared.
Bit 4 SWITCHF: RTC clock switch flag
This bit is set by hardware and can be cleared only by power-on reset.
0: No RTC clock switch occurred or no failure on LSE detected
1: RTC clock switch to LSI completed
Bit 3 CSSF : CSS on LSE flag
This bit is set by hardware and cleared by software by writing 0.
0: CSS on LSE is OFF or no LSE crystal clock disturbance is detected.
1: An LSE crystal clock disturbance is detected.
RM0031 Rev 15
RM0031 Clock control (CLK)
Bit 2 CSSIE : Clock security system on LSE interrupt enable
This bit is set and cleared by software.
0: Clock security system on LSE interrupt disabled
1: Clock security system on LSE interrupt enabled
Bit 1 SWITCHEN : RTC clock switch to LSI in case of LSE failure enable
This bit is set only by software and can be cleared only by power-on reset.
0: Clock switch to LSI in case of LSE failure OFF
1: Clock switch to LSI in case of LSE failure ON
Bit 0 CSSEN : Clock security system on LSE enable
This bit is set only by software and can be cleared only by power-on reset.
0: Clock security system on LSE OFF
1: Clock security system on LSE ON
9.8.4 CSS on LSE register map and reset values
Table 17. CSS on LSE register map
Address offset
(1)
Register name
7 6 5 4 3 2 1
0x00
CSSLSE_CSR
Power-on reset value
-
0
-
0
-
0
SWITCHF
0
CSSF
0
CSSIE
0
SWITCHEN
0
1. Please refer to the “general hardware register map” table in the datasheet for details on register addresses.
0
CSSEN
0
9.9 RTC and LCD clock
The RTC has two clock sources:
• RTCCLK used for RTC timer/counter
RTCCLK can be either the HSE, LSE, HSI or LSI clock. This selection is performed by programming the RTCSEL[3:0] bits in the Clock RTC register (CLK_CRTCR). These clocks can be optionally divided by a programmable divider (factor 1 to 64) by programming the RTCDIV[2:0] bits in the Clock RTC register (CLK_CRTCR). When the
HSE or HSI clock is selected as RTCCLK source, this clock must be divided to have a maximum of 1 MHz as input for the RTCCLK.
• SYSCLK used for RTC register read/write accesses
SYSCLK is gated by bit 2 of the Peripheral clock gating register 2 (CLK_PCKENR2).
The LCD has two clock sources:
• RTCCLK divided by 2 used to generate the LCD frame rate while it is sampled by the
LCDCLK signal input
This clock is gated by bit 3 in the Peripheral clock gating register 2 (CLK_PCKENR2).
As a consequence, even if the RTC is not used in the application, the RTCCLK must be configured to drive the LCD.
• LCDCLK used for LCD register read/write access and as an input frequency for the
LCD frame rate sampling
This clock is derived from SYSCLK by setting the bit 3 in the Peripheral clock gating register 2 (CLK_PCKENR2). In Active-halt mode the LCDCLK source is RTCCLK instead of SYSCLK.
RM0031 Rev 15
116
Clock control (CLK) RM0031
The BEEP clock sources can be either the LSE or LSI clocks. They can be selected by programming the CLKBEEPSEL[1:0] bits in the
Clock BEEP register (CLK_CBEEPR)
.
Note:
The configurable clock output (CCO) capability allows you to output a clock on the external
CCO pin. You can select one of 4 clock signals as CCO clock:
• f
HSE
• f
HSI
• f
LSE
• f
LSI
50% duty cycle is not guaranteed on all possible prescaled values
The selection is controlled by the CCOSEL[3:0] bits in the
Configurable clock output register
(CLK_CCOR) . The clock frequency can then be prescaled. The division factor depends on
the CCODIV[2:0] bits.
The sequence to really output the chosen clock starts with the selection of the desired clock and the division factor for the dedicated I/O pin (see “pin description” chapter). This I/O must be set at 1 in the corresponding Px_CR1 register to be set as input with pull-up or push-pull output. The PxCR2 register should be configured to match the maximum output speed of the desired clock.
The CCOSWBSY is set to indicate that the configurable clock output system is operating.
As long as the CCOBSWY bit is set, the CCOSEL and CCODIV bits are write protected.
The CCO automatically activates the target oscillator if needed.
To disable the clock output the user has to clear the CCOSEL bits. The CCOSWBSY flag remains at 1 till the shut down is completed. The time between the clear of CCOSEL bits and the reset of the flag can be relatively long, for instance in case the selected clock output is very slow compared to f
CPU
.
Note:
In some applications using the 32.768 kHz clock as a time base for the RTC, it may be interesting to have time bases that work completely independently from the system clock.
The user can then schedule tasks without having to take into account the system clock.
For this purpose, the LSE clock is internally redirected to the 2 timers' ETR inputs (TIM2 and
TIM3) which are used as additional clock sources. Refer to Section 11.5.2: SYSCFG remap control register 2 (SYSCFG_RMPCR2) on page 152 .
The ETR prescaler of the corresponding timer must be set to have a ratio of at least 4 with respect to the selected system clock.
The LSE clock must be properly switched on as defined in the CLK configuration registers.
RM0031 Rev 15
RM0031 Clock control (CLK)
The following interrupts can be generated by the clock controller:
• System clock source switch event
• Clock security system event
Both interrupts are individually maskable.
Interrupt event
CSS event
System clock switch event
Table 18. CLK interrupt requests
Event flag
Enable control bit
CSSD
SWIF
CSSDIE
SWIEN
Exit from
Wait/Low power wait
Yes
Yes
Exit from
Halt/
Active-halt
No
No
9.14.1 System clock divider register (CLK_CKDIVR)
7
-
Address offset: 0x00
Reset value: 0x03
6
-
5
Reserved
-
4
-
3
-
2 rw
Bits 7:3 Reserved, must be kept cleared.
Bits 2:0 CKM[2:0] : System clock prescaler
000: System clock source/1
001: System clock source /2
010: System clock source /4
011: System clock source /8
100: System clock source
101: System clock source
110: System clock source
111: System clock source
/16
/32
/64
/128
These bits are written by software to define the system clock prescaling factor.
1
CKM[2:0] rw
0 rw
9.14.2 Clock RTC register (CLK_CRTCR)
7
RTCDIV2 rw
Address offset: 0x01
Power-on reset value: 0x00
Reset value: not affected (the content of this register is not affected by system resets)
6
RTCDIV1 rw
5
RTCDIV0 rw
4
RTCSEL3 rw
3
RTCSEL2 rw
2
RTCSEL1 rw
1
RTCSEL0 rw
0
RTCSWBSY r
RM0031 Rev 15
116
Clock control (CLK)
Bits 7:5 RTCDIV[2:0] : Clock RTC prescaler
These bits are written by software to select the clock RTC division factor.
000: RTC clock source/1
001: RTC clock source /2
010: RTC clock source /4
011: RTC clock source /8
100: RTC clock source
101: RTC clock source
110: RTC clock source
111: RTC clock source
/16
/32
/64
/128
Note: Any write with a non valid target code will be skipped.
The content of these bits is frozen and write protected when RTCSWBSY is set.
Bits 4:1 RTCSEL[3:0] : Configurable RTC clock source selection
These bits are written by software to select the clock source to be used by the RTC.
0000: No clock selected
0001: HSI clock used as RTC clock source
0010: LSI clock used as RTC clock source
0100: HSE clock used as RTC clock source
1000: LSE clock used as RTC clock source
Note: Any write with a non valid target code will be skipped.
The content of these bits is frozen and write protected when RTCSWBSY is set.
Bit 0 RTCSWBSY : The system is busy during a RTC clock change
This bit is set by hardware any time a valid clock change for RTC is required.
It is reset when the RTC clock change procedure is complete.
RM0031
RM0031 Rev 15
RM0031 Clock control (CLK)
Address offset: 0x02
Reset value: 0x11
7
Reserved
-
6
BEEPAHALT rw
5
FHWU rw
4
SAHALT rw
3
LSIRDY r
2
LSION rw
1
HSIRDY r
0
HSION rw
Bit 7 Reserved, must be kept cleared.
Bit 6 BEEPAHALT: BEEP clock Halt/Active-halt mode
This bit is set and cleared by software.
0: BEEP clock is switched off during Halt mode or Active-halt mode
1: BEEP clock is kept running during Halt mode
Bit 5 FHWU : Fast wakeup from Halt/Active-halt modes
This bit is set and cleared by software.
0: Fast wakeup from Halt/Active-halt modes disabled: system clock is the last selected clock source before entering Halt/Active-halt mode
1: Fast wakeup from Halt/Active-halt modes enabled: HSI/8 used as system clock source after wakeup from Halt/Active-halt
Bit 4 SAHALT : Slow HALT/Active-halt mode
This bit is set and cleared by software. When it is set, the main voltage regulator is powered off as soon as the MCU enters Active-halt mode, so the wakeup time is longer.
0: MVR regulator ON in HALT/Active-halt mode
1: MVR regulator OFF in HALT/Active-halt mode
Bit 3 LSIRDY : Low speed internal oscillator ready
This bit is set and cleared by hardware.
0: LSI clock not ready
1: LSI clock ready
RM0031 Rev 15
116
Clock control (CLK) RM0031
Bit 2 LSION : Low speed internal RC oscillator enable
″
″
″
″
This bit is set and cleared by software. It is set by hardware whenever the LSI oscillator is required, for example:
″
″
″
When switching to the LSI clock (see CLK_SWR register)
When LSI is selected as the active CCO source (see CLK_CCOR register)
When LSI is selected as the active RTC clock source (see CLK_CRTCR register)
″
″
When LSI is selected as the active BEEP clock source (see CLK_CBEEPR register)
When LSI measurement is enabled (MSR bit set in the BEEP_CSR1 register)
It cannot be cleared when LSI is selected as system clock source (CLK_SCSR register) as active CCO source as clock source for the BEEP peripheral while BEEPAHALT bit is set or as active clock source for RTC.
0: Low speed internal RC OFF
1: Low speed internal RC ON
Bit 1 HSIRDY : High-speed internal oscillator ready
This bit is set and cleared by hardware.
0: HSI clock not ready
1: HSI clock ready
Bit 0 HSION : High-speed internal RC oscillator ON
This bit is set and cleared by software. It is set by hardware whenever the HSI oscillator is required, for example:
″
″
″
″
When activated as safe oscillator by the CSS
When switching to HSI clock (see CLK_SWR register)
When HSI is selected as the active CCO source, RTC clock
When exiting Halt/Active-halt in fast wake up mode
It cannot be cleared when HSI is selected as system clock (CLK_SCSR register), as active CCO source, as active RTC clock or if the safe oscillator (AUX) is enabled.
0: High-speed internal RC OFF
1: High-speed internal RC ON
RM0031 Rev 15
RM0031 Clock control (CLK)
9.14.4 Peripheral clock gating register 1 (CLK_PCKENR1)
Address offset: 0x3
Reset value: 0x00
7 rw
6 rw
5 rw
4 rw
PCKEN1[7:0]
3 rw
2 rw
1 0 rw rw
Bits 7:0 PCKEN1[7:0] : Peripheral clock enable
These bits are written by software to enable or disable the SYSCLK clock to the corresponding
0: SYSCLK to peripheral disabled
1: SYSCLK to peripheral enabled
Table 19. Peripheral clock gating bits (PCKEN 10 to PCKEN 17)
Control bit Peripheral
PCKEN17
PCKEN16
PCKEN15
PCKEN14
PCKEN13
PCKEN12
PCKEN11
PCKEN10
DAC
BEEP
USART1
SPI1
I2C1
TIM4
TIM3
TIM2
RM0031 Rev 15
116
Clock control (CLK) RM0031
9.14.5 Peripheral clock gating register 2 (CLK_PCKENR2)
Address offset: 0x04
Reset value: 0x80
7
PCKEN27 rw
6
Reserved
-
5 rw
4 rw
3 rw
2
PCKEN2[5:0] rw
1 0 rw rw
Bit 7 PCKEN27 : Peripheral clock enable
These bits are written by software to enable or disable the SYSCLK clock to the corresponding
0: SYSCLK to peripheral disabled
1: SYSCLK to peripheral enabled
Bit 6 Reserved
Bits 5:0 PCKEN2[5:0] : Peripheral clock enable
These bits are written by software to enable or disable the SYSCLK clock to the corresponding
0: SYSCLK to peripheral disabled
1: SYSCLK to peripheral enabled
Table 20. Peripheral clock gating bits ((PCKEN 20 to PCKEN 27)
Control bit Peripheral
PCKEN27
(1)
PCKEN25
PCKEN24
PCKEN23
PCKEN22
Boot ROM
COMP1 and COMP2
DMA1
LCD
RTC
PCKEN21
PCKEN20
TIM1
ADC1
1. The only bit which is enabled by default at reset state is PCKEN27 as it is used for the Boot ROM. Software has to be properly written to switch off the ROM clock after the Bootloader execution.
RM0031 Rev 15
RM0031 Clock control (CLK)
9.14.6 Peripheral clock gating register 3 (CLK_PCKENR3)
Address offset: 0x10
Reset value: 0x00
7
Reserved
-
6 5 rw
4 rw
3 2 rw
PCKEN3[5:0] rw
1 0 rw rw
Note: This peripheral is available in low-density, medium+ and high-density devices only. In lowdensity devices, only bit 5 is available.
Bits 7:0 PCKEN3[5:0] : Peripheral clock enable
These bits are written by software to enable or disable the SYSCLK clock to the corresponding
0: SYSCLK to peripheral disabled
1: SYSCLK to peripheral enabled
Table 21. Peripheral clock gating bits (PCKEN 30 to PCKEN 35)
Control bit Peripheral
PCKEN35
PCKEN34
PCKEN33
PCKEN32
PCKEN31
PCKEN30
CSS_LSE
USART3
USART2
SPI2
TIM5
AES
RM0031 Rev 15
116
Clock control (CLK) RM0031
Address offset: 0x05
Reset value: 0x00
7 rw
6
CCODIV[2:0] rw
5 rw
4 rw
3 2 rw
CCOSEL[3:0] rw
1 rw
0
CCOSWBSY r
Bits 7:5 CCODIV[2:0] : Configurable clock output prescaler
These bits are written by software to select the clock CCO division factor.
000: CCO
001: CCO divided by 2
010: CCO divided by 4
011: CCO divided by 8
100: CCO divided by 16
101: CCO divided by 32
110: CCO divided by 64
111: CCO divided by 64
Note: Any write with a non valid target code will be skipped.
The content of these bits is frozen and write protected when CCOSWBSY is set.
Bits 4:1 CCOSEL[3:0] : Configurable clock output selection.
These bits are written by software to select the source of the output clock available on the CCO pin.
0000: Clock output disabled, no clock output on CCO pin
0001: HSI clock output on CCO pin
0010: LSI clock output on CCO pin
0100: HSE clock output on CCO pin
1000: LSE clock output on CCO pin
Note: Any write with a non valid target code will be skipped.
The content of these bits is frozen and write protected when CCOSWBSY is set.
Bit 0 CCOSWBSY : Configurable clock output switch busy
This bit is set and cleared by hardware. It indicates that the selected CCO clock source is being switched-on and stabilized. While CCOSWBSY is set, the CCOSEL bits and CCODIV bits are writeprotected. CCOSWBSY remains set until the CCO clock is enabled.
0: CCO clock not busy
1: CCO clock busy
RM0031 Rev 15
RM0031 Clock control (CLK)
7
Address offset: 0x06
Reset value: 0x00
Reserved
-
6 5
LSEBYP rw
4
HSEBYP rw
3
LSERDY r
2
LSEON rw
1
HSERDY r
0
HSEON rw
Bits 7:6 Reserved, must be kept cleared.
Bit 5 LSEBYP : Low speed external clock bypass
Set and reset by software to bypass the oscillator. This bit can be written only when the external low speed oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 4 HSEBYP : High-speed external clock bypass
Set and reset by software in debug for bypassing the oscillator with the external clock. This bit can be written only if the external 1-16 MHz oscillator is disabled.
0: external 1-16 MHz oscillator not bypassed
1: external 1-16 MHz oscillator bypassed with external clock
Bit 3 LSERDY : Low speed external crystal oscillator ready
This bit is set and cleared by hardware.
0: LSE clock not ready
1: LSE clock ready (LSE clock is stabilized and available)
Note: the user must wait for the LSE startup time t
SU(LSE)
to get a stabilized frequency.
RM0031 Rev 15
116
Clock control (CLK) RM0031
Bit 2 LSEON : Low speed external crystal oscillator enable
″
″
″
″
This bit is set and cleared by software. It can be used to switch the external crystal oscillator on or off.
It is set by hardware in the following cases:
″
″
″
When switching to LSE clock (see CLK_SWR register)
When LSE is selected as the active CCO source (see CLK_CCOR register)
When LSE is selected as the active RTC source (see CLK_CRTCR register)
″ When LSE is selected as the active BEEP source (see CLK_CBEPR register)
It cannot be cleared when LSE is selected as system clock source (CLK_SCSR register), as active CCO source as clock source for the BEEP peripheral and BEEPAHALT bit is set or as active clock source for RTC.
0: LSE clock off
1: LSE clock on
Bit 1 HSERDY : High-speed external crystal oscillator ready
This bit is set and cleared by hardware.
0: HSE clock not ready
1: HSE clock ready (HSE clock is stabilized and available)
Bit 0 HSEON : High-speed external crystal oscillator enable
This bit is set and cleared by software. It can be used to switch the external crystal oscillator ON or
OFF. It is set by hardware in the following cases:
″
″
″
When switching to HSE clock (see CLK_SWR register)
When HSE is selected as the active CCO source (see CLK_CCOR register)
When HSE is selected as the active RTC source (see CLK_CRTCR register)
It cannot be cleared when HSE is selected as system clock (indicated in CLK_SCSR register) or as the active CCO source or as active RTC clock source.
0: HSE clock OFF
1: HSE clock ON
9.14.9 System clock status register (CLK_SCSR)
Address offset: 0x07
Reset value: 0x01
7 6 5 4 3
CKM[7:0] r r r r r
2 1 0 r r r
Bits 7:0 CKM[7:0] : System clock status bits
These bits are set and cleared by hardware. They indicate the currently selected system clock source.
0x01: HSI selected as system clock source (reset value)
0x02: LSI selected as system clock source
0x04: HSE selected as system clock source
0x08: LSE selected as system clock source
RM0031 Rev 15
RM0031 Clock control (CLK)
9.14.10 System clock switch register (CLK_SWR)
Address offset: 0x08
Reset value: 0x01
7 6 5 4 3
SWI[7:0] rw rw rw rw rw
2 1 0 rw rw rw
Bits 7:0 SWI[7:0] : System clock selection bits
These bits are written by software to select the system clock source. Their contents are write protected while a clock switch is ongoing (while the SWBSY bit is set). They are set to the reset value (HSI) if the
AUX bit is set in the CLK_CSSR register. If Fast halt wakeup mode is selected (FHW bit =1 in
CLK_ICKCR register) then these bits are set by hardware to 0x01 (HSI selected) when resuming from
Halt/Active-halt mode.
0x01: HSI selected as system clock source (reset value)
0x02: LSI selected as system clock source
0x04: HSE selected as system clock source
0x08: LSE selected as system clock source
7
Address offset: 0x09
Reset value: 0x00
6 5
Reserved
-
4 3
SWIF rc_w0
2
SWIEN rw
1
SWEN rw
0
SWBSY rw
Bits 7:4 Reserved, must be kept cleared.
Bit 3 SWIF : Clock switch interrupt flag
This bit is set by hardware when the SWIEN bit is set and cleared by software writing 0. Its meaning
depends on the status of the SWEN bit. Refer to Figure 19
.
″ In manual switching mode (SWEN=0)
0: Target clock source not ready
1: Target clock source ready
:
″ In automatic switching mode (SWEN=1) :
0: No clock switch event occurred
1: Clock switch event occurred
RM0031 Rev 15
116
Clock control (CLK) RM0031
Bit 2 SWIEN : Clock switch interrupt enable
This bit is set and cleared by software.
0: Clock switch interrupt disabled
1: Clock switch interrupt enabled
Bit 1 SWEN : Switch start/stop
This bit is set and cleared by software. Writing a 1 to this bit enables switching the system clock to the source defined in the CLK_SWR register.
0: Disable clock switch execution
1: Enable clock switch execution
Bit 0 SWBSY : Switch busy
This bit is set and cleared by hardware. It can be cleared by software to reset the clock switch process.
0: No clock switch ongoing
1: Clock switch ongoing
9.14.12 Clock security system register (CLK_CSSR)
Address offset: 0x0A
Reset value: 0x00
7 6
Reserved
-
5 4
CSSDGON rw
3
CSSD rc_w0
2
CSSDIE rw
1
AUX r
0
CSSEN rwo
Bits 7:5 Reserved, must be kept cleared.
Bit 4 CSSDGON: CSS deglitcher system
This bit, when set, avoids any clock glitch generated during the HSE switch-off executed by the CSS mechanism.
Bit 3 CSSD : Clock security system detection
This bit is set by hardware and only cleared by device reset.
0: CSS is OFF or no HSE crystal clock disturbance detected.
1: HSE crystal clock disturbance detected.
Bit 2 CSSDIE : Clock security system detection interrupt enable
This bit is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Bit 1 AUX : Auxiliary oscillator connected to system clock
This bit is set and cleared by hardware.
0: Auxiliary oscillator is OFF.
1: Auxiliary oscillator (HSI) is ON and selected as current system clock source.
Bit 0 CSSEN : Clock security system enable
This bit can be written once-only by software. It cannot be reset before the next device reset.
0: Clock security system OFF
1: Clock security system ON
RM0031 Rev 15
RM0031 Clock control (CLK)
9.14.13 Clock BEEP register (CLK_CBEEPR)
7
Address offset: 0x0B
Reset value: 0x00
6 5
Reserved
-
4 3 2 1 0
CLKBEEPSEL1 CLKBEEPSEL0 BEEPSWBSY rw rw r
Bits 7:3 Reserved
Bits 2:1 CLKBEEPSEL[1:0] : Configurable BEEP clock source selection.
These bits are set by software to select the clock source to be used by the BEEP.
00: No clock selected
01: LSI clock used as BEEP clock source
10: LSE clock used as BEEP clock source
Note: Any write with a non valid target code will be skipped.
The content of these bits is frozen and write protected when BEEPSWBSY is set.
Bit 0 BEEPSWBSY : System busy during BEEP clock change
This bit is set by hardware any time a valid clock change for BEEP is required.
It is reset when the BEEP clock change procedure is complete.
9.14.14 HSI calibration register (CLK_HSICALR)
7 r
Address offset: 0x0C
Reset value: 0xXX where X is undefined
6 5 4
HSICAL[7:0] r r r
3 r
2 1 r r
Bits 7:0 HSICAL[7:0]: HSI calibration
This register is initially loaded with the factory calibration value used to trim the HSI oscillator.
0 r
RM0031 Rev 15
116
Clock control (CLK) RM0031
Address offset: 0x0D
Reset value: 0x00
6 5 7 4 3 rw
HSITRIM[7:0] rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 HSITRIM[7:0] : HSI trimming value.
To ensure the best HSI clock accuracy, the value to be written to this register should be within the following range: [(HSICALR regiter value) -12] < x < [(HSICALR regiter value) + 8 ].
Note: Once this register configured, its value is used instead of the HSICALR register values.
These bits are used by the application to choose/change the HSI oscillator trimming value. A hardware protection can be provided to avoid erroneous write access to this register, refer to the CLK_HSIUNLCK register.
Address offset: 0x0E
Reset value: 0x00
6 5 7 4 3 rw
HSIUNLCK[7:0] rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 HSIUNLCK7:0] : HSI unlock mechanism
This register is used by the application for both unlocking the hardware write protection of HSITRIM register and enabling the use of HSITRIM as trimming value for HSI oscillator.
The HSITRIM unlock/enable procedure consists in:
1) two consecutive write accesses at this address, the first one with the value 0xAC and the second one with the value 0x35
2) a write access to the HSITRIM register.
Note: When this procedure is correctly completed the HSITRIM will be locked again
RM0031 Rev 15
RM0031 Clock control (CLK)
9.14.17 Main regulator control status register (CLK_REGCSR)
Address offset: 0x0F
Reset value: 0xB9
7
EEREADY r
6
EEBUSY r
5
LSEPD r
4
HSEPD r
3
LSIPD r
2
HSIPD r
1
REGOFF rw
0
REGREADY r
Bit 7 EEREADY : Flash program memory and Data EEPROM ready
This bit indicated if the Flash program memory and Data EEPROM are ready
0: Flash program memory and Data EEPROM not ready
1: Flash program memory and Data EEPROM ready
Bit 6 EEBUSY : Flash program memory and Data EEPROM busy
This bit indicates if the Flash program memory and Data EEPROM ready are busy
0: Flash program memory and Data EEPROM not busy
1: Flash program memory and Data EEPROM busy
Bit 5 LSEPD : LSE power-down
This bit indicates the status of the LSE oscillator
0: LSE oscillator ON
1: LSE oscillator OFF
Bit 4 HSEPD : HSE power-down
This bit indicates the status of the HSE oscillator
0: HSE oscillator ON
1: HSE oscillator OFF
Bit 3 LSIPD : LSI power-down
This bit indicates the status of the LSI oscillator
0: LSI oscillator ON
1: LSI oscillator OFF
Bit 2 HSIPD : HSI power-down
This bit indicates the status of the oscillator
0: HSI oscillator ON
1: HSI oscillator OFF
Bit 1 REGOFF: Main regulator OFF
This bit enables the direct switch-off of the main regulator regardless of the REGREADY flag status
0: The main regulator follows the standard functionality
1: The main regulator is switched off and all clocks are provided without taking into account the
REGREADY flag status
Bit 0 REGREADY: Main regulator ready
The REGREADY bit indicates the main regulator status: this bit is set when the main regulator is ready to provide the full power.
RM0031 Rev 15
116
Clock control (CLK) RM0031
Table 22. CLK register map and reset values
Address offset
(1)
Register name
7 6 5 4 3 2 1 0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10 (2)
CLK_CKDIVR
Reset value
CLK_CRTCR
Reset value
CLK_ICKCR
Reset value
CLK_PCKENR1
Reset value
CLK_PCKENR2
Reset value
CLK_CCOR
Reset value
CLK_ECKCR
Reset value
CLK_SCSR
Reset value
CLK_SWR
Reset value
CLK_SWCR
Reset value
CLK_CSSR
Reset value
CLK_CBEEPR
Reset value
CLK_HSICALR
Reset value
CLK_HSITRIMR
Reset value
CLK_HSIUNLCKR
Reset value
CLK_REGCSR
Reset value
CLK_PCKENR3
Reset value
-
0
CKM7
0
SWI7
0
-
0
x
-
0
RTCDIV2
0
-
0
PCKEN17
0
PCKEN27
1
CCODIV2
0
-
0
HSICAL7
0
HSITRIM7
0
HSIUNLCK7
0
EEREADY x
-
0
-
0
CKM6
0
SWI6
0
-
0
x
-
0
RTCDIV1
0
BEEPAHALT
0
PCKEN16
0
-
0
CCODIV1
0
-
0
HSICAL6
0
HSITRIM6
0
HSIUNLCK6
0
EEBUSY x
-
0
-
0
RTCDIV0
0
FHW
0
PCKEN15
0
PCKEN25
0
0
CCODIV0
0
-
RTCSEL3
0
SAHALT
1
PCKEN14
0
PCKEN24
0
CCOSEL3
0
-
0
RTCSEL2
0
LSIRDY
0
PCKEN13
0
PCKEN23
0
CCOSEL2
0
CKM2
0
RTCSEL1
0
LSION
0
PCKEN12
0
PCKEN22
0
CCOSEL1
0
CKM1
1
RTCSEL0
0
HSIRDY
0
PCKEN11
0
PCKEN21
0
CCOSEL0
0
CKM0
1
RTCSWBSY
0
HSION
1
PCKEN10
0
PCKEN20
0
CCOSWBSY
0
LSEBYP
0
CKM5
0
SWI5
0
x
-
0
-
0
x
CSSDGON
0
0
-
SWIF
0
CSSD
0
-
0
SWIEN
0
CSSDIE
0
CLKBEEPS
EL1
0
HSICAL2
0
SWEN
0
AUX
0
CLKBEEPS
EL0
0
HSICAL1
0
HSICAL5
0
HSICAL4
0
HSICAL3
0
HSITRIM5
0
HSITRIM4
0
HSIUNLCK5
0
HSIUNLCK4
0
HSITRIM3
0
HSITRIM2
0
HSIUNLCK3
0
HSIUNLCK2
0
HSITRIM1
0
HSIUNLCK1
0
LSEPD
1
PCKEN35
0
HSEBYP
0
CKM4
0
SWI4
0
HSEPD
1
PCKEN34
0
LSERDY
0
CKM3
0
SWI3
0
LSIPD
1
PCKEN33
0
LSEON
0
CKM2
0
SWI2
0
HSIPD
0
PCKEN32
0
HSERDY
0
CKM1
0
SWI1
0
REGOFF
0
PCKEN31
0
HSEON
0
CKM0
1
SWI0
1
SWBSY
0
CSSEN
0
BEEPSWBSY
0
HSICAL0
0
HSITRIM0
0
HSIUNLCK0
0
REGREADY x
PCKEN30
0
1.
Please refer to the “general hardware register map” table in the datasheet for details on register addresses.
2.
This register is available in low-density, medium+ and high-density devices only. In low-density devices, only bit 5 is available.
RM0031 Rev 15
RM0031
10
General purpose I/O ports (GPIO)
General purpose I/O ports (GPIO)
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
10.1 Introduction
General purpose input/output ports are used for data transfers between the chip and the external world. An I/O port can contain up to eight pins. Each pin can be individually programmed as a digital input or digital output. In addition, some ports may have alternate functions like analog inputs, external interrupts, input/output for on-chip peripherals. Only one alternate function can be mapped to a pin at a time.
An output data register, input data register, data direction register and two configuration registers are associated with each port. A particular port will behave as an input or output depending on the status of the data direction register of the port.
10.2 GPIO main features
• Port bits can be configured individually
• Selectable input modes: floating input or input with pull-up
• Selectable output modes: push-pull output or pseudo-open-drain.
• Separate registers for data input and output
• External interrupts can be enabled and disabled individually
• Output slope control for reduced EMC noise
• Alternate function I/Os for on-chip peripherals
• Read-modify-write possible on data output latch
• I/O state guaranteed in voltage range 1.6 V to V
DDIOmax
RM0031 Rev 15
125
General purpose I/O ports (GPIO) RM0031
ALTERNATE
OUTPUT
OUTPUT
ODR REGISTER
DDR REGISTER
Figure 22. GPIO block diagram
ALTERNATE
ENABLE
1
0
V
DD
PAD
P-BUFFER
PULL-UP
PULL-UP
CONDITION
V
DD
PIN
CR1 REGISTER
CR2 REGISTER
SLOPE
CONTROL
N-BUFFER
PROTECTION
DIODES
Schmitt trigger
Analog input
On/Off
INPUT
IDR REGISTER
(Read only)
Note:
ALTERNATE FUNCTION
INPUT TO ON-CHIP
PERIPHERAL
EXTERNAL
INTERRUPT
TO INTERRUPT
CONTROLLER
FROM
OTHER
BITS ai17840
In the 3.6 V tolerant and 5 V tolerant I/Os, protection diode to V
DD
is not implemented.
In the true open-drain I/Os, P-Buffer, weak pull-up and protection diode to VDD is not implemented.
10.3 Port configuration and usage
An output data register (ODR), pin input register (IDR), data direction register (DDR) are always associated with each port.
The control register 1 (CR1) and control register 2 (CR2) allow input/output options. An I/O pin is programmed using the corresponding bits in the DDR, ODR, CR1 and CR2 registers.
Bit n in the registers corresponds to pin n of the Port.
The various configurations are summarized in Table 23
.
RM0031 Rev 15
RM0031 General purpose I/O ports (GPIO)
Table 23. I/O port configuration summary
Mode
DDR bit
CR1 bit
CR2 bit
Function Pull-up P-buffer
Diodes to V
DD to V
SS
Input
Output
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
Floating without interrupt
Pull-up without interrupt
1 Floating with interrupt
1 Pull-up with interrupt
0 Open drain output
0 Push-pull output
1
Open drain output, fast mode
1 Push-pull, fast mode
Off
On
Off
On
Off
Off
Off
Off
On
Off
On
On
On
1 x x
True open drain (on specific pins)
Not implemented
Not implemented
(1)
1. The diode connected to V
DD pad and V
OL
is not implemented in true open drain pads. A local protection between the
is implemented to protect the device against positive stress.
Warning: On some packages, some ports must be considered as active even if they do not exist on the package. To avoid spurious effects, configure them as pull-up inputs without interrupt at startup, and keep them in this state when changing the port configuration. Refer to the datasheet for additional information.
Clearing the DDRx bit selects input mode. In this mode, reading a IDR bit returns the digital value of the corresponding I/O pin.
Refer to Section 10.7: Input mode details on page 121
for information on analog input, external interrupts and Schmitt trigger enable/disable.
As shown in , four different input modes can be theoretically be configured by software: floating without interrupt, floating with interrupt, pull-up without interrupt or pull-up with interrupt. However in practice, not all ports have external interrupt capability or pull-ups. You should refer to the datasheet pin-out description for details on the actual hardware capability of each port.
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General purpose I/O ports (GPIO) RM0031
Setting the DDRx bit selects output mode. In this mode, writing to the ODR bits applies a digital value to the I/O through the latch. Reading IDR bit returns the digital value from the corresponding I/O pin. Using the CR1, CR2 registers, different output modes can be configured by software: Push-pull output, Open-drain output.
Refer to Section 10.8: Output mode details on page 121 for more information.
All I/O pins are generally input floating under reset (i.e. during the reset phase) and at reset state (i.e. after reset release). However, a few pins may have a different behavior. Refer to the datasheet pinout description for all details.
10.5 Unused I/O pins
Unused I/O pins must not be left floating to avoid extra current consumption. They must be put into one of the following configurations:
• connected to V
DD
or V
SS
by external pull-up or pull-down resistor and kept as input floating (reset state),
• configured as input with internal pull-up/down resistor,
• configured as output push-pull low.
The I/O ports not present on smaller packages are automatically configured by a factory setting (unless otherwise specified in the datasheet). As a consequence, no configuration is required on these I/O ports. The bits corresponding to these ports in the configuration registers Px_ODR, PxDDR, PxCR1 and PxCR2 can be written, but this will have no effect.
The value read in the corresponding bits of the PxIDR register will be '0'.
10.6 Low power modes
Mode
Wait
Halt
Table 24. Effect of low power modes on GPIO ports
Description
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to wakeup from
Halt mode.
RM0031 Rev 15
RM0031 General purpose I/O ports (GPIO)
10.7.1 Alternate function input
Some I/Os can be used as alternate function input. For example as the port may be used as the input capture input to a timer. Alternate function inputs are not selected automatically, you select them by writing to a control bit in the registers of the corresponding peripheral.
For Alternate Function input, you should select floating or pull-up input configuration in the
DDR and CR1 registers.
Each I/O can be configured as an input with interrupt capability by setting the CR2x bit while the I/O is in input mode. In this configuration, a signal edge or level input on the I/O generates an interrupt request.
Falling or rising edge sensitivity is programmed independently for each interrupt vector in the EXTI_CR[2:1] registers.
External interrupt capability is only available if the port is configured in input mode.
Interrupt masking
Interrupts can be enabled/disabled individually by programming the corresponding bit in the configuration register (Px_CR2).
At reset state, the interrupts are disabled.
On all I/Os with an analog input, it is possible to disable the Schmitt trigger, even if the corresponding ADC channel is not enabled. The two registers ADC_TDRH and ADC_TDRL allow to disable the Schmitt trigger.
Setting one bit in these registers leads to disabling the corresponding Schmitt trigger input buffer.
In case an I/O is used as analog input, and the corresponding ADC channel is enabled
(CH[3:0] bits in ADC_CSR register), the Schmitt trigger is disabled.
Selected I/Os can be used to deliver analog signal to ADC, Comparators or DAC periphery.
The GPIO pin have to be configured in the input floating configuration without interrupt
(default state) to use it for analog function. The current consumption of the IO with enabled analog function can be reduced by disabling unused Schmitt trigger in IO input section
either by ADC_TRIGRx register in ADC interface (see Section 14.3.15: Schmitt trigger disabling
) or by switching on a corresponding analog switch in RI by setting corresponding
CHxE bit in RI_IOSRx (see
). See the product datasheet for pins with analog functions.
10.8 Output mode details
10.8.1 Alternate function output
Alternate function outputs provide a direct path from a peripheral to an output or to an I/O pad, taking precedence over the port bit in the data output latch register (Px_ODR) and forcing the Px_DDR corresponding bit to 1.
RM0031 Rev 15
125
General purpose I/O ports (GPIO) RM0031
An alternate function output can be push-pull or pseudo-open drain depending on the peripheral and Control register 1 (Px_CR1) and slope can be controlled depending on the
Control register 2 (Px_CR2) values.
Examples:
SPI outputs must be set-up as push-pull. The slope of SPI outputs is controlled by hardware and configured in fast mode to enable an optimal operation. The user must then keep the
CR2 slope control bit cleared to avoid spurious interrupts.
The maximum frequency that can be applied to an I/O can be controlled by software using the CR2 bit. Low frequency operation with improved EMC behavior is selected at reset.
Higher frequency (up to 10 MHz) can be selected if needed. This feature can be applied in either open drain or push-pull output mode on I/O ports of output type O3 or O4. Refer to the pin description tables in the datasheets for the specific output type information for each pin.
RM0031 Rev 15
RM0031 General purpose I/O ports (GPIO)
The bit of each port register drives the corresponding pin of the port.
10.9.1 Port x output data register (Px_ODR)
Address offset: 0x00
Reset value: 0x00
7
ODR7 rw
6
ODR6 rw
5
ODR5 rw
4
ODR4 rw
3
ODR3 rw
2
ODR2 rw
1
ODR1 rw
0
ODR0 rw
Bits 7:0 ODR[7:0] : Output data register bits
Writing to the ODR register when in output mode applies a digital value to the I/O through the latch.
Reading the ODR returns the previously latched value in the register.
In Input mode, writing in the ODR register, latches the value in the register but does not change the pin state. The ODR register is always cleared after reset. Bit read-modify-write instructions (BSET,
BRST) can be used on the DR register to drive an individual pin without affecting the others.
10.9.2 Port x pin input register (Px_IDR)
Address offset: 0x01
Reset value: 0xXX
7
IDR7 r
6
IDR6 r
5
IDR5 r
4
IDR4 r
3
IDR3 r
2
IDR2 r
1
IDR1 r
0
IDR0 r
Bits 7:0 IDR[7:0] : Pin input values
The pin register can be used to read the pin value irrespective of whether port is in input or output mode. This register is read-only.
0: Low logic level
1: High logic level
Note: Px_IDR reset value depends on the external circuitry.
RM0031 Rev 15
125
General purpose I/O ports (GPIO) RM0031
10.9.3 Port x data direction register (Px_DDR)
Address offset: 0x02
Reset value: 0x00
7
DDR7 rw
6
DDR6 rw
5
DDR5 rw
4
DDR4 rw
3
DDR3 rw
2
DDR2 rw
1
DDR1 rw
0
DDR0 rw
Bits 7:0 DDR[7:0] : Data direction bits
These bits are set and cleared by software to select input or output mode for a particular pin of a port.
0: Input mode
1: Output mode
10.9.4 Port x control register 1 (Px_CR1)
Address offset: 0x03
Reset value: 0x00 except for PA_CR1 which reset value is 0x01.
7
C17 rw
6
C16 rw
5
C15 rw
4
C14 rw
3
C13 rw
2
C12 rw
1
C11 rw
0
C10 rw
Bits 7:0 C1[7:0] : Control bits
These bits are set and cleared by software. They select different functions in input mode and output mode ( see .
– In input mode (DDR = 0):
0: Floating input
1: Input with pull-up
– In output mode (DDR = 1):
0: Pseudo open drain
1: Push-pull, slope control for the output depends on the corresponding CR2 bit
Note: This bit has no effect on true open drain ports (refer to pin marked “T” in datasheet pin description table).
RM0031 Rev 15
RM0031 General purpose I/O ports (GPIO)
10.9.5 Port x control register 2 (Px_CR2)
7
C27 rw
Address offset: 0x04
Reset value: 0x00
6
C26 rw
5
C25 rw
4
C24 rw
3
C23 rw
2
C22 rw
1
C21 rw
0
C20 rw
Bits 7:0 C2[7:0] : Control bits
These bits are set and cleared by software. They select different functions in input mode and output mode. In input mode, the CR2 bit enables the interrupt capability if available. If the I/O does not have interrupt capability, setting the CR2 bit has no effect. In output mode, setting the bit increases the speed of the I/O. This applies to ports with O3 and O4 output types (see pin description table).
– In input mode (DDR = 0):
0: External interrupt disabled
1: External interrupt enabled
– In output mode (DDR = 1):
0: Output speed up to 2 MHz
1: Output speed up to 10 MHz
10.9.6 Peripheral alternate function remapping
Some peripheral alternate functions can be remapped to different I/O ports through two remapping registers. Refer to SYSCFG remap control register 1 (SYSCFG_RMPCR1),
SYSCFG remap control register 2 (SYSCFG_RMPCR2) and SYSCFG remap control register 3 (SYSCFG_RMPCR3), in Section 11: Routing interface (RI) and system configuration controller (SYSCFG) .
Note:
Each GPIO port has five registers mapped as shown in Table 25
. Refer to the register map in the corresponding datasheet for the base address for each port.
At reset state, all ports are input floating. Exceptions are indicated in the pin description table of the corresponding datasheet.
Address offset Register name
0x00
0x01
0x02
0x03
0x04
Px_ODR
Reset value
Px_IDR
Reset value
Px_DDR
Reset value
Px_CR1
(1)
Reset value
Px_CR2
Reset value
1. PA_CR1 reset value is 0x01.
7
Table 25. GPIO register map
6 5 4
ODR7
0
IDR7 x
DDR7
0
C17
0
C27
0
ODR6
0
IDR6 x
DDR6
0
C16
0
C26
0
ODR5
0
IDR5 x
DDR5
0
C15
0
C25
0
ODR4
0
IDR4 x
DDR4
0
C14
0
C24
0
3
ODR3
0
IDR3 x
DDR3
0
C13
0
C23
0
2
ODR2
0
IDR2 x
DDR2
0
C12
0
C22
0
1
ODR1
0
IDR1 x
DDR1
0
C11
0
C21
0
0
ODR0
0
IDR0 x
DDR0
0
C10
0
C20
0
RM0031 Rev 15
125
Routing interface (RI) and system configuration controller (SYSCFG)
11 Routing interface (RI) and system configuration controller (SYSCFG)
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
11.1 RI and SYSCFG introduction
The system configuration controller offers remapping capabilities of some alternate functions on different I/O ports and on TIM4 & ADC1 DMA channels. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not affect the GPIO capabilities of the I/O ports (see
General purpose I/O ports (GPIO) on page 117
). Refer to Section 11.5: SYSCFG registers
for remapping capabilities on TIM4 & ADC1 DMA channels.
The routing interface provides high flexibility by allowing the software routing of I/Os to the input captures of TIM1. It also controls the routing of internal analog signals to ADC1,
COMP1, COMP2, DAC and internal reference voltage V
REFINT
. It also provides a set of registers for efficiently managing up to 20 capacitive sensing channels (low-density devices) and up to 16 capacitive sensing channels (medium, medium+ and high-density devices).
11.2 RI main features
• 28 programmable I/O switches (low-density devices) and 24 programmable I/O switches (medium, medium+ and high-density devices) for signal routing
• 10 programmable analog switches (low and medium-density devices) or 13 programmable analog switches (medium+ and high-density devices) for signal routing
• COMP1 and COMP2 input and output routing (a)
• TIM1 input capture 2 and 3 routing selection from selectable I/Os (medium, medium+ and high-density devices).
•
DAC output routing to selectable I/Os for 28 and 32-pin packages (a)
medium+ and high-density devices).
• Internal reference voltage routing to selectable I/Os.
• Software or hardware management of the charge transfer acquisition sequence.
a. Not available on STM8L051xx/L052xx devices, but STM8L05xxx devices have comparators.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Figure 23. Routing interface (RI) block diagram (medium+ and high-density devices)
Routing interface
PA 6
PA 5
PA 4
COMP -
PC 7
PC 4
PC 3
V REFINT out
PC 2
PD7
PD6
PD5
PD4
PB 7
DAC
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
PD3
PD2
COMP+
PD1
PD0
PE 5
I/O switches
CHxE[24:1]
WNDWE bit
Window mode
PF 0
PF 1
PF 2
PF 3
NC
NC
Analog switches
AS[14:0] bits
AS0
AS1
AS2
AS3
AS4
AS5
AS6
AS7
AS8
AS9
AS1 0
AS1 1
AS1 2
AS1 3
AS1 4
ADC1
V DD
400 kΩ pull-up
400 kΩ pull-d own
GN D
10 kΩ pull-up
10 kΩ pull-d own
V
REFIN T
+
-
COMP
COMP1
VREFEN bit
Bias fromV REFINT
Closed for 28- and
32-pin packages
VREFOUTEN bit
External input
DAC1
Rail to rail
+
COMP
-
COMP2
Fast/Slow
DAC2
PF0
R
Buffer
DAC1
R/2R
Bu ffer
Closed for 48-pin packages
V
REFINT
V
REFINT
¾ V
REFINT
½ V
REFINT
¼ V
REFINT
INSEL[2:0]
Internal voltage reference
PF1
R
Buffer
DAC2
R/2R
MS19204V2
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Figure 24. Routing interface (RI) block diagram (medium-density devices)
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PA 6
PA 5
PA 4
PC 7
PC 4
PC 3
PC 2
PD7
PD6
PD5
PD4
PB 7
PB 0
PD3
PD2
PD1
PD0
PE 5
I/O switches
CHxE[24:1] bits
NC
NC
NC
NC
NC
NC
Analog switches
AS[14:0] bits
AS0
AS1
AS2
AS3
AS4
AS5
AS6
AS7
AS8
AS9
AS10
AS11
AS12
AS13
AS14
ADC1
PF 0
Closed for 28- and
32-pi n pac kages
R
Buffer
WNDWE bit
Window mode
DAC
R/2R
V
REFINT
400 kΩ pull-up
V DD
10 kΩ pull-up
400 kΩ pull-down
GND
10 kΩ pull-down
V REFINT
+
COMP
-
VREFEN bit
Bias from
V
REFINT
COMP1
External input
Rail to rail
+
COMP
-
COMP2
Fast/Slow
VREFOUTEN bit
Buffer
V
REFINT
¾ V
REFINT
½ V
REFINT
¼ V
REFINT
INSEL[2:0]
Internal reference voltage
DAC ai18270c
1. DAC and comparators are not available on STM8L05xx value line devices.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Figure 25. Routing interface (RI) block diagram (low-density devices)
PB3
PB2
PB1
PB0
PD3
PD2
PE3
PD1
PD0
PE5
PE4
I/O switches
CHxE[24:1] bits
PA6
PA5
PA4
PA7
PC7
PC4
PC3
PE7
PC2
PD7
PD6
PD5
PD4
PB7
PB6
PB5
PB4
PF0
NC
NC
NC
NC
NC
Analog switches
AS[14:0] bits
AS0
AS1
AS2
AS3
AS4
AS5
AS6
AS7
AS8
AS9
AS10
AS11
AS12
AS13
AS14
ADC1
Closed only in
20-pin devices
WINDWE bit
Window mode
400 kΩ pull-up
V DD
10 kΩ pull-up
400 kΩ pull-down
GND
10 kΩ pull-down
V
REFINT
+
COMP
-
VREFEN
bit
Bias from V REFINT
COMP1
External input
Rail to rail
+
-
COMP
COMP2
Fast/Slow
VREFOUTEN bit
V
REFINT
Buffer
V
REFINT
3/4 V REFINT
1/2 V REFINT
1/4 V REFINT
Internal reference voltage
INSEL[2:0]
MS19808V2
1. Comparators (COMP) are not available on STM8L051/L052 value line devices.
The RI registers can be accessed only when the comparator clock is enabled by setting the
PCKEN25 bit in the CLK_PCKENR2 register. Refer to
.
On low-density devices, 28 general purpose I/Os are grouped into 4 groups of three I/Os each and into groups of 4 I/Os each. On medium, medium+ and high-density devices, 24
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031 general purpose I/Os are grouped into 4 groups of three I/Os each.
shows the I/O groups and the control registers used to route them to the analog blocks.
• Two blocks of switches control the routing of signals to the analog blocks.
– I/O switches controlled by the RI_IOSRx registers
– Analog switches controlled by the RI_ASCRx registers
• An additional set of switches controls the routing to the TIM1 timer inputs (not shown in block diagram)
• A complementary set of registers controls the configuration of the I/Os and are designed to manage up to 20 capacitive sensing channels on low-density devices and up to 16 capacitive sensing channels on medium, medium+ and high-density devices
(not shown in the block diagram).
When the I/Os are switched to analog mode (I/O switches CHxE are set or ADC used) , the
Schmitt trigger is disabled by default. At that time, the bit in the Px_IDR register associated with the I/O is always read as 0 whatever the level on the pin. The Schmitt trigger can be enabled by setting the STE bit in the COMP_CSR1 register but it acts as a simple comparator in this configuration mode. In that case, it is possible to read the I/O state through the Px_IDR register while the hysteresis is kept disabled to reduce the power consumption of the device. The state of an I/O switched to analog mode can be read through the RI_IOIRx registers anyway whatever the STE bit value.
• When I/Os are used as ADC inputs: the I/O switch and analog switches are controlled directly by the ADC. The corresponding CHxE and ASx bits in the RI registers are not used and must be kept cleared (switches left open).
• When I/Os are used as inputs/outputs for analog blocks other than the ADC : the
I/O switch and analog switch have to be controlled by the RI_IOSRx and RI_ASCRx registers. The corresponding CHxE and ASx bits in the RI registers must be set by software to close the switches and cleared to open the switches.
I/O
Group
GPIO port
Table 26. I/O groups and selection
I/O switch control bit
RI_IOSRx registers
ADC1 input
Analog switch control bit in
RI_ASCR1 register
Comparator
(1)
/
REFINT functions
Group 1
Group 2
Group 3
PA5
PA4
PA7
(2)
PC7
PC4
PC3
PE7
PC2
PD7
PD6
CH2E bit
CH3E bit
CH29E bit
CH4E bit
CH5E bit
CH6E bit
CH26E bit
CH7E bit
CH8E bit
CH9E bit
ADC1_IN1
ADC1_IN2
-
ADC1_IN3
ADC1_IN4
ADC1_IN5
ADC1_IN25
ADC1_IN6
ADC1_IN7
ADC1_IN8
AS0 bit
AS1 bit
AS2 bit
COMP1+ in
COMP1+ in
COMP2- in
COMP1+ in
V
REFINT
out
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
I/O
Group
GPIO port
Table 26. I/O groups and selection (continued)
I/O switch control bit
RI_IOSRx registers
ADC1 input
Analog switch control bit in
RI_ASCR1 register
Comparator (1) /
DAC
(1)
/V
REFINT functions
Group 4
Group 5
Group 6
Group 7
Group 8
NA
NA
NA
NA
PB5
PB4
PB3
PB2
PD5
PD4
PB7
PB6
PB1
PB0
PD3
PD2
PE3
PD1
PD0
PE5
PE4
PF0
PF1
PF2
PF3
(3)
CH10E bit
CH11E bit
CH12E bit
CH13E bit
CH14E bit
CH15E bit
CH16E bit
CH17E bit
CH18E bit
CH19E bit
CH20E bit
CH21E bit
CH27E bit
CH22E bit
CH23E bit
CH24E bit
CH28E bit
NA
NA
NA
NA
ADC1_IN9
ADC1_IN10
ADC1_IN11
ADC1_IN12
ADC1_IN13
ADC1_IN14
ADC1_IN15
ADC1_IN16
ADC1_IN17
ADC1_IN18
ADC1_IN19
ADC1_IN20
ADC1_IN26
ADC1_IN21
ADC1_IN22
ADC1_IN23
ADC1_IN27
ADC1_IN24
ADC1_IN25
ADC1_IN26
ADC1_IN27
AS3 bit
AS4 bit
AS5 bit
AS6 bit
AS7 bit
AS8 bit
AS9 bit
AS10 bit
AS11 bit
COMP1+ in
COMP1+ in
DAC out
COMP1+ in
COMP1+ in
COMP1+ in
COMP2+ in
COMP1+ in
COMP1+ in
COMP1+ in
COMP1+ in
1. Comparators (COMP) are not available on STM8L051xx/L052xx devices. DAC is not available on low density STM8L05xxx/STM8L15xxx devices.
2. On low-density devices only
3. On medium+ and high-density devices only.
11.2.3 TIM1 input capture routing
TIM1 is not available in low-density devices.
After reset, the Timer 1 Input Capture 2 and Input Capture 3 signals are connected to the I/O port assigned in the datasheet pinout (default routing). The I/O routing can be changed by
programming registers RI_ICR1 and RI_ICR2. Refer to Table 27
.
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Table 27. TIM1 input capture routing
IC2CS[4:0] /
IC3CS[4:0] bit value
00000
00001
00010
I/O port routed to TIM1.IC2 input I/O port routed to TIM1.IC3 input default routing (PD4)
PF0
Reserved (medium-density devices)
PF2 (medium+ and high-density devices) default routing (PD5)
Reserved (medium-density devices)
PF1 (medium+ and high-density devices)
Reserved (medium-density devices)
PF3 (medium+ and high-density devices)
01111
10000
10001
10010
10011
10100
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
10101
10110 other values
PE2
PE4
PE6
PE3
PE5
PE7
PD0
PD2
PD1
PD3
PD4 PD5
PD6 PD7
PC0 PC1
PC2 PC3
PC4 PC5
PB0
PB6
PA5 PA6 default routing (PD4)
PB1
PB7 default routing (PD5)
11.2.4 TIM2 & TIM3 routing
Note: Only available on low-density devices.
To reduce the CPU load required for the management of the 20 capacitive sensing channels, low-density devices feature a hardware mode for handling the charger transfer acquisition sequence. This is done by using timer TIM2 to control the state of the I/Os in the
I/O groups. Timer TIM3 is used to count the number of charge transfer cycles generated before the voltage across C
S
reaches V
IH
.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Figure 26. TIM2 and TIM3 interconnections
TIF bit
RI_IOMRx bit
I/O1
RI_IOMRx bit
I/O2
THALT bit
AM bit
ITR
TIM2
OC1
TGO
OC2
RI_IOMRx bit
I/O3
ITR TIM3
TIM3_CH1
1
0
IC1
RI trigger interrupt
TIE bit
MS19206V2
When using the hardware acquisition mode:
• TIM2 OC1 controls the state of the electrode I/O
– When OC1 is high, the electrode I/O is set to output push-pull high.
– When OC1 is low, the electrode I/O is set to input floating mode
• TIM2 OC2 controls both the sampling capacitor and the electrode I/O analog switch
– When OC2 is high, the analog switch is closed
– When OC2 is low, the analog switch is open
Refer to Section 16.3: Comparator 1 (COMP1) on page 247 for the description of the
COMP1 interconnections.
Refer to Section 16.4: Comparator 2 (COMP2) on page 248 for the description of the
COMP2 interconnections.
Note:
DAC is not available on low-density STM8L05xxx/STM8L15xxx.
In medium-density devices, for 28 and 32-pin devices, the DAC_OUT1 can be routed to any
I/O of group 5 by setting the corresponding I/O switch bit (CH13E in the RI_IOSR1 register,
CH14E in the RI_IOSR2 register or CH15E in the RI_IOSR3 register).
In medium+ and high-density devices, for 48-pin devices, the DAC_OUT2 can be routed to any I/O of group 5 by setting the corresponding I/O switch bit (CH13E in the RI_IOSR1 register, CH14E in the RI_IOSR2 register or CH15E in the RI_IOSR3 register).
In this case group 5 cannot be used for ADC1.
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG)
Figure 27. DAC interconnections
To ADC1 (fast channel)
RM0031
PF0
DAC buffer
R/2R
This switch is closed in 28- and 32-pin devices
+
–
COMP2
PB4
PB5
DAC output
Other inputs
Other inputs
Other inputs
PB6
To ADC1 (slow channel) ai14874c
The DAC_OUT1 can be routed to the COMP2 inverting input by writing the value 0b110 in the INSEL[2:1] bits in the COMP_CSR3 register.
In medium-density devices, for 48-pin packages, the DAC_OUT1 is connected to the
ADC1_IN24 input.
In medium+ and high-density devices, for 64 and 80-pin packages, the DAC_OUT2 is connected to the ADC1_IN25 input.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
11.2.7 Internal reference voltage routing
Figure 28. Internal reference voltage output
PB4
PB5
PB6
Closed only in 20-pin devices
VREFOUTEN
PC2
PD7
PD6
Internal reference voltage
V
REFINT
V
REFINT
~1.2 V
3/4 V
REFINT
1/2 V
REFINT
1/4 V
REFINT
Internal reference voltage output can be routed to any I/O of group 3 following this procedure:
1.
Set the bit VREFOUTEN in COMP_CSR3
2. Close the I/O switch of any I/O of group 3 by setting CH7E in RI_IOSR1 or CH8E in
RI_IOSR2 or CH9E in RI_IOSR3.
Interrupt event
Interrupt event trigger
Table 28. RI interrupt requests
Event flag
Enable control bit
Exit from
Wait/
Low power wait
TIF TIE Yes
Exit from
Halt/
Active-halt
No
11.4.1 Timer input capture routing register 1 (RI_ICR1)
7
Address offset: 0x01
Reset value: 0x00
6 5 4 3
Reserved rw rw
2
IC2CS[4:0] rw
1 rw
0 rw
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Bits 7:5 Reserved, must be kept cleared.
Bits 4:0 IC2CS[4:0] : TIM1 Input Capture 2 I/O selection
These bits are set and cleared by software. They select which I/O port is routed to Timer 1 input
Note: This register is not available on low-density devices.
11.4.2 Timer input capture routing register 2 (RI_ICR2)
7
Address offset: 0x02
Reset value: 0x00
6 5 4 3
Reserved rw rw
2
IC3CS[4:0] rw
1 0 rw rw
Bits 7:5 Reserved, must be kept cleared.
Bits 4:0 IC3CS[4:0] : TIM1 Input Capture 3 I/O selection
These bits are set and cleared by software. They select which I/O port is routed to Timer 1 Input
.
Note: This register is not available on low-density devices.
Address offset: 0x03
Reset value: 0xXX where X is undefined
7
CH22I r
6
CH19I r
5
CH16I r
4
CH13I r
3
CH10I r
2
CH7I r
1
CH4I r
0
CH1I r
Bits 7:0 CHxI : I/O pin input value
These bits return the corresponding I/O pin value irrespective of the port configuration (similar to the Px_IDR register). This register is read-only.
0: Low logic level
1: High logic level
Note: This register controls the first I/O of each group of I/Os.
7
CH23I r
Address offset: 0x04
Reset value: 0xXX where X is undefined
6
CH20I r
5
CH17I r
4
CH14I r
3
CH11I r
2
CH8I r
1
CH5I r
0
CH2I r
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Bits 7:0 CHxI : I/O pin input value
These bits return the corresponding I/O pin value irrespective of the port configuration (similar to the Px_IDR register). This register is read-only.
0: Low logic level
1: High logic level
Note: This register controls the second I/O of each group of I/Os.
Address offset: 0x05
Reset value: 0xXX where X is undefined
7
CH24I r
6
CH21I r
5
CH18I r
4
CH15I r
3
CH12I r
2
CH9I r
1
CH6I r
0
CH3I r
Bits 7:0 CHxI : I/O pin input value
These bits return the corresponding I/O pin value irrespective of the port configuration (similar to the Px_IDR register). This register is read-only.
0: Low logic level
1: High logic level
Note: This register controls the third I/O of each group of I/Os.
11.4.6 I/O control mode register 1 (RI_IOCMR1)
Address offset: 0x06
Reset value: 0x00
7
CH22M rw
6
CH19M rw
5
CH16M rw
4
CH13M rw
3
CH10M rw
2
CH7M rw
1
CH4M rw
0
CH1M rw
Bits 7:0 CHxM : I/O control mode
These bits are set and cleared by software to select how the I/O is controlled.
0: I/O x is controlled by the standard GPIO registers. The I/O x switch is directly controlled by the
RI_IOSR1 register.
1: I/O x is set to protected mode and is only controlled by the RI_IOSR1 and RI_IOGCR registers (standard GPIO registers have no effect on the configuration of I/O x).
Note: This register controls the first I/O of each group of I/Os.
11.4.7 I/O control mode register 2 (RI_IOCMR2)
Address offset: 0x07
Reset value: 0x00
7
CH23M rw
6
CH20M rw
5
CH17M rw
4
CH14M rw
3
CH11M rw
2
CH8M rw
1
CH5M rw
0
CH2M rw
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Bits 7:0 CHxM : I/O control mode
These bits are set and cleared by software to select how the I/O is controlled.
0: I/O x is controlled by the standard GPIO registers. The I/O x switch is directly controlled by the
RI_IOSR2 register.
1: I/O x is set to protected mode and is only controlled by the RI_IOSR2 and RI_IOGCR registers (standard GPIO registers have no effect on the configuration of I/O x).
Note: This register controls the second I/O of each group of I/Os.
11.4.8 I/O control mode register 3 (RI_IOCMR3)
Address offset: 0x08
Reset value: 0x00
7
CH24M rw
6
CH21M rw
5
CH18M rw
4
CH53M rw
3
CH12M rw
2
CH9M rw
1
CH6M rw
0
CH3M rw
Bits 7:0 CHxM : I/O control mode
These bits are set and cleared by software to select how the I/O is controlled.
0: I/O x is controlled by the standard GPIO registers. The I/O x switch is directly controlled by the
RI_IOSR3 register.
1: I/O x is set to protected mode and is only controlled by the RI_IOSR3 and RI_IOGCR registers (standard GPIO registers have no effect on the configuration of I/O x).
Note: This register controls the third I/O of each group of I/Os.
11.4.9 I/O switch register 1 (RI_IOSR1)
Address offset: 0x09
Reset value: 0x00
7
CH22E rw
6
CH19E rw
5
CH16E rw
4
CH13E rw
3
CH10E rw
2
CH7E rw
1
CH4E rw
0
CH1E rw
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Bits 7:0 CHxE : I/O switch control
If the corresponding RI_IOCMRx bit is cleared:
These bits are set and cleared by software to open and close the I/O switches. If the I/O is used for the ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: I/O x switch is open (I/O x is controlled by the GPIO registers or ADC1).
1: I/O x switch is closed (analog channel enabled).
If the corresponding RI_IOCMRx bit is set and the AM bit is cleared in the RI_CR register
(software management of the charge transfer acquisition sequence ):
These bits are set and cleared by software. They define the configuration of the I/O.
0: I/O x is forced to output push-pull low mode.
1: I/O x configuration is determined by bit 0 and bit 1 in the RI_IOGCR register.
If the corresponding RI_IOCMRx bit is set and the AM bit is also set in the RI_CR register
(hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define if the corresponding I/O x state is controlled by the TIM2 timer.
0: I/O x is forced to output push-pull low mode
1: I/O x configuration is determined by the timer TIM2
Note: This register controls the first I/O of each group of I/Os.
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG) RM0031
11.4.10 I/O switch register 2 (RI_IOSR2)
Address offset: 0x0A
Reset value: 0x00
7
CH23E rw
6
CH20E rw
5
CH17E rw
4
CH14E rw
3
CH11E rw
2
CH8E rw
1
CH5E rw
0
CH2E rw
Bits 7:0 CHxE : I/O switch control.
If the corresponding RI_IOCMRx bit is cleared:
These bits are set and cleared by software to open and close the I/O switches. If the I/O is used for the ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: I/O x switch is open (I/O x is controlled by the GPIO registers or ADC1).
1: I/O x switch is closed (analog channel enabled).
If the corresponding RI_IOCMRx bit is set and the AM bit is cleared in the RI_CR register
(software management of the charge transfer acquisition sequence ):
These bits are set and cleared by software. They define the configuration of the I/O.
0: I/O x is forced to output push-pull low mode.
1: I/O x configuration is determined by bit 2 and bit 3 in the RI_IOGCR register.
If the corresponding RI_IOCMRx bit is set and the AM bit is also set in the RI_CR register
(hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define if the corresponding I/O x state is controlled by the TIM2 timer.
0: I/O x is forced to output push-pull low mode
1: I/O x configuration is determined by the timer TIM2
Note: This register controls the second I/O of each group of I/Os.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
11.4.11 I/O switch register 3 (RI_IOSR3)
Address offset: 0x0B
Reset value: 0x00
7
CH24E rw
6
CH21E rw
5
CH18E rw
4
CH15E rw
3
CH12E rw
2
CH9E rw
1
CH6E rw
0
CH3E rw
Bits 7:0 CHxE : I/O Switch control.
If the corresponding RI_IOCMRx bit is cleared:
These bits are set and cleared by software to open and close the I/O switches. If the I/O is used for the ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: I/O x switch is open (I/O x is controlled by the GPIO registers or ADC1).
1: I/O x switch is closed (analog channel enabled).
If the corresponding RI_IOCMRx bit is set and the AM bit is cleared in the RI_CR register
(software management of the charge transfer acquisition sequence ):
These bits are set and cleared by software. They define the configuration of the I/O.
0: I/O x is forced to output push-pull low mode.
1: I/O x configuration is determined by bit 4 and bit 5 in the RI_IOGCR register.
If the corresponding RI_IOCMRx bit is set and the AM bit is also set in the RI_CR register
(hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define if the corresponding I/O x state is controlled by the TIM2 timer.
0: I/O x is forced to output push-pull low mode
1: I/O x configuration is determined by the timer TIM2
Note: This register controls the third I/O of each group of I/Os.
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG)
11.4.12 IO group control register (RI_IOGCR)
Address offset: 0x0C
Reset value: 0xFF
7 6 5 4 3
IOM4[1:0] IOM3[1:0] rw rw rw rw rw
IOM2[1:0]
2 rw
RM0031
1 rw
IOM1[1:0]
0 rw
Bits 7:6 IOM4[1:0] : I/O mode 4
If the bit AM in the RI_CR register is cleared (software management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the configuration of the I/O if the corresponding RI_IOCMRx bit is set.
00: I/O x is forced to output push-pull low mode.
01: I/O x is forced to output push-pull high mode.
10: I/O x is forced to input floating mode with the I/O switch open.
11: I/O x is forced to input floating mode with the I/O switch closed. The I/O x Schmitt trigger hysteresis is disabled but the I/O pin value can still be read.
If the AM bit in the RI_CR register is set (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the usage of the I/O.
00: I/O used for the sampling capacitor
01: I/O used for the electrode
Other: reserved
Note: These bits control the fourth I/O of each group of I/Os (only available on low-density devices).
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Bits 5:4 IOM3[1:0] : I/O mode 3
If the bit AM in the RI_CR register is cleared (software management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the configuration of the I/O if the corresponding RI_IOCMRx bit is set.
00: I/O x is forced to output push-pull low mode.
01: I/O x is forced to output push-pull high mode.
10: I/O x is forced to input floating mode with the I/O switch open.
11: I/O x is forced to input floating mode with the I/O switch closed. The I/O x Schmitt trigger hysteresis is disabled but the I/O pin value can still be read.
On low-density devices, if the AM bit in the RI_CR register is set (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the usage of the I/O.
00: I/O used for the sampling capacitor
01: I/O used for the electrode
Other: reserved
Note: These bits control the third I/O of each group of I/Os .
Bits 3:2 IOM2[1:0] : I/O mode 2
If the bit AM in the RI_CR register is cleared (software management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the configuration of the I/O if the corresponding RI_IOCMRx bit is set.
00: I/O x is forced to output push-pull low mode.
01: I/O x is forced to output push-pull high mode.
10: I/O x is forced to input floating mode with the I/O switch open.
11: I/O x is forced to input floating mode with the I/O switch closed. The I/O x Schmitt trigger hysteresis is disabled but the I/O pin value can still be read.
On low-density devices, if the AM bit in the RI_CR register is set (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the usage of the I/O.
00: I/O used for the sampling capacitor
01: I/O used for the electrode
Other: reserved
Note: These bits control the second I/O of each group of I/Os.
RM0031 Rev 15
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Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Bits 1:0 IOM1[1:0] : I/O mode 1
If the bit AM in the RI_CR register is cleared (software management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the configuration of the I/O if the corresponding RI_IOCMRx bit is set.
00: I/O x is forced to output push-pull low mode.
01: I/O x is forced to output push-pull high mode.
10: I/O x is forced to input floating mode with the I/O switch open.
11: I/O x is forced to input floating mode with the I/O switch closed. The I/O x Schmitt trigger hysteresis is disabled but the I/O pin value can still be read.
On low-density devices, if the AM bit in the RI_CR register is set (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define the usage of the I/O.
00: I/O used for the sampling capacitor
01: I/O used for the electrode
Other: reserved
Note: These bits control the first I/O of each group of I/Os.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
7
AS7 rw
Address offset: 0x0D
Reset value: 0x00
6
AS6 rw
5
AS5 rw
4
AS4 rw
3
AS3 rw
2
AS2 rw
1
AS1 rw
0
AS0 rw
Bits 7:0 ASx : Analog switch control
These bits are set and cleared by software to control the analog switches. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
7
Reserved
Address offset: 0x0E
Reset value: 0x00
6
AS14 rw
5
Reserved
4 3
AS11
rw
2
AS10
rw
1
rw
0
AS8 rw
Bit 6 AS14 : Analog switch 14
This bit is set and cleared by software to control AS14 analog switch. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
Bit 3
(1)
AS11
This bit is set and cleared by software to control AS11 analog switch. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
AS10
This bit is set and cleared by software to control AS10 analog switch. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
AS9
This bit is set and cleared by software to control AS9 analog switch. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
Bit 0 AS8 : Analog switch control
This bit is set and cleared by software to control AS8 analog switch. If the I/O is used for ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: Analog switch open
1: Analog switch closed
1. Available on low, medium+ and high-density devices only. Reserved on medium-density devices.
7
Address offset: 0x0F
Reset value: 0x00
6 5
Reserved
4
Bits 7:4 Reserved, must be kept cleared
Bit 3 400KPD : 400 k Ω pull-down resistor
This bit enables the 400 k Ω pull-down resistor.
0: 400 k Ω pull-down resistor disabled
1: 400 k Ω pull-down resistor enabled
Bit 2 10KPD : 10 k Ω pull-down resistor
This bit enables the 10 k Ω pull-down resistor.
0: 10 k Ω pull-down resistor disabled
1: 10 k Ω pull-down resistor enabled
Bit 1 400KPU : 400 k Ω pull-up resistor
This bit enables the 400 k Ω pull-up resistor.
0: 400K pull-up resistor disabled
1: 400K pull-up resistor enabled
Bit 0 10KPU : 10 k Ω pull-up resistor
This bit enables the 10 k Ω pull-up resistor.
0: 10 k Ω pull-up resistor disabled
1: 10 k Ω pull-up resistor enabled
3
400KPD rw
2
10KPD rw
1
400KPU rw
0
10KPU rw
Note: 1 To connect the pull-up or pull-down to ADC1 input, the corresponding ADC1 analog switch must be enabled using the corresponding register.
2 To avoid extra power consumption, only one resistor should be enabled at a time.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
11.4.16 Control register (RI_CR)
Address offset: 0x20
Reset value: 0x00
7 6
Reserved
5 4 3
THALT rw
2
AM rw
1
TIF rc_w1
0
TIE rw
Bits 7:4 Reserved, must be kept cleared.
Bit 3 THALT : Timer halted mode
This bit is set and cleared by software to select Timer halted mode. In this mode, TIM2 and TIM3 are halted when a trigger event occurs and remain halted until the event is cleared. This allows the event to be processed.
0: Timer halted mode disabled
1: Timer halted mode enabled
Bit 2 AM : Acquisition mode
This bit is set and cleared by software. It selects how the charge transfer acquisition sequence is managed .
0: Charge transfer acquisition sequence managed by software
1: Charge transfer acquisition sequence managed by hardware
Bit 1 TIF : Trigger interrupt flag
This flag is set by hardware when a trigger event occurs caused by V
IH
voltage being reached on the sampling capacitor I/O and only if the corresponding I/O mask bit is not set. It is cleared by software writing “1”. If the bit TIE is set, an interrupt is generated.
0: No trigger event occurred
1: Trigger event pending
Bit 0 TIE : Trigger interrupt enable
This bit is set and cleared by software. It enables the generation of an interrupt on trigger event.
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Note: This register is only available on low-density devices.
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
11.4.17 IO mask register 1 (RI_IOMR1)
Address offset: 0x21
Reset value: 0x00
7
CH22M rw
6
CH19M rw
5
CH16M rw
4
CH13M rw
3
CH10M rw
2
CH7M rw
1
CH4M rw
0
CH1M rw
Note:
Bits 7:0 CHxM : I/O mask
These bits are set and cleared by software to mask events from an I/O or to avoid triggering multiple events from an I/O.
0: Event from the I/O is allowed
1: Event from the I/O is masked
This register controls the first I/O of each group of I/Os and is only available on low-density devices.
11.4.18 IO mask register 2 (RI_IOMR2)
Address offset: 0x22
Reset value: 0x00
7
CH23M rw
6
CH20M rw
5
CH17M rw
4
CH14M rw
3
CH11M rw
2
CH8M rw
1
CH5M rw
0
CH2M rw
Note:
Bits 7:0 CHxM : I/O mask
These bits are set and cleared by software to mask event from an I/O or to avoid triggering multiple events from an I/O .
0: Event from the I/O is allowed
1: Event from the I/O is masked
This register controls the second I/O of each group of I/Os and is only available on lowdensity devices.
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
11.4.19 IO mask register 3 (RI_IOMR3)
Address offset: 0x23
Reset value: 0x00
7
CH24M rw
6
CH21M rw
5
CH18M rw
4
CH15M rw
3
CH12M rw
2
CH9M rw
1
CH6M rw
0
CH3M rw
Note:
Bits 7:0 CHxM : I/O mask
These bits are set and cleared by software to mask events from an I/O or to avoid triggering multiple events from an I/O.
0: Event from the I/O is allowed
1: Event from the I/O is masked
This register controls the first I/O of each group of I/Os and is only available on low-density devices.
11.4.20 IO mask register 4 (RI_IOMR4)
Address offset: 0x24
Reset value: 0x00
7
CH28M rw
6
CH27M rw
5 4
Reserved
3 2 1
CH26M rw
0
CH29M rw
Bits 7:6 CHxM : I/O mask
These bits are set and cleared by software to mask events from an I/O or to avoid triggering multiple events from an I/O.
0: Event from the I/O is allowed
1: Event from the I/O is masked
Bits 5:2 Reserved, must be kept cleared.
Bits 1:0 CHxM : I/O mask
These bits are set and cleared by software to mask events from an I/O or to avoid triggering multiple events from an I/O.
0: Event from the I/O is allowed
1: Event from the I/O is masked
Note: This register controls the first I/O of each group of I/Os. and is only available on low-density devices.
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Address offset: 0x25
Reset value: 0xXX where X is undefined
7
CH28I r
6
CH27I r
5 4
Reserved
3 2 1
CH26I r
0
CH29I r
Bits 7:6 CHxI : I/O pin input value
These bits return the corresponding I/O pin value irrespective of the port configuration (similar to the
Px_IDR register). This register is read-only.
0: Low logic level
1: High logic level
Bits 5:2 Reserved, must be kept cleared.
Bits 1:0 CHxI : I/O pin input value
These bits return the corresponding I/O pin value irrespective of the port configuration (similar to the
Px_IDR register). This register is read-only.
0: Low logic level
1: High logic level
Note: This register controls the fourth I/O of each group of I/Os and this register is only available on low-density devices.
11.4.22 I/O control mode register 4 (RI_IOCMR4)
Address offset: 0x26
Reset value: 0x00
7
CH28M rw
6
CH27M rw
5 4
Reserved
3 2 1
CH26M rw
0
CH29M rw
Bits 7:6 CHxM : I/O control mode
These bits are set and cleared by software to select how the I/O is controlled.
0: I/O x is controlled by the standard GPIO registers. The I/O x switch is directly controlled by the
RI_IOSR2 register.
1: I/O x is set to protected mode and is only controlled by the RI_IOSR2 and RI_IOGCR registers
(standard GPIO registers have no effect on the configuration of I/O x).
Bits 5:2 Reserved, must be kept cleared.
Bits 1:0 CHxM : I/O control mode
These bits are set and cleared by software to select how the I/O is controlled.
0: I/O x is controlled by the standard GPIO registers. The I/O x switch is directly controlled by the
RI_IOSR2 register.
1: I/O x is set to protected mode and is only controlled by the RI_IOSR2 and RI_IOGCR registers
(standard GPIO registers have no effect on the configuration of I/O x).
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Note: This register controls the fourth I/O of each group of I/Os and is only available on lowdensity devices.
11.4.23 I/O switch register 4 (RI_IOSR4)
Address offset: 0x27
Reset value: 0x00
7
CH28E rw
6
CH27E rw
5 4
Reserved
3 2 1
CH26E rw
0
CH29E rw
Bits 7:6 CHxE : I/O switch control
If the corresponding RI_IOCMRx bit is cleared:
These bits are set and cleared by software to open and close the I/O switches. If the I/O is used for the ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: I/O x switch is open (I/O x is controlled by the GPIO registers or ADC1).
1: I/O x switch is closed (analog channel enabled).
If the corresponding RI_IOCMRx bit is set and the AM bit is cleared in the RI_CR register
(software management of the charge transfer acquisition sequence ):
These bits are set and cleared by software. They define the configuration of the I/O.
0: I/O x is forced to output push-pull low mode.
1: I/O x configuration is determined by bit 6 and bit 7 in the RI_IOGCR register.
If the corresponding RI_IOCMRx bit is set and the AM bit is also set in the RI_CR register (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define if the corresponding I/O x state is controlled by the TIM2 timer.
0: I/O x is forced to output push-pull low mode
1: I/O x configuration determined by the timer TIM2
Bits 5:2 Reserved, must be kept cleared.
Bits 1:0 CHxE : I/O switch control
If the corresponding RI_IOCMRx bit is cleared:
These bits are set and cleared by software to open and close the I/O switches. If the I/O is used for the ADC1 input, the switch must be left open to allow the ADC1 to control it.
0: I/O x switch is open (I/O x is controlled by the GPIO registers or ADC1).
1: I/O x switch is closed (analog channel enabled).
If the corresponding RI_IOCMRx bit is set AND the AM bit is cleared in the RI_CR register
(software management of the charge transfer acquisition sequence ):
These bits are set and cleared by software. They define the configuration of the I/O.
0: I/O x is forced to output push-pull low mode.
1: I/O x configuration is determined by bit 6 and bit 7 in the RI_IOGCR register.
If the corresponding RI_IOCMRx bit is set and the AM is also set in the RI_CR register (hardware management of the charge transfer acquisition sequence):
These bits are set and cleared by software. They define if the corresponding I/O x state is controlled by the timer TIM2.
0: I/O x is forced to output push-pull low mode
1: I/O x configuration determined by the timer TIM2
Note: This register controls the fourth I/O of each group of I/Os.
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
Note: This register controls the fourth I/O of each group of I/Os and is only available on lowdensity devices.
11.4.24 RI register map and reset values
7
Table 29. Routing interface register map
6 5 4 3
Address offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x20
0x21
0x22
Register name
RI_IOSR1
Reset value
RI_IOSR2
Reset value
RI_IOSR3
Reset value
RI_IOGCR
Reset value
RI_ASCR1
Reset value
RI_ASCR2
Reset value
RI_RCR
Reset value
RI_CR
(4)
Reset value
Reset value
Reset value
Reserved
Reset value
RI_ICR1 (1)
Reset value
RI_ICR2
Reset value
RI_IOIR1
Reset value
RI_IOIR2
Reset value
RI_IOIR3
Reset value
RI_IOCMR1
Reset value
RI_IOCMR2
Reset value
RI_IOCMR3
Reset value
CH21M
0
CH19E
0
CH20E
0
CH21E
0
AS6
0
AS14
0
-
0
-
0
CH19M
0
CH20M
0
CH20I x
CH21I x
CH19M
0
CH20M
0
-
0
CH19I x
-
0
-
0
CH24M
0
CH22E
0
CH23E
0
CH24E
0
IOM41
(2)
1
AS7
0
-
0
-
0
-
0
CH22M
0
CH23M
0
CH23I x
CH24I x
CH22M
0
CH23M
0
-
0
-
0
-
0
CH22I x
CH12M
0
CH10E
0
CH11E
0
CH12E
0
IOM21
1
AS3
0
AS11
(3)
0
400KPD
0
CH11I x
CH12I x
CH10M
0
CH11M
0
-
0
IC2CS3
0
IC3CS3
0
CH10I x
THALT
0
CH10M
0
CH11M
0
IOM31
1
AS5
0
-
0
-
0
CH18M
0
CH16E
0
CH17E
0
CH18E
0
CH17I x
CH18I x
CH16M
0
CH17M
0
-
0
CH16I x
-
0
-
0
-
0
CH16M
0
CH17M
0
IOM30
1
AS4
0
-
0
-
0
CH15M
0
CH13E
0
CH14E
0
CH15E
0
CH14I x
CH15I x
CH13M
0
CH14M
0
-
0
IC2CS4
0
IC3CS4
0
CH13I x
-
0
CH13M
0
CH14M
0
2
CH9M
0
CH7E
0
CH8E
0
CH9E
0
IOM20
1
AS2
0
AS10
0
10KPD
0
CH8I x
CH9I x
CH7M
0
CH8M
0
-
0
IC2CS2
0
IC3CS2
0
CH7I x
AM
0
CH7M
0
CH8M
0
1
CH6M
0
CH4E
0
CH5E
0
CH6E
0
IOM11
1
AS1
0
0
400KPU
0
CH5I x
CH6I x
CH4M
0
CH5M
0
-
0
IC2CS1
0
IC3CS1
0
CH4I x
TIF
0
CH4M
0
CH5M
0
0
IOM10
1
AS0
0
AS8
0
10KPU
0
CH3M
0
CH1E
0
CH2E
0
CH3E
0
CH2I x
CH3I x
CH1M
0
CH2M
0
-
0
IC2CS0
0
IC3CS0
0
CH1I x
TIE
0
CH1M
0
CH2M
0
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Table 29. Routing interface register map (continued)
Address offset
0x23
0x24
0x25
0x26
0x27
Register name
Reset value
Reset value
RI_IOIR4
Reset value
Reset value
Reset value
7
CH24M
0
CH28M
0
CH28I x
CH28M
0
6
CH21M
0
CH27M
0
CH27I x
CH27M
0
5
CH18M
0
-
0
-
0
x
4
CH15M
0
-
0
-
0
x
3
CH12M
0
-
0
-
0
x
CH28E
0
CH27E
0
-
0
-
0
-
0
1. On medium, medium+ and high-density devices only.
2. These bits are available on low-density devices only. Reset values are 0 for the other devices.
3. On medium+ and high-density devices only.
4. On low-density devices only
2
-
0
x
CH9M
0
-
0
-
0
1
CH6M
0
CH26M
0
CH26I x
CH26M
0
CH26E
0
0
CH3M
0
CH29M
0
CH29I x
CH29M
0
CH29E
0
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG) RM0031
7
Address offset: 0x01
Reset value: 0x0C
6
SPI1_REMAP1 USART1CK_REMAP rw rw
5 4
USART1TR_REMAP[1:0] rw rw
3 2
TIM4DMA_REMAP[1:0] rw rw
Bit 7 SPI1_REMAP1 : SPI1 remapping
″
″
″
″
When this bit is reset:
″
″
″
″
SPI1_MIS0 is mapped on PB7
SPI1_MOSI is mapped on PB6
SPI1_SCK is mapped on PB5
SPI1_NSS is mapped on PB4
When this bit is set:
SPI1_MIS0 is mapped on PA2
SPI1_MOSI is mapped on PA3
SPI1_SCK is mapped on PC6
SPI1_NSS is mapped on PC5
Bit 6 USART1CK_REMAP : USART1_CK remapping
0: USART1_CK mapped on PC4
1: USART1_CK mapped on PA0
Bits 5:4 USART1TR_REMAP[1:0] : USART1_TX and USART1_RX remapping
00: USART1_TX on PC3 and USART1_RX on PC2
01: USART1_TX on PA2 and USART1_RX on PA3
10: USART1_TX on PC5 and USART1_RX on PC6
11: Reserved
Bits 3:2 TIM4DMA_REMAP[1:0] : TIM4 DMA channel remapping
00: TIM4 DMA request/acknowledge mapped on DMA1 channel 0
01: TIM4 DMA request/acknowledge mapped on DMA1 channel 1
10: TIM4 DMA request/acknowledge mapped on DMA1 channel 2
11: TIM4 DMA request/acknowledge mapped on DMA1 channel 3
Bits 1:0 ADC1DMA_REMAP[1:0] : ADC1 DMA channel remapping
00: ADC1 DMA request/acknowledge mapped on DMA1 channel 0
01: ADC1 DMA request/acknowledge mapped on DMA1 channel 1
10: ADC1 DMA request/acknowledge mapped on DMA1 channel 2
11: ADC1 DMA request/acknowledge mapped on DMA1 channel 3
1 0
ADC1DMA_REMAP[1:0] rw rw
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
7
TIM23BKIN_
REMAP
rw
Address offset: 0x02
Reset value: 0x00
6 5
TIM3TRIG_
REMAP2
rw
SPI2_REMAP
rw
4
TIM3TRIGLSE_
REMAP rw
3
TIM2TRIGLSE_
REMAP rw
2
TIM3TRIG_
REMAP1 rw
1
TIM2TRIG_
REMAP rw
0
ADC1TRIG_
REMAP rw
Bit 7
(1)
TIM23BKIN_REMAP : TIM2 break input and TIM3 break input remapping
0: TIM2_BKIN &TIM3_BKIN mapped on PA4 & PA5
1: TIM2_BKIN & TIM3_BKIN mapped on PG0 & PG1 (only on 64- and 80-pin packages)
TIM3TRIG_REMAP2 : TIM3 trigger remapping
0: TIM3_TRIG mapped on PD1 if TRIM3TRIG_REMAP1=0 or on PA5 if TRIM3TRIG_REMAP1=1
1: TIM3_TRIG mapped on PG3 (only on 64- and 80-pin packages)
SPI2_REMAP : SPI2 remapping
″
″
″
″
When this bit is reset:
″
″
″
″
SPI2_MIS0 is mapped on PG7
SPI2_MOSI is mapped on PG6
SPI2_SCK is mapped on PG5
SPI2_NSS is mapped on PG4
When this bit is set:
SPI2_MIS0 is mapped on PI3
SPI2_MOSI is mapped on PI2
SPI2_SCK is mapped on PI1
SPI2_NSS is mapped on PI0
Bit 4 TIM3TRIGLSE_REMAP : TIM3 trigger controlled by LSE
TIM3 trigger controlled by the LSE oscillator.
0: TIM3_TRIG mapped as defined in the TIM3TRIG_REMAP1 bit
1: TIM3_TRIG mapped on OSC32_IN (LSE oscillator input)
Note: When the TIM2TRIGLSE_REMAP or TIM3TRIGLSE_REMAP are set, the ETR prescaler of the corresponding timer must be set to have a ratio of at least 4 with respect to the selected system clock.
LSE needs to be properly switched on as defined in the CLK configuration registers.
Bit 3 TIM2TRIGLSE_REMAP : TIM2 trigger controlled by LSE
TIM2 trigger controlled by the LSE oscillator.
0: TIM2_TRIG mapped as defined in the TIM2TRIG_REMAP bit
1: TIM2_TRIG mapped on OSC32_IN (LSE oscillator input)
Note: When the TIM2TRIGLSE_REMAP or TIM3TRIGLSE_REMAP are set, the ETR prescaler of the corresponding timer must be set to have a ratio of at least 4 with respect to the selected system clock.
LSE needs to be properly switched on as defined in the CLK configuration registers.
RM0031 Rev 15
157
Routing interface (RI) and system configuration controller (SYSCFG)
Bit 2 TIM3TRIG_REMAP1 : TIM3 trigger remapping
0: TIM3_TRIG mapped on PD1
1: TIM3_TRIG mapped on PA5
Bit 1 TIM2TRIG_REMAP : TIM2 trigger remapping
0: TIM2_TRIG mapped on PB3
1: TIM2_TRIG mapped on PA4
Bit 0 ADC1TRIG_REMAP : ADC1 trigger remapping
0: ADC1_TRIG mapped on PA6
1: ADC1_TRIG mapped on PD0
1. These bits are reserved in low and medium-density devices.
RM0031
Note:
Address offset: 0x00
Reset value: 0x00
This register is available in low-density devices (with 20-pin packages), medium+ and highdensity devices only.
7
TIM2_CH2_RE
6
TIM2_CH1_RE
MAP
rw rw
5
CCO_REMAP rw
4
TIM3_CH2_
REMAP rw
3
TIM3_CH1_
REMAP rw
2
USART3CK_
REMAP rw
1
USART3TR_
REMAP rw
Bit 7
(1)
TIM2_CH2_REMAP TIM2 channel 2 remapping (20-pin package low-density devices only)
0: TIM2_CH2 is mapped on PB2
1: TIM2_CH2 is mapped on PC6
TIM2_CH1_REMAP TIM2 channel 1 remapping (20-pin package low-density devices only)
0: TIM2_CH1 is mapped on PB0
1: TIM2_CH1 is mapped on PC5
Bit 5 CCO_REMAP : Configurable clock output remapping
0: CCO mapped on PC4
1: CCO mapped on PE2
Bit 4 TIM3_CH2_REMAP : TIM3 channel 2 remapping
0: TIM3_CH2 mapped on PD0
1: TIM3_CH2 mapped on PI3 (80-pin packages only)
Bit 3 TIM3_CH1_REMAP : TIM3 channel 1 remapping
0: TIM3_CH1 mapped on PB1
1: TIM3_CH1 mapped on PI0 (80-pin packages only)
0
SPI1_REMAP2 rw
RM0031 Rev 15
RM0031 Routing interface (RI) and system configuration controller (SYSCFG)
Bit 2 USART3CK_REMAP : USART3_CK remapping
0: USART3_ CK mapped on PG2
1: USART3_CK mapped on PF2 (80-pin packages only)
Bit 1 USART3TR_REMAP : USART3_TX and USART3_RX remapping
0: USART3_TX mapped on PG1 and USART3_RX mapped on PG0
1: USART3_TX mapped on PF0 and USART3_RX mapped on PF1
Bit 0 SPI1_REMAP2 : SPI1 remapping (80-pin packages only)
″
″
″
″
When this bit is reset:
″
″
″
″
SPI1_MIS0 is mapped on PB7
SPI1_MOSI is mapped on PB6
SPI1_SCK is mapped on PB5
SPI1_NSS is mapped on PB4
When this bit is set:
SPI1_MIS0 is mapped on PF0
SPI1_MOSI is mapped on PF1
SPI1_SCK is mapped on PF2
SPI1_NSS is mapped on PF3
1. Available on low-density devices only. Reserved on medium and high-density devices.
Table 30. SYSCFG register map
Offset addres s
Register name
7 6 5 4 3 2 1 0
0x00
0x01
SYSCFG_
RMPCR3
Reset value
SYSCFG_
RMPCR1
Reset value
TIM2_CH2_RE
MAP
0 (1)
SPI1_
REMAP1
0
TIM2_CH1_
REMAP
CCO_
REMAP
0
TIM3_CH2_
REMAP
0
USART1CK_
REMAP
0
USART1TR_REMAP[1:0]
00
0x02
SYSCFG_
RMPCR2
Reset value
TIM23BKIN_
REMAP (2)
0
TIM3TRIG_
REMAP2
0
SPI2_
0
1.
On medium and high-density devices, bit 6and bit 7= reserved.
2.
On low, medium+ and high-density devices only.
TIM3TRIGL
SE_REMAP
0
TIM3_CH1_
REMAP
0
USART3CK
_REMAP
0
TIM4DMA_REMAP[1:0]
11
TIM2TRIGLSE
_REMAP
0
TIM3TRIG_
REMAP1
0
USART3TR
_REMAP
0
ADC1DMA_REMAP[1:0]
TIM2TRIG_
REMAP
0
00
SPI1_
REMAP2
0
ADC1TRIG_
REMAP
0
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Interrupt controller (ITC) RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density devices and high-density
STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
• Management of hardware interrupts
– External interrupt capability on all I/O pins with dedicated interrupt vector per port and dedicated flag per pin
– Peripheral interrupt capability
• Management of software interrupt (TRAP)
• Nested or concurrent interrupt management with flexible interrupt priority and level management:
– Up to 4 software programmable nesting levels
– Up to 32 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
• Up to 40 external interrupt sources on 11 vectors
This interrupt management is based on:
• Bit I1 and I0 of the CPU Condition Code register (CCR)
• Software priority registers (ITC_SPRx)
• Reset vector located at 0x00 8000 at the beginning of program memory. The Reset initialization routine is programmed in ROM by STMicroelectronics.
• Fixed interrupt vector addresses located at the high addresses of the memory map
(0x00 8004 to 0x00 807C) sorted by hardware priority order.
The interrupt masking is managed by bits I1 and I0 of the CCR register and by the
ITC_SPRx registers which set the software priority level of each interrupt vector (see
Table 31 ). The processing flow is shown in Figure 29
.
When an interrupt request has to be serviced:
1.
Normal processing is suspended at the end of the current instruction execution.
2. The PC, X,Y, A and CCR registers are saved onto the stack.
3. Bits I1 and I0 of CCR register are set according to the values in the ITC_SPRx registers corresponding to the serviced interrupt vector.
4. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched .
The interrupt service routine should end with the IRET instruction which causes the content of the saved registers to be recovered from the stack. As a consequence of the IRET instruction, bits I1 and I0 are restored from the stack and the program execution resumes.
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
Table 31. Software priority levels
Software priority Level
Level 0 (main)
Level 1
Level 2
Level 3 (= software priority disabled)
Low
High
Figure 29. Interrupt processing flowchart
I1
0
1
1
0
I0
0
1
0
1
RESET
PENDING
INTERRUPT
N
FETCH NEXT
INSTRUCTION
Y
Interrupt has the same or a lower software priority than current one
TRAP
Y
N
I1:0
THE INTERRUPT
STAYS PENDING
Y
« IRET »
N
RESTORE PC, X, Y, A, CCR
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, Y, A, CCR
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
MSv45260V1
Caution: If the interrupt mask bits I0 and I1 are set within an interrupt service routine (ISR) with the instruction SIM, removal of the interrupt mask with RIM causes the software priority to be set to level 0.
To restore the correct priority when disabling and enabling interrupts inside an ISR, follow the procedures presented in
Table 31 for disabling and enabling the interrupts.
12.2.1 Servicing pending interrupts
Several interrupts can be pending at the same time. The interrupt to be taken into account is determined by the following two-step process:
1.
The highest software priority interrupt is serviced.
2. If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.
Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.
2 RESET and TRAP are considered as having the highest software priority in the decision process.
See
for a description of pending interrupt servicing process.
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Interrupt controller (ITC)
Figure 30. Priority decision process
PENDING
INTERRUPTS
Same SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
RM0031
MSv45261V1
Two interrupt source types are managed by the STM8 interrupt controller:
• Non-maskable interrupts: RESET and TRAP
• Maskable interrupts: external interrupts or interrupts issued by internal peripherals
Non-maskable interrupt sources
Non-maskable interrupt sources are processed regardless of the state of bits I1 and I0 of the
CCR register (see
Figure 29 ). PC, X, Y, A and CCR registers are stacked only when a TRAP
interrupt occurs. The corresponding vector is then loaded in the PC register and bits I1 and
I0 of the CCR register are set to disable interrupts (level 3).
• TRAP (non-maskable software interrupt)
This software interrupt source is serviced when the TRAP instruction is executed. It is
serviced according to the flowchart shown in Figure 29 .
A TRAP interrupt does not allow the processor to exit from Halt mode.
• RESET
The RESET interrupt source has the highest STM8 software and hardware priorities.
This means that all the interrupts are disabled at the beginning of the reset routine.
They must be re-enabled by the RIM instruction (see Table 34: Dedicated interrupt instruction set
).
A RESET interrupt allows the processor to exit from Halt mode.
See RESET chapter for more details on RESET interrupt management.
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
Maskable interrupt sources
Maskable interrupt vector sources are serviced if the corresponding interrupt is enabled and if its own interrupt software priority in ITC_SPRx registers is higher than the one currently being serviced (I1 and I0 in CCR register). If one of these two conditions is not met, the interrupt is latched and remains pending.
• External interrupts
External interrupts can be used to wake up the MCU from Halt mode. The device sensitivity to external interrupts can be selected by software through the External
Interrupt Control registers (EXTI_CRx).
When several input pins connected to the same interrupt line are selected simultaneously, they are logically ORed.
When external level-triggered interrupts are latched, if the given level is still present at the end of the interrupt routine, the interrupt remains activated except if it has been inactivated in the routine.
• Peripheral interrupts
A few peripheral interrupts cause the MCU to wake up from Halt mode. See the interrupt vector table in the datasheet.
A peripheral interrupt occurs when a specific flag is set in the peripheral status register and the corresponding enable bit is set in the peripheral control register.
The standard sequence for clearing a peripheral interrupt performs an access to the status register followed by a read or write to an associated register. The clearing sequence resets the internal latch. A pending interrupt (that is an interrupt waiting to be serviced) is therefore lost when the clear sequence is executed.
All interrupts allow the processor to exit from Wait mode.
Only a Reset or an event allows the processor to exit from Low power wait mode. This mode is entered by executing a WFE instruction in Low power run mode. The wakeup by an event makes the system go back to Low power run mode (refer to for more details).
Only external and other specific interrupts allow the processor to exit from Halt and Activehalt mode (see wakeup from halt and wakeup from Active-halt in the interrupt vector table in the datasheet).
When several pending interrupts are present while waking up from Halt mode, the first interrupt serviced can only be an interrupt with exit-from-Halt mode capability. It is selected
through the decision process shown in Figure 30
. If the highest priority pending interrupt cannot wake up the device from Halt mode, it will be serviced next.
If any internal or external interrupt (from a timer for example) occurs while the HALT instruction is executing, the HALT instruction is completed but the interrupt invokes the wakeup process immediately after the HALT instruction has finished executing. In this case the MCU is actually waking up from Halt mode to Run mode, with the corresponding delay of t
WUH
as specified in the datasheet.
Before executing the HALT instruction, the user program must clear any pending peripheral interrupts (clear interrupt pending bit in the corresponding peripheral configuration registers). Otherwise, the HALT instruction is not executed and program execution continues.
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Interrupt controller (ITC) RM0031
12.4 Activation level/low power mode control
The MCU activation level is configured by programming the AL bit in the CFG_GCR register
(see global configuration register (CFG_GCR)).
This bit is used to control the low power modes of the MCU. In very low power applications, the MCU spends most of the time in WFI/Halt mode and is woken up (through interrupts) at specific moments in order to execute a specific task. Some of these recurring tasks are short enough to be treated directly in an ISR (interrupt service routine), rather than going back to the main program. To cover this case, you can set the AL bit before entering Low power mode (by executing WFI/HALT instruction). Consequently, the interrupt routine causes the device to return to low power mode., then the interrupt routine returns directly to
Low power mode. The run time/ISR execution is reduced due to the fact that the register context is saved only on the first interrupt.
As a consequence, all the operations can be executed in ISR in very simple applications. In more complex ones, an interrupt routine may relaunch the main program by simply resetting the AL bit.
For example, an application may need to be woken up by the auto-wakeup unit (AWU) every 50 ms in order to check the status of some pins/sensors/push-buttons. Most of the time, as these pins are not active, the MCU can return to Low power mode without running the main program. If one of these pins is active, the ISR decides to launch the main program by resetting the AL bit.
STM8 devices feature two interrupt management modes:
• Concurrent mode
• Nested mode
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
In this mode, all interrupts are interrupt priority level 3 so that none of them can be interrupted, except by a RESET, or TRAP.
The hardware priority is given in the following order from the lowest to the highest priority, that is: MAIN, IT4, IT3, IT2, IT1, IT0, TRAP (same priority), and RESET.
shows an example of concurrent interrupt management mode.
Figure 31. Concurrent interrupt management
Software priority level
I1 I0
RIM
Main
11/10
IT2
IT1
TRAP
IT1
IT0
IT3
IT4
10
Main
3
3
3
3
3
3
3/0
1 1
1 1
1 1
1 1
1 1
1 1
MSv47717V2
12.5.2 Nested interrupt management mode
In this mode, interrupts are allowed during interrupt routines. This mode is activated as soon as an interrupt priority level lower than level 3 is set.
The hardware priority is given in the following order from the lowest to the highest priority, that is: MAIN, IT4, IT3, IT2, IT1, IT0, and TRAP.
The software priority is configured for each interrupt vector by setting the corresponding
I1_x and I0_x bits of the ITC_SPRx register. I1_x and I0_x bits have the same meaning as
I1 and I0 bits of the CCR register (see
Level 0 can not be programmed (I1_x=1, I0_x=0). In this case, the previously stored value is kept. For example: if previous value is 0xCF, and programmed value equals 64h, the result is 44h.
The RESET and TRAP vectors have no software priorities. When one is serviced, bits I1 and I0 of the CCR register are both set.
Caution: If bits I1_x and I0_x are modified while the interrupt x is executed, the device operates as follows: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, then the interrupt x is re-entered.
Otherwise, the software priority remains unchanged till the next interrupt request (after the
IRET of the interrupt x).
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority till the next IRET instruction or one of the
previously mentioned instructions is issued. See Section 12.7
interrupt instructions.
RM0031 Rev 15
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Interrupt controller (ITC)
shows an example of nested interrupt management mode.
RM0031
Warning: A stack overflow may occur without notifying the software of the failure.
Table 32. Vector address map versus software priority bits
Vector address ITC_SPRx bits
0x00 8008h
0x00 800Ch
...
0x00 807Ch
I1_0 and I0_0 bits
I1_1 and I0_1 bits
...
I1_29 and I0_29 bits
Figure 32. Nested interrupt management
RIM
Main
11/10
IT2
IT1
IT4
TRAP
IT4
IT0
IT3
IT1
IT2
Software priority level
I1
10
Main
I0
3
3
3
3
2
1
3/0
1 1
1 1
0 0
0 1
1 1
1 1
MSv47718V2
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
Note:
Eleven interrupt vectors are dedicated to external Interrupt events:
• EXTIB/G - 8 lines on Port B or G: PB[7:0] or PG[7:0]EXTID/H - 8 lines on Port D or H:
PD[7:0] or PH[7:0]
• EXTIE/F - 8 lines on Port E or F: PE[7:0] or PF[7:0]
• EXTI0 - 6 lines on Port A/B/C/D/E/F, bit 0: Px[0]
• EXTI1 - 5 lines on Port A/B/C/D/E, bit 1: Px[1]
• EXTI2 - 5 lines on Port A/B/C/D/E, bit 2: Px[2]
• EXTI3 - 5 lines on Port A/B/C/D/E, bit 3: Px[3]
• EXTI4 - 5 lines on Port A/B/C/D/E, bit 4: Px[4]
• EXTI5 - 5 lines on Port A/B/C/D/E, bit 5: Px[5]
• EXTI6 - 5 lines on Port A/B/C/D/E, bit 6: Px[6]
• EXTI7 - 5 lines on Port A/B/C/D/E, bit 7: Px[7]
Ports G, H and I are available on medium+ and high-density devices only.
To generate an interrupt, the corresponding GPIO port must be configured in input mode with interrupts enabled. Refer to the register description in the GPIO chapter for details.
When an external interrupt occurs, the corresponding bit is set in the EXTI_SRx status register. This indicates a pending interrupt. Clearing this bit, writing a 1 in it, clears the corresponding pending external interrupt.
The interrupt sensitivity must be configured in the external interrupt control register 1
(EXTI_CR1), external interrupt control register 2 (EXTI_CR2), and external interrupt control register 3 (EXTI_CR3) (see
Table 33. External interrupt sensitivity
GPIO port
EXTI0 to EXTI3 on port A, B, C,
D, E and F
EXTI4 to EXTI7 of port A, B, C,
D and E
EXTIE and EXITF
Interrupt sensitivity
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
Configuration register
EXTI_CR1
EXTI_CR2
EXTI_CR3
Instruction
HALT
IRET
JRM
JRNM
Table 34 shows the interrupt instructions.
Table 34. Dedicated interrupt instruction set
New description Function/example I1
Entering Halt mode
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
-
Pop CCR, A, X, Y, PC
I1:0=11 ?
I1:0<>11 ?
1
I1
-
-
H I0 N
0
H I0
-
-
-
N
-
-
Z
-
Z
-
-
C
-
C
-
-
RM0031 Rev 15
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Interrupt controller (ITC)
Instruction
POP CC
PUSH CC
RIM
SIM
TRAP
WFI
WFE
RM0031
Table 34. Dedicated interrupt instruction set (continued)
New description Function/example I1 H I0 N
Pop CCR from the stack
Push CC on the stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Wait for interrupt
Wait for event
Memory => CCR
CC =>Memory
Load 10 in I1:0 of CCR
Load 11 in I1:0 of CCR
Software NMI
-
-
1
1
1
1
1
I1
-
-
-
-
-
-
H I0 N
-
0
1 -
-
1
0
0
-
-
-
C
-
-
-
-
-
C
-
Z
-
-
-
-
-
Z
-
Refer to the corresponding device datasheet for the table of interrupt vector addresses.
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
12.9 ITC and EXTI registers
12.9.1 CPU condition code register interrupt bits (CCR)
Address: refer to the general hardware register map table in the datasheet.
Reset value: 0x28
7
V r
6
– r
5
I1 rw
4
H r
3
I0 rw
2
N r
1
Z r
0
C r
Bits 5, 3
(1)
I[1:0]: Software interrupt priority bits
(2)
These two bits indicate the software priority of the current interrupt request. When an interrupt request occurs, the software priority of the corresponding vector is loaded automatically from the software priority registers (ITC_SPRx).
The I[1:0] bits can be also set/cleared by software using the RIM, SIM, HALT, WFI, IRET or
PUSH/POP instructions (see Figure 32: Nested interrupt management ).
I1 I0 Priority Level
1
0
0
0
1
0
Level 0 (main)
Level 1
Level 2
1 1 Level 3 (= software priority disabled*)
1. Refer to the central processing section for details on the other CCR bits.
2. TRAP and RESET events can interrupt a level-3 program.
Low
High
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Interrupt controller (ITC) RM0031
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Address offset: 0x00 to 0x07
Reset value: 0xFF
7
VECT3SPR[1:0]
6
VECT7SPR[1:0]
VECT11SPR[1:0]
VECT15SPR[1:0]
VECT19SPR[1:0]
VECT23SPR[1:0]
VECT27SPR[1:0]
Reserved rw
5
VECT2SPR[1:0]
4
VECT6SPR[1:0]
VECT10SPR[1:0]
VECT14SPR[1:0]
VECT18SPR[1:0]
VECT22SPR[1:0]
VECT26SPR[1:0]
3
VECT1SPR[1:0]
2
VECT5SPR[1:0]
VECT9SPR[1:0]
VECT13SPR[1:0]
VECT17SPR[1:0]
VECT21SPR[1:0]
VECT25SPR[1:0]
VECT29SPR[1:0] rw rw
1
VECT0SPR[1:0]
0
VECT4SPR[1:0]
VECT8SPR[1:0]
VECT12SPR[1:0]
VECT16SPR[1:0]
VECT20SPR[1:0]
VECT24SPR[1:0]
VECT28SPR[1:0] rw rw
Bits 7:0 VECTxSPR[1:0]: Vector x software priority bits
These eight read/write registers (ITC_SPR1 to ITC_SPR8) are written by software to define the software priority of each interrupt vector.
The list of vectors is given in
Table 32: Vector address map versus software priority bits
.
Refer to Section 12.9.1: CPU condition code register interrupt bits (CCR) for the values to be
programmed for each priority.
Reserved
ITC_SPR8 bits 7:4 are forced to 1 by hardware.
Note: It is forbidden to write 10 (priority level 0). If 10 is written, the previous value is kept and the interrupt priority remains unchanged.
12.9.3 External interrupt control register 1 (EXTI_CR1)
Address offset: 0x00
Reset value: 0x00
7 6 5 4 3 2
P3IS[1:0] rw
P2IS[1:0] rw
P1IS[1:0] rw
1
P0IS[1:0] rw
0
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
Bits 7:6 P3IS[1:0]: Portx bit 3 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of bit 3 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 5:4 P2IS[1:0]: Portx bit 2 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of bit 2 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 3:2 P1IS[1:0]: Portx bit 1 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of bit 1 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 1:0 P0IS[1:0]: Portx bit 0 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of bit 0 of Port A, B, C, D, E and/or F external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
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Interrupt controller (ITC) RM0031
12.9.4 External interrupt control register 2 (EXTI_CR2)
Address offset: 0x01
Reset value: 0x00
7 6 5 4 3 2
P7IS[1:0] rw
P6IS[1:0] rw
P5IS[1:0] rw
1 0
P4IS[1:0] rw
Bits 7:6 P7IS[1:0]: Portx bit 7 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the bit 7 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 5:4 P6IS[1:0]: Portx bit 6 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the bit 6 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 3:2 P5IS[1:0]: Portx bit 5 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the bit 5 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 1:0 P4IS[1:0]: Portx bit 4 external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the bit 4 of Port A, B, C, D and/or E external interrupts.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
12.9.5 External interrupt control register 3 (EXTI_CR3)
Address offset: 0x02
Reset value: 0x00
7 6 5 4 3 2
PFIS[1:0] rw
PEIS[1:0] rw
PDIS[1:0] rw
1 0
PBIS[1:0] rw
Bits 7:6 PFIS[1:0]: Port F external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port F external interrupts, when EXTIF for Port F[3:0] and/or Port F[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 5:4 PEIS[1:0]: Port E external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port E external interrupts, when EXTIE for Port E[3:0] and/or Port E[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 3:2 PDIS[1:0]: Port D external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port D external interrupts, when EXTID for Port D[3:0] and/or Port D[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 1:0 PBIS[1:0]: Port B external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port B external interrupts, when EXTIB for Port B[3:0] and/or PortB[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
RM0031 Rev 15
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Interrupt controller (ITC) RM0031
12.9.6 External interrupt control register 4 (EXTI_CR4)
Note:
Address offset: 0x0A
Reset value: 0x00
This register is available in medium+ and high-density devices only
7 6 5 4 3 2
Reserved
PHIS[1:0] rw
1 0
PGIS[1:0] rw
Bits 7:4 Reserved.
Bits 3:2 PHIS[1:0]: Port H external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port H external interrupts, when EXTIH for Port H[3:0] and/or Port H[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
Bits 1:0 PGIS[1:0]: Port G external interrupt sensitivity bits
These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of the Port G external interrupts, when EXTIG for Port G[3:0] and/or Port G[7:4] is enabled.
00: Falling edge and low level
01: Rising edge only
10: Falling edge only
11: Rising and falling edge
12.9.7 External interrupt status register 1 (EXTI_SR1)
Address offset: 0x03
Reset value: 0x00
7
P7F rc_w1
6
P6F rc_w1
5
P5F rc_w1
4
P4F rc_w1
3
P3F rc_w1
2
P2F rc_w1
1
P1F rc_w1
0
P0F rc_w1
Bits 7:0 PxF: Port A/B/C/D/E/F bit x external interrupt flag
These bits are set by hardware when an interrupt event occurs on the corresponding pin.They are cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
12.9.8 External interrupt status register 2 (EXTI_SR2)
Address offset: 0x04
Reset value: 0x00
7
Reserved
6 5
rc_w1
4
rc_w1
3
PFF rc_w1
2
PEF rc_w1
1
PDF rc_w1
0
PBF rc_w1
Bits 7:6 Reserved.
Bit 5
(1)
PHF: Port H external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin. It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
Bit 4
PGF: Port G external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin.It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
Bit 3 PFF: Port F external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin. It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
Bit 2 PEF: Port E external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin.It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
Bit 1 PDF: Port D external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin. It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
Bit 0 PBF: Port B external interrupt flag
This bit is set by hardware when an interrupt event occurs on the corresponding pin.It is cleared by writing a ‘1’ by software.
0: No interrupt
1: External interrupt pending
1. This bit is available in medium+ and high-density devices only. It is reserved in medium-density devices.
12.9.9 External interrupt port select register (EXTI_CONF1)
Address offset: 0x05
Reset value: 0x00
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Interrupt controller (ITC)
7
PFES rw
6
PFLIS rw
5
PEHIS rw
4
PELIS rw
3
PDHIS rw
Bit 7 PFES: Port F or port E external interrupt select
0: Port E is used for interrupt generation
1: Port F is used for interrupt generation
Bit 6 PFLIS: Port F[3:0] external interrupt select
It selects pins PF[3:0] for EXTIF interrupt.
0: PF[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PF[3:0] are used for EXTIF interrupt generation
Bit 5 PEHIS: Port E[7:4] external interrupt select
It selects pins PE[7:4] for EXTIE interrupt.
0: PE[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PE[7:4] are used for EXTIE interrupt generation
Bit 4 PELIS: Port E[3:0] external interrupt select
It selects pins PE[3:0] for EXTIE interrupt.
0: PE[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PE[3:0] are used for EXTIE interrupt generation
Bit 3 PDHIS: Port D[7:4] external interrupt select
It selects pins PD[7:4] for EXTID interrupt.
0: PD[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PD[7:4] are used for EXTID interrupt generation
Bit 2 PDLIS: Port D[3:0] external interrupt select
It selects pins PD[3:0] for EXTID interrupt.
0: PD[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PD[3:0] are used for EXTID interrupt generation
Bit 1 PBHIS: Port B[7:4] external interrupt select
It selects pins PB[7:4] for EXTIB interrupt.
0: PB[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PB[7:4] are used for EXTIB interrupt generation
Bit 0 PBLIS: Port B[3:0] external interrupt select
It selects pins PB[3:0] for EXTIB interrupt.
0: PB[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PB[3:0] are used for EXTIB interrupt generation
2
PDLIS rw
1
PBHIS rw
RM0031
0
PBLIS rw
RM0031 Rev 15
RM0031 Interrupt controller (ITC)
12.9.10 External interrupt port select register (EXTI_CONF2)
Note:
Address offset: 0x0B
Reset value: 0x00
This register is available in medium+ and high-density devices only
7
Reserved rw
6
PHDS rw
5
PGBS rw
4
PHHIS rw
3
PHLIS rw
Bit 7 Reserved
Bit 6 PHDS: Port H or port D external interrupt select
0: Port D is used for interrupt generation
1: Port H is used for interrupt generation
Bit 5 PGBS: Port G or port B external interrupt select
0: Port B is used for interrupt generation
1: Port G is used for interrupt generation
Bit 4 PHHIS: Port H[7:4] external interrupt select
It selects pins PH[7:4] for EXTIH interrupt.
0: PH[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PH[7:4] are used for EXTIH interrupt generation
Bit 3 PHLIS: Port H[3:0] external interrupt select
It selects pins PH[3:0] for EXTIH interrupt.
0: PH[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PH[3:0] are used for EXTIH interrupt generation
Bit 2 PGHIS: Port G[7:4] external interrupt select
It selects pins PG[7:4] for EXTIG interrupt.
0: PG[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PG[7:4] are used for EXTIG interrupt generation
Bit 1 PGLIS: Port G[3:0] external interrupt select
It selects pins PG[3:0] for EXTIG interrupt.
0: PG[3:0] are used for EXTI3-EXTI0 interrupt generation
1: PG[3:0] are used for EXTIG interrupt generation
Bit 0 PFHIS: Port F[7:4] external interrupt select
It selects pins PF[7:4] for EXTIF interrupt.
0: PF[7:4] are used for EXTI7-EXTI4 interrupt generation
1: PF[7:4] are used for EXTIF interrupt generation
2
PGHIS rw
1
PGLIS rw
0
PFHIS rw
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Interrupt controller (ITC) RM0031
12.9.11 ITC and EXTI register map and reset values
7
Table 35. ITC and EXTI register map
6 5 4 3
Add. offset
Register name
ITC-SPR block
(1)
ITC_SPR1
0x00
Reset value
ITC_SPR2
0x01
Reset value
ITC_SPR3
0x02
Reset value
ITC_SPR4
0x03
Reset value
ITC_SPR5
0x04
Reset value
ITC_SPR6
0x05
Reset value
ITC_SPR7
0x06
Reset value
ITC_SPR8
0x07
Reset value
ITC-EXTI block (2)
0x00
0x01
0x02
0x03
0x04
0x05
EXTI_CR1
Reset value
EXTI_CR2
Reset value
EXTI_CR3
Reset value
EXTI_SR1
Reset value
EXTI_SR2
Reset value
EXTI_CONF1
Reset value
0x06 to
0x09
VECT17
SPR1
1
VECT22
SPR1
1
VECT26
SPR1
1
-
VECT2
SPR1
1
VECT6
SPR1
1
VECT10
SPR1
1
VECT14
SPR1
1
1
VECT19
SPR0
1
VECT23
SPR0
1
VECT27
SPR0
1
-
VECT3
SPR0
1
VECT7
SPR0
1
VECT11
SPR0
1
VECT15
SPR0
1
1
VECT19
SPR1
1
VECT23
SPR1
1
VECT27
SPR1
1
-
VECT3
SPR1
1
VECT7
SPR1
1
VECT11
SPR1
1
VECT15
SPR1
1
1
P3IS1
0
P7IS1
0
PFIS1
0
P7F
0
-
0
PFES
0
P3IS0
0
P7IS0
0
PFIS0
0
P6F
0
-
0
PFLIS
0
P2IS1
0
P6IS1
0
PEIS1
0
P5F
0
-
0
PEHIS
0
Reserved area
P2IS0
0
P6IS0
0
PEIS0
0
P4F
0
-
0
PELIS
0
P1IS1
0
P5IS1
0
PDIS1
0
P3F
0
PFF
0
PDHIS
0
VECT17
SPR1
1
VECT21
SPR1
1
VECT25
SPR1
1
VECT29
SPR1
1
VECT1
SPR1
1
VECT5
SPR1
1
VECT9
SPR1
1
VECT13
SPR1
1
VECT17
SPR1
1
VECT22
SPR0
1
VECT26
SPR0
1
-
VECT2
SPR0
1
VECT6
SPR0
1
VECT10
SPR0
1
VECT14
SPR0
1
1
2
VECT17
SPR1
1
VECT21
SPR0
1
VECT25
SPR0
1
VECT29
SPR0
1
VECT1
SPR0
1
VECT5
SPR0
1
VECT9
SPR0
1
VECT13
SPR0
1
P1IS0
0
P5IS0
0
PDIS0
0
P2F
0
PEF
0
PDLIS
0
1
P0IS1
0
P4IS1
0
PBIS1
0
P1F
0
0
PBHIS
0
0
VECT16
SPR0
1
VECT20
SPR0
1
VECT24
SPR0
1
VECT28
SPR0
1
VECT0
SPR0
1
VECT4
SPR0
1
VECT8
SPR0
1
VECT12
SPR0
1
VECT16
SPR1
1
VECT20
SPR1
1
VECT24
SPR0
1
VECT28
SPR1
1
VECT0
SPR1
1
VECT4
SPR1
1
VECT8
SPR1
1
VECT12
SPR1
1
P0IS0
0
P4IS0
0
PBIS0
0
P0F
0
PBF
0
PBLIS
0
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RM0031 Interrupt controller (ITC)
Table 35. ITC and EXTI register map (continued)
Add. offset
0x0A
(3)
Register name
Reset value
Reset value
7
-
0
-
0
6
-
0
PHDS
0
5
-
0
PGBS
0
4
-
0
PHHIS
0
3
PHIS1
0
PHLIS
0
2
PHIS0
0
PGHIS
0
1
PGIS1
0
PGLIS
0
0
PGIS0
0
PFHIS
0
1. The address offsets are expressed for the ITC-SPR block base address (see Table CPU/SWIM/debug module/interrupt controller registers in the datasheet).
2. The address offsets are expressed for the ITC-EXTI block base address (see Table General hardware register map in the datasheet).
3. These registers are available in medium+ and high-density devices only.
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Direct memory access controller (DMA)
13 Direct memory access controller (DMA)
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory as well as between memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has 4 channels. Each channel is dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.
Glossary
The term DMA refers to direct memory access.
A DMA transaction consists of a complete DMA read/write operation on a set of softwareprogrammable data blocks . A DMA transaction can be divided into single DMA transfers.
A DMA transfer consists of a single read/write operation on a data block. It cannot be interrupted.
A data block is either an 8-bit or a 16-bit data depending on the selected transfer size.
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RM0031 Direct memory access controller (DMA)
13.2 DMA main features
•
)
• Data transfers from peripherals to memory, from memory to peripherals and from memory to memory
• Hardware/software arbitration between each channel depending on the priority level
• Programmable number of “data to be transferred” : up to 255 data block (byte or word) transactions
• Incrementing and decrementing addressing mode
• Channel priority programmable by hardware and software
• Optional interrupt on Half transaction and End of transaction
• Two transfer sizes supported (8-bit and 16-bit data), programmable by software
• Priorities between requests from channels: they can be software-programmable (4 levels consisting of very high, high, medium, low ) or hardware-programmable in case of equality (request 1 has priority over request 2, etc.).
• Software trigger also supported by memory channels depending on the hardware configuration (memory channel).
• 2 flags (DMA Half transfer, DMA Transfer complete) logically ORed together in a single interrupt request for each channel
• Circular buffer management (auto-reload mode)
• Capability to suspend and resume a DMA transfer.
• Capability to operate in low power modes (Wait for interrupt or Wait for event)
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Direct memory access controller (DMA)
Figure 33. DMA block diagram
PROGRAM
MEMORY
RAM
PROGRAM BUS
RAM BUS
DMA REQUEST 0
DMA REQUEST 1
DMA REQUEST 2
DMA REQUEST 3
DMA
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
ARBITER
DMA BUS
PERIPHERAL 0 PERIPHERAL 1
SLAVE
PERIPHERAL BUS
RM0031
STM8 CORE
13.3 DMA functional description
The DMA controller performs direct memory transfer by sharing the address and data bus with the STM8™ core. The DMA request may stop the CPU access to the bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral).
The arbitration is performed inside the STM8™ core and is managed in a different way depending on the chosen bus (peripheral bus, RAM bus or program bus). Refer to the
STM8 core description for further information.
Besides, the DMA controller can signal to the STM8 core that the current access must have priority over the CPU. There are two ways to do this:
• the application can specify the timeout duration (number of wait cycles starting from the last request) by configuring the TO[5:0] bits in the DMA_GCSR register. Then the DMA waits until this timeout has elapsed before requesting from the core a high priority access to the bus.
• the application can also program a channel so that it always takes priority over the
CPU.
After an event, the peripheral sends a request signal to the DMA controller. The DMA controller serves the request depending on channel priorities. As soon as the DMA controller accesses the peripheral, an Acknowledge (one cycle pulse) is sent to the
RM0031 Rev 15
RM0031 Direct memory access controller (DMA) peripheral by the DMA controller. If the peripheral has no other pending request, it releases its request signal as soon as it gets the Acknowledge from the DMA controller.
Note:
The arbiter manages the channel requests based on their priority and it launches the peripheral/memory access sequences.
The priorities are managed in two stages:
• Software: each channel priority can be configured in the DMA_CxSPR register. There are four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
• Hardware: if 2 requests have the same software priority level, the channel with the lowest number gets priority versus the channel with the highest number. For example, channel 1 gets priority over channel 3.
Each DMA request is stored into a queue and is served when all requests with higher priority inside the sequence are completed.
A channel with a very high priority takes also priority over the CPU.
Note:
Four channels are available: three regular channels (channel 0, channel 1 and channel 2) and one memory channel (channel 3).
• The regular channels handle DMA transfers between a peripheral register located at a fixed address and a memory area addressed by an auto-increment/decrement pointer.
• The memory channel is a regular channel that can also handle data transfer between two memory areas managed by two memory pointers.
When the channel is configured for a memory transfer, DMA requests are ignored and the transfer is triggered through software: the transaction from memory area 0 to memory area
1 starts as soon as the channel is enabled and stops once the total number of bytes has been transferred.
The amount of data to be transferred (up to 255) is programmable depending on the value in the DMA_CxNDTR register. The DMA_CxNDTR register, which contains the amount of data items to be transferred, is decremented after each transfer.
Programmable data size
Transfer data size (8-bit or 16-bit) is user programmable through the TSIZE bit in the
DMA_CxSPR register.
When operating in 16-bit mode, the system handles big-endian addressing in both increment or decrement modes. The destination and source pointers must contain the address of the MSB (even address).
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Direct memory access controller (DMA)
Figure 34. Endianess in 16-bit mode
RM0031
Note:
0x0005 DATA3 LSB
0x0004 DATA3 MSB
0x0003 DATA1 LSB
0x0002 DATA1 MSB
0x0001 DATA0 LSB
0x0000 DATA0 MSB
MINCDEC = 1
0x00FB DATA3 LSB
0x00FA DATA3 MSB
0x00FD DATA1 LSB
0x00FC DATA1 MSB
0x00FF DATA0 LSB
0x00FE DATA0 MSB
MINCDEC = 0
When configured for 16-bit data transfer (TSIZE = 1), a transfer consists of four consecutive
8-bit read and write operations:
• Read the MSB from the source at even address
• Read the LSB from the source at odd address
• Write the MSB to the destination at even address
• Write the LSB to the destination at odd address
To ensure data coherence, the two read operations as well as the two write operations are not divisible.
This does not prevent the software from synchronizing the CPU and the DMA 16-bit accesses: the software must make sure the DMA will not read the 16-bit data while the CPU has only written half of the 16-bit data to the source area. In the same way, the software must make sure the DMA will not write the 16-bit data while the CPU has already started to read half of the 16-bit data.
The initial value address alignment is handled by software.
Pointer incrementation
During a memory-to-peripheral or a peripheral-to-memory transaction, the memory pointer is automatically post-incremented or post-decremented after each transaction depending on the MINCDEC bit in the DMA_CxCR register while the peripheral pointer is always fixed.
If incremented mode is enabled, the address of the next transfer is the address of the previous one incremented by 1. The first transfer address is the address programmed in the
DMA_CxPARH/L and DMA_CxM0ARH/L registers in medium-density devices and in the
DMA_CxPARH/L, DMA_CxM0ARH/L and DMA_C3M0EAR (for channel 3) registers in medium+ and high-density devices.
If the transfer data size is programmed to 16-bit mode (TSIZE = 1), the address is incremented/decremented by 1 after each byte transfer (by 2 after the two byte transfers).
If the channel is configured in non-circular mode, no DMA request is served after the end of the transfer (that is, once the number of data to be transferred reaches zero).
Channel configuration procedure
The following sequence should be followed to configure a DMA channel x (where x is the channel number):
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RM0031 Direct memory access controller (DMA)
1.
Set the peripheral register address in the DMA_CxPARL/H registers. The data is then moved from (or to) this address to (or from) the memory after the peripheral event.
2. Set the memory address in the DMA_CxPARH/L and DMA_CxM0ARH/L registers in medium-density devices and in the DMA_CxPARH/L, DMA_CxM0ARH/L and
DMA_C3M0EAR (for channel 3) registers in medium+ and high-density devices. The data is then written to or read from this memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CxNDTR register.
After each peripheral event, this value is then decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CxSPR register.
5. Configure data transfer direction, circular mode, memory incremented mode, transfer data size, and interrupt after half and/or full transfer in the DMA_CxCR register.
6. Activate the channel by setting the EN bit (Channel enable bit) in the DMA_CxCR register.
7. Once all channels are correctly configured (steps 1 to 6), it is possible to enable the
DMA through the GEN bit (Global enable bit) in the DMA_GCSR register.
As soon as the channels are enabled, they can serve any DMA request from the peripherals connected with them.
Once half of the bytes are transferred, the HTIF bit (Half-transfer interrupt flag) is set and an interrupt is generated if the HTIE bit (Half-transfer interrupt enable) is set. At the end of the transfer, the TCIF bit (Transfer complete interrupt flag) is set and an interrupt is generated if the TCIE bit (Transfer complete interrupt enable) is set.
Circular mode (auto-reload mode)
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit (circular buffer mode bit) in the
DMA_CxCR register.
When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.
Memory-to-memory mode
This mode is available only for channel 3 which is a memory channel.
Channel 3 can also handle data transfers between two memories, without being triggered by a request from a peripheral. This mode is called Memory to Memory mode.
If the MEM bit in the DMA_C3CR register is set, then the channel initiates transfers as soon as it is enabled by software by setting the EN bit (Channel enable bit) in the DMA_C3CR.
Peripheral requests are ignored.
The transfer stops once the DMA_C3NDTR register reaches zero.
Memory-to-memory mode must not be used at the same time as Circular mode.
When the channel is configured in memory-to-memory mode:
• the Auto-reload mode is disabled and the CIRC bit in the DMA_C3CR register is “don’t care”.
• the DIR bit (Data transfer direction bit) in the DMA_C3CR register is “don’t care”: the source is always the memory pointer address 0 (DMA_CxPARH/L and
DMA_CxM0ARH/L registers in medium-density devices and DMA_CxPARH/L,
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Direct memory access controller (DMA) RM0031
DMA_CxM0ARH/L and DMA_C3M0EAR registers in high-density devives) and the destination is always the memory pointer address 1 (DMA_C3PARL_C3M1ARL and
DMA_C3PARH_C3M1ARH registers).
• the source pointer address 0 is always incremented while the destination pointer address 1 is incremented or decremented depending on the MINCDEC bit in the
DMA_C3CR register.
Source and destination addresses
Channels 0, 1 and 2 can only address peripherals with addresses comprised between
0x5200 and 0x53FF, or within RAM memory (addresses comprised between 0x0000 and
0x07FF for medium-density devices and between 0x0000 and 0xFFFF for medium+ and high-density devices).
Figure 35. Regular channel (medium-density devices)
0xFFFF 0xFFFF
PERIPHERAL
SPACE
0x53FF
0x5200
DMA TRANSACTION
DIR=0
DMA TRANSACTION
DIR=1
0x0000
0x07FF
0x0000
Figure 36. Regular channel (medium+ and high-density devices)
0x17FFF 0x17FFF
MEMORY
SPACE
(RAM)
PERIPHERAL
SPACE
0x53FF
0x5200
DMA TRANSACTION
DIR=0
DMA TRANSACTION
DIR=1
0x0000
0x0FFF
0x0000
Channel 3, which is a memory channel, can address more memory space:
• When performing peripheral-to-memory or memory-to-peripheral transactions
(MEM=0), the memory address is comprised between 0x0000 and 0xFFFF for
MEMORY
SPACE
(RAM)
RM0031 Rev 15
RM0031 Direct memory access controller (DMA) medium-density devices and between 0x0000 and 0x17FFF for medium+ and highdensity devices, the peripheral address is comprised between 0x4000 and 0x5FFF.
• When performing memory-to-memory transactions (MEM=1), the source memory address is comprised between 0x0000 and 0xFFFF for medium-density devices and between 0x0000 and 0x17FFF for medium+ and high-density devices while the destination memory address is comprised between 0x0000 and 0x1FFF (which includes the Data EEPROM).
Figure 37. Memory channel with MEM=0 (medium-density devices)
0xFFFF 0xFFFF
PERIPHERAL
SPACE
0x5FFF
0x4000
DMA TRANSACTION
DIR=0
MEM=0
DMA TRANSACTION
DIR=1
MEM=0
MEMORY
SPACE
0x0000 0x0000
Figure 38. Memory channel with MEM=0 (medium+ and high-density devices)
0x17FFF 0x17FFF
PERIPHERAL
SPACE
0x5FFF
0x4000
DMA TRANSACTION
DIR=0
MEM=0
DMA TRANSACTION
DIR=1
MEM=0
MEMORY
SPACE
0x0000 0x0000
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Direct memory access controller (DMA)
Figure 39. Memory channel with MEM=1 (medium-density devices)
0xFFFF
0xFFFF
RM0031
MEMORY
AREA 0
DMA TRANSACTION
MEM=1
0x1FFF
0x0000
MEMORY
AREA 1
0x0000
Figure 40. Memory channel with MEM=1 (medium+ and high-density devices)
0xFFFF
0xFFFF
MEMORY
AREA 0
DMA TRANSACTION
MEM=1
0x0000
0x1FFF
0x0000
MEMORY
AREA 1
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RM0031 Direct memory access controller (DMA)
Channel
Table 36. Source and destination addresses
Transfer direction Source address range
Regular channels
Channel 0, Channel1,
Channel2
Peripheral to memory
Memory to peripheral
0x5200 to 0x53FF
0x0000 to 0x0FFF
Destination address range
0x0000 to 0x07FF
(1)
0x0000 to 0x0FFF
(2)
0x5200 to 0x53FF
Peripheral to memory 0x4000 to 0x5FFF
0x0000 to 0xFFFF
(memory area 0)
Memory channel
Channel 3
Memory to peripheral
Memory to memory
0x0000 to 0xFFFF
(memory area 0)
0x0000 to 0xFFFF
(memory area 0)
0x4000 to 0x5FFF
0x0000 to 0x1FFF
(memory area 1)
1. On medium-density devices.
2. On medium+ and high-density devices.
DMA transaction suspension
A DMA transaction can be suspended at any time (even during the transfer) by disabling the
EN bit (Channel enable bit) in the DMA_CxCR register or by disabling each channel using the GEN bit (Global Enable bit) in the DMA_GCSR register.
If the channel is disabled when a DMA data transfer is ongoing, the channel is effectively disabled only once the current data transfer is completed.
Re-enabling the DMA channel resumes the DMA transaction.
When a DMA transaction is suspended, the software must modify the DMA registers.
Otherwise, the DMA transaction may not resume properly. If the number of data to transfer is modified, re-enabling the DMA causes a new transaction to be started instead of the current transaction to be resumed.
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Direct memory access controller (DMA) RM0031
The four hardware requests from the peripherals are simply logically ORed together before entering the DMA. This means that only one hardware request must be enabled at a time.
Refer to Figure 41 on page 189
. Each OR function allows you to connect ADC1, SPIx, I2C1,
USARTx, DAC and TIMx (x=1,2,3,) DMA requests to one of the four channels. The table below lists the DMA requests for each channel.
IPs
ADC1
(1)
SPI1
AES
I2C
USART1
DAC
TIM2
TIM3
TIM1
USART2
USART3
SPI2
TIM5
TIM4
(2)
Table 37. DMA1 channel request mapping
Channel 0 Channel 1 Channel 2
EOC EOC
SPI1_RX
EOC
SPI1_TX
AES_IN
I2C_RX
TIM2_CC1
TIM3_U
USART1_TX
DAC_CH2TRIG
TIM2_U
TIM3_CC1
USART1_RX
TIM1_CC3 TIM1_CC4
TIM3_CC2
TIM1_U
TIM1_CC1
TIM1_COM
USART2_TX
USART3_TX USART3_RX
SPI2_RX
TIM5_U
TIM4_U TIM4_U
TIM5_CC1
TIM4_U
Channel 3
EOC
AES_OUT
I2C_TX
DAC_CH1TRIG
TIM2_CC2
TIM1_CC2
USART2_RX
SPI2_TX
TIM5_CC2
TIM4_U
Note: 1 ADC1 can be mapped on each of the four channels: depending on the
SYSCFG_RMPCR1[1:0] bits (please refer to the ADC chapter and Section 11.5: SYSCFG registers ). The default mapping is Channel 0.
2 TIM4 can be mapped on each of the four channels: depending on the
SYSCFG_RMPCR1[3:2] bits (please refer to Timer chapter and Section 11.5: SYSCFG registers ). The default mapping is Channel 3.
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Figure 41. DMA1 request mapping (medium-density devices)
Peripheral
request signals
SYSCFG_RMPCR1[1:0]
ADC1
I2C1_RX
TIM2_CC1
ADC1
TIM3_U
TIM1_CC3
TIM4_U
ADC1
SPI1_RX
USART1_TX
TIM2_U
TIM3_CC1
TIM1_CC4
TIM4_U
Hardware request 0
Channel 0 EN bit
Hardware request 1
Fixed hardware priority
Channel 0
Channel 1
High priority
Channel 1 EN bit
TIM4_U
ADC1
SPI1_TX
USART1_RX
TIM3_CC2
TIM1_U
TIM1_CC1
TIM1_COM
TIM4_U
Hardware request 2
Channel 2 EN bit
Channel 2 internal
DMA
request
SYSCFG_RMPCR1[3:2]
ADC1
I2C1_TX
DAC
TIM1_CC2
TIM4_U
Hardware request 3
Channel 3
Low priority
Channel 3 EN bit
Figure 42. DMA1 request mapping (medium+ and high-density devices)
Peripheral
request signals
SYSCFG_RMPCR1[1:0]
ADC1
EOC, AES_IN, I2C_RX
TIM1_CC3, TIM2_CC1
ADC1
TIM5_U, TIM3_U
USART2_TX, SPI2_RX
TIM4_U
ADC1
EOC, SPI1_RX
USART3_TX, USART1_TX
DAC_CH2TRIG, TIM2_U
TIM3_CC1
TIM1_CC4
TIM4_U
TIM4_U
ADC1
EOC, SPI1_TX
USART3_TX, USART1_RX
TIM3_CC2
TIM5_CC1, TIM1_U
TIM1_CC1
TIM1_COM
TIM4_U
Hardware request 0
Channel 0 EN bit
Hardware request 1
Channel 1
Channel 1 EN bit
Hardware request 2
Channel 2
Channel 2 EN bit
Fixed hardware priority
Channel 0
High priority internal
DMA
request
SYSCFG_RMPCR1[3:2]
ADC1
EOC, I2C_TX
AES_OUT, DAC_CH1TRIG
USART2_RX, TIM2_CC2, TIM1_CC2
SPI2_TX, TIM5_CC2
TIM4_U
Hardware request 3
Channel 3
Low priority
Channel 3 EN bit
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13.3.5 DMA hardware request description
AES DMA requests
The AES accelerator provides an interface to connect to the DMA controller. The DMA must be configured to transfer bytes. The AES can be associated with two distinct DMA request channels:
• A DMA request channel for the inputs : When the DMAEN bit is set in the AES_CR register, the AES initiates a DMA request (AES_IN) during the input phase each time it requires a byte to be written into the AES_DINR register. The DMA channel must be configured in memory-to-peripheral mode (bit DTD=1 in the corresponding
DMA_CxCR register).
• A DMA request channel for the outputs : When the DMAEN bit is enabled, the AES initiates a DMA request (AES_OUT) during the output phase each time it requires a byte to be written into the AES_DOUTR register. The DMA channel must be configured in peripheral-to-memory mode (bit DTD=0 in the corresponding DMA_CxCR register).
SPIx DMA requests
The Transmission DMA request and the Reception DMA request can be independently enabled or disabled by programming the control bits inside the SPI.
USARTx DMA requests
The Transmission DMA request and the Reception DMA request can be independently enabled or disabled by programming the control bits inside the USART.
Request
USARTx_RX
SPIx_RX
USARTx_TX
SPIx_TX
Table 38. SPIx/USARTx DMA requests
Description
Reception requests: DMA transfer request when one character has been received.
Transmission requests: DMA transfer request when the transmit buffer is empty
(Data to be transmitted has been loaded into the shift register)
I2C1 DMA requests
DMA requests are generated only for data transfers by the I2C1 data register (I2C1_DR)
• in transmission when it becomes empty
• in reception when it is full.
When the number of data transfers that have been programmed in the DMA controller is reached, the DMA controller sends an EOT signal (End of transfer) to the I 2 C interface and generates a DMA interrupt.
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Request
I2C1_TX
I2C1_RX
Table 39. I2C1 DMA requests
Description
M aster transmitter : During an EOT interrupt from the DMA controller, DMA requests must be disabled. The DMA controller has then to wait until a BTF (byte transfer finished) event before programming the STOP condition.
Master receiver : The DMA controller sends a hardware signal EOT_1 corresponding to the (number of bytes-1). If LAST=1 in ITDMA register, I2C automatically sends a NACK after the next byte following EOT_1. DMA controller
End of transfer interrupt allows to program the STOP condition.
ADC1 DMA requests
DMA requests are asserted when the conversion of a selected channel is completed.
TIM
x
DMA requests
TIM x DMA requests can be independently enabled/disabled by programming the DMA control bit inside the Timer.
Request
TIMx_UP (1)
TIM1_CC3
TIM1_CC4
TIM1_COM
Table 40. TIMx DMA requests
Description
Update event request: DMA transfer request at each update event
Capture/Compare 1 request: DMA transfer request at each Cap/Com 1 event
Capture/Compare 2 request: DMA transfer request at each Cap/Com 2 event
Capture/Compare 3 request: DMA transfer request at each Cap/Com 3 event
Capture/Compare 4 request: DMA transfer request at each Cap/Com 4 event
DMA transfer request at each commutation (COM) event: that is, when CCxE,
CCxNE and OCxM Capture/Compare control bits have been updated
1. x= 1, 2, 3 and 4 in medium-density devices and x= 1, 2, 3 , 4 and 5 in medium+ and high-density devices.
DAC DMA requests
DAC DMA requests are generated when the external trigger occurs, either using a software trigger (SWTRIG bit in the DAC_SWTRIGR register) or a hardware trigger (TIM4_TRGO in medium-density devices and TIM4_TRGO / TIM5_TRGO / external trigger input PE4 in medium+ and high-density devices). The request indicates that the CHxDHR registers have been transferred to the CHxDOR registers.
13.4 DMA low power modes
Table 41. DMA behavior in low power modes
Mode Description
Wait, Low power wait
DMA transfers are still operating
Halt/Active-halt DMA transfers are stopped
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Note:
Interrupt event
Table 42. DMA interrupt requests
Event flag
Enable control bit
Exit from
Wait/
Low power wait
Half transaction interrupt flag
Transaction complete interrupt flag
HTIF
TCIF
HTIE
TCIE
Yes
Yes
Exit from
Halt/
Active-halt
No
No
To ensure that a transaction is really completed when using a peripheral to trigger a DMA request, the software must choose carefully between the DMA internal interrupt flag and the peripheral interrupt.
The TCIF flag rises when the whole programmed transaction is completed by the DMA, but this does not necessarily mean that the peripheral ended the data transmission.
The reset operation of the HTIF and TCIF bits has priority over the set operation.
The DMA controller has two sets of registers:
• a set of global registers used to globally enable/disable the DMA and to identify quickly the interrupt source
• a set of control, status and pointer registers dedicated for each channel.
In the following description, the name of the registers dedicated to each channel starts with
DMA_Cx where x represents the channel number (numbered from 0 to 3).
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13.6.1 DMA global configuration & status register (DMA_GCSR)
7
Address offset: 0x00
Reset value: 0xFC
6 5 4 3 2 rw rw rw
TO[5:0] rw rw rw
1
GB r
0
GEN rw
Bits 7:2 TO[5:0] : Timeout
These bits define the timeout duration (number of cycles to wait starting from the last request). Then the DMA waits until this timeout has elapsed before asking to the core a high priority access to the bus. These bits are write protected if GEN bit and GB bit is set.
When programmed to 0x00, there is no timeout and once a request is served, the DMA immediately asks to the CPU a high priority access to the bus.
Bit 1 GB : Global busy
0: There is no ongoing DMA transfer
1: There is an ongoing DMA transfer
Note: The GB bit is logically ORed with all BUSY flags of each channel.
Bit 0 GEN : Global enable
0: All DMA channels are disabled
1: The DMA channels are locally enabled depending on the EN bit in the DMA_CxCR register.
13.6.2 DMA global interrupt register 1 (DMA_GIR1)
7
Reserved r
Address offset: 0x01
Reset value: 0x00
6
Reserved
5
Reserved r r
4
Reserved r
3
IFC3 r
2
IFC2 r
Bits 7: 4 Reserved
Bit 3 IFC3 : Interrupt flag channel 3
0: No pending interrupt on channel 3.
1: At least one pending interrupt on channel 3.
Bit 2 IFC2 : Interrupt flag channel 2
0: No pending interrupt on channel 2.
1: At least one pending interrupt on channel 2.
Bit 1 IFC1 : Interrupt Flag Channel 1
0: No pending interrupt on channel 1.
1: At least one pending interrupt on channel 1.
Bit 0 IFC0 : Interrupt flag channel 0
0: No pending interrupt on channel 0.
1: At least one pending interrupt on channel 0.
1
IFC1 r
0
IFC0 r
Note: This register is useful to quickly identify the channel which has generated an interrupt without checking all status registers of each channel. Then the software can check the corresponding channel status register and handle the interrupt software management.
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For each channel, the dedicated flag is set by hardware as soon as one of the two interrupt flags of the corresponding channel is set. The softwFare resets it when clearing the interrupt flag of the DMA_CxSPR register of the channel which has generated the interrupt.
13.6.3 DMA channel configuration register (DMA_CxCR)
7
Reserved r
There is one control register per channel where x represents the regular channel number
(numbered from 0 to 3).
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
6 5
MEM (rw) or
Reserved (r) r/rw
MINCDEC rw
4
CIRC rw
3
DIR rw
2
HTIE rw
1
TCIE rw
0
EN rw
This register is write protected when the DMA channel is enabled (EN bit and GEN bit set) and when the channel is busy (BUSY bit set).
Bit 7 Reserved
Bit 6 MEM : Memory transfer enabled
0: The channel works as a regular channel.
1: The channel works as a memory channel.
Note: This bit is implemented only for channel 3 (memory channel). Otherwise it is a reserved bit.
Bit 5 MINCDEC : Memory increment/decrement mode
0: Decrement mode.
1: Increment mode.
This bit defines if the memory address pointer will be incremented or decremented but the peripheral address pointer is never incremented or decremented.
Note: In case of memory to memory transfer, only the destination memory pointer (memory pointer address 1) can be incremented or decremented. This bit has no effect on the source memory pointer (Memory pointer address 0) which is always incremented (it cannot be decremented).
Bit 4 CIRC : Circular buffer mode (Auto-reload mode)
0: Circular mode disabled.
1: Circular mode enabled.
Note: This bit is don’t care if MEM = 1 (in this case, the Auto-reload mode is always disabled)
Bit 3 DIR : Data transfer direction
0: Transfer from the peripheral to the memory.
1: Transfer from the memory to the peripheral.
Note: This bit is don’t care if MEM = 1
Bit 2 HTIE : Half-transaction interrupt enable
0: Half-transaction interrupt disabled.
1: Half-transaction interrupt enabled.
Bit 1 TCIE : Transaction complete interrupt enable
0: Transaction complete interrupt disabled.
1: Transaction complete interrupt enabled.
Bit 0 EN : Channel enable
0: Channel disabled.
1: Channel disable.
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Note: 1 At the end of a transaction (when the current data counter reaches zero), the DMA channel is NOT automatically disabled (for interrupt mask management).
2 When the channel is disabled, all pointer registers remain as they were.
13.6.4 DMA channel status & priority register (DMA_CxSPR)
7
BUSY r
There is one status and priority register (SPR) per channel where x represents the channel number (numbered from 0 to 3).
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
6 5
PEND r rw
PL[1:0]
4 rw
3
TSIZE rw
2
HTIF rc_w0
1
TCIF rc_w0
0
Reserved r
Bit 7 BUSY : Channel busy
0: There is no ongoing DMA transfer
1: There is an ongoing DMA transfer
Bit 6 PEND : Channel pending
0: There is no pending request
1: There is a DMA pending request
Note: If MEM = 1, this bit is don’t care.
Bit 5:4 PL[1:0] : Channel priority level
This bit is used for software arbitration between channels
00: Low
01: Medium
10: High
11: Very high (DMA takes precedence over the CPU).
Note: These bits are write protected when the channel is enabled (EN and GEN bits set) and when the channel is busy (BUSY bit set).
Bit 3 TSIZE : Transfer size
This bit is used to perform a 16-bit wide transfer to ensure data coherence
0: 8-bit mode
1: 16-bit mode
Note: This bit is write protected when the channel is enabled (EN and GEN bits set) and when the channel is busy (BUSY bit set).
Bit 2 HTIF : Half transaction interrupt flag
0: No event.
1: Half transaction completed.
This bit is set by hardware and can be cleared by software writing 0 (even if the DMA channel is enabled).
Note: The reset operation of the HTIF bit has priority over the set operation.
Bit 1 TCIF : Transaction complete interrupt flag
0: No event.
1: Transaction completed.
This bit is set by hardware and can be cleared by software writing 0 (even if the DMA channel is enabled).
Note: The reset operation of the TCIF bit has priority over the set operation.
Bit 0 Reserved
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13.6.5 DMA number of data to transfer register (DMA_CxNDTR)
7 rw/r
There is one “number of data to transfer register” per channel where x represents the channel number (numbered from 0 to 3).
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
6 5 4 3 2 1 0
NDT[7:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r
Bits 7:0 NDT[7:0] : Number of data to transfer
Number of data (byte or word) to be transferred (0 up to 255).
This register can only be written when the channel is disabled. When the channel is enabled, this register is write protected and can be read to indicate the remaining data to be transmitted.
Once the transaction is completed, this register remains to zero.
If the channel is configured in auto-reload mode (CIRC = 1), it is automatically reloaded by the value previously programmed.
If a request occurs and the number of data to transfer is zero, the DMA does not serve the transaction.
13.6.6 DMA peripheral address high register (DMA_CxPARH)
Address offset: Refer to Table 43: DMA register map on page 201
There is one “peripheral address high register” per regular channel where x represents the channel number (numbered from 0 to 2).
This register is write protected when the DMA channel is enabled (EN = 1 and GEN = 1) and when the channel is busy (BUSY = 1).
Reset value: 0x52
7 6 5 4 3 2 1 0
PA[15:8] r r r r r r r rw
Bits 7:0 PA[15:8] : Peripheral address pointer (MSB)
The PA pointer is the source address when DIR = 0 or the destination address when DIR = 1.
Only bit 0 is accessible and the other bits are fixed to allow a value range from 0x52 to 0x53.
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13.6.7 DMA peripheral address low register (DMA_CxPARL)
There is one “peripheral address low register” per regular channel where x represents the regular channel number (numbered from 0 to 2).
Address offset: Refer to Table 43: DMA register map on page 201
.
Reset value: 0x00
This register is write protected when the DMA channel is enabled (EN and GEN bits set) and when the channel is busy (BUSY bit set).
7 6 5 4 3 2 1
PA[7:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r
Bits 7:0 PA[7:0] : Peripheral address pointer (LSB)
The PA Pointer is the source address if DIR = 0 or the destination address if DIR = 1.
0 rw/r
13.6.8 DMA channel 3 peripheral address high & memory 1 address high register (DMA_C3PARH_C3M1ARH)
Note:
7 r
Address offset: Refer to Table 43: DMA register map on page 201
. This register is write protected when the DMA channel is enabled (EN= 1 and GEN = 1) and when the channel is busy (BUSY = 1).
It has two different meanings depending on the MEM bit configuration:
• DMA channel 3 peripheral address high (DMA_C3PARH)
This definition is valid when the MEM bit is reset.
Reset value: 0x40
6 5 4 3 2 1 0
PA[15:8] r r rw/r rw/r rw/r rw/r rw/r
Bits 7:0 PA[15:8] : Peripheral address pointer (MSB)
The PA pointer is the source address when DIR = 0 or the destination address when DIR = 1.
Only bits 0, 1, 2, 3 and 4 are accessible and the other bits are fixed to allow a value range from 0x40 to 0x5F.
Note:
• DMA channel 3 memory 1 address high (DMA_C3M1ARH)
This definition is valid when the MEM bit is set.
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Reset value: N/A
7 6 5 4 rw/r
3
M1A[15:8] rw/r
2 1 0 r r r rw/r rw/r rw/r
Bits 7:0 M1A[15:8] : Memory 1 address pointer (MSB)
The M1A pointer is the destination address when performing memory-to-memory transfers. Only bits
0, 1, 2, 3 and 4 are accessible. The other bits are fixed to allow a value range from 0x00 to 0x1F.
13.6.9 DMA channel 3 peripheral address low & memory 1 address low register (DMA_C3PARL_C3M1ARL)
Note:
7 rw/r
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
This register is write protected when the DMA channel is enabled (EN and GEN bits set) and when the channel is busy (BUSY bit set).
This register has two different meanings depending on the MEM bit configuration:
• DMA channel 3 peripheral address low (DMA_C3PARL)
This definition is valid when the MEM bit is reset.
6 5 4 3
PA[7:0] rw/r rw/r rw/r rw/r
2 rw/r
1 rw/r
0 rw/r
Bits 7:0 PA[7:0] : Peripheral address pointer (LSB)
The PA Pointer is the source address if DIR = 0 or the destination address if DIR = 1.
Note:
7 rw/r
• DMA channel 3 memory 1 address low (DMA_C3M1ARL)
This definition is valid when the MEM bit is set.
6 5 4 3 2 rw/r rw/r rw/r
M1A[7:0] rw/r rw/r
1 rw/r
Bits 7:0 M1A[7:0] : Memory 1 address pointer (LSB)
The M1A pointer is the destination address when performing memory-to-memory transfers.
0 rw/r
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13.6.10 DMA memory 0 address high register (DMA_CxM0ARH)
7 rw/r or r
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
This register is write protected when the DMA channel is enabled (EN = 1 and GEN = 1) and when the channel is busy (BUSY = 1).
6 5 4 3 2 1 0
M0A[15:8] rw/r or r rw/r or r rw/r rw/r or r rw/r rw/r rw/r
Bits 7:0 M0A[15:8] : Memory 0 address pointer (MSB)
″ When MEM = 0, for regular channels or memory channels, the M0A pointer is the destination address when DIR = 0 or the source address when DIR = 1.
″ When MEM = 1, for memory channels, the M0A pointer is always the source address. All bits are accessible to allow a value range from 0x00 to 0xFF.
″ For regular channels, only bits 0,1 and 2 are accessible and the other bits are fixed to allow a value range from 0x00 to 0x07.
13.6.11 DMA memory 0 address low register (DMA_CxM0ARL)
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
This register is write protected when the DMA channel is enabled (EN= 1 and GEN = 1) and when the channel is busy (BUSY = 1).
7 6 5 4 3 2 1 0
M0A[7:0] rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r
Bits 7:0 M0A[7:0] : Memory 0 address pointer (LSB)
For regular channels or memory channels when MEM = 0, the M0A Pointer is the destination address when DIR = 0 or the source address when DIR = 1.
For memory channels when MEM = 1, the M0A Pointer is always the source address.
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13.6.12 DMA channel 3 memory 0 extended address register
(DMA_C3M0EAR)
Note:
Address offset: Refer to Table 43: DMA register map on page 201
Reset value: 0x00
This register is available in medium+ and high-density devices only.
It is write protected when the DMA channel is enabled (EN= 1 and GEN = 1) and when the channel is busy (BUSY = 1).
7 6 5 4
Reserved r
3 2 1 0
M0A16 rw/r
Bit 0 M0A16 : Memory 0 address pointer 16
For regular channels or memory channels when MEM = 0, the M0A pointer is the destination address when DIR = 0 or the source address when DIR = 1.
For memory channels when MEM = 1, the M0A Pointer is always the source address.
Bits 7:1 Reserved
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0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
Offset address
0x00
0x01
0x19
Register name
DMA_GCSR
Reset value
DMA_GIR1
Reset value
DMA_C0CR
Reset value
DMA_C0SPR
Reset value
DMA_C0NDTR
Reset value
DMA_C0PARH
Reset value
DMA_C0PARL
Reset value
DMA_C0M0ARH
Reset value
DMA_C0M0ARL
Reset value
DMA_C1CR
Reset value
DMA_C1SPR
Reset value
DMA_C1NDTR
Reset value
DMA_C1PARH
Reset value
DMA_C1PARL
Reset value
DMA_C1M0ARH
Reset value
DMA_C1M0ARL
Reset value
DMA_C2CR
Reset value
Table 43. DMA register map
7 6 5 4 3 2 1 0
TO5
1
-
0
TO4
1
-
0
TO3
1
-
0
-
0
DMA channel 0 registers
-
0
MINCDEC
0
BUSY
0
PEND
0
PL1
0
NDT7
0
PA15
0
NDT6
0
PA14
1
NDT5
0
PA13
0
PA7
0
M0A15
0
PA6
0
PA5
0
Reserved area
M0A14
0
M0A13
0
M0A7
0
M0A6
0
M0A5
0
DMA channel 1 registers
-
0
BUSY
0
-
0
PEND
0
MINCDEC
0
PL1
0
NDT7
0
NDT6
0
NDT5
0
PA15
0
PA7
0
PA14
1
PA6
0
PA13
0
PA5
0
Reserved area
M0A15
0
M0A7
0
M0A14
0
M0A6
0
M0A13
0
M0A5
0
-
0
DMA channel 2 registers
-
0
MINCDEC
0
TO2
1
-
0
M0A12
0
M0A4
0
M0A12
0
M0A4
0
CIRC
0
CIRC
0
PL0
0
NDT4
0
PA12
1
PA4
0
CIRC
0
PL0
0
NDT4
0
PA12
1
PA4
0
TO1
1
IFC3
0
DIR
0
TSIZE
0
NDT3
0
PA11
0
PA3
0
M0A11
0
M0A3
0
DIR
0
TSIZE
0
NDT3
0
PA11
0
PA3
0
TO0
1
IFC2
0
HTIE
0
HTIF
0
NDT2
0
PA10
0
PA2
0
M0A10
0
M0A2
0
HTIE
0
HTIF
0
NDT2
0
PA10
0
PA2
0
GB
0
IFC1
0
TCIE
0
TCIF
0
NDT1
0
PA9
1
PA1
0
M0A9
0
M0A1
0
TCIE
0
TCIF
0
NDT1
0
PA9
1
PA1
0
GEN
0
IFC0
0
EN
0
-
0
NDT0
0
PA8
0
PA0
0
M0A8
0
M0A0
0
EN
0
-
0
NDT0
0
PA8
0
PA0
0
M0A11
0
M0A3
0
M0A10
0
M0A2
0
M0A9
0
M0A1
0
M0A8
0
M0A0
0
DIR
0
HTIE
0
TCIE
0
EN
0
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Table 43. DMA register map (continued)
Offset address
Register name 7 6 5 4 3 2
0x1A
0x1B
0x1C
0x1D
0x1E
DMA_C2SPR
Reset value
DMA_C2NDTR
Reset value
DMA_C2PARH
Reset value
DMA_C2PARL
Reset value
BUSY
0
NDT7
0
PA15
0
PA7
0
PEND
0
NDT6
0
PL1
0
NDT5
0
PA14
1
PA6
0
PA13
0
PA5
0
Reserved area
PL0
0
NDT4
0
PA12
1
PA4
0
TSIZE
0
NDT3
0
PA11
0
PA3
0
HTIF
0
NDT2
0
PA10
0
PA2
0
0x1F
0x20
DMA_C2M0ARH
Reset value
DMA_C2M0ARL
Reset value
M0A15
0
M0A7
0
M0A14
0
M0A6
0
M0A13
0
M0A5
0
M0A12
0
M0A4
0
M0A11
0
M0A3
0
M0A10
0
M0A2
0
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
DMA_C3CR
Reset value
DMA_C3SPR
Reset value
DMA_C3NDTR
Reset value
DMA_C3PARH_C3M1ARH
DMA_C3PARL_C3M1ARL
Reset value
DMA_C3M0EAR
(1)
Reset value
DMA_C3M0ARH
Reset value
DMA_C3M0ARL
Reset value
-
0
0
0
-
0
0
DMA channel 3 registers
BUSY
NDT7
M0A15
M0A7
0
MEM
0
PEND
0
NDT6
0
-
0
M0A14
0
M0A6
0
MINCDEC
0
PL1
0
NDT5
0
PA[15:8] (reset value: 0x40) or M1A[15:8]
-
0
M0A13
0
M0A5
0
CIRC
0
PL0
0
NDT4
0
DIR
0
TSIZE
0
NDT3
0
PA[7:0] or M1A[7:0]
0000 0000
-
0
M0A12
0
M0A4
0
1. Available in medium+ and high-density devices only. Reserved in medium-density devices.
-
0
M0A11
0
M0A3
0
HTIE
0
HTIF
0
NDT2
0
-
0
M0A10
0
M0A2
0
1 0
TCIF
0
NDT1
0
PA9
1
PA1
0
-
0
NDT0
0
PA8
0
PA0
0
M0A9
0
M0A1
0
M0A8
0
M0A0
0
TCIE
0
TCIF
0
NDT1
0
EN
0
-
0
NDT0
0
-
0
M0A9
0
M0A1
0
M0A16
0
M0A8
0
M0A0
0
RM0031 Rev 15
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14
Analog-to-digital converter (ADC)
Analog-to-digital converter (ADC)
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The analog-to-digital converter is used to convert the analog voltage signals to digital values. Up to 28 analog channels are available. A/D conversion can be performed in single or continuous mode.
14.2 ADC main features
• Configurable resolution (up to 12-bit data width)
• Number of analog channels:
– Medium-density devices:
25 analog channels : 1 fast channel (1 µs) + 24 slow channels
– Low, medium+ and high-density devices:
28 analog channels : 4 fast channels (1 µs) + 24 slow channels
• 2 internal channels connected to temperature sensor and internal reference voltage
• Configurable single or continuous conversion
• Prescalable ADC clock
• Analog watchdog
• Separate interrupt generation at end of conversion, watchdog or overrun event
• Multiple channel conversion (scan mode)
• Data integrity mechanism
• DMA capability
• Programmable sampling time
• Schmitt trigger disabling capability
• Conversion time which can be up to 1 µs when SYSCLK = 16 MHz
• Voltage range: 1.8 V to 3.6 V
– Maximum conversion rate obtained from 2.4 V to 3.6 V
– ADC at a lower speed between 1.8 V and 2.4 V
– ADC functionality not guaranteed below 1.8 V
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Analog-to-digital converter (ADC)
14.3 ADC functional description
RM0031
shows the block diagram of the complete system ADC interface.
Figure 43. ADC block diagram
ADC interface
Interrupt
ADC_DRH -
ADC_DRL D7 D6
-
D5
-
D4
-
D3
D11 D10 D9
D2 D1 D0
D8
ADC_SR EOC / AWD/
OVER
ADC_CR1
EOCIE /
AWDIE /
OVERIE
ADC_CR1
START ADON
Clock prescaler
Control logic
27
ADC_IN0
ADC_IN1
ADC_IN27
1)
ANALOG
MUX
ADC_IN V
REFINT
ADC_IN TS
TSON
VREFINTON
1. ADC_IN27 for medium+ and high-density devices.
ADC_IN24 for medium-density devices.
2. Only basic features are shown in this diagram
ADC_CLK
V
IN
RST
Analog to digital converter
Temperature sensor
Internal reference voltage V
REFINT
Digital value
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RM0031 Analog-to-digital converter (ADC)
14.3.2 Number of analog channels
Up to 30 analog input channels are available in the STM8L05xx/STM8L15xx devices:
• Up to 27 analog input channels in the medium-density devices.
• Up to 28 analog input channels in the low-density devices.
• Up to 30 analog input channels in the medium+ and high-density devices.
They can be classified into three groups:
• Slow channels: channels 0 to 23 with a sampling time selected through the SMP1 bits in the ADC_CR2 register
• Fast channels: channel 24 (medium-density devices) or channels 24 to 27 (medium+ and high-density devices) with a sampling time selected through the SMP2 bits in the
ADC_CR3 register
• Fast internal channels: channels V
REFINT
and TS with a sampling time selected through the SMP2 bits in the ADC_CR3 register.
The ADC can be powered-on by setting the ADON bit in the ADC_CR1 register. When the
ADON bit is set, it wakes up the ADC from Power-down mode. Conversion should be started only when the ADC power-up time (t
WKUP maximum idle delay (t
IDLE in Power-down mode by resetting the ADON bit.
) has elapsed and before the ADC
) has elapsed. The software can stop conversion and put the ADC
14.3.4 Single conversion mode
Note:
Note:
In this mode, only one input channel must be selected in the ADC_SQRx registers ( if more channels are selected, the highest selected channel is measured). In addition, the DMAOFF bit must be set in the ADC_SQR1 register (to disable DMA transfer). The input channel is then converted and the ADC conversion stops (one simple conversion). The converted value is stored into the ADC_DR data register. An interrupt (EOC) can be generated after the end of conversion. The time between 2 conversions must be lower than the ADC maximum idle delay (t
IDLE
). In case the time between 2 conversions is greater than t
IDLE
, the ADC must be powered-off between the 2 conversions (by clearing the ADON bit).
Another possiblity is to discard the first conversion (occuring in a time greater than tidle after previous one) and keep the next one
If the DMAOFF bit in the ADC_SQR1 register is reset (and if DMA is properly programmed) the conversion is then performed in single scan mode.
In the single conversion mode, the ADC does one conversion. The conversion can be started in two different ways:
• by software: conversion is performed by setting the START bit in the ADC_CR1 register. The START bit is then reset by hardware.
The channel selection is performed using the ADC_SQRx registers.
Before starting a conversion, the software should wait for the stabilization time (t
WKUP
).
• by hardware: three external triggers can start a conversion (ADC_TRIGR1,
ADC_TRIGR2 or ADC_TRIGR3). The selection of one of these three triggers is made through the EXTSEL[1:0] bits in the ADC_CR2 register. The conversion can be triggered either on the rising edge, on the falling edge or on both edges of the signal, depending on the TRIG_EDGE[1:0] bits in the ADC_CR2 register.
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Analog-to-digital converter (ADC) RM0031
Note: Any start event occurring during the conversion will be ignored.
Once the conversion is complete:
• the EOC flag is set
• and an interrupt is produced if the EOCIE bit is set in the ADC_CR1 register.
The EOC flag can be reset by software or by reading the LSB of the converted data.
Further single conversions can be initiated by simply setting the START bit or by rising an external trigger.
Note: 1 The channel must not be changed during a conversion.
2 The user must avoid generating triggers before the end of an ongoing conversion.
3 The trigger edge configuration must be set before enabling the triggers
4 Even if no channel is programmed, a conversion can be started and the EOC flag will be set.
ADC external triggers
Three external trigger sources can be selected:
• ADC trigger 1.
The trigger can be performed
– either from PA6 (if the ADC_TRIG bit in the SYSCFG_RMPCR2 register is reset; refer to Alternate function remapping section in the datasheet)
– or directly from PD0 (if ADC_TRIG bit in the SYSCFG_RMPCR2 register is set; refer to Alternate function remapping section in the datasheet)
• ADC trigger 2.
The trigger is performed directly from Timer 1 trigger output (TIM1_TRGO)
• ADC trigger 3.
The trigger is performed directly from Timer 2 trigger output (TIM2_TRGO)
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RM0031 Analog-to-digital converter (ADC)
Figure 44. ADC external triggers
SYSCFG_RMPCR2[0]
PA6 0
PD0
1
TRGO from TIM1
TRIG_1
TRIG_2
TRIG_3
ADC1
TRGO from TIM2 ai15365c
14.3.5 Continuous conversion mode
Note:
In this mode , the ADC does not stop after conversion but continues to the next channel in the selected channel sequence. Conversions continue until the CONT bit and the ADON bits are set and the converted values are transferred through the DMA to the RAM or
EEPROM memory buffer.
As the EOC interrupt is generated only after the end of the conversion of the selected channel sequence, the result of each channel conversion cannot be read from the ADC_DR register.
To save the conversion of each channel in a memory (RAM or EEPROM), the DMA must be used in peripheral to memory mode. If the CONT bit is reset during a conversion, the current selected channel sequence conversions end with the last selected channel) and then the ADC stops.
The CONT bit must not be set again during a conversion.
The ADC clock provided by the clock controller can be either the ADC system clock (CK) or the ADC system clock divided by 2. The selection of the frequency feeding the clock
(f
ADC_CLK
= CK or f
ADC_CLK
= CK/2) is done through the PRESC bit in the ADC_CR2 register.
The analog watchdog status bit (AWD) in the ADC_SR register is set when the analog voltage converted by the ADC is above or below a reference voltage threshold defined by
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Analog-to-digital converter (ADC) RM0031
Note: the higher/lower thresholds programmed into the ADC_HTRH/L and ADC_LTRH/L registers.
In scan mode, the channel where the analog watchdog is enabled is the one selected through the CHSEL[4:0] bits in the ADC_CR3 register.
The threshold values must be set/changed before starting the conversion.
In scan mode a watchdog flag rise occurring during a conversion does not stop the next conversions of the sequence. This avoids having to start the ADC again every time an analog watchdog is enabled.
The action related to the analog watchdog is not necessarily linked to the other tasks using the other ADC channels.
14.3.8 Interrupts
An interrupt can be generated when an EOC event occurs (end of conversion in single mode or end of last scan conversion in scan mode) when the analog watchdog status bit
(AWD) is set in the ADC_SR register or, in scan mode, when a DMA request is not serviced and a new conversion is completed.
Individual interrupt lines are available as well as a common interrupt line. The following table summarizes the possible flag/interrupt configuration.
Flag
OVER
AWD
EOC
Table 44. Flag/interrupt configuration
Description Interrupt generation
Rises when a new converted data is ready and the previous one is not yet read by the DMA (scan mode)
Rises when the converted data is outside the reference voltage threshold
Rises when an end of conversion occurs (single mode)
Rises when the end of conversion of last channel of the sequence occurs (scan mode) yes yes yes
14.3.9 Channel selection (Scan mode)
This mode works automatically in continuous mode. It can also be used in single mode by resetting the DMAOFF bit in the ADC_SQR1 register.
In scan mode, the selected channel sequence is taken into account (like in single mode) and the selected channels are converted and transferred through DMA to memory (DMA should be properly programmed).
If the single mode is selected, the ADC converts the selected channel sequence and it is stopped after the last channel conversion. For the next selected channel sequence, a scan conversion is necessary to restart the ADC. An interrupt (EOC) can be generated after the end of the channel sequence conversion.
Three registers are available to select the channel or the sequence of channels used for conversion in Scan mode: ADC_SQR1, ADC_SQR2 and ADC_SQR3.
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Note:
Analog-to-digital converter (ADC)
This feature must be used in conjunction with the DMA controller.
The channel selection must be performed after enabling the ADC peripheral (by setting the
ADON bit in the ADC_CR1 register).
A single conversion is initiated on each channel of a sequence. After the end of conversion, the next channel of the sequence is automatically converted.
The channel selection is performed using the ADC_SQRx registers. A logic 1 in the position
‘n’ of these registers means that channel ‘n’ is in the list of channels to be converted.
For example,
Figure 45 below shows how to select the sequence: 0; 2; 6; 8; 10; 14; 18.
Figure 45. Sequence example
ADC_SQR1 ADC_SQR2 ADC_SQR3
0 0 0 0 0 0 0 0
27 1) 26 1) 25 1) 24
0 0 0
23 22 21
0 0
20 19
1 0 0
18 17 16
0 1
15 14
0 0 0 1
13 12 11 10 9
0 1
8
ADC_SQR4
0
7
1
6
0
5
0
4
0
3
1
2
0
1
1
0
Note:
1. Available on medium+ and high-density devices only.
If the CONT bit in the ADC_CR1 register is set (continuous mode selected), the conversion does not stop at channel ‘n’ but restarts from the first channel of the sequence. After each conversion, a DMA ADC request is sent and the DMA controller is used to transfer the converted data to the RAM.
The ADC_SQRx registers must not be changed during a conversion.
Note:
An 8-bit shadow register is used to store the LSB data when the MSB is read. The LSB data is read from the shadow register.
This guarantees the data consistency if a new data from the ADC is coming between the
MSB and LSB data read. Consequently, the software must read the MSB before reading the
LSB to be sure that both LSB and MSB are related to the same data.
An MSB read operation must always be followed by an LSB read operation.
When a scan conversion is performed, a DMA ADC request is sent as soon as an end of conversion is detected, to signal that a data is ready to be transferred.
If a new conversion is complete and the DMA has not completed the transfer of previous conversion data, the overrun flag is risen and an interrupt is generated (if enabled).
The DMA transfer can be disabled by setting the DMAOFF bit in the ADC_SQR1 register.
Caution: In scan mode, DMA transfer shall be disabled only when the ADC scan sequence is finalized.
It is possible to reduce the conversion time by reducing the ADC resolution.
The RES[1:0] bits in the ADC_CR1 register are used to configure the resolution to 6, 8, 10 or 12 bits. The converted data is received from the ADC through its serial output.
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Analog-to-digital converter (ADC)
Note:
RM0031
When the desired number of bits is achieved, a new conversion can start immediately.
The resolution bits can be changed only when no ADC conversion is ongoing.
The converted data stored after conversion are right aligned and their configuration depends on the selected resolution, as shown in the following figure:
Figure 46. Resolution and data alignment
12-bit resolution:
ADC_DRH 0 0 0 0 D11 D10 D9 D8
ADC_DRL D7 D6 D5 D4 D3 D2 D1 D0
10-bit resolution:
ADC_DRH 0 0 0 0 0 0 D11 D10
ADC_DRL D9 D8 D7 D6 D5 D4 D3 D2
8-bit resolution:
ADC_DRH 0 0 0 0 0 0 0 0
6-bit resolution:
ADC_DRH 0 0 0 0 0 0
ADC_DRL D11 D10 D9 D8 D7 D6 D5 D4
0 0
ADC_DRL 0 0 D11 D10 D9 D8 D7 D6 ai17091
The ADC input voltage is sampled during a number of cycles which is selected using:
• the SMP1[2:0] bits in the ADC_CR2 register for the first 24 channels
• and the SMP2[2:0] bits in the ADC_CR3 register for channels 24 to 27 (or channel 24 in medium-density devices), V
REFINT
and TS.
The following table shows the allowed values of sampling cycles.
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Note:
Analog-to-digital converter (ADC)
Table 45. Authorized sampling cycles
Bit configuration Sampling cycles
SMP1[2:0] for channels
0 to 23
&
SMP2[2:0] for channels 24 to
27 (or for channel
24 in mediumdensity devices)
V
REFINT
and TS
100
101
110
111
000
001
010
011
48
96
192
384
16
24
4
9
A different sampling time can be selected for slow channels and for fast channels.
The sampling time must not be changed during a conversion.
Note:
The Schmitt trigger can be disabled to reduce the consumption on some pins used as analog inputs.
As there are 2 internal channels, only 25 Schmitt triggers can be disabled on mediumdensity devices and 28 Schmitt triggers on medium+ and high-density devices.
In order to disable the Schmitt trigger on the ADC channels which are shared with the comparators inputs, it is also required to disable the Schmitt trigger through the
COMP_CSR4 and/or COMP_CSR5 registers.
If the control of the I/O using the Routing interface is enabled (with the corresponding bit set in the RI_IOCMRn register), the setting of the STE bit in the COMP_CSR1 register takes priority over the setting of the ADC_TRIGRn registers.
Note:
The temperature sensor is not available on STM8L05xx value line devices.
The temperature sensor can be used to measure the internal temperature of the device. It is internally connected to the ADC TS (temperature sensor) input channel that is used to convert the sensor output voltage into a digital value.
When it is not used, this sensor can be put in power-down mode.
The TSON bit in the ADC_TRIGR1 register must be set to enable the internal ADC TS channel connection. This connection must be enabled only if the temperature sensor conversion is required.
The internal temperature sensor can also be used to detect temperature variations. The output voltage of the temperature sensor is factory measured at high temperature and the result of the ADC conversion is stored in a specific data address: the
TS_Factory_CONV_V90 byte represents the LSB of the V90 12-bit ADC conversion result while the MSB have a fixed value: 0x3.
To reduce the temperature sensor error, the user can measure it at ambient temperature
(25°C) to redefine more accurately the average slope (avg_slope) and the offset.
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Analog-to-digital converter (ADC) RM0031
How to read the temperature
To read the temperature from the sensor, use the following procedure:
1.
Select the ADC1 TS (temperature sensor) input channel.
2. Select a sample time of 10 µs.
3. Set the TSON bit in the ADC_TRIGR1 register to wake up the temperature sensor from power-down mode.
4. Start the ADC conversion.
5. Read the resulting V
SENSE
data in the ADC data register (ADC_DRx).
6. Calculate the temperature using the following formulae:
T [ ° K ] =
V
SENSE
Note:
T [ ° C ] =
V
SENSE
AvgSlope
– 273.15
Where
Avg_Slope = estimation of the average slope of the “Temperature vs. V
SENSE in V/°K).
” curve (given
Refer to the Electrical characteristics section for the Avg_Slope value.
When the sensor wakes up from power-down mode, a stabilization time is required before a correct voltage can be output.
After power-on, the ADC also needs a stabilization time. To minimize this delay, the ADON and TSON bits should be set at the same time.
14.3.17 Internal reference voltage conversion
The internal reference voltage is internally connected to the V
REFINT
channel. This analog input channel is used to convert the internal reference voltage into a digital value.
The VREFINTON bit in the ADC_TRIGR1 register must be set to enable the internal reference voltage. This reference voltage must be enabled only if its conversion is required.
The internal reference voltage is factory measured and the result of the ADC conversion is stored in a specific data address: the VREFINT_Factory_CONV byte represents the LSB of the VREFINT 12-bit ADC conversion result while the MSB have a fixed value: 0x6.
VREFINT_Factory_CONV is not available in STM8L05xx value line devices.
14.4 ADC low power modes
Table 46. Behavior in low power modes
Mode Description
Wait/
Low power wait
Halt/
Active-halt
ADC interface is active.
Interrupt events cause the device to exit from Wait or Low power wait mode.
ADC interface is not active.
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RM0031 Analog-to-digital converter (ADC)
Interrupt event
End of conversion flag
Analog watchdog flag
Overrun flag
Table 47. Interrupt requests
Event flag
Enable control bit
EOC
AWD
OVER
EOCIE
AWDIE
OVERIE
Exit from
Wait / Low power wait
Yes
Yes
Yes
Exit from
Halt /
Active-halt
No
No
No
Address offset: 0x00
Reset value: 0x00
7
OVERIE rw
6
RES[1:0] rw
5 4
AWDIE rw
3
EOCIE rw
2
CONT rw
1
START rw
0
ADON rw
Bit 7 OVERIE : Overrun interrupt enable
This bit is set and cleared by software. If set it enables the interrupt generated by an overrun event.
0: Overrun interrupt disabled
1: Overrun interrupt enabled
Bits 6:5 RES[1:0] : Configurable resolution
These bits are set and cleared by software. These bits are used to configure the ADC resolution.
00: 12-bit resolution
01: 10-bit resolution
10: 8-bit resolution
11: 6-bit resolution
Bit 4 AWDIE : Analog watchdog interrupt enable
This bit is set and cleared by software. If set it enables the interrupt generated by the analog watchdog.
0: Analog watchdog interrupts disabled
1: Analog watchdog interrupts enabled
Bit 3 EOCIE : Interrupt enable for EOC
This bit is set and cleared by software. It enables the interrupt at the end of conversion.
0: EOC interrupt disabled
1: EOC interrupt enabled
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Analog-to-digital converter (ADC) RM0031
Bit 2 CONT : Continuous conversion
This bit is set and cleared by software. If set, conversion takes place continuously till this bit is reset.
0: Single conversion mode
1: Continuous conversion mode
Bit1 START : Conversion start
This bit is set by software and cleared by hardware.
If set, it starts a conversion (if enabled). It is automatically reset by hardware after one ADC clock cycle.
Note: If this bit is set during a conversion, it will not be considered.
Bit 0 ADON : A/D converter ON / OFF
This bit is set and reset by software. It wakes up the ADC from Power down mode.
0: ADC disabled (Power-down mode)
1: ADC enabled (wakeup from Power-down mode)
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RM0031 Analog-to-digital converter (ADC)
Address offset: 0x01
Reset value: 0x00
7
PRESC rw
6
TRIG_EDGE1 rw
5
TRIG_EDGE0 rw
4
EXTSEL1 rw
3
EXTSEL0 r
2 rw
1
SMTP1[2:0] rw
0 rw
Bit 7 PRESC : Clock prescaler
This bit is set and cleared by software. If set, it divides the ADC clock frequency by 2.
0: f
(ADC_CLK)
= CK
1: f
(ADC_CLK)
= CK/2
Bits 6:5 TRIG_EDGE[1:0] : Active edge for external triggers
These bits are set and cleared by software. They select the active edges for external triggers.
00: Reserved
01: Rising edge sensitive
10: Falling edge sensitive
11: Both rising and falling edge sensitive
Bits 4:3 EXTSEL[1:0] : External event selection
These two bits select the software start or one of 3 external events that can trigger a conversion.
00: Triggers disabled, software start enabled.
01: Trigger 1 enabled
10: Trigger 2 enabled
11: Trigger 3 enabled
Bits 2:0 SMTP1[2:0] : Sampling time selection
These bits are set/reset by software. They are used to select one of the following sampling times for the first 24 channels.
000: 4 ADC clock cycles
001: 9 ADC clock cycles
010: 16 ADC clock cycles
011: 24 ADC clock cycles
100: 48 ADC clock cycles
101: 96 ADC clock cycles
110: 192 ADC clock cycles
111: 384 ADC clock cycles
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Analog-to-digital converter (ADC) RM0031
Address offset: 0x02
Reset value: 0x1F
7 rw
6
SMTP2[2:0] rw
5 rw
4 rw
3 rw
2
CHSEL[4:0] rw
1 rw
0 rw
Bit 7:5 SMTP2[2:0] : Sampling time selection
These bits are set/reset by software. They are used to select one of the following sampling times for channels 24, V
REFINT
and TS.
000: 4 ADC clock cycles
001: 9 ADC clock cycles
010: 16 ADC clock cycles
011: 24 ADC clock cycles
100: 48 ADC clock cycles
101: 96 ADC clock cycles
110: 192 ADC clock cycles
111: 384 ADC clock cycles
Bit 4:0 CHSEL[4:0] : Channel selection
These bits are set and cleared by software. They are used to select the channel to be checked by the analog watchdog.
00000: ADC channel 0 is selected
00001: ADC channel 1 is selected
...
10111: ADC channel 23 is selected
11000: ADC channel 24 is selected
11001: ADC channel 25 is selected
(1)
11010: ADC channel 26 is selected
11011: ADC channel 27 is selected
11100: ADC channel V
REFINT
is selected
11101: ADC channel TS is selected
(2)
1. This configuration is “reserved” in medium-density devices.
2. This configuration is “reserved” in STM8L05xx value line devices.
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RM0031 Analog-to-digital converter (ADC)
14.6.4 ADC status register (ADC_SR)
Address offset: 0x03
Reset value: 0x00
7 6 5
Reserved
4 3 2
OVER rw_0
1
AWD rw_0
0
EOC rw_0
Bits 7:3 Reserved, forced by hardware to 0.
Bit 2 OVER : Overrun flag
This bit is reset by software writing 0 to it or by hardware when the ADC is put in power-down mode. It is set by hardware when, after a conversion, a second conversion has completed and the DMA has not read the first conversion value.
It cannot be set by software.
0: No overrun occurred
1: Overrun occurred
Bit 1 AWD : Analog watchdog flag
This bit is reset by software writing 0 to it or by hardware when the ADC is in power-down mode. It is set when the analog voltage converted by the ADC is above or below the reference voltage thresholds defined by the lower/higher thresholds in the ADC_xTRx registers.
It cannot be set by software.
0: No analog watchdog event occurred
1: Analog watchdog event occurred
Bit 0 EOC : End of conversion
This bit is set by hardware at the end of conversion. It is cleared by software by writing ‘0’ to it or by reading the LSB of the converted data or when the ADC is put in power-down mode.
In case of scan conversion, this bit is set at the end of conversion of the last channel of the sequence.
It cannot be set by software.
0: Conversion not complete
1: Conversion complete
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Analog-to-digital converter (ADC) RM0031
Address offset: 0x04
Reset value: 0x00
7 6
Reserved
5 4 3 r
2
CONV_DATA[11:8]
1 r r
0 r
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0 CONV_DATA[11:8] : Data bits high
These bits are set/reset by hardware and are read only. They contain the 4 MS bits of the converted data. The converted voltage data bits are right aligned and their configuration depends on the programmed resolution, as described below:
12-bit resolution: bits 3:0 = CONV_DATA[11:8]
10-bit resolution: bits 3:2 = reserved; Bits1:0 : CONV_DATA[9:8]
8-bit resolution: bits 3:0 = reserved
6-bit resolution: bits 3:0 = reserved
Address offset: 0x05
Reset value: 0x00
7 6 5 4
CONV_DATA[7:0]
3 r r
2 1 0 r r r r r r
Bits 7:0 Data[7:0] : Data bits low
These bits are set/reset by hardware and are read only. They contain the 8 LS bits of the converted data. The converted voltage data bits are right aligned and their configuration depends on the programmed resolution, as described below:
12-bit resolution: Bits 7:0 = CONV_DATA[7:0]
10-bit resolution: Bits 7:0 = CONV_DATA[7:0]
8-bit resolution: Bits 7:0 = CONV_DATA[7:0]
6-bit resolution: Bits 7:6 = reserved; bits 5: 0 = CONV_DATA[5:0]
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RM0031 Analog-to-digital converter (ADC)
Address offset: 0x06
Reset value: 0x0F
7 6 5 4 3 2 1 0
Reserved HT[11:8] rw rw rw rw
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0 HT[11: 8] : Analog watchdog higher threshold high
These bits are set/reset by software. They define the MSB of the higher threshold for the analog watchdog.
Address offset: 0x07
Reset value: 0xFF
7 6 5 4 3 2 1 0
HT[7:0] rw rw rw rw rw rw rw rw
Bits 7:0 HT[7:0] : Analog watchdog higher threshold low
These bits are set/reset by software. They define the LSB of the higher threshold for the analog watchdog.
14.6.9 ADC low threshold register high (ADC_LTRH)
Address offset: 0x08
Reset value: 0x00
7 6 5 4 3 2 1 0
Reserved LT[11:8] rw rw rw rw
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0 LT[11: 8] : Analog watchdog lower threshold high
These bits are set/reset by software. They define the MSB of the lower threshold for the analog watchdog.
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Analog-to-digital converter (ADC) RM0031
14.6.10 ADC low threshold register low (ADC_LTRL)
Address offset: 0x09
Reset value: 0x00
7 6 5 4 3 2 1 0
LT[7:0] rw rw rw rw rw rw rw rw
Bits 7:0 LT[7:0] Analog watchdog lower threshold low
These bits are set/reset by software. They define the LSB of the lower threshold for analog watchdog.
Note: The reference voltage threshold data bits are right aligned and their configuration depends on the programmed resolution, as described below:
12-bit resolution
ADC_HTRH & ADC_LTRH Bits 7:4 = reserved ; Bits 3:0 = HT[11:8] or LT[11:8]
ADC_HTRL & ADC_LTRL Bits 7:0 = HT[7:0] or LT[7:0]
10-bit resolution
ADC_HTRH & ADC_LTRH Bits 7:2 = reserved ; Bits 1:0 = HT[9:8] or LT[9:8]
ADC_HTRL & ADC_LTRL Bits 7:0 = HT[7:0] or LT[7:0]
8-bit resolution
ADC_HTRH & ADC_LTRH Bits 7:0 = reserved
ADC_HTRL & ADC_LTRL Bits 7:0 = HT[7:0] or LT[7:0]
6-bit resolution
ADC_HTRH & ADC_LTRH Bits 7:0 = reserved
ADC_HTRL & ADC_LTRL Bits 7:6 = reserved ; Bits 5:0 = HT[5:0] or LT[5:0]
14.6.11 ADC channel sequence 1 register (ADC_SQR1)
Address offset: 0x0A
Reset value: 0x00
7
DMAOFF rw
6
Reserved
-
5
rw
4
CHSEL_
SVREFINT rw
Bits 7 DMAOFF : DMA disable for a single conversion
0: DMA Enabled
1: DMA Disabled
Bit 6 Reserved, forced by hardware to 0.
3 rw
2 1
rw rw
0 rw
RM0031 Rev 15
RM0031 Analog-to-digital converter (ADC)
Bit 5 CHSEL_STS : Selection of channel TS for scan
These bits are set/reset by software. Channel TS must be kept reset.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
Bit 4 CHSEL_SVREFINT : Selection of channel V
REFINT
for scan
These bits are set/reset by software. Channels V
REFINT
must be kept reset.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
CHSEL_S[27:24] : Selection of channels 24 to 27 for scan
(1)
These bits are set/reset by software.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
1. On medium-density devices, bits 3:1 are reserved and bit 0 is the CHSEL_S24 bit (selection of channel 24 for scan).
On STM8L05xx value line devices, bit 5 is reserved and must be kept cleared.
Note: This register must be modified after ADC is enabled by ADON bit in ADC_CR1 register.
14.6.12 ADC channel sequence register 2 (ADC_SQR2)
Address offset: 0x0B
Reset value: 0x00
7 6 5 4 3 rw
CHSEL_S[23:16] rw
2 1 rw rw rw rw rw
Bits 7:0 CHSEL_S[23:16] : Selection of channels 16 to 23 for scan
These bits are set/reset by software.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
0 rw
Note: This register must be modified after ADC is enabled by ADON bit in ADC_CR1 register.
14.6.13 ADC channel select scan 3 (ADC_SQR3)
Address offset: 0x0C
Reset value: 0x00
7 6 5 4 3 rw
CHSEL_S[15:8] rw
2 1 rw rw rw rw rw
Bits 7:0 CHSEL_S[15:8] : Selection of channels 8 to 15 for scan
These bits are set/reset by software.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
0 rw
Note: This register must be modified after ADC is enabled by ADON bit in ADC_CR1 register.
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Analog-to-digital converter (ADC) RM0031
14.6.14 ADC channel select scan 4 (ADC_SQR4)
Address offset: 0x0D
Reset value: 0x00
7 6 5 4 3 rw
CHSEL_S[7:0] rw
2 1 rw rw rw rw rw
Bits 7:0 CHSEL_S[7:0] : Selection of channels 0 to 7 for scan
These bits are set/reset by software.
A value ‘1’ in the CHSEL_Sx bit means that channel x is assigned in the scan sequence.
0 rw
Note: This register must be modified after ADC is enabled by ADON bit in ADC_CR1 register.
Address offset: 0x0E
Reset value: 0x00
7
Reserved
6 5
rw
4
VREFINTON rw
3 rw
2 rw
TRIG[27:24]
1 rw
0 rw
Bits 7:6 Reserved, forced by hardware to 0.
Bit 5 TSON : Temperature sensor internal reference voltage enable
This bit is set/reset by software.
0: Temperature sensor internal reference voltage disabled
1: Temperature sensor internal reference voltage enabled
Bit 4 VREFINTON : Internal reference voltage enable
This bit is set/reset by software.
0: Internal reference voltage disabled
1: Internal reference voltage enabled
Bits 3:0
(1)
TRIG[27:24] : Channels 24 to 27 schmitt trigger disable
These bits are set/reset by software.
A value ‘1’ in the TRIGx bit means that the Schmitt trigger corresponding to channel x is disabled.
1. On medium-density devices, bits 3:1 are reserved and bit 0 is the TRIG24 bit (channel 24 schmitt trigger disabled). On
STM8L05xx value line devices, bit 5 is reserved and must be kept cleared.
RM0031 Rev 15
RM0031 Analog-to-digital converter (ADC)
Address offset: 0x0F
Reset value: 0x00
7 6 5 4 3
TRIG[23:16] rw
2 1 0 rw rw rw
Bits 7:0 TRIG[23:16] : Channels 16 to 23 schmitt trigger disable
These bits are set/reset by software.
A value ‘1’ in the TRIGx bit means that the Schmitt trigger corresponding to channel x is disabled.
Address offset: 0x10
Reset value: 0x00
7 6 5 4 3 2 1 0
TRIG[15:8] rw rw rw rw
Bits 7:0 TRIG[15:8] : Channels 8 to 15 schmitt trigger disable
These bits are set/reset by software.
A value ‘1’ in the TRIGx bit means that the Schmitt trigger corresponding to channel x is disabled.
Address offset: 0x11
Reset value: 0x00
7 6 5 4 3 2 1 0
TRIG(7:0) rw rw rw rw
Bits 7:0 TRIG[7:0] : Channels 0 to 7 schmitt trigger disable
These bits are set/reset by software.
A value ‘1’ in the TRIGx bit means that the schmitt trigger corresponding to channel x is disabled
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Analog-to-digital converter (ADC) RM0031
Table 48. ADC register map
Address offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Register name
ADC_CR1
Reset value
ADC_CR2
Reset value
ADC_CR3
Reset value
ADC_SR
Reset value
ADC_DRH
Reset value
ADC_DRL
Reset value
ADC_HTRH
Reset value
ADC_HTRL
Reset value
ADC_LTRH
Reset value
ADC_LTRL
Reset value
ADC_SQR1
Reset value
ADC_SQR2
Reset value
ADC_SQR3
Reset value
ADC_SQR4
Reset value
ADC_TRIGR1
Reset value
ADC_TRIGR2
Reset value
ADC_TRIGR3
Reset value
ADC_TRIGR4
Reset value
7
-
-
-
HT7
1
-
LT7
0
DMAOFF
0
-
TRIG23
0
TRIG15
0
TRIG7
0
6
-
-
-
HT6
1
-
LT6
0
-
-
TRIG22
0
TRIG14
0
TRIG6
0
1.
This bit is reserved in STM8L05xx value line devices.
2.
This bit is reserved in medium-density devices.
5
OVERIE
0
PRESC
0
SMTP2_2
0
RES[1:0]
00
TRIG_EDG
E1
0
SMTP2_1
0
TRIG_EDG
E0
0
SMTP2_0
0
4
AWDIE
0
EXTSEL1
0
3
EOCIE
0
EXTSEL0
0
2
CONT
0
SMPT1_2
0
1
START
0
SMTP1_1
0
-
-
CHSEL4
1
-
-
CHSEL3
1
-
CHSEL2
1
CHSEL1
1
OVER
0
AWD
0
CONV_DATA[11:8]
0
-
HT5
1
-
LT5
0
CHSEL_ST
S (1)
0
TSON
0
TRIG21
0
TRIG13
0
TRIG5
0
-
-
CONV_DATA[7:0]
0
HT11
1
HT4
1
HT3
1
LT11
0
LT4
0
CHSEL_S
VREFINT
0
LT3
0
CHSEL_S
27
0
CHSEL_S[23:16]
0
CHSEL_S[15:8]
0
CHSEL_S[7:0]
0
VREFINTO
N
0
-TRIG27
0
(2)
TRIG20
0
TRIG12
0
TRIG4
0
TRIG19
0
TRIG11
0
TRIG3
0
0
TRIG18
0
TRIG10
0
TRIG2
0
HT10
1
HT2
1
LT10
0
LT2
0
CHSEL_S
26
0
TRIG25
0
TRIG17
0
TRIG9
0
TRIG1
0
HT9
1
HT1
1
LT9
0
LT1
0
CHSEL_S
0
HT8
1
HT0
1
LT8
0
LT0
0
CHSEL_S
24
0
TRIG24
0
TRIG16
0
TRIG8
0
TRIG0
0
0
ADON
0
SMTP1_0
0
CHSEL0
1
EOC
0
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
This section applies to medium-density STM8L15xx devices, medium+ density STM8L15xx devices and high-density STM8L15xx/STM8L16xx devices, unless otherwise specified.
Digital-to-analog converter (DAC) is not available on STM8L05xxx/STM8L15xxx devices.
The DAC module is a 12-bit voltage output digital-to-analog converter. The DAC can be configured in 8-bit or 12-bit mode and can be used in conjunction with the DMA controller. In
12-bit mode, the data can be left or right aligned. The DAC has one output channel in the medium-density devices and two output channels (each output channel with its own converter) in medium+ and high-density devices. An input reference pin V
REF+ for a better resolution.
is available
In dual DAC channel mode (available on medium+ and high-density devices only), conversions can be performed etiher independently or simultaneously when both channels are grouped together for synchronous update operations.
15.2 DAC main features
• 8-bit or 12-bit monotonic output
• Left of right data alignment in 12-bit mode
• Synchronized update capability
• DMA capability
• External triggers for conversion
• Input voltage reference V
REF+
• Noise-wave generation (medium+ and high-density devices only)
• Triangular-wave generation (medium+ and high-density devices only)
• Dual DAC channel for independent or simultaneous conversions (medium+ and highdensity devices only)
The block diagram of a DAC channel is shown in Figure 47 .
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Digital-to-analog converter (DAC)
Figure 47. DAC channel block diagram (medium-density devices)
RM0031
V
DDA
V
SSA
V
REF+
TSEL [2:0] bits
DAC control register
DMAENx
SWTRIG
TIM4_TRGO
DHR
12-bit
Control logic
DMA request
DMA underrun interrupt
TEN
12-bit
DOR
12-bit
Digital-to-analog converter
DAC_OUT ai15364c
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
Figure 48. DAC channel block diagram (medium+ and high-density devices)
External_TRGO
SWTRIGx
TIM4_TRGO
TIM5_TRGO
V
DDA
V
SSA
V
REF+
TSELx[[2:0] bits
DMAENx
DAC control register
MAMPx[3:0]
DHRx
12-bit
Control logic x
LSFRx Trianglex
DMA request x
DMA underrun interrupts
WAVENx[1:0]
TENx
12-bit
DORx
12-bit
Digital-to-analog converter x
DAC_OUTx ai17848
15.3 DAC functional description
15.3.1 DAC channel x enable
Digital-to-analog conversions can be performed only if the DAC channels have been powered on by setting the EN bit in the DAC_CHxCR1 register. The DAC channels are then enabled after a t
WAKEUP startup time (refer to the product datasheet).
15.3.2 DAC output buffer enable
The DAC integrates one output buffer (on medium-density devices) or two output buffers (on medium+ and high-density devices) that can be used to reduce the output impedance and to drive external loads directly without having to add an external operational amplifier. It can be enabled and disabled using the BOFF bit in the DAC_CHxCR1 register.
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Digital-to-analog converter (DAC) RM0031
15.3.3 DAC output switch configuration
The following table describes the DAC output switch configuration depending on devices and packages.
See also Figure 24: Routing interface (RI) block diagram (medium-density devices)
.
Table 49. DAC output switch configuration (medium and medium+ and high-density devices)
Packages
Configuration on medium-density devices
Configuration on medium+ and high-density devices
64-pin and 80-pin packages
48-pin packages
28-pin and 32-pin packages
N/A
DAC_OUT1 is connected to PF0.
DAC_OUT2 is connected to PF1.
DAC_OUT1 is connected PF0.
DAC_OUT1 can be connected to PB4,
PB5 or PB6 by closing the corresponding RI switches
(see Figure 23: Routing interface (RI) block diagram
(medium+ and high-density devices) ).
N/A
DAC_OUT1 is connected to PF0
DAC_OUT2 can be connected to
PB4, PB5 or PB6 by closing the corresponding RI switches (1) (see
Figure 23: Routing interface (RI) block diagram (medium+ and high-density devices) ).
1. DAC output buffer must be kept off and no load must be applied on the DAC output.
Depending on the selected configuration mode, the data has to be written in the specified register as described below:
• 8-bit right alignment: data to be loaded to DAC_DHR8 [7:0] bits by converted data[11:4]
• 12-bit left alignment: data to be loaded to DAC_LDHRH [7:0] bits by the converted data[11:4] and the DAC_LDHRL[7:4] bits by the converted data [3:0]
• 12-bit right alignment: data to be loaded to DAC_RDHRH [3:0] bits by the converted data[11:8] and the DAC_RDHRL[7:0] bits by the converted data [7:0]
15.3.5 DAC conversion sequence
To start a conversion, the content of the DAC_xDHRx and DAC_DHR8 registers is moved to the DAC_CHxDORH/L (data output) registers. Depending on the TEN bit in the
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
DAC_CHxCR1 register, this transfer to DAC_CHxDORH/L can be performed in two different manners:
• TEN = 0. The transfer is performed when:
– DAC_DHR8 is written for 8-bit conversion data in single mode
– LSB of DAC_xDHRL is written for 12-bit conversion data in single mode,
• TEN = 1. The transfer is performed when a trigger occurs. Two different triggers
(TIM4_TRGO or SWTRIG) in the medium-density devices or three triggers
(TIM4_TRGO, TIM5_TRGO or SWTRIG) can be selected through the TSEL bits in the
DAC_CHxCR1 register. Refer to Section 15.3.7: DAC trigger selection .
Note:
Digital inputs are converted to output voltages on a linear conversion between 0 and V
REF+
The analog output voltages on the DAC_OUTx pin are determined by the following
. equation:
DAC_OUT x = V
REF
×
4096
If the TEN bit is set in the DAC_CHxCR1 register, the following events can trigger a conversion:
• a software trigger (SWTRIG)
• one external event (TIM4_TRGO: Timer 4 counter channel output) in medium-density devices
• three external events (TIM4_TRGO, TIM5_TRGO or external pin) in medium + and high-density devices.
The TSEL[2:0] bits can be used to determine which out of the 2 or 4 possible sources will trigger a conversion (SWTRIG or TIM4_TRGO in medium-density devices and SWTRIG,
TIM4_TRGO, TIM5_TRGO or external pin in medium+ and high-density devices):
• If the software trigger (SWTRIG) is selected, the conversion starts once the SWTRIGx bit is set in the DAC_SWTRIGR. This bit is reset by hardware once the DAC_DORx registers are loaded with the DAC_xDHRx values.
• If TIM4_TRGO, TIM5_TRGO or external pin is selected, the data transfer is synchronized by a two-stage rising edge synchronizer
TSEL[2:0] bits cannot be changed when the EN bit is set in the DAC_CHxCR1 register.
Refer to the following table.
Table 50. Sources of conversion trigger (medium, medium+ and high-density devices)
Medium- density
Medium+ and high-density
Timer 4 TRGO event Internal signal from on-chip
Timer 5 TRGO event timers
PA4 GPIO External pin
000
001
010
X
-
-
X
X x
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Digital-to-analog converter (DAC) RM0031
Table 50. Sources of conversion trigger (medium, medium+ and high-density devices)
Medium- density
Medium+ and high-density
NA (reserved)
SWTRIG
-
Software control bit
011
100
101
110
111
-
-
-
-
X
-
-
-
-
X
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
A DAC channel DMA request is generated when an external trigger occurs while the TEN and DMAENx bits are set. The DAC channel DMA request remains set until a DAC channel
DMA Acknowledge comes from the DMA controller. The DAC channel DMA request indicates that DACx_DHRx registers have been transferred to the DAC_CHxDORH/L registers.
DAC channel DMA request is not kept in a request queue, so if a second external trigger arrives before the DMA receives the acknowledge for the first external trigger, no new request is serviced and no error is reported.
15.3.9 DAC DMA underrun interrupt
A DAC DMA underrun interrupt is generated in DMA mode when the next trigger event occurs while the previous DMA request is still pending. This may happen, for instance, when the DAC trigger frequency is higher than the DMA request servicing process.
For each DAC channel, DMA underrun interrupt can be enabled or disabled through the
DMAUDRIE bits in DAC_CHxCR2 register. If it occurs, it is signalled by the DMAUDR bits in the DAC_SR register.
In order to generate a variable-amplitude pseudonoise, a linear feedback shift register
(LFSRx) register is available. The DAC noise generation is enabled by setting
DAC_CHxCR1/WAVEN to “01” and TENx to 1 in the DAC_CHxCR1 register. The preloaded value in LFSR is 0xAAA, and the LFSRx output is updated at each conversion. This register is updated three CPU clock cycles after each trigger event, following a specific calculation algorithm (see
Figure 49: DAC LFSR register calculation algorithm on page 231
).
If LFSRx is 0x000, a ‘1’ is injected into it (antilock-up mechanism).
The LFSRx value, that may be masked partially or totally by means of the
DAC_CHxCR2/MAMP bits in the DAC_CHxCR2, is added to the DAC_DHRx (which can be
DAC_CHxRDHRH/L or DAC_CHxLDHRH/L or DAC_CHxDHR8 register depending on the selected data format) contents without overflow and this value is then stored into the
DAC_CHxDORH/L register (see the following figure).
RM0031 Rev 15
RM0031
Note:
Digital-to-analog converter (DAC)
Figure 49. DAC LFSR register calculation algorithm
XOR
X
12
11 10 9 8 7
X
6
6 5
X
4
4 3 2 1
X
0
X
0
12
NOR ai14713c
It is possible to reset LFSRx wave generation by resetting the DAC_CHxCR1/WAVEN[1:0] bits.
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CHxCR1 register.
Note:
It’s possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected DAC_CH2CR1/TSELsetting
DAC_CHxCR1/WAVEN[1:0] to “10” and DAC_CHxCR1/TEN bits to 1 The amplitude is configured through the DAC_CHxCR2/MAMP[3:0] bits in the DAC_CHxCR2 register. A 12bit internal triangle counter is incremented three CPU clock cycles after each trigger event.
The value of this counter is then added to the DAC_DHRx (which can be
DAC_CHxRDHRH/L or DAC_CHxLDHRH/L or DAC_CHxDHR8 register depending on the selected data format) without overflow and the sum is stored into the DAC_CHxDORH/L.
The triangle counter is incremented while it is less than the maximum amplitude defined by the DAC_CHxCR2/MAMP[3:0] bits (refer to DAC_CHxCR2).Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on till
WAVENx[1:0]=”10” and TENx=’1’ ( Figure 50.
It is possible to reset triangle wavex generation by resetting DAC_CHxCR1/WAVEN.
DAC_CHxCR2/MAMP[3:0] bits cannot be changed when the DAC_CHxCR1/EN bit is set.
Figure 50. DAC triangle wave generation
MAMPx[3:0] max amplitude
+ DAC_DHRx base value
Decrementation
Incrementation
DAC_DHRx base value
0 ai14715c
1. The DAC trigger must be enabled for triangle generation by setting the TENx bit in the DAC_CHxCR1 register.
2. The DAC_CH1CR2/MAMP[3:0] bits must be configured before enabling the DAC. Otherwise, they cannot be changed.
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Digital-to-analog converter (DAC) RM0031
15.3.12 Dual DAC conversion
To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented. A unique register access is then required to drive both DAC channels at the same time.
Nine possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.
All modes (independent and simultaneous modes) are described in the paragraphs below.
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure different trigger sources by setting different values in the
DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Load the dual DAC channel data into the desired DAC_DHRx register (which can be
DAC_CHxRDHRH/L or DAC_CHxLDHRH/L or DAC_CHxDHR8 register depending on the selected data format).
When a DAC channel1 trigger arrives, the DAC_DHR1 (which can be DAC_CH1RDHRH/L or DAC_CH1LDHRH/L or DAC_CH1DHR8 register depending on the selected data format) register is transferred into DAC_CH1DORH/L (three CPU clock cycles later).
When a DAC channel2 trigger arrives, the DAC_DHR2(which can be DAC_CH2RDHRH/L or DAC_CH2LDHRH/L or DAC_CH2DHR8 register depending on the selected data format) register is transferred into DAC_CH2DORH/L (three CPU clock cycles later).
Independent trigger with same LFSR generation
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure different trigger sources by setting different values in the
DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “01” and the same LFSR mask value in the DAC_CHxCR2/MAMP[3:0] bits
• Load the dual DAC channel data into the desired DAC_DHRx register (which can be
DAC_CHxRDHRH/L or DAC_CHxLDHRH/L or DAC_CHxDHR8 register depending on the selected data format)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask/amplitude, is added to the DAC_DHR1(which can be DAC_CH1RDHRH/L or DAC_CH1LDHRH/L or
DAC_CH1DHR8 register depending on the selected data format) register and the sum is transferred into DAC_DOR1. Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DAC_DHR2(which can be DAC_CH2RDHRH/L or DAC_CH2LDHRH/L or
DAC_CH2DHR8 register depending on the selected data format) register and the sum is transferred into DAC_DOR2. Then, the LFSR2 counter is updated.
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
Independent trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure different trigger sources by setting different values in the
DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “01” and set different LFSR masks values in the DAC_CH1CR2/MAMP[3:0] and DAC_CH2CR2/MAMP[3:0] bits
• Load the dual DAC channel data into the desired DHR register
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
DAC_CH1CR2/MAMP[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three CPU clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
DAC_CH2CR2/MAMP[3:0], is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three CPU clock cycles later). Then the LFSR2 counter is updated.
Independent trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure different trigger sources by setting different values in the
DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “1x” and set different maximum amplitude values in the DAC_CH1CR2/MAMP[3:0] and DAC_CH2CR2/MAMP[3:0] bits
• Load the dual DAC channel data into the desired DHR register
When a DAC channel1 trigger arrives, the 12-bit DAC channel1 triangle counter, with a triangle amplitude configured by DAC_CH1CR2/MAMP[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three CPU clock cycles later). The 12-bit DAC channel1 triangle counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by DAC_CH2CR2/MAMP[3:0], is added to the DHR2 register part and the sum is transferred into DAC_DOR2 (three CPU clock cycles later). The DAC channel2 triangle counter is then updated.
Simultaneous trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure the same trigger source for both DAC channels by setting the same value in the DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Load the dual DAC channel data to the desired DHR register
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three CPU clock cycles).
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
Simultaneous trigger with same LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure the same trigger source for both DAC channels by setting the same value in the DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “01” and the same LFSR mask value in the DAC_CH1CR2/MAMP[3:0] bits
• Load the dual DAC channel data to the desired DHR register
When a trigger arrives, the LFSR1 counter, with the mask configured by
DAC_CH1CR2/MAMP[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by
DAC_CH2CR2/MAMP[3:0], is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three CPU clock cycles later). The LFSR2 counter is then updated.
Simultaneous trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure the same trigger source for both DAC channels by setting the same value in the DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “01” and set different LFSR masks values using the DAC_CH1CR2/MAMP[3:0] and DAC_CH2CR2/MAMP[3:0] bits
• Load the dual DAC channel data into the desired DHR register
When a trigger arrives, the LFSR1 counter, with the mask configured by
DAC_CH1CR2/MAMP[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three CPU clock cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by
DAC_CH2CR2/MAMP[3:0], is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three CPU clock cycles later). The LFSR2 counter is then updated.
Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
• Set the two DAC channel trigger enable bits DAC_CH1CR1/TEN and
DAC_CH2CR1/TEN
• Configure the same trigger source for both DAC channels by setting the same value in the DAC_CH1CR1/TSEL[2:0] and DAC_CH2CR1/TSEL[2:0] bits
• Configure the two DAC channel WAVENx[1:0] bits as “1x” and set different maximum amplitude values in the DAC_CH1CR2/MAMP[3:0] and DAC_CH2CR2/MAMP[3:0] bits
• Load the dual DAC channel data into the desired DHR register
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by DAC_CH1CR2/MAMP[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three CPU clock cycles later). Then the DAC channel1 triangle counter is updated.
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by DAC_CH2CR2/MAMP[3:0], is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three CPU clock cycles later). Then the DAC channel2 triangle counter is updated.
Simultaneous software start
To configure the DAC in this conversion mode, the following sequence is required:
• Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
In this configuration, one CPU clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively.
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
15.4.1 DAC channel x control register 1 (DAC_CHxCR1)
-
-
7
Address offset: 0x00 (channel 1) or 0x02 (channel 2 available on high devices only)
Reset value: 0x00
6 5 4 3 2 1 0
-
-
-
-
TSEL[2:0] rw rw rw rw
TEN rw rw
BOFF rw rw
EN rw rw
Bits 7:6
WAVEN[1:0] : DAC channel x noise/triangle waveform generation enable.
These bits are used only if TEN1=1.
00: Wave generation disabled.
01: Noise generation enabled.
1x: Triangle generation enabled.
Bits 5:3 TSEL[2:0] : DAC channel x trigger selection.
These bits are only used if TEN=1.
000: TIM4_TRGO (Timer 0 counter channel output) selected
001: Reserved
010: Reserved
001
(1)
: TIM5_TRGO selected
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: SWTRIG (Software trigger) selected
Bit 2 TEN : DAC channel trigger enable.
0: The data written into the data holding register (DHR) is transferred one CPU clock cycle later to the data output register (DORx).
1: The data transfer from the DHRx to the DORx is synchronized by the selected trigger.
Bit 1 BOFF : DAC channel output buffer disable.
0: DAC Channel output buffer enabled
1: DAC Channel output buffer disabled
Bit 0 EN : DAC channel enable.
0: DAC channel disabled
1: DAC channel enabled
1. Reserved on medium-density devices
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
15.4.2 DAC channel x control register 2 (DAC_CHxCR2)
Address offset: 0x01 (channel 1) or 0x03 (channel 2 available on medium+ and high-density devices only)
7
Reset value: 0x00
6 5
DMAUDRIE
Reserved rw
1. Reserved on medium-density devices
4
DMAEN rw
3
-
2
-
MAMP[3:0] (1)
1
-
0
-
Bits 7:6 Reserved, forced by hardware at 0.
Bit 5 DMAUDRIE : DAC channel DMA underrun interrupt enable.
0: DMA underrun interrupt disabled.
1: DMA underrun interrupt enabled.
Bit 4 DMAEN : DAC DMA enable.
0: DMA disabled.
1: DMA enabled.
Bits 3:0
(1)
MAMP[3:0] : DAC channel x mask/amplitude selector.
0000: UnMask bit(0) of LFSR bit/ 2^1-1 triangle amplitude
0001: UnMask bit(1:0) of LFSR bit/ 2^2-1 triangle amplitude
0010: UnMask bit(2:0) of LFSR bit/ 2^3-1 triangle amplitude
0011: UnMask bit(3:0) of LFSR bit/ 2^4-1 triangle amplitude
0100: UnMask bit(4:0) of LFSR bit/ 2^5-1 triangle amplitude
0101: UnMask bit(5:0) of LFSR bit/ 2^6-1 triangle amplitude
0110: UnMask bit(6:0) of LFSR bit/ 2^7-1 triangle amplitude
0111: UnMask bit(7:0) of LFSR bit/ 2^8-1 triangle amplitude
1000: UnMask bit(8:0) of LFSR bit/ 2^9-1 triangle amplitude
1001: UnMask bit(9:0) of LFSR bit/ 2^10-1 triangle amplitude
1010: UnMask bit(10:0) of LFSR bit/ 2^11-1 triangle amplitude
1x1x: UnMask bit(11:0) of LFSR bit/ 2^12-1 triangle amplitude
1. Reserved on medium-density devices.
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
Address offset: 0x04
Reset value: 0x00
6 5 7
Reserved
4 3 2 1
SWTRIG2 (1) rs
0
SWTRIG1 rs
1. Reserved on medium-density devices.
Bits 7:2 Reserved, forced by hardware to 0.
Bit 1
(1)
SWTRIG2 : DAC channel 2 software trigger.
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disable
1: Software trigger enable
This bit is present only if the dual DAC is implemented (dual=1), otherwise it is forced to 0 by hardware.
Bit 0 SWTRIG1 : DAC channel 1 software trigger.
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disable
1: Software trigger enable
Note: This bit is reset by hardware once the DAC_DHRx register value is loaded to the
DAC_DORx register
1. Reserved on medium-density devices.
15.4.4 DAC status register (DAC_SR)
7
Address offset: 0x05
Reset value: 0x00
6 5 4
Reserved
1. Reserved on medium-density devices.
3 2 1
DMAUDR2 (1)
-
0
DMAUDR1 rc_w0
Bits 7:2 Reserved, forced by hardware at 0.
Bit 1
(1)
DMAUDR2 : DAC channel DMA underrun flag.
0: No DMA underrun condition is detected.
1: DMA underrun condition detection.
This bit is present only if the dual DAC is implemented. Otherwise, it is forced to 0 by hardware.
Note: This bit generates the DMA underrun interrupt.
Bit 0 DMAUDR1 : DAC channel DMA underrun flag.
0: No DMA underrun condition is detected.
1: DMA underrun condition detection.
Note: This bit generates the DMA underrun interrupt.
1. Reserved on medium-density devices.
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
15.4.5 DAC channel x right aligned data holding register high
(DAC_RDHRH)
7
Address offset: 0x08 (channel 1) or 0x14 (channel 2 available on medium + and highdensity devices only)
Reset value: 0x00
6 5 4 3 2 1 0
RDHRH[3:0]
Reserved rw rw rw rw
Bits 7:4 Reserved, forced by hardware at 0.
Bits 3:0 RDHRH[3:0] : DAC right aligned data holding register most significant bits.
These bits will be loaded as the 4 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
15.4.6 DAC channel x right aligned data holding register low
(DAC_CHxRDHRL)
7 rw
Address offset: 0x09 (channel 1) or 0x15 (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6 5 4 3 2 1 0
RDHRL[7:0] rw rw rw rw rw rw rw
Bits 7:0 RDHRL[7:0] : DAC right aligned data holding register least significant bits.
These bits will be loaded as the 8 least significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TEN is not set, write to this register triggers the 12-bit parallel load of DHRx by
RDHRH + RDHRL
15.4.7 DAC channel x left aligned data holding register high
(DAC_CHxLDHRH)
7 rw
Address offset: 0x0C (channel 1) or 0x18 (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6 5 4 3 2 1 0
LDHRH rw rw rw rw rw rw rw
Bits 7:0 LDHRH[7:0] : DAC left aligned data holding register most significant bits.
These bits will be loaded as the 8 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
15.4.8 DAC channel x left aligned data holding register low
(DAC_CHxLDHRL)
7 rw
Address offset: 0x0D (channel 1), 0x19 (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6
LDHRL[7:4] rw
5 rw
4 rw
3 2
Reserved
1 0
Bits 7:4 LDHRL[7:4] : DAC channel x left aligned data holding register least significant bits.
These bits will be loaded as the 4 least significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TENx is not set, write to this register triggers the 12-bits parallel load of DHRx by
LDHRH + LDHRL.
Bits 3:0 Reserved, forced by hardware at 0.
15.4.9 DAC channel x 8-bit data holding register
(DAC_CHxDHR8)
7 rw
Address offset: 0x10 (channel 1) or 0x1C (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6 5 4 3 2 1 0
8DHR rw rw rw rw rw rw rw
Bits 7:0 8DHR[7:0] : DAC 8-bit data holding register.
These bits will be loaded as the 8 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TEN is not set, writing to this register triggers the 8-bit load of DHR by DHR8[11:4]. 4
LSBits of DHR buffer keep unchanged.
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
15.4.10 DAC channel x dual mode right aligned data holding register high
(DAC_DCHxRDHRH)
Note:
Address offset: 0x20 (channel 1) or 0x22 (channel 2)
Reset value: 0x0000 000
This register is available on medium+ and high-density devices only.
7 6 5 4 3 2 1 0
RDHRH[3:0]
Reserved rw rw rw rw
Bits 7:4 Reserved, forced by hardware at 0.
Bits 3:0 RDHRH[3:0] : DAC channel x dual mode right aligned data holding register most significant bits.
These bits will be loaded as the 4 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
15.4.11 DAC channel x dual mode right aligned data holding register low
(DAC_DCHxRDHRL)
Note:
Address offset: 0x21 (channel1) or 0x23 (channel2)
Reset value: 0x0000 0000
This register is available on medium+ and high-density devices only.
7 6 5 4 3 2 1 0
RDHRL[7:0] rw rw rw rw rw rw rw rw
Bits 7:0 RDHRL[7:0]: DAC channel x right aligned data holding register least significant bits.
These bits will be loaded as the 8 least significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TEN is not set, write to DAC_DCH2RDHRL register triggers the 12-bits parallel load of both DHRx by DAC_DCHxRDHRH + DAC_DCHxRDHRL
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
15.4.12 DAC channel x dual mode left aligned data holding register high
(DAC_DCHxLDHRH)
Note:
Address offset: 0x24 (channel 1), 0x26 (channel 2)
Reset value: 0x0000 0000
This register is available on medium+ and high-density devices only.
7 6 5 4 3 2 1 0
LDHRH rw rw rw rw rw rw rw rw
Bits 7:0 LDHRH[7:0] : DAC channel x dual mode left aligned data holding register most significant Bits.
These bits will be loaded as the 8 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
15.4.13 DAC channel x left aligned data holding register low
(DAC_DCHxLDHRL)
Note:
Address offset: 0x25 (Channel1), 0x27 (Channel2)
Reset value: 0x0000 0000
This register is available on medium+ and high-density devices only.
7 6 5 4 3 2
LDHRL[7:4]
Reserved rw rw rw rw
1 0
Bits 7:4 LDHRL[7:4]: DAC channel x data holding register left aligned data least significant bits.
These bits will be loaded as the 4 least significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TEN is not set, write to DAC_DCH2LDHRL register triggers the 12-bits parallel load of both DHRx by DAC_DCHxLDHRH + DAC_DCHxLDHRL.
Bits 3:0 Reserved, forced by hardware at 0.
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
15.4.14 DAC channel x dual mode 8-bit data holding register
(DAC_DCHxDHR8)
Note:
Address offset: 0x28 (channel1) or 0x29 (channel2)
Reset value: 0x0000 0000
This register is available on medium+ and high-density devices only.
7 6 5 4 3 2 1
8DHR rw rw rw rw rw rw rw
0 rw
Bits 7:0 8DHR[7:0]: DAC channel x dual mode 8-bit data holding register.
These bits will be loaded as the 8 most significant bits of the 12-bit digital-to-analog conversion data stored into DHR.
Note: If TEN is not set, write to DAC_DCH2DHR8 register triggers the 8bit load of both
DHRx[11:4] by DAC_DCHxDHR8. 4LSB of DHRx buffers keep unchanged.
15.4.15 DAC channel x data output register high
(DAC_CHxDORH)
7
Address offset: 0x2C (channel 1) or 0x30 (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6 5 4 3 2 1 0
DORH[3:0]
Reserved r r r r
Bits 7:4 Reserved, forced by hardware at 0.
Bits 3:0 DORH[3:0] : DAC data output register most significant bit.
4 most significant bits of digital data currently under conversion.
15.4.16 DAC channel x data output register low
(DAC_CHxDORL)
7 r
Address offset: 0x2D (channel 1), 0x31 (channel 2 available on medium+ and high-density devices only)
Reset value: 0x00
6 5 4 3 2 1 0
DORL r r r r r r r
Bits 7:0 DORL[7:0] : DAC data output register least significant bit.
8 least significant bits of digital data currently under conversion.
RM0031 Rev 15
245
Digital-to-analog converter (DAC) RM0031
0x19
0x1A to 0x1B
0x1C
0x1D to 0x1F
0x20
0x0D
0x0E to 0x0F
0x10
0x11 to 0x13
0x14
Address offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06 to
0x07
0x08
0x09
0x0A to
0x0B
0x0C
Table 52. DAC register map (medium, medium+ and high-density devices)
Register name
7 6 5 4 3 2 1
WAVEN[2:0]
(1)
0
DAC_CH1CR1
Reset value
DAC_CH1CR2
Reset value
DAC_CH2CR1
Reset value
DAC_CH2CR2
Reset value
DAC_SWTRIGR
Reset value
DAC_SR
Reset value
-
-
-
-
WAVEN[2:0]
0
-
-
-
-
DMAUDRIE
0
TSEL[2:0]
0
DMAEN
0
DMAUDRIE
0
TSEL[2:0]
0
DMAEN
0
-
-
-
-
-
-
0
TEN
0
BOFF
0
MAMP[3:0]
0
TEN
0
BOFF
0
MAMP[3:0]
0
-
-
EN
0
EN
0
SWTRIG1
0
DMAUDR1
0
Reserved area
DAC_CH1RDHRH
Reset value
DAC_CH1RDHRL
Reset value
-
RDHRL7
0
-
RDHRL6
0
RDHRH3
0
RDHRL3
0
RDHRH2
0
RDHRL2
0
RDHRH1
0
RDHRL1
0
RDHRH0
0
RDHRL0
0
DAC_CH1LDHRH
Reset value
DAC_CH1LDHRL
Reset value
DAC_CH1DHR8
Reset value
LDHRH7
0
LDHRL7
0
8DHR7
0
LDHRH6
0
LDHRL6
0
8DHR6
0
-
RDHRL5
0
RDHRL4
0
Reserved area
LDHRH5
0
LDHRL5
0
LDHRH4
0
LDHRL4
0
8DHR5
0
Reserved area
8DHR4
0
Reserved area
LDHRH3
0
-
8DHR3
0
LDHRH2
0
-
8DHR2
0
LDHRH1
0
-
8DHR1
0
LDHRH0
0
-
8DHR0
0
DAC_CH2RDHRH
Reset value
DAC_CH2RDHRL
Reset value
-
RDHRL7
0
-
RDHRL6
0
RDHRH3
0
RDHRL3
0
RDHRH2
0
RDHRL2
0
RDHRH1
0
RDHRL1
0
RDHRH0
0
RDHRL0
0
0x15
0x16 to 0x17
0x18
DAC_CH2LDHRH
Reset value
DAC_CH2LDHRL
Reset value
DAC_CH2DHR8
Reset value
LDHRH7
0
LDHRL7
0
8DHR7
0
LDHRH6
0
LDHRL6
0
8DHR6
0
-
RDHRL5
0
RDHRL4
0
Reserved area
LDHRH5
0
LDHRL5
0
LDHRH4
0
LDHRL4
0
8DHR5
0
Reserved area
8DHR4
0
Reserved area
LDHRH3
0
-
8DHR3
0
LDHRH2
0
-
8DHR2
0
LDHRH1
0
-
8DHR1
0
LDHRH0
0
-
8DHR0
0
DAC_DCH1RDHRH
Reset Value
-
RDHRH3
0
RDHRH2
0
RDHRH1
0
RDHRH0
0
RM0031 Rev 15
RM0031 Digital-to-analog converter (DAC)
Table 52. DAC register map (medium, medium+ and high-density devices) (continued)
Address offset
Register name
7 6 5 4 3 2 1 0
RDHRL6
0
RDHRL5
0
RDHRL4
0
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
DAC_DCH1RDHRL
Reset Value
DAC_DCH2RDHRH
Reset Value
DAC_DCH2RDHRL
Reset Value
DAC_DCH1LDHRH
Reset Value
DAC_DCH1LDHRL
Reset Value
DAC_DCH2LDHRH
Reset Value
DAC_DCH2LDHRL
Reset Value
DAC_DCH1DHR8
Reset Value
DAC_DCH2DHR8
Reset Value
RDHRL7
0
-
0x2A to
0x2B
0x2C
0x2D
DAC_CH1DORH
Reset value
DAC_CH1DORL
Reset value
-
DORL7
0
0x2E to 0x2F
0x30
0x31
DAC_CH2DORH
Reset value
DAC_CH2DORL
Reset value
-
DORL7
0
0x32 to 0x35
1.
Reserved on medium-density devices.
RDHRL7
0
LDHRH7
0
LDHRL7
0
LDHRH7
0
LDHRL7
0
8DHR7
0
8DHR7
0
-
RDHRL6
0
LDHRH6
0
LDHRL6
0
LDHRH6
0
LDHRL6
0
8DHR6
0
8DHR6
0
-
DORL6
0
-
DORL6
0
-
RDHRL5
0
LDHRH5
0
LDHRL5
0
LDHRH5
0
LDHRL5
0
8DHR5
0
8DHR5
0
-
DORL5
0
-
DORL5
0
-
RDHRL4
0
LDHRH4
0
LDHRL4
0
LDHRH4
0
LDHRL4
0
8DHR4
0
8DHR4
0
Reserved area
-
DORL4
0
Reserved area
-
DORL4
0
Reserved area
RDHRL3
0
RDHRH3
0
RDHRL3
0
LDHRH3
0
-
LDHRH3
0
-
8DHR3
0
8DHR3
0
DORH3
0
DORL3
0
DORH3
0
DORL3
0
RDHRL2
0
RDHRH2
0
RDHRL2
0
LDHRH2
0
-
LDHRH2
0
-
8DHR2
0
8DHR2
0
DORH2
0
DORL2
0
DORH2
0
DORL2
0
RDHRL1
0
RDHRH1
0
RDHRL1
0
LDHRH1
0
-
LDHRH1
0
-
8DHR1
0
8DHR1
0
DORH1
0
DORL1
0
DORH1
0
DORL1
0
RDHRL0
0
RDHRH0
0
RDHRL0
0
LDHRH0
0
-
LDHRH0
0
-
8DHR0
0
8DHR0
0
DORH0
0
DORL0
0
DORH0
0
DORL0
0
RM0031 Rev 15
245
Comparators (COMP) RM0031
This section applies to STM8L050xxx devices, low-density STM8L15xxx devices, mediumdensity STM8L15xxx devices, medium+ density STM8L15xxx devices and high-density
STM8L15xxx/STM8L16xxx devices, unless otherwise specified.
Note:
The STM8L15xx and STM8L050xx contain two zero-crossing comparators COMP1 and
COMP2 that share the same current bias.
For all I/Os used as comparator inputs, the configuration in the GPIO registers must be remain input floating.
.
16.2 COMP main features
• One comparator (COMP1) with fixed threshold (internal reference voltage). The noninverting input can be selected from 25 (medium-density devices) or 28 (medium+ and high-density devices) external I/Os.
• One rail-to-rail comparator (COMP2) with selectable threshold. The non-inverting input can be selected from three I/Os. The threshold can be selected from:
– Internal reference voltage V
REFINT
– Internal reference voltage submultiple (1/4, 1/2, 3/4)
– DAC output
– One of three external I/Os.
• The 2 comparators can be combined into window comparators.
• A zero-crossing can generate a rising edge or a falling edge on comparator outputs depending on a polarity bit
• Each comparator can generate an interrupt with wakeup from Halt capability
• COMP2 output can be redirected to TIM1 BRK or OCREFCLR inputs, or TIM2/TIM3
Input Capture 2.
• COMP2 speed is configurable for optimum speed/consumption ratio.
The block diagram is shown on Figure 1 .
RM0031 Rev 15
RM0031
16.3 Comparator 1 (COMP1)
shows the comparator 1 interconnections.
Figure 51. COMP1 interconnections
Comparators (COMP)
Note:
Group 1 of 3 I/Os
CH1
CH2
CH3
Group 8 of 3 I/Os
CH1
CH2
CH3
AS0
AS1
AS2
AS3
AS4
AS5
AS6
AS7
PF1 1)
PF2 1)
PF3 1)
NC
NC
AS10
AS11
AS12
AS13
AS14
CMP1[1:0] bits
+
V
REFINT
COMP1
-
VREFEN
bit
Bias from internal reference voltage
EF1
IE1 bit to COMP2
Wakeup
Interrupt
1. On medium+ and high-density devices only.
COMP1 and ADC cannot be used simultaneously except for Group 8 of I/Os (PD1, PD0,
PE5) when comparators "Window mode" is selected. As soon as ADC is enabled, AS[14:0] switches are controlled individually by ADC peripheral and only one switch is closed at a time.
To use the COMP1 comparator, the application must perform the following steps:
1.
Set the VREFEN bit in COMP_CSR3 register to connect VREFINT to comparator 1 inverting input.
2. Close the analog switches to create the path from selected I/O to the non-inverting input:
– Close analog switch number 14 by setting the AS14 bit in the RI_ASCR2 register.
– Close analog switch number ‘n’ corresponding to the I/O group (refer to Table 27 ), by setting the ASx bit in the RI_ASCR1 or RI_ASCR2 register
3. Close the I/O switch of the I/O to be connected to the COMP1 non-inverting input. The input can be any of the 24 I/Os from the 8 groups of 3 I/Os (refer to Table 27 ).
– Select the correct I/O port by setting the corresponding CHxE bit in the I/O switch registers: RI_IOSR1, RI_IOSR2 or RI_IOSR3 (refer to Table 27 )
4. If required, enable the COMP1 interrupt by setting the IE1 bit in the COMP_CSR1 register edges using the CMP1[1:0] bits in the COMP_CSR1 register.
RM0031 Rev 15
256
Comparators (COMP)
Note: The channel can be changed once the comparator is enabled.
The step 3 is not applicable for PF0, PF1, PF2 and PF3.
RM0031
16.4 Comparator 2 (COMP2)
shows the comparator 2 interconnections.
Figure 52. COMP2 interconnections
Note:
Wakeup
CMP2[1:0] bits
PD1
PD0
PE5
+
COMP2
-
EF2
Interrupt
From DAC1
IE2 bit
I/O ports
PC7
PC4
PC3
PC2
PD7
PD6
V
REFINT
3/4 V
REFINT
1/2 V
REFINT
1/4 V
REFINT
Internal reference voltage
COMP2 and ADC cannot be used simultaneously except for Group 8 of I/Os (PD1, PD0,
PE5). As soon as ADC is enabled, AS[14:0] switches are controlled individually by ADC peripheral and only one switch is closed at a time.
To use the COMP2 comparator, perform the following steps:
1.
Select the COMP2 Inverting Input with the INSEL[2:0] bits in the COMP_CSR3 register.
– To select an external I/O (any I/O in of group 2), close the I/O channel switch by setting the CH4E bit in the RI_IOSR1, the CH5E bit in the RI_IOSR2 or the CH6E bit in the RI_IOSR3 register (see Table 27 ).
2. Close the I/O channel switch to connect the I/O to the COMP2 non-inverting input. The input can be from any I/O in group 8 (see Table 27 ).
– Set the CH22E bit in the RI_IOSR1 register, the CH23E bit in the RI_IOSR2 or the
CH24E bit in the RI_IOSR3 register.
3. If required, perform the following procedures:
– Select the speed with the SPEED bit in COMP_CSR2 register.
– Redirect the COMP2 output to timer 1, 2 or 3 by configuring the OUTSEL[1:0] bits in the COMP_CSR3 register (see
– Enable the COMP2 interrupt by setting the IE2 bit in the COMP_CSR2 register.
4. To detect rising edge, falling edge or both rising and falling edges using the CMP2[1:0] bits in the COMP_CSR2 register.
RM0031 Rev 15
RM0031
Note:
Comparators (COMP)
The channel can be changed once the comparator is enabled.
Figure 53. COMP2 output redirection
Wakeup
CMP2[1:0] bits
COMP2
+
–
EF2
IE2 bit
Comparator 2 interrupt
TIM2 input capture
TIM3 input capture
TIM1 break input
TIM1 OCref clear
OUTSEL[1:0] bits ai15872b
16.5 Using comparators in window mode
Figure 54. Configuring the comparators in window mode
Upper threshold: V
REFINT
–
COMP1
VREFEN bit
WNDWE
+
Note:
PD1
PD0
PE5
V
IN
+
Lower threshold: Multiple src, inc. programmable V
REFINT
–
COMP2 ai15873c
In window mode, only the Group 8 (PD0, PD1 and PE5) can be used as a non-inverting input.
To use the COMP1 and COMP2 comparators in window mode, perform the following steps:
RM0031 Rev 15
256
Comparators (COMP) RM0031
1.
Set the VREFEN bit in COMP_CSR3 register to connect VREFINT to comparator 1 inverting input.
2. Select the COMP2 inverting input as explained in
.
3. Enable the Window mode by setting the WNDWE bit in the COMP_CSR3 register.
4. Select the COMP2 non-inverting input:
–
like for COMP1: follow step 2 and 3 from Section 16.3
–
like for COMP2: follow step 3 from Section 16.4
5. Enable the COMP1 comparator using the CMP1[1:0] bits in the COMP_CSR1 register and the COMP2 comparator using the CMP2[1:0] in the COMP_CSR2 register. Refer to
Table 53 for the different configurations which must be programmed to get the
correct wakeup or interrupt event.
Table 53. Window interrupts/wakeup modes
Interrupt/wakeup mode
CMP1[1:0] upper threshold
CMP2[1:0] lower threshold
Vin > Upper (above)
Vin < Lower (below)
Lower<Vin<Upper (inside)
Vin<Lower or Vin>Upper (outside)
0b10
0b00
0b01
0b10
0b00
0b01
0b10
0b01
16.6 COMP low power modes
Table 54. Behavior of comparators in low power modes
Mode Description
Wait or Low power wait mode
No effect on comparator.
Comparator interrupts cause the device to exit from Wait or Low power wait mode.
Active-halt or
Halt
No effect on comparator.
Comparator interrupts cause the device to exit from Active-halt or Halt mode.
Note: Comparators cannot be used to exit the device from Halt/Active-halt mode when the internal reference voltage is stopped using the ULP bit in the PWR_CSR2 register.
RM0031 Rev 15
RM0031 Comparators (COMP)
Interrupt event
Comparator 1 event flag
Comparator 2 event flag
Table 55. Comparator interrupt requests
Event flag
EF1
EF2
Enable control bit
IE1
IE2
Exit from
Wait/Low power wait
Exit from
Halt/
Activehalt
Yes
Yes
Yes
Yes
16.8.1 Comparator control and status register 1 (COMP_CSR1)
Address offset: 0x00
Reset value: 0x00
.
7
Reserved
6 5
IE1 rw
4
EF1 rc_w0
3
CMP1OUT r
2
STE rw
1 0 rw
CMP1[1:0] rw
Bits 7:6 Reserved, must be kept cleared
Bit 5 IE1 : Comparator 1 interrupt enable
This bit enables the comparator 1 interrupt generation when an event is detected.
0: Comparator 1 interrupt disabled
1: Comparator 1 interrupt enabled
Bit 4 EF1 : Comparator 1 event flag
This bit is set when the selected edge in COMP1[1:0] on comparator 1 output occurs. It is cleared writing 0 to it. If the comparator interrupt is enabled, then an interrupt is generated.
0: No event detected
1: Event detected
RM0031 Rev 15
256
Comparators (COMP) RM0031
Bit 3 CMP1OUT : Comparator 1 output
This bit is the exact copy of the comparator 1 output.
0: Comparator 1 output is low when non inverting input is at lower voltage than inverting input
1: Comparator 1 output is high when non-inverting input is at higher voltage than inverting input
Bit 2 STE : Schmitt trigger enable
0: Schmitt trigger disabled
1: Schmitt trigger enabled
Note: The STE bit modifies the behavior of the Schmitt trigger of the I/Os featuring an analog function
(ADC channels, comparator inputs) only when the I/O analog switch is closed.
Bits 1:0 CMP1[1:0] : Comparator 1 configuration
00: Comparator 1 disabled
01: Event detection on the falling edge of comparator 1 output
10: Event detection on the rising edge of comparator 1 output
11: Event detection on both rising/falling edges of comparator 1 output
RM0031 Rev 15
RM0031 Comparators (COMP)
16.8.2 Comparator control and status register 2 (COMP_CSR2)
Address offset: 0x01
Reset value: 0x00
.
7
Reserved
6 5
IE2 rw
4
EF2 rc_w0
3
CMP2OUT r
2
SPEED rw
1 rw
CMP2[1:0]
0 rw
Bits 7:6 Reserved, must be kept cleared
Bit 5 IE2 : Comparator 2 Interrupt Enable
This bit enables the comparator 2 interrupt generation when an event is detected.
0: Comparator 2 interrupt disabled
1: Comparator 2 interrupt enabled
Bit 4 EF2 : Comparator 2 event flag
This bit is set when the selected edge in COMP2[1:0] on comparator 2 output occurs. It is cleared by writing 0 to it. If the comparator interrupt is enabled, then an interrupt is generated.
0: No event detected
1: Event detected
Bit 3 CMP2OUT : Comparator 2 output
This bit is the exact copy of the comparator 2 output.
0: Comparator 2 output is low when non inverting input is at lower voltage than inverting input
1: Comparator 2 output is high when non inverting input is at higher voltage than inverting input
Bit 2 SPEED : Comparator 2 speed mode
0: Slow speed
1: Fast speed
Bits 1:0 CMP2[1:0] : Comparator 2 configuration
00: Comparator 2 disabled
01: Event detection on the falling edge of comparator 2 output
10: Event detection on the rising edge of comparator 2 output
11: Event detection on both rising/falling edges of comparator 2 output
RM0031 Rev 15
256
Comparators (COMP) RM0031
16.8.3 Comparator control and status register 3 (COMP_CSR3)
Address offset: 0x02
Reset value: 0xC0
.
7 rw
OUTSEL[1:0]
6 rw
5 rw
4
INSEL[2:0] rw
3 rw
2
VREFEN rw
1
WNDWE rw
0
VREFOUTEN rw
Bits 7:6 OUTSEL[1:0] Comparator 2 output selection
These bits are written by software to connect the output of COMP2 to a selected timer input.
00: COMP2 output connected to Timer 2 input capture 2 (TIM2 IC2). The corresponding input capture from the I/O is no more available.
01: COMP2 output connected to Timer 3 input capture 2 (TIM3 IC2). The corresponding input capture from the I/O is no more available.
10: COMP2 output connected to Timer 1 break input (TIM1 BRK). The break input from the I/O is no more available.
11: COMP2 output connected to Timer 1 OCREF clear (TIM1 OCREFCLR)
Bits 5:3 INSEL : Comparator 2 inverting input selection
000 = no selection
001 = I/O (Group 2 of I/Os)
010 = Internal reference voltage V
REFINT
011 = 3/4 V
REFINT
100 = 1/2 V
REFINT
101 = 1/4 V
REFINT
110 = DAC1
111 = DAC2
Bit 2 VREFEN : Internal reference voltage V
REFINT enable
0: V
REFINT
1: V
REFINT
disconnected from COMP1 inverting input
connected to COMP1 inverting input
Bit 1 WNDWE : Window mode enable
0: Disabled
1: Enabled
Bit 0 VREFOUTEN : V
REFINT
output enable
This bit can be set by software to output the internal voltage reference on Group 3 I/Os. Refer to
Figure 27 .
0: Disabled
1: Enabled
RM0031 Rev 15
RM0031 Comparators (COMP)
16.8.4 Comparator control and status register 4 (COMP_CSR4)
Address offset: 0x03
Reset value: 0x00
.
7
Reserved
6 5 rw
4
NINVTRIG[2:0] rw
3 rw
2 rw
1
INVTRIG[2:0] rw
0 rw
Bits 7:6 Reserved, must be kept cleared
Bits 5:3 NINVTRIG[2:0]: COMP2 non inverting input
These bits control the Schmitt triggers of all the I/Os belonging to the I/O group 8 (see Table 27 ), corresponding to the COMP2 non inverting inputs.
NINVTRIG[0] enables/disables the trigger on pin PE5.
NINVTRIG[1] enables/disables the trigger on pin PD0.
NINVTRIG[2] enables/disables the trigger on pin PD1.
0: Trigger enabled
1: Trigger disabled
Bits 2:0 INVTRIG[2:0] : COMP2 inverting input
These bits control the Schmitt triggers of all the I/Os belonging to the I/O group 2 (see Table 27 ) , corresponding to the COMP2 inverting inputs.
INVTRIG[0] enables/disables the trigger on pin PC3.
INVTRIG[1] enables/disables the trigger on pin PC4.
INVTRIG[2] enables/disables the trigger on pin PC7.
0: Trigger enabled
1: Trigger disabled
Note: When the trigger is disabled on an I/O, the associated bit in Px_IDR register is always read as 0 even if another level is present on the pin.
16.8.5 Comparator control and status register 5 (COMP_CSR5)
Address offset: 0x04
Reset value: 0x00
.
7
Reserved
6 5 rw
4
DACTRIG[2:0] rw
3 rw
2 rw
1
VREFTRIG[2:0] rw
0 rw
RM0031 Rev 15
256
Comparators (COMP) RM0031
Note:
Bits 7:6 Reserved, must be kept cleared
Bits 5:3 DACTRIG[2:0] : DAC outputs
These bits control the Schmitt triggers of all the I/Os belonging to the I/O group 5 (see Table 27 ) , corresponding to the DAC outputs.
DACTRIG[0] enables/disables the trigger on pin PB6.
DACTRIG[1] enables/disables the trigger on pin PB5.
DACTRIG[2] enables/disables the trigger on pin PB4.
0: Trigger enabled
1: Trigger disabled
Bits 2:0 VREFTRIG[2:0]: V
REFINT
outputs
These bits control the Schmitt triggers of all the I/Os belonging to the I/O group 3 (see Table 27 ) , corresponding to the V
REFINT
outputs.
VREFTRIG[0] enables/disables the trigger on pin PC2.
VREFTRIG[1] enables/disables the trigger on pin PD7.
VREFTRIG[2] enables/disables the trigger on pin PD6.
0: Trigger enabled
1: Trigger disabled
When the trigger is disabled on an I/O, the associated bit in Px_IDR register is always read as 0 even if another level is present on the pin.
Address offset
0x00
0x01
0x02
0x03
0x04
Register name
Table 56. Comparators and routing Interface register map
7 6 5 4 3 2
COMP_CSR1
Reset value
COMP_CSR2
Reset value
COMP_CSR3
Reset value
COMP_CSR4
Reset value
COMP_CSR5
Reset value
OUTSEL1
1
-
0
-
0
-
0
-
0
OUTSEL0
1
-
0
-
0
-
0
-
0
IE1
0
IE2
0
INSEL2
0
INVTRIG2
0
DACTRIG2
0
1 0
EF1
0
EF2
0
INSEL1
0
INVTRIG1
0
DACTRIG1
0
CMP1OUT
0
CMP2OUT
0
INSEL0
0
INVTRIG0
0
DACTRIG0
0
STE
0
SPEED
0
VREFEN
0
NINVTRIG2
0
CMP11
0
CMP21
0
WINDWE
0
NINVTRIG1
0
VREFTRIG2
0
VREFTRIG1
0
CMP10
0
CMP20
0
VREFOUTEN
0
NINVTRIG0
0
VREFTRIG0
0
RM0031 Rev 15
RM0031 LCD controller
This section applies to medium-density STM8L052x/STM8L152x devices, medium+ density
STM8L052x/STM8L152x devices and high-density STM8L052x/STM8L152x/STM8L162x devices, unless otherwise specified.
17.1 LCD controller introduction
The LCD controller can drive a passive-matrix LCD (liquid crystal display) unit.
• In STM8L05xx value line high-density devices, it can interface with 8 common terminals and up to 24 segment terminals to drive up to 192 picture elements (pixels).
• In medium+ and high-density devices, it can interface with 8 common terminals and up to 44 segment terminals to drive up to 320 picture elements (pixels).
• In medium-density devices, It can interface with 4 common terminals and up to 28 segment terminals to drive up to 112 picture elements (pixels).
The LCD is made up of several segments (pixels or complete symbols) which can be turned visible or invisible. Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The segment voltage must be alternated to avoid an electrophoresis effect in the liquid crystal (which degrades the display). The waveform across a segment must then be generated so as to avoid having a direct current
(DC).
17.1.1 Definitions
Glossary
• LCD (Liquid crystal display): a passive display panel with terminals driving segments.
• Segment: the smallest viewing element (a single bar or dot that is used to help create a character on a LCD display).
• Common: electrical connection terminal connected to several segments.
• Duty ratio: number defined as 1 / (number of common terminals on an LCD display).
• Bias: indicates the number of voltage levels used when driving an LCD. It is defined as
1 / (number of voltage levels used driving a LCD display - 1).
• Frame: one period of the waveforms written to a segment.
• Frame rate: number of frames per second, that is, number of times the LCD segments are energized per second.
• Boost circuit: contrast controller circuit.
RM0031 Rev 15
286
LCD controller RM0031
17.2 LCD controller main features
• High-flexibility frame rate control
• In value line high-density devices
– Static,1/2, 1/3, 1/4 and 1/8 duty supported
– 1/2, 1/3 and 1/4 bias supported
– LCD data RAM of up to 18 x 8-bit registers which contain pixel (LCD picture element) information (active/inactive)
– Capability to drive 112 (28x4) or 192 (24x8) pixels
• In medium+ and high-density devices
– Static,1/2, 1/3,1/4 and 1/8 duty supported
– 1/2, 1/3 and 1/4 bias supported
– LCD data RAM of up to 22 x 8-bit registers which contain pixel (LCD picture element) information (active/inactive)
– Capability to drive 176 (44x4) or 320 (40x8) pixels
• In medium-density devices
– Static,1/2, 1/3 and 1/4 duty supported
– 1/2 and 1/3 bias supported
– LCD data RAM of up to 14 x 8-bit registers which contain pixel (LCD picture element) information (active/inactive)
– Capability to drive 112 (28x4) pixels
• LCD output voltage software selectable
• No need for external analog components:
– A booster is embedded to generate an internal V
LCD
V
DD
.
voltage independent from
– Software selection between external and internal V
LCD
voltage source. In case of an external source, the internal boost circuit is disabled to reduce power consumption.
– A resistive network is embedded to generate intermediate V
LCD
voltages.
– The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel.
• The contrast can be adjusted using two different methods:
– When using the internal booster, the software can adjust V
LCD
between V
LCDmin and V
LCDmax.
– Programmable dead time (up to 7 phase periods) between frames.
• Full support of low power modes: the LCD controller can be displayed in Active-halt,
Wait, Low power run and Low power wait modes or can be fully disabled to reduce power consumption
• Phase inversion to reduce power consumption and EMI (electromagnetic interference)
• Start of frame interrupt to synchronize the software when updating the LCD data RAM.
• Blink capability:
– SEG0 COM0, SEG0 COMx, or SEGx COMx which can be programmed to blink at a configurable frequency.
– Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or
4 Hz.
RM0031 Rev 15
RM0031 LCD controller
• Capability to assign some of the SEGx (segment) and COMx (common) pins as standard general purpose IOs when not used.
The availability of SEGx pins for GPIO depends on LCD_PM registers; the availability of COMx pins depends on COM signal duty setting exclusively when LCD is enabled.
17.3 LCD functional description
The block diagram of the LCD controller is shown in the following figure.
Figure 55. Medium + and high-density LCD controller block diagram
RTCCLK
LCDCLK Sampling unit
FREQUENCY GENERATOR
16-bit Prescaler
LCDCLK LCDCLK/65536
PS[3:0]
Clock mux
LCD REGS
DIV[3:0]
Ck_ps
Divide by 16 to 31
COM driver
Interrupt
COM[7:0]
LCD RAM
(44x8 bits)
SEG driver
SEG[43:0]
44
COM0
Analog switch array
COM7
SEG0
SEG43
LEGEND
LEGEND
LCD REGS
PULSE GEB
VSEL
STATIC
EN
HD
Voltage generator
BIAS[1:0]
CC[2:0]
Contrast controller
ANALOG BOOSTER
READY
V
SS
1/3 – 1/4 V
LCD
2/3 – 3/4 V
LCD
1/2 V
LCD
V
LCD
LEGEND
LEGEND
LEGEND
LEGEND
I/O Ports
MSv46312V1
RM0031 Rev 15
286
LCD controller RM0031
Figure 56. Medium-density LCD controller block diagram
RTCCLK
LCDCLK Sampling unit
FREQUENCY GENERATOR
16-bit Prescaler
LCDCLK LCDCLK/65536
PS[3:0]
Clock mux
LCD REGS
DIV[3:0]
Ck_ps
Divide by 16 to 31
COM driver
Interrupt
COM[3:0]
LCD RAM
(14x8 bits)
SEG driver
SEG[17:0]
28
COM0
Analog switch array
COM3
SEG0
SEG27
LCD REGS
PULSE GEB
VSEL
STATIC
EN
HD
Voltage generator
B2
CC[2:0]
Contrast controller
ANALOG BOOSTER
READY
V
SS
1/3 V
LCD
2/3 V
LCD
1/2 V
LCD
V
LCD
LEGEND
LEGEND
LEGEND
LEGEND
LEGEND
LEGEND
I/O Ports
MSv46313V1
The frequency generator allows to achieve various LCD frame rates starting from an LCD input clock frequency which is equal to RTCCLK divided by 2. For more information about the LCD clock source configuration please refer to
Section 9.9: RTC and LCD clock
.
This clock source must be in the range of 16.384 kHz to 500 kHz and must be stable to obtain an accurate LCD timing and minimize the DC voltage offset across LCD segments. It can be divided by values from 1 up to 2 15 x 31. The frequency generator consists of a prescaler (16-bit ripple counter) and a programmable clock divider (factor 16 to 31).
RM0031 Rev 15
RM0031 LCD controller
The PS[3:0] bits in the LCD_FRQ register select the prescaler so as to divide LCDCLK by
2 PS[3:0] . If a finer resolution rate is required, the DIV[3:0] bits in the LCD_FRQ register can be used to further divide the clock by 16 to 31. In this way the user can fine-tune the frequency by linearly scaling (up/down) the clock with the counter.
The output of the frequency generator block is ck_div which constitutes the time base for the entire LCD controller. The ck_div frequency is equivalent to the LCD phase frequency rather than the frame frequency (they are equal only in case of static duty).
The frame frequency (f frame
) is obtained from ck_div by dividing it by the number of active common terminals (or by multiplying it by the duty ratio). Thus the relation between the input clock frequency (f
LCDCLK is:
) of the frequency generator and its output clock frequency f ck_div f ck_div
= f
-------------------------------------------------
2
PS
× ⟨ 16 DIV ⟩ f frame
= f ck_div
× duty
The frame frequency which must be selected to be within a range of around ~30 Hz to ~100
Hz is a compromise between power consumption and acceptable refresh rate. In addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined as: f
BLINK
= f
-----------------------------
2 with BLINKF[2:0] = 0,1,2,..,7
The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. Some examples of typical frame rate calculation are shown in
.
RM0031 Rev 15
286
LCD controller RM0031
CLK
16.384 kHz
Table 57. Typical frame rate calculation for input frequency of 16.384 kHz
Duty PS[3:0] DIV[3:0] Ratio f
LCD f frame
BLINKF[2:0] divider
1/8
1/4
1/2 static
2
1
0
3
2
1
4
3
2
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
64
32
16
128
64
32
256
128
64
512
256
128
256 Hz
512 Hz
1024 Hz
128 Hz
256 Hz
512 Hz
64 Hz
128 Hz
256 Hz
32 Hz
64 Hz
128 Hz
32 Hz
64 Hz
128 Hz
32 Hz
64 Hz
128 Hz
32 Hz
64 Hz
128 Hz
32 Hz
64 Hz
128 Hz
/512
/256
/64
/1024
/512
/128
/1024
/256
/128
/64
/16
/256
/128
/32
/512
/256
/64
/64
/32
/8
/128
/64
/16
/256
/128
/32
/256
/128
/32
/512
/256
/64
/1024
/512
/128 f
BLINK
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
0.5 Hz
1.0 Hz
4.0 Hz
RM0031 Rev 15
RM0031 LCD controller
CLK
500 kHz
Table 58. Typical frame rate calculation for input frequency of 500 kHz
Duty PS[3:0] DIV[3:0] Ratio f
LCD f
FRAME
BLINKF[2:0] divider
1/8
1/4
1/2 static
7
5
8
6
9
7
10
8
0
3
0
3
0
3
0
3
2048
608
4096
1216
8192
2432
16384
4864
244.00 Hz 30.51 Hz
822.30 Hz 102.79 Hz
122.00 Hz 30.51 Hz
411.10 Hz 102.79 Hz
61.00 Hz 30.51 Hz
205.60 Hz 102.79 Hz
30.51 Hz 30.51 Hz
102.79 Hz 102.79 Hz
/256
/128
/32
/1024
/256
/128
/64
/16
/512
/256
/64
/64
/32
/8
/256
/128
/32
/256
/128
/32
/1024
/512
/128 f
BLINK
0.47 Hz
0.95 Hz
3.81 Hz
0.80 Hz
3.21 Hz
0.47 Hz
0.95 Hz
3.81 Hz
0.40 Hz
0.80 Hz
3.21 Hz
0.47 Hz
0.95 Hz
3.81 Hz
0.40 Hz
0.80 Hz
3.21 Hz
0.47 Hz
0.95 Hz
3.81 Hz
0.40 Hz
0.80 Hz
3.21 Hz
Note: The software can decrement the frame frequency by simply incrementing the LCD_FRQ register.
Note:
Common signals are generated by a common driver which is a programmable ring counter
COM signal bias
Each common signal (COMn) has identical waveforms but different phases. It has the maximum amplitude V
LCD
or V
SS
only during the phase n of a frame cycle. During the other phases, the signal amplitude is
• 1/4 V
LCD
or 3/4 V
LCD
in case of 1/4 bias (high-density devices only)
• 1/3 V
LCD
or 2/3 V
LCD
in case of 1/3 bias
• 1/2 V
LCD
in case of 1/2 bias.
The LCD controller generates only one type of LCD waveforms (waveform consuming less power). The waveforms are described in
and
RM0031 Rev 15
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LCD controller RM0031
Selection between 1/2, 1/3 and 1/4 bias mode can be done by programming the B2 bit in the
LCD_CR1 register.
• the B2 bit in the LCD_CR1 register and the B4 bit in the LCD_CR4 register in medium+ and high-density devices
• the B2 bit in the LCD_CR1 register in medium-density devices
A pixel is activated when both of its corresponding common and segment lines have their maximum amplitudes during the same phase. As shown in
, common signal in even frames vs. odd frames are phase inverted in order to reduce EMI (electromagnetic interference). The first frame generated is the odd one followed by an even one.
Figure 57. 1/3 bias, 1/4 duty
Odd frame Even frame
V
LCD
2/3 V
LCD
1/3 V
LCD
V
SS
V
LCD
2/3 V
LCD
1/3 V
LCD
V
SS
COM active COM inactive COM inactive COM inactive COM active COM inactive COM inactive COM inactive
SEG active SEG active SEG inactive SEG inactive SEG active SEG active SEG inactive SEG inactive
Phase 0 Phase 1 Phase 2 Phase 3 Phase 0 Phase 1 Phase 2 Phase 3
In case of 1/2 bias (B2 bit set in the LCD_CR1 register in medium, medium+ and highdensity devices and B4 bit reset in the LCD_CR4 register in medium+ and high-density devices), an intermediate voltage equal to 1/2 V
LCD
is generated for even and odd frames;
The input of this common driver is ck_div which is used to generate common waveforms.
COM signal duty
In medium+ and high-density devices:
Common signals are generated depending on the DUTY[1:0] bits in the LCD_CR1 register and on the DUTY8 bit in the LCD_CR4 register. Five duty ratios can be selected:
•
Static duty (see Figure 59: Liquid crystal display and terminal connection (static duty) on page 267
)
• 1/2 duty (see
Figure 60: Liquid crystal display and terminal connection (1/2 duty, 1/2 bias) on page 268 )
• 1/3 duty (see
Figure 61: Liquid crystal display and terminal connection (1/3 duty, 1/3 bias) on page 269 )
• 1/4 duty (see
Figure 62: Liquid crystal display and terminal connection (1/4 duty, 1/3 bias) on page 270 )
• 1/8 duty (see
Figure 63: Liquid crystal display and terminal connection (1/8 duty, 1/4 bias) on page 271 )
RM0031 Rev 15
RM0031 LCD controller
In medium-density devices:
Common signals are generated depending on the DUTY[1:0] bits in the LCD_CR1 register.
Four duty ratios can be selected:
•
Static duty (see Figure 59: Liquid crystal display and terminal connection (static duty) on page 267
)
• 1/2 duty (see
Figure 60: Liquid crystal display and terminal connection (1/2 duty, 1/2 bias) on page 268 )
• 1/3 duty (see
Figure 61: Liquid crystal display and terminal connection (1/3 duty, 1/3 bias) on page 269 )
• 1/4 duty (see
Figure 62: Liquid crystal display and terminal connection (1/4 duty, 1/3 bias) on page 270 )
The ‘n’ value has an impact on COMn behaviors:
• COMn (with ‘n’ from 0 to 3 in medium-density devices and from 0 to 7 in medium+ and high-density devices) is active
– during phase ‘n’ of an even frame. The COMn pin is then driven to V
LCD
– during phase ‘n’ of an odd frame. The COMn pin is then driven to V
SS
• COMn is inactive during a phase not equal to ‘n’
– In case of 1/4 bias (medium+ and high-density devices only), the COMn pin is then driven to 1/4 V
LCD during an even frame and to 3/4 V
LCD
during an odd frame
– In case of 1/3 bias, the COMn pin is then driven to 1/3 V
LCD and to 2/3 V
LCD
during an odd frame during an even frame
– In case of 1/2 bias, the COMn pin is then always driven to 1/2 V
LCD frame).
(odd and even
When static duty is selected, the segment lines are not multiplexed, which means that each segment output corresponds to one pixel. In this way only 28 pixels in the medium-density devices and up to 44 pixels in the medium+ and high-density devices can be driven. COM0 is always active and only two voltage levels are used for the segment and common lines:
V
LCD
and V
SS
, while COM[3:1] in medium-density devices or COM[7:1] in medium+ and high-density devices are not used.
A pixel is active if the corresponding segment line gets a voltage different from that of the common line. It is inactive when both voltages are the same. In this case, the LCD has the maximum contrast (see
and
In the following figure, pixel 0 is active while pixel 1 is inactive.
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LCD controller RM0031
COM0
SEG0
SEG1
COM0-
SEG0
COM0-
SEG1
V
LCD
V
SS
V
LCD
V
SS
V
LCD
V
SS
V
LCD
0
-V
LCD
V
LCD
0
-V
LCD
Figure 58. Static duty
Odd frame
Even frame
Odd frame
Even frame
In each frame there is only one phase, this is why f frame is equal to f fck_div
.
In case of 1/4 duty:
If 1/4 duty is selected there are four phases in a frame in which COM0 is active during phase
0, COM1 is active during phase 1, COM2 is active during phase 2, and COM3 is active during phase 3.
In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding segments and common lines are active in the same phase.
• To deactivate pixel 0 connected to COM0, SEG0 needs to be inactive during the phase
0 when COM0 is active.
• To activate pixel 27 connected to COM1, SEG27 needs to be active during phase 1
when COM1 is active (see Figure 62
).
• To activate pixels from 0 to 27 connected to COM0, SEG[0:27] need to be active during phase 0 when CM0 is active.
These rules can be applied to all other pixels.
8 to 1 multiplexer
In medium+ and high-density devices, when COM[0] is active, the common driver block also
in order to select the content of RAM register locations corresponding to
COM[0]. When COM[7] is active, the output of the 8 to 1 multiplexer is the content of the
RAM locations corresponding to COM[7]. Refer to
Section 17.6.7: LCD display memory
.
4 to 1 multiplexer
In medium-density devices, when COM[0] is active, the common driver block also drives the
4 to 1 multiplexer shown in
Figure 56: Medium-density LCD controller block diagram in
order to select the content of RAM register locations corresponding to COM[0]. When
COM[4] is active, the output of the 4 to 1 multiplexer is the content of the RAM locations
RM0031 Rev 15
RM0031 LCD controller
corresponding to COM[4]. Refer to Section 17.6.7: LCD display memory (LCD_RAM) on page 283
.
Figure 59. Liquid crystal display and terminal connection (static duty)
1/1 V
PIN
COM0
0/1 V
1/1 V
PIN
SEG0 COM0
SEG7
SEG6
SEG5
PIN
SEG1
0/1 V
1/1 V
0/1 V
1/1 V
COM0 - SEG0
Selected waveform
0/1 V
COM0 - SEG1
Non selected waveform
1 frame
-1/1 V
0/1 V
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LCD controller RM0031
Figure 60. Liquid crystal display and terminal connection (1/2 duty, 1/2 bias)
PIN
COM0
COM1
COM0
PIN
COM1
PIN
SEG0
PIN
SEG1
COM0 - SEG0
Selected waveform
COM0 - SEG1
Non selected waveform
0/2 V
2/2 V
0/2 V
2/2 V
1/2 V
0/2 V
-1/2 V
-2/2 V
1/2 V
0/2 V
-1/2 V
2/2 V
1/2 V
0/2 V
2/2 V
1/2 V
0/2 V
2/2 V
1 frame
RM0031 Rev 15
RM0031 LCD controller
Figure 61. Liquid crystal display and terminal connection (1/3 duty, 1/3 bias)
SEG0 SEG1 SEG2
PIN
COM0
COM2
COM1
COM0
PIN
COM1
PIN
COM2
PIN
SEG0
PIN
SEG1
COM0 - SEG1
Selected waveform
COM0 - SEG0
Non selected waveform
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
-1/3 V
-2/3 V
-3/3 V
1/3 V
0/3 V
-1/3 V
1 frame
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LCD controller RM0031
Figure 62. Liquid crystal display and terminal connection (1/4 duty, 1/3 bias)
Liquid crystal display and terminal connection
COM3
COM2
SEG0 SEG1
COM1
COM0
PIN
COM0
PIN
COM1
PIN
COM2
PIN
COM3
PIN
SEG0
PIN
SEG1
COM3 - SEG0
Selected Waveform
COM0 - SEG0
Non selected waveform
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
-1/3 V
-2/3 V
-3/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
3/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
2/3 V
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
-1/3 V
1 frame
RM0031 Rev 15
RM0031 LCD controller
Figure 63. Liquid crystal display and terminal connection (1/8 duty, 1/4 bias)
COM6
COM3
COM2
Liquid Crystal Display and Terminal Connection
COM7
COM5
COM4
COM1
COM0
SEG0
PIN
COM0
PIN
COM1
PIN
COM2
PIN
COM7
PIN
SEG0
COM0 - SEG0
Selected Waveform
COM2 - SEG0
Non selected waveform
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
-1/4 V
-2/4 V
-3/4 V
-4/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
-1/4 V
-2/4 V
-3/4 V
-4/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
4/4 V
3/4 V
2/4 V
1/4 V
0/4 V
1 frame
1. Available on medium+ and high-density devices only.
The segment driver controls the segments depending on the input pixel data coming from the 4 to 1 multiplexers (in the medium-density devices) or from 8 to 1 multiplexers (in the medium+ and high-density devices) driven in each phase by the common driver.
In case of 1/4 duty, when COM0 is active, pixel information (active/inactive) relative to pixel connected to COM0 goes through the 4 to 1 multiplexer.
In case of 1/8 duty, when COM0 is active, the pixel information (active/inactive) relative to the pixel connected to COM0 goes through the 8 to 1 multiplexer.
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LCD controller RM0031
The segment driver can operate in different ways:
• If pixel 'n' is active when COM0 is active:
– the segment driver drives the SEGn pin (with ‘n’ from 0 to 27 in medium-density devices or from 0 to 43 in medium+ and high-density devices) to V SS in the phase
0 of an even frame
– the segment driver drives the SEGn pin to V LCD in the phase 0 of an odd frame
• If pixel 'n' is inactive
– in case of 1/4 bias (in medium+ and high-density devices) the segment driver drives the SEGn pin to 1/2 V
LCD
in an even frame and to 1/2 V
LCD
in an odd frame
– in case of 1/3 bias the segment driver drives the SEGn pin to 2/3 V
LCD frame. the segment drives drives the SEGn pin to 1/3 V
LCD
in an even
in an odd frame.
– in case of 1/2 bias SEGn pin is driven to V
LCD
in an even frame and to Vss in an
odd frame (see Figure 60: Liquid crystal display and terminal connection (1/2 duty,
).
The segment driver also performs LCD pin multiplexing as general I/O.
Each segment pin (SEG[27:0] or SEG[43:0]) can be enabled or disabled (configured as general purpose I/O) independently through 4 or 6 LCD_PM registers. If the LCDEN bit in the LCD_CR3 register is reset and pins are configured as segment pins, segment lines are then pulled down to V
SS at the end of the even frame.
17.3.6 Blink
The segment driver also implements a programmable blink feature. It is possible to select the number of blink pixels through the BLINK[1:0] bits in the LCD_CR1 register:
• a single pixel (COM0, SEG0),
• all the pixels attached to SEG0 (up to 4),
• or all pixels.
To do this, the corresponding bits in the LCD data RAM must be programmed.
The blink prescaler, through the BLINKF[2:0] bits, selects a wide range of blink frequencies, including 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
17.3.7 Multiplexing COM[7:4] and SEG[43:40], SEG[39:36], or SEG[31:28]
Note:
In medium+ and high-density devices, the LCD controller can drive Nx4 or (N-4)x8 pixels through the N+4 available LCD pins. The COM4..7 signals and some SEG signals
(depending on packages) share the same four pins and the multiplexing is controlled by the
DUTY8 bit in the LCD_CR4 register.
“N” values can be 44, 40 or 28 respectively on 80-pin, 64-pin or 48-pin packages.
For STM8L05xx value line devices, “N” value is 28 on 64-pin or 48-pin packages.
RM0031 Rev 15
RM0031 LCD controller
Packages
80-pin packages
64-pin packages
48-pin packages
Table 59. SEG and COM signal mapping
DUTY8 = 0 DUTY8 = 1
SEG40...43 are mapped respectively on ports PF4...PF7.
COM4...7 are mapped respectively on ports PF4...PF7
SEG36...39 are mapped respectively on ports PF4...PF7.
COM4...7 are mapped respectively on ports PF4...PF7
SEG24...27 are mapped respectively on ports PC4, PC7, PE6 and PE7
COM4...7 are mapped respectively on ports PC4, PC7, PE6 and PE7
• On 80-pin packages: The LCD controller can drive 44x4 or 40x8 pixels through the 48 available LCD pins. The COM4..7 signals and the SEG40..43 signals share the same four pins and the multiplexing is controlled by the DUTY8 bit in the LCD_CR4 register:
– if DUTY8=0, the SEG40..43 are respectively mapped on PF4..PF7 ports.
– if DUTY8=1, the COM4..7 are respectively mapped on PF4..PF7 ports.
•
On 64-pin package: The LCD controller can drive 40x4 or 36x8 pixels
through the 44 available LCD pins. The COM4..7 signals and the SEG36..39 signals share the same four pins and the multiplexing is controlled by the DUTY8 bit in the LCD_CR4 register:
– if DUTY8=0, the SEG36..39 are respectively mapped on PF4..PF7 ports.
– if DUTY8=1, the COM4..7 are respectively mapped on PF4..PF7 ports.
•
On 48-pin package: The LCD controller can drive 28x4 or 24x8 pixels (1)
through the 32 available LCD pins. The COM4..7 signals and the SEG24..27 signals share the same four pins and the multiplexing is controlled by the DUTY8 bit in the LCD_CR4 register:
– if DUTY8=0, the SEG24..27 are respectively mapped PC4, PC7, PE6 and PE7 on ports.
– if DUTY8=1, the COM4..7 are respectively mapped on PC4, PC7, PE6 and PE7 ports.
1. On STM8L05xx value line devices, the LCD controller can drive 28x4 or 24x8 pixels for 64-pin package and 28x4 pixels for 48-pin package. 80-pin package is not available.
17.3.8 Generation of LCD voltage levels
The LCD voltage levels are generated internally using:
• an internal booster which generates V
LCD
. The user can also provide the V
LCD voltage externally through the VLCD pin if the VSEL bit is set in the LCD_CR2 register
• an internal resistor divider network which generates all V
LCD
intermediate voltages, as
In fact, two resistive networks are used, one with low value resistors (Rl) and one with high value resistors (RH) which are respectively used to increase the current during transitions and to reduce power consumption in static state.
The EN switch follows the following rules:
• If LCDEN bit in the LCD_CR3 register is set, the EN switch is closed.
• When clearing the LCDEN bit in the LCD_CR3, the EN switch is open at the end of the even frame in order to avoid a medium voltage level different from 0 during the frame.
The PON[2:0] (Pulse ON duration) bits in the LCD_CR2 register configure the time during which RL is enabled (see
) through a HD (high drive) when the levels of common and segment lines change. A short drive time decreases power consumption, but displays
RM0031 Rev 15
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LCD controller RM0031 with high internal resistance may need a longer drive time to achieve a satisfactory contrast.
The R
L
divider can be always switched on using the HD bit in the LCD_CR2 register.
The HD switch follows the rules described below:
• If the HD bit and the PON[2:0] bits in the LCD_CR2 are reset, then HD switch is open.
• If the HD bit in the LCD_CR2 register is reset and the PON[2:0] bits in the LCD_CR2 are different from 00 then, the HD switch is closed during the number of pulses defined in the PON[2:0] bits.
• If HD bit in the LCD_CR2 register is 1 then HD switch is always closed.
The V
LCD
value can be chosen among a wide set of values from V
LCDmin
to V
LCDmax
using
the CC[2:0] bits (contrast control bits) in the LCD_CR2 register (see Figure 55 ). New VLCD
values take effect at each beginning of a new frame.
Figure 64. Resistive network
H D EN
V LC D node c bias 1/3 node b bias 1/2 or bias 1/4 bias 1/3
R
LN
1) bias 1/4
R
HN
1)
STATIC
V
SS
1. R
LN
: Low value resistor network. R
HN
: High value resistor network.
node a
MS19205V1
RM0031 Rev 15
RM0031 LCD controller
Note:
• In case of 1/2 bias, one voltage level (1/2 V
LCD
V
LCD
.
) is generated and node b voltage is 1/2
• In case of 1/3 bias, two intermediate voltage levels (1/3 V
LCD
, 2/3 V
LCD
) are generated
– node a is 1/3 V
LCD
– node b is 2/3 V
LCD
• In case of 1/4 bias (medium+ and high-density devices only), three intermediate voltage levels (1/4 V
LCD
, 1/2 V
LCD and 3/4 V
LCD
) are generated
– node a is 1/4 V
LCD
– node b is 1/2
LCD
– node c is 3/4 V
LCD
.
Internal or external V
LCD register.
source can be selected using the VSEL bits of the LCD_CR2
In case the internal V
LCD
source is selected (VSEL=0) and the LCD is used in Active-halt mode, the ULP bit (bit 1) in the PWR_CSR2 register must be programmed to '0' because the internal V
LCD
source needs the internal reference voltage.
The contrast can be controlled by programming a dead time between each couple of frames where the COM and SEG value is tied to Vss in the same time. The DEAD[0:2] bits in the
LCD_CR3 register can be used to program up to 7 times a phase period.
odd frame
Figure 65. Contrast control even frame dead time odd frame even frame
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LCD controller RM0031
Note:
Each time the LCD message is to be changed, LCD_RAM content is to be updated with new data.
Single buffered memory does not allow data in LCD_RAM buffer to be updated at any time by the application firmware without affecting the integrity of data displayed. So, to avoid any display unexpected behavior, the application firmware must make sure that LCD_RAM content is updated synchronously with the start of frame.
To update the LCD_RAM content, proceed as follow:
• Clear SOF flag by setting SOFC bit in LCD_CR3
• Wait until SOF active (start of new frame) by polling SOF bit in LCD_CR3 until it is asserted or waiting until the LCD Interrupt is serviced (if the SOFIE bit is set)
• Update LCD_RAM buffer
Thereby, LCD_RAM refresh rate should not be faster than the LCD frame frequency.
Otherwise it might result in lower quality display results like pixel blinking.
17.4 LCD controller low power modes
Table 60. LCD behavior in low power modes
Mode Description
Low power wait
/Wait
The LCD is still active.
Active-halt
Halt
The LCD is still active. If internal VLCD booster is used, ULP bit must be '0' in
PWR_CSR2.
The LCD is not active.
Note: The device can enter Halt mode only when the RTC is OFF, or when HSE or HSI is used as
RTC clock source. The device is in Active-halt mode when LSE or LSI is selected.
17.5 LCD controller interrupts
The common driver can also generate a start of new frame flag through the SOF bit in the
LCD_CR3 register. This bit is set at the beginning of the last COM of the even frame. At this moment, the last segments are displayed and the CPU can update the data RAM to avoid displaying flickering data on the LCD panel.
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RM0031 LCD controller
Figure 66. SOF interrupt signal
Last COM
IT
The LCD start of frame interrupt is generated if the SOFIE bit (interrupt enable bit) in the
LCD_CR3 register is set. The start of frame flag is cleared by software by writing 1 to the
SOFC bit in the LCD_CR3 register.
Interrupt event
Start of frame flag
Table 61. LCD interrupt requests
Event flag
Enable control bit
Exit from Wait
SOF SOFIE yes
Exit from Halt no
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LCD controller
17.6 LCD controller registers
17.6.1 Control register 1 (LCD_CR1)
Address offset: 0x00
Reset value: 0x00
7
BLINK1 rw
6
BLINK0 rw
5
BLINKF2 rw
Bits 7:6 BLINK [1:0]: Blink enable
00: Blink inactive
01: SEG0/COM0 (1 pixel)
10: SEG0 COMx (up to 4 pixels)
11: SEGx COMx (all pixels)
Bits 5:3 BLINKF[2:0] : Blink frequency
000: f
LCD
001: f
LCD
010: f
LCD
011: f
LCD
100: f
LCD
101:
110:
111: f f f
LCD
LCD
LCD
/8
/16
/32
/64
/128
/256
/512
/1024
Bits 2:1 DUTY : Duty ratio selection
00: Static duty
01: 1/2 duty
10: 1/3 duty
11: 1/4 duty
Bit 0 B2 : 1/2 Bias selector
0: 1/3 bias
1: 1/2 bias
4
BLINKF1 rw
3
BLINKF0 rw
2
DUTY1 rw
1
DUTY0 rw
RM0031
0
B2 rw
RM0031 Rev 15
RM0031 LCD controller
17.6.2 Control register 2 (LCD_CR2)
Address offset:
0x01
Reset value: 0x00
7
PON2 rw
6
PON1 rw
5
PON0 rw
4
HD rw
3
CC2 rw
2
CC1 rw
1
CC0 rw
0
VSEL rw
Bits 7:5 PON : Pulse ON duration
These bits specify the pulse duration (number of CLK
PS
pulses). The pulse duration is PON[2:0] clock cycles coming out from the first prescaler thus determining the amount of time the RL resistive network is turned on for each voltage transition on SEG and COM pins. A short drive time decreases power consumption, but displays with a high internal resistance may need longer drive time to achieve a satisfactory contrast.
Note: The drive time will never be longer than half the prescaled LCD clock period
000: 0 CLK
PS
001: 1 CLK
PS
010: 2 CLK
PS
011: 3 CLK
PS
100: 4 CLK
PS
pulses
pulses
pulses
pulses
pulses
101: 5 CLK
PS
110: 6 CLK
PS
111: 7 CLK
PS
pulses
pulses
pulses
Bit 4 HD : High drive enable
This bit permanently enables the low resistance divider. Displays with a high internal resistance may need longer drive time to achieve a satisfactory contrast, so the software can set the HD bit if there is no strong power constraint.
0: High drive permanent disabled
1: High drive permanent enabled
Bits 3:1 CC[2:0] : Contrast control
These bits specify one of the V
LCD maximum voltage (independent of V
DD)
.
The new values will have effect every beginning of a new frame. The contrast controller (Boost circuit) is required inside the voltage generator.
000: VLCD0
001: VLCD1
010: VLCD2
011: VLCD3
100: VLCD4
101: VLCD5
110: VLCD6
111: VLCD7
Note: Refer to the device datasheet for the VLCDx values.
Bit 0 VSEL : The VSEL bit determines the LCD voltage source
0: Internal source
1: External source
Note: Refer to Section 17.3.8: Generation of LCD voltage levels
RM0031 Rev 15
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LCD controller RM0031
17.6.3 Control register 3 (LCD_CR3)
Address offset:
0x02
Reset value: 0x00
7
Reserved
6
LCDEN rw
5
SOFIE rw
4
SOF r
3
SOFC w
2
DEAD2 rw
1
DEAD1 rw
0
DEAD0 rw
Bit 7 Reserved, tied to 0
Bit 6 LCDEN : LCD enable
Clearing this bit during a frame delays the reset at the end of the even frame in order to avoid a medium voltage level different from 0 during the frame.
0: LCD controller disabled
1: LCD controller enabled
Bit 5 SOFIE : Interrupt enable
When this bit is set, the LCD start of frame interrupt is enabled.
0: SOF interrupt disabled
1: SOF interrupt enabled
Bit 4 SOF : Start of frame flag
This bit is set by hardware at the beginning of a last COM of an even frame. The LCD Interrupt is serviced if the SOFIE bit is set. SOF is cleared by software by setting the SOFC bit.
0: SOF inactive
1: SOF active (start of new frame)
Bit 3 SOFC : SOF flag clear
Setting this bit will clear the SOF flag. This bit is reset by hardware automatically.
Bits 2:0 DEAD[2:0] : Dead time enable
These bits determine the number of phases between different couples of frames where the COM and the SEG voltage levels are tied to 0 to reduce the contrast.
Dead = 000: no dead time
Dead = 001: 1-phase period dead time
Dead = 010: 2-phase period dead time
Dead = 011: 3-phase period dead time
Dead = 100: 4-phase period dead time
Dead = 101: 5-phase period dead time
Dead = 110: 6-phase period dead time
Dead = 111: 7-phase periods dead time
RM0031 Rev 15
RM0031 LCD controller
Address offset:
0x03
Reset value: 0x00
7
PS3 rw
6
PS2 rw
5
PS1 rw
4
PS0 rw
3
DIV3 rw
2
DIV2 rw
1
DIV1 rw
0
DIV0 rw
Bits 7:4 PS[3:0] : CLK 16-bit prescaler
The input clock (CLK) goes to a prescaler. The PS[3:0] bits select the prescaler so as to divide the clock by a factor of 2 PS[3:0] . The prescaled output CLK
PS
can be further divided by setting the DIV[3:0] bits. PS and DIV bits determine the prescaled LCD clock (CLK
LCD
) feeding the LCD module.
Bits 3:0 DIV[3:0] : Divider from 16 to 31
These bits set the frequency of the LCD clock such that the period can be DIV[3:0]+16 clocks coming out from the first prescaler. This clock divider provides a more flexible frame rate selection.
17.6.5 Port mask registers (LCD_PM)
Address offset:
0x04 to 0x07 (medium-density devices) or 0x04 to 0x09 (medium+ and high-density devices)
Reset value: 0x00
7 6 5 4
0x04
(LCD_PM0)
0x05
(LCD_PM1)
SEG07
SEG15
SEG06
SEG14
SEG05
SEG13
SEG04
SEG12
0x06
(LCD_PM2)
SEG23 SEG22
0x07
(LCD_PM3)
SEG31
SEG21 SEG20
SEG29
SEG28
0x08
(LCD_PM4)
0x09
(LCD_PM5)
SEG39
Reserved
SEG36
3
SEG03
SEG11
SEG19
SEG27
(2)
2
SEG02
SEG10
SEG18
1
SEG01
SEG09
SEG17
SEG25
0
SEG00
SEG08
SEG16
SEG24
SEG34
SEG42
rw rw rw rw rw rw rw rw
1. Available on medium+ and high-density devices only. Reserved on medium-density devices.
2. Reserved on STM8L05xx value line high-density devices.
Bits 7:0 PM[7:0] : Port mask for SEG[i]
These bits determine the number of port pins to be used as segment drivers.
Unused pins can be used as general purpose I/Os.
0: Pin configured as general purpose I/O
1: Segment enabled
RM0031 Rev 15
286
LCD controller RM0031
17.6.6 Control register 4 (LCD_CR4)
Note:
Address offset:
0x2F
Reset value: 0x00
This register is available in medium+ and high-density devices only.
7 6 5
Reserved r
4 3 2
PAGE_COM rw
1
DUTY8 rw
B4
0 rw
Bits 7:3 Reserved. tied to 0
Bit 2 PAGE_COM : LCD_RAM page selector
0: Addresses 0x0C to 0x021 give access to the first page of the LCD RAM, corresponding to COM0, 1,
2 and 3
- The S0[i] LCD RAM bit corresponds to SEG[i] of COM0
- The S1[i] LCD RAM bit corresponds to SEG[i] of COM1
- The S2[i] LCD RAM bit corresponds to SEG[i] of COM2
- The S3[i] LCD RAM bit corresponds to SEG[i] of COM3
1: Addresses 0x0C to 0x021 give access to the first page of the LCD RAM, corresponding to COM4, 5,
6 and 7
- The S0[i] LCD RAM bit corresponds to SEG[i] of COM4
- The S1[i] LCD RAM bit corresponds to SEG[i] of COM5
- The S2[i] LCD RAM bit corresponds to SEG[i] of COM6
- The S3[i] LCD RAM bit corresponds to SEG[i] of COM7
Bit 1 DUTY8 : 1/8 duty enable
0: Duty selected through the DUTY [1:0] bits in the LCD_CR1 register
1: 1/8 duty enabled
Bit 0 B4: 1/4 bias enable
0: 1/2 or 1/3 Bias is selected through the B2 bit in the LCD_CR1 register
1: 1/4 Bias enabled (bit B2 in the LCD_CR1 register must be reset).
RM0031 Rev 15
RM0031 LCD controller
17.6.7 LCD display memory (LCD_RAM)
Address offset:
0x0C to 0x19 (medium-density devices) or 0x0C to 0x21 (medium+ and high-density devices)
Reset value: 0x00
0x0C
0x0D
0x0E
7 6 5 4 3
S0[7:0]
(COM0 or COM4 (1) ) rw
S0[15:8]
(COM0 or COM4
rw
S0[23:16]
(COM0 or COM4
rw
2 1
0x0F
S1[3:0]
(COM1 or COM5
)
S0[27:24]
0x10
0x11
0x12
0x13
0x14
0x15 rw
S1[11:4]
(COM1 or COM5
rw
S1[19:12]
(COM1 or COM5
rw
S1[27:20]
(COM1 or COM5
rw
S2[7:0]
(COM2 or COM6
rw
S2[15:8]
(COM2 or COM6
rw
S2[23:16]
(COM2 or COM6
rw
0x16
S3[3:0]
(COM3 or COM7
)
S2[27:24]
0x17
0x18
0x19
rw
S3[11:4]
(COM3 or COM7
rw
S3[19:12]
(COM3 or COM7
rw
S3[27:20]
(COM3 or COM7
rw
S0[35:28]
(2)(3)
(COM0 or COM4) rw
0
RM0031 Rev 15
286
LCD controller RM0031
0x1B
(COM0 or COM4) rw
(COM1 or COM5)
0x1C
0x1D
0x1E
rw
(COM1 or COM5) rw
(COM2 or COM6) rw
(COM2 or COM6) rw
(COM3 or COM7) rw
(COM3 or COM7) rw
1. COM4, 5, 6 and 7 are available on medium+ and high-density devices only.
2. Register available on medium + and high-density devices only. Reserved on medium-density devices.
3. Reserved on STM8L05xx value line high-density devices.
Each bit corresponds to one pixel of the LCD display.
0: Pixel inactive
1: Pixel active
In medium+ and high-density devices:
When setting the DUTY8 bit in the LCD_CR4 (to activate 8 COMs), the LCD RAM is accessed through two pages, each being activated by the PAGE_COM bit in the LCD_CR4 register:
When PAGE_COM=0, addresses 0x0C to 0x21 give access to the first page, corresponding to COM0, 1, 2 and 3. Refer to the PAGE_COM bit description.
lWhen PAGE_COM=1, addresses 0x0C to 0x21 give access to the second page, corresponding to COM4, 5, 6 and 7. Refer to the PAGE_COM bit description.
In medium-density devices:
Addresses 0x0C-0x19 give access to the LCD RAM page, corresponding to COM0,1,2 and
3.
• The LCD RAM bits S0[i] corresponds to SEG[i] of COM0
• The LCD RAM bits S1[i] corresponds to SEG[i] of COM1
• The LCD RAM bits S2[i] corresponds to SEG[i] of COM2
• The LCD RAM bits S3[i] corresponds to SEG[i] of COM3.
RM0031 Rev 15
RM0031 LCD controller
Address offset
0x00
0x11
0x12
0x13
0x14
0x0D
0x0E
0x0F
0x10
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A to 0x0B
0x0C
0x15
0x16
0x17
Register name
LCD_CR1
Reset value
LCD_CR2
Reset value
LCD_CR3
Reset value
LCD_FRQ
Reset value
LCD_PM0
Reset value
LCD_PM1
Reset value
LCD_PM2
Reset value
LCD_PM3
Reset value
LCD_PM4
Reset value
LCD_PM5
Reset value
Reserved
LCD_RAM0
Reset value
LCD_RAM1
Reset value
LCD_RAM2
Reset value
LCD_RAM3
Reset value
LCD_RAM4
Reset value
LCD_RAM5
Reset value
LCD_RAM6
Reset value
LCD_RAM7
Reset value
LCD_RAM8
Reset value
LCD_RAM9
Reset value
LCD_RAM10
Reset value
LCD_RAM11
Reset value
Table 62. LCD register map
6 5 4 7 3 2 1 0
BLINK1
0
PON2
0
Reserved
0
PS3
0
BLINK0
0
PON1
0
LCDEN
0
PS2
0
BLINKF2
0
PON0
0
SOFIE
0
PS1
0
BLINKF1
0
HD
0
SOF
0
PS0
0
BLINKF0
0
CC2
0
SOFC
0
DIV3
0
DUTY1
0
CC1
0
DEAD2
0
DIV2
0
DUTY0
0
CC0
0
DEAD1
0
DIV1
0
PM_SEG[7:0]
00000000
PM_SEG[15:8]
00000000
PM_SEG[23:16]
00000000
PM_SEG[31:24] (1)
00000000
PM_SEG[39:32]
00000000
Reserved
SEG[43:40]
00000000
Reserved
S0[7:0] (COM0 or COM4) (4)
00000000
00000000
00000000
0000
S1[11:4] (COM1 or COM5)
00000000
0000
00000000
00000000
00000000
00000000
00000000
0000
0000
S3[11:4] (COM3 or COM7)
00000000
B2
0
VSEL
0
DEAD0
0
DIV0
0
RM0031 Rev 15
286
LCD controller RM0031
Table 62. LCD register map (continued)
Address offset
Register name
7 6 5 4 3 2 1 0
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22 to 0x2E
LCD_RAM12
Reset value
LCD_RAM13
Reset value
LCD_RAM14
Reset value
LCD_RAM15
Reset value
LCD_RAM16
Reset value
LCD_RAM17
Reset value
LCD_RAM18
Reset value
LCD_RAM19
Reset value
LCD_RAM20
Reset value
LCD_RAM21
Reset value
Reserved
Reset value
00000000
00000000
S0[35:28] (COM0 or COM4)
00000000
00000000
Reserved
00000000
00000000
S1[35:28] (COM1 or COM5)
00000000
00000000
S2[35:28] (COM2 or COM6)
00000000
00000000
S3[35:28] (COM3 or COM7)
00000000
0x2F
LCD_CR4
Reset value
Reserved
00000
PAGE_
COM
0
DUTY8
0
1.
On STM8L05xx value line devices, refer to datasheet for more details.
2.
PM_SEG[39:28] available on medium+ and high-density devices only. Reserved on medium-density devices.
3.
Available on medium+ and high-density devices only. Reserved on medium-density devices.
4.
COM4, 5, 6 and 7 are available on medium+ and high-density devices only and are activated by setting the DUTY8 bit in the LCD_CR4.
5.
Not available on STM8L05xx value line high-density devices.
B4
0
RM0031 Rev 15
RM0031 Timer overview
Symbol t w(ICAP)in t res(TIM)
Res
TIM t
COUNTER
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The devices in the STM8L05xx, STM8L15xx and STM8L16xx family may be equipped with up to three different timer types: Advanced control (TIM1), general purpose
(TIM2/TIM3/TIM5), and basic timer (TIM4). The timers share the same architecture, but some have additional unique features. The common timer architecture, which includes identical register mapping and common basic features, simplifies their use and makes it
easier to design applications. Table 63
shows the main timer characteristics.
The TIM5 general purpose timer is available on low, medium+ and high-density devices only
(not on medium-density devices). The TIM1 advanced control timer is not available on lowdensity devices. Refer to the product datasheets for more details.
Although the timers do not share any resources, they can be linked together and synchronized.
This section gives a comparison of the different timer features (
internal timer signal names ( Table 65
).
Section 19: 16-bit advanced control timer (TIM1) contains a full description of all the various
timer modes. The other timer sections ( Section 20
and
) are more brief and give only specific details on each timer, its block diagram, and register description. t
MAX_COUNT
Table 63. Timer characteristics
Parameter Min
Input capture pulse time
Timer resolution time
Timer resolution with 16-bit counter
Timer resolution with 8-bit counter
Counter clock period when internal clock is selected
Maximum possible count with 16-bit counter
Maximum possible count with 8-bit counter
2
1
Typ
16
8
1
Max
65,536
256
Unit
1/f
SYSCLK
1/f
SYSCLK bit bit
1/f
SYSCLK
1/f
SYSCLK
1/f
SYSCLK
RM0031 Rev 15
417
Timer overview RM0031
Timer
Counter resolution
Counter type
Table 64. Timer feature comparison
Prescaler factor
Capture/ compare channels
Complementary outputs
Repetition counter
External trigger input
External break input
Timer synchronization/ chaining
TIM1
(advanced control timer)
TIM2, TIM3 and TIM5
(general purpose timers)
TIM4
(basic timer)
16-bit
8-bit
Up/down
Any integer from 1 to
65536
Up/down
Any power of
2 from 1 to
128
Up
Any power of
2 from 1 to
32768
3 + 1
2
0
3
None
Yes
No
1
1
0
1
1
0
Yes
RM0031 Rev 15
RM0031 Timer overview
18.2 Glossary of timer signal names
Table 65. Glossary of internal timer signals
Internal signal name Description Related figures f
BI
CC i I: CC1I, CC2I, CC3I, CC4I
CK_CNT
CK_PSC
CNT_EN
CNT_INIT
ETR
ETRF
ETRP
SYSCLK
IC
IC i i
PS: IC1PS, IC2PS
ITR
: IC1, IC2
MATCH1
OC
OC
TGI
TI
TI
TI1_ED
TI i i i i i i
: ITR0, ITR1, ITR2, ITR3
: OC1, OC2
REF: OC1REF, OC2REF
: TI1, TI2
F: TI1F, TI2F
FPn: TI1FP1, TI1FP2,
TI2FP1, TI2FP2, TI3FP3,
TI3FP4, TI4FP3, TI4FP4
TRC
Break interrupt
Capture/compare interrupt
Counter clock
Prescaler clock
Counter enable
Figure 67: TIM1 general block diagram on page 293
Figure 71: Counter update when ARPE =
0 (ARR not preloaded) with prescaler = 2 on page 297
Counter initialize
Timer input
Timer input filtered
Timer input edge detector
Figure 81: TI2 external clock connection example on page 305
External trigger from
TIMx_ETR pin
External trigger filtered
External trigger prescaled
Figure 83: External trigger input block diagram on page 307
Timer peripheral clock from clock controller
(CLK)
Input capture
Input capture prescaled
Internal trigger input tied to TRGO of other
TIM timers
Figure 17: Clock structure on page 88
Figure 100: Input stage of TIM 1 channel 1 on page 321
Figure 67: TIM1 general block diagram on page 293
Compare match
Figure 90: Trigger/master mode selection blocks on page 314 and
Control register 2 (TIM1_CR2) on page 346
Timer output channel
Output compare reference signal
Figure 125: Output stage of channel 1 on page 384
Trigger interrupt
Figure 79: Clock/trigger controller block diagram on page 304
Figure 100: Input stage of TIM 1 channel 1 on page 321
Timer input filtered prescaled
Trigger capture
RM0031 Rev 15
417
Timer overview RM0031
UEV
UIF
Table 65. Glossary of internal timer signals (continued)
Internal signal name Description Related figures
TRGI
TRGO
Trigger input to clock/trigger/slave mode controller
Trigger output tied to trigger input INTx of other timers
Update event
Update interrupt
Figure 80: Control circuit in normal mode, f
Figure 67: TIM1 general block diagram on page 293
Figure 71: Counter update when ARPE =
0 (ARR not preloaded) with prescaler = 2 on page 297
i n x
Table 66. Explanation of indices‘ i ’, ‘n’, and ‘x’
(1)
Signal number: May be 1, 2, 3, 4 depending on the device
Bit number: May be 1, 2, 3, 4 ........ depending on the device
Register number: May be 1, 2, 3, 4 depending on the device
Signal number (when i is already used): May be 1, 2, 3, 4 depending on the device
Timer number: May be 1, 2, 3, 4, 5, 6 depending on the device
Don’t care (for bits)
1. These indices are used in
.
RM0031 Rev 15
RM0031
19
16-bit advanced control timer (TIM1)
16-bit advanced control timer (TIM1)
This section gives a description of the full set of timer features.
TIM1 consists of a 16-bit up-down auto-reload counter driven by a programmable prescaler.
The timer may be used for a variety of purposes, including:
• Time base generation
• Measuring the pulse lengths of input signals (input capture)
• Generating output waveforms (output compare, PWM and one-pulse mode)
• Interrupt capability on various events (capture, compare, overflow, break, trigger)
• DMA request capability on capture, compare, overflow events
• Synchronization with other timers or external signals (external clock, reset, trigger and enable).
This timer is ideally suited for a wide range of control applications, including those requiring center-aligned PWM capability with complementary outputs and deadtime insertion.
The timer clock can be sourced from internal clocks or from an external source selectable through a configuration register.
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
19.2 TIM1 main features
TIM1 features include:
• 16-bit up, down, up/down counter auto-reload counter
• Repetition counter to update the timer registers only after a given number of cycles of the counter.
• 16-bit programmable prescaler allowing the counter clock frequency to be divided “on the fly” by any factor between 1 and 65536.
• Synchronization circuit to control the timer with external signals and to interconnect several timers.
• 3 independent channels (channel 1, channel 2 and channel 3) that can alternately be configured as:
– Input capture
– Output compare
– PWM generation (edge and center-aligned mode)
– 6-step PWM generation
– One-pulse mode output
– Complementary outputs on three channels with programmable deadtime insertion.
• One additional capture/compare channel (channel 4) not connected to external output
• Break input to put the timer output signals in reset state or in a known state.
• External trigger input pin (ETR)
• OCREFCLR signal or break input can be connected internally to comparator 2
(COMP2) output
• Input capture 2 and input capture 3 channels can be routed from 21 selected I/Os
• Interrupt generation on the following events:
– Update: Counter overflow/underflow, counter initialization (by software or internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
– Break input
– Commutation event
• DMA request generation on the following events:
– Update: counter overflow/underflow
– Input capture
– Output compare
– Commutation event
• DMA burst transfer mode
RM0031 Rev 15
RM0031 fSYSCLK
TIM1_ETR
TRGO from other TIM timers
ETR
ITR
TRC
16-bit advanced control timer (TIM1)
Figure 67. TIM1 general block diagram
TRGO to other TIM timers
CLOCK/TRIGGER CONTROLLER
Clock/reset/enable
TIME BASE UNIT
CK_PSC
Prescaler
CK_CNT
UP-DOWN COUNTER Auto-reload register
TIM1_CH1 TI1
TIM1_CH2 TI2
TIM1_CH3 TI3
INPUT
STAGE
BRK from COMP2
IC1
CAPTURE COMPARE ARRAY
Prescaler
CC1I
IC1PS
UEV
Capture/compare 1 register
OC1REF
IC2
CC2I
Prescaler
IC2PS
UEV
Capture/compare 2 register
OC2REF
IC3
CC3I
Prescaler
IC3PS
UEV
Capture/compare 3 register
OC3REF
CC4I
Prescaler
IC4PS
UEV
Capture/compare 4 register
OC4REF
OUTPUT
STAGE
OCREFCLR from COMP2
ETRF from clock/trigger control block
OC1
OC1N
TIM1_CH1
TIM1_NCH1
OC2
OC2N
TIM1_CH2
TIM1_NCH2
OC3
OC3N
TIM1_CH3
TIM1_NCH3
TIM1_BKIN
Legend:
Reg
Preload registers transferred to shadow registers on update event (UEV) according to control bit
Event
Interrupt/DMA request
RM0031 Rev 15
417
16-bit advanced control timer (TIM1)
19.3 TIM1 time base unit
The timer has a time base unit that includes:
• 16-bit up/down counter
• 16-bit auto-reload register
• Repetition counter
• Prescaler
Figure 68. Time base unit
RM0031
Note:
The 16-bit counter, the prescaler, the auto-reload register and the repetition counter register can be written or read by software.
The auto-reload register is composed of a preload register plus a shadow register.
Writing to the auto-reload register can be done in two modes:
• Auto-reload preload enabled (ARPE bit set in the TIM1_CR1 register). In this mode, when data is written to the auto-reload register, it is kept in the preload register and transferred into the shadow register at the next update event (UEV).
• Auto-reload preload disabled (ARPE bit cleared in the TIM1_CR1 register). In this mode, when data is written to the auto-reload register it is transferred into the shadow register immediately.
An update event is generated:
• On a counter overflow or underflow
• By software, setting the UG bit in the TIM1_EGR register
• By a trigger event from the clock/trigger controller
With preload enabled (ARPE = 1), when an update event occurs: The auto-reload shadow register is updated with the preload value (TIM1_ARR) and the buffer of the prescaler is reloaded with the preload value (content of the TIM1_PSCR register).
The UEV can be disabled by setting the UDIS bit in the TIM1_CR1
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIM1_CR1 register is set.
The actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.3.1 Reading and writing to the 16-bit counter
Note:
There is no buffering when writing to the counter. Both TIM1_CNTRH and TIM1_CNTRL can be written at any time, so it is suggested not to write a new value into the counter while it is running to avoid loading an incorrect intermediate content.
An 8-bit buffer is implemented for the read. Software must read the MS byte first, after which the LS byte value is buffered automatically (see
). This buffered value remains unchanged until the 16-bit read sequence is completed.
Do not use the LDW instruction to read the 16-bit counter. It reads the LS byte first and returns an incorrect result.
Figure 69. 16-bit read sequence for the counter (TIM1_CNTR)
19.3.2 Write sequence for 16-bit TIM1_ARR register
16-bit values are loaded in the TIM1_ARR register through preload registers. This must be performed by two write instructions, one for each byte. The MS byte must be written first.
The shadow register update is blocked as soon as the MS byte has been written, and stays blocked until the LS byte has been written. Do not use the LDW instruction as this writes the
LS byte first which produces incorrect results.
19.3.3 Prescaler
The prescaler implementation is as follows:
The TIM1 prescaler is based on a 16-bit counter controlled through a 16-bit register (in
TIM1_PSCR register). It can be changed on the fly as this control register is buffered. It can divide the counter clock frequency by any factor between 1 and 65536.
The counter clock frequency is calculated as follows: f
CK_CNT
= f
CK_PSC
/(PSCR[15:0]+1)
The prescaler value is loaded through a preload register. The shadow register, which contains the current value to be used, is loaded as soon as the LS byte has been written.
To update the 16-bit prescaler, load two bytes in separate write operations starting with the
MSB. Do not use the LDW instruction for this purpose as it writes the LSB first.
The new prescaler value is taken into account in the following period (after the next counter update event).
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Read operations to the TIM1_PSCR registers access the preload registers, so no special care needs to be taken to read them.
In up-counting mode, the counter counts from 0 to a user-defined compare value (content of the TIM1_ARR register). It then restarts from 0 and generates a counter overflow event and a UEV if the UDIS bit is 0 in the TIM1_CR1 register.
shows an example of this counting mode.
Figure 70. Counter in up-counting mode
Counter
TIMx_ARR
O
Overflow Overflow Overflow Overflow Time
MSv45278V1
An update event can also be generated by setting the UG bit in the TIM1_EGR register
(either by software or by using the trigger controller).
The UEV can be disabled by software by setting the UDIS bit in the TIM1_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers.
No UEV occurs until the UDIS bit has been written to 0. Note that the counter and the prescaler restart counting from 0 but, the prescaler division factor does not change. In addition, if the URS bit (update request selection) in the TIM1_CR1 register is set, setting the UG bit generates an UEV without setting the UIF flag. Consequently, no interrupt or
DMA request is sent. This avoids generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR1 register) is set (depending on the URS bit):
• The auto-reload shadow register is updated with the preload value (TIM1_ARR).
• The buffer of the prescaler is reloaded with the preload value (content of the
TIM1_PSCR register).
and
Figure 72 show two examples of the counter behavior for different clock
frequencies when TIM1_ARR = 0x36.
In Figure 71 , the prescaler divider is set to 2, so the counter clock (CK_CNT) frequency is at
half the frequency of the prescaler clock source (CK_PSC). The auto-reload preload is disabled (ARPE = 0). Consequently, the shadow register is immediately changed and counter overflow occurs when upcounting reaches 0x36. This generates a UEV.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 71. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2
In
Figure 72 the prescaler divider is set to 1, so CK_CNT has the same frequency as
CK_PSC. The auto-reload preload is enabled (ARPE = 1), so the next counter overflow occurs at 0xFF. The new auto-reload value register value of 36h is taken into account after the overflow which generates a UEV.
Figure 72. Counter update event when ARPE = 1 (TIM1_ARR preloaded)
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
In down-counting mode, the counter counts from the auto-reload value (content of the
TIM1_ARR register) down to 0. It then restarts from the auto-reload value and generates a counter underflow and a UEV, if the UDIS bit is 0 in the TIM1_CR1 register.
shows an example of this counting mode.
Figure 73. Counter in down-counting mode
TIMx_ARR
0
Underflow Underflow Underflow Underflow Time
MSv45281V1
An update event can also be generated by setting the UG bit in the TIM1_EGR register (by software or by using the clock/trigger mode controller).
The UEV update event can be disabled by software by setting the UDIS bit in TIM1_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. No update event occurs until the UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (without any change to the prescale rate).
In addition, if the URS bit (update request selection) in the TIM1_CR1 register is set, setting the UG bit generates a UEV without setting the UIF flag (thus no interrupt or DMA request is sent). This avoids generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR1 register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the
TIM1_PSCR register),
• The auto-reload shadow register is updated with the preload value (content of the
TIM1_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.
and
Figure 75 show some examples of the counter behavior for different clock
frequencies when TIM1_ARR = 0x36.
In downcounting mode, preload is not normally used. Consequently, the new value is taken
into account in the next period (see Figure 74 ).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 74. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2
Figure 75. Counter update when ARPE = 1 (ARR preloaded), with prescaler = 1
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
In center-aligned mode, the counter counts from 0 to the auto-reload value of -1 (content of the TIM1_ARR register). This generates a counter overflow event. The counter then counts down to 0 and generates a counter underflow event. After this, the counter restarts counting from 0.
In this mode, the direction bit (DIR) in the TIM1_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.
The
shows an example of this counting mode.
Figure 76. Counter in center-aligned mode
Counter
TIMx_ARR
0
Overflow Underflow Overflow Underflow Time
MSv45279V1
If the timer has a repetition counter (as in TIM1), the UEV is generated after up and down counting and repeated for the number of times programmed in the repetition counter register (TIM1_RCR). Otherwise, the UEV is generated at each counter overflow and at each counter underflow.
Setting the UG bit in the TIM1_EGR register (by software or by using the clock/trigger mode controller) also generates an update event. In this case, the counter and the prescaler restart counting from 0.
The UEV can be disabled by software by setting the UDIS bit in the TIM1_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers.
In this way, no update event occurs until the UDIS bit is written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In timers with a repetition counter, the new update rate is used because the repetition register is not double buffered. For this reason, care must be taken when changing the update rate.
In addition, if the URS bit in the TIM1_CR1 register is set, setting the UG bit generates a
UEV without setting the UIF flag. Consequently, no interrupt or DMA request is sent. This avoids generating both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all registers are updated and the update flag (the UIF bit in the TIM1_SR1 register) is set (depending on the URS bit).
• The buffer of the prescaler is reloaded with the preload value (content of the
TIM1_PSCR register).
• The auto-reload shadow register is updated with the preload value (content of the
TIM1_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).
Below are some examples of the counter behavior for different clock frequencies.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 77. Counter timing diagram, f
CK_CNT
= f
CK_PSC
, TIM1_ARR = 06h, ARPE = 1
Hints on using center-aligned mode:
• When starting in center-aligned mode, the current up-down configuration is used. It means that the counter starts counting up or down depending on the value written in the DIR bit in the TIM1_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:
– The direction is not updated if a value is written in the counter that is greater than the auto-reload value (TIM1_CNT>TIM1_ARR). For example, if the counter is counting up, it continues to do so.
– The direction is updated if 0 or the TIM1_ARR value are written in the counter but no UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIM1_EGR register) just before starting the counter. Avoid writing to the counter while it is running.
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Section 19.3: TIM1 time base unit
describes how the UEV is generated with respect to counter overflows/underflows. It is generated only when the repetition down-counter reaches zero. This can be useful while generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIM1_ARR auto-reload register, TIM1_PSCR prescaler register, and TIM1_CCRx capture/compare registers in compare mode) every ‘n’ counter overflow or underflow, where
N is the value in the TIM1_RCR repetition counter register.
The repetition down-counter is decremented:
• At each counter overflow in up-counting mode
• At each counter underflow in down-counting mode
• At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetitions to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is
2 x t
CK_PSC
due to the symmetry of the pattern.
The repetition down-counter is an auto-reload type, the repetition rate of which is
maintained as defined by the TIM1_RCR register value (refer to Figure 78 ). When the UEV
is generated by software (by setting the UG bit in the TIM1_EGR register) or by hardware
(through the clock/trigger controller), it occurs immediately irrespective of the value of the repetition down-counter. The repetition down-counter is reloaded with the content of the
TIM1_RCR register.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 78. Update rate examples depending on mode and TIM1_RCR register settings
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
The clock/trigger controller allows the timer clock sources, input triggers, and output triggers
to be configured. The block diagram is shown in Figure 79.
Figure 79. Clock/trigger controller block diagram f
SYSCLK
TIM1_ETR
ETR
TRGO from TIM4 (ITR0)
TRGO from TIM5 (ITR1)
TRGO from TIM3 (ITR2)
TRGO from TIM2 (ITR3)
From input stage
Polarity selection & edge detector & prescaler
ETRP
Input filter
ITR
TRC
TI1F_ED
ETRF
Trigger
Controller
TGI
TRGI
Clock/Trigger
Mode
Controller
TRGO
To other timers
& ADC
Reset, Enable,
Up/Down, Count
CK_PSC
To Time Base Unit
From input stage
TI1FP1
TI2FP2
Encoder
Interface
19.4.1 Prescaler clock (CK_PSC)
The time base unit prescaler clock (CK_PSC) can be provided by the following clock sources:
• Internal clock ( f
SYSCLK
)
• External clock mode 1: External timer input (TIx)
• External clock mode 2: External trigger input (ETR)
• Internal trigger inputs (ITR i ): using one timer as prescaler for another timer. Refer to
Using one timer as prescaler for another timer on page 314
for more details.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.4.2 Internal clock source (f
SYSCLK
)
If both the clock/trigger mode controller and the external trigger input are disabled
(SMS = 000 in TIM1_SMCR and ECE = 0 in the TIM1_ETR register), the CEN, DIR, and UG bits behave as control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock.
The figure below shows the behavior of the control circuit and the up-counter in normal mode, without the prescaler.
Figure 80. Control circuit in normal mode, f
CK_PSC
= f
SYSCLK f
SYSCLK
CEN = CNT_EN
UG
CNT_INIT (=UG synchronized: UG or UG+1 clock)
COUNTER CLOCK = CK_CNT = CK_PSC
COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07
19.4.3 External clock source mode 1
The counter can count at each rising or falling edge on a selected timer input. This mode is
selected when SMS = 111 in the TIM1_SMCR register (see Figure 81 ).
Figure 81. TI2 external clock connection example
TIM1_SMCR
TS[2:0]
TI2
Filter
ICF[3:0]
TIM1_CCMR2
TRGO from other timers ti2f_rising ti2f_falling
0
1
TI1F_ED
TI1FP1
TI2FP2
ETRF
CC2P
TIM1_CCER1 or
TI2F or
TI1F or Encoder mode
100
101
110
111
TRGI External clock mode 1
ETRF External clock mode 2 f
SYSCLK
(internal clock)
Internal clock mode
CK_PSC
ECE
TIM1_ETR
SMS[2:0]
TIM1_SMCR
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Procedure
Use the following procedure to configure the up-counter and, for example, to count in response to a rising edge on the TI2 input:
1.
Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = 01 in the
TIM1_CCMR2 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIM1_CCMR2 register (if no filter is needed, keep IC2F = 0000).
Note: The capture prescaler is not used for triggering, so it does not need t o be configured. The CC2S bits do not need to be configured either as they only select the input capture source.
3. Select rising edge polarity by writing CC2P = 0 in the TIM1_CCER1 register.
4. Configure the timer in external clock mode 1 by writing SMS = 111 in the TIM1_SMCR register.
5. Select TI2 as the input source by writing TS = 110 in the TIM1_SMCR register.
6. Enable the counter by writing CEN = 1 in the TIM1_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the trigger flag is set (TIF bit in the TIM1_SR1 register) and an interrupt request can be sent if enabled (depending on the
TIE bit in the TIM1_IER register).
The delay between the rising edge on TI2 and the actual reset of the counter is due to the resynchronization circuit on TI2 input.
Figure 82. Control circuit in external clock mode 1
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.4.4 External clock source mode 2
The counter can count at each rising or falling edge on the ETR. This mode is selected by writing ECE = 1 in the TIM1_ETR register.
The
gives an overview of the external trigger input block.
Figure 83. External trigger input block diagram or
TI2F or
TI1F or
ETR pin
ETR
0
1
ETP
TIM1_ETR divider
/1, /2, /4, /8
ETRP f
SYSCLK filter down-counter
ETPS[1:0]
TIM1_ETR
ETF[3:0]
TIM1_ETR
TRGI
CK_PSC
ETRF f
SYSCLK
(internal clock)
ECE
TIM1_ETR
SMS[2:0]
TIM1_SMCR
Procedure
Use the following procedure to configure the up-counter and, for example, to count once every two rising edges on the ETR:
1.
As no filter is needed in this example, write ETF[3:0] = 0000 in the TIM1_ETR register.
2. Set the prescaler by writing ETPS[1:0] = 01 in the TIM1_ETR register.
3. Select rising edge detection on the ETR pin by writing ETP = 0 in the TIM1_ETR register.
4. Enable external clock mode 2 by writing ECE = 1 in the TIM1_ETR register.
5. Enable the counter by writing CEN = 1 in the TIM1_CR1 register.
The counter counts once every two ETR rising edges.
The delay between the rising edge on the ETR and the actual reset of the counter is due to the resynchronization circuit on the external trigger signal (ETRP).
Figure 84. Control circuit in external clock mode 2 f
SYSCLK
CNT_EN
ETR
ETRP
ETRF
COUNTER CLOCK = CK_CNT = CK_PSC
COUNTER REGISTER 34 35 36
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
There are four trigger inputs (refer to
Table 65: Glossary of internal timer signals on page 289
):
• ETR
• TI1
• TI2
• TRGO from other timers
The TIM1 timer can be synchronized with an external trigger in three modes: Trigger standard mode, trigger reset mode and trigger gated mode.
Trigger standard mode
The counter can start in response to an event on a selected input.
Procedure
Use the following procedure to start the up-counter in response, for example, to a rising edge on the TI2 input:
1.
Configure channel 2 to detect rising edges on TI2. As no filter is required in this example, configure an input filter duration of 0 (IC2F = 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC2S bits select the input capture source and do not need to be configured either. Write CC2P = 0 in the
TIM1_CCER1 register to select rising edge polarity.
2. Configure the timer in trigger mode by writing SMS = 110 in the TIM1_SMCR register.
Select TI2 as the input source by writing TS = 110 in the TIM1_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual reset of the counter is due to the resynchronization circuit on TI2 input.
Figure 85. Control circuit in trigger mode
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Trigger reset mode
The counter and its prescaler can be re-initialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIM1_CR1 register is low, a UEV is generated. Then all the preloaded registers (TIM1_ARR, TIM1_CCR i ) are updated.
Example
Use the following procedure to clear the up-counter in response to a rising edge on TI1 input:
1.
Configure channel 1 to detect rising edges on TI1. As no filter is required in this example, configure an input filter duration of 0 (IC2F = 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC1S bits select the input capture source and do not need to be configured either. Write CC1P = 0 in
TIM1_CCER1 register to validate the polarity (and detect rising edges).
2. Configure the timer in reset mode by writing SMS = 100 in TIM1_SMCR register. Select
TI1 as the input source by writing TS = 101 in the TIM1_SMCR register.
3. Start the counter by writing CEN = 1 in the TIM1_CR1 register.
The counter starts counting on the internal clock and behaves normally until the TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIM1_SR1 register) and an interrupt request can be sent if enabled (depending on the TIE in the TIM1_IER register).
shows this behavior when the auto-reload register TIM1_ARR = 36h. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
Figure 86. Control circuit in trigger reset mode
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Trigger gated mode
The counter can be enabled depending on the level of a selected input.
Example
Use the following procedure to enable the up-counter when TI1 input is low:
1.
Configure channel 1 to detect low levels on TI1. Configure the input filter duration (IC1F
= 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC1S bits select the input capture source and do not need to be configured either. Write CC1P = 1 in the TIM1_CCER1 register to validate the polarity
(and detect low level).
2. Configure the timer in trigger gated mode by writing SMS = 101 in the TIM1_SMCR register. Select TI1 as the input source by writing TS = 101 in the TIM1_SMCR register.
3. Enable the counter by writing CEN = 1 in the TIM1_CR1 register (in trigger gated mode, the counter does not start if CEN = 0 irrespective of the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low. It stops as soon as
TI1 becomes high. The TIF flag is set when the counter starts or stops.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input.
Figure 87. Control circuit in trigger gated mode
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Combining trigger modes with external clock mode 2
External clock mode 2 can be used with another trigger mode. For example, the ETR can be used as the external clock input, and a different input can be selected as trigger input (in trigger standard mode, trigger reset mode, or trigger gated mode). Care must be taken not to select ETR as TRGI (through the TS bits in the TIM1_SMCR register).
Example
Use the following procedure to enable the up-counter at each rising edge on the ETR as soon as a rising edge occurs on TI1 (standard trigger mode with external ETR clock):
1.
Configure the external trigger input circuit by writing to the TIM1_ETR register. Write
ETF = 0000 (no filter needed in this example). Write ETPS = 00 to disable the prescaler, write ETP = 0 to detect rising edges on the ETR, and write ECE = 1 to enable external clock mode 2.
2. Configure channel 1 to detect rising edges on TI1. Configure the input filter duration
(IC1F = 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC1S bits select the input capture source and do not need to be configured either. Write CC1P = 0 in the TIM1_CCER1 register to select rising edge polarity.
3. Configure the timer in trigger mode by writing SMS = 110 in the TIM1_SMCR register.
Select TI1 as the input source by writing TS = 101 in the TIM1_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. Consequently, the counter counts on the ETR rising edges.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. The delay between the rising edge on the ETR and the actual reset of the counter is due to the resynchronization circuit on the ETRP signal.
Figure 88. Control circuit in external clock mode 2 + trigger mode
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
19.4.6 Synchronization between timers
On STM8AF and STM8S low-density devices, the timers are linked together internally for timer synchronization or chaining. When one timer is configured in master mode, it can output a trigger (TRGO) to reset, start, stop, or clock the counter of any other timer configured in slave mode.
RM0031 Rev 15
RM0031
TRGO from TIM4
TRGO from TIM5
TRGO from TIM3
TRGO from TIM2
ITR0
ITR1
ITR2
ITR3
16-bit advanced control timer (TIM1)
Figure 89. Timer chaining system implementation example
TIM 1
TIM 2
TIM1_CH1
TIM1_CH2
TI1
TI2
Trigger
Controller
TRGO
TRGO from TIM4
TRGO from TIM1
ITR0
ITR1
TRGO from TIM3
TRGO from TIM5
ITR2
ITR3
Trigger
Controller
TRGO
TIM 4
TIM2_CH1
TIM2_CH2
TI1
TI2
TRGO from TIM5
TRGO from TIM1
TRGO from TIM3
TRGO from TIM2
ITR0
ITR1
ITR2
ITR3
Trigger
Controller
TRGO
TIM 3
TRGO from TIM4
TRGO from TIM1
TRGO from TIM5
ITR0
ITR1
ITR2
TRGO from TIM2
ITR3
Trigger
Controller
TRGO
TRGO from TIM4
TRGO from TIM1
TRGO from TIM3
TRGO from TIM2
ITR0
ITR1
ITR2
ITR3
TIM 5
TIM3_CH1
TIM3_CH2
TI1
TI2
Trigger
Controller
TRGO
TIM5_CH1
TIM5_CH2
TI1
TI2
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
presents an overview of the trigger selection and the master mode selection blocks.
Figure 90. Trigger/master mode selection blocks
TRIGGER SELECTION BLOCK
TRGO from TIM4
TRGO from TIM5
TRGO from TIM3
TRGO from TIM2
ITR0
ITR1
ITR2
ITR3
From the Capture/
Compare block
TI1F_ED
TI1FP1
TI2FP2
ETRF
ITR
TIMx_SMCR
TS[2:0]
TRC
TRGI
MASTER MODE SELECTION BLOCK
UG
CNT_EN
UEV
MATCH1
OC1REF
OC3REF
OC3REF
OC4REF
TRGO
MMS[2:0]
TIMx_CR2
Note:
Using one timer as prescaler for another timer
Refer to Figure 91 to see how timer A can be configured to act as a prescaler for timer B.
1.
Configure timer A in master mode so that it outputs a periodic trigger signal on each
UEV. To configure that a rising edge is output on TRGO1 each time an update event is generated, write MMS = 010 in the TIMx_CR2 register.
2. Connect the TRGO1 output of timer A to timer B, timer B must be configured in slave mode using ITR1 as the internal trigger. Select this through the TS bits in the
TIMx_SMCR register (see TS[2:0] bit definitions in TIMx_SMCR register).
3. Put the clock/trigger controller in external clock mode 1, by writing SMS = 111 in the
TIMx_SMCR register. This causes timer B to be clocked by the rising edge of the periodic timer A trigger signal (which corresponds to the timer A counter overflow).
4. Enable both timers by setting their respective CEN bits (TIMx_CR1 register).
If OCi is selected on timer A as trigger output (MMS = 1xx), its rising edge is used to clock the counter of timer B.
Figure 91. Master/slave timer example
RM0031 Rev 15
RM0031
Note:
16-bit advanced control timer (TIM1)
Using one timer to enable another timer
Example 1
The enable of timer B is controlled with the output compare 1 of timer A (refer to
for connections). Timer B counts on the divided internal clock only when OC1REF of timer A f is high. Both counter clock frequencies are divided by four by the prescaler compared to
SYSCLK
(f
CK_CNT
= f
SYSCLK
/4).
1.
Configure timer A master mode to send its output compare 1 reference (OC1REF) signal as trigger output (MMS = 100 in the TIMx_CR2 register).
2. Configure the timer A OC1REF waveform (TIMx_CCMR1 register)
3. Configure timer B to get the input trigger from timer A (see TS[2:0] bit definitions in
TIMx_SMCR register).
4. Configure timer B in trigger gated mode (SMS = 101 in TIMx_SMCR register)
5. Enable timer B by writing 1 in the CEN bit (TIMx_CR1 register)
6. Start timer A by writing 1 in the CEN bit (TIMx_CR1 register)
The counter 2 clock is not synchronized with counter 1. This mode only affects the timer B counter enable signal.
Figure 92. Gating timer B with OC1REF of timer A f
SYSCLK
Timer A-OC1REF
Timer A-CNT
Timer B-CNT
Timer B-TIF
3045
FC FD
3046
FE
3047
FF 00
3048
01
Write TIF=0
In
Figure 92 , the timer B counter and prescaler are not initialized before being started.
Therefore, they start counting from their current value. It is possible to start from a given value by resetting both timers before starting timer A. In this case, any value can be written in the timer counters. The timers can easily be reset by software using the UG bit in the
TIMx_EGR registers.
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
Example 2
Timer A and timer B are synchronized. Timer A is the master and starts from 0. Timer B is the slave and starts from E7h. The prescaler ratio is the same for both timers. Timer B stops when timer A is disabled by writing 0 to the CEN bit in the TIMx_CR1 register:
1.
Configure timer A master mode to send its output compare 1 reference (OC1REF) signal as trigger output (MMS = 100 in the TIMx_CR2 register).
2. Configure the timer A OC1REF waveform (TIMx_CCMR1 register)
3. Configure timer B to get the input trigger from timer A (see TS[2:0] bit definitions in
TIMx_SMCR register).
4. Configure timer B in trigger gated mode (SMS = 101 in TIMx_SMCR register)
5. Reset timer A by writing 1 in UG bit (TIMx_EGR register)
6. Reset timer B by writing 1 in UG bit (TIMx_EGR register)
7. Initialize timer B to 0xE7 by writing ‘E7h’ in the timer B counter (TIMx_CNTRL)
8. Enable timer B by writing 1 in the CEN bit (TIMx_CR1 register)
9. Start timer A by writing 1 in the CEN bit (TIMx_CR1 register)
10. Stop timer A by writing 0 in the CEN bit (TIMx_CR1 register)
Figure 93. Gating timer B with the counter enable signal of timer A (CNT_EN) f
SYSCLK
Timer A-CEN = CNT_EN
Timer A-UG
Timer A-CNT
Timer B-CNT
Timer B-UG
Timer B write CNT
Timer B-TIF
75
AB 00
00
E7
Write TIF=0
01
E8
02
E9
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Using one timer to start another timer
Example 1
The enable of timer B is set with the UEV of timer A (refer to
for connections).
Timer B starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the UEV is generated by timer A. When timer B receives the trigger signal, its CEN bit is automatically set and the counter counts until 0 is written to the
CEN bit in the TIM1_CR1 register. Both counter clock frequencies are divided by four by the prescaler compared to f
SYSCLK
(f
CK_CNT
= f
SYSCLK
/4).
1.
Configure timer A master mode to send its UEV as trigger output (MMS = 010 in the
TIM1_CR2 register).
2. Configure the timer A period (TIM1_ARR registers)
3. Configure timer B to get the input trigger from timer A (see TS[2:0] bit definitions in
TIM1_SMCR register).
4. Configure timer B in trigger mode (SMS = 110 in TIM1_SMCR register)
5. Start timer A by writing 1 in the CEN bit (TIM1_CR1 register)
Figure 94. Triggering timer B with the UEV of timer A (TIMERA-UEV) f
SYSCLK
Timer A-UEV
Timer A-CNT
Timer B-CNT
Timer B-CEN = CNT_EN
FD FE
45
FF 00
46
01
47
02
48
Timer B-TIF
Write TIF=0
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16-bit advanced control timer (TIM1) RM0031
Example 2
As in the previous example, both counters can be initialized before starting to count.
shows the behavior, with the same configuration as in
standard mode instead of trigger gated mode (SMS = 110 in the TIM1_SMCR register).
Figure 95. Triggering timer B with counter enable CNT_EN of timer A
Note: f
SYSCLK
Timer A-CEN = CNT_EN
Timer A-UG
Timer A-CNT
Timer B-CNT
Timer B-UG
Timer B write CNT
Timer B-TIF
75
CD 00
00
E7
01
E8 E9
02
EA
Write TIF=0
Starting 2 timers synchronously in response to an external trigger
Example
The enable of timer A is set when its TI1 input rises and the enable of timer B is set with the
enable of timer A (refer to Figure 91 for connections). To ensure the counters alignment,
timer A must be configured in master/slave mode (slave with respect to TI1, master with respect to timer B).
1.
Configure timer A master mode to send its enable as trigger output (MMS = 001 in the
TIMx_CR2 register).
2. Configure timer A slave mode to get the input trigger from TI1 (TS = 100 in the
TIMx_SMCR register).
3. Configure timer A in trigger mode (SMS = 110 in the TIMx_SMCR register)
4. Configure timer A in master/slave mode by writing MSM = 1 (TIMx_SMCR register)
5. Configure timer B to get the input trigger from timer A (see TS[2:0] bit definitions in
TIMx_SMCR register).
6. Configure timer B in trigger mode (SMS = 110 in the TIMx_SMCR register)
When a rising edge occurs on TI1 (timer A), both counters start counting synchronously on the internal clock and both TIF flags are set.
In this example both timers are initialized before starting (by setting their respective UG bits). Both counters start from 0, but an offset can easily be inserted between them by writing to any of the counter registers (TIMx _ CNT). It can be seen that the master/slave mode inserts a delay between CNT_EN and CK_PSC on timer A.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 96. Triggering Timer A and B with Timer A TI1 input f
SYSCLK
Timer A-TI1
Timer A-CEN = CNT_EN
Timer A-CK_PSC
Timer A-CNT
Timer A-TIF
Timer B-CEN = CNT_EN
Timer B-CK_PSC
Timer B-CNT
Timer B-TIF
00
00
01 02 03 04 05 06 07 08 09
01 02 03 04 05 06 07 08 09
The timer I/O pins (TIM1_CC i ) can be configured either for input capture or output compare functions. The choice is made by configuring the CC i S channel selection bits in the capture/compare channel mode registers (TIM1_CCMR i ), where i is the channel number.
Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Figure 97. Capture/compare channel 1 main circuit
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16-bit advanced control timer (TIM1) RM0031
The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are made in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.
When the channel is configured in output mode (CC i S = 00 in the TIM1_CCMR i registers), the TIM1_CCR i registers can be accessed without any restriction.
When the channel is configured in input mode, the sequence for reading the TIM1_CCR i registers is the same as for the counter (see
). When a capture occurs, the content of the counter is captured into the TIM1_CCR i shadow registers. Then this value is loaded into the preload register, except during a read sequence, when the preload register is frozen.
Figure 98. 16-bit read sequence for the TIM1_CCR i register in capture mode
shows the sequence for reading the CCR i registers in the 16-bit timers. This buffered value remains unchanged until the 16-bit read sequence is completed.
After a complete read sequence, if only the TIM1_CCR i L registers are read, they return the
LS byte of the count value at the time of the read.
If the MS byte is read after the LS byte, it no longer corresponds to the same captured value as the LS byte.
19.5.1 Write sequence for 16-bit TIM1_CCR
i
registers
16-bit values are loaded in the TIM1_CCR i registers through preload registers. This must be performed by two write instructions, one for each byte. The MS byte must be written first.
The shadow register update is blocked as soon as the MS byte has been written, and stays blocked until the LS byte is written. Do not use the LDW instruction, as this writes the LS byte first, and produces incorrect results in this case.
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RM0031 16-bit advanced control timer (TIM1)
TIM1_CH1
TIM1_CH2
TIM1_CH3
XOR
Figure 99. Channel input stage block diagram
TI1F_ED
TI1S
TI1
Input filter &
Edge detector
TI1FP1
TI1FP2
TRC
(from clock/trigger controller)
TI2
Input filter &
Edge detector
TI2FP1
TI2FP2
TRC
(from clock/trigger controller)
TI3
Input filter &
Edge detector
TI3FP3
TI3FP4
TRC
(from clock/trigger controller)
IC1
IC2
IC3
TRC to clock/trigger controller to capture/compare channels
IC4
TRC
(from clock/trigger controller)
Figure 100 shows how the input stage samples the corresponding TI
i input to generate a filtered signal TI i F. Then, an edge detector with polarity selection, generates a signal
(TI i FPn) which can be used as trigger input by the clock/trigger controller or as the capture command. The signal is prescaled before entering the capture register (IC i PS).
Figure 100. Input stage of TIM 1 channel 1 f
SYSCLK
TI1
TI1F_ED to clock/trigger controller filter down-counter
TI1F Edge detector
ICF[3:0]
TIMx_CCMR1
TI1F_rising
TI1F_falling
0
1
TI1FP1
TI2FP1
01
10
IC1 divider
/1, /2, /4, /8
CC1P
TIMx_CCER1
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
1
TRC
(from clock/trigger controller)
11
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
ICPS
CC1E
TIMx_CCER1
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16-bit advanced control timer (TIM1) RM0031
Note:
In input capture mode, the capture/compare registers (TIM1_CCR i ) are used to latch the value of the counter after a transition detected on the corresponding IC i signal. When a capture occurs, the corresponding CC i IF flag (TIM1_SR1 register) is set.
An interrupt or DMA request can be sent if it is enabled, by setting the CC i IE bits in the
TIM1_IER register or the CCxDE bit in the TIM1_DER register. If a capture occurs while the
CC i IF flag is already high, the over-capture flag CC i OF (TIM1_SR2 register) is set. CC i IF can be cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCR i L registers. CC i OF is cleared by writing it to 0.
Procedure
The following procedure shows how to capture the counter value in TIM1_CCR1, for example, when TI1 input rises.
1.
Select the active input: For example, to link the TIM1_CCR1 register to the TI1 input, write the CC1S bits to 01 in the TIM1_CCMR1 register. This configures the channel in input mode and the TIM1_CCR1 register becomes read-only.
2. Program the required input filter duration for the signal to be connected to the timer.
This is done for each TI i input using the IC i F bits in the TIM1_CCMR i registers. For example, if the input signal is unstable for up to five t
SYSCLK
cycles when it toggles, the filter duration must be performed for longer than five clock cycles. The filter bits allow a duration of eight cycles to be selected by writing them to 0011 in the TIMx_CCMR1 register. With this filter setting, a transition on TI1 is valid only when eight consecutive samples with the new level have been detected (sampled at f
SYSCLK
frequency).
3. Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0 in the TIM1_CCER1 register (rising edge in this case).
4. Program the input prescaler. In this example, the capture needs to be performed at each valid transition, so the prescaler is disabled (write the IC1PS bits to 00 in the
TIM1_CCMR1 register).
5. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIM1_CCER1 register.
6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIM1_IER register and/or DMA request by setting the CC1IE bit in the TIM1_DER register.
When an input capture occurs:
• The TIM1_CCR1 register gets the value of the counter on the active transition
• The input capture flag (CC1IF) is set. The overcapture flag (CC1OF) is also set if at least two consecutive captures occur while the flag remains uncleared.
• An interrupt is generated depending on the CC1IE bit
• A DMA request is generated depending on the CC1DE bit
To handle the overcapture event (CC1OF flag), it is recommended to read the data before the overcapture flag. This avoids missing an overcapture which could occur after reading the flag and before reading the data.
IC interrupts and/or DMA requests can be generated by software by setting the corresponding CCiG bits in the TIM1_EGR register.
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RM0031 16-bit advanced control timer (TIM1)
PWM input signal measurement
This mode is a particular case of input capture mode (see Figure 101
). The procedure is the same except:
• Two IC i signals are mapped on the same TI i input
• These two IC i signals are active on edges with opposite polarity
• One of the two TI i FP signals is selected as trigger input and the clock/trigger controller is configured in trigger reset mode.
Figure 101. PWM input signal measurement
Procedure
Depending on the f
SYSCLK
frequency and prescaler value, the period (in the TIM1_CCR1 register) can be measured and the duty cycle (in the TIM1_CCR2 register) of the PWM can be applied on TI1 using the following procedure:
1.
Select the active input capture or trigger input for TIM1_CCR1 by writing the CC1S bits to 01 in the TIM1_CCMR1 register (TI1FP1 selected).
2. Select the active polarity for TI1FP1 (used for both capture and counter clear in
TIMx_CCR1) by writing the CC1P bit to 0 (TI1FP1 active on rising edge).
3. Select the active input for TIM1_CCR2 by writing the CC2S bits to 10 in the
TIM1_CCMR2 register (TI1FP2 selected).
4. Select the active polarity for TI1FP2 (used for capture in TIM1_CCR2) by writing the
CC2P bit to 1 (TI1FP2 active on falling edge).
5. Select the valid trigger input by writing the TS bits to 101 in the TIM1_SMCR register
(TI1FP1 selected).
6. Configure the clock/trigger controller in reset mode by writing the SMS bits to 100 in the
TIM1_SMCR register.
7. Enable the captures by writing the CC1E and CC2E bits to 1 in the TIM1_CCER1 register.
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16-bit advanced control timer (TIM1)
Figure 102. PWM input signal measurement example
RM0031
The output stage generates an intermediate waveform called OC i REF (active high) which is then used for reference. Break functions and polarity act at the end of the chain.
Figure 103. Channel output stage block diagram
Deadtime generation
DTG registers
TIM1_CH1
OC1REF
DTG output control
OC1
OC1N
TIM1_NCH1
TIM1_CH2 from capture/compare channels
OC2REF
DTG output control
OC2
OC2N
TIM1_NCH2
TIM1_CH3
OC3REF
DTG output control
OC3
OC3N
TIM1_NCH3
Break from COMP2
BI
TIM1_BKIN Polarity Selection Enable
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 104. Detailed output stage of channel with complementary output (channel 1)
OCREFCLR from COMP2
ETR
internal OCREFCLR
0 TIM1_CH1
OCCS
TIM1_SMCR1
Counter > CCR1
Output mode
Counter = CCR1 controller
OC1REF Deadtime generator
OC1_DT
OC1N_DT
‘0’ x0
01
11
1
CC1P
TIM1_CCER1
Output
Enable
Circuit
‘0’
11
10
0x
0
1
Output enable circuit
TIM1_NCH1
OC1M[2:0]
TIM1_CCMR1
DTG[7:0]
TIM1_DTR
CC1NE CC1E
TIM1_CCER1
CC1NE CC1E TIM1_CCER1
CC1NP
TIM1_CCER1
MOE OSSI OSSR TIM1_BKR
OIS1N OIS1 TIM1_OISR
19.5.5 Forced output mode
In output mode (CC i S bits = 00 in the TIM1_CCMR i registers), each output compare signal can be forced to high or low level directly by software, independently of any comparison between the output compare register and the counter.
To force an output compare signal to its active level, write 101 in the OC i M bits in the corresponding TIM1_CCMR i registers. OC i REF is forced high (OC i REF is always active high) and the OC i output is forced high or low depending on the CC i P polarity bits.
For example, if CC i P = 0 (OC i active high) => OC i is forced high.
The OC i REF signal can be forced low by writing the OC i M bits to 100 in the TIMx_CCMRx registers.
Nevertheless, the comparison between the TIM1_CCR i shadow registers and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.
19.5.6 Output compare mode
This function is used to control an output waveform or indicate when a period of time has elapsed.
When a match is found between the capture/compare register and the counter:
• Depending on the output compare mode, the corresponding OC i output pin:
– Keeps its level (OC i M = 000),
– Is set active (OC i M = 001),
– Is set inactive (OC i M = 010)
– Toggles (OC i M = 011)
• A flag is set in the interrupt status register (CC i IF bits in the TIM1_SR1 register).
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16-bit advanced control timer (TIM1) RM0031
• An interrupt is generated if the corresponding interrupt mask is set (CC i IE bits in the
TIM1_IER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIM1_DER register)
The output compare mode is defined by the OC i M bits in the TIM1_CCMR i registers. The active or inactive level polarity is defined by the CC i P bits in the TIM1_CCER i registers.
The TIM1_CCR i registers can be programmed with or without preload registers using the
OC i PE bits in the TIM1_CCMR i registers.
In output compare mode, the UEV has no effect on the OC i REF and OC i output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse.
Procedure
1.
Select the counter clock (internal, external, or prescaler).
2. Write the desired data in the TIM1_ARR and TIM1_CCR i registers.
3. Set the CC i IE bits if an interrupt request is to be generated.
4. Set the CC i DE bit if a DMA request is to be generated.
5. Select the output mode as follows:
– Write OC i M = 011 to toggle the OC i output pin when CNT matches CCR i
– Write OC i PE = 0 to disable the preload register
– Write CC i P = 0 to select active high polarity
– Write CC i E = 1 to enable the output
6. Enable the counter by setting the CEN bit in the TIMx_CR1 register
The TIM1_CCR i registers can be updated at any time by software to control the output waveform, provided that the preload registers are not enabled (OC i PE = 0). Otherwise, the
TIMx_CCR i
shadow registers are updated only at the next UEV (see example in Figure 105 .
Figure 105. Output compare mode, toggle on OC1
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIM1_ARR register and a duty cycle determined by the value of the
TIM1_CCR i registers.
The PWM mode can be selected independently on each channel (one PWM per OC i output) by writing 110 (PWM mode 1) or 111 (PWM mode 2) in the OC i M bits in the TIM1_CCMR i registers. The corresponding preload register must be enabled by setting the OC i PE bits in the TIM1_CCMR i registers. The auto-reload preload register (in up-counting or centeraligned modes) may be optionally enabled by setting the ARPE bit in the TIM1_CR1 register.
As the preload registers are transferred to the shadow registers only when an UEV occurs, all registers have to be initialized by setting the UG bit in the TIM1_EGR register before starting the counter.
OC i polarity is software programmable using the CC i P bits in the TIM1_CCER i registers. It can be programmed as active high or active low. The OC i output is enabled by a combination of CC i E, MOE, OIS i , OSSR and OSSI bits (TIM1_CCER i and TIM1_BKR registers). Refer to the TIM1_CCER i register descriptions for more details.
In PWM mode (1 or 2), TIM1_CNT and TIM1_CCR i are always compared to determine whether TIM1_CCR i ≤ of the counter).
TIM1_CNT or TIM1_CNT ≤ TIM1_CCR i (depending on the direction
The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIM1_CR1 register.
PWM edge-aligned mode
Up-counting configuration
Up-counting is active when the DIR bit in the TIM1_CR1 register is low.
Example
This example uses PWM mode 1. The reference PWM signal, OC i REF, is high as long as
TIM1_CNT < TIM1_CCR i . Otherwise, it becomes low. If the compare value in TIM1_CCR i is greater than the auto-reload value (in TIM1_ARR) then OC i REF is held at 1. If the compare value is 0, OC i
shows some edge-aligned PWM waveforms in an example where TIM1_ARR = 8.
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16-bit advanced control timer (TIM1) RM0031
Figure 106. Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8)
Down-counting configuration
Down-counting is active when the DIR bit in the TIM1_CR1 register is high. Refer to
In PWM mode 1, the reference signal OC i REF is low as long as TIM1_CNT> TIM1_CCR i.
Otherwise, it becomes high. If the compare value in the TIM1_CCR i registers is greater than the auto-reload value in the TIM1_ARR register, OC i REF is held at 1. Zero percent PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in the TIM1_CR1 register are different from 00 (all the remaining configurations have the same effect on the OC i REF/OC i signals).
The compare flag is set when the counter counts up, down, or up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIM1_CR1 register is updated by hardware and is read-only in this mode (refer to
Center-aligned mode (up/down counting) on page 300
).
Figure 107 shows some center-aligned PWM waveforms in an example where:
• TIM1_ARR = 8,
• PWM mode is PWM mode 1
•
The flag is set (arrow symbol in Figure 107
) in three different cases:
– When the counter counts down (CMS = 01)
– When the counter counts up (CMS = 10)
– When the counter counts up and down (CMS = 11)
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 107. Center-aligned PWM waveforms (ARR = 8)
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16-bit advanced control timer (TIM1) RM0031
One-pulse mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Starting the counter can be controlled through the clock/trigger controller. Generating the waveform can be done in output compare mode or PWM mode. Select one-pulse mode by setting the OPM bit in the TIM1_CR1 register. This makes the counter stop automatically at the next UEV.
A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:
• In up-counting: CNT< CCR i ≤ ARR (in particular, 0 < CCR i ),
• In down-counting: CNT> CCR i
Figure 108. Example of one-pulse mode
Example
This example shows how to generate a positive pulse on OC1 with a length of t
PULSE after a delay of t
DELAY
as soon as a positive edge is detected on the TI2 input pin.
and
Follow the procedure below to use IC2 as trigger 1:
• Map IC2 on TI2 by writing CC2S = 01 in the TIM1_CCMR2 register
• IC2 must detect a rising edge, so write CC2P = 0 in the TIM1_CCER1 register
• Configure IC2 as trigger for the clock/trigger controller (TRGI) by writing TS = 110 in the
TIM1_SMCR register.
• IC2 is used to start the counter by writing SMS to 110 in the TIM1_SMCR register
(trigger mode).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler) as follows:
• The t
DELAY is defined by the value written in the TIM1_CCR1 register
• The t
PULSE
is defined by the difference between the auto-reload value and the compare value (TIM1_ARR - TIM1_CCR1).
• To build a waveform with a transition from 0 to 1 when a compare match occurs and a transition from 1 to 0 when the counter reaches the auto-reload value, enable PWM mode 2 by writing OC i M = 111 in the TIM1_CCMR1 register. Alternatively, enable the preload registers by writing OC1PE = 1 in the TIM1_CCMR1 register and ARPE = 0 in the TIM1_CR1 register (optional). In this case, write the compare value in the
TIM1_CCR1 register and write the auto-reload value in the TIM1_ARR register. Then, generate an update by setting the UG bit and wait for an external trigger event on TI2.
CC1P is written to 0 in this example.
In the example outlined above, the DIR and CMS bits in the TIM1_CR1 register should be low.
As only one pulse is required, write 1 in the OPM bit in the TIM1_CR1 register to stop the counter at the next UEV (when the counter rolls over from the auto-reload value back to 0).
Particular case: OCi fast enable
In one-pulse mode, the edge detection on the TI i input sets the CEN bit which enables the counter. Then, a comparison between the counter and the compare value makes the output toggle. However, several clock cycles are needed for these operations and this affects the the minimum delay (t
DELAY
min) that can be obtained.
To output a waveform with the minimum delay, set the OC i FE bits in the TIM1_CCMR i registers. OC i REF (and OC i ) are forced in response to the stimulus, without taking the comparison into account. The new level of OC i REF (and OC i ) is the same as if a compare match had occured. The OC i FE bits acts only if the channel is configured in PWM1 or
PWM2 mode.
Complementary outputs and deadtime insertion
TIM1 can output two complementary signals per channel. It also manages the switching-off and switching-on instants of the outputs (see
Figure 67: TIM1 general block diagram on page 293
).
This time is generally known as deadtime. Deadtimes must be adjusted depending on the characteristics of the devices connected to the outputs (example, intrinsic delays of levelshifters, delays due to power switches).
The polarity of the outputs can be selected (main output OC i or complementary OC i N) independently for each output. This is done by writing to the CC i P and CC i NP bits in the
TIM1_CCER i registers.
The complementary signals OC i and OC i N are activated by a combination of several control bits: The CC i E and CC i NE bits in the TIM1_CCER i register and, if the break feature is implemented, the MOE, OIS i , OIS i N, OSSI, and OSSR bits in the TIM1_BKR register.
for more details. In particular, the deadtime is activated when switching to the IDLE state (when MOE falls to 0).
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16-bit advanced control timer (TIM1) RM0031
Deadtime insertion is enabled by setting the CC i E and CC i NE bits, and the MOE bit if the break circuit is present. Each channel embeds an 8-bit deadtime generator. It generates two outputs: OC i and OC i N from a reference waveform, OC i REF. If OC i and OC i N are active high:
• The OC i output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge.
• The OC i N output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OC i or OC i N), the corresponding pulse is not generated.
Figure 109 , Figure 110 , and Figure 111 show the relationships between the output signals of
the deadtime generator and the reference signal OC i REF (where CC i P = 0, CC i NP = 0,
MOE = 1, CC i E = 1, and CC i NE = 1 in these examples)
Figure 109. Complementary output with deadtime insertion
Figure 110. Deadtime waveforms with a delay greater than the negative pulse
Figure 111. Deadtime waveforms with a delay greater than the positive pulse
The deadtime delay is the same for each of the channels and is programmable with the
DTG bits in the TIM1_DTR register. Refer to Section 19.8.32: Deadtime register
(TIM1_DTR) on page 374 for delay calculation.
RM0031 Rev 15
RM0031
Note:
16-bit advanced control timer (TIM1)
Re-directing OC
i
REF to OC
i
or OC
i
N
In output mode (forced, output compare, or PWM), OC i REF can be re-directed to the OC i or
OC i N outputs by configuring the CC i E and CC i NE bits in the corresponding TIM1_CCER i registers. This means bypassing the deadtime generator which allows a specific waveform
(such as PWM or static active level) to be sent on one output while the complementary output remains at its inactive level. Alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with deadtime.
When only OCiN is enabled (CCiE = 0, CCiNE = 1), it is not complemented and becomes active as soon as OCiREF is high. For example, if CCiNP = 0 then OCiN = OCiREF. On the other hand, when both OCi and OCiN are enabled (CCiE = CCiNE = 1), OCi becomes active when OCiREF is high whereas OCiN is complemented and becomes active when OCiREF is low.
Six-step PWM generation for motor control
When complementary outputs are implemented on a channel, preload bits are available on the OC i M, CC i E and CC i NE bits. The preload bits are transferred to the active bits at the commutation event (COM). This allows the configuration for the next step to be programmed in advance and for configuration of all the channels to be changed at the same time. The COM event can be generated by software by setting the COMG bit in the
TIM1_EGR register or by hardware trigger (on the rising edge of TRGI).
A flag is set when the COM event occurs (COMIF bit in the TIM1_SR register) which can generate an interrupt (if the COMIE bit is set in the TIM1_IER register) or a DMA request (if the COMDE bit is set in the TIM1_DER register).
Figure 112 shows the behavior of the OC
i and OC i N outputs when a COM event occurs, for three different examples of programmed configurations.
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16-bit advanced control timer (TIM1)
Figure 112. Six-step generation, COM example (OSSR = 1)
RM0031
19.5.8 Using the break function
The break function is often used in motor control. When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE,
OSSR and OSSI bits in the TIM1_BKR register).
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break function is enabled by setting the BKE bit in the TIM1_BKR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIM1_BKR register). It results in some delays between the asynchronous and the synchronous signals. For example, if MOE is written to 1 after it has been low, a delay (dummy instruction) must be inserted before it can be read correctly.
RM0031 Rev 15
RM0031
Note:
Note:
16-bit advanced control timer (TIM1)
When a break occurs (selected level on the break input):
• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state, or reset state (selected by the OSSI bit). This happens even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OIS i bits in the
TIM1_OISR register as soon as MOE = 0. If OSSI = 0, the timer releases the enable output otherwise the enable output remains high.
• When complementary outputs are implemented:
– The outputs are first put in inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.
– If the timer clock is still present, the deadtime generator is reactivated to drive the outputs with the level programmed in the OIS i and OIS i N bits after a deadtime.
Even in this case, OC i and OC i N cannot be driven to their active level together.
Note that because of the resynchronization on MOE, the deadtime duration is a bit longer than usual (around two 2 ck_tim clock cycles).
• The break status flag (BIF bit in the TIM1_SR1 register) is set. An interrupt can be generated if the BIE bit in the TIM1_IER register is set.
• If the AOE bit in the TIM1_BKR register is set, the MOE bit is automatically set again at the next UEV. This can be used to perform a regulation. Otherwise, MOE remains low until it is written to 1 again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors, or any security components.
The break inputs act on signal level. Thus, the MOE bit cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.
The break can be generated by the break input (BKIN) which has a programmable polarity and can be enabled or disabled by setting or resetting the BKE bit in the TIM1_BKR register.
In addition to the break inputs and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows the configuration of several parameters (OC i polarities and state when disabled, OC i M configurations, break enable, and polarity) to be frozen. Three levels of protection can be selected using the
LOCK bits in the TIM1_BKR register. The LOCK bits can be written only once after an MCU reset.
Figure 113 shows an example of the behavior of the outputs in response to a break.
The break can also be generated by Comparator 2 through the OUTSEL[1:0] bits in the
COMP_CSR3 register. Refer to the Comparator section.
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
Figure 113. Behavior of outputs in response to a break (channel without complementary output)
Figure 114 shows an example of behavior of the complementary outputs (TIM1 only) in
response to a break.
Figure 114. Behavior of outputs in response to a break (TIM1 complementary outputs)
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
the
i
REF signal on an external event
The OC i REF signal of a given channel can be cleared when a high level is detected on
OCREFCLR internal signal (if OC i CE =1 in the TIM1_CCMR i registers, one enable bit per channel). The OC i REF signal remains low until the next UEV occurs. This function can be used in output compare mode and PWM mode only. It does not work in forced mode.
The source of the OCREFCLR internal signal can be selected between the OCREFCLR input and the ETRF (ETR after the filter) by configuring the OCCS bit in the TIM1_SMCR register
The OC i REF signal can be connected to the output of a comparator and be used for current handling by configuring the external trigger as follows:
1.
Switch off the external trigger prescaler by setting bits ETPS[1:0] in the TIM1_ETR register to 00.
2. Disable external clock mode 2 by setting the ECE bit in the TIM1_ETR register to 0
3. Configure the external trigger polarity (ETP) and the external trigger filter (ETF) as desired.
Refer to Figure 83: External trigger input block diagram .
Figure 115 shows the behavior of the OC
i REF signal when the ETRF input becomes high, for both values of the enable bits OC i CE. In this example, the timer is programmed in PWM mode.
Figure 115. OCREFCLR activation
(CCRx) counter (CNT)
OCREFCLR internal
OC i REF
(OC i CE=0)
OC i REF
(OC i CE=1)
OCREFCLR internal becomes high
OCREFCLR internal still high
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
Encoder interface mode is typically used for motor control. It can be selected by writing:
• SMS = 001 in the TIM1_SMCR register if the counter is counting on TI2 edges only
• SMS = 010 if the counter is counting on TI1 edges only
• SMS = 011 if the counter is counting on both TI1 and TI2 edges
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the
TIM1_CCER1 register. When needed, the input filter can also be programmed.
The two inputs TI1 and TI2 are used to interface an incremental encoder (see
the counter is enabled (when the CEN bit in the TIM1_CR1 register is written to 1), it is clocked by each valid transition on TI1FP1 or TI2FP2 (see
generate count pulses and a direction signal. Depending on the sequence, the counter counts up or down, and the DIR bit in the TIM1_CR1 register is modified accordingly by hardware. The DIR bit is calculated at each transition based on inputs from either TI1 or TI2. without this being dependent on whether the counter is counting pulses on TI1, TI2 or both.
Encoder interface mode acts as an external clock with direction selection. The counter counts continuously between 0 and the auto-reload value in the TIM1_ARR register (0 to
ARR or ARR down to 0 depending on the direction). TIM1_ARR must be configured before starting. The capture, compare, prescaler, and trigger output features continue to work as normal in this mode. Encoder mode and external clock mode 2 are not compatible and must not be selected together.
In encoder interface mode, the counter is modified automatically depending on the speed and the direction of the incremental encoder. The content of the counter therefore always represents the encoder's position. The count direction corresponds to the rotation direction of the connected sensor.
summarizes the possible combinations of counting directions and encoder signals, assuming that TI1 and TI2 do not switch at the same time.
Active edge
Counting on
TI1 only
Counting on
TI2 only
Counting on both TI1 and
TI2
Table 67. Counting direction versus encoder signals
Level on opposite signal
(TI1FP1 for TI2,
TI2FP2 for TI1)
TI1FP1 signal
Rising Falling
TI2FP2 signal
Rising Falling
High
Low
High
Low
High
Down
Up
No count
No count
Down
Up
Down
No count
No count
Up
No count
No count
Up
Down
Up
No count
No count
Down
Up
Down
Low Up Down Down Up
An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Figure 116 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near one of the switching points. In the example below, configuration is as follows:
• CC1S = 01 (TIM1_CCMR1 register, IC1 mapped on TI1)
• CC2S = 01 (TIM1_CCMR2 register, IC2 mapped on TI2)
• CC1P = 0 (TIM1_CCER1 register, IC1 non-inverted, IC1=TI1)
• CC2P = 0 (TIM1_CCER2 register, IC2 non-inverted, IC2=TI2)
• SMS = 011 (TIM1_SMCR register, both inputs are active on both rising and falling edges).
• CEN = 1 (TIM1_CR1 register, counter is enabled)
Figure 116. Example of counter operation in encoder interface mode
except that CC1P =1).
Figure 117. Example of encoder interface mode with IC1 polarity inverted
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
When the timer is configured in encoder interface mode, it provides information on the current position of the sensors. Dynamic information, such as speed, acceleration, and slowdown, can be obtained by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder, which indicates the mechanical zero, can be used for this purpose. Depending on the time between two events, the counter can also be read at regular intervals. This can be done by latching the counter value into a third input capture register, if one is available. In this case, the capture signal must be periodic and can be generated by another timer.
If the TI1S bit is set in the TIM1_CR2 register, the input filter of channel 1 can be connected to the output of an XOR gate, combining the three TIM1_CH1, TIM1_CH2 and TIM1_CH3 input pins.
The XOR output can be used with all timer input functions such as trigger or input capture.
An example of this feature used to interface Hall sensors is given in the following section.
19.5.12 Interfacing with Hall sensors
This is done by using the advanced-control timer (TIM1) to generate PWM signals to drive the motor and another TIMx timer (TIM2, TIM3 or TIM5) referred to as “interfacing timer” in
Figure 118 . The “interfacing timer” captures the 3 timer input pins connected through an
XOR gate to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED.
Consequently, each time one of the 3 inputs toggles, the counter restarts counting from 0.
This creates a time base triggered by any change on the Hall inputs.
On the “interfacing timer”, the capture/compare channel 1 is configured in capture mode and the capture signal is TRC (
See Figure 100: Input stage of TIM 1 channel 1 on page 321
).
The captured value (which corresponds to the time elapsed between 2 changes on the inputs) gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so as to generate a positive pulse after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced control timer (TIM1) through the TRGO output.
Example: you want to change the PWM configuration of your TIM1 advanced-control timer after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. Use the following procedure:
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
• Configure the 3 timer inputs XORed to the TI1 input channel by writing the TI1S bit to 1 in the TIMx_CR2 register,
• Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change). Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors,
• Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘11’. You can also program the digital filter if needed,
• Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to
‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR2 register,
• Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’.
In the TIM1 advanced-control timer, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (COMS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step.
Figure 118. Example of Hall sensor interface
TIH1
TIH2
TIH3 counter (CNT)
(CCR2)
CCR1
TRGO=OC2REF
C7A3 C7A8 C794 C7A5 C7AB C796
COM
OC1
OC1N
OC2
OC2N
OC3
OC3N
Write CCxE, CCxNE and OCxM for next step
RM0031 Rev 15 ai17096
417
16-bit advanced control timer (TIM1) RM0031
TIM1 has eight interrupt request sources, mapped on 2 interrupt vectors:
• Break interrupt
• Trigger interrupt
• Commutation interrupt
• Capture/compare 4 interrupt
• Capture/compare 3 interrupt
• Capture/compare 2 interrupt
• Capture/compare 1 interrupt
• Update interrupt (example: overflow, underflow, and counter initialization)
To use the interrupt features for each interrupt channel used, set the desired interrupt enable bits (BIE, TIE, COMIE, CC i IE, and UIE) in the TIM1_IER register to enable interrupt requests.
The different interrupt sources can also be generated by software using the corresponding bits in the TIM1_EGR register.
19.6.1 TIM1 wait-for-event capability
In wait-for-event mode (WFE), TIM1 capture/compare, break, trigger and update interrupts can be used to wake up the device. The interrupt event must have been previously configured through bits TIM1_EV0 and TIM1_EV1 in the WFE_CR1 register (see
Section 9.5: WFE registers ).
TIM1 has six DMA request sources:
• Commutation event
• Capture/compare 4 event
• Capture/compare 3 event
• Capture/compare 2 event
• Capture/compare 1 event
• Update event (example: overflow, underflow, counter initialization)
To use the DMA requests set the corresponding “DMA Enable” bit: COMDE, CC i DE, UDE in the TIM1_DER register.
The different DMA requests can be also generated by software using the corresponding bits in the TIM1_EGR register.
19.7.1 DMA single mode
The DMA controller can be configured to transfer a single byte (or two bytes) to or from a single TIM1 register (or two TIM1 registers) by programming the register address in the
DMA_CxPARH and DMA_CxPARL registers.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.7.2 DMA burst mode
DMA can work in burst mode with TIM1. In this mode, the DMA can transfer a block of data from/to a block of TIM1 registers. The maximum DMA burst length (defined in the DBL[4:0] bits in the TIM1_DCR2 register) is 32 bytes.
To configure this mode:
1.
Write the address of the TIM1_DMAR register in the DMA_CxPARL and
DMA_CxPARH registers.
2. In the TIM1_DCR register, write the address of the first register to be transferred and the number of registers in the burst.
for a simplified example of how to configure DMA burst mode.
Figure 119. DMA burst modes example
Base address
Timer registers
DMA controller registers
Number of registers to be transferred in burst
Peripheral/memory
DMA transfer
DMA_CxNDTR
DMA_CxPARL
DMA_CxPARH
DMA_CxM0ARL
DMA_CxM0ARH
DMA Number of Data to Transfer Register
DMA Peripheral
Address Register
DMA Memory
Address Register
R/W
TIM1_DCR
TIM1_DMAR
RAM
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
19.8.1 Control register 1 (TIM1_CR1)
Address offset: 0x00
Reset value: 0x00
7
ARPE rw
6 rw
CMS[1:0]
5 rw
4
DIR rw
3
OPM rw
2
URS rw
1
UDIS rw
0
CEN rw
Bit 7 ARPE : Auto-reload preload enable
0: TIM1_ARR register is not buffered through a preload register. It can be written directly
1: TIM1_ARR register is buffered through a preload register
Bits 6:5 CMS[1:0] : Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in TIM1_CCMR i registers) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in CCMR i registers) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in TIM1_CCMR i registers) are set both when the counter is counting up and down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode while the counter is enabled (CEN = 1)
Encoder mode (SMS = 001, 010 or 011 in TIM1_SMCR register) must be disabled in centeraligned mode.
Bit 4 DIR : Direction
0: Counter used as up-counter
1: Counter used as down-counter
Note: This bit is read-only when the timer is configured in center-aligned mode or encoder mode.
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit)
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 2 URS : Update request source
0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one of the following events occurs:
– Registers are updated (counter overflow/underflow)
– UG bit is set by software
– Update event is generated through the clock/trigger controller
1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when registers are updated (counter overflow/underflow).
Bit 1 UDIS : Update disable.
0: A UEV is generated as soon as a counter overflow occurs, a software update is generated, or a hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded with their preload values.
1: A UEV is not generated and shadow registers keep their value (ARR, PSC, CCR i ). The counter and the prescaler are re-initialized if the UG bit is set or if a hardware reset is received from the clock/trigger mode controller.
Bit 0 CEN : Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, trigger gated mode, and encoder mode can work only if the CEN bit has been previously set by software. However, trigger mode can set the CEN bit automatically by hardware.
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
19.8.2 Control register 2 (TIM1_CR2)
Address offset: 0x01
Reset value: 0x00
7
TI1S rw
6 rw
5
MMS[2:0] rw
4 rw
3
CCDS rw
2
COMS rw
1
Reserved
0
CCPC rw
Bit 7 TI1S : TI1 (digital filter input) selection
0: TI1 is connected to CH1 input pin
1: TI1 is connected to the 3 inputs CH1, CH2 and CH3 (XORed)
Bits 6:4 MMS[2:0] : Master mode selection
These bits select the information to be sent in master mode to the 2 other timers for synchronization
(TRGO). The combination is as follows:
000: Reset - The UG bit from the TIM1_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (clock/trigger mode controller configured in reset mode), the signal on
TRGO is delayed compared to the actual reset.
001: Enable - The counter enable signal is used as trigger output (TRGO). It is used to start several timers to control a window in which a slave timer is enabled. The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in trigger gated mode. When the counter enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIM1_SMCR register).
010: Update - The update event is selected as trigger output (TRGO)
011: Compare pulse (MATCH1) - The trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurs (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Bit 3 CCDS : Capture/compare DMA selection
0: TIM1_CC i DMA request sent when a CC i (capture/compare) event occurs
1: TIM1_CC i DMA request sent when an update event occurs
Bit 2 COMS : Capture/compare control update selection
0: When capture/compare control bits are preloaded (CCPC = 1), they are updated by setting the
COMG bit.
1: When capture/compare control bits are preloaded (CCPC = 1), they are updated by setting the
COMG bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels with complementary outputs.
Bit 1 Reserved, forced by hardware to 0
Bit 0 CCPC : Capture/compare preloaded control
0: The CC i E, CC i NE, CC i P, and CC i NP bits in the TIM1_CCER i registers and the OC i M bit in the
TIM1_CCMR i registers are not preloaded
1: CC i E, CC i NE, CC i P, CC i NP and OC i M bits are preloaded, after having been written, they are updated only when COMG bit is set in the TIM1_EGR register.
Note: This bit acts only on channels with complementary outputs.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x02
Reset value: 0x00
7
MSM rw
6 rw
5
TS[2:0] rw
4 rw
3
OCCS rw
2 rw
1
SMS[2:0] rw
0 rw
Bit 7 MSM : Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between TIM1 and another timer (through TRGO).
Bits 6:4 TS[2:0] : Trigger selection
This bit field selects the trigger input (TRGI) to be used to synchronize the counter.
000: Internal trigger ITR0 connected to TIM4 TRGO
001: Internal trigger ITR1 connected to TIM5 TRGO
010: Internal trigger ITR2 connected to TIM3 TRGO
011: Internal trigger ITR3 connected to TIM2 TRGO
100: TI1 edge detector (TI1F_ED)
101: Filtered timer input 1 (TI1FP1)
110: Filtered timer input 2 (TI2FP2)
111: External trigger input (ETRF)
Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid incorrect edge detections at the transition.
Bit 3 OCCS: OCREFCLR selection
This bit is set and cleared by software to select the source of the internal OCREFCLR signal.
0: OCREFCLR_Internal is connected to the OCREFCLR input
1: OCREFCLR_Internal is connected to ETRF external trigger
Bits 2:0 SMS[2:0] : Clock/trigger/slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see input control register and control register description).
000: Clock/trigger controller disabled - If CEN = 1, the prescaler is clocked directly by the internal clock.
001: Encoder mode 1 - Counter counts up or down on TI2FP2 edge depending on TI1FP1 level
010: Encoder mode 2 - Counter counts up or down on TI1FP1 edge depending on TI2FP2 level
011: Encoder mode 3 - Counter counts up or down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
100: Reset mode - Rising edge of the selected trigger signal (TRGI) re-initializes the counter and generates an update of the registers.
101: Trigger gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
110: Trigger standard mode - The counter starts at a rising edge of the trigger TRGI (but, it is not reset). Only the start of the counter is controlled.
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
Note: Trigger gated mode must not be used if TI1F_ED is selected as the trigger input (TS = 100).
TI1F_ED outputs 1 pulse for each transition on TI1F, whereas trigger gated mode checks the level of the trigger signal.
RM0031 Rev 15
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16-bit advanced control timer (TIM1)
Address offset: 0x03
Reset value: 0x00
7
ETP rw
6
ECE rw
5
ETPS[1:0]
4 3 2 rw rw rw rw
Bit 7 ETP : External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
ETF[3:0]
1 rw
RM0031
0 rw
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 6 ECE : External clock enable
This bit enables external clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS = 111 and TS = 111 in the TIM1_SMCR register).
It is possible to simultaneously use external clock mode 2 with the following modes: Trigger standard mode, trigger reset mode, and trigger gated mode. Nevertheless, TRGI must not be connected to ETRF in these cases (TS bits must not be 111 in the TIM1_SMCR register).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
Bits 5:4 ETPS : External trigger prescaler
The ETRP frequency must be, at most,1/4 of f
SYSCLK
frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler off
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 3:0 ETF : External trigger filter.
This bitfield defines the frequency used to sample the ETRP signal and the length of the digital filter applied to it. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
SYSCLK
0001: f
SAMPLING
0010: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
0011: f
SAMPLING
=f
SYSCLK
, N = 2
, N = 4
, N = 8
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
=f
SYSCLK
0111: f
SAMPLING
=f
SYSCLK
/2, N = 6
/2, N = 8
/4, N = 6
/4, N = 8
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
=f
SYSCLK
1011: f
SAMPLING
=f
SYSCLK
/8, N = 6
/8, N = 8
1100: f
SAMPLING
=f
SYSCLK
/16, N = 5
/16, N = 6
/16, N = 8
1101: f
SAMPLING
1110: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
1111: f
SAMPLING
=f
SYSCLK
/32, N = 5
/32, N = 6
/32, N = 8
RM0031 Rev 15
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16-bit advanced control timer (TIM1) RM0031
Address offset: 0x04
Reset value: 0x00
7
Reserved
6 5
COMDE rw
4
CC4DE rw
3
CC3DE rw
2
CC2DE rw
1
CC1DE rw
0
UDE rw
Bits 7:6 Reserved, must be kept cleared
Bit 5 COMDE : Commutation DMA request enable
(1)
0: Commutation DMA request disabled
1: Commutation DMA request enabled
Bit 4 CC4DE
: Capture/compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
Bit 3 CC3DE
: Capture/compare 3 DMA request enable
0: CC3 DMA request disabled
1: CC3 DMA request enabled
Bit 2 CC2DE
: Capture/compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 1 CC1DE
: Capture/compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 0 UDE
0: Update DMA request disabled
1: Update DMA request enabled
Note: The conditions for generating a DMA request on the update event are the same as for setting the UIF bit (in the TIM1_SR1 register). In particular, the DMA request depends on the URS bit
(in the TIM1_CR1 register).
1.
The DMA request is related to the actual event and not to the status bit (in the TIM1_SR1 register). Thus, no DMA request is sent if the xxDE bit is written to 1 while the corresponding status bit is already set.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x05
Reset value: 0x00
7
BIE rw
6
TIE rw
5
COMIE rw
4
CC4IE rw
Bit 7 BIE : Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE : Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE : Commutation interrupt enable
0: Commutation interrupt disabled
1: Commutation interrupt enabled
Bit 4 CC4IE : Capture/compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
Bit 3 CC3IE : Capture/compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled
Bit 2 CC2IE : Capture/compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE : Capture/compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
3
CC3IE rw
2
CC2IE rw
1
CC1IE rw
0
UIE rw
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
19.8.7 Status register 1 (TIM1_SR1)
Address offset: 0x06
Reset value: 0x00
7
BIF rc_w0
6
TIF rc_w0
5
COMIF rc_w0
4
CC4IF rc_w0
3
CC3IF rc_w0
2
CC2IF rc_w0
1
CC1IF rc_w0
0
UIF rc_w0
Bit 7 BIF : Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0: No break event has occurred
1: An active level has been detected on the break input
Bit 6 TIF : Trigger interrupt flag
This flag is set by hardware on a trigger event (the active edge is detected on a TRGI signal, both edges are detected if trigger gated mode is selected). It is cleared by software.
0: No trigger event has occurred
1: Trigger interrupt pending
Bit 5 COMIF : Commutation interrupt flag
This flag is set by hardware on a COM (when capture/compare control bits - CC i E, CC i NE, OC i M - have been updated). It is cleared by software.
0: No COM has occurred
1: COM interrupt pending
Bit 4 CC4IF : Capture/compare 4 interrupt flag
Refer to CC1IF description
Bit 3 CC3IF : Capture/compare 3 interrupt flag
Refer to CC1IF description
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 2 CC2IF : Capture/compare 2 interrupt flag
Refer to CC1IF description
Bit 1 CC1IF : Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits from TIM1_CR1 register description). It is cleared by software.
0: No match
1: The content of the counter register TIM1_CNT matches the content of the TIM1_CCR1 register
Note: When the contents of TIMx_CCRi are greater than the contents of TIMx_ARR, the CCiIF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow
(in down-counting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the TIM1_CCR1L register.
0: No input capture has occurred
1: The counter value has been captured in the TIM1_CCR1 register (an edge has been detected on
IC1 which matches the selected polarity).
Bit 0 UIF : Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update has occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow if UDIS = 0 in the TIM1_CR1 register
– When CNT is re-initialized by software using the UG bit in TIM1_EGR register, if URS = 0 and UDIS = 0 in the TIM1_CR1 register.
– When CNT is re-initialized by a trigger event (refer to the TIM1_SMCR register description), if URS = 0 and UDIS = 0 in the TIM1_CR1 register.
19.8.8 Status register 2 (TIM1_SR2)
Address offset: 0x07
Reset value: 0x00
7
r
6
Reserved r
5 4
CC4OF rc_w0
Bits 7:5 Reserved, must be kept cleared
Bit 4 CC4OF : Capture/compare 4 overcapture flag
Refer to CC1OF description
Bit 3 CC3OF : Capture/compare 3 overcapture flag
Refer to CC1OF description
3
CC3OF rc_w0
2
CC2OF rc_w0
1
CC1OF rc_w0
0
Reserved r
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Bit 2 CC2OF : Capture/compare 2 overcapture flag
Refer to CC1OF description
Bit 1 CC1OF : Capture/compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0.
0: No overcapture has been detected
1: The counter value has been captured in TIM1_CCR1 register while CC1IF flag was already set
Bit 0 Reserved, must be kept cleared.
Address offset: 0x08
Reset value: 0x00
7
BG w
6
TG w
5
COMG w
4
CC4G w
3
CC3G w
2
CC2G w
1
CC1G w
0
UG w
Bit 7 BG : Break generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: A break event is generated. The MOE bit is cleared and the BIF flag is set. An interrupt is generated if enabled by the BIE bit.
Bit 6 TG : Trigger generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIM1_SR1 register. An interrupt is generated if enabled by the TIE bit.
Bit 5 COMG : Capture/compare control update generation
This bit can be set by software and is automatically cleared by hardware.
0: No action
1: When the CCPC bit in the TIM1_CR2 register is set, it allows the CC i E, CC i NE CC i P, CC i NP, and
OC i M bits to be updated.
Note: This bit acts only on channels that have a complementary output.
Bit 4 CC4G : Capture/compare 4 generation
Refer to CC1G description.
Bit 3 CC3G : Capture/compare 3 generation
Refer to CC1G description.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 2 CC2G : Capture/compare 2 generation
Refer to CC1G description.
Bit 1 CC1G : Capture/compare 1 generation.
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If the CC1 channel is configured in output mode:
The CC1IF flag is set and the corresponding interrupt request is sent if enabled.
If the CC1 channel is configured in input mode:
The current value of the counter is captured in the TIM1_CCR1 register. The CC1IF flag is set, and the corresponding interrupt request is sent if enabled. The CC1OF flag is set if the CC1IF flag is already high.
Bit 0 UG : Update generation
This bit can be set by software and is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. Note that the prescaler counter is also cleared. The counter is cleared if center-aligned mode is selected or if DIR = 0 (upcounting). Otherwise, it takes the auto-reload value (TIM1_ARR) if DIR = 1 (down-counting).
Address offset: 0x09
Reset value: 0x00
This channel can be used in input (capture mode) or in output (compare mode). The direction of the channel is defined by configuring the CC1S bits. All the other bits of this register have a different function in input and output mode. For a given bit, OC ii describes its function when the channel is configured in output, IC ii describes its function when the channel is configured in input. Therefore, be aware that the same bit can have a different meaning for the input and output stage.
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Channel configured in output
7
OC1CE rw
6 rw
5
OC1M[2:0] rw
4 rw
3
OC1PE rw
2
OC1FE rw
1 rw
CC1S[1:0]
0 rw
Bit 7 OC1CE : Output compare 1 clear enable
This bit is used to enable the clearing of the channel 1 output compare signal (OC1REF) by the
OCREFCLR internal signal (see Section 19.5.9 on page 337
).
0: OC1REF is not affected by the OCREFCLR internal signal
1: OC1REF is cleared as soon as a high level is detected on the OCREFCLR internal signal
Bits 6:4 OC1M : Output compare 1 mode
These bits define the behavior of the output reference signal, OC1REF, from which OC1 is derived.
OC1REF is active high whereas OC1 active level depends on the CC1P bit.
000: Frozen - The comparison between the output compare register TIM1_CCR1 and the counter register TIM1_CNT has no effect on the outputs.
001: Set channel 1 to active level on match - OC1REF signal is forced high when the counter register TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
010: Set channel 1 to inactive level on match - OC1REF signal is forced low when the counter register TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
011: Toggle - OC1REF toggles when TIM1_CNT = TIM1_CCR1
100: Force inactive level - OC1REF is forced low
101: Force active level - OC1REF is forced high
110: PWM mode 1 - In up-counting, channel 1 is active as long as TIM1_CNT < TIM1_CCR1, otherwise, the channel is inactive. In down-counting, channel 1 is inactive (OC1REF = 0) as long as
TIM1_CNT > TIM1_CCR1, otherwise, the channel is active (OC1REF = 1).
111: PWM mode 2 - In up-counting, channel 1 is inactive as long as TIM1_CNT < TIM1_CCR1, otherwise, the channel is active. In down-counting, channel 1 is active as long as TIM1_CNT >
TIM1_CCR1, otherwise, the channel is inactive.
Note: These bits can no longer be modified while LOCK level 3 has been programmed (LOCK bits in
TIM1_BKR register) and CC1S = 00 (the channel is configured in output).
In PWM mode 1 or 2, the OCiREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode (refer
to PWM mode on page 327 for more details).
On channels that have a complementary output, this bitfield is preloaded. If the CCPC bit is set in the TIM1_CR2 register, the OCM active bits take the new value from the preload bits only when a COM is generated.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 3 OC1PE : Output compare 1 preload enable
0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1 can be written at anytime. The new value is taken into account immediately.
1: Preload register on TIM1_CCR1 enabled. Read/write operations access the preload register.
TIM1_CCR1 preload value is loaded in the shadow register at each UEV.
Note: These bits can no longer be modified while LOCK level 3 has been programmed (LOCK bits in
TIM1_BKR register) and CC1S = 00 (the channel is configured in output).
For correct operation, preload registers must be enabled when the timer is in PWM mode. This is not mandatory in one-pulse mode (OPM bit set in TIM1_CR1 register).
Bit 2 OC1FE : Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on the counter and CCR1 values, even when the trigger is on.
The minimum delay to activate CC1 output when an edge occurs on the trigger input, is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on the CC1 output. If this happens,
OC is set to the compare level irrespective of the result of the comparison. The delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0] : Capture/compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1FP1
10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM1_SMCR register).
Note: CC1S bits are writable only when the channel is off (CC1E = 0 in TIM1_CCER1).
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
7
Channel configured in input
6 rw
IC1F[3:0]
5 rw
4 rw
3 rw
2
IC1PSC[1:0] rw
1 rw
CC1S[1:0]
0 rw rw
Bits 7:4 IC1F[3:0] : Input capture 1 filter
This bitfield defines f
SAMPLING
, the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
0000: No filter, f
SAMPLING
0001: f
SAMPLING
0010: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
0011: f
SAMPLING
=f
SYSCLK
= f
SYSCLK
, N = 2
, N = 4
, N = 8
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
=f
SYSCLK
0111: f
SAMPLING
=f
SYSCLK
/2, N = 6
/2, N = 8
/4, N = 6
/4, N = 8
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
=f
SYSCLK
1011: f
SAMPLING
=f
SYSCLK
/8, N = 6
/8, N = 8
1100: f
SAMPLING
=f
SYSCLK
/16, N = 5
/16, N = 6
/16, N = 8
1101: f
SAMPLING
1110: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
1111: f
SAMPLING
=f
SYSCLK
/32, N = 5
/32, N = 6
/32, N = 8
Note: Even on channels that have a complementary output, this bit field is not preloaded and does not take into account the content of the CCPC bit (in the TIM1_CR2 register).
Bits 3:2 IC1PSC[1:0] : Input capture 1 prescaler
This bitfield defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E = 0 (TIM1_CCER register).
00: No prescaler, capture is made each time an edge is detected on the capture input
01: Capture is made once every 2 events
10: Capture is made once every 4 events
11: Capture is made once every 8 events
Bits 1:0 CC1S[1:0] : Capture/compare 1 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1FP1
10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM1_SMCR register).
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIM1_CCER1).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x0A
Reset value: 0x00
Channel configured in output
7
OC2CE rw
6 rw
5
OC2M[2:0] rw
4 rw
3
OC2PE rw
2
OC2FE rw
1 rw
CC2S[1:0]
0 rw
Bit 7 OC2CE : Output compare 2 clear enable
Bits 6:4 OC2M(2:0] : Output compare 2 mode
Bit 3 OC2PE : Output compare 2 preload enable
Bit 2 OC2FE : Output compare 2 fast enable
Bits 1:0 CC2S[1:0] : Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2FP2
10: CC2 channel is configured as input, IC2 is mapped on TI1FP2
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM1_SMCR register)
Note: CC2S bits are writable only when the channel is off (CC2E and CC2NE = 0 and updated in
TIM1_CCER1).
Channel configured in input
7 6
IC2F[3:0]
5 4 3 rw
2
IC2PSC[1:0] rw
1
CC2S[1:0]
0 rw rw rw rw rw rw
Bits 7:4 IC2F : Input capture 2 filter
Bits 3:2 IC2PSC(1:0] : Input capture 2 prescaler
Bits 1:0 CC2S[1:0] : Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2FP2
10: CC2 channel is configured as input, IC2 is mapped on TI1FP2
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM1_SMCR register).
Note: CC2S bits are writable only when the channel is off (CC2E and CC2NE = 0 and updated in
TIM1_CCER1).
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Address offset: 0x0B
Reset value: 0x00
Refer to the CCMR1 register description above.
Channel configured in output
7
OC3CE rw
6 rw
5
OC3M[2:0] rw
4 rw
3
OC3PE rw
2
OC3FE rw
1 rw
CC3S[1:0]
0 rw
Bit 7 OC3CE : Output compare 3 clear enable
Bits 6:4 OC3M[2:0] : Output compare 3 mode
Bit 3 OC3PE : Output compare 3 preload enable
Bit 2 OC3FE : Output compare 3 fast enable
Bits 1:0 CC3S[1:0] : Capture/compare 3 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3FP3
10: Reserved
11: CC3 channel is configured as input, IC3 is mapped on TRC. This configuration only works if an internal trigger input is selected through the TS bit in the TIM1_SMCR register
Note: CC3S bits are writable only when the channel is off (CC3E and CC3NE = 0 and updated in
TIM_CCER2).
Channel configured in input
7 6
IC3F[3:0]
5 4 3 rw
2
IC3PSC[1:0] rw
1
CC3S[1:0]
0 rw rw rw rw rw
Bits 7:4 IC3F : Input capture 3 filter
Bits 3:2 IC3PSC[1:0] : Input capture 3 prescaler
Bits 1:0 CC3S[1:0] : Capture/compare 3 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3FP3
10: Reserved
11: CC3 channel is configured as input, IC3 is mapped on TRC. This configuration only works if an internal trigger input is selected through the TS bit in the TIM1_SMCR register.
CC3S bits are writable only when the channel is off (CC3E and CC3NE = 0 and updated in
TIM_CCER2).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0xC
Reset value: 0x00
Refer to the CCMR1 register description above.
Channel configured in output
7
OC4CE rw
6 rw
5
OC4M[2:0] rw
4 rw
3
OC4PE rw
2
Reserved
1 rw
CC4S[1:0]
0 rw
Bit 7 OC4CE : Output compare 4 clear enable
Bits 6:4 OC4M[2:0] : Output compare 4 mode
Bit 3 OC4PE : Output compare 4 preload enable
Bit 2 Reserved
Bits 1:0 CC4S[1:0] : Capture/compare 4 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC4 channel is configured as output
01: Reserved
10: CC4 channel is configured as input, IC4 is mapped on TI3FP4
11: CC4 channel is configured as input, IC4 is mapped on TRC. This configuration only works if an internal trigger input is selected through the TS bit in the TIM1_SMCR register
Note: CC4S bits are writable only when the channel is off (CC4E and CC4NE = 0 and updated in
TIM1_CCER2).
Channel configured in input
7 6
IC4F[3:0]
5 4 3 rw
2
IC4PSC[1:0] rw
1
CC4S[1:0]
0 rw rw rw rw rw rw
Bits 7:4 IC4F : Input capture 4 filter
Bits 3:2 IC4PSC[1:0] : Input capture 4 prescaler
Bits 1:0 CC4S[1:0] : Capture/compare 4 selection
This bitfield defines the direction of the channel (input/output) and the used input.
00: CC4 channel is configured as output.
01: Reserved
10: CC4 channel is configured as input, IC4 is mapped on TI3FP4.
11: CC4 channel is configured as input, IC4 is mapped on TRC. This configuration only works if an internal trigger input is selected through the TS bit in the TIM1_SMCR register
Note: CC4S bits are writable only when the channel is off (CC4E and CC4NE = 0 and updated in
TIM_CCER2).
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Address offset: 0x0D
Reset value: 0x00
7
CC2NP rw
6
CC2NE rw
5
CC2P rw
4
CC2E rw
3
CC1NP rw
2
CC1NE rw
1
CC1P rw
0
CC1E rw
Bit 7 CC2NP : Capture/compare 2 complementary output polarity
Refer to CC1NP description.
Bit 6 CC2NE : Capture/compare 2 complementary output enable
Refer to CC1NE description.
Bit 5 CC2P : Capture/compare 2 output polarity
Refer to CC1P description.
Bit 4 CC2E : Capture/compare 2 output enable
Refer to CC1E description.
Bit 3 CC1NP : Capture/compare 1 complementary output polarity
0: OC1N active high
1: OC1N active low
Note: This bit is no longer writable while LOCK level 2 or 3 have been programmed (LOCK bits in
TIM1_BKR register) and CC1S = 00 (the channel is configured in output).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM1_CR2 register, the CC1NP active bit takes the new value from the preload bit only when a COM is generated.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Bit 2 CC1NE : Capture/compare 1 complementary output enable
0: Off - OC1N is not active. OC1N level is then a function of the MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on the MOE, OSSI,
OSSR, OIS1, OIS1N and CC1E bits.
Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM1_CR2 register, the CC1NE active bit takes the new value from the preload bit when a
COM is generated.
Bit 1 CC1P : Capture/compare 1 output polarity
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input for trigger function (see
) :
0: Trigger on a high level or rising edge of TI1F
1: Trigger on a low level or falling edge of TI1F
CC1 channel configured as input for capture function (see
) :
0: Capture on a rising edge of TI1F or TI2F
1: Capture on a falling edge of TI1F or TI2F
Note: This bit is no longer writable while LOCK level 2 or 3 have been programmed (LOCK bits in
TIM1_BKR register).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM1_CR2 register, the CC1P active bit takes the new value from the preload bit when a
COM is generated.
Bit 0 CC1E : Capture/compare 1 output enable
CC1 channel is configured as output:
0: Off - OC1 is not active. OC1 level is then a function of the MOE, OSSI, OSSR, OIS1, OIS1N and
CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on the MOE, OSSI, OSSR,
OIS1, OIS1N and CC1NE bits.
CC1 channel is configured as input:
This bit determines if a capture of the counter value can be made in the input capture/compare register 1 (TIM1_CCR1) or not.
0: Capture disabled
1: Capture enabled
Note: On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIM1_CR2 register, the CC1E active bit takes the new value from the preload bit only when a COM is generated.
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Table 68. Output control for complementary OC i and OC i N channels with break
feature (1)
Control bits Output states
MOE OSSI OSSR CCiE CCiNE OCi OCiN
1 x
(2)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output disabled
(not driven by the timer)
Output disabled
(not driven by the timer)
OC
OC
OC i i i
REF + polarity OC
REF xor CC i P i =
REF + polarity + deadtime
Output disabled
(not driven by the timer)
OCiREF + polarity OC i N =
OCiREF xor CC i NP
Output disabled
(not driven by the timer)
Complementary to OC i REF
(not OC i REF) + polarity + deadtime
Output disabled
(not driven by the timer)
Output disabled
(not driven by the timer)
Off state
(output enabled with inactive state) OC i = CC i P
OCiREF + polarity OC
OC i REF xor CC i NP i N =
OCiREF + polarity OC
OC i REF xor CC i P i =
OCiREF + polarity + deadtime
Off state
(output enabled with inactive state) OC i N = CCiNP
Complementary to OC i REF
(not OC i REF) + polarity + deadtime
0
0
1
1
1
1
0
0
0 x
x x
Output disabled (not driven by the timer)
Off state (output enabled with inactive state)
Asynchronously: OC i = CC i P and OC i N = CC i NP
Then if the clock is present: OC i = OIS i and OC i N = OIS i N after a deadtime, assuming that OIS with OC i and OC i i and OIS
N in active state i N do not correspond
1. Never set CCiE = CCNiE = 0 when the channel is used. When the channel is not used, program CCiP = CCiNP = OISi =
OISiN = 0 otherwise.
2. Don’t care
Note: The state of the external I/O pins connected to the OCi channels depends on the OCi channel state and the GPIO registers.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x0E
Reset value: 0x00
7
Reserved r
6 5
CC4P rw
4
CC4E rw
3
CC3NP rw
2
CC3NE rw
1
CC3P rw
0
CC3E rw
Bits 7:6 Reserved
Bit 5 CC4P : Capture/compare 4 output polarity
Refer to CC1P description. As this bit is not connected to the external output, it is not used when the channel 4 is configured in output mode.
Bit 4 CC4E : Capture/compare 4 output enable
Refer to CC1E description. As this bit is not connected to the external output, it is not used when the channel 4 is configured in output mode.
Bit 3 CC3NP : Capture/compare 3 complementary output polarity
Refer to CC1NP description.
Bit 2 CC3NE : Capture/compare 3 complementary output enable
Refer to CC1NE description.
Bit 1 CC3P : Capture/compare 3 output polarity
Refer to CC1P description.
Bit 0 CC3E : Capture/compare 3 output enable
Refer to CC1E description.
Address offset: 0x0F
Reset value: 0x00
6 5 7 4 rw rw rw
Bits 7:0 CNT[15:8] : Counter value (MSB) rw
3
CNT[15:8] rw
2 rw
1 rw
0 rw
RM0031 Rev 15
417
16-bit advanced control timer (TIM1)
Address offset: 0x10
Reset value: 0x00
6 5 7 4 rw rw rw
Bits 7:0 CNT[7:0] : Counter value (LSB).
rw
CNT[7:0]
3 rw
2 rw
1 rw
RM0031
0 rw
7 rw
Bits 7:0
Address offset: 0x11
Reset value: 0x00
6 5 4 3 2 1 0
PSC[15:8] rw rw rw rw rw rw rw
PSC[15:8] : Prescaler value (MSB)
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT equal to f
CK_PSC
is
/ (PSCR[15:0]+1). PSCR contain the value which is loaded in the active prescaler register at each UEV (including when the counter is cleared through the UG bit of the TIM_EGR register or through the trigger controller when configured in trigger reset mode). A UEV must be generated so that a new prescaler value can be taken into account.
19.8.19 Prescaler low (TIM1_PSCRL)
Address offset: 0x12
Reset value: 0x00
7 6 5 4 3 2 1 0
PSC[7:0] rw rw rw rw rw rw rw rw
Bits 7:0 PSC[7:0] : Prescaler value (LSB)
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT equal to f
CK_PSC
is
/ (PSCR[15:0]+1). PSCR contains the value which is loaded in the active prescaler register at each UEV (including when the counter is cleared through the UG bit of the TIM1_EGR register or through the trigger controller when configured in trigger reset mode).
A UEV must be generated so that a new prescaler value can be taken into account.
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.8.20 Auto-reload register high (TIM1_ARRH)
Address offset: 0x13
Reset value: 0xFF
7 6 5 4 3 2 1 0
ARR[15:8] rw rw rw rw rw rw rw rw
Bits 7:0 ARR[15:8] : Auto-reload value (MSB)
for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
19.8.21 Auto-reload register low (TIM1_ARRL)
Address offset: 0x14
Reset value: 0xFF
7 6 5 4 3
ARR[7:0] rw rw rw
Bits 7:0 ARR[7:0] : Auto-reload value (LSB).
rw rw
2 rw
1 rw
0 rw
Address offset: 0x15
Reset value: 0xFF
7 6 5 4 3 2 1 0
REP[7:0] rw rw rw rw rw rw rw rw
Bits 7:0 REP[7:0] : Repetition counter value.
When the preload registers are enabled, these bits allow the user to set up the update rate of the compare registers (periodic transfers from preload to shadow registers) as well as the update interrupt generation rate if the update interrupt is enabled (UIE=1).
Each time the REP_CNT related down-counter reaches zero, a UEV is generated and it restarts counting from the REP value. As REP_CNT is reloaded with the REP value only at the repetition update event U_RC, any write to the TIM1_RCR register is not taken into account until the next repetition update event.
In PWM mode (REP+1) corresponds to:
– The number of PWM periods in edge-aligned mode
– The number of half PWM periods in center-aligned mode
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Address offset: 0x16
Reset value: 0x00
7 6 5 4 rw
CCR1[15:8]
3 rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 CCR1[15:8] : Capture/compare 1 value (MSB)
If the CC1 channel is configured as output (CC1S bits in TIM1_CCMR1 register):
The value of CCR1 is loaded permanently into the actual capture/compare 1 register if the preload feature is enabled (OC1PE bit in TIMx_CCMR1). Otherwise, the preload value is copied in the active capture/compare 1 register when a UEV occurs. The active capture/compare register contains the value which is compared to the counter register, TIMx_CNT, and signalled on the OC1 output.
If the CC1 channel is configured as input (CC1S bits in TIM1_CCMR1 register):
The value of CCR1 is the counter value transferred by the last input capture 1 event (IC1). In this case, these bits are read only.
Address offset: 0x17
Reset value: 0x00
7 6 5 4
CCR1[7:0] rw rw rw rw
Bits 7:0 CCR1[7:0] : Capture/compare 1 value (LSB)
3 rw
2 rw
1 rw
0 rw
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x18
Reset value: 0x00
7 6 5 4 rw
CCR2[15:8]
3 rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 CCR2[15:8] : Capture/compare 2 value (MSB)
If the CC2 channel is configured as output (CC2S bits in TIM1_CCMR2 register):
The value of CCR2 is loaded permanently into the actual capture/compare 2 register if the preload feature is not enabled (OC2PE bit in TIM1_CCMR2). Otherwise, the preload value is copied in the active capture/compare 2 register when a UEV occurs.The active capture/compare register contains the value which is compared to the counter register, TIM1_CNT, and signalled on the OC2 output.
If the CC2 channel is configured as input (CC2S bits in TIM1_CCMR2 register):
The value of CCR2 is the counter value transferred by the last input capture 2 event (IC2). In this case, these bits are read only.
Address offset: 0x19
Reset value: 0x00
7 6 5 4
CCR2[7:0] rw rw rw rw
Bits 7:0 CCR2[7:0] : Capture/compare value (LSB)
3 rw
2 rw
1 rw
0 rw
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Address offset: 0x1A
Reset value: 0x00
7 6 5 4 rw
CCR3[15:8]
3 rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 CCR3[15:8] : Capture/compare value (MSB)
If the CC3 channel is configured as output (CC3S bits in TIM_CCMR3 register):
The value of CCR3 is loaded permanently into the actual capture/compare 3 register if the preload feature is not enabled (OC3PE bit in TIM1_CCMR3). Otherwise, the preload value is copied in the active capture/compare 3 register when a UEV occurs.The active capture/compare register contains the value which is compared to the counter register, TIM1_CNT, and signalled on the OC3 output.
If the CC3 channel is configured as input (CC3S bits in TIM_CCMR3 register):
The value of CCR3 is the counter value transferred by the last input capture 3 event (IC31).
Address offset: 0x1B
Reset value: 0x00
7 6 5 4
CCR3[7:0] rw rw rw rw
Bits 7:0 CCR3[7:0] : Capture/compare value (LSB)
3 rw
2 rw
1 rw
0 rw
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset: 0x1C
Reset value: 0x00
7 6 5 4 rw
CCR4[15:8]
3 rw
2 1 0 rw rw rw rw rw rw
Bits 7:0 CCR4[15:8] : Capture/compare value (MSB)
If the CC4 channel is configured as output (CC4S bits in TIM1_CCMR4 register) :
The value of CCR4 is loaded permanently into the actual capture/compare 4 register if the preload feature is not enabled (OC4PE bit in TIM1_CCMR4). Otherwise, the preload value is copied in the active capture/compare 4 register when a UEV occurs.The active capture/compare register contains the value which is compared to the counter register, TIM1_CNT, and signalled on the OC4 output.
If the CC4 channel is configured as input (CC4S bits in TIM1_CCMR4 register) :
The value of CCR4 is the counter value transferred by the last input capture 4 event (IC4).
Address offset: 0x1D
Reset value: 0x00
7 6 5 4
CCR4[7:0] rw rw rw rw
Bits 7:0 CCR4[7:0] : Capture/compare value (LSB)
3 rw
2 rw
1 rw
0 rw
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
19.8.31 Break register (TIM1_BKR)
Address offset: 0x1E
Reset value: 0x00
7
MOE rw
6
AOE rw
5
BKP rw
4
BKE rw
3
OSSR rw
2
OSSI rw
1 rw
LOCK
0 rw
Bit 7 MOE : Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It acts only on the channels which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state
1: OC and OCN outputs are enabled if their respective enable bits are set (CC i E in TIM1_CCER i registers).
See OC/OCN enable description for more details ( Section 19.8.14 on page 362 ).
Bit 6 AOE : Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next UEV (if the break input is not active)
Note: This bit can no longer be modified while LOCK level 1 has been programmed (LOCK bits in the
TIM1_BKR register).
Bit 5 BKP : Break polarity
0: Break input BKIN is active low
1: Break input BKIN is active high
Note: This bit can no longer be modified while LOCK level 1 has been programmed (LOCK bits in the
TIM1_BKR register).
Bit 4 BKE : Break enable
0: Break input (BKIN) disabled
1: Break input (BKIN) enabled
Note: This bit can no longer be modified while LOCK level 1 has been programmed (LOCK bits in the
TIM1_BKR register).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Note:
Bit 3 OSSR : Off state selection for Run mode
This bit is used when MOE = 1 on channels with a complementary output which are configured as
outputs. See OC/OCN enable description for more details ( Section 19.8.14
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal = 0)
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CC i E = 1 or
CC i NE = 1, after which the OC/OCN enable output signal = 1
Note: This bit can no longer be modified while LOCK level 2 has been programmed (LOCK bits in
TIM1_BKR register).
Bit 2 OSSI : Off state selection for idle mode
This bit is used when MOE = 0 on channels configured as outputs. See OC enable description for
more details ( Section 19.8.14
).
0: When inactive, OC i outputs are disabled (OC i enable output signal = 0)
1: When inactive, OC i outputs are forced first with their idle level as soon as CC i E = 1 (OC enable output signal = 1)
Note: This bit can no longer be modified while LOCK level 2 has been programmed (LOCK bits in the
TIM1_BKR register).
Bits 1:0 LOCK[1:0] : Lock configuration
These bits offer a write protection against software errors.
00: LOCK off - No bits are write protected
01: LOCK level 1 - OIS i bit in TIM1_OISR register and BKE/BKP/AOE bits in TIM1_BKR register can no longer be written.
10: LOCK level 2 - LOCK level 1 + CC polarity bits (CC i P bits in TIM1_CCER i registers, as long as the related channel is configured in output through the CC i S bits) as well as the OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 - LOCK level 2 + CC control bits (OC i M and OC i PE bits in TIM1_CCMR i registers, as long as the related channel is configured in output through the CC i S bits) can no longer be written.
Note: The LOCK bits can be written only once after reset. Once the TIM1_BKR register has been written, their content is frozen until the next reset.
As the bits AOE, BKP, BKE, OSSR, and OSSI can be write-locked depending on the LOCK configuration, it is necessary to configure all of them during the first write access to the
TIM1_BKR register.
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
Address offset: 0x1F
Reset value: 0x00
7 6 5 4 3 2 1 0
DTG7:0] rw rw rw rw rw rw rw rw
Bits 7:0 DTG[7:0] : Deadtime generator set-up
This bitfield defines the duration of the deadtime inserted between the complementary outputs. DT corresponds to this duration. t
CK_PSC
is the TIM clock pulse.
DTG[7:5] = 0xx => DT= DTG[7:0] x t dtg
with t dtg
DTG[7:5] = 10x => DT= (64 + DTG[5:0]) x t dtg
DTG[7:5] = 110 => DT = (32 + DTG[4:0]) x t dtg
= t
CK_PSC
(f1)
with t dtg
= 2 x t
CK_PSC
(f2)
with t dtg
= 8 x t
CK_PSC
(f3)
DTG[7:5] = 111 => DT = (32 + DTG[4:0]) x t dtg
Example
with t dtg
= 16 x t
CK_PSC
(f4)
If t
CK_PSC
= 125 ns (8 MHz), deadtime possible values are:
DTG[7:0] = 0 x 0 to 0 x 7F from 0 to 15875 ns in 125 ns steps (refer to f1)
DTG[7:0] = 0 x 80 to 0 x BF from 16 µs to 31750 ns in 250 ns steps (refer to f2)
DTG[7:0] = 0 x C0 to 0 x DF from 32 µs to 63 µs in 1µs steps (refer to f3)
DTG[7:0] = 0 x E0 to 0 x FF from 64 µs to 126 µs in 2 µs steps (refer to f4)
Note: This bitfield can not be modified while LOCK level 1, 2, or 3 have been programmed (LOCK bits in the TIM_BKR register).
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.8.33 Output idle state register (TIM1_OISR)
Address offset: 0x20
Reset value: 0x00
7
Reserved
6 5
OIS3N rw
4
OIS3 rw
3
OIS2N rw
2
OIS2 rw
1
OIS1N rw
0
OIS1 rw
Bits 7:6 Reserved, forced by hardware to 0
Bit 5 OIS3N : Output idle state 3 (OC3N output)
Refer to OIS1N bit
Bit 4 OIS3 : Output idle state 3 (OC3 output)
Refer to OIS1 bit
Bit 3 OIS2N : Output idle state 2 (OC2N output)
Refer to OIS1N bit
Bit 2 OIS2 : Output idle state 2 (OC2 output)
Refer to OIS1 bit
Bit 1 OIS1N : Output idle state 1 (OC1N output).
0: OC1N = 0 after a deadtime when MOE = 0
1: OC1N = 1 after a deadtime when MOE = 0
Note: This bit can no longer be modified while LOCK level 1, 2 or 3 have been programmed (LOCK bits in the TIM1_BKR register).
Bit 0 OIS1 : Output idle state 1 (OC1 output).
0: OC1=0 (after a deadtime if OC1N is implemented) when MOE=0
1: OC1=1 (after a deadtime if OC1N is implemented) when MOE=0
Note: This bit can no longer be modified while LOCK level 1, 2 or 3 have been programmed (LOCK bits in the TIM1_BKR register).
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
19.8.34 DMA control register 1 (TIM1_DCR1)
7
Address offset: 0x21
Reset value: 0x00
6 5 4 3
Reserved rw rw
2
DBA[4:0] rw
1 rw
0 rw
Bits 7:5 Reserved, forced by hardware to 0
Bits 4:0 DBA[4:0] : DMA base address
This 5-bit vector defines the base-address for DMA transfers in burst mode (when read/write access is made through the TIM1_DMAR address). DBA is defined as an offset starting from the address of the TIM1_CR1 register.
00000: TIM1_CR1
00001: TIM1_CR2
00010: TIM1_SMCR
00011: TIM1_ETR
...
19.8.35 DMA control register 2 (TIM1_DCR2)
7
Address offset: 0x22
Reset value: 0x00
6 5 4 3
Reserved rw rw
2
DBL[4:0] rw
1 rw
Bits 7:5 Reserved, forced by hardware to 0
Bits 4:0 DBL[4:0] : DMA burst length
This 5-bit vector defines the length of DMA transfers in burst mode by setting the number of registers to be accessed.
00000: 1 register
00001: 2 registers
00010: 3 registers
...
11111: 32 registers
Note: The timer recognizes a burst transfer when a read or a write access is made to the
TIM1_DMAR register.
0 rw
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
19.8.36 DMA address for burst mode (TIM1_DMAR)
7
Address offset: 0x23
Reset value: 0x00
6 5 4 3
DMAB[7:0] rw rw rw rw rw
2 rw
1 0 rw rw
Bits 7:0 DMAB[15:0] : DMA register for burst accesses
″
″
″
A read or write access to the TIM1_DMAR register accesses the register located at the address:
“(TIM1_CR1 address) + DBA + (DMA index)” in which:
TIM1_CR1 is the address of control register 1
DBA is the DMA base address configured in the TIM1_DCR1 register
DMA index is the offset automatically controlled by the DMA transfer
RM0031 Rev 15
417
16-bit advanced control timer (TIM1) RM0031
0
CC3CE
0
IC3F3
0
OC4CE
0
IC4F3
0
CC2NP
0
-
0
CNT15
0
CNT7
0
0
IC1F3
0
CC2CE
0
IC2F3
ETP
0
-
0
BIE
0
BIF
0
ARPE
0
TI1S
0
MSM
0
-
0
BG
0
CC1CE
19.8.37 TIM1 register map and reset values
Address offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Register name
TIM1_SR2
Reset value
TIM1_EGR
Reset value
TIM1_CCMR1
(output mode)
Reset value
TIM1_CCMR1
(input mode)
Reset value
TIM1_ CCMR2
(output mode)
Reset value
TIM1_CCMR2
(input mode)
Reset value
TIM1_CCMR3
(output mode)
Reset value
TIM1_CCMR3
(input mode)
Reset value
TIM1_CR1
Reset value
TIM1_CR2
Reset value
TIM1_SMCR
Reset value
TIM1_ETR
Reset value
TIM1_DER
Reset value
TIM1_IER
Reset value
TIM1_SR1
Reset value
TIM1_CCMR4
(output mode)
Reset value
TIM1_CCMR4
(input mode)
Reset value
TIM1_CCER1
Reset value
TIM1_CCER2
Reset value
TIM1_CNTRH
Reset value
TIM1_CNTRL
Reset value
7
Table 69. TIM1 register map
6 5 4 3
0
OC3M2
0
IC3F2
0
OC4M2
0
IC4F2
0
CC2NE
0
-
0
CNT14
0
CNT6
0
0
IC1F2
0
OC2M2
0
IC2F2
ECE
0
-
0
TIE
0
TIF
0
CMS1
0
MMS2
0
TS2
0
-
0
TG
0
OC1M2
0
OC3M1
0
IC3F1
0
OC4M1
0
IC4F1
0
CC2P
0
CC4P
0
CNT13
0
CNT5
0
0
IC1F1
0
OC2M1
0
IC2F1
CMS0
0
MMS1
0
TS1
0
ETPS1
0
COMDE
0
COMIE
0
COMIF
0
-
0
COMG
0
OC1M1
0
OC3M0
0
IC3F0
0
OC4M0
0
IC4F0
0
CC2E
0
CC4E
0
CNT12
0
CNT4
0
0
IC1F0
0
OC2M0
0
IC2F0
DIR
0
MMS0
0
TS0
0
ETPS0
0
CC4DE
0
CC4IE
0
CC4IF
0
CC4OF
0
CC4G
0
OC1M0
2
0
OC3FE
0
IC3PSC0
0
-
0
IC4PSC0
0
CC1NE
0
CC3NE
0
CNT10
0
CNT2
0
URS
0
COMS-
0
SMS2
0
EFT2
0
CC2DE
0
CC2IE
0
CC2IF
0
CC2OF
0
CC2G
0
OC1FE
0
IC1PSC0
0
OC2FE
0
IC2PSC0
0
OC3PE
0
IC3PSC1
0
OC4PE
0
IC4PSC1
0
CC1NP
0
CC3NP
0
CNT11
0
CNT3
0
OPM
0
CCDS
0
OCCS
0
EFT3
0
CC3DE
0
CC3IE
0
CC3IF
0
CC3OF
0
CC3G
0
OC1PE
0
IC1PSC1
0
OC2PE
0
IC2PSC1
1
0
CC3S1
0
CC3S1
0
CC4S1
0
CC4S1
0
CC1P
0
CC3P
0
CNT9
0
CNT1
0
0
CC1S1
0
CC2S1
0
CC2S1
UDIS
0
-
0
SMS1
0
EFT1
0
CC1DE
0
CC1IE
0
CC1IF
0
CC1OF
0
CC1G
0
CC1S1
0
0
CC3S0
0
CC3S0
0
CC4S0
0
CC4S0
0
CC1E
0
CC3E
0
CNT8
0
CNT0
0
0
CC1S0
0
CC2S0
0
CC2S0
CEN
0
CCPC-
0
SMS0
0
EFT0
0
UDE
0
UIE
0
UIF
0
-
0
UG
0
CC1S0
RM0031 Rev 15
RM0031 16-bit advanced control timer (TIM1)
Address offset
0x11
0x1D
0x1E
0x1F
0x20
0x19
0x1A
0x1B
0x1C
0x21
0x22
0x23
0x15
0x16
0x17
0x18
0x12
0x13
0x14
Register name
TIM1_PSCRH
Reset value
TIM1_PSCRL
Reset value
TIM1_ARRH
Reset value
TIM1_ARRL
Reset value
TIM1_RCR
Reset value
TIM1_CCR1H
Reset value
TIM1_CCR1L
Reset value
TIM1_CCR2H
Reset value
TIM1_CCR2L
Reset value
TIM1_CCR3H
Reset value
TIM1_CCR3L
Reset value
TIM1_CCR4H
Reset value
TIM1_CCR4L
Reset value
TIM1_BKR
Reset value
TIM1_DTR
Reset value
TIM1_OISR
Reset value
TIM1_DCR1
Reset value
TIM1_DCR2
Reset value
TIM1_DMAR
Reset value
Table 69. TIM1 register map (continued)
7 6 5 4 3
CCR17
0
CCR215
0
CCR27
0
CCR315
0
CCR37
0
CCR415
0
CCR47
0
MOE
0
-
0
-
0
DTG7
0
-
0
DMAB7
0
PSC15
0
PSC7
0
ARR15
1
ARR7
1
REP7
0
CCR115
0
CCR15
0
CCR213
0
CCR25
0
CCR313
0
CCR35
0
CCR413
0
CCR45
0
BKP
0
DTG5
0
OIS3N
0
-
0
-
0
DMAB5
0
PSC13
0
PSC5
0
ARR13
1
ARR5
1
REP5
0
CCR113
0
CCR16
0
CCR214
0
CCR26
0
CCR314
0
CCR36
0
CCR414
0
CCR46
0
AOE
0
-
0
-
0
DTG6
0
-
0
DMAB6
0
PSC14
0
PSC6
0
ARR14
1
ARR6
1
REP6
0
CCR114
0
CCR14
0
CCR212
0
CCR24
0
CCR312
0
CCR34
0
CCR412
0
CCR44
0
BKE
0
DTG4
0
OIS3
0
DBA4
0
DBL4
0
DMAB4
0
PSC12
0
PSC4
0
ARR12
1
ARR4
1
REP4
0
CCR112
0
2
CCR12
0
CCR210
0
CCR22
0
CCR310
0
CCR32
0
CCR410
0
CCR42
0
OSSI
0
DTG2
0
OIS2
0
DBA2
0
DBL2
0
DMAB2
0
PSC10
0
PSC2
0
ARR10
1
ARR2
1
REP2
0
CCR110
0
CCR13
0
CCR211
0
CCR23
0
CCR311
0
CCR33
0
CCR411
0
CCR43
0
OSSR
0
DTG3
0
OIS2N
0
DBA3
0
DBL3
0
DMAB3
0
PSC11
0
PSC3
0
ARR11
1
ARR3
1
REP3
0
CCR111
0
1
CCR31
0
CCR49
0
CCR41
0
LOCK
0
CCR11
0
CCR29
0
CCR21
0
CCR39
0
DTG1
0
OIS1N
0
DBA1
0
DBL1
0
DMAB1
0
PSC9
0
PSC1
0
ARR9
1
ARR1
1
REP1
0
CCR19
0
0
CCR30
0
CCR48
0
CCR40
0
LOCK
0
CCR10
0
CCR28
0
CCR20
0
CCR38
0
DTG0
0
OIS1
0
DBA0
0
DBL0
0
DMAB0
0
PSC8
0
PSC0
0
ARR8
1
ARR0
1
REP0
0
CCR18
0
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
20 16-bit general purpose timers (TIM2, TIM3, TIM5)
RM0031
20.1 TIM2, TIM3 and TIM5 introduction
This chapter describes TIM2, TIM3 and TIM5which are identical timers.
Each timer consists of a 16-bit up-down auto-reload counter driven by a programmable prescaler.
It may be used for a variety of purposes, including:
• Time base generation
• Measuring the pulse lengths of input signals (input capture)
• Generating output waveforms (output compare, PWM and One-pulse mode)
• Interrupt capability on various events (capture, compare, overflow)
• Synchronization with other timers or external signals (external clock, reset, trigger and enable)
The timer clock can be sourced from internal clocks or from an external source selectable through a configuration register.
Only the main features of the general purpose timers are given in this chapter. Refer to the
corresponding paragraphs of Section 19: 16-bit advanced control timer (TIM1) on page 291
for more details on each feature.
20.2 TIMx main features
General purpose TIMx TIM2/TIM3 features include:
• 16-bit up, down, up/downauto-reload counter.
• 3-bit programmable prescaler allowing the counter clock frequency to be divided “on the fly” by any power of 2 from 1 to 128.
• 2 independent channels for:
– Input capture
– Output compare
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Break input to put the timer output signals in reset state or in a known state.
• Input capture 2 can be routed from COMP2 comparator
• Interrupt/ DMA request generation on the following events:
– Update: counter overflow, counter initialization (by software)
– Input capture
– Output compare
– Break input
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.3 TIMx functional description
Figure 120. TIMx block diagram f
SYSCLK
TIMx_ETR ETR
TRGO from other TIM timers
INTx
TRC
(from clock/trigger controller)
CLOCK/TRIGGER CONTROLLER
TIM2 TRGO to other TIM timers & ADC
TIM3 TRGO to other TIM timers
TIM5 TRGO to other TIM timers & DAC
TIME BASE UNIT
CK_PSC Prescaler
CK_CNT
UP-DOWN COUNTER Auto-reload register
TIMx_CH1
TI1
TIMx_CH2
TI2
INPUT
STAGE
IC1
CAPTURE COMPARE ARRAY
CC1I
IC1PS
UEV
Prescaler Capture/Compare 1 Register
IC2
CC2I
Prescaler
IC2PS
UEV
Capture/Compare 2 Register
OC1REF
OC2REF
OUTPUT
STAGE to IR block
OC1
TIMx_ CH1
OC2
TIMx_CH2 from COMP2 1)
TIMx_BKIN
Legend:
Reg
Preload registers transferred to shadow registers on update event (UEV) according to control bit event interrupt
1. Available only for TIM2 and TIM3
20.3.1 Time base unit
The timer has a time base unit that includes:
• 16-bit up-down counter
• 16-bit auto-reload register
• 3-bit programmable prescaler
There is no repetition counter.
The clock source for is the internal clock (f
SYSCLK
). It is connected directly to the CK_PSC clock that feeds the prescaler driving the counter clock CK_CNT.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
Figure 121. Time base unit
RM0031
For more details refer to Section 19.3: TIM1 time base unit on page 294 .
Prescaler
The prescaler implementation is as follows:
• The prescaler is based on a 7-bit counter controlled through a 3-bit register (in
TIMx_PSCR register). It can be changed on the fly as this control register is buffered. It can divide the counter clock frequency by 1, 2, 4, 8, 16, 32, 64 or 128.
The counter clock frequency is calculated as follows: f
CK_CNT
= f
CK_PSC
/2 (PSCR[2:0])
Counter operation
Refer to Section 19.3.4: Up-counting mode on page 296 ,
Section 19.3.5: Down-counting mode on page 298
and Section 19.3.6: Center-aligned mode (up/down counting) on page 300
.
Refer to Section 19.4: TIM1 clock/trigger controller on page 304 .
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Input stage
Refer to Section 19.5: TIM1 capture/compare channels on page 319 .
There are two input channels, as shown in
Figure 122: Input stage block diagram . Channel
2 is internally connected to the comparator.
Figure 122. Input stage block diagram
TIMx_CH1
TI1F_ED
XOR
TI1S
TI1
Input Filter &
Edge Detector
TI1FP1
TI1FP2
TRC to clock/trigger controller
TIMx_CH2
TIMx_BKIN
TI2 Input Filter &
Edge Detector
TI2FP1
TI2FP2
TRC
(from clock/trigger controller)
From comparator
IC2 to capture/compare channels
Figure 123. Input stage of TIM 2 channel 1
TI1F_ED to the clock/trigger controller
TI1 f
SYSCLK filter down-counter
TI1F Edge
Detector
ICF[3:0]
TIM2_CCMR1
TI1F_rising
TI1F_falling
CC1P
TIM2_CCER1
TI2F_rising
(from channel 2)
TI2F_falling
(from channel 2)
0
1
0
TI1FP1
1
01
TI2FP1
10
IC1 divider
/1, /2, /4, /8
TRC
11
(from clock/trigger controller)
CC1S[1:0] ICPS[1:0]
TIM2_CCMR1
ICPS
CC1E
TIM2_CCER1
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
Output stage
Refer to Section 19.5.4: Output stage on page 324 ,
Section 19.5.5: Forced output mode on page 325
,
Section 19.5.7: PWM mode on page 327 .
As shown in
Figure 124 . TIMx outputs have no deadtime or complementary outputs.
Figure 124. Output stage
OC1REF output control OC1 from capture/compare channels
OC2REF output control OC2
TIMx_CH1
TIMx_CH2
The output stage generates an intermediate waveform which is then used for reference:
OCxREF (active high). Break functions and polarity act at the end of the chain (see
Figure 125. Output stage of channel 1
ETR
Counter
Counter
> CCR1
Output mode
= CCR1 controller
OC1REF
0
1
CC1P
TIMx_CCER1
Output
Enable
Circuit
OC1
OC1M[2:0]
TIMx_CCMR1
CC1E TIMx_CCER1
M0E OSSI TIMx_BKR
Break
When using the break function, the output enable sig nals and inactive levels are modified according to additional control bits (MOE and OSSI bits in the TIMx_BKR register).
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break function by setting the BKE bit in the TIMx_BKR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time.
For more details, refer to “
Using the break function on page 334
. See also
.
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.3.4 Timer input XOR function
The TI1S bit in the TIMx_CR2 register allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_BKIN.
The XOR output can be used with all the timer input functions such as trigger or input capture.
An example of this feature used to interface Hall sensors is given in
Interfacing with Hall sensors on page 340 .
The timers have 5 interrupt request sources:
• Capture/compare 2 interrupt
• Capture/compare 1 interrupt
• Update interrupt
• Break input
• Trigger interrupt
To use the interrupt features, for each interrupt channel used, set the desired CC2IE and/or
CC1IE bits in the TIMx_IER register to enable interrupt requests.
The different interrupt sources can be also generated by software using the corresponding bits in the TIMx_EGR register.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
20.5.1 Control register 1 (TIMx_CR1)
7
ARPE rw
Address offset: 0x00
Reset value: 0x00
6 5
CMS[1:0] rw
4
DIR rw
3
OPM rw
2
URS rw
1
UDIS rw
0
CEN rw
Bit 7 ARPE : Auto-reload preload enable
0: TIMx_ARR register is not buffered through a preload register. It can be written directly
1: TIMx_ARR register is buffered through a preload register
Bits 6:5 CMS(1:0] : Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in TIMx_CCMR i registers) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in TIMx_CCMR i registers) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternately. Output compare interrupt flags of channels configured in output (CC i S = 00 in TIMx_CCMR i registers) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN = 1).
Encoder mode (SMS = 001, 010, or 011 in GPT_SMCR register) must be disabled in centeraligned mode.
Bit 4 DIR : Direction
0: Counter used as up-counter
1: Counter used as down-counter
Note: This bit is read only when the timer is configured in center-aligned mode or encoder mode.
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit)
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Bit 2 URS : Update request source
0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one of the following events occurs:
– Registers are updated (counter overflow/underflow)
– UG bit is set by software
– Update event is generated through the clock/trigger controller
1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when registers are updated (counter overflow/underflow).
Bit 1 UDIS : Update disable
0: A UEV is generated as soon as a counter overflow occurs or a software update is generated or an hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded with their preload values.
1: A UEV is not generated, shadow registers keep their value (ARR, PSC, CCR i ). The counter and the prescaler are re-initialized if the UG bit is set.
Bit 0 CEN : Counter enable
0: Counter disabled
1: Counter enabled
20.5.2 Control register 2 (TIMx_CR2)
Address offset: 0x01
Reset value: 0x00
7
TI1S
6 rw
5
MMS[2:0] rw
4 rw
3
CCDS rw
2 1
Reserved
0
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
Bit 7 TI1S: TI1 (digital filter input) selection
0: TI1 is connected to CH1 input pin
1: TI1 is connected to the 3 inputs CH1, CH2 and break (XOR combination)
Bits 6:4 MMS[2:0] : Master mode selection
These bits select the information to be sent in master mode to the slave timers for synchronization
(TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If the reset is generated by the trigger input (clock/trigger mode controller configured in trigger reset mode), the signal on TRGO is delayed compared to the actual reset.
001: Enable - the counter enable signal is used as a trigger output (TRGO). It is used to start several timers at the same time or to control a window in which a slave timer is enabled. The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in gated mode. When the counter enable signal is controlled by the trigger input, there is a delay on
TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
010: Update - The update event is selected as a trigger output (TRGO)
011: Reserved
100: Reserved
101: Reserved
111: Reserved
Bit 3 CCDS : Capture/compare DMA selection
0: TIMx_CC i DMA request sent when a CC i (capture/compare) event occurs
1: TIMx_CC i DMA request sent when an update event occurs
Bits 2:0 Reserved, must be kept cleared
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
7
MSM rw
Address offset: 0x02
Reset value: 0x00
6 rw
5
TS[2:0] rw
4 rw
3
Reserved r
2 rw
1
SMS[2:0] rw
0 rw
Bit 7 MSM Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between timers (through TRGO).
Bits 6:4 TS[2:0] Trigger selection
(1)
This bit field selects the trigger input to be used to synchronize the counter.
000: Internal trigger ITR0
001: Internal trigger ITR1
010: Internal trigger ITR2
011: Internal trigger ITR3 connected to TIM1 TRGO
100: TI1 edge detector (TI1F_ED)
101: Filtered timer input 1 (TI1FP1)
110: Filtered timer input 2 (TI2FP2)
111: External trigger input (ETRF) (from TIM1_ETR pin). Signal filtering and polarity can be controlled by the TIM5_CCMRi and TIM5_CCERi registers.
Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid wrong edge detections at the transition.
Bit 3 Reserved.
Bits 2:0 SMS[2:0] Clock/trigger/slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description).
000: Clock/trigger controller disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock.
001, 010 and 011: Reserved
100: Trigger reset mode - Rising edge of the selected trigger signal (TRGI) reinitializes the counter and generates an update of the registers.
101: Gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both the start and stop of the counter are controlled.
110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
1. Refer to Table 70: TIMx internal trigger connection on page 389
for more details on the ITRx meaning for each timer.
Slave TIM
TIM2
TIM3
Table 70. TIMx internal trigger connection
ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)
TIM3 TIM4
TIM4
TIM4
TIM1
TIM1
TIM1 TIM3
ITR3 (TS = 011)
TIM2
TIM2
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
Note:
RM0031
When a timer is not present in the product, the corresponding trigger (ITRx) is not available.
7
ETP rw
Address offset: 0x03
Reset value: 0x00
6
ECE
5 rw rw
ETPS[1:0]
4 rw
3 rw
2 rw
ETF[3:0]
1 rw
0 rw
Bit 7 ETP : External trigger polarity
This bit selects whether ETR or ETR is used for trigger operations.
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 6 ECE : External clock enable
This bit enables external clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Note: Setting the ECE bit has the same effect as selecting the external clock mode 1 with TRGI connected to ETRF (SMS = 111 and TS = 111 in the TIM1_SMCR register).
It is possible to use the external clock mode 2 simultaneously with the following modes: Trigger standard mode, trigger reset mode and trigger gated mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111 in TIMx_SMCR register).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input will be ETRF.
Bits 5:4 ETPS[1:0] : External trigger prescaler
External trigger signal ETRP frequency must be at 1/4 of f
SYSCLK
frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
00: Prescaler off
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 3:0 ETF[3:0] : External trigger filter
This bitfield defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
SYSCLK
1000: f
SAMPLING
=f
SYSCLK
/8, N = 6
0001: f
SAMPLING
=f
SYSCLK
, N = 2 1001: f
SAMPLING
=f
SYSCLK
/8, N = 8
/16, N = 5 0010: f
SAMPLING
=f
SYSCLK
0011: f
SAMPLING
=f
SYSCLK
0100: f
SAMPLING
=f
SYSCLK
, N = 4 1010: f
SAMPLING
, N = 8 1011: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
/16, N = 6
/16, N = 8
0101: f
SAMPLING
=f
SYSCLK
0110: f
0111: f
SAMPLING
SAMPLING
=f
=f
SYSCLK
SYSCLK
/2, N = 6 1100: f
SAMPLING
/2, N = 8 1101: f
SAMPLING
=f
SYSCLK
=f
SYSCLK
/4, N = 6 1110: f
SAMPLING
=f
SYSCLK
/32, N = 5
/32, N = 6
/4, N = 8 1111: f
SAMPLING
=f
SYSCLK
/32, N = 8
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Address offset: 0x04
Reset value: 0x00
7 6 5
Reserved
4 3 2
CC2DE rw
1
CC1DE rw
0
UDE rw
Bits 7:3 Reserved.
Bit 2 CC2DE : Capture/compare 2 DMA request enable
(1)
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 1 CC1DE
: Capture/compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 0 UDE
0: Update DMA request disabled
1: Update DMA request enabled
Note: The conditions for generating a DMA request on the update event are the same as for setting the UIF bit (in the TIMx_SR1 register). In particular, the DMA request depends on the URS bit
(in the TIMx_CR1 register).
1.
The DMA request is related to the actual event and not to the status bit (in the TIMx_SR1 register). Thus no DMA request is sent if the xxDE bit is written to 1 while the corresponding status bit was already set.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
7
BIE rw
Address offset: 0x05
Reset value: 0x00
6
TIE rw
5 4
Reserved
Bit 7 BIE : Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE : Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bits 5:3 Reserved, must be kept cleared
Bit 2 CC2IE : Capture/compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE : Capture/compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
3
RM0031
2
CC2IE rw
1
CC1IE rw
0
UIE rw
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.5.7 Status register 1 (TIMx_SR1)
7
BIF rc_w0
Address offset: 0x06
Reset value: 0x00
6
TIF
5 rc_w0
4
Reserved
3 2
CC2IF rc_w0
1
CC1IF rc_w0
0
UIF rc_w0
Bit 7 BIF : Break interrupt flag
This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
Bit 6 TIF : Trigger interrupt flag
This flag is set by hardware on a trigger event (active edge is detected on TRGI signal and both edges are detected when gated mode is selected). It is cleared by software.
0: No trigger event has occurred
1: Trigger interrupt pending
Bits 5:3 Reserved, must be kept cleared
Bit 2 CC2IF : Capture/compare 2 interrupt flag
Refer to CC1IF description.
Bit 1 CC1IF : Capture/compare 1 interrupt flag
If channel CC1 is configured as output :
This flag is set by hardware when the counter matches the compare value. It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register
If channel CC1 is configured as input :
This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1L register.
0: No input capture has occurred
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity).
Bit 0 UIF : Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update has occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow if UDIS = 0 in the TIMx_CR1 register
– When CNT is re-initialized by software using the UG bit in TIMx_EGR register, if URS = 0 and
UDIS = 0 in the TIMx_CR1 register.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
20.5.8 Status register 2 (TIMx_SR2)
7
Address offset: 0x07
Reset value: 0x00
6 5 4
Reserved
3 2
CC2OF rc_w0
1
CC1OF rc_w0
0
Reserved
Bits 7:3 Reserved
Bit 2 CC2OF : Capture/compare 2 overcapture flag
Refer to CC1OF description
Bit 1 CC1OF : Capture/compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bit 0 Reserved, forced by hardware to 0
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
7
BG w
Address offset: 0x08
Reset value: 0x00
6
TG w
5 4
Reserved
3 2
CC2G w
1
CC1G w
0
UG w
Bit 7 BG : Break generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: A break event is generated. The MOE bit is cleared and the BIF flag is set. An interrupt is generated if enabled by the BIE bit.
Bit 6 TG : Trigger generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIMx_SR1 register. An interrupt is generated if enabled by the TIE bit
Bits 5:3 Reserved
Bit 2 CC2G : Capture/compare 2 generation
Refer to CC1G description
Bit 1 CC1G : Capture/compare 1 generation
This bit is set by software to generate an even. It is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
– If the CC1 channel is configured in output mode. In this case, the CC1IF flag is set, and the corresponding interrupt request is sent if enabled.
– If the CC1 channel configured in input mode. In this case, the current value of the counter is captured in the TIMx_CCR1 register. The CC1IF flag is set, and the corresponding interrupt request is sent if enabled. The CC1OF flag is set if the CC1IF flag is already high.
Bit 0 UG : Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. Note that the prescaler counter is also cleared.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
7 r
Reserved
The channel can be used in input (capture mode) or in output (compare mode). The direction of the channel is defined by configuring the CC1S bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OC i describes its function when the channel is configured in output and IC i describes its function when the channel is configured in input. Therefore, be aware that the same bit can have a different meaning for the input stage and for the output stage.
Address offset: 0x09
Reset value: 0x00
Channel configured in output
6 rw rw
5 rw
OC1M[2:0] rw
4 rw rw
3 rw
OC1PE rw
2 r
OC1FE rw
1 rw rw
CC1S[1:0]
0 rw rw
Bit 7 Reserved
Bits 6:4 OC1M[2:0] : Output compare 1 mode
These bits defines the behavior of the output reference signal OC1REF from which OC1 is derived.
OC1REF is active high whereas OC1 active level depends on the CC1P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter
TIMx_CNT has no effect on the outputs
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
100: Force inactive level - OC1REF is forced low
101: Force active level - OC1REF is forced high
110: PWM mode 1 - In up-counting, channel 1 is active as long as TIMx_CNT< TIMx_CCR1.
Otherwise, channel 1 is inactive. In down-counting, channel 1 is inactive (OC1REF = 0) as long as
TIMx_CNT> TIMx_CCR1. Otherwise, channel 1 is active (OC1REF = 1).
111: PWM mode 2 - In up-counting, channel 1 is inactive as long as TIMx_CNT< TIMx_CCR1.
Otherwise, channel 1 is active.
Note: In PWM mode 1 or 2, the OCiREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.
Refer to Section 19.5.7 on page 327
for more details.
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Bit 3 OC1PE : Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime. The new value is taken into account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/write operations access the preload register.
TIMx_CCR1 preload value is loaded in the shadow register at each update event.
Note: For correct operation, preload registers must be enabled when the timer is in PWM mode. This is not mandatory in one-pulse mode (OPM bit set in TIMx_CR1 register).
Bit 2 OC1FE : Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is on. The minimum delay to activate CC1 output when an edge occurs on the trigger input, is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. The delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S[1:0] : Capture/compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1FP1
10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM5_SMCR register).
Note: CC1S bits are writable only when the channel is off (CC1E = 0 and is updated in
TIMx_CCER1).
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
7 rw
Channel configured in input
6 5 4
IC1F[3:0] rw rw rw
3 2 rw
IC1PSC[1:0] rw
RM0031
1 rw
CC1S[1:0]
0 rw
Bits 7:4 IC1F[3:0] : Input capture 1 filter
This bitfield defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at f
SYSCLK
0001: f
SAMPLING
0010: f
SAMPLING
= f
SYSCLK
= f
SYSCLK
0011: f
SAMPLING
= f
SYSCLK
, N = 2
, N = 4
, N = 8
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
= f
SYSCLK
= f
SYSCLK
= f
SYSCLK
0111: f
SAMPLING
= f
SYSCLK
/2, N = 6
/2, N = 8
/4, N = 6
/4, N = 8
1000: f
SAMPLING
1001: f
SAMPLING
= f
SYSCLK
= f
SYSCLK
/8, N = 6
/8, N = 8
/16, N = 5 1010: f
SAMPLING
1011: f
SAMPLING
= f
SYSCLK
= f
SYSCLK
/16, N = 6
/16, N = 8 1100: f
SAMPLING
1101: f
SAMPLING
1110: f
SAMPLING
= f
SYSCLK
= f
SYSCLK
= f
SYSCLK
1111: f
SAMPLING
= f
SYSCLK
/32, N = 5
/32, N = 6
/32, N = 8
Bits 3:2 IC1PSC[1:0] : Input capture 1 prescaler
This bitfield defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E = 0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: Capture is done once every 2 events
10: Capture is done once every 4 events
11: Capture is done once every 8 events
Note: The internal event counter is not reset when IC1PSC is changed on the fly. In this case the old value is used until the next capture occurs. To force a new value to be taken in account immediately, the CC1E bit can be cleared and set again.
Bits 1:0 CC1S[1:0] : Capture/compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1FP1
10: CC1 channel is configured as input, IC1 is mapped on TI2FP1
11: Reserved
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER1 and updated).
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Note:
Refer to Capture/compare mode register 1 (TIMx_CCMR1) on page 396
for details on using these bits.
Address offset: 0x0A
Reset value: 0x00
Channel configured in output
7
Reserved r
6 rw
5
OC2M[2:0] rw
4 rw
3
OC2PE rw
2
OC2FE rw
1
CC2S[1:0] rw
0
Bit 7 Reserved
Bits 6:4 OC2M[2:0] : Output compare 2 mode
Bit 3 OC2PE : Output compare 2 preload enable
Bit 2 OC2FE : Output compare 2 fast enable
Bits 1:0 CC2S[1:0] : Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2FP2
10: CC2 channel is configured as input, IC2 is mapped on TI1FP2
11:CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIM5_SMCR register).
Note: CC2S bits are writable only when the channel is off (CC2E = 0 in TIMx_CCER1).
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
Channel configured in input
7 6
IC2F[3:0]
5 4 3 2 rw
IC2PSC[1:0] rw
1
CC2S[1:0] rw rw rw rw rw
Bits 7:4 IC2F[3:0] : Input capture 2 filter
Bits 3:2 IC2PCS[1:0] : Input capture 2 prescaler
Bits 1:0 CC2S[1:0] : Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2FP2
10: CC2 channel is configured as input, IC2 is mapped on TI1FP2
11: Reserved
Note: CC2S bits are writable only when the channel is off (CC2E = 0 in TIMx_CCER1).
0 rw
7
Address offset: 0x0B
Reset value: 0x00
6 5
Reserved r
CC2P rw
4
CC2E rw
Bits 6:7 Reserved
Bit 5 CC2P : Capture/compare 2 output polarity
Refer to CC1P description
Bit 4 CC2E : Capture/compare 2 output enable
Refer to CC1E description.
3
Reserved r
2 1
CC1P rw
0
CC1E rw
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
Bits 2:3 Reserved
Bit 1 CC1P : Capture/compare 1 output polarity
CC1 channel configured as output :
0: OC1 active high
1: OC1 active low
CC1 channel configured as input for capture function (see
) :
0: Capture is done on a rising edge of TI1F or TI2F
1: Capture is done on a falling edge of TI1F or TI2F
Bit 0 CC1E : Capture/Compare 1 output Enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input :
In this case, this bit determines if a capture of the counter value can be made in the input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled
Address offset: 0x0C
Reset value: 0x00
6 5 7 4 rw rw rw
Bits 7:0 CNT[15:8] : Counter value (MSB) rw
3
CNT[15:8] rw
Address offset: 0x0D
Reset value: 0x00
6 5 7 rw rw rw
Bits 7:0 C NT[7:0] : Counter value (LSB)
4 rw
CNT[7:0]
3 rw
2 rw
2 rw
1 rw
1 rw
0 rw
0 rw
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
20.5.15 Prescaler register (TIMx_PSCR)
7
Address offset: 0x0E
Reset value: 0x00
6 5 4
Reserved
3 2 rw
1
PSC[2:0] rw
0 rw
Bits 7:3 Reserved
Bits 2:0 PSC[2:0] : Prescaler value
The prescaler value divides the CK_PSC clock frequency.
The counter clock frequency f hardware.
CK_CNT
is equal to f
CK_PSC
/ 2 (PSC[2:0]) . PSC[7:3] are forced to 0 by
PSCR contains the value which is loaded in the active prescaler register at each update event
(including when the counter is cleared through the UG bit of the TIMx_EGR register).
This means that a UEV must be generated so that a new prescaler value can be taken into account.
20.5.16 Auto-reload register high (TIMx_ARRH)
7
Address offset: 0x0F
Reset value: 0xFF
6 5 4 3
ARR[15:8] rw rw rw rw rw
2 1 0 rw rw rw
Bits 7:0 ARR[15:8] : Auto-reload value (MSB)
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
Section 19.3: TIM1 time base unit on page 294 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is 0.
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.5.17 Auto-reload register low (TIMx_ARRL)
7
Address offset: 0x10
Reset value: 0xFF
6 5 4 3
ARR[7:0] rw rw rw rw rw
Bits 7:0 ARR[7:0] : Auto-reload value (LSB)
2 rw
1 rw
0 rw
Address offset: 0x11
Reset value: 0x00
6 5 7 4 3 2 1 0
CCR1[15:8] rw rw rw rw rw rw rw rw
Bits 7:0 CCR1[15:8] : Capture/compare 1 value (MSB)
If the CC1 channel is configured as output (CC1S bits in TIMx_CCMR1 register) :
The value of CCR1 is loaded permanently into the actual capture/compare 1 register if the preload feature is not enabled (OC1PE bit in TIMx_CCMR1). Otherwise, the preload value is copied in the active capture/compare 1 register when a UEV occurs. The active capture/compare register contains the value which is compared to the counter register, TIMx_CNT, and signalled on the OC1 output.
If the CC1 channel is configured as input (CC1S bits in TIMx_CCMR1 register) :
The value of CCR1 is the counter value transferred by the last input capture 1 event (IC1). In this case, these bits are read only.
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5)
Address offset: 0x12
Reset value: 0x00
6 5 7 4
CCR1[7:0] rw rw rw rw
Bits 7:0 CCR1[7:0] : Capture/compare 1 value (LSB)
3 rw
2 rw
1 rw
RM0031
0 rw
Address offset: 0x13
Reset value: 0x00
6 5 7 4 3 2 1 0
CCR2[15:8] rw rw rw rw rw rw rw rw
Bits 7:0 CCR2[15:8] : Capture/compare 2 value (MSB)
If the CC2 channel is configured as output (CC2S bits in TIMx_CCMR2 register) :
The value of CCR2 is loaded permanently into the actual capture/compare 2 register if the preload feature is not enabled (OC2PE bit in TIMx_CCMR2). Otherwise, the preload value is copied in the active capture/compare 2 register when a UEV occurs. The active capture/compare register contains the value which is compared to the counter register, TIMx_CNT, and signalled on the OC2 output.
If the CC2 channel is configured as input (CC2S bits in TIMx_CCMR2 register) :
The value of CCR2 is the counter value transferred by the last input capture 2 event (IC2).
Address offset: 0x14
Reset value: 0x00
6 5 7 4
CCR2[7:0] rw rw rw rw
Bits 7:0 CCR2[7:0] : Capture/compare value (LSB)
3 rw
2 rw
1 rw
0 rw
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.5.22 Break register (TIMx_BKR)
7
MOE rw
Address offset: 0x15
Reset value: 0x00
6
AOE rw
5
BKP rw
4
BKE rw
3
Reserved
2
OSSI rw
1 rw
LOCK
0 rw
Bit 7 MOE : Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It acts only on the channels which are configured in output.
0: OC outputs are disabled or forced to idle state
1: OC outputs are enabled if their respective enable bits are set (CCxE in TIMx_CCER i registers)
See OC enable description for more details (
).
Bit 6 AOE : Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next UEV (if the break input is not active).
Note: This bit can no longer be modified as long as LOCK level 1 has been programmed (LOCK bits in the TIMx_BKR register).
Bit 5 BKP : Break polarity
0: Break input BKIN is active low
1: Break input BKIN is active high
Note: This bit can no longer be modified as long as LOCK level 1 has been programmed (LOCK bits in the TIMx_BKR register).
Bit 4 BKE : Break enable
0: Break input (BKIN) disabled
1: Break input (BKIN) enabled
Note: This bit can no longer be modified as long as LOCK level 1 has been programmed (LOCK bits in the TIMx_BKR register).
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
Note:
Bit 3 Reserved, must be kept cleared
Bit 2 OSSI : Off state selection for idle mode
This bit is used when MOE = 0 on channels configured as outputs. See OC enable description for
more details ( Section 19.8.14 on page 362 ).
0: When inactive, OC i outputs are disabled (OC i enable output signal = 0).
1: When inactive, OC i outputs are forced first with their idle level as soon as CC i E = 1. OC enable output signal = 1)
Note: This bit can no longer be modified as soon as the LOCK level 2 has been programmed (LOCK bits in the TIMx_BKR register).
Bits 1:0 LOCK[1:0] : Lock configuration.
These bits offer a write protection against software errors.
00: LOCK off - No bits are write protected
01: LOCK level 1 = OIS i bit in TIMx_OISR register and BKE/BKP/AOE bits in TIMx_BKR register can no longer be written.
10: LOCK level 2 = LOCK level 1 + CC polarity bits (CC i P bits in TIMx_CCER i registers, as long as the related channel is configured in output through the CC i S bits) as well as the OSSR and OSSI bits can no longer be written.
11: LOCK level 3 = LOCK level 2 + CC control bits (OC i M and OC i PE bits in TIMx_CCMR i registers, as long as the related channel is configured in output through the CC i S bits) can no longer be written.
Note: The LOCK bits can be written only once after reset. Once the TIMx_BKR register has been written, their content is frozen until the next reset.
As the bits AOE, BKP, BKE and OSSI can be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the
TIMx_BKR register.
Table 71. Output control bit for OC i channels with break feature (break feature implemented, complementary output not implemented)
Control bits
OC i /OC i _EN output state
MOE bit
OSSI bit
CC i E bit
1 x
0
1
Output disabled (not driven by the timer)
OC i = CC i P, OC i _EN = 0
OC i = OC i REF + polarity (OC i REF xor CC i P)
OC i _EN = 1
0
0
0
1
0
1
0
Output disabled (not driven by the timer)
OC i = OIS i , OC i _EN = 0
1 1
Off State (output enabled with inactive state)
OC i = OIS i , OCx_EN = 1
Note: The state of the external I/O pins connected to the OCx channels depends on the OCx channel state and the GPIO registers.
RM0031 Rev 15
RM0031 16-bit general purpose timers (TIM2, TIM3, TIM5)
20.5.23 Output idle state register (TIMx_OISR)
7
Address offset: 0x16
Reset value: 0x00
6 5 4 3
Reserved
2
OIS2 rw
1
Reserved
0
OIS1 rw
Bits 7:3 Reserved, must be kept cleared
Bit 2 OIS2 : Output idle state 2 (OC2 output)
Refer to OIS1 bit
Bit 1 Reserved, must be kept cleared
Bit 0 OIS1 : Output idle state 1 (OC1 output)
0: OC1 = 0 when MOE = 0
1: OC1 = 1 when MOE = 0
Note: This bit can no longer be modified as long as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in the TIMx_BKR register).
20.5.24 TIMx register map and reset values
7
Table 72. TIMx register map
6 5 4
Address offset
Register name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
TIMx_CR1
Reset value
TIMx_CR2
Reset value
TIMx_SMCR
Reset value
TIMx_ETR
Reset value
TIMx_DER
Reset value
TIMx_IER
Reset value
TIMx_SR1
Reset value
TIMx_SR2
Reset value
TIMx_EGR
Reset value
-
0
-
0
-
0
-
0
-
0
CMS0
0
MMS1
0
TS1
0
ETPS1
0
TIF
0
-
0
-
0
TIE
0
TG
0
CMS1
0
MMS2
0
TS2
0
ECE
0
BIF
0
-
0
-
0
BIE
0
BG
0
ARPE
0
TI1S
0
MSM
0
ETP
0
-
0
-
0
-
0
-
0
-
0
DIR
0
MMS0
0
TS0
0
ETPS0
0
3
-
0
-
0
-
0
-
0
-
0
OPM
0
CCDS
0
-
0
EFT3
0
2 1
CC2DE
0
CC2IE
0
CC2IF
0
CC2OF
0
CC2G
0
URS
0
-
0
SMS2
0
EFT2
0
CC1DE
0
CC1IE
0
CC1IF
0
CC1OF
0
CC1G
0
UDIS
0
-
0
SMS1
0
EFT1
0
0
UDE
0
UIE
0
UIF
0
-
0
UG
0
CEN
0
-
0
SMS0
0
EFT0
0
RM0031 Rev 15
417
16-bit general purpose timers (TIM2, TIM3, TIM5) RM0031
Table 72. TIMx register map (continued)
Address offset
Register name
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
TIMx_CCMR1
(output mode)
Reset value
TIMx_CCMR1
(input mode)
Reset value
TIMx_ CCMR2
(output mode)
Reset value
TIMx_CCMR2
(input mode)
Reset value
TIMx_CCER1
Reset value
TIMx_CNTRH
Reset value
TIMx_CNTRL
Reset value
TIMx_PSCR
Reset value
TIMx_ARRH
Reset value
TIMx_ARRL
Reset value
TIMx_CCR1H
Reset value
TIMx_CCR1L
Reset value
TIMx_CCR2H
Reset value
TIMx_CCR2L
Reset value
TIMx_BKR
Reset value
TIMx_OISR
Reset value
7 6 5 4 3 2
-
0
IC1F3
0
-
0
IC2F3
0
-
0
CNT14
0
CNT6
0
-
0
ARR14
1
ARR6
1
CCR114
0
CCR16
0
CCR214
0
CCR26
0
AOE
0
OIS4
0
0
-
0
CNT15
0
CNT7
0
-
0
ARR15
1
ARR7
1
CCR115
0
CCR17
0
CCR215
0
CCR27
0
MOE
0
-
0
OC1M2
0
IC1F2
0
OC2M2
0
IC2F2
OC1M1
0
IC1F1
0
OC2M1
0
IC2F1
OC1M0
0
IC1F0
0
OC2M0
0
IC2F0
0
CC2E
0
CNT12
0
CNT4
0
-
0
ARR12
1
ARR4
1
CCR112
0
CCR14
0
CCR212
0
CCR24
0
BKE
0
OIS3
0
0
CC2P
0
CNT13
0
CNT5
0
-
0
ARR13
1
ARR5
1
CCR113
0
CCR15
0
CCR213
0
CCR25
0
BKP
0
OIS3N
0
OC1PE OC1FE
0
IC1PSC1
0
IC1PSC0
0
OC2PE
0
OC2FE
0
IC2PSC1
0
IC2PSC0
0
-
0
CNT10
0
CNT2
0
PSC2
0
ARR10
1
ARR2
1
CCR110
0
CCR12
0
CCR210
0
CCR22
0
OSSI
0
OIS2
0
0
-
0
CNT11
0
CNT3
0
-
0
ARR11
1
ARR3
1
CCR111
0
CCR13
0
CCR211
0
CCR23
0
OSSR
0
OIS2N
0
1
CC1S1
0
CC1S1
0
CC2S1
0
CC2S1
PSC1
0
ARR9
1
ARR1
1
CCR19
0
0
CC1P
0
CNT9
0
CNT1
0
CCR11
0
CCR29
0
CCR21
0
LOCK
0
OIS1N
0
0
CC1S0
0
CC1S0
0
CC2S0
0
CC2S0
PSC0
0
ARR8
1
ARR0
1
CCR18
0
0
CC1E
0
CNT8
0
CNT0
0
CCR10
0
CCR28
0
CCR20
0
LOCK
0
OIS1
0
RM0031 Rev 15
RM0031
21 8-bit basic timer (TIM4)
8-bit basic timer (TIM4)
The timer consists of an 8-bit auto-reload up-counter driven by a programmable prescaler. It can be used for time base generation, with interrupt generation on timer overflow.
Refer to Section 19.3 on page 294
for the general description of the timer features.
Figure 126. TIM4 block diagram f
SYSCLK
TRGO from TIM5 (ITR0)
TRGO from TIM1 (ITR1)
TRGO from TIM3 (ITR2)
TRGO from TIM2 (ITR3)
ITR = TRC= TRGI
TGI
CLOCK/TRIGGER CONTROLLER TIM4_TRGO
To other timers and DA
Legend:
Reg
Preload registers transferred to shadow registers on update event ( UEV) control bit according to event interrupt
TIME BASE UNIT
CK_PSC
Prescaler
UEV Auto-reload register
Stop or Clear
CK_CNT
UP-COUNTER
UEV
UIF
21.2 TIM4 main features
The main features include:
• 8-bit auto-reload up counter
• 4-bit programmable prescaler which allows dividing (also “on the fly”) the counter clock frequency by any power of 2 from 1 to 32768.
• Interrupt generation
– On counter update: Counter overflow
– On trigger input
• DMA request generation
– On counter update: Counter overflow
21.3 TIM4interrupts
The timer has 2 interrupt request sources:
• Update interrupt (overflow, counter initialization)
• Trigger input
RM0031 Rev 15
417
8-bit basic timer (TIM4) RM0031
21.4 TIM4 clock selection
The clock source for the timer is the internal clock (f
SYSCLK
). It is connected directly to the
CK_PSC clock that feeds the prescaler driving the counter clock CK_CNT.
Prescaler
The prescaler implementation is as follows:
• The TIM4 prescaler is based on a 16-bit counter controlled through a 4-bit register (in
TIM4_PSCR register). It can be changed on the fly as this control register is buffered. It can divide the counter clock frequency by any power of 2 from 1 to 32768.
The counter clock frequency is calculated as follows: f
CK_CNT
= f
CK_PSC
/2 (PSCR[3:0])
The prescaler value is loaded through a preload register. The shadow register, which contains the current value to be used, is loaded as soon as the LS byte has been written.
Read operations to the TIM_PSCR registers access the preload registers, so no special care needs to be taken to read them.
21.5 TIM4 registers
21.5.1 Control register 1 (TIM4_CR1)
7
ARPE rw
Address offset: 0x00
Reset value: 0x00
6 5
Reserved r
4 3
OPM rw
2
URS rw
1
UDIS rw
Bit 7 ARPE : Auto-reload preload enable
0: TIM4_ARR register is not buffered through a preload register. It can be written directly
1: TIM4_ARR register is buffered through a preload register
Bits 6:4 Reserved, must be kept cleared
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit)
0
CEN rw
RM0031 Rev 15
RM0031 8-bit basic timer (TIM4)
Bit 2 URS : Update request source
0: When enabled, an update interrupt request is sent as soon as registers are updated (counter overflow).
1: When enabled, an update interrupt request is sent only when the counter reaches the overflow/underflow.
Bit 1 UDIS : Update disable
0: A UEV is generated as soon as a counter overflow occurs or a software update is generated.
Buffered registers are then loaded with their preload values.
1: A UEV is not generated, shadow registers keep their value (ARR, PSC). The counter and the prescaler are re-initialized if the UG bit is set.
Bit 0 CEN : Counter enable
0: Counter disable
1: Counter enable
RM0031 Rev 15
417
8-bit basic timer (TIM4) RM0031
21.5.2 Control register 2 (TIM4_CR2)
7
Reserved r
Address offset: 0x01
Reset value: 0x00
6 5
MMS[2:0] rw rw
4 rw
3 2 1 0
Reserved r
Bit 7 Reserved, must be kept cleared
Bits 6:4 MMS[2:0] : Master mode selection
These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIM4_EGR register is used as a trigger output (TRGO). If the reset is generated by the trigger input (clock/trigger mode controller configured in trigger reset mode), the signal on the TRGO is delayed compared to the actual reset.
001: Enable - the counter enable signal is used as a trigger output (TRGO). It is used to start several timers at the same time or to control a window in which a slave timer is enabled. The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in gated mode. When the counter enable signal is controlled by the trigger input, there is a delay on
TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIM4_SMCR register).
010: Update - The update event is selected as trigger output (TRGO)
011: Reserved
100: Reserved
101: Reserved
111: Reserved
Bits 3:0 Reserved, must be kept cleared
7
MSM rw
Address offset: 0x02
Reset value: 0x00
6 5
TS[2:0] rw rw
4 rw
3
Reserved r
2 rw
1
SMS[2:0] rw
0 rw
RM0031 Rev 15
RM0031 8-bit basic timer (TIM4)
Bit 7 MSM : Master/slave mode
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between timers (through TRGO).
Bits 6:4 TS[2:0] : Trigger selection
This bit field selects the trigger input to be used to synchronize the counter.
000: Internal trigger ITR0 connected to TIM5 TRGO
001: Internal trigger ITR1 connected to TIM1 TRGO
010: Internal trigger ITR2 connected to TIM35 TRGO
011: Internal trigger ITR3 connected to TIM2 TRGO
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid wrong edge detections at the transition.
Bit 3 Reserved.
Bits 2:0 SMS[2:0] :Clock/trigger/slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and control register description).
000: Clock/trigger controller disabled - If CEN = 1, the prescaler is clocked directly by the internal clock.
001: Reserved
010: Reserved
011: Reserved
100: Trigger reset mode - The rising edge of the selected trigger signal (TRGI) reinitializes the counter and generates an update of the registers.
101: Gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
RM0031 Rev 15
417
8-bit basic timer (TIM4) RM0031
Address offset:
0x03
Reset value: 0x00
7 6 5 4
Reserved
3 2 1 0
UDE rw
Bits 7:1 Reserved, always read as 0.
Bit 0 UDE
0: Update DMA request disabled
1: Update DMA request enabled
Note: The conditions for generating a DMA request on the UEV are the same as for setting the UIF bit (in the TIM4_SR1 register). In particular, the DMA request depends on the URS bit (in the
TIM4_CR1 register).
RM0031 Rev 15
RM0031 8-bit basic timer (TIM4)
7
Reserved r
Address offset: 0x04
Reset value: 0x00
6
TIE rw
5
Bit 7 Reserved, must be kept cleared
Bit 6 TIE : Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bits 5:1 Reserved, must be kept cleared
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
4 3
Reserved r
2 1 0
UIE rw
21.5.6 Status register 1 (TIM4_SR)
7
Reserved
Address offset: 0x05
Reset value: 0x00
6
TIF
5 rc_w0
4 3
Reserved
2 1 0
UIF rc_w0
Bit 7 Reserved, must be kept cleared
Bit 6 TIF : Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI signal, both edges in case gated mode is selected). It is cleared by software.
0: No trigger event has occurred
1: Trigger interrupt pending
Bits 5:1 Reserved, must be kept cleared
Bit 0 UIF : Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update has occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow if UDIS = 0 in the TIM4_CR1 register
– When CNT is re-initialized by software using the UG bit in the TIM4_EGR register, if URS = 0 and UDIS = 0 in the TIM4_CR1 register.
RM0031 Rev 15
417
8-bit basic timer (TIM4) RM0031
7
Reserved
Address offset: 0x06
Reset value: 0x00
6
TG w
5 4 3
Reserved
2 1
Bit 7 Reserved, must be kept cleared
Bit 6 TG : Trigger generation
This bit is set by software to generate an event. It is automatically cleared by hardware.
0: No action
1: The TIF flag is set in TIM4_SR1 register. An interrupt is generated if enabled by the TIE bit
Bits 5:1 Reserved, must be kept cleared
Bit 0 UG : Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. Note that the prescaler counter is also cleared.
0
UG w
Address offset: 0x07
Reset value: 0x00
6 5 7 4 rw
CNT[7:0]
3 rw
2 rw
1 0 rw rw rw
Bits 7:0 CNT[7:0] : Counter value rw rw
21.5.9 Prescaler register (TIM4_PSCR)
7
Address offset: 0x08
Reset value: 0x00
6 5 4 3 2 1 0
PSC[3:0]
Reserved rw rw rw rw
Bits 7:4 Reserved, must be kept cleared
Bits 3:0 PSC[3:0] : Prescaler value
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT
/ 2(PSC[3:0]).
is equal to f
CK_PSC
PSC contains the value which is loaded into the active prescaler register at each UEV (including when the counter is cleared through the UG bit of TIM4_EGR).
Consequently, a UEV must be generated so that a new prescaler value can be taken into account.
RM0031 Rev 15
RM0031
21.5.10 Auto-reload register (TIM4_ARR)
7
Address offset: 0x09
Reset value: 0xFF
6 5 4
ARR[7:0] rw rw rw rw
3 rw
Bits 7:0 ARR[7:0] : Auto-reload value
2 rw
8-bit basic timer (TIM4)
1 rw
0 rw
Address offset
Register name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
TIM4_CR1
Reset value
TIM4_CR2
Reset value
TIM4_SMCR
Reset value
TIM4_DER
Reset value
TIM4_IER
Reset value
TIM4_SR1
Reset value
TIM4_EGR
Reset value
TIM4_CNTR
Reset value
TIM4_PSCR
Reset value
TIM4_ARR
Reset value
7
Table 73. TIM4 register map
6 5 4 3
-
0
CNT7
0
-
0
-
0
ARPE
0
-
0
MSM
0
-
0
-
0
ARR7
1
TIE
0
TIF
0
TG
0
CNT6
0
-
0
MMS2
0
TS2
0
-
0
-
0
ARR6
1
-
0
CNT5
0
-
0
-
0
-
0
MMS1
0
TS1
0
-
0
-
0
ARR5
1
-
0
CNT4
0
-
0
-
0
-
0
MMS0
0
TS0
0
-
0
-
0
ARR4
1
-
0
CNT3
0
-
0
-
0
-
0
-
0
OPM
0
-
0
PSC3
0
ARR3
1
1
-
0
CNT1
0
-
0
-
0
UDIS
0
-
0
SMS1
0
-
0
PSC1
0
ARR1
1
2
-
0
CNT2
0
-
0
-
0
URS
0
-
0
SMS2
0
-
0
PSC2
0
ARR2
1
0
UIE
0
UIF
0
UG
0
CNT0
0
CEN
0
-
0
SMS0
0
UDE
0
PSC0
0
ARR0
1
RM0031 Rev 15
417
Infrared (IRTIM) interface
22 Infrared (IRTIM) interface
RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
An infrared interface (IRTIM) can be used with an IR LED to perform remote control functions.
To generate the infrared remote control signals, the IR interface must be enabled and TIM2 channel 1 (TIM2_OC1) and TIM3 channel 1 (TIM3_OC1) must be properly configured to generate correct waveforms.
Figure 127. IR internal hardware connections with TIM2 and TIM3
All standard IR pulse modulation modes can be obtained by programming the two timer output compare channels.
TIM 2 is used to generate the high frequency carrier signal, while TIM3 generates the modulation envelope.
The infrared function is output on the IR_TIM pin. The activation of this function is done through the IR_CR register. When the IR function is enabled by setting the IR_EN bit, the standard TIM2_CC1 and TIM3_CC1 become automatically inactive (these pins may be used as general purpose I/O pins or for other alternate functions).
The high sink LED driver capability (only available on the IR_TIM pin) can be activated through the HS_EN bit in the IR_CR register and used to sink the high current needed to directly control an infrared LED. When the pin is driving the LED in this mode, the other pin input/output levels cannot be guaranteed. It is therefore recommended to program all other device I/Os in input mode without interrupt before sending any infrared signal. The previous function can be restored immediately after the infrared communication is completed.
When the high sink capability of the pin is not used (or the current is limited to the standard
I/O capabilities) all other pins of the device can be used normally.
RM0031 Rev 15
RM0031 Infrared (IRTIM) interface
22.3.1 Control register (IR_CR)
7
Reserved rw
Reset value: 0x00
6
Reserved rw
5
Reserved rw
4
Reserved rw
3
Reserved rw
2
Reserved rw
1
HS_EN rw
Bits 7:2 Reserved. Must be kept cleared
Bit 1 HS_EN : High Sink LED driver capability enable.
0: High Sink LED driver capability disabled.
1: High Sink LED driver capability enabled.
When activated, this pin can sink 20 mA min. with a power supply down to 2 V.
Bit 0 IR_EN : Infrared output enable.
This bit enables the IR output.
0: IR_TIM output disabled.
1: IR_TIM output enabled and provided to PA0 (TIM2 and TIM3 must have been previously configured properly by software)
0
IR_EN rw
Address offset
0x00
Register name
IR_CR
Reset value
♥
7
-
0
-
0
6
Table 74. IR register map
5 4 3
-
0
-
0
-
0
2
-
0
1 0
HS_EN
0
IR_EN
0
RM0031 Rev 15
419
Beeper (BEEP) RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
This Beeper module is used to generate a BEEP signal in the range of 1, 2 or 4 kHz. The
Beeper clock is derived from the LSE or LSI clock. The clock is selected by programming the CLKBEEPSEL[1:0] bits in the Clock BEEP register (CLK_CBEEPR).
Figure 128. BEEP block diagram
LSI
LSE
BEEPCLK
CLKBEEPSEL[1:0]
MSR to Timer input capture
(for measurement)
BEEPDIV[4:0] bits BEEPSEL[1:0] bits
BEEPCLK
5-BIT BEEPER PROG
COUNTER
~8 kHz
3-BIT COUNTER
BEEPEN
1 kHz, 2 kHz, 4 kHz
BEEP pin
RM0031 Rev 15
RM0031 Beeper (BEEP)
Note:
To use the BEEP function, perform the following steps in order:
1.
Calibrate the LSI clock frequency as described in Section 23.2.2: Beeper calibration
to define BEEPDIV[4:0] value.
2. Select 1 kHz, 2 kHz or 4 kHz output frequency by writing to the BEEPSEL[1:0] bits in the
BEEP control/status register 2 (BEEP_CSR2) .
3. Set the BEEPEN bit in the BEEP control/status register 2 (BEEP_CSR2) to enable the
LS clock source.
The prescaler counter starts to count only if BEEPDIV[4:0] value is different from its reset value, 0x1F.
Note:
This procedure can be used to calibrate the LS clock sources in order to reach the standard frequency output, 1 kHz, 2 kHz or 4 kHz.
Use the following procedure:
1.
Disable the BEEP clock by resetting the CLKBEEPSEL bit in the CLK_CBEEPR register.
2. Measure the LSI clock frequency (refer to
Section 23.2.3: LSI clock frequency measurement )
This step is performed when the beeper is clocked by the LSI clock source.
3. Calculate the BEEP
DIV value as follows, where A and x are the integer and fractional part of BEEPCLK/8 (in kHz):
BEEP
DIV
= A-2 when x is less than or equal to A/(1+2*A), else
BEEP
DIV
= A-1
4. Write the resulting BEEP
DIV
register 2 (BEEP_CSR2) . value in the BEEPDIV[4:0] bits in the BEEP control/status
23.2.3 LSI clock frequency measurement
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator after RC factory trimming is 38 kHz on the whole temperature range. To obtain a precise beeper output, the exact LSI frequency has to be measured.
Use the following procedure:
1.
Set the MSR bit in the
BEEP control/status register 1 (BEEP_CSR1)
to connect the LSI clock internally to ICAP1 of the TIM2 timer.
2. Measure the frequency of LSI clock using the Timer input capture interrupt.
RM0031 Rev 15
423
Beeper (BEEP) RM0031
Address offset: 0x00
Reset value: 0x00
6 5 7 4
Reserved
3 2 1 0
MSR rw
Bits 7:1 Reserved, must be kept cleared.
Bit 0 MSR : Measurement enable
This bit connects the BEEPCLK to the TIM2 channel 1 input capture. This allows the timer to be used to measure the LSI frequency (f
LSI
).
0: Measurement disabled
1: Measurement enabled
7 rw
Address offset: 0x03
Reset value: 0x1F
BEEPSEL[1:0]
6 rw
5
BEEPEN rw
4 rw
3 rw
2
BEEPDIV[4:0] rw
1 rw
0 rw
Bits 7:6 BEEPSEL[1:0] : BEEP selection
These bits are set and cleared by software to select 1, 2 or 4 kHz BEEP output when calibration is done.
00: BEEPCLK/(8 x BEEP
DIV
01: BEEPCLK/(4 x BEEP
DIV
1x: BEEPCLK/(2 x BEEP
DIV
) kHz output
) kHz output
) kHz output
Bit 5 BEEPEN : BEEP enable
This bit is set and cleared by software to enable the BEEP feature.
0: BEEP disabled
1: BEEP enabled
Note: Before enabling or disabling the BEEP feature, the BEEP clock must be disabled by resetting the CLKBEEPSEL[1:0] bits in the CLK_CBEEPR register .
Bits 4:0 BEEPDIV[4:0] : BEEP prescaler divider
These bits are set and cleared by software to define the beeper prescaler dividing factor BEEP
DIV
0x00: BEEP
DIV
0x01: BEEP
...
DIV
= 2
= 3
.
0x0E: BEEP
DIV
0x0F: BEEP
DIV
....
= 16
= 17
0x1E: BEEP
DIV
= 32
Note: This register must not be kept at its reset value (0x1F)
RM0031 Rev 15
RM0031 Beeper (BEEP)
Address offset
Register name
BEEP_CSR1 0x00
0x01 to
0x02
0x03 BEEP_CSR2
7
Table 75. BEEP register map
6 5 4 3 2 1 0
-
0
-
0
-
0
Reserved
-
0
-
0
-
0
-
0
MSR
0
BEEPSEL2
0
BEEPSEL1
0
BEEPEN
0
BEEPDIV4
1
BEEPDIV3
1
BEEPDIV2
1
BEEPDIV1
1
BEEPDIV0
1
RM0031 Rev 15
423
Real-time clock (RTC) RM0031
This section applies to low-density STM8L05xx/STM8L15xx devices, medium-density
STM8L05xx/STM8L15xx devices, medium+ density STM8L05xx/STM8L15xx devices and high-density STM8L05xx/STM8L15xx/STM8L16xx devices, unless otherwise specified.
The real-time clock (RTC) is an independent BCD timer/counter. It provides a time-of-day clock and calendar with an associated programmable alarm. The RTC also includes an auto wakeup unit useful for managing low-power modes.
8-bit registers contain seconds, minutes, hours (12 or 24 hour format), day (day of the week), date (day of the month), month, and year, coded in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format on low, medium+ and highdensity devices only. The adjustment for 28-, 29- (leap year), 30-, and 31-day months is performed automatically.
Additional 8-bit registers contain the programmable alarm subseconds (low, medium+ and high-density devices only), seconds, minutes, hours, day, and date.
Low, medium+ and high-density devices also allow to calibrate the RTC with a resolution of
0.954 ppm.
After reset, the RTC registers are protected against possible parasitic write accesses.
As long as the supply voltage is maintained in the operating range, the RTC never stops, regardless of the MCU status (Run mode, low power mode or under reset).
RM0031 Rev 15
RM0031 Real-time clock (RTC)
24.2 RTC main features
The RTC unit main features are the following ones (see Figure 130: RTC block diagram
and Figure 131: RTC block diagram (medium+ and high-density devices) ):
• A calendar with subseconds (low, medium+ and high-density devices only), seconds, minutes, hours (12 or 24 format), day (day of the week), date (day of the month), month, and year.
• Daylight saving time adjustment by software.
• A programmable alarm with interrupt (alarm A) . The alarm can be triggered by any combination of the calendar fields.
• An auto wake up unit providing periodic flag triggering an automatic wakeup interrupt.
• Five maskable interrupt/events:
– Alarm A
– Wakeup interrupt
– 3 tamper detections
• Accurate synchronization with an external clock using the subsecond shift feature (on low, medium+ and high-density devices).
• Digital calibration with an accuracy of 0.954 ppm (on low, medium+ and high-density devices).
• Three tamper inputs with configurable filter and internal pull-up to wake up the CPU
(available on low, medium+ and high-density devices only).
• Alternate function outputs:
– RTC_CALIB output: configurable 512 Hz clock output or 1 Hz clock output on low, medium+ and high-density devices (with RTC clock at 32.768 kHz).
– RTC_ALARM output: alarm A or wakeup flag can be routed to this output.
24.3 RTC functional description
The RTC unit is controlled by a set of 8-bit registers accessible in read or write mode. For
more information, refer to Section 24.6: RTC registers
.
In this section:
• RTC_CRx stands for RTC_CR1 / RTC_CR2 / RTC_CR3,
• RTC_SSRx for RTC_SSRH/RTC_SSRL,
• RTC_TRx for RTC_TR1 / RTC_TR2 / RTC_TR3,
• RTC_DRx for RTC_DR1 / RTC_DR2 / RTC_DR3,
• RTC_ALRMARx for RTC_ALRMAR1 / RTC_ALRMAR2 / RTC_ALRMAR3 /
RTC_ALRMAR4,
• RTC_ALRMASSRx for RTC_ALRMASSRH/RTC_ALRMASSRL,
• RTC_SHIFTRx for RTC_SHIFTRH/RTC_SHIFTRL,
• RTC_CALRx for RTC_CALRH/RTC_CALRL,
• RTC_TCRx for RTC_TCR1/RTC_TCR2
RM0031 Rev 15
460
Real-time clock (RTC) RM0031
24.3.1 Clock and prescalers
Note:
The RTC clock source (RTCCLK) used for timer/counter is selected through the clock controller. It can be either the HSE, LSE, HSI or LSI clock. For more information about the
RTC clock source configuration, please refer to Section 9.9: RTC and LCD clock .
A clock security system on LSE is implemented on low, medium+ and high-density devices to monitor the low speed external clock when it is used as the RTC clock source. For more
In order to access the RTC registers properly, the system clock frequency (f
SYSCLK equal to or greater than four times the f
RTCCLK behavior of the synchronization mechanism.
) must be
RTC clock frequency. This ensures a secure
When the system clock (SYSCLK) is equal to a low speed clock (like LSE or LSI), the user must use exactly the same clock as RTCCLK and must set the RATIO bit in the RTC_CR1 register to disable the synchronization mechanism. In these conditions, the RSF synchronization flag is meaningless.
A programmable prescaler stage generates a 1 Hz clock used to update the calendar. This
prescaler stage is split into 2 programmable prescalers ( Figure 130
):
• A 7-bit asynchronous prescaler configured through PREDIV_A bits of the RTC_APRER register
• A synchronous prescaler configured through PREDIV_S bits of the RTC_SPRERx registers. The prescaler features 13 bits for medium-density devices, and 15 bits for low, medium+ and high-density devices.
This division into two blocks (the asynchronous prescaler and the synchronous prescaler) has been defined to reach the lowest possible consumption.
It is recommended to keep a high value in the asynchronous prescaler when both prescalers are used to ensure the best consumption level.
The asynchronous prescaler division factor is consequently set by default to 128, and the synchronous division factor to 256, to get an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32768 Hz.
The minimum division factor is 2 on medium-density devices and 1 on low, medium+ and high-density devices. The maximum division factor is 2
20
on medium-density devices and
2
22
on low, medium+ and high-density devices. This corresponds to a maximum input frequency of around 1 MHz and 4 MHz respectively.
f
CK_SPRE
=
( f
RTCCLK
) ( PREDIV_A 1 )
Note:
The 1 Hz internal clock (ck_spre) is input to the calendar.
The ck_spre clock can also be used as a time base for the 16-bit wakeup auto-reload timer.
The 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler so as to reach short time-out periods. See
Section 24.3.4: Periodic auto-wakeup
for details.
RM0031 Rev 15
RM0031 Real-time clock (RTC)
HSE
HSI
LSE
LSI
RTC prescaler
RTCDIV[2:0]
RTCCLK
Figure 129. RTC block diagram (low-density devices)
PREDIV_A[5:0]
512 Hz clock output
1 Hz clock output
RTC_CR3 COSEL
Alarm
RTC_ALRMAx registers
RTC_CALIB pin
Asyn ch.
7-bit prescaler
PREDIV_A[6:0]
Smooth calib.
level
FCAL
Syn ch .
15-bit prescaler
PREDIV_S[14:0]
Calendar
Time
RTC_TRx registers
Date
RTC_DRx registers
=
Alarm A flag
RTC_CR2 OSEL[1:0]
RTC_ALARM pin
Prescaler
/2,4,8,16
WUCKSEL[1:0]
16-bit wakeup auto-reload timer
Periodic wakeup flag
WUCKSEL[2:0]
HSE
HSI
LSE
LSI
MS19200V2
Figure 130. RTC block diagram (medium-density devices)
512 Hz clock output
RTC prescaler
RTCCLK
RTCDIV[2:0]
PREDIV_A[5:0]
RTC_CALIB pin
Alarm
RTC_ALRMAx registers Asyn ch.
7-bit prescaler
PREDIV_A[6:0]
Syn ch .
13-bit prescaler
PREDIV_S[12:0]
Calendar
Time
RTC_TRx registers
Date
RTC_DRx registers
=
Alarm A flag
RTC_CR2 OSEL[1:0]
RTC_ALARM pin
Prescaler
/2,4,8,16
WUCKSEL[1:0]
WUCKSEL[2:0]
16-bit wakeup auto-reload timer
Periodic wakeup flag
MS15506V1
RM0031 Rev 15
460
Real-time clock (RTC)
Figure 131. RTC block diagram (medium+ and high-density devices)
RM0031
HSE
HSI
LSE
LSI
RTC prescaler
RTCDIV[2:0]
RTCCLK
PREDIV_A[5:0]
512 Hz clock output
1 Hz clock output
RTC_CR3 COSEL
RTC_CALIB pin
Asyn ch.
7-bit prescaler
PREDIV_A[6:0]
Smooth calib.
level f
CAL
Synch.
15-bit prescaler
PREDIV_S[14:0]
Alarm
RTC_ALRMAx registers
Sub-seconds
RTC_SSRx registers
Calendar
Time
RTC_TRx registers
Date
RTC_DRx registers
=
Alarm A flag
RTC_CR2 OSEL[1:0]
RTC_ALARM pin
16-bit wakeup auto-reload timer
Periodic wakeup flag
Tamper pull-up activation
AFI_TAMPER[3:1]
Prescaler
/2,4,8,16
WUCKSEL[1:0]
WUCKSEL[2:0]
Tamper filter 3 Tamperflags
MS19201V2
24.3.2 Real-time clock and calendar
Note:
The RTC calendar time and date registers are accessed through shadow registers synchronized with SYSCLK (system clock). In low, medium+ and high-density devices, they can also be accessed directly in order to avoid waiting for the synchronization duration.
• RTC_SSRx (subseconds) (available on low, medium+ and high-density devices only)
• RTC_TR1 (seconds)
• RTC_TR2 (minutes)
• RTC_TR3 (hours)
• RTC_DR1 (date)
• RTC_DR2 (day and month)
• RTC_DR3 (year)
The current calendar value is periodically copied into these shadow registers which are reset by system reset. The copy periodicity is the RTCCLK period. The RSF bit is set in the
RTC_ISR register each time the copy is performed .
The copy is not performed during Active-halt mode. When exiting Active-halt mode, the shadow registers are updated after up to one RTCCLK period.
When the user makes a read access to the calendar registers, he reads the content of the shadow registers. In low, medium+ and high-density devices, it is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR1 register. By default, this bit is cleared, and the user accesses the shadow registers.
RM0031 Rev 15
RM0031 Real-time clock (RTC)
The RTC provides a programmable alarm (alarm A). The programmable alarm function is enabled through the ALRAE bit in the RTC_CR2 register.
The ALRAF flag is set to 1 if the calendar subseconds ( low, medium+ and high-density devices only), seconds, minutes, hours and/or date match the value programmed in the
RTC_ALRMASSRx and RTC_ALRMARx alarm registers. The subseconds, seconds, minutes, hours and/or date can be independently selected or masked through the ALSSx and MSKx bits of the RTC_ALRMASSRx and RTC_ALRMARx registers.
The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR2 register. When enabled, the programmable alarm interrupt exits the device from Low power modes.
The alarm A flag signal can be routed to the RTC_ALARM device output when the
OSEL[1:0] bits in the RTC_CR3 register have the adequate value. The RTC_ALARM polarity can be configured through the POL bit in the RTC_CR3 register (see
A positive shift operation (see
Section 24.3.8: RTC synchronization (low, medium+ and high-density devices only)
) might cause an alarm to be missed if the subsecond field is compared (if MASKSS in RTC_ALRMASSMSKR is non-zero). Similarly, a negative shift operation might cause an alarm to be activated an extra time if the sub-second field is compared.
Caution: If the “seconds” field is masked (MSK1 bit set in RTC_ALRMAR1), the synchronous prescaler division factor set in the RTC_SPRER register must be at least 3 to ensure a correct behavior of the RTC.
The periodic wakeup flag is generated by a 16-bit programmable binary auto-reload down- counting timer. The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR2 register. The wakeup timer clock can be:
• RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE (32.768 kHz), it is possible to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61µs,
• ck_spre (usually 1 Hz internal clock). When ck_spre is 1 Hz, a wakeup time from 1 s to around 36 hours with one-second resolution can be achieved. This large programmable time range is divided in 2 parts:
– from 1s to 18 hours when WUCKSEL [2:1] = 10
– and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 2 16 is added to the 16-bit counter current value.
When the initialization sequence is completed (see
Section : Programming the auto-wakeup timer
), the wakeup timer starts down-counting. When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the
WUTF flag in the RTC_ISR2 register is set and the wakeup counter is automatically reloaded with its reload value (WUT register value).
The WUTF flag must then be reset by the software.
When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low power modes.
RM0031 Rev 15
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Real-time clock (RTC) RM0031
The periodic wakeup flag can be routed to the RTC_ALARM device output when the
OSEL[1:0] bits in the RTC_CR3 register have the adequate value. The RTC_ALARM polarity can be configured through the POL bit in the RTC_CR3 register (see
System reset as well as Run and Low power operating modes have no influence on the down-counting timer.
24.3.5 RTC initialization and configuration
Note:
RTC register write protection
By default, all the RTC registers (except the RTC_ISR2 register which contains the alarm and auto-wakeup timer interrupt source flags) are write-protected. Writing to the RTC registers is enabled by writing a key into the RTC_WPR write protection register.
The following steps are required to unlock the write protection of the RTC registers.
1.
Write ‘ 0xCA ’ into the RTC_WPR register
2. Write ’ into the RTC_WPR register
Writing a wrong key reactivates the write protection.
Calendar initialization and configuration
To program the initial time and date calendar values including the time format and potentially the prescaler setup, the following sequence is required:
1.
Set INIT bit to 1 in the RTC_ISR register to enter intialization mode. In this mode, the calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when
INITF is set to 1. It takes around 2 RTCCLK clock cycles for synchronization purposes.
3. To generate a 1 Hz clock for the calendar counter, program the prescaler register
(RTC_PRER).
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is completed, the subseconds value is also reinitialized, so that the next second increment can occur after a full second.
Note: 1 After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its power-on reset default value (0x00).
2 To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.
Daylight saving time
The daylight saving time management is performed through bits SUB1H, ADD1H, and BCK of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.
RM0031 Rev 15
RM0031
Note:
Real-time clock (RTC)
In addition, the software can use the BCK bit to memorize this operation.
Programming the alarm
Use the following procedure to program or update the programmable alarm (alarm A):
1.
Clear ALRAE in RTC_CR2 to disable alarm A.
2. Poll ALRAWF until it is set in RTC_ISR1 to make sure the access to alarm registers is allowed. On medium-density devices, it takes around 2 RTCCLK clock cycles (due to clock synchronization). On low, medium+ and high-density devices, ALRAWF is always set, so this step can be skipped.
3. Program alarm A registers: RTC_ALRMASSRx and RTC_ ALRMASSMSKR (on low, medium+ and high-density devices only) and RTC_ALRMARx.
4. Set ALRAE in RTC_CR2 to enable alarm A again.
5. On low, medium+ and high-density devices, after setting ALRAE to '1', the alarm effectively remains deactived for one additional ck_apre cycle. In other words, an alarm which is set to occur on the first sub-second update after enabling the alarm will be masked.
Each change in the RTC_CR2 register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization.
Programming the auto-wakeup timer
The following sequence is required to configure or change the wakeup timer reload value:
1.
Clear WUTE in RTC_CR2 to disable the wakeup timer.
2. Poll WUTWF until it is set in RTC_ISR1 to make sure the access to wakeup autoreload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. Program the value into the wakeup timer (RTC_WUTRL and RTC_WUTRH) and select the desired clock (WUCKSEL[2:0] bits in RTC_CR1).
4. Set WUTE in RTC_CR2 register to enable the timer again. The wakeup timer restarts down-counting.
• In medium-density devices, or when BYPSHAD is cleared:
In order to read the RTC calendar registers (RTC_SSRx, RTC_TRx and RTC_DRx) properly, the system clock frequency (f
SYSCLK times the f
RTCCLK synchronization mechanism.
) must be equal to or greater than four
RTC clock frequency. This ensures a secure behavior of the
The RSF bit is set in TRTC_ISR register each time the calendar registers are copied into the RTX_SSRx, RTC_TRx and RTC_DRx shadow registers. The copy is performed every RTCCLK cycle. To ensure the consistency between the values when the software reads the calendar, the update of all shadow registers (RTC_SSRL,
RTC_SSRH, RTC_TR1, RTC_TR2, RTC_TR3, RTC_DR1, RTC_DR2 and RTC_DR3) is frozen after RTC_SSRL (low, medium+ and high-density devices) or RTC_TR1
(medium-density devices) is read, and until RTC_DR3 is read. In low, medium+ and high-density devices, if the software does not need to read the sub-second values, it can first read RTC_TR1 and all the values are locked until RTC_DR3 is read.
In case the software makes read accesses to the calendar in a time interval smaller than 1 RTCCLK period: RSF must be cleared by software after the first calendar read,
RM0031 Rev 15
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Real-time clock (RTC) RM0031 and then the software must wait until RSF is set before reading again the calendar shadow registers.
After a low power mode wakeup, RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_TR and RTC_DR registers. The
RSF bit must be cleared after wakeup and not before entering low power mode.
Note: 1 After a system reset,the software must wait until RSF is set before reading the RTC_SSRx,
RTC_TRx and RTC_DRx registers. Indeed, a system reset resets the shadow registers to their default values.
2 After an initialization (refer to
Section : Calendar initialization and configuration
), or after a
): the software must wait until RSF is set before reading the
RTC_SSRx, RTC_TRx and RTC_DRx registers.
Note:
• In low, medium+ and high-density devices, when the BYPSHAD control bit in the
RTC_CR1 register is set to 1 (bypass shadow registers):
Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for RSF to be set. This is especially useful after exiting from Active-halt since the shadow registers are not updated during Active-halt mode.
When BYPSHAD is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct.
When BYPSHAD is set to 1, the instructions which read the calendar registers require one extra system cycle to complete.
The calendar shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx) and the RTC status registers (RTC_ISRx) are reset to their default value by all available system reset sources.
On the contrary, the RTC current calendar registers and control registers (RTC_CRx), the prescaler registers (RTC_SPREx and RTC_APRE), the wakeup timer registers
(RTC_WUTRx) and the alarm A registers (RTC_ALRMASSRx and RTC_ALRMARx) are reset to their default values by Power-on reset only. They are not affected by a system reset.
In addition, as soon as an RTC clock is enabled in the CLK_CRTCR clock controller register, the RTC continues to run under reset (if the reset source is other than the Power-on reset).
When power-on reset occurs, the RTC is stopped and all its registers are set to their reset values.
24.3.8 RTC synchronization (low, medium+ and high-density devices only)
On low, medium+ and high-density devices, the RTC can be synchronized to a remote clock with a high degree of precision. After reading the subsecond field (RTC_SSRx), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be finely adjusted to eliminate this offset by
“shifting” its clock by a fraction of a second using the RTC_SHIFTRx register.
RM0031 Rev 15
RM0031 Real-time clock (RTC)
Reading the RTC_SSRx registers gives the value of the synchronous prescaler counter.
This allows to calculate the exact RTC time down to a resolution of 1/(PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 µs with a
32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing the synchronous prescaler value means that the asynchronous prescaler value (PREDIV_A[6:0]) must be decreased to maintain the synchronous prescaler output at 1 Hz. As a result, the frequency of the asynchronous prescaler output increases, which may increase the RTC dynamic consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / ( PREDIV_S + 1) seconds.
The shift operation consists in adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this delays the clock. If at the same time ADD1S is set, this adds one second and at the same time substracts a fraction of second, so this advances the clock.
Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTRL register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed.
24.3.9 RTC smooth digital calibration (low, medium+ and high density devices only)
On low, medium+ and high-density devices, the RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from − 487.1 to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK clock cycles). These adjustments are fairly well distributed so that the
RTC is well calibrated even when observed over short periods of time.
The calibration is performed during a cycle of about 2
20
32 seconds when the input frequency is 32768 Hz.
RTCCLK clock cycles, or
The calibration registers (RTC_CALRx) specify the number of RTCCLK clock cycles to be masked during the 32-second cycle:
• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32second cycle.
• Setting CALM[1] to 1 causes two additional cycles to be masked
• Setting SMC[2] to 1 causes four additional cycles to be masked,
• and so on up to SMC[8] set to 1 which causes 256 clocks to be masked.
While the CALM bits allow to reduce the RTC frequency by up to 487.1 ppm with a fine resolution, the bit CALP of the RTC_CALRH register can be used to increase the frequency by 488.5 ppm. Setting this bit 1 effectively inserts an additional RTCCLK clock cycle every
2
11
RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle.
Using the CALM bits in conjunction with CALP, an offset ranging from − 511 to 512 RTCCLK cycles can be added during each 32-second cycle. This corresponds to a calibration range of − 487.1 to 488.5 ppm with a resolution of about 0.954 ppm.
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Real-time clock (RTC) RM0031
The formula to calculate the effective calibrated frequency (f
CAL
(f
RTCCLK
) is as follows:
) given the input frequency f
CAL
= f
RTCCLK
× ( 1 + ( CALP × 512 – CALM ) ⁄ ( 2
20
+ – × 512 ) )
Calibration when PREDIV_A<3
The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_APRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between − 255 and 256 clock pulses (corresponding to a calibration range from − 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows: f
CAL
= f
RTCCLK
× ( 1 + ( 256 CALM ) ⁄ ( 2
20
+ CALM 256 ) )
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz.
Verifying the RTC calibration
RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. However, for certain applications, standards require that the RTC precision be measured and verified on each device. An optional 1 Hz output is provided on low, medium+ and high-density devices to allow applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.
However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration.
• By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution).
• Alternatively, the CALW16 bit of the RTC_CALRH register can be set to 1 to force a 16second calibration cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the
RM0031 Rev 15
RM0031 Real-time clock (RTC) calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] and CALW16 can not be set to 1 simultaneously.
• To reduce the calibration cycle to 8 seconds, the CALW8 bit of the RTC_CALRH register can be set to 1. In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when
CALW8 is set to 1.
Re-calibration on-the-fly
The calibration registers (RTC_CALRH/RTC_CALRL) can be updated on-the-fly while
RTC_ISR1/INITF=0, by using the follow process:
1.
Poll the RTC_ISR1/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALRH,if necessary.
3. Write to the RTC_CALRL register. RECALPF is then automatically set to 1.
4. Within three ck_apre cycles after the write operation to RTC_CALRL, the new calibration settings take effect.
24.3.10 Tamper detection (low, medium+ and high-density devices only)
Note:
There are three tamper detection inputs. Each one is associated with a flag
TAMP1F/TAMP2F/ TAMP3F in the RTC_ISR2 register. Each input can be enabled by setting the corresponding TAMP1E/TAMP2E/TAMP3E bits to 1. The tamper detection control bits are available in the RTC_TCR1 and RTC_TCR2 registers.
By setting the TAMPIE bit in the RTC_TCR1 register, an interrupt is generated when a tamper detection event occurs. A tamper detection event is generated when either 2, 4, or 8 consecutive samples (depending on TAMPFLT bit) are observed at the level configured through the TAMPTRG bit.
The TAMPER inputs are pre-charged through the I/O internal resistance before its state is sampled, unless the pull-up is disabled by setting TAMPPUDIS to 1. The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper inputs.
The trade-off between tamper detection latency and any power consumption through the weak pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection.
Refer to the datasheets for the electrical characteristics of the pull-up resistors.
24.3.11 Calibration clock output
Note:
When the COE bit is set to 1 in the RTC_CR3 register, a reference clock is provided on the
RTC_CALIB device output. If the COSEL bit (bit 3 in the RTC_CR3 register) is reset and
PREDIV_A = 0x7F, the RTC_CALIB frequency is f
RTCCLK
/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz.
The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.
On low, medium+ and high-density devices, if COSEL is set and “PREDIV_S+1” is a nonzero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), RTC_CALIB frequency is f
RTCCLK
/(256 *
(PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768 kHz.
RM0031 Rev 15
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Real-time clock (RTC) RM0031
Two functions can be selected on Alarm output: ALRAF, and WUTF. They reflect the content of the corresponding flag registers. The OSEL[1:0] control bits in the RTC_CR3 register are used to activate and select the function which is output on RTC_ALARM. The polarity of the output is determined by the POL control bit in RTC_CR3: the opposite of the selected flag bit is output on RTC_ALARM when the POL bit is set to 1.
24.4 RTC low power modes
Table 76. Effect of low power modes on RTC
Mode Description
Low power wait/Wait
Active halt/Halt
No effect
RTC interrupts cause the device to exit from Wait mode.
The RTC remains active if its clock source is LSE or LSI. RTC interrupts can exit the device from Active-halt/Halt mode: alarm A interrupt, periodic
wakeup interrupt and the 3 tamper interrupts (see Section 24.5: RTC interrupts
).
Note: 1 The “Active-halt” mode is a low power mode where the CPU and the peripheral clocks are
stopped, except the RTC. It is described in Section 7: Low power modes on page 72
.
2 The RTC is designed to have a reduced consumption when clocked by LSE/LSI (refer to the
Electrical characteristics section in the device datasheet for more details).
The alarm A interrupt, the periodic wakeup interrupt and the 3 tamper interrupts share the same interrupt vector.
Alarm A
Interrupt event
Periodic wakeup (wakeup)
Tamper 1 event
Tamper 2 event
Tamper 3 event
Table 77. Interrupt control bits
Event flag
Enable control bit
Exit from Wait Exit from Halt
ALRAF
WUTF
TAMP1F
TAMP2F
TAMP3F
ALRAIE
WUTIE
TAMPIE
(RTC_TCR1)
1. Wakeup from Halt is possible only when the RTC clock source is LSE or LSI.
Yes
Yes
Yes
Yes
Yes
Yes
(1)
Yes
Yes
Yes
Yes
RM0031 Rev 15
RM0031 Real-time clock (RTC)
Refer to Section 5.1 on page 63 for a list of abbreviations used in register descriptions.
24.6.1 Time register 1 (RTC_TR1)
7
Reserved
RTC_TR1 is a calendar time shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x00
Reset value: 0x00
6 rw
5
ST[2:0] rw
4 rw
3 rw
2 rw
SU[3:0]
1 rw
0 rw
Bit 7 Reserved, always read as 0.
Bits 6:4 ST[2:0] : Second tens in BCD format
Bits 3:0 SU[3:0] : Second units in BCD format
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
24.6.2 Time register 2 (RTC_TR2)
7
Reserved
RTC_TR2 is a calendar time shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x01
Reset value: 0x00
6 rw
5
MNT[2:0] rw
4 rw
3 rw
2 rw
MNU[3:0]
1 rw
0 rw
Bit 7 Reserved, always read as 0.
Bits 6:4 MNT[2:0] : Minute tens in BCD format.
Bits 3:0 MNU[3:0] : Minute units in BCD format.
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
RM0031 Rev 15
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Real-time clock (RTC) RM0031
24.6.3 Time register 3 (RTC_TR3)
RTC_TR3 is a calendar time shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x02
Reset value: 0x00
7
Reserved
6
PM rw
5 rw
HT[1:0]
Bit 7 Reserved, always read as 0.
Bit 6 PM : AM/PM notation
0: AM or 24-hour format
1: PM
Bits 5:4 HT[1:0] : Hour tens in BCD format.
Bits 3:0 HU[3:0] : Hour units in BCD format.
4 rw
3 rw
2 rw
HU[3:0]
1 rw
0 rw
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
24.6.4 Date register 1 (RTC_DR1)
RTC_DR1 is a calendar date shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x04
Reset value: 0x01
7 6 5 4
DT[1:0]
Reserved rw
Bits 7:6 Reserved, always read as 0.
Bits 5:4 DT[1:0] : Date tens in BCD format
Bits 3:0 DU[3:0] : Date units in BCD format rw
3 rw
2 rw
DU[3:0]
1 rw
0 rw
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
RM0031 Rev 15
RM0031 Real-time clock (RTC)
24.6.5 Date register 2 (RTC_DR2)
RTC_DR2 is a calendar date shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x05
Reset value: 0x21
7 rw
6
WDU[2:0] rw
5 rw
Bits 7:5 WDU[2:0]: Week day units
000: forbidden.
001: Monday
...
111: Sunday
Bit 4 MT : Month tens in BCD format
Bits 3:0 MU[3:0] : Month units in BCD format
4
MT rw
3 rw
2 rw
MU[3:0]
1 rw
0 rw
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
24.6.6 Date register 3 (RTC_DR3)
RTC_DR3 is a calendar date shadow register. This register can be written in initialization
mode. Refer to Section : Calendar initialization and configuration on page 430 and
Section 24.3.6: Reading the calendar on page 431
.
Address offset: 0x06
Reset value: 0x00
7 6 5 4
YT[3:0] rw rw rw
Bits 7:4 YT[3:0]: Year tens in BCD format.
Bits 3:0 YU[3:0] : Year units in BCD format.
rw
3 rw
2 rw
YU[3:0]
1 rw
0 rw
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
RM0031 Rev 15
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Real-time clock (RTC) RM0031
Note:
The RTC_SSRH is available only on low, medium+ and high-density devices. Refer to
Section 24.3.6: Reading the calendar on page 431
for read procedures on this register.
Address offset: 0x17
Reset value: 0x00
7 6 5 4 r r r r
Bits 7:0 SS[15:8] : Sub second value upper bits
See RTC_SSRL for details.
SS[15:8]
3 r
2 r
1 r
0 r
This register is write protected. The write access procedure is described in
Section : RTC register write protection on page 430
Note:
The RTC_SSRL is available only on low, medium+ and high-density devices. Refer to
Section 24.3.6: Reading the calendar on page 431
for read procedures on this register.
Address offset: 0x18
Reset value: 0x00
7 6 5 4 3 2 1 0
SS[7:0] r r r r r r r r
Bits 7:0 SS[7:0] : Sub second value lower bits
SS[15:0] (in RTC_SSRH and RTC_SSRL registers) is the value of the synchronous prescaler's counter. The fraction of second is given by the formula below:
Second fraction = ( RTC_SPRE - SS) / (RTC_SPRE + 1)
Note: SS[15:0] can be larger than RTC_SPRE only after a shift operation. In this case, the correct time/date is one second less than indicated by RTC_TRx/RTC_DRx.
This register is write protected. The write access procedure is described in
Section : RTC register write protection on page 430
RM0031 Rev 15
RM0031 Real-time clock (RTC)
24.6.9 Control register 1 (RTC_CR1)
Address offset: 0x08
Power-on reset value: 0x00
Reset value: 0xXX (this register is not impacted by a system reset. It is reset at power-on).
7
Reserved
6
FMT rw
5
RATIO rw
4
BYPSHAD rw
3
Reserved
2 rw
1
WUCKSEL[2:0] rw
0 rw
Bit 7 Reserved, always read as 0.
Bit 6 FMT : Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 RATIO : System clock (SYSCLK) versus RTCCLK ratio
0: f
SYSCLK
≥ 2 x f
RTCCLK
must be respected
1: f
SYSCLK
= f
RTCCLK
Caution: The case where f
SYSCLK
is less than 2 f
RTCCLK and not equal to f
RTCCLK forbidden.
In order to perform a read access to the calendar registers (RTC_TRx, is
RTC_DRx and RTC_SSRx), f
SYSCLK
must be ≥ 4 x f
RTCCLK
when RATIO=0.
Bit 4 BYPSHAD : Bypass the shadow registers
This bit is available on low, medium+ and high-density devices only.
0: Calendar values (when reading from RTC_SSRx, RTC_TRx, and RTC_DRx) are taken from the shadow registers, which are updated once every RTCCLK cycle.
1: Calendar values (when reading from RTC_SSRx, RTC_TRx, and RTC_DRx) are taken directly from the calendar counters.
Bit 3 Reserved, always read as 0.
Bits 2:0 WUCKSEL[2:0] : Wakeup clock selection
000: RTCCLK/16 clock is selected
001: RTCCLK/8 clock is selected
010: RTCCLK/4 clock is selected
011: RTCCLK/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 2
16
is added to the WUT counter value (refer to the note below).
Note: Wakeup unit counter = WUT counter value (from 0x0000 up to 0xFFFF) + 0x10000 (added value when WUCKSEL[2:1]=”11”).
Bit 6 of this register can be written in initialization mode only when INITF bit is set to 1 in
RTC_ISR1.
Bits 2 to 0 of this register can be written only when WUTE bit is set to 0 in RTC_CR2 and
WUTWF is set to 1 in RTC_ISR1.
This register is write protected. The write access procedure is described in
Section : RTC register write protection .
RM0031 Rev 15
460
Real-time clock (RTC) RM0031
24.6.10 Control register 2 (RTC_CR2)
7
Reserved
Address offset: 0x09
Power-on reset value: 0x00
Reset value: 0xXX (this register is not impacted by a system reset. It is reset at power-on).
6
WUTIE rw
5
Reserved
4
ALRAIE rw
3
Reserved
2
WUTE rw
1
Reserved
0
ALRAE rw
Bit 7 Reserved, always read as 0.
Bit 6 WUTIE : Wakeup timer interrupt enable
0: Wakeup timer Interrupt disable
1: Wakeup Timer Interrupt enable
Bit 5 Reserved, always read as 0.
Bit 4 ALRAIE : Alarm A interrupt enable
0: Alarm A Interrupt disable
1: Alarm A Interrupt enable
Bit 3 Reserved, always read as 0.
Bit 2 WUTE : Wakeup timer enable
0: Wakeup timer disable
1: Wakeup timer enable
Bit 1 Reserved, always read as 0.
Bit 0 ALRAE : Alarm A enable
0: Alarm A disable
1: Alarm A enable
Note: This register is write protected. The write access procedure is described in
Section : RTC register write protection .
RM0031 Rev 15
RM0031 Real-time clock (RTC)
24.6.11 Control register 3 (RTC_CR3)
Address offset: 0x0A
Power-on reset value: 0x00
Reset value: 0xXX (this register is not impacted by a system reset. It is reset at power-on).
7
COE rw
6 rw
OSEL[1:0]
5 rw
4
POL rw
3
COSEL rw
2
BCK rw
1
SUB1H w
0
ADD1H w
Bit 7 COE Calibration output enable
This bit enables the RTC_CALIB device output
0: Calibration output disable
1: Calibration output enable
Bits 6:5 OSEL[1:0] : Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
00: Output disable
01: Alarm A output enable
10: Reserved
11: Wakeup output enable
Bit 4 POL : Output polarity
This bit is used to configure the polarity of RTC_ALARM device output
0: The RTC_ALARM pin is