ST STM32F10 Series Application Note
The ST STM32F10 Series is a powerful and versatile microcontroller that offers a wide range of features and potential use cases. With its high-performance ARM Cortex-M3 core, up to 1 Mbyte of Flash memory, and various peripherals, it is ideal for a wide range of applications, including industrial automation, medical devices, and consumer electronics. Whether you're looking to develop a complex control system, create a data acquisition device, or design a sophisticated user interface, the ST STM32F10 Series has the capabilities to meet your needs.
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November 2011
AN2586
Application note
Getting started with STM32F10xxx hardware development
Introduction
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the low-density value line, low-density, medium-density value line, medium-density, high-density, XL-density and connectivity line STM32F10xxx product families and describes the minimum hardware resources required to develop an
STM32F10xxx application.
Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes.
Glossary
●
●
●
●
●
●
●
●
Low-density value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 64 and 128 Kbytes.
Medium-density devices are STM32F100xx, STM32F101xx, STM32F102xx and
STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Doc ID 13675 Rev 7 www.st.com
1/28
Contents
Contents
AN2586
Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6
Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 12
External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 13
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 19
SWJ debug port connection with standard JTAG connector . . . . . . . . . 19
2/28 Doc ID 13675 Rev 7
AN2586
Contents
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SS
, V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 13675 Rev 7 3/28
List of tables
List of tables
AN2586
4/28 Doc ID 13675 Rev 7
AN2586
List of figures
List of figures
DD
/V
SS
pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 13675 Rev 7 5/28
Power supplies AN2586
1.1 Introduction
The device requires a 2.0 V to 3.6 V operating voltage supply (V
DD
). An embedded regulator is used to supply the internal 1.8 V digital power.
The real-time clock (RTC) and backup registers can be powered from the V
BAT
voltage when the main V
DD
supply is powered off.
Figure 1.
Power supply overview
Note:
1.1.1
(V
SSA
) V
REF–
(from 2.4 V up to V
DDA
) V
REF+
(V
DD
) V
DDA
(V
SS
) V
SSA
V
DDA
domain
A/D converter
Temp. sensor
Reset block
PLL
V
V
SS
DD
(V
DD
) V
BAT
V
DD
domain
I/O Ring
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
1.8 V domain
Core memories' digital
peripherals
Low voltage detector
Backup domain
LSE crystal 32 KHz oscillator
BKP registers
RCC BDCR register
RTC ai14863
V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
Independent A/D converter supply and reference voltage
●
●
To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB.
the ADC voltage supply input is available on a separate V an isolated supply ground connection is provided on the V
DDA
SSA
pin
pin
When available (depending on package), V
REF–
must be tied to V
SSA
.
On 100-pin and 144-pin packages
To ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage ADC input on V
REF+
. The voltage on V
REF+
may range from 2.4 V to
V
DDA
.
6/28 Doc ID 13675 Rev 7
AN2586 Power supplies
On packages with 64 pins or less
The V
REF+
and V
REF-
pins are not available, they are internally connected to the ADC voltage supply (V
DDA
) and ground (V
SSA
).
To retain the content of the Backup registers when V
DD is turned off, the V
BAT pin can be connected to an optional standby voltage supplied by a battery or another source.
The V
BAT
pin also powers the RTC unit, allowing the RTC to operate even when the main digital supply (V
DD
) is turned off. The switch to the V
BAT
supply is controlled by the power down reset (PDR) circuitry embedded in the Reset block.
If no external battery is used in the application, it is highly recommended to connect V
BAT externally to V
DD
.
1.2
The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes.
● in Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals)
●
● in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the contents of the registers and SRAM in Standby mode, the regulator is powered off. The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.
Power supply schemes
The circuit is powered by a stabilized power supply, V
DD
.
● Caution:
●
– If the ADC is used, the V
DD range is limited to 2.4 V to 3.6 V
– If the ADC is not used, the V
DD range is 2.0 V to 3.6 V
The V
DD
pins must be connected to V
DD
with external decoupling capacitors (one
100 nF Ceramic capacitor for each V
DD
pin + one Tantalum or Ceramic capacitor (min.
4.7 µF typ.10 µF).
● The V
BAT
pin can be connected to the external battery (1.8 V < V
BAT
< 3.6 V). If no external battery is used, it is recommended to connect this pin to V
DD
with a 100 nF external ceramic decoupling capacitor.
●
●
●
The V
DDA
pin must be connected to two external decoupling capacitors (100 nF
Ceramic + 1 µF Tantalum or Ceramic).
The V
REF+
pin can be connected to the V
DDA
external power supply. If a separate, external reference voltage is applied on V
REF+
, a 100 nF and a 1 µF capacitors must be connected on this pin. In all cases, V
REF+
must be kept between 2.4 V and V
DDA
.
Additional precautions can be taken to filter analog noise:
– V
DDA
can be connected to V
DD
through a ferrite bead.
– The V
REF+
pin can be connected to V
DDA
through a resistor (typ. 47 Ω ).
Doc ID 13675 Rev 7 7/28
Power supplies AN2586
Figure 2.
Power supply scheme
Battery
N × 100 nF
+ 1 × 10 µF
V
V
BAT
DD
V
BAT
STM32F10xxx
V
REF+
V
V
DD 1/2/3/.../N
SS 1/2/3/.../N
V
DDA
V
SSA
V
REF–
V
DD
100 nF + 1 µF
V
REF
100 nF + 1 µF
(note 1) ai14865b
1.
Optional. If a separate, external reference voltage is connected on V
REF+
1 µF) must be connected.
, the two capacitors (100 nF and
2.
V
REF
+ is either connected to V
DDA
or to V
REF
.
3.
N is the number of V
DD
and V
SS inputs.
1.3
1.3.1
Reset and power supply supervisor
Power on reset (POR) / power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from
2 V.
The device remains in the Reset mode as long as V
DD is below a specified threshold,
V
POR/PDR
, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics in the lowdensity, medium-density, high-density, XL-density, and connectivity line STM32F10xxx datasheets.
Figure 3.
Power on reset/power down reset waveform
V
DD
POR
PDR
40 mV hysteresis
Temporization t
RSTTEMPO
RESET ai14364
8/28 Doc ID 13675 Rev 7
AN2586 Power supplies
You can use the PVD to monitor the V
DD
power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate whether V
DD
is higher or lower than the PVD threshold. This event is internally connected to
EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V
DD
drops below the PVD threshold and/or when
V
DD
rises above the PVD threshold depending on the EXTI Line16 rising/falling edge configuration. As an example the service routine can perform emergency shutdown tasks.
Figure 4.
PVD thresholds
V
DD
PVD threshold
100 mV hysteresis
PVD output ai14365
A system reset sets all registers to their reset values except for the reset flags in the clock controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2. window watchdog end-of-count condition (WWDG reset)
3. Independent watchdog end-of-count condition (IWDG reset)
4. A software reset (SW reset)
5. Low-power management reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
Doc ID 13675 Rev 7 9/28
Power supplies AN2586
The STM32F1xx does not require an external reset circuit to power-up correctly. Only a pulldown capacitor is recommended to improve EMS performance by protecting the device against parasitic resets. See
.
Charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. The capacitor recommended value (100 nF) can be reduced to
10 nF to limit this power consumption;
Figure 5.
Reset circuit
%XTERNAL
RESETCIRCUIT
.234
6
$$
6
$$!
2
05
&ILTER
3YSTEMRESET
&
0ULSE
GENERATOR
MINS
77$'RESET
)7$'RESET
0OWERRESET
3OFTWARERESET
,OWPOWERMANAGEMENTRESET
AIC
10/28 Doc ID 13675 Rev 7
AN2586
2 Clocks
2.1
Clocks
●
●
●
Three different clock sources can be used to drive the system clock (SYSCLK):
HSI oscillator clock (high-speed internal clock signal)
HSE oscillator clock (high-speed external clock signal)
PLL clock
The devices have two secondary clock sources:
● 40 kHz low-speed internal RC (LSI RC) that drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby modes.
● 32.768 kHz low-speed external crystal (LSE crystal) that optionally drives the real-time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize the power consumption.
Refer to the STM32F10xxx or STM32F100xx reference manual (RM0008 or RM0041, respectively) for a description of the clock tree:
● RM0008 for STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/107xx microcontrollers
● RM0041 for STM32F100xx value line microcontrollers
HSE OSC clock
●
●
The high-speed external clock signal (HSE) can be generated from two possible clock sources:
HSE external crystal/ceramic resonator (see
HSE user external clock (see
Figure 6.
External clock
Hardware configuration
Figure 7.
Crystal/ceramic resonators
Hardware configuration
STM32F10xxx
OSC_IN OSC_OUT
OSC_IN OSC_OUT
R
EXT
(1)
(Hi-Z)
External source
C
L1
C
L2 ai14369 ai14370
1.
The value of R
EXT
depends on the crystal characteristics. Typical value is in the range of 5 to 6 R
S
(resonator series resistance).
2.
Load capacitance C
L
has the following formula: C
L
= C
L1
x C
L2
/ (C
L1
+ C
L2
) + C stray
where: C stray
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Please refer to
Section 5: Recommendations on page 20 to minimize its value.
Doc ID 13675 Rev 7 11/28
Clocks
2.1.1
AN2586
External source (HSE bypass)
●
●
In this mode, an external clock source must be provided.
It can have a frequency of up to:
● 24 MHz for STM32F100xx value line devices
25 MHz for STM32F101xx, STM32F102xx and STM32F103xx devices
50 MHz for connectivity line devices
The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance state (see
).
The external oscillator frequency ranges from:
●
●
●
4 to 16 MHz on STM32F101xx, STM32F102xx and STM32F103xx devices
4 to 24 MHz for STM32F100xx value line devices
3 to 25 MHz on connectivity line devices
The external oscillator has the advantage of producing a very accurate rate on the main
clock. The associated hardware configuration is shown in Figure 7
.
The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.
For C
L1
and C
L2 it is recommended to use high-quality ceramic capacitors in the 5 pF-to-
25 pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. C
L1
and C
L2, are usually the same value. The crystal manufacturer typically specifies a load capacitance that is the series combination of
C
L1
and C
L2
. The PCB and MCU pin capacitances must be included when sizing C
L1
and
C
L2
(10 pF can be used as a rough estimate of the combined pin and board capacitance).
Refer to the electrical characteristics sections in the datasheet of your product for more details.
12/28 Doc ID 13675 Rev 7
AN2586 Clocks
●
●
The low-speed external clock signal (LSE) can be generated from two possible clock sources:
LSE external crystal/ceramic resonator (see
LSE user external clock (see Figure 8
)
Figure 8.
External clock Figure 9.
Crystal/ceramic resonators
Hardware configuration
Hardware configuration
STM32F10xxx
OSC32_IN OSC32_OUT
OSC32_IN OSC32_OUT
R
EXT
(3)
External source
(Hi-Z) ai14371
C
L1
C
L2 ai14372c
Note: 1 “External clock” figure:
To avoid exceeding the maximum value of C
L1 to use a resonator with a load capacitance C
L
and C
L2
(15 pF) it is strongly recommended
≤
7 pF. Never use a resonator with a load capacitance of 12.5 pF
2 “External clock” and “crystal/ceramic resonators” figures:
OSC32_IN and OSC_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same application
3 “ Crystal/ceramic resonators” figure:
The value of R
EXT
depends on the crystal characteristics. A 0
Ω
resistor would work but would not be optimal. Typical value is in the range of 5 to 6 R
S
(resonator series resistance).
To fine tune R
S value refer to AN2867 - Oscillator design guide for ST microcontrollers.
2.2.1 External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see
).
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.
Doc ID 13675 Rev 7 13/28
Clocks
2.3
AN2586
Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
● If a failure is detected on the HSE oscillator clock, the oscillator is automatically disabled. A clock failure event is sent to the break input of the TIM1 advanced control timer and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The
CSSI is linked to the Cortex™-M3 NMI (non-maskable interrupt) exception vector.
● If the HSE oscillator is used directly or indirectly as the system clock (indirectly means that it is used as the PLL input clock, and the PLL clock is used as the system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
For details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference manuals available from the STMicroelectronics website www.st.com
.
14/28 Doc ID 13675 Rev 7
AN2586 Boot configuration
3.2
In the STM32F10xxx, three different boot modes can be selected by means of the
BOOT[1:0] pins as shown in
Table 1.
Boot modes
BOOT mode selection pins
BOOT1 BOOT0
Boot mode Aliasing x
0
1
0
1
1
Main Flash memory
System memory
Embedded SRAM
Main Flash memory is selected as boot space
System memory is selected as boot space
Embedded SRAM is selected as boot space
The values on the BOOT pins are latched on the 4 th
rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.
The BOOT pins are also resampled when exiting the Standby mode. Consequently, they must be kept in the required Boot mode configuration in the Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004.
Boot pin connection
shows the external connection required to select the boot memory of the
STM32F10xxx.
Figure 10.
Boot mode selection implementation example
STM32F10xxx
V
DD
10 k Ω
V
DD
10 k
Ω
BOOT0
BOOT1 ai14373
1.
Resistor values are given only as a typical example.
Doc ID 13675 Rev 7 15/28
Boot configuration
3.3
AN2586
Embedded boot loader mode
The Embedded boot loader mode is used to reprogram the Flash memory using one of the available serial interfaces:
● In low-density, low-density value line, medium-density, medium-density value line, and high-density devices, the boot loader is activated through the USART1 interface. For further details please refer to AN2606.
● In XL-density devices, the boot loader is activated through the USART1 or USART2
(remapped) interface. For further details please refer to AN2606.
● In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG
FS in Device mode (DFU: device firmware upgrade).
The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and
USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25
MHz clock (HSE) is present. For further details, please refer to AN2662.
This embedded boot loader is located in the System memory and is programmed by ST during production.
16/28 Doc ID 13675 Rev 7
AN2586 Debug management
4.1 Introduction
The Host/Target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
shows the connection of the host to the evaluation board (STM3210B-EVAL,
STM3210C-EVAL, STM32100B-EVAL or STM3210E-EVAL).
The Value line evaluation board (STM32100B-EVAL or STM32100E-EVAL) embeds the debug tools (ST-LINK). Consequently, it can be directly connected to the PC through a USB cable.
Figure 11.
Host-to-board connection
$EBUGTOOL
*4!'37CONNECTOR
(OST0#
%VALUATIONBOARD
0OWERSUPPLY
AIB
4.2
4.3
4.3.1
SWJ debug port (serial wire and JTAG)
The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is an
ARM® standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
● The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
● The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.
Pinout and debug port pins
The STM32F10xxx MCU is offered in various packages with different numbers of available pins. As a result, some functionality related to the pin availability may differ from one package to another.
SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in Table 2
, are available on all packages.
Doc ID 13675 Rev 7 17/28
Debug management
4.3.2
AN2586
Table 2.
JNTRST
Debug port pin assignment
JTAG debug port
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
Type Description
I
JTAG test mode selection
I JTAG test clock
I JTAG test data input
O JTAG test data output
I JTAG test nReset
SW debug port
Pin assignment
Type Debug assignment
I/O
Serial wire data input/output
-
I
-
Serial wire clock
PA13
PA14
PA15
-
-
TRACESWO if async trace
PB3 is enabled
PB4
Flexible SWJ-DP pin assignment
After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements a register to disable some part or all of the
SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This register is programmed by the user software program and not by the debugger host.
Table 3.
SWJ I/O pin availability
SWJ I/O pin assigned
Available Debug ports PA13 /
JTMS/
SWDIO
X
PA14 /
JTCK/
SWCLK
X
PA15 /
JTDI
PB3 /
JTDO
PB4/
JNTRST
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
X
X
X
X
Released
X
X
X
X
X
Table 3 shows the different possibilities to release some pins.
For more details, see the STM32F10xxx (RM0008) and STM32F100xx (RM0041) reference manuals, available from the STMicroelectronics website www.st.com
.
18/28 Doc ID 13675 Rev 7
AN2586
4.3.3
Note:
4.3.4
Debug management
Internal pull-up and pull-down resistors on JTAG pins
The JTAG input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops.
●
●
●
●
To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-up and pulldown resistors on JTAG input pins:
JNTRST: Internal pull-up
JTDI: Internal pull-up
JTMS/SWDIO: Internal pull-up
TCK/SWCLK: Internal pull-down
●
●
●
●
●
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
JNTRST: Input pull-up
JTDI: Input pull-up
JTMS/SWDIO: Input pull-up
JTCK/SWCLK: Input pull-down
JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but there is no special recommendation for TCK. However, for the STM32F10xxx , an integrated pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external resistors.
SWJ debug port connection with standard JTAG connector
shows the connection between the STM32F10xxx and a standard JTAG connector.
Figure 12.
JTAG connector implementation
V
DD
JTAG connector CN9
Connector 2 × 10
V
DD
STM32F10xxx nJTRST
JTDI
JSTM/SWDIO
JTCK/SWCLK
JTDO nRSTIN
10 k
Ω
(1) VTREF
(3) nTRST
(5) TDI
(7) TMS
(9) TCK
(11) RTCK
(13)TDO
(15) nSRST
(17) DBGRQ
(19) DBGACK
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
10 k Ω
10 k
Ω V
SS ai14376
Doc ID 13675 Rev 7 19/28
Recommendations
5 Recommendations
5.1
AN2586
Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V
SS
) and another dedicated to the V
DD
supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for ground and for the power supply.
5.3
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to reduce cross-coupling on the PCB, that is noisy, high-current circuits, low-voltage circuits, and digital components.
Ground and power supply (V
SS
, V
DD
)
Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. Loops must be avoided or have a minimum area.
The power supply should be implemented close to the ground line to minimize the area of the supply loop. This is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using singlelayer PCBs).
5.4 Decoupling
All power supply and ground pins must be properly connected to the power supplies. These connections, including pads, tracks and vias should have as low an impedance as possible.
This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors C
(100 nF) and a chemical capacitor C of about 10 µF connected in parallel on the
STM32F10xxx device. These capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but
exact values depend on the application needs. Figure 13 shows the typical layout of such a
V
DD
/V
SS
pair.
20/28 Doc ID 13675 Rev 7
AN2586
Figure 13.
Typical layout for V
DD
/V
SS
pair
Via to V
DD
Cap.
Via to V
SS
Recommendations
STM32F10xxx
V
DD
V
SS
5.6
●
●
When designing an application, the EMC performance can be improved by closely studying:
● Signals for which a temporary disturbance affects the running process permanently
(the case of interrupts and handshaking strobe signals, and not the case for LED commands).
For these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve EMC performance.
For digital signals, the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states.
Noisy signals (clock, etc.)
Sensitive signals (high impedance, etc.)
Unused I/Os and features
All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources.
To increase EMC performance, unused clocks, counters or I/Os, should not be left free, e.g.
I/Os should be set to “0” or “1”(pull-up or pull-down to the unused I/O pins.) and unused features should be “frozen” or disabled.
Doc ID 13675 Rev 7 21/28
Reference design AN2586
6.1 Description
The reference design shown in Figure 14 , is based on the STM32F103ZE(T6), a highly
integrated microcontroller running at 72 MHz, that combines the new Cortex
™
-M3 32-bit
RISC CPU core with 512 Kbytes of embedded Flash memory and up to 64 Kbytes of highspeed SRAM .
This reference design can be tailored to any other STM32F10xxx device with different
package, using the pins correspondence given in Table 6: Reference connection for all packages .
6.1.1 Clock
●
●
Two clock sources are used for the microcontroller:
LSE: X1– 32.768 kHz crystal for the embedded RTC
HSE: X2– 8 MHz crystal for the STM32F10xxx microcontroller
Refer to
Section 2: Clocks on page 11 .
6.1.2 Reset
The reset signal in
Figure 14 is active low. The reset sources include:
●
●
Reset button (B1)
Debugging tools via the connector CN1
Refer to
Section 1.3: Reset and power supply supervisor on page 8
.
Note:
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page 15 .
In low-power mode (more specially in Standby mode) the boot mode is mandatory to be able to connect to tools (the device should boot from the SRAM).
Note:
The reference design shows the connection between the STM32F10xxx and a standard
JTAG connector. Refer to
Section 4: Debug management on page 17
.
It is recommended to connect the reset pins so as to be able to reset the application from the tools.
Refer to
Section 1: Power supplies on page 6
.
22/28 Doc ID 13675 Rev 7
AN2586 Reference design
Table 4.
Mandatory components
Id Components name Reference
1 Microcontroller
2 Capacitors
3 Capacitor
STM32F103ZE(T6)
100 nF
10 µF
Quantity
1
11
1
Comments
144-pin package
Ceramic capacitors (decoupling capacitors)
Ceramic capacitor (decoupling capacitor)
Table 5.
Optional components
Id Components name Reference Quantity
1
2
3
4
5
6
7
8
9
10
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
Capacitor
Quartz
Quartz
JTAG connector
10 k
Ω
390
Ω
0
Ω
100 nF
1µF
10 pF
20 pF
8 MHz
32 kHz
HE10
5
1
1
1
1
1
3
2
2
2
Comments
Pull-up and pull-down for JTAG and Boot mode.
Used for HSE: the value depends on the crystal characteristics.
This resistor value is given only as a typical example.
Used for LSE: the value depends on the crystal characteristics.
This resistor value is given only as a typical example.
Ceramic capacitor
Used for VDDA and VREF.
Used for LSE: the value depends on the crystal characteristics.
Used for HSE: the value depends on the crystal characteristics.
Used for HSE
Used for LSE
11
12
13
Battery
Switch
Push-button
3V3
3V3
B1
1
2
1
If no external battery is used in the application, it is recommended to connect
V
BAT externally to V
DD
Used to select the correct boot mode.
Doc ID 13675 Rev 7 23/28
Reference design
Figure 14.
STM32F103ZE(T6) microcontroller reference schematic
AN2586
2
1
3
4
2
3 4
1
24/28
1.
If no external battery is used in the application, it is recommended to connect V
BAT
externally to V
DD
.
2.
To be able to reset the device from the tools this resistor has to be kept.
Doc ID 13675 Rev 7
AN2586 Reference design
Table 6.
Pin name
Reference connection for all packages
Pin numbers for LQFP packages
Pin numbers for
BGA packages
144 pins 100 pins 64 pins 48 pins 144 pins 100 pins
Pin numbers for
VFQFPN package
36 pins
F4
D3
G5
G6
F8
G7
F9
F5
H5
H6
G8
G10
E7
E6
A7
H7
G9
E5
G4
D2
D5
J5
F1
A12
A11
A10
A6
-
-
-
-
-
24
36
48
-
-
-
-
-
-
39
23
35
47
-
-
44
20
7
34
37
38
40
19
-
-
-
-
32
48
64
-
-
-
-
-
-
55
31
47
63
18
-
60
28
7
46
49
50
56
72
108
144
39
17
52
62
84
94
120
130
51
61
83
133
71
107
143
38
16
138
48
25
105
109
110
134
50
75
100
-
-
28
11
-
-
-
-
-
-
-
89
49
74
99
27
10
94
37
14
72
76
77
90
OSC_IN
OSC_OUT
PC15-
OSC32_OUT
PC14-
OSC32_IN
BOOT0
PB2-BOOT1
NRST
PA13
PA14
PA15
PB4
PB3
V
SS_9
V
SS_10
V
SS_11
V
DD_1
V
DD_2
V
DD_3
V
DD_4
V
DD_5
V
DD_6
V
DD_7
V
DD_8
V
SS_1
V
SS_2
V
SS_3
V
SS_4
V
SS_5
V
SS_6
V
SS_7
V
SS_8
23
24
9
8
12
13
9
8
5
6
4
3
5
6
4
3
D1
E1
C1
B1
C1
D1
B1
A1
A7
E7
E6
E5
E4
C2
D5
G5
E1
A10
A9
A8
A6
-
-
-
-
-
F7
F5
F4
D2
-
-
-
2
3
-
-
-
-
-
-
-
19
27
1
-
-
-
-
-
-
30
18
26
36
-
-
35
17
4
25
28
29
31
Doc ID 13675 Rev 7 25/28
Reference design AN2586
Table 6.
Pin name
Reference connection for all packages (continued)
Pin numbers for LQFP packages
Pin numbers for
BGA packages
144 pins 100 pins 64 pins 48 pins 144 pins 100 pins
Pin numbers for
VFQFPN package
36 pins
V
DD_9
V
DD_10
V
DD_11
V
REF+
V
REF-
V
SSA
V
DDA
V
BAT
95
121
131
32
31
30
33
6
21
20
19
22
6
-
-
-
12
13
-
-
1
-
-
-
8
9
-
-
1
-
-
-
F10
F7
F6
L1
K1
J1
M1
C2
J1
H1
G1
K1
B2
-
-
-
-
-
-
-
-
-
-
-
26/28 Doc ID 13675 Rev 7
AN2586 Revision history
Table 7.
Date
12-Jul-2007
23-May-2008
23-Jun-2009
01-Mar-2010
19-Oct-2010
14-Apr-2011
Document revision history
18-Nov-2011
Revision
1
2
3
4
5
6
7
Changes
Initial release.
Application note also applicable to High-density devices.
Figure 1: Power supply overview
,
and Figure 6: Clock overview updated.
Low-speed internal RC frequency modified in
Section 2: Clocks on page 11 . V
REF+
voltage range modified.
Table 6: Reference connection for all packages on page 25 added.
Small text changes.
Connectivity line STM32F10xxx and
added.
Section 1.2: Power supply schemes
and Figure 2: Power supply scheme
updated.
updated. Figure 6 Clock overview removed in
added
Note 3 updated below Figure 8:
Section 2.1.1: External source (HSE bypass)
and
Section 2.1.2: External crystal/ceramic resonator (HSE crystal)
updated.
Section 2.3 Clock-out capability section removed.
Section 3.1: Boot mode selection
and Section 3.3: Embedded boot loader mode updated.
When no external battery is used, it is recommended to externally connect the V
BAT
pin to V
DD
.
PA14 updated in
Table 7: Document revision history
.
Small text changes.
STM3210C-EVAL evaluation board added in
.
This application note also applies to STM32F100xx low- and medium-density value line products:
– low- and medium-density value line devices added to
–
Section 2.1.1: External source (HSE bypass) and Section 2.1.2:
External crystal/ceramic resonator (HSE crystal) updated
– reference to value line’s evaluation board added to Section 4.1:
Table 5: Reset circuit updated.
Modified
Section 2.2.1: External source (LSE bypass)
Updated for high-density value line devices.
Updated VDDA and VREF schematics in
STM32F103ZE(T6) microcontroller reference schematic on page 24
and Table 5: Optional components
.
Updated to include XL-density devices.
Doc ID 13675 Rev 7 27/28
AN2586
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28/28 Doc ID 13675 Rev 7

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