32” TFT SERVICE MANUAL (17MB08P)

32” TFT SERVICE MANUAL (17MB08P)
32” TFT
SERVICE MANUAL
(17MB08P)
RELEASE DATE:
04.03.2005
PREPARED BY:
VESTEL ELECTRONICS
THIS PAGE IS INTENTIONALLY LEFT BLANK
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
INTRODUCTION ...................................................................................................................................... 1
TUNER...................................................................................................................................................... 1
IF PART (TDA9886) ................................................................................................................................. 1
MULTI STANDARD SOUND PROCESSOR ............................................................................................ 2
VIDEO SWITCH TEA6415 ....................................................................................................................... 2
AUDIO AMPLIFIER STAGE WITH TPA3002D2 ...................................................................................... 2
POWER .................................................................................................................................................... 2
MICROCONTROLLER SDA55XX............................................................................................................ 3
8.1.
General Features............................................................................................................................... 3
8.2.
External Crystal and Programmable Clock Speed............................................................................ 3
8.3.
Microcontroller Features.................................................................................................................... 3
8.4.
Memory.............................................................................................................................................. 3
8.5.
Display Features................................................................................................................................ 3
8.6.
ROM Characters................................................................................................................................ 3
8.7.
Acquisition Features .......................................................................................................................... 4
8.8.
Ports .................................................................................................................................................. 4
9.
SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16 .................................................................. 4
10.
CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................... 4
11.
SAW FILTERS.......................................................................................................................................... 4
12.
IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ....................................................................... 5
12.1.
LM1117.............................................................................................................................................. 5
12.1.1.
General Description ................................................................................................................. 5
12.1.2.
Features .................................................................................................................................... 5
12.1.3.
Applications.............................................................................................................................. 5
12.1.4.
Connection Diagrams .............................................................................................................. 5
12.2.
LM2576.............................................................................................................................................. 6
12.2.1.
General Description ................................................................................................................. 6
12.2.2.
Features .................................................................................................................................... 6
12.2.3.
Pin description ......................................................................................................................... 6
12.3.
LM317T ............................................................................................................................................. 7
12.3.1.
Description................................................................................................................................ 7
12.3.2.
Features .................................................................................................................................... 7
12.4.
ST24LC21 ......................................................................................................................................... 8
12.4.1.
Description................................................................................................................................ 8
12.4.2.
Features .................................................................................................................................... 8
12.4.3.
Pin connections........................................................................................................................ 8
12.5.
TEA5114A ......................................................................................................................................... 9
12.5.1.
General description ................................................................................................................. 9
12.5.2.
Features .................................................................................................................................... 9
12.5.3.
Pin Connections ....................................................................................................................... 9
12.6.
TEA6415.......................................................................................................................................... 10
12.6.1.
General description ............................................................................................................... 10
12.6.2.
Features .................................................................................................................................. 10
12.6.3.
Pinning .................................................................................................................................... 10
12.7.
VPC3230D....................................................................................................................................... 11
12.7.1.
General Description ............................................................................................................... 11
12.7.2.
Pin Connections and Short Descriptions ............................................................................ 11
12.8.
SDA55XX (SDA5550)...................................................................................................................... 13
12.8.1.
General description ............................................................................................................... 13
12.9.
TPA3003D2 ..................................................................................................................................... 14
12.9.1.
General Description ............................................................................................................... 14
12.9.2.
Features .................................................................................................................................. 14
12.9.3.
Pin Connection ....................................................................................................................... 14
12.10. TDA9885/86 .................................................................................................................................... 15
12.10.1. General description ............................................................................................................... 15
12.10.2. Features .................................................................................................................................. 15
12.10.3. Pinning .................................................................................................................................... 15
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12.11. TDA1308 ......................................................................................................................................... 16
12.11.1. General Description ............................................................................................................... 16
12.11.2. Features .................................................................................................................................. 16
12.11.3. Pinning .................................................................................................................................... 16
12.12. PI5V330........................................................................................................................................... 17
12.12.1. General description ............................................................................................................... 17
12.12.2. Features .................................................................................................................................. 17
12.12.3. Pin Descriptions ..................................................................................................................... 17
12.13. GM6015........................................................................................................................................... 18
12.13.1. General description ............................................................................................................... 18
12.13.2. Features .................................................................................................................................. 18
12.14. AD9883A ......................................................................................................................................... 19
12.14.1. General description ............................................................................................................... 19
12.14.2. Features .................................................................................................................................. 19
12.14.3. Pin Descriptions ..................................................................................................................... 19
12.15. MC141585 ....................................................................................................................................... 22
12.15.1. General description ............................................................................................................... 22
12.15.2. Features .................................................................................................................................. 22
12.15.3. Pin Description ....................................................................................................................... 22
12.16. MC34063 ......................................................................................................................................... 24
12.16.1. Description.............................................................................................................................. 24
12.16.2. Features .................................................................................................................................. 24
12.16.3. Pin connections...................................................................................................................... 24
12.17. MSP34X0G (MSP3410G) ............................................................................................................... 25
12.17.1. Introduction ............................................................................................................................ 25
12.17.2. Features .................................................................................................................................. 25
12.17.3. Pin connections...................................................................................................................... 26
12.18. DS90C385 ....................................................................................................................................... 28
12.18.1. General Description ............................................................................................................... 28
12.18.2. Features .................................................................................................................................. 28
12.18.3. Pinning .................................................................................................................................... 28
12.19. NDS8947 ......................................................................................................................................... 29
12.19.1. General Description ............................................................................................................... 29
12.19.2. Features .................................................................................................................................. 29
13.
SERVICE MENU SETTINGS ................................................................................................................. 30
13.1.
ADJUST MENU SETTINGS............................................................................................................ 30
13.2.
OPTIONS MENU SETTINGS.......................................................................................................... 32
13.3.
APS WSS TEST MENU .................................................................................................................. 37
14.
BLOCK DIAGRAM.................................................................................................................................. 38
15.
CIRCUIT DIAGRAMS ............................................................................................................................. 39
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1. INTRODUCTION
32” TFT TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1366*768
panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour
standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM
stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8Ω speakers. The chassis is
equipped with many inputs and outputs allowing it to be used as a center of a media system.
It supports following peripherals:
2 SCART’s with all of them supporting full SCART features including RGB input
1 AV input. (CVBS+ Stereo Audio)
1 SVHS iput
1 Stereo Headphone output
1 D-Sub 15 PC input
1 DVI input (Optional)
1 Audio line out
1 Stereo audio input for PC/DVI
2. TUNER
As the thickness of the TV set has a limit, a horizontal mounted tuner is used in the product, which is
suitable for CCIR systems B/G, H, L, L’, I/I’, and D/K. The tuning is available through the digitally controlled
I2C bus (PLL). Below you will find info on the Tuner in use.
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF
output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyper band
5. Compact size
6. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1.
Gain control voltage (AGC)
2.
Tuning voltage
3.
I²C-bus address select
4.
I²C-bus serial clock
5.
I²C-bus serial data
6.
Not connected
7.
PLL supply voltage
8.
ADC input
9.
Tuner supply voltage
10.
Symmetrical IF output 1
11.
Symmetrical IF output 2
:
4.0V, Max: 4.5V
:
:
:
Max: 5.5V
Min:-0.3V, Max: 5.5V
Min:-0.3V, Max: 5.5V
:
5.0V, Min: 4.75V, Max: 5.5V
:
33V, Min: 30V, Max: 35V
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal
PLL demodulator for positive and negative modulation, including sound AM and FM processing.
The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO
and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier,
SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio
amplifier and mute time constant, I²C-bus transceivers and MAD (module address), Internal voltage stabilizer.
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4. MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a
single chip.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS)
signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC).
The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio
standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC
and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main
function of this device is to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of
the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is
switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a
normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are
changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same
input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3002D2
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3002D2 can drive stereo speakersas low as 8 Ω. The high efficiency of the TPA3002D2
eliminates the need for external heatsinks when playing music.
7. POWER
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient
design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving
a 3.0A load with excellent line and load regulation. Two different versions (one having a fixed output
voltage of 3.3 V, and one with 5.0 V) of this IC are used in the regulator board.
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8. MICROCONTROLLER SDA55XX
8.1. General Features
• Feature selection via special function register
• Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)
• Supply Voltage 2.5 and 3.3 V
• ROM version is used.
8.2. External Crystal and Programmable Clock Speed
• Single external 6MHz crystal, all necessary clocks are generated internally
• CPU clock speed selectable via special function registers.
• Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz
8.3. Microcontroller Features
• 8bit 8051 instruction set compatible CPU.
• 33.33-MHz internal clock (max.)
• 0.360 μs (min.) instruction cycle
• Two 16-bit timers
• Watchdog timer
• Capture compare timer for infrared remote control decoding
• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)
• ADC (4 channels, 8 bit)
• UART (rxd, txd)
8.4. Memory
• Up to 128 Kilobyte on Chip Program ROM
• Eight 16-bit data pointer registers (DPTR)
• 256-bytes on-chip Processor Internal RAM (IRAM)
• 128bytes extended stack memory.
• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX
• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;
- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)
- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software
- 3-Kilobyte Display Memory
8.5. Display Features
• ROM Character set supports all East and West European Languages in single device
• Mosaic Graphic Character Set
• Parallel Display Attributes
• Single/Double Width/Height of Characters
• Variable Flash Rate
• Programmable Screen Size (25 Rows x 33...64 Columns)
• Flexible Character Matrixes (HxV) 12 x 9...16
• Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters
in Enhanced Mode
• CLUT with up to 4096 colour combinations
• Up to 16 Colours per DRCS Character
• One out of 8 Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters
8.6. ROM Characters
• Shadowing
• Contrast Reduction
• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours
• Support of Progressive Scan and 100 Hz.
• 3 X 4Bits RGB-DACs On-Chip
• Free Programmable Pixel Clock from 10 MHz to 32MHz
• Pixel Clock Independent from CPU Clock
• Multinorm H/V-Display Synchronisation in Master or Slave Mode
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8.7. Acquisition Features
• Multistandard Digital Data Slicer
• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)
• Four Different Framing Codes Available
• Data Caption only limited by available Memory
• Programmable VBI-buffer
• Full Channel Data Slicing Supported
• Fully Digital Signal Processing
• Noise Measurement and Controlled Noise Compensation
• Attenuation Measurement and Compensation
• Group Delay Measurement and Compensation
• Exact Decoding of Echo Disturbed Signals
8.8. Ports
• One 8-bit I/O-port with open drain output and optional I 2 C Bus emulation support (Port0)
• Two 8-bit multifunction I/O-ports (Port1, Port3)
• One 4-bit port working as digital or analogue inputs for the ADC (Port2)
• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7)
• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)
9. SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16
The ST24C16 is a 16Kbit electrically erasable programmable memory (EEPROM), organised as 8 blocks
of 256*8 bits. The memory is compatible with the I²C standard, two wire serial interface, which uses a bidirectional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code
(1010) corresponding to the I²C bus definition. This is used together with 1 chip enable input (E) so that up
to 2*8K devices may be attached to the I²C bus and selected individually.
10. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The
device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio
applications.
11. SAW FILTERS
K3953M is an IF Filter for Video Applications. The package is SIP5K. Supported standards are B/G, D/K, I,
L/L’.
K9656M is an IF Filter for Audio Applications. The package is SIP5K. Supported standards are B/G, D/K, I,
L/L’.
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12. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
LM1117
LM2576
LM317T
ST24LC21
TEA5114A
TEA6415
VPC3230D
SDA55XX
TPA3002D2
TDA9886
TDA1308T
PI5V330
GM6015
AD9883A
MC141585
MC34063
MSP3410G
DS90C385
NDS8947
12.1. LM1117
12.1.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current.
It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in
an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external
resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223,
TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to
improve the transient response and stability.
12.1.2. Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
12.1.3. Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
12.1.4. Connection Diagrams
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12.2. LM2576
12.2.1. General Description
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient
design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving
a 3.0 A load with excellent line and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output
version. These regulators were designed to minimize the number of external components to simplify the
power supply design. Standard series of inductors optimized for use with the LM2576 are offered by
several different inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in
comparison with popular three–terminal linear regulators, especially with higher input voltages. In many
cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages
and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External
shutdown is included, featuring 80 mA (typical) standby current. The output switch includes cycle–by–cycle
current limiting, as well as
thermal shutdown for full protection under fault conditions.
12.2.2. Features
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
12.2.3. Pin description
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12.3. LM317T
12.3.1. Description
The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1.5
amps over an output range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use and
requires only two external resistors to set the output voltage. Further, it employs internal current limiting,
thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317 serves a
wide variety of applications including local, on card regulation. This device can also be used to make a
programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the
LM317 can be used as a precision current regulator.
12.3.2. Features
• Output Current in Excess of 1.5 A
• Output Adjustable between 1.2 V and 37 V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting Constant with Temperature
• Output Transistor Safe–Area Compensation
• Floating Operation for High Voltage Applications
• Available in Surface Mount D2PAK, and Standard 3–Lead Transistor Package
• Eliminates Stocking many Fixed Voltages
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12.4. ST24LC21
12.4.1. Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered,
the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal
applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal
applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power supply value as low
as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
12.4.2. Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
12.4.3. Pin connections
DIP Pin connections
CO Pin connections
NC: Not connected
Signal names
SDA
SCL
Vcc
Vss
VCLK
Serial data Address Input/Output
Serial Clock (I2C mode)
Supply voltage
Ground
Clock transmit only mode
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12.5. TEA5114A
12.5.1. General description
This integrated circuit provides RGB switching allowing connections between peri TV plug, internal RGB
generator and video processor in a TV set.
The input signal black level is tied to the same reference voltage on each input in order to have no
differential voltage when switching two RGB generators.
An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video
amplifier from saturation.
Fast blanking output is a logical OR between FB1 (Pin 8) and FB2 (Pin 10).
12.5.2. Features
• 25MHz Bandwidth
• Crosstalk : 55dB
• Short circuit to ground or VCC protected
• Anti saturation gain changing
• Video switching
12.5.3. Pin Connections
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12.6. TEA6415
12.6.1. General description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched
on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of
synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is
6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor
bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with
external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75Ω load
needs an external transistor. It is possible to have the same input connected to several outputs. The
starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16
bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to
determine one configuration.
12.6.2. Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
1.
2.
12.6.3. Pinning
Input
:
Data
:
3.
4.
Input
Clock
:
:
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Input
Input
Prog
Input
Vcc
Input
Input
Ground
Output :
Output :
Output :
Output :
Output :
Output :
Ground
Input
:
:
Max
: 2Vpp, Input Current: 1mA, Max : 3mA
Low level
: -0.3V Max: 1.5V,
High level
: 3.0V Max
: Vcc+0.5V
Max
: 2Vpp, Input Current: 1mA, Max
: 3mA
Low level
: -0.3V Max: 1.5V,
High level
: 3.0V Max
: Vcc+0.5V
Max
: 2Vpp, Input Current: 1mA, Max : 3mA
Max
: 2Vpp, Input Current: 1mA, Max : 3mA
:
:
:
:
Max
12V
Max
Max
: 2Vpp, Input Current: 1mA, Max: 3mA
: 2Vpp, Input Current: 1mA, Max : 3mA
: 2Vpp, Input Current: 1mA, Max : 3mA
5.5Vpp,
Min : 4.5Vpp
5.5Vpp,
Min : 4.5Vpp
5.5Vpp,
Min : 4.5Vpp
5.5Vpp,
Min : 4.5Vpp
5.5Vpp,
Min : 4.5Vpp
5.5Vpp, Min : 4.5Vpp
:
Max : 2Vpp, Input Current
: 1mA, Max
: 3mA
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12.7. VPC3230D
12.7.1. General Description
The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz
and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as
DDP 331x) and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface
• one 20.25-MHz crystal, few external components
• 80-pin PQFP package
12.7.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
Pin No.
PQFP
80-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Pin Name
Type
Connection
(if not used)
Short Description
B1/CB1IN
G1/Y1IN
R1/CR1IN
B2/CB2IN
G2/Y2IN
R2/CR2IN
ASGF
FFRSTWIN
VSUPCAP
VSUPD
GNDD
GNDCAP
SCL
SDA
RESQ
TEST
VGAV
YCOEQ
FFIE
FFWE
FFRSTW
FFRE
FFOE
CLK20
GNDPA
VSUPPA
LLC2
LLC1
VSUPLLC
IN
IN
IN
IN
IN
IN
VREF
VREF
VREF
VREF
VREF
VREF
X
LV or GNDD
X
X
X
X
X
X
X
GNDD
GNDD
GNDD
LV
LV
LV
LV
LV
LV
X
X
LV
LV
X
Blue1/Cb1 Analog Component Input
Green1/Y1 Analog Component Input
Read1/Cr1 Analog Component Input
Blue2/Cb2 Analog Component Input
Green2/Y2 Analog Component Input
Read2/Cr2 Analog Component Input
Analog Shield GNDF
FIFO Reset Write Input
Digital Decoupling Circuitry Supply Voltage
Supply Voltage, Digital Circuitry
Ground, Digital Circuitry
Digital Decoupling Circuitry GND
I2C Bus Clock
I2C Bus Data
Reset Input, Active Low
Test Pin, connect to GNDD
VGAV Input
Y/C Output Enable Input, Active Low
FIFO Input Enable
FIFO Write Enable
FIFO Reset Write/Read
FIFO Read Enable
FIFO Output Enable
Main Clock output 20.25 MHz
Pad Decoupling Circuitry GND
Pad Decoupling Circuitry Supply Voltage
Double Clock Output
Clock Output
Supply Voltage, LLC Circuitry
IN
OUT
SUPPLYD
SUPPLYD
OUT
IN/OUT
IN/OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN/OUT
OUT
OUT
OUT
IN/OUT
SUPPLYD
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30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
GNDLLC
Y7
Y6
Y5
Y4
GNDY
VSUPY
Y3
Y2
Y1
Y0
C7
C6
C5
C4
VSUPC
GNDC
C3
C2
C1
C0
GNDSY
VSUPSY
INTLC
AVO
FSY/HC/HSYA
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
OUT
SUPPLYD
SUPPLYD
OUT
OUT
OUT
X
GNDY
GNDY
GNDY
GNDY
X
X
GNDY
GNDY
GNDY
GNDY
GNDC
GNDC
GNDC
GNDC
X
X
GNDC
GNDC
GNDC
GNDC
X
X
LV
LV
LV
56
57
58
MSY/HS
VS
FPDAT/VSYA
IN/OUT
OUT
IN/OUT
LV
LV
LV
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VSTBYY
CLK5
NC
XTAL1
XTAL2
ASGF
GNDF
VRT
I2CSEL
ISGND
VSUPF
VOUT
CIN
VIN1
VIN2
VIN3
VIN4
VSUPAI
GNDAI
VREF
SUPPLYA
OUT
IN
OUT
SUPPLYA
OUTPUT
IN
SUPPLYA
SUPPLYA
OUT
IN
IN
IN
IN
IN
SUPPLYA
SUPPLYA
OUTPUT
X
LV
LV or GNDD
X
X
X
X
X
X
X
X
LV
LV
VRT
VRT
VRT
VRT
X
X
X
79
80
FB1IN
AISGND
IN
SUPPLYA
VREF
X
Ground, LLC Circuitry
Picture Bus Luma (MSB)
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Ground, Luma Output Circuitry
Supply Voltage, Luma Output Circuitry
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma
Picture Bus Luma (LSB)
Picture Bus Chroma (MSB)
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Supply Voltage, Chroma Output Circuitry
Ground, Chroma Output Circuitry
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma
Picture Bus Chroma (LSB)
Ground Sync Pad Circuitry
Supply Voltage, Sync Pad Circuitry
Interlace Output
Active Video Output
Front Sync/ Horizontal Clamp Pulse/Front-End
Horizontal Sync Output
Main Sync/Horizontal Sync Pulse
Vertical Sync Pulse
Front End/Back-End Data/Front-End Vertical Sync
Output
Standby Supply Voltage
CCU 5 MHz Clock Output
Not Connected
Analog Crystal Input
Analog Crystal Output
Analog Shield GNDF
Ground, Analog Front-End
Reference Voltage Top, Analog
I2C Bus Address Select
Signal Ground for Analog Input, connect to GNDF
Supply Voltage, Analog Front-End
Analog Video Output
Chroma/Analog Video 5 Input
Video 1 Analog Input
Video 2 Analog Input
Video 3 Analog Input
Video 4 Analog Input
Supply Voltage, Analog Component Inputs Front-End
Ground, Analog Component Inputs Front-End
Reference Voltage Top, Analog Component Inputs
Front-End
Fast Blank Input
Signal Ground for Analog Component Inputs, connect
to GNDAI
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12.8. SDA55XX (SDA5550)
12.8.1. General description
The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video
Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data
used for PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and
decoding. The device provides an integrated general-purpose, fully 8051-compatible Microcontroller with
television specific hardware features. Microcontroller has been enhanced to provide powerful features such
as memory banking, data pointers, and additional interrupts etc. The on-chip display unit for displaying
Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists
of up to16 Kbytes. Device has an internal ROM of up to 128 KBytes. ROMless versions can access up to 1
MByte of external RAM and ROM. The SDA 55XX supports a wide range of standards including PAL,
NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed Caption, an accelerating
acquisition hardware module, a display generator for Level 1.5 TTX data and powerful On screen Display
capabilities based on parallel attributes, and Pixel oriented characters (DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of
the internal TTX acquisition processing, transfers data to/from external memory interface and receives/
transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX
data in a VBI buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming
and parity-checks, page search and evaluation of header control bits) once per field. Additionally, the
firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The
interface to user software is optimized for minimal overhead. SDA 55XX is realized in 0.25 micron
technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and hardware
development environment (TEAM) is available to simplify and speed up the development of the software
and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the TV controller
software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
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12.9. TPA3003D2
12.9.1. General Description
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3002D2 can drive stereo speakers as low as 8 &. The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks when playing music.
12.9.2. Features
- 9-W/Ch Into an 8-Ω Load From 12-V Supply
- Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
- 32-Step DC Volume Control From –40 dB to 36 dB
- Line Outputs For External Headphone
- Amplifier With Volume Control
- Regulated 5-V Supply Output for Powering TPA6110A2
- Space-Saving, Thermally-Enhanced PowerPAD Packaging
- Thermal and Short-Circuit Protection
12.9.3. Pin Connection
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12.10. TDA9885/86
12.10.1. General description
The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL
demodulator for positive and negative modulation including sound AM and FM processing.
Both devices can be used for TV, VTR, PC and set-top box applications.
12.10.2. Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good
intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all
negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal
oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative
modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits
via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance
single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
12.10.3. Pinning
SYMBOL
VIF1
VIF2
OP1
FMPLL
DEEM
AFD
DGND
AUD
TOP
SDA
SCL
SIOMA
n.c.
TAGC
REF
VAGC
CVBS
AGND
VPLL
VP
AFC
OP2
SIF1
SIF2
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION
VIF differential input 1
VIF differential input 2
output 1 (open-collector)
FM-PLL for loop filter
de-emphasis output for capacitor
AF decoupling input for capacitor
digital ground
audio output
tuner AGC TakeOver Point (TOP)
I2C-bus data input/output
I2C-bus clock input
sound intercarrier output and MAD select
not connected
tuner AGC output
4 MHz crystal or reference input
VIF-AGC for capacitor; (Not connected for TDA9885)
video output
analog ground
VIF-PLL for loop filter
supply voltage (+5 V)
AFC output
output 2 (open-collector)
SIF differential input 1
SIF differential input 2
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12.11. TDA1308
12.11.1. General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable
digital audio applications.
12.11.2. Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
12.11.3. Pinning
SYMBOL
OUTA
INA(neg)
INA(pos)
VSS
INB(pos)
INB(neg)
OUTB
VDD
PIN
1
2
3
4
5
6
7
8
DESCRIPTION
Output A (Voltage swing)
Inverting input A
Non-inverting input A
Negative supply
Non-inverting input B
Inverting input B
Output B (Voltage swing)
Positive supply
PIN VALUE
Min : 0.75V, Max : 4.25V
Vo(clip) : Min : 1400mVrms
2.5V
0V
2.5V
Vo(clip) : Min : 1400mVrms
Min : 0.75V, Max : 4.25V
5V, Min : 3.0V, Max : 7.0V
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12.12. PI5V330
12.12.1. General description
Pericom Semiconductor’s PI5V series of mixed signal video circuits are produced in the Company’s
advanced CMOS low-power technology, achieving industry leading performance.
The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is recommended for both
RGB and composite video switching applications. The VideoSwitch™ can be driven from a current output
RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also this device has
exceptionally high current capability which is far greater than most
analog switches offered today. A single 5V supply is all that is required for operation.
The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The
application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
12.12.2. Features
• High-performance, low-cost solution to switch between video sources
• Wide bandwidth: 200 MHz
• Low ON-resistance: 3W
• Low crosstalk at 10 MHz: –58 dB
• Ultra-low quiescent power (0.1 µA typical)
• Single supply operation: +5.0V
• Fast switching: 10 ns
• High-current output: 100 mA
• Packages available:
– 16-pin 300-mil wide plastic SOIC (S)
– 16-pin 150-mil wide plastic SOIC (W)
– 16-pin 150-mil wide plastic QSOP (Q)
12.12.3. Pin Descriptions
Pin Name
S1A, S2A
S1B, S2B
S1C, S2C
S1D, S2D
IN
EN
DA, DB,
D C, D D
GND
VCC
Description
Analog Video I/O
Select Input
Enable
Analog Video I/O
Ground
Power
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12.13. GM6015
12.13.1. General description
The Genesis Microchip 6015RD1 LCD TV reference board is a complete display processor for LCD, PDP
and LCOS based televisions. The reference board demonstrates the processing capabilities of the Genesis
Microchip gm6015 television controller IC. The gm6015 IC is a full-featured, dual-channel video processor
with Genesis industry leading Crystal Ciema PlusTM video scan conversion. The 6015RD1 board inputs
analog YPbPr/RGB, NTSC/PAL/SECAM CVBS/YC, UHF/VHF and outputs digital RGB to an XGA LCD
panel. A convenient on-screen display system provides easy control of the board’s processing capabilities.
The design kit is complete with hardware and software. Software includes G-Probe debug software, GWizard register calculator and G-TV application source code.
The 6015RD1 is a related reference board that outputs analog YpbPr/RGB.
12.13.2. Features
• Dual channel, gm6015 based LCD TV system
• Industry leading Crystal Cinema Plus video scan conversion
• Inputs:
i.
Component analog YPbPr/RGB
480/576I, 480/576P, 720P and 1080I HD
ii.
Dual NTSC/PAL/SECAM CVBS and YC
iii.
VGA, SVGA, XGA PC graphics
iv.
Separate, composite or sync on Y/G
v.
vi.
UHF/VHF RF (NTSC)
• Default output with XGA LCD interface PCB:
i.
Component analog YpbPr/RGB
• Other outputs:
ii.
8/16/20/24-bit 4:2:2/4:4:4 digital YCbCr/RGB
480/576I, 480/576P, 720P and 1080I HD
iii.
VGA, SVGA, XGA PC graphics
iv.
Separate, composite or sync on Y/G
v.
• On-screen display (OSD) user interface with automated self running demonstration
• Small form factor PCB
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12.14. AD9883A
12.14.1. General description
The AD9883A is a complete 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB
graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full
power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and
COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies
range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST
signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A
also offers full sync processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This
interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP
surface-mount plastic package and is specified over the 0C to 70C temperature range.
12.14.2. Features
• 140 MSPS Maximum Conversion Rate
• 300 MHz Analog Bandwidth
• 0.5 V to 1.0 V Analog Input Range
• 500 ps p-p PLL Clock Jitter at 110 MSPS
• 3.3 V Power Supply
• Full Sync Processing
• Sync Detect for “ Plugging ”
• Midscale Clamping
• Power-Down Mode
• Low Power:500 mW Typical
• 4:2:2 Output Format Mode
12.14.3. Pin Descriptions
Pin Name
OUTPUTS
HSOUT
Function
VSOUT
Vertical Sync Output
A reconstructed and phase-aligned version of the video Vsync. The polarity of this
output can be controlled via a
serial bus bit. The placement and duration in all modes is set by the graphics
transmitter.
SOGOUT
Sync-On-Green Slicer Output
This pin outputs either the signal from the Sync-on-Green slicer comparator or an
unprocessed but delayed version
of the Hsync input.
(Note: Besides slicing off SOG, the output from this pin gets no other additional
processing on the AD9883A. Vsync separation is performed via the sync
separator.)
SERIAL PORT
(2-Wire)
SDA
SCL
A0
Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity
and duration of this output can be
programmed via serial bus registers. By maintaining alignment with DATACK and
Data, data timing with respect to
horizontal sync can always be determined.
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2Wire Serial Control Port section.
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DATA OUTPUTS
RED
GREEN
BLUE
DATA CLOCK OUTPUTS
DATACK
Data Output, RED Channel
Data Output, GREEN Channel
Data Output, BLUE Channel
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to
output is fixed. When the sampling
time is changed by adjusting the PHASE register, the output timing is shifted as
well. The DATACK and HSOUT
outputs are also moved, so the timing relationship among the signals is
maintained.
Data Output Clock
This is the main clock output signal used to strobe the output data and
HSOUT into external logic. It is produced by the internal clock generator
and is synchronous with the internal pixel sampling clock. When the
sampling time is changed by adjusting the PHASE register, the output
timing is shifted as well. The Data, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.
INPUTS
RAIN
GAIN
BAIN
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
High impedance inputs that accept the RED, GREEN, and BLUE channel graphics
signals, respectively. (The three channels are identical, and can be used for any
colors, but colors are assigned for convenient reference.) They accommodate input
signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to
these pins to support clamp operation.
HSYNC
Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference
and provides the frequency reference
for pixel clock generation. The logic sense of this pin is controlled by serial register
0Eh Bit 6 (Hsync Polarity). Only the leading edge of Hsync is active; the trailing
edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used.
When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt
trigger for noise immunity, with a nominal input threshold of 1.5 V.
VSYNC
Vertical Sync Input
This is the input for vertical sync.
SOGIN
Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync,
typically on the GREEN channel. The pin is connected to a high speed comparator
with an internally generated threshold. The threshold level can be programmed in
10 mV steps to any voltage between 10 mV and 330 mV above the negative peak
of the input signal. The default voltage threshold is 150 mV. When connected to an
ac-coupled graphics signal with embedded sync, it will produce a noninverting
digital output on SOGOUT. (This is usually a composite sync signal, containing
both vertical and horizontal sync information that must be separated before
passing the horizontal sync signal to Hsync.) When not used, this input should be
left unconnected. For more details on this function and how it should be
configured, refer to the Sync-on-Green section.
CLAMP
External Clamp Input
This logic input may be used to define the time during which the input signal is
clamped to ground. It should be exercised when the reference dc level is known to
be present on the analog input channels, typically during the back porch of the
graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to
1, (register 0FH, Bit 7, default is 0).
When disabled, this pin is ignored and the clamp timing is determined internally by
counting a delay and duration from the trailing edge of the Hsync input. The logic
sense of this pin is controlled by Clamp Polarity register 0FH, Bit 6. When not
used, this pin must be grounded and Clamp Function programmed to 0.
COAST
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing
with Hsync and continue producing a clock at its current frequency and phase. This
is useful when processing signals from sources that fail to produce horizontal sync
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pulses during the vertical interval. The COAST signal is generally not required for
PC-generated signals. The logic sense of this pin is controlled by Coast Polarity
(register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity
programmed to 1, or tied HIGH (to VD through a 10 k resistor) and Coast Polarity
programmed to 0. Coast Polarity defaults to 1 at power-up.
REF BYPASS
Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to
ground through a 0.1 µF capacitor. The absolute accuracy of this reference is ±4%,
and the temperature coefficient is ±50 ppm, which is adequate for most AD9883A
applications. If higher accuracy is required, an external reference may be
employed instead.
MIDSCV
Midscale Voltage Reference BYPASS
Bypass for the internal midscale voltage reference. It should be connected to
ground through a 0.1 µF capacitor. The exact voltage varies with the gain setting of
the BLUE channel.
FILT
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter.
Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize
noise and parasitics on this node.
POWER SUPPLY
VD
Main Power Supply
These pins supply power to the main elements of the circuit. They should be as
quiet and filtered as possible.
VDD
Digital Output Power Supply
A large number of output pins (up to 25) switching at high speed (up to 110 MHz)
generate a lot of power supply transients (noise). These supply pins are identified
separately from the VD pins so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9883A is interfacing with
lower voltage logic, VDD may be connected to a lower supply voltage (as low as
2.5 V) for compatibility.
VD
Clock Generator Power Supply
The most sensitive portion of the AD9883A is the clock generation circuitry. These
pins provide power to the clock PLL and help the user design for optimal
performance. The designer should provide “quiet,” noise-free power to these pins.
GND
Ground
The ground return for all circuitry on chip. It is recommended that the AD9883A be
assembled on a single solid ground plane, with careful attention to ground current
paths.
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12.15. MC141585
12.15.1. General description
This is a high performance HCMOS device designed to interface with a micro controller unit to allow
colored symbols or characters to be displayed onto a LCD monitor. Because of the large number of fonts,
512 fonts including 496 standard fonts and 16 multi-color fonts, LMOSD2-16 is suitable to be adopted for
the multi-language monitor application especially. It minimizes the MCU’s burden through its built-in RAM.
By storing a full screen of data and control information, this device has a capability to carry out ‘screenrefresh’ without any MCU supervision. Programmable hatch pattern generator is added for individual pixel
inspection.
Since there is no clearance between characters, special graphics oriented characters can be generated by
combining two or more character blocks. The full OSD menu is formed of 15 rows x 30 columns which can
by freely positioned on anywhere of the monitor screen by changing vertical or horizontal delay.
Special functions such as character background color, blinking, bordering or shadowing, four-level
windows with programmable size, row double height and double width, programmable vertical height of
character and row-to-row spacing, and full-screen erasing and Fade-In/Fade-Out are also incorporated.
There are 8 color selections for any individual character display with row intensity attribute and window
intensity attribute to expand the color mixture on OSD menu.
12.15.2. Features
• Totally 512 Fonts Including 496 Standard Fonts and 16 Multi-Color Fonts.
• 10x18 or 12x18 Font Matrix Selection
• Maximum Pixel CLK of 80MHz
• Maximum input resolution of 1580 dots/line (PIXin/HSYNC ratio)
• Wide Operating Frequency: max. 150KHz for Monitor
• Fully Programmable Character Array of 15 Rows by 30 Columns
• 8-Color Selection for Characters with Color Intensity Attribute on Each Row
• 7-Color Selection for Characters background
• True 16-Color Selection for Windows
• Shadowing on Windows with Programmable Shadow Width/Height/Color
• Fancy Fade-In/Fade-Out Effects
• Programmable Height of Character to Meet Multi-Sync Requirement
• Row To Row Spacing Control to Avoid Expansion Distortion
• Four Programmable Windows with Overlapping Capability
• Character Bordering or Shadowing
• Character/Symbol Blinking Function
• Programmable Vertical and Horizontal Positioning for Display Center
• M_BUS (IIC) Interface with Address $7A
12.15.3. Pin Description
Pin Assignment
VSS(Pin 1)
This is the ground pin for the chip.
PIXin (Pin 2)
This is the Pixel clock input for chip. The MC141585 chip is driven by this pixel clock for all the logics
inside.
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NC (Pin 3)
No connection.
VDD (Pin 4)
This is the +5V power pin for the chip.
HSYNC (Pin 5)
This pin inputs a horizontal synchronize signal. It is negative polarity by default. The leading edge of
HSYNC synchronizes its internal horizontal timing. The maximum input ratio between PIXin/HSYNC should
not greater than 1580 for displaying 12X18 font matrix. For displaying 10X18 font matrix, this ratio should
not greater than 1280.
RESET (Pin 6)
An active low signal will reset ROW15 and ROW16 control registers. Refer to Control Registers section for
default set-tings. A proper RC network have to be tighten to this pin to ensure the device initialize properly
during power up. Refer to the application diagram.
SDA (Pin 7)
Data and control message are being transmitted to this chip from a host MCU via M_bus systems. This
wire is configurated as a uni-directional data line. (Detailed description of protocols will be discussed in the
M_BUS section).
SCL (Pin 8)
A separate synchronizing clock input from the transmitter is required for M_Bus protocol. Data is read at
the rising edge of each clock signal.
VDD (Pin 9)
This is the power pin for the digital logic of the chip.
VSYNC (Pin 10)
Similar to Pin 5, this pin inputs a vertical synchronize signal to synchronize the vertical control circuit. It is
negative polarity by default.
VDD (I) (Pin 11)
This is the voltage supply of RGB outputs when low intensity of Windows/ROW is selected. The RBG
output level would be equal to VDD(I) in this case. Please refer to Row Attribute/Window registers for more
detail. The input voltage for this pin should be equal to or less than V DD (Pin 17) for normal operation.
FBKG (Pin 12)
This pin will output a logic high while displaying characters or windows. It is defaulted to high impedance
state after power on, or when there is no output. An external 10 κΩ resistor pulled low is recommended to
avoid level toggling caused by hand effect when there is no output.
B,G,R (Pin 13, 14, 15)
LMOSD2-16 color outputs in CMOS level to the host monitor. These three signals are open drain outputs if
3_STATE bit is set and the color intensity is inactive. Otherwise, they are active high push-pull outputs.
See “REGISTERS” for more information. These pins are in high impedance state after power on.
VSS (Pin 24)
This is the ground pin for the digital logic of the chip.
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12.16. MC34063
12.16.1. Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–
DC converters. These devices consist of an internal temperature compensated reference, comparator,
controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This
series was specifically designed to be incorporated in Step–Down and Step–Up and Voltage–Inverting
applications with a minimum number of external components.
12.16.2. Features
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference
12.16.3. Pin connections
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12.17. MSP34X0G (MSP3410G)
Multistandard Sound Processor Family
12.17.1. Introduction
The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a
single chip. Figure shows a simplified functional block diagram of the MSP 34x0G.
This new generation of TV sound processing ICs now includes versions for processing the multichannel
television sound (MTS) signal conforming to the standard recommended by the Broadcast Television
Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction
(MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex
standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures
in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo
performance without any adjustments.
All MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D. The MSP 34x0G
further simplifies controlling software. Standard selection requires a single I²C transmission only.
The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard
automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be
evaluated internally with subsequent switching between mono/stereo/bilingual; no I²C interaction is
necessary (Automatic Sound Selection).
Source Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle
(32 kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
12.17.2. Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
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• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard
12.17.3. Pin connections
NC = not connected; leave vacant
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS
Pin No.
Pin Name
Type
Connection
(if not used)
PLCC
68-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PSDIP
64-pin
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
PSDIP
52-pin
14
13
12
11
10
9
8
7
6
5
4
3
-
PQFP
80-pin
9
8
7
6
5
4
3
2
1
80
79
78
77
76
75
-
PLQFP
64-pin
8
7
6
5
4
3
2
1
64
63
62
61
60
59
58
-
ADR_WS
NC
ADR_DA
I2S_DA_IN1
I2S_DA_OUT
I2S_WS
I2S_CL
I2C_DA
I2C_CL
NC
STANDBYQ
ADR_SEL
D_CTR_I/O_0
D_CTR_I/O_1
NC
NC
NC
OUT
18
1
2
74
57
AUD_CL_OUT
OUT
LV
19
20
21
22
64
63
62
61
1
52
51
50
73
72
71
70
56
55
54
53
TP
XTAL_OUT
XTAL_IN
TESTEN
OUT
IN
IN
LV
OBL
OBL
OBL
23
60
49
69
52
ANA_IN2+
IN
AVSS via
56 pF/LV
24
59
48
68
51
ANA_IN-
IN
AVSS via
56 pF/LV
25
26
27
28
-
58
57
56
55
-
47
46
45
44
-
67
66
65
64
63
62
61
60
59
50
49
48
47
-
ANA_IN1+
AVSUP
AVSUP
NC
NC
AVSS
AVSS
MONO_IN
NC
IN
29
54
43
58
46
VREFTOP
30
31
32
33
34
35
36
53
52
51
50
49
48
47
42
41
40
39
38
57
56
55
54
53
52
51
45
44
43
42
41
40
39
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
ASG2
SC3_IN_R
OUT
IN
OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN
IN
IN/OUT
IN/OUT
IN
LV
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
OBL
OBL
LV
LV
LV
LV
LV
LV
OBL
OBL
LV
LV
OBL
OBL
LV
LV
OBL
IN
IN
IN
IN
IN
LV
LV
AHVSS
LV
LV
AHVSS
LV
Short Description
ADR word strobe
Not connected
ADR Data Output
2
I S1 data input
2
I S data output
2
I S word strobe
2
I S clock
2
I C data
2
I C clock
Not connected
Stand-by (low-active)
2
I C bus address select
D_CTR_I/O_0
D_CTR_I/O_1
Not connected
Not connected
Not connected
Audio clock output
(18.432 MHz)
Test pin
Crystal oscillator
Crystal oscillator
Test pin
IF Input 2 (can be left
vacant, only if IF input 1 is
also not in use)
IF common (can be left
vacant, only if IF input 1 is
also not in use)
IF input 1
Analog power supply 5V
Analog power supply 5V
Not connected
Not connected
Analog ground
Analog ground
Mono input
Not connected
Reference voltage IF A/D
converter
SCART 1 input, right
SCART 1 input, left
Analog Shield Ground 1
SCART 2 input, right
SCART 2 input, left
Analog Shield Ground 2
SCART 3 input, right
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37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
SC3_IN_L
ASG4
SC4_IN_R
SC4_IN_L
NC
AGNDC
AHVSS
AHVSS
NC
NC
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R
NC
NC
DACM_SUB
NC
DACM_L
DACM_R
VREF2
DACA_L
DACA_R
NC
NC
RESETQ
NC
NC
NC
I2S_DA_IN2
DVSS
DVSS
DVSS
DVSUP
DVSUP
DVSUP
ADR_CL
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
LV
AHVSS
LV
LV
LV or AHVSS
OBL
OBL
OBL
LV
LV
OBL
OBL
OBL
LV
LV
OBL
LV
LV
LV
LV
LV
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
LV
LV
LV
LV
OBL
OBL
OBL
OBL
OBL
OBL
LV
SCART 3 input, left
Analog Shield Ground 4
SCART 4 input, right
SCART 4 input, left
Not connected
Analog reference voltage
Analog ground
Analog ground
Not connected
Not connected
Volume capacitor MAIN
Analog power supply 8V
Volume capacitor AUX
SCART output 1, left
SCART output 1, right
Reference ground 1
SCART output 2, left
SCART output 2, right
Not connected
Not connected
Subwoofer output
Not connected
Loudspeaker out, left
Loudspeaker out, right
Reference ground 2
Headphone out, left
Headphone out, right
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
2
I S2-data input
Digital ground
Digital ground
Digital ground
Digital power supply 5V
Digital power supply 5V
Digital power supply 5V
ADR clock
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12.18. DS90C385
12.18.1. General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that
converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data
streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a
dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe
Receiver (DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which
provides a 44% reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal
means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
12.18.2. Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA
• Narrow bus reduces cable size and cost
• Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
12.18.3. Pinning
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12.19. NDS8947
12.19.1. General Description
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high density process is especially tailored to
minimize on-state resistance and provide superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
12.19.2. Features
• -4A, -30V. RDS(ON) = 0.065W @ VGS = -10V
RDS(ON) = 0.1W @ VGS = -4.5V.
• High density cell design for extremely low RDS(ON).
• High power and current handling capability in a widely used surface mount package.
• Dual MOSFET in surface mount package.
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13. SERVICE MENU SETTINGS
All system, geometry and white balance alignments are performed in production service mode. Before
starting the production mode alignments, make sure that all manual adjustments are done correctly. To
start production mode alignments enter the main menu by pressing “M” button and then press the digits 4,
7, 2 and 5 respectively. The following menu appears on the screen.
Service
Adjust...
Options...
Aps Wss Test
TFT26 Version Time Date
After entering the Service menu, you can access its items by pressing “▲/▼” buttons. In order to enter
selected menu, use “◄/►” buttons. To exit the service menu press “M” button.
Entire service menu parameters of TFT TV are listed below.
13.1. ADJUST MENU SETTINGS
In order to enter Adjust menu, move the cursor to Adjust… parameter by pressing “▲/▼” buttons in
Service Menu and press “◄/►” button. The following menu appears on the screen.
Adjust...
P 08 CNN S 04 BG 463
There are 12 items in the OPTIONS menu, but 11 of them are seen when you first enter the menu. Using
“▲/▼” buttons remaining items can be seen.
By Pass VLUT
On/Off
Enables / disables VLUT bypass.
R
Adjusts the red level in the video.
Min. Value:
Max. Value:
000
255
G
Adjusts the green level in the video.
Min. Value:
Max. Value:
000
255
B
Adjusts the blue level in the video.
Min. Value:
Max. Value:
000
255
R
Adjusts the red level in the video.
Min. Value:
Max. Value:
000
255
VPC BR
Adjusts the brightness level.
Min. Value:
Max. Value:
000
255
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VPC CT RF
Adjusts the contrast level. for RF mode.
Min. Value:
Max. Value:
000
063
VPC CT AV
Adjusts the contrast level. for AV modes.
Min. Value:
Max. Value:
000
063
VPC SATCB
Adjusts the VPC satcb register.
Min. Value:
Max. Value:
000
063
VPC SATCR
Adjusts the VPC satcr register.
Min. Value:
Max. Value:
000
063
VPC CIPBR
Adjusts the VPC cipbr register.
Min. Value:
Max. Value:
000
255
VPC CIPCT
Adjusts the VPC cipct register.
Min. Value:
Max. Value:
000
063
Dimming
Adjusts the panel dimming.
Min. Value:
Max. Value:
000
255
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13.2. OPTIONS MENU SETTINGS
In order to enter Options menu, move the cursor to Options… parameter by pressing “▲/▼” buttons in
Service Menu and press “◄/►” button. The following menu appears on the screen.
Options...
Hue
First APS
A.P.S.
Headphone
Vsr
DBE
Subwoofer
Lineout
DolbyPro
Equalizer
000:
On
There are 53 items in the OPTIONS menu, but 11 of them are seen when you first enter the menu. Using
“▲/▼” buttons remaining items can be seen.
Hue
On/Off
Enables / disables Hue option in Picture menu.
First APS
On/Off
If ON, TV starts with APS menu at Start-up.
A.P.S
On/Off
Enables / disables Automatic Programming System.
Headphone
On/Off
Enables / disables the usage of the HP and HP related items in Sound menu.
Vsr
Enables / disables Vsr.
On/Off
DBE
On/Off
Enables / disables DBE.
Subwoofer
On/Off
Enables / disables Subwoofer.
Lineout
On/Off
Enables / disables Lineout.
DolbyPro
On/Off
Enables / disables dolby prologic system.
Equalizer
On/Off
Enables / disables equalizer system.
BG
On/Off
Enables / disables BG Standard.
DK
On/Off
Enables / disables DK Standard.
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Options...
Equalizer
BG
DK
I
L
L’
AUS
NZ
NM
FM Prs Avl On
017:
Off
I
On/Off
Enables / disables I Standard.
L
On/Off
Enables / disables L Standard.
L’
On/Off
Enables / disables L’ Standard.
AUS
On/Off
Enables / disables AUS Standard.
NZ
On/Off
Enables / disables NZ Standard.
NM
On/Off
Enables / disables NM Standard.
FM Prs Avl On
Adjusts the FM Prescaler value, when Automatic Volume Levelling is On.
Min. Value:
000
Max. Value:
255
Options...
FM Prs Avl On
Nicam Prs Avl On
Scart Prs Avl On
Scart Volume Avl On
FM Prs Avl Off
Nicam Prs Avl Off
Scart Prs Avl Off
Scart Volume Avl Off
HOTEL VoD
X
027: FFFF 65535
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Nicam Prs Avl On
Adjusts the Nicam Prescaler value, when Automatic Volume Levelling is On.
Min. Value:
000
Max. Value:
255
Scart Prs Avl On
Adjusts the Scart Prescaler value, when Automatic Volume Levelling is On.
Min. Value:
000
Max. Value:
255
Scart Volume Avl On
Adjusts the Scart Volume value, when Automatic Volume Levelling is On.
Min. Value:
000
Max. Value:
255
FM Prs Avl Off
Adjusts the FM Prescaler value, when Automatic Volume Levelling is Off.
Min. Value:
000
Max. Value:
255
Nicam Prs Avl Off
Adjusts the Nicam Prescaler value, when Automatic Volume Levelling is Off.
Min. Value:
000
Max. Value:
255
Scart Prs Avl Off
Adjusts the Scart Prescaler value, when Automatic Volume Levelling is Off.
Min. Value:
000
Max. Value:
255
Scart Volume Avl Off
Adjusts the Scart Volume value, when Automatic Volume Levelling is Off.
Min. Value:
000
Max. Value:
255
Hotel VoD
On/Off
Enables / disables Hotel Video-on-Demand feature.
Options...
X
X
X
Avl
Top TXT
Fast TXT
TXT Lang
IF Freq
Sound
Carrier
036:
On
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Avl
On/Off
Enables / disables Automatic Volume Levelling feature.
Top TXT
On/Off
Enables / disables TopText feature.
Fast TXT
On/Off
Enables / disables FastText feature.
TXT Lang
Switches between Teletext Language Groups.
Min. Value:
000
Max. Value:
004
IF Freq
Adjusts the IF Frequency value.
Min. Value:
Max. Value:
000
255
Sound
On/Off
Enables / disables Sound.
Carrier
On/Off
Enables / disables sound Carrier feature.
Options...
Carrier
RC_Options
AV-1
AV-2
S-VIDEO
AV-3
PC
MENU
MIX
HOTEL MODE
045-
Off
RC_Options
Adjusts the Remote Control type. The values are:
1: RCMM standard remote control
2: Metz RC
3: Toshiba RC
4: Credit card 2025
Values greater than 4 are invalid and standard RC will be chosen automatically.
AV-1
On/Off
Enables / disables AV-1.
AV-2
On/Off
Enables / disables AV-2.
S-VIDEO
On/Off
Enables / disables S-VIDEO.
AV-3
On/Off
Enables / disables AV-3.
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PC
Enables / disables PC.
On/Off
MENU
On/Off
Enables / disables semi-transparent MENU.
MIX
Enables / disables teletext MIX mode.
Enable:
001
Disable:
000
HOTEL MODE
On/Off
Enables /disables Hotel mode feature.
OTHER
Adjusts the standard value for APS for Eastern European countries. The values are:
0: BG standard
1: DK standard
LDLY
Adjusts the Luna / chroma DeLaY value.
Min. Value:
000
Max. Value:
007
AGC
Adjusts the Automatic Gain Control value.
Min. Value:
000
Max. Value:
031
Options...
AV-3
PC
MENU
MIX
HOTEL MODE
X
OTHER
X
LDLY
AGC
050- 0012 00018
PIP
Enables / disables PIP.
On/Off
PAP
On/Off
Enables / disables PAP.
Full PC
On/Off
Enables / disables Full PC.
PC AUDIO
On/Off
Enables / disables PC AUDIO.
OSDCLK_DLY
Adjusts the Osd clock.
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Min. Value:
Max. Value:
000
003
OSDCLK_PINDLY
Adjusts the Osd clock.
Min. Value:
Max. Value:
000
003
TUNER OPTION
Philips/Thomson
Selects the tuner type used.
.
13.3. APS WSS TEST MENU
In order to enter Aps Wss Test menu, move the cursor to Aps Wss Test parameter by pressing “▲/▼”
buttons in Service Menu and press “◄/►” button. The following menu appears on the screen.
Aps Wss Test
Programme
Search
VPS
Pdc Format 1
Pdc Format 2
Name
Wss
P 08
CNN S 04 BG 463
There are 7 items in the Aps Wss Test menu.
Programme
Search
VPS
Pdc Format 1
Pdc Format 2
Name
Wss
37
32” TFT TV Service Manual
06/03/2006
14. BLOCK DIAGRAM
17MB08Pxx
LCD TFT PANEL
KEYPAD
SDRAM
2MX32bits
LVDS
DS90C385
AMPLIFIER
TPA3002
24bit RGB
CVBS IN
PC AUDIO IN
HEADPHONE
GM6015
AUDIO IN
L&R
AMMONO
QSS
OSD
MTV130
+5V
YPBPR AUDIO IN
BT.656
SC2_OUT_LR
POWER SUPPLY
AUDIO
PROCESSOR
MSP3410
SC2_IN_LR
+8V
RGB_SEL
+12V
SC1_OUT_LR
HP AMP.
TDA1308
SC1_IN_LR
IR&LED CARD
ADC
MST9883
S-VIDEO IN
R[0-7]
G[0-7]
B[0-7]
V SYNC
H SYNC
LINE OUT
L&R
SUBWOOFER
OUT
Headphone
RGB_TXT
+2.5V
RGB
SWITCH
+3.3V
VIDEO
PRO
VPC3230
+33V
RGB_SC
CVBS_IF
INVERTER
SC1_CVBS
MUX
R,G,B_SC2
PI5V330
R,G,B_SC1
SC1_IN_LR
SCART2
YPbPr Audio In
IF PRO
TDA9886
SC1_OUT_LR
YPBPR IN
CVBS_OUT1
PC IN
SC2_OUT_LR
SC2_IN_LR
DC
CVBS_OUT2
I2C
SC2_CVBS
EEPROM
24C16
PI5V330
CVBS
VIDEO MATRIX
TEA6415
BL_ON/OFF, BRT_ADJ
MUX
S-VIDEO
CVBS_TXT
C
Y/CVBS
MCU
SDA5550
FLASH
512K
SCART1
sound
SAW
video
SAW
IF
TUNER
PC AUDIO IN
38
32” TFT TV Service Manual
06/03/2006
15. CIRCUIT DIAGRAMS
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