1975 , Volume , Issue Dec-1975

1975 , Volume , Issue Dec-1975

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DECEMBER 1975

© Copr. 1949-1998 Hewlett-Packard Co.

A 100-MHz Analog Oscilloscope for

Digital Measurements

A n e w g e n e r a l - p u r p o s e o s c i l l o s c o p e h a s f e a t u r e s s u c h a s d u a l - c h a n n e l m a g n i f i c a t i o n a n d t h i r d - c h a n n e l trigger display that enhance its versatility, particularly with respect to measurements in digital systems.

by Allan I. Best

DESPITE CONTINUING ADVANCES in circuit speeds, a great amount of digital design work continues to be carried on at clock rates below

100 MHz.

This is particularly true for digital designs involv ing TTL and CMOS devices where clock rates below 50 MHz predominate. Hence, the growing need in digital test instrumentation is not so much for the ability to work at the highest possible speed as it is for means of coping with the complexity of digital circuit operation, a need that is becoming more and more acute as the applications of microprocessors continue to expand.

In assessing the oscilloscope needs of digital designers, it became clear that the requirements of a large segment of users could be met by a general- purpose, dual-channel scope that had a bandwidth of 100 MHz, a wide range of vertical deflection fac tors, a bright CRT capable of finely-drawn traces, a precision time base, sensitive, stable triggering and a delaying sweep with low inherent jitter that would enable timing measurements with less than

1% error.

In particular, for the debugging and field mainte nance of digital systems — especially those based on microprocessors — it was expected that users would want to team such a scope with a logic state analyzer,1 the logic state analyzer to locate problems in the data domain and the oscilloscope to work in the time domain finding the electrical malfunctions that cause the data-domain problems (see box, page 5).

A Well Fitted Oscilloscope

It was with this background in mind that a new oscilloscope was developed. The primary goal was to provide lab-quality performance and versatility in an easily-maintained instrument at an economical price.

The result is shown in Fig. 1.

Although this instrument, the HP Model 1740A, has the compactness, ruggedness, and ease of main tenance required of an instrument for the field, it has all the attributes of a high-quality, dual-channel,

100-MHz laboratory oscilloscope. It is well suited for digital work with its bright CRT display, precision time bases, stable triggering, and a third channel that enables the timing of an external sweep trigger signal

I C o v e r : D i s p l a y o f w a v e f o r m s f u l f i l l s a n i m p o r t a n t f u n c t i o n i n t h e w o r l d o f 1 ' s and O's just as it always has i n t h e w o r l d o f a n a l o g s i g n a l s . T h e o s c i l l o s c o p e p i c t u r e d h e r e d i s p l a y s w a v e f o r m s i n t h e t r a d i t i o n a l m a n ner but it can also be adapted t o d i s p l a y 1 ' s a n d O ' s i n a d a t a f o r m a t , a s e x p l a i n e d i n t h e a r t i c l e b e g i n n i n g o n t h i s p a g e .

In this Issue:

A 1 0 0 - M H z A n a l o g O s c i l l o s c o p e f o r

Digital Measurements, by Allan I. Best page 2

A n O s c i l l o s c o p e V e r t i c a l - C h a n n e l

A m p l i f i e r t h a t C o m b i n e s M o n o l i t h i c ,

T h i c k - F i l m H y b r i d , a n d D i s c r e t e

Technologies, by Joe K. Millard .... page 8

A R e a l - T i m e O p e r a t i n g S y s t e m w i t h

Multi-Terminal and Batch /Spool Capa b i l i t i e s , b y G e o r g e A . A n z i n g e r a n d

A d e l e M . G a d o l p a g e 1 2

Real-Time Executive System Manages

Large Memories, by Linda W. Averett page 18

Printed in US. A. c H e w l e t t - P a c k a r d C o m p a n y . 1 9 7 5

© Copr. 1949-1998 Hewlett-Packard Co.

»- V Ei ^

F i g . 1 . M o d e l 1 7 4 0 A O s c i l l o s c o p e c a n d i s p l a y t h e s w e e p t r i g g e r w a v e f o r m a s a t h i r d t r a c e s i m u l t a n e o u s l y w i t h t h e w a v e f o r m s i n c h a n n e l s A a n d B . T h e n e w o s c i l l o s c o p e h a s d c - t o -

1 0 0 - M H z b a n d w i d t h , s e l e c t a b l e i n p u t i m p e d a n c e ( h i g h i m p e d a n c e o r a w e l l - m a t c h e d 5 0 à œ ) , p r e c i s i o n d e l a y e d s w e e p , a b r i g h t , f i n e l y - f o c u s s e d t r a c e , a n d a l l t h e o t h e r c h a r a c t e r i s t i c s o f a h i g h - q u a l i t y l a b o r a t o r y oscilloscope.

to be compared to the signals in both vertical chan nels. Of particular interest to digital designers is an option that enables the new scope to serve as the digital display for a logic state analyzer, with instant pushbutton restoration of the analog display when ever desired (Fig. 2).

x5 Vertical Magnifier

In earlier high-frequency oscilloscopes, increased sensitivity at reduced bandwidth in the vertical chan nel was obtained by cascading the two vertical chan nels into one channel, thus sacrificing the dual- channel display. In the new Model 1740A Oscil loscope, the X5 magnifier operates on both vertical channels, increasing the sensitivity from a vertical deflection factor of 5mV/cm to 1 mV/cm, at a band width of 40 MHz, while retaining dual-channel oper ation. In this mode the two channels may display sig nals separately in either the alternate or chopped dis play mode, or they may be combined (A — B) for single- channel display of differential signals.

Trigger Display

When two signals are being displayed on the Model

1740A in either the alternate or chopped modes, pressing the TRIG VIEW pushbutton adds a third trace, giving a three-channel display (Fig. 2b). The third trace displays the sweep trigger signal, thus enabling the user to make timing measurements between an external trigger signal and the signals in channels A and B. The propagation delay through the trigger- view channel matches those of the vertical channels within 2.5 ns ± 1 ns, thus assuring integrity in timing comparisons between the external trigger signal and the signals in channels A and B.

In effect, the trigger-view mode provides a third,

80-MHz channel for viewing a signal applied at the trigger input. The deflection factor is nominally 100 mV/div, compatible with ECL logic levels, or 1 V/div with the xio attenuator, compatible with TTL and

CMOS levels. These are changed to 20 mV/div and

200 mV/div when the x 5 magnifier is used.

When the sweep is triggered by the signal in chan nel A or B, the trigger-view channel displays the same signal with approximately the same deflection factor and, as with an external trigger, it may be posi tioned by the TRIGGER LEVEL control to show the trig gering point. The dc levels of the trigger amplifier are set so the sweep trigger level corresponds to the center horizontal graticule line on the CRT, thus the operator can see which point on the waveform ini tiates the sweep.

The displayed waveform is also processed through the trigger input filtering (HF REJECT, LF REJECT) so the operator sees the waveform exactly as the trigger- recognition circuit sees it. The trigger-level control functions like a positioning control, displacing the waveform vertically so the operator can choose a trig ger level that avoids the likelihood of triggering on noise or other waveform anomalies

© Copr. 1949-1998 Hewlett-Packard Co.

F i g . 2 . W h e n e q u i p p e d w i t h t h e l o g i c - s t a t e o p t i o n M o d e l 1 7 4 0 A can display either the data domain o u t p u t s o f a l o g i c s t a t e a n a l y z e r

(a) or time-domain waveforms ap p l i e d t h r o u g h i t s o w n i n p u t s ( b ) .

The upper trace in (b) is the digital w a v e f o r m c o r r e s p o n d i n g t o t h e right-hand column of the table dis p l a y i n ( a ) , d e l a y e d o n e c l o c k p e r i o d . T h e s c o p e i s i n t h e T R I G

V I E W m o d e , d i s p l a y i n g t h e l o g i c state analyzer's trigger output on the middle trace.

Design Approach

Although the design of the new oscilloscope covered ground already traversed by other HP oscil loscopes with respect to performance, it was decided not to retain elements of earlier designs if advancing technology made it possible to improve the design with respect to maintainability, reliability, and man ufacturing cost.

One element of earlier designs that was retained, however, was the cathode-ray tube. This is the same tube used in the 180-series oscilloscopes.2 Noted for its small spot size and bright traces, it has the writing speed needed for displaying low rep-rate, fast tran sitions at the 5-ns/cm sweep speed. An advanced design to begin with, it has been improved over the years and in the course of building 40,000 or so, HP production engineers have refined the manufactur ing process such that a long, trouble-free life can be expected from these CRT's.

The highly-integrated vertical amplifier, on the other hand, is entirely new and contributes to the stable performance and manufacturability of the new oscilloscope. It is discussed in detail in the article beginning on page 8.

Horizontal System

Another technique retained from earlier designs is the trigger recognition circuits. For both the main and delayed sweeps, the new scope uses the same HP monolithic integrated circuits as the 275-MHz Model

1720A Oscilloscope.3 They provide stable triggering on signals above 100 MHz but require an amplitude equivalent to only 1 cm of deflection at 100 MHz to do so.

A variety of trigger modes gives the flexibility needed for lab applications. The new scope triggers repetitively or singly on externally supplied or in ternal signals. Trigger slope and amplitude are selec table. The trigger input coupling can be dc or ac and it can be filtered to remove noise above 4 kHz (HF REJECT) or remove powerline and other interference below

4 kHz (LF REJECT).

The main sweep circuit has controllable trigger holdoff time, as used for the past eight years on HP high-performance scopes. This inhibits triggering for a selected time interval after a sweep terminates and is useful when examining complicated waveforms that have more than one trigger point.

The sweep circuits use the familiar Miller integra tor. The well-regulated supply voltages and high- gain amplifiers for the integrators assure sweep ac curacy well within 2% on the fast sweeps (3% with the horizontal x 10 magnifier). A full complement of sweep modes is provided, including main sweep, main intensified, calibrated delayed sweep, and calibrated mixed sweep.

The comparator that selects the point on the main sweep where the delayed sweep is to start has a stable trigger level such that delay jitter is less than 0.002% of the maximum delay on each range. This plus the precision 10-turn delay control and the sweep accur acy enables time intervals to be measured by the dif ferential time measurement technique over most of the range with an accuracy of ±(0.5% + 0.1% of full scale).

The new scope also has an A versus B mode for high-speed X-Y plotting. In this mode, the A channel signal drives the CRT in the vertical direction and the signal in the B channel drives it in the horizontal direction. The bandwidth of the horizontal channel in this case is 5 MHz. The A versus B capability is re placed by the logic-state option, however, when that option is installed.

The Logic-State Option

When equipped with the logic-state option, the

Model 1740A can work with the Model 1607A Logic

State Analyzer1 to provide a measurement tool of sin gular usefulness for the digital designer and trouble- shooter (Fig. 3). This option equips the 1740A with internal switching and rear-panel inputs for the logic state analyzer outputs. A front-panel pushbutton en ables the user to switch back and forth between the

â € ¢ T o m a k e t h i s m e a s u r e m e n t , t h e d e l a y e d s w e e p i s u s e d a n d ( t i e s t a r t 1 p o i n t i s p o s i t i o n e d a t c e n t e r s c r e e n t h e n t h e d e l a y c o n t r o l . T h e d e l a y s e t t i n g i s n o t e d a n d t h e s t o p " p o i n t i s t h e n p o s i t i o n e d a t c e n t e r s c r e e n , a n d w i t h t h e d e l a y c o n t r o l . T h e d i f f e r e n c e b e t w e e n t h e n e w d e l a y - c o n t r o l s e t t i n g a n d t h e p r e v i o u s o n e i s t h e t i m e i n t e r v a l b e t w e e n s t a r t a n d s t o p p o i n t s .

© Copr. 1949-1998 Hewlett-Packard Co.

Working in the Data Domain — Logic State

Analyzers and Oscilloscopes

The on-going diffusion of digital techniques into all branches o f e l e c t r o n i c d e s i g n h a s r a d i c a l l y c h a n g e d t h e n a t u r e o f many — if not most — design, production test, and field mainten ance tasks. Electronic engineers, who have all learned to use the underlying mathematics and analytical instrumentation for d e s i g n i n g i n t h e f r e q u e n c y a n d t i m e d o m a i n s , m u s t n o w b e come familiar with the data domain.

A simple example will illustrate what one faces when dealing w i t h t h e d a t a d o m a i n . T h e d r a w i n g s h o w s f o u r w a v e f o r m s .

Whether we think of these as being generated in a series of com binatorial logic gates or from instructions in a microprocessor or a computer is irrelevant — simultaneous waveforms like these o c c u r o n a o n e - s h o t b a s i s t h r o u g h o u t a l l d i g i t a l e q u i p m e n t , usually on a much grander scale, from 16 to 128 simultaneous signals.

Time

T h e q u e s t i o n i s , i f y o u a r e t r a c k i n g d o w n a s y s t e m m a l f u n c tion where these waveforms are involved, what do you measure and how? If the clock rate is too fast for a chopped oscilloscope display, you can't capture the four waveforms on a storage os cilloscope for analysis. Electronic counters could tell you how many logic highs occurred on each channel, but would not give timing relationships. You could also derive the number of logic highs from voltmeter measurements of the average value of the w a v e f o r m s b u t w h a t w o u l d t h i s t e l l y o u ? O s c i l l o s c o p e s , v o l t meters, and counters are familiar to all, but none of these clas s i c i n s t r u m e n t s d o e s a v e r y g o o d j o b o n d i g i t a l p r o b l e m s b e c a u s e n o n e w a s d e s i g n e d t o s o l v e t h e m .

Such a set of signals can be examined meaningfully with the aid of a logic state analyzer. These instruments sample all chan nels on every clock edge, detect the logic levels on all channels simultaneously, and store them for display and study.

The more important aspect of the problem, however, is what do we need to know about these signals once they have been c a p t u r e d ? H e r e i s w h e r e t h e c o n c e p t o f t h e d a t a d o m a i n comes in. These waveforms can be control signals or they can b e i n s t r u c t i o n s , m e m o r y a d d r e s s e s , o r d a t a . W h a t e v e r t h e y are, they can have varied meanings. If, for example, they repre sent bit-serial ASCII symbols with even parity, as may be found on an I/O bus, then the 8-bit frames here represent the letters D,

B , F , a n d J . I t m i g h t n o t b e o b v i o u s f r o m e x a m i n i n g t h e w a v e f o r m s t h a t a p a r i t y e r r o r o c c u r r e d w i t h t h e l e t t e r J n o r w h a t caused the error, yet in terms of the data being transmitted, an error ex certainly did occur. Before it can be corrected, its ex istence must be recognized.

T h e s e w a v e f o r m s c o u l d a l s o b e b i t - s e r i a l , l e a s t - s i g n i f i c a n t bit and least significant digit first, hexadecimal code (essential ly the data format of HP's pocket calculators). They would then be interpreted as 44, 42, 46, and 4A. Or, if they were word-serial h e x a d e c i m a l , a s i n H P ' s 2 1 M X C o m p u t e r s , t h e y w o u l d m e a n something else.

Obviously, there are a host of choices in terms of data format, d a t a c o d e , a n d l o g i c c o n v e n t i o n s t h a t m u s t b e t a k e n i n t o a c count when dealing with the data domain. For the first genera tion of logic state analyzers, the choice was made to use single- l e v e l t h r e s h o l d ( h i o r l o , u p o r d o w n , o n o r o f f ) , i n d e x i n g b y r e c o g n i z i n g b i n a r y s t a t e m e n t s ( B o o l e a n t r i g g e r i n g ) , a n d p o r trayal of the data as 1 's and O's. This machine-language presen tation does not restrict the data format but leaves it to the user to interpret the display in terms of the code used.

When considering where and for what tasks a logic state ana lyzer may be used, the question invariably arises, "don't you ulti mately have to see the waveforms to fix the problem?" It is worth trying to put this into perspective.

What logic state analyzers can do is to aid in the debugging of complex digital systems, particularly between the time that the computer simulation of the design is complete and the work ing hardware is operational. Because of the long data stream s e q u e n c e s t y p i c a l l y u s e d i n m o s t a l g o r i t h m i c d e s i g n , p a r t i c u larly when looping or nested sub-routines are involved, locating the problem is more critical than analyzing why the problem oc c u r r e d . I t m a y s i m p l y b e a s o f t w a r e p r o b l e m , s u c h a s a c c e s s ing the wrong instruction in memory. This can be readily identi fied by a logic state analyzer.

However, when an electrical malfunction is the culprit, an os c i l l o s c o p e  ¡ s n e e d e d b u t i t c a n ' t f i n d w h i c h e l e c t r i c a l p a r a meters are at fault unless it gets a trigger from the vicinity of the b a d d a t a . T h i s c a n b e l o c a t e d a n d p r o v i d e d b y a l o g i c s t a t e analyzer.

The logic state analyzer is not about to displace the oscillo scope as a troubleshooting tool for digital systems, but it does add a dimension to test instrumentation that until now had not b e e n a d e q u a t e l y p r o v i d e d . T h e l o g i c s t a t e a n a l y z e r c a n c a p t u r e a s e g m e n t o f a r a p i d l y e x e c u t i n g d i g i t a l s e q u e n c e f o r a n a l y s i s j u s t a s t h e o s c i l l o s c o p e c a n c a p t u r e a w a v e f o r m for examination.

Charles H. House

logic state display, as generated by the analyzer, and the analog display of signals detected by the scope's own probes (Fig. 2). There is no need to reconnect cables or reset controls when switching displays.

The logic state analyzer monitors data flow clocked in on up to 16 lines simultaneously. It generates the deflection voltages necessary for the oscilloscope so the clocked-in data can be displayed as a machine- language table of 1's and O's, enabling the user to see the data flow on the monitored lines. A front-panel switch register can be set to any digital word up to 16 bits wide and when that word occurs, a pulse is gener ated that can be used to trigger the scope.

The user can page through an executing program with the logic state analyzer and once a problem area has been identified, the trigger word can be reset to a

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© Copr. 1949-1998 Hewlett-Packard Co.

A "Visible" Mechanical Design

T h e p h o t o b e l o w , s h o w i n g t h e M o d e l 1 7 4 0 A O s c i l l o s c o p e w i t h b o t h c o v e r s r e m o v e d , i l l u s t r a t e s t h e o p e n n e s s o f t h e m e c h a n i c a l d e s i g n . T h e b y w o r d d u r i n g t h e d e s i g n p h a s e w a s

"visibility" — visibility in this case meaning a high degree of order in the internal layout and ready accessibility to all test points and components. are mounted on one of the power-supply circuit boards rather t h a n t h e r e a r p a n e l . T h i s e n a b l e d e f f e c t i v e i s o l a t i o n o f t h e p o w e r l i n e p r i m a r y c i r c u i t f r o m t h e r e s t o f t h e i n s t r u m e n t , a n d it further simplified wiring.

A new approach to attenuator design eliminated much of the p r o d u c t i o n t i m e f o r m e r l y r e q u i r e d f o r a s s e m b l i n g a c o m p l e x a t t e n u a t o r . N o e l e c t r o n i c s a r e c o n t a i n e d w i t h i n t h e s w i t c h mechanism itself. Instead, actuating cams press spring-finger shorting contacts down on pads in the printed-circuit board to s w i t c h g a i n a n d / o r s e l e c t i n p u t c o u p l i n g m o d e s , a s s h o w n b y the wide-angle photo below where the switch has been raised o f f t h e b o a r d t o d i s c l o s e d e t a i l s . A l l t h e s w i t c h e d c i r c u i t s c a n thus be incorporated on the printed-circuit board. This arrange m e n t r e d u c e d a s s e m b l y c o s t s s i g n i f i c a n t l y .

1

The primary element in the "visible" design was the reduction in wiring and cabling. The circuits are grouped functionally on eleven plug-together boards: three for the power supply, three for the vertical section, and five for the horizontal section. The three sections are interconnected by the interconnect board, a twelfth circuit board that satisfies the requirements of a cable t h a t w o u l d h a v e h a d p e r h a p s s o m e 2 6 w i r e s . T h u s , 5 2 c a b l e s o l d e r a n d / o r c r i m p e d c o n n e c t i o n s w e r e e l i m i n a t e d . A f u r t h e r b e n e f i t o f t h e a r r a n g e m e n t i s t h a t t h e v e r t i c a l a n d h o r i z o n t a l s e c t i o n s c a n b e d i s c o n n e c t e d f r o m t h e p o w e r s u p p l i e s a n d from each other to aid in troubleshooting.

F r o n t - p a n e l w i r i n g w a s r e d u c e d s u b s t a n t i a l l y b y m o u n t i n g controls on the circuit boards wherever possible and using ex tension shafts from the front-panel. In many cases this also ob tained an electrical advantage by placing the controls close to the circuits they control.

The powerline switch, fuse, and line-voltage-select switches

Besides contributing to a more visible mechanical layout, the p l u g - t o g e t h e r d e s i g n a l s o s i m p l i f i e d s o m e o f t h e c i r c u i t s . B y e l i m i n a t i n g t h e c a b l e - t o - c a b l e v a r i a t i o n s i n a d j a c e n t l e a d c a p a c i t a n c e , t h e p l u g - t o g e t h e r c o n s t r u c t i o n p e r m i t t e d a r e d u c t i o n i n t h e n u m b e r o f a d j u s t m e n t s t h a t w o u l d o t h e r w i s e b e r e q u i r e d t o n o r m a l i z e p e r f o r m a n c e . T h e p l u g - t o g e t h e r - b y - f u n c tion design also permits thorough testing of the individual circuit functions before final assembly.

I n t h e i n t e r e s t o f r e d u c i n g a s s e m b l y c o s t s , t h e m e c h a n i c a l parts, such as brackets, were standardized or eliminated as far a s p o s s i b l e . F o r e x a m p l e , t h e u s u a l p r a c t i c e o f s e l e c t i n g t h e length of a screw to be just long enough to protrude 1/32 inch beyond its fastener was abandoned in the interest of reducing the number of different screws. This reduction in the number of s c r e w t y p e s w i l l b e e s p e c i a l l y a p p r e c i a t e d b y s e r v i c e p e r s o n nel who may have an occasion to disassemble and reassemble the instrument.

Circuits were designed not only for performance but also for m i n i m u m p o w e r c o n s u m p t i o n . A s a r e s u l t , t h e o s c i l l o s c o p e ' s total power consumption is less than 1 00 VA. Thus, no fan is re quired nor are vent holes required, thereby obtaining an extra degree of protection against dust and other contaminants.

J o h n W . C a m p b e l l

word near the problem area. Then by switching the scope to the analog display, bus and control lines can be monitored to locate glitches, race problems, insuf ficient amplitude and other electrical problems that may be the cause of the digital problems.

Acknowledgments

The 1 740A design group was led by Stan Lang until the start of pilot production when he transferred to another project. In addition to those mentioned else where in these articles, the design team included Jim

Garner, mechanical design including the vertical attenuator switch, Eldon Cornish, who designed the horizontal section, and Van Harrison who designed the CRT circuits, power supplies, and gate ampli fier. Special thanks are due John Riggen and John

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© Copr. 1949-1998 Hewlett-Packard Co.

Cardón who provided valuable suggestions and support as section managers, and to Dick Stone who as product manager provided inputs anticipating customer requirements.

References

1. C.T. Small and J.S. Morrill, Jr., "The Logic State Ana lyzer, a Viewing Port for the Data Domain," Hewlett-

Packard Journal, August 1975.

2. F.G. Siegel, "A New DC-50+ MHz Transistorized

Oscilloscope of Basic Instrumentation Character," Hew lett-Packard Journal, August 1966.

3. P.K. Hardage, S.R. Kushnir, and T.J. Zamborelli,

"Optimizing the Design of a High-Performance Oscil loscope," Hewlett-Packard Journal, September 1974.

F i g . 3 . M o d e l 1 7 4 0 A O s c i l l o s c o p e e q u i p p e d w i t h t h e l o g i c - s t a t e o p t i o n ( o p t 1 0 1 ) i s a v a i l a b l e w i t h M o d e l 1 6 0 7 A L o g i c

S t a t e A n a l y z e r ( l o w e r u n i t ) i n a p a c k a g e k n o w n a s

Model 1740S.

Allan I. Best

A San Franciscan by birth, Al

Best joined Hewlett-Packard's

Oscilloscope Division in Palo

Alto upon getting his BSEE degree from the University of California at

Berkeley (1960), and moved with the division to Colorado Springs in 1964. Over the years he has c o n t r i b u t e d t o a w i d e r a n g e o f oscilloscope products as a circuit d e s i g n e r ( 1 8 5 B S a m p l i n g O s c i l loscope), project leader (1410A and related sampling plug-ins) a n d g r o u p m a n a g e r ( 1 7 4 0 A ) . I n f e w * . h i s s p a r e t i m e , A l e n j o y s s k i i n g i n the winter and high-country trout fishing, back-packing, and

4-wheel driving during the rest of the year. He is married and has four children.

Vertical Display Modes

C h a n n e l A , c h a n n e l B c h a n n e l s A a n d B d i s p l a y e d a l t e r n a t e l y c s w e e p s ( A L T ) 0 1 b y s w i t c h i n g b e t w e e n c h a n n e l s a t 2 5 0 k H z r a t e w i t h b l a n k i n g dunng switching ICHOPI channel A plus channel B lakjeDraic addition] , and trigger

V e r t i c a l A m p l i f i e r s ( 2 )

B a n d w i d t h a n d R i s e T i m e a t a l l d e f l e c t i o n f a c t o r s o v e r t e m p e r a t u r e r a n g e o (

0*C to -55 C

B A N D W I D T H ( 3 d B d o w n f r o m B - d i v r e f e r e n c e s i g n a l !

D C - C O U P L E D d c t o 1 0 0 M H z m b o t h 5 0 1 1 a n d t M i l i n p u t m o d e s

A C - C O U P L E D a p p r o * 1 0 H z t o 1 0 0 M H z . 1 H z w i t h 1 0 1 d i v i d e r p r o b e s

B A N D W I D T H L I M I T : b r r a t s u p p e r B a n d w i d t h t o 2 0 M H z

RISE input 3 5 ns. measured from 10°= to 90% points of a 6-div input Step

D E F L E C T I O N F A C T O R

R A N G E S 5 m V . d i v t o 2 0 V d i v O 2 c a l i b r a t e d p o s i t i o n s ) i n 1 . 2 , 5 s e q u e n c e , accurate witfun 3%

VERNIER continuously variable between all ranges, extends maximum deflec-

POLARITV: channel B may be inverted, front-panel pushbutton

DELAY LINE: input signals are delayed sufficiently to view triggering edge

I N P U T C O U P L I N G : s e l e c t a b l e a c o r d c . 5 0 i l ( 0 c | , o r g r o u n d G r o u n d p o s i t i o n d i s connects input connector and grounds amplifier input

INPUT HC (selectable)

A C O R D C 1 M i l  ± 2 % s h u n t e d b y a p p r o * 2 0 p F

5 0 O H M 5 0 ( 1 Â ± 3 % . S W R - 1 4 a t 1 0 0 M H z o n a t r a n g e s

M A X I M U M I N P U T

A C O R D C 2 5 0 V ( d c - p e a k a c ) o r 5 0 0 V p - p a t 1 k H z o r l e s s

5 0 O H M 5 V r m s

A - 8 O P E R A T I O N

A M P L I F I E R b a n d w i d t h a n d d e t e c t i o n t a c t o r s a r e u n c h a n g e d , c h a n n e l B m a y b e i n v e r t e d f o r A B o p e r a t i o n

D I F F E R E N T I A L ( A - B ) C O M M O N M O D E C M R R - s a t l e a s t 2 0 d B f r o m d c t o

20 MHz Common mode signal amplitude equivalent to 8 divisions with one ver - mor adjusted for optimum rejection

V E R T I C A L M A G N I F I C A T I O N ( - 5 )

B A N D W I D T H 3 d B d o w n f i o m 8 - d i v r e f e r e n c e * g n a l .

D C - C O U P L E D d c t o a p p r o i 4 0 M H z

A C - C O U P L E D a p p r o  » 1 0 H z l o 4 0 M H z

R I S E T I M E * 9 n s l m e a s u r e d f r o m 1 0 % t o 9 0 % p o i n t s o f 8 - d i v i n p u t s t e p )

D E F L E C T I O N F A C T O R i n c r e a s e s s e n s i t i v i t y o f e a c h d e f l e c t i o n f a c t o r s e t t i n g b y f a c t o r o f 5 w i t h m a x i m u m s e n s i t i v i t y o M m V o n c h a n n e l s A a n d B

TRIGGER SOURCE

CHANNEL A a» display modes mgge<«l by channel A signal

C H A N N E L B a d d i s p l a y m o d e s t r i g g e r e d b y c h a n n e l B s i g n a l

COMPOSITE at! display modes triggered by displayed signal except in Chop In

Chop mode, trigger signal is derived from channel A

L I N E F R E Q U E N C Y t r i g g e r s i g n a l i s d e r i v e d f r o m p o w e r k n e f r e q u e n c y .

TRIGGER VIEW

Displays internal or external tngger signal In Alternate or Chop mode. Channel A, channel B, and Digger signals are displayed In channel A or B mode. Tngger View over n oes that channel Internal tngger Signal amplitude appro» ma tes vertical

S i g n a l a m p l i t u d e E x t t r i g g e r s i g n a t d e f l e c t i o n f a c t o r i s a p p r o * 1 0 0 m V d r v . o r

1 V d r v i n E X T - 1 0 T r i g g e r i n g p a n i s a p p r o x i m a t e l y c e n t e r s c r e e n W i t h

•denticaly timed signáis lo a vertical «put and the Ext ngoer input, tngger signal delay is 2 S ns ± 1 ns

Horizontal Display Modes

Main, main intensified, mixed, delayed, mag • 10, and A vs B

MAIN AND DELAYED TIME BASE RANGES

MAIN SO n&drv to 2 sdrv (24 ranges) in t25 sequence

DELAYED 50 ns drv to 20 m&drv {IB ranges) m t

S P E C I F I C A T I O N S

M o d e l 1 7 4 0 A O s c i l l o s c o p e

T I M E B A S E A C C U R A C Y

S w e e p T i m e D i v

0 : C t o - 1

- 1 5 ' C t o * 3

- 3 5 Â ° C t o + 5

, lor 50 ms K

M A I N S W E E P V E R N I E R : c o n t i n u o u s l y v a r i a b l e b e t w e e n a l l r slowest sweep to at least 5 s div tends

MAGNIFIER (x 10): expands all sweeps by (actor of 10. extends lastest sweep

C A L I B R A T E D S W E E P D E L A Y

D E L A Y T I M E R A N G E 0 5 t o 1 0 - M a i n T i m e / D i v s e t t a n g s o f 1 0 0 n s t o 2 s ( m i mum delay 1 50 ns)

D I F F E R E N T I A L T I M E M E A S U R E M E N T A C C U R A C Y

M a i n T i m e B a t e

S e t t i n g

Accuracy

1 - 1 5 C t o - 3 5 C | '

100 ns div to 20 ms/drv

5 0 m s / d r v t o 2 s * v

: ( 0 5 % - 0 . 1 % o f f u l i  » c a  » )

- ( 1 % - 0 1 % o f f u l l s c a l e )

•Add 1 % tor temperatures (rom D'C to - 1 5 C and - 35 C lo - 55 C

DELAY JITTER < 0 002% ( 1 part in 50 000) O* maximum delay in each step Irom

- 1 5 C 1 0 - 3 5 C - 0 0 0 5 % [ 1 p a r t i n 2 0 0 0 0 ) f r o m d ' C t o - 1 5 C a n d

- 3 5 C 1 0 - 5 5 C

CALIBRATED MIXED TIME BASE

Dual and base in which mam time base dnves first portion of sweep and delayed time base completes sweep at faster rate Also operates m single sweep mode

A c c u r a c y a d d 2 % t o m a m t i m e b a s e a c c u r a c y

T r i g g e r i n g

MAIN SWEEP

N O R M A L S w e e p i s t r i g g e r e d b y i n t e r n a l o r e x t e r n a l s i g n a l

A U T O M A T I C b r i g h t b a s e h n e d i s p l a y e d m a b s e n c e o f i n p u t s i g n a l T r i g g e r i n g i s s a m e a s N o r m a l a b o v e 4 0 H z

S I N G L E s w e e p o c c u r s o n c e w i t h s a m e I n g g e n n g a s N o r m a l , r e s e t p u s h b u t t o n arms sweep and kghts indicator

D E L A Y E D S W E E P ( S W E E P A F T E R D E L A Y )

A U T Q d e l a y e d s w e e p a u t o m a t i c a l y s t a r t s a t e n d o f d e l a y .

TRIG delayed sweep is armed and trigger able at end of delay penad

INTERNAL oc to 25 MHz on signals causing 0 3 divisions or more vertical deflec t i o n , a l t o 1 d i v i s i o n o f v e r t i c a l d e f l e c t i o n a t 1 0 0 M H z i n a l d i s p l a y m o d e s

{required signal level is increased by 2 when in Chop mode and by 5 when • 5 vertical magnifier is used). Triggering on Line frequency is also selectable

EX ERNAL: dc to 50 MHz on signals of 50 mV p-p or more increasing to 100 mV p at 100 MHz (required signal level is increased by 2 when m Chop mode)

E X E R N A L I N P U T R C : a p p r o . 1 M i l s h u n t e d b y a p p r o . 2 0 p F

M A X I M U M E X T E R N A L I N P U T : 2 5 0 V ( d c - p e a k a c ) o r 5 0 0 V p - p a c a t 1 k H z

EL AND SLOPE

INTERNAL at any point on positrve or negative slope o* displayed waveform

E X T E R N A L c o n t i n u o u s l y v a r i a b l e I r o m - 1 5 V t o - 1 5 V o n e i t h e r s l o p e o f t r i g g e r s i g n a l , - r t S V t o - 1 5 V m d i v i d e - B y - 1 0 m o d e ( - 1 0 )

COUPLING:

D C f u l l r a n g e

A C a t t e n u a t e s s i g n a l s b e l o w a p p r o . 2 0 H z

L F R E J E C T ( M A I N S W E E P ) a t t e n u a t e s s i g n a l s b e l o w a p p r o * 4 k H z

H F R E J E C T ( M A I N S W E E P ) a t t e n u a t e s S i g n a l s a b o v e a p p r o * 4 k H z

T R I G G E R H O L D O F F ( M A I N S W E E P ) : i n c r e a s e s s w e e p h o k J o f f b m e

A v s B O p e r a t i o n

BANDWIDTH

C H A N N E L A ( Y A X I S ) s a m e a s c h a n n e l A

C H A N N E L B ( X - A X I S ) d c t o 5 M H z

D E F L E C T I O N F A C T O R : 5 m V d i v t o 2 0 V d i v ( 1 2 c a l i b r a t e d p o s i t i o n s ) i n

1.2.5 sequence

P H A S E D I F F E R E N C E B E T W E E N C H A N N E L S : - 3 d c l o 1 0 0 k H z

C a t h o d e - R a y T u b e a n d C o n t r o l s

TYPE: Hewlett-Packard 12 7 cm (S in) rectangular CRT. post accelerator appro»

1 5 - W a c c e l e r a t i n g p o t e n t i a l a l u n v n i z e d P 3 1 p h o s p h o r

GRATICULE: 8 • 10 div (1 div = 1 cm) internat, non -parallax graticule with 0.2 s u b d i v i s i o n m a r k i n g s o n m a j o r h o r i z o n t a l a n d v e r t i c a l a x e s a n d m a r k i n g s f o r rise time measurements Internal floodgun graticule illumination

B E A M F I N D E R : r e t u r n s I r a c e l o C R T s c r e e n r e g a r d l e s s o f s e t t i n g o f h o r i z o n t a l . vertical or intensity controls

Z - A X I S I N P U T : â € ¢ 4 V * 5 0 n s W

i n t e n s i t y , u s a b l e u p t o 1 0 M H z l o r r u p u l s e b l a n k s t r a c e o f a n y i r t t e n s i t y I n p u t R . 1 M l à ¯ 1 0 %

M a x i m u m i n p u t - 2 0 V f o e - p e a k a c )

R E A R P A N E L C O N T R O L S : a s t i g m a t i s m a n d t r a c e a l i g n

G e n e r a l

REAR PANEL OUTPUTS: mam and delayed gates. 0 8 V to s u p p l y i n g a p p r o . 5 m A .

• - 25VC,

A M P L I T U D E C A L I B R A T O R ( f f C l o - 5 5 C )

O U T P U T V O L T A G E 1 V p - p  ± 1 % i n i o = M M i l . 0 1 V p - p  ± ! % i n t o S O U

R I S E T I M E - - 0 1 M S

F R E Q U E N C Y a p p r o x i m a t e l y 1 4 k H z

P O W E R : 1 0 0 . 1 2 0 . 2 2 0 . 2 4 0 V a c : 1 0 % . 4 8 t o 4 4 0 H z . 1 0 0 V A m a x

W E I G H T : 1 3 k g ( 2 8 6 l b j

O P E R A T I N G E N V I R O N M E N T

T E M P E R A T U R E O C t O - 5 5 C

H U M I D I T Y t o 9 5 % r e l a t i v e h u m i d i t y a t - 4 0 i C

A L T I T U D E 1 0 4 6 0 0 m ( 1 5 . 0 0 0 I t )

V I B R A T I O N v i b r a t e d m t h r e e p l a n e s l o r 1 5 r w n e a c h w i t h 0 2 5 4 m m ( 0 0 1 0 m ) e . c u r s i o n . 1 0 t o 5 5 H z

DIMENSIONS: 335 mm W • 197 mm H • 492 mm D (0.19 > 7.75 • 19.38 in)

A C C E S S O R I E S F U R N I S H E D : b l u e l i g h t t i t t e r , f r o n t p a n e l c o v e r , p o w e r c o r d . v i n y l M o d e l s t o r a g e p o u c h , o p e r a t o r s g u i d e a n d s e r v i c e m a n u a l , t w o M o d e l

100060 10 1 divider probes

O P T I O N S

0 0 1 f i x e d p o w e r c o r d n h e u o f d e t a c h a b l e p o w e r c o r d

101 LOGIC STATE DISPLAY single pushbutton (Gold Button) interface Option for operation with HP Model 1607A Logic State Analyzer

P R I C E S I N U S A

M O D E L 1 7 4 0 A 1 0 0 M H z O s o l o s c o p e S 1 9 9 5

O P T I O N 0 0 1 A d d S I S .

O P T I O N 1 0 1 A d d S 1 0 5

M O D E L 1 7 4 0 S i n c l u d e s 1 7 4 0 A w i t h O p t i o n 1 0 1 . M o d e l 1 6 0 7 A L o g i c S l a t e

Analyzer, four interconnecting cabtes. and bracket and strap for combirang into a single package. $4935

M A N U F A C T U R I N G D I V I S I O N : C O L O R A D O S P R I N G S D I V I S I O N

1 9 0 0 G a r d e n o f t h e G o d s R o a d

C o l o r a d o S p r i n g s C o l o r a d o 8 0 9 0 7 U S A

© Copr. 1949-1998 Hewlett-Packard Co.

An Oscilloscope Vertical-Channel

Amplifier that Combines Monolithic, Thick-

Film Hybrid, and Discrete Technologies

T o m i n i m i z e m a i n t e n a n c e a n d c a l i b r a t i o n t i m e s b y m i n i m i z i n g t h e n u m b e r o f p a r t s a n d t h e n u m b e r o f a d j u s t m e n t s , a h i g h d e g r e e o f i n t e g r a t i o n w a s incorporated in the vertical amplifier system of the

Model 17 40 A Oscilloscope.

by Joe K. Millard

HYBRID THICK-FILM TECHNOLOGY using HP- manufactured monolithic chips enables the vertical channel of the Model 1740A Oscilloscope to meet its bandwidth specifications without time- consuming adjustment of many trimmers. Further more, the specified bandwidth is maintained through out an operating temperature range of 0 to 55°C.

Signal conditioning is accomplished primarily by two hybrid thick-film integrated circuits, shown as

Ul and U2 in the block diagram of Fig. 1. The only other active components are the discrete FET imped ance converters at the input, and the circuits involv ing transistors Q1-Q4.

Discrete components are used for attenuation only in the xlOO section preceding the FET impedance converter in each channel. The preamplifier 1C (Ul), besides carrying out the necessary control functions, performs six de-actuated attenuation ranges per channel. With the x 100 attenuator, this realizes twelve calibrated deflection-factor ranges, from 5 mV/ cm to 20 V/cm.

Range selection is accomplished by the switch as sembly described on page 6 of the preceding arti cle. The spring-finger contacts of this switch com plete circuit paths through appropriate pads on the circuit board. Only the first five contacts, controlling

o - v w - i

From Horizontal

Channel

Fig. Oscilloscope. the diagram of the vertical channel in the Model 1740A Oscilloscope. Most of the s i g n a l U 2 . o c c u r s w i t h i n t h e t w o h y b r i d t h i c k - f i l m c i r c u i t s , U 1 a n d U 2 .

© Copr. 1949-1998 Hewlett-Packard Co.

Designing a High-Density Thick-

Film Hybrid Integrated Circuit

P l a c i n g t h r e e m o n o l i t h i c c h i p s , t h i r t y - o n e r e s i s t o r s , f o u r c a p a c i t o r s , a n d s e v e n t y - s i x w i r e b o n d s o n a s t a n d a r d

2 5 x 3 5 - m m s u b s t r a t e f o r t h e M o d e l 1 7 4 0 A O s c i l l o s c o p e p r e a m p c h a l l e n g e d t h e l i m i t s o f t h i c k - f i l m t e c h n o l o g y ( t h i c k - f i l m s a r e u s e d r a t h e r t h a n t h i n f i l m s t o m i n i m i z e c o s t s ) . T h e c o m p o n e n t d e n s i t y d i c t a t e d t h e u s e o f 0 . 1 5 - m m c o n d u c t o r s , w h i c h i s d e f i n i t e l y f i n e - l i n e g e o m e t r y b y t h i c k - f i l m s t a n d a r d s . I n a d d i t i o n , t h e r e s i s t o r s a n d c a p a c i t o r s w o u l d h a v e to be smaller than those used in present practice. The design w o u l d a l s o h a v e t o e l i m i n a t e m a n y o f t h e p r o p o s e d p r o b i n g pads needed for resistor trimming. These are space hogs that are better done without.

H o w w e r e a l l t h e s e r e q u i r e m e n t s m e t w i t h a 2 1 0 - n a n o a c r e substrate? The fine-line geometry was achieved by pre-treating t h e s u b s t r a t e s u r f a c e w i t h a c h e m i c a l a g e n t t h a t l o w e r s t h e s u r f a c e e n e r g y , p r e v e n t i n g t h e s c r e e n e d p a s t e f r o m r u n n i n g i n m u c h t h e s a m e w a y t h a t t h e f r e s h l y - w a x e d s u r f a c e o f a n automobile doesn't allow water beads to spread out.

The small-sized precision resistors were realized by refining l a s e r t r i m m i n g t e c h n i q u e s t o w o r k w i t h s m a l l e r g e o m e t r i e s .

T h e n u m b e r o f p r o b i n g p a d s w a s r e d u c e d b y c o n n e c t i n g s e l e c t e d r e s i s t o r s t o c o m m o n n o d e s w i t h s h o r t i n g t a b s a n d o p e n i n g t h e t a b s w i t h t h e l a s e r a f t e r t h e r e s i s t o r s h a v e b e e n trimmed. The need for discrete chip capacitors was eliminated by using thick-film capacitors constructed with an interdigitated s t r u c t u r e c o a t e d w i t h a g l a s s f r i t t h a t h a s a h i g h d i e l e c t r i c constant.

A f o u r - d a y b u r n - i n o f e a c h c o m p l e t e d h y b r i d , p l u s s e v e r a l quality-assurance gates along the way, assures high reliability.

Finished circuits are thoroughly tested in only twenty seconds using an automatic test system designed for that purpose.

R i c h a r d D . T a b b u t t

the coupling modes and the x 100 attenuator, carry signal currents while the other five simply switch dc control voltages to integrated circuit Ul. This arrange ment, besides minimizing the number of components and simplifying assembly, also improves perfor mance by shortening the signal paths.

The preamp circuit Ul performs the conventional control functions of signal polarity selection, gain vernier control, channel switching and sync extrac tion, in addition to the six ranges of signal attenuation.

The trigger-view amplifier routes the trigger signal into the vertical channel at the output of Ul , as shown in Fig. 1. It is electronically switchable, so it can be sequenced with channels A and B to derive a three- channel display showing the time relationship between the sweep trigger and the signals in chan nels A and B.

The output of Ul drives the delay line. Resistors Rl and R2 terminate the delay line to prevent reflections.

Transistors Ql and Q2 are impedance converters that also function as dc level shifters.

Deflection factors to 1 mV/cm for both channels are provided by the x 5 magnifier controlled by transis tors Q3 and Q4. These transistors are normally satur ated, shorting out R3 and R4 to provide a low RC time constant at the input to U2. When transistors Q3 and

Q4 are switched off, the system gain is increased by a factor of five with a bandwidth of 40 MHz. At the same time, the positioning voltages are reduced by the same factor to maintain constant positioning.

Hybrid integrated circuit U2 provides a voltage gain of 50 for driving the CRT.

Preamplifier 1C

Further simplification of the overall vertical as sembly was achieved by placing most of the pre amplifier circuits for both channels on a single hybrid integrated circuit (Ul). The 25.4 x 34.9-mm ceramic substrate (see box at left) has 31 thick-film resis tors, 4 capacitors, and 3 monolithic chips. The two large chips are the channels A and B preamp circuits, each consisting of 27 transistors, 23 diodes, and 34 monolithic resistors. The third chip is a four-tran sistor differential shunt-feedback amplifier that drives the balanced delay line.

An abridged schematic of one of the preamp chips is shown in Fig. 2. Following the signal path starting at the input to the chip, transistors Q1-Q3 along with diodes D1-D4 form a de-controlled x 10 attenua tor in conjunction with laser-trimmed resistors RTl and RT2 on the hybrid substrate. The attenuator is ac tuated by biasing the lower end of resistor Rl to the appropriate negative voltage and allowing the lower end of R2 to float.

The xio attenuator is followed by triple-emitter transistors Q4 and Q5 and thick-film resistors RT3-

© Copr. 1949-1998 Hewlett-Packard Co.

T o D e l a y - L i n e D r i v e r

Preamplifier

Output

P o s i t i o n +

100

0 2 7 P o s i t i o n -

0 2 6

100

Polarity and

Vernier

Gain

022 Q23

Q24 025

Q21

Channel

O f f

1

Q20

O 1 9

+VB i i

0 1 7

Buffer

0 1 5

016

Q18

R6

T o S y n c

Circuit

+ 5V

External

Sync

Internal

+VA

Input

R T 1 1 8 0 0

0 2

0 1 0 3

D 1 D 2

D 3 D 4

R T 2 2 0 0

R 1 R 2

Preamplifier

Chip x 1 0 x 1 x 1 , x 1 0

A t t e n u a t o r - v

V

0 4

Sync Pick-Off

RT3

R T 4

R T 5

Q6

0 9

0 1 0

0 8

Q7

011

0 5

Sync

0 1 3 0 1 4 p 0 | a r i t y w O

012 x 1 , x 2 , x 4

Attenuator

LyvV^VvV

- 1 2 V

R 3 R 4 R 5

- x : x 1 x 4

$

- 1 2 V

- 4 V

-V*

-VC

F i g . 2 . c i r c u i t s . s c h e m a t i c o f o n e o f t h e t w o p r e a m p l i f i e r m o n o l i t h i c i n t e g r a t e d c i r c u i t s .

10

© Copr. 1949-1998 Hewlett-Packard Co.

F i g . 4 . H y b r i d o u t p u t s t a g e u s e s d i s c r e t e c h i p s f o r d r i v e r s .

F i g . 3 . P r e a m p c h i p h a s t w e n t y - s e v e n 2 - G H z t r a n s i s t o r s .

RT5 which constitute an attenuator with a 1-2-4 atten uation sequence. Range selection in this section is ac complished by grounding the lower end of resistor

R3, R4, orR5 to actuate the appropriate set of current- source transistors (Q6-Q11).

During range selection, this section cycles four times while the x 10 section cycles twice and the external x 100 section once to give twelve attenua tion ranges.

Sync Extraction

The sync signal is extracted at the outputs of tran sistors Q4 and Q5. As with other recent HP oscillo scopes, sync extraction precedes the polarity and gain vernier controls to prevent loss of triggering when these controls are adjusted. Transistors Q17 and Q18 invert the sync signal when they are turned on (and transistors Q15 and Q16 are turned off) by transistors Q13 and Q14. To switch the sync signal channel completely off, + 5V is applied to resistor R6.

Proceeding towards the output through buffer am plifier Q19-Q20, the next control functions are the gain vernier control and channel polarity. These two functions are accomplished by a four-quadrant multi plier configuration (Q22-Q25) that provides con tinuously adjustable gain over a 2.5:1 range while maintaining a constant dc bias current.

Channel switching is accomplished by double- emitter transistor Q21. When the base potential on this device exceeds the base voltages on transistors

Q22-Q25, it extracts and sums the currents that would flow to transistors Q22-Q25. The collector current of

Q21 divides equally into the lower emitters of Q26 and Q27 so the channel bias current remains con stant, maintaining the dc output level constant, but all signal information is lost.

Position modulation is accomplished by differen tially varying the bias currents injected into the upper emitters of Q26 and Q27.

The collectors of Q26and Q2 7 are connected to the corresponding collectors of the other preamp chip and to the input of a four-transistor delay-line driver.

This stage provides a current gain of 8 when driving the 180ÃÃ differential delay line.

Output 1C

The output amplifier (U2 in Fig. 1) consists of a

25-mm square ceramic substrate with nine thick-film resistors, one high-frequency monolithic chip con taining six transistors, and two discrete transistor chips for the final drive. The short signal paths af forded by the thick-film hybrid technology plus the performance of the HP transistors enabled these eight transistors to achieve a differential voltage gain in excess of 50 at a bandwidth of 150 MHz and with differential drive capability of 70 mA.

Acknowledgments

Ruth Buss, Gina Anderson, and Rose Stamps spent many hours developing prototypes of the hybrid cir cuits. Ken Fulton contributed to the special hybrid processing procedures and Joe Cochran developed the hybrid testing procedures. ^?

J o e K . M i l l a r d

A native of Maryville, Tennessee,

Joe Millard was involved with the d e s i g n a n d d e v e l o p m e n t o f nuclear instrumentation for seven years at the Oak Ridge National

Laboratory (Tennessee) before joining Hewlett-Packard in 1972.

He has BS, MS, and PhD degrees from the University of Tennessee.

Married, and with two children,

Joe golfs, skis, and hikes during leisure hours.

1 1

© Copr. 1949-1998 Hewlett-Packard Co.

A Real-Time Operating System with

Multi-Terminal and Batch/Spool

Capabilities

RTE-II, an advanced version of HP's real-time executive s y s t e m f o r 2 1 0 0 S e r i e s C o m p u t e r s , h a s s e v e r a l n e w f e a t u r e s t h a t a i d b o t h r e a l - t i m e m e a s u r e m e n t a n d c o n t r o l a n d c o n c u r r e n t b a c k g r o u n d a c t i v i t i e s s u c h a s p r o g r a m development.

by George A. Anzinger and Adele M. Gadol

ONE OF THE FIRST REAL-TIME operating sys tems to run on a 16-bit computer was Hewlett-

Packard's disc-based, multiprogramming Real-Time

Executive (RTE) system, introduced in 1968. Key fea tures of this system were a priority scheme for concur rent execution of multiple programs and a fore ground/background partition separating real-time tasks from non-real-time tasks. A powerful file man agement package was added later.

Experience gained in hundreds of RTE applica tions has now led to the development of RTE-II, an ad vanced version of this operating system. Major new capabilities are multi-terminal access to system re sources and an optional batch-spool monitor that supplements the file manager. Multi-terminal opera tion is aided by buffering of input as well as output, background swapping, resource locking, and class input/output, a system of buffering and queuing I/O requests according to class numbers. The batch-spool monitor supervises program development and other background jobs, using spooling, or buffering of input and output job streams, to maximize throughput.

The principal hardware environment for RTE-II is the HP 9600 Series of real-time measurement and control systems.1 RTE-II is also the operating system for central stations in HP 9700 Series Distributed Sys tems.2 Central processors in these systems are HP

2100 or 21MX Computers.3'4

Multi-Terminal Operation

One of the requirements for RTE-II was that the sys tem be able to handle multiple users at terminals, en gaged either in program development or in use of the system for its real-time function, which might be any thing from controlling a test to entering star charts in an observatory system. The central problems that were solved are common to many such uses.

The first of these problems was buffer manage ment. Each terminal must be able to send data to the program or programs controlling it without locking any program into main memory so that it cannot be moved to the disc; this occurs, of course, if the area of memory we wish to move to the disc is being used in part as an input buffer. It is also desirable to have the input in the program's memory, so that it can be protected from other users and may be moved to the disc when input is not going on. RTE has al ways used buffered output. The output buffer and control information for it are moved to a block of sys tem memory reserved for buffering; the actual output then takes place from this system memory, freeing the requesting program's buffer for further processing without waiting for the I/O device. In RTE-II we have provided for input buffering as well, by doing I/O from a reentrant subroutine, that is, a subroutine that can be shared by many programs. In the RTE system, reentrant subroutines contain a work space that the system moves to system available memory prior to reentering the subroutine (giving control of the sub routine to another program or process). The system restores this work space before it returns control to the interrupted process (see Fig. 1). Thus a program that has an active I/O request in progress may be moved to the disc in favor of a higher-priority pro gram, which may also use the same I/O routine. When such an I/O request is completed, the I/O buffer is in system memory and is moved back to the user pro gram's memory (as a side effect of restoring the work space) before it continues. By keeping the I/O buffer outside the user program while I/O is in progress but inside at other times the system minimizes its need for buffer memory and simplifies the protection of the system while allowing the program to be swapped.

(Swapping, as defined in the HP RTE systems, con sists of saving an executing program in its current state on the disc and replacing it in main memory

12

© Copr. 1949-1998 Hewlett-Packard Co.

[ A c t i v e

Program A

S t a t e ' S u s p e n d e d

I I / O S u s p e n d e d

Memory

Program B

State

Memory

Main Memory

System Memory

Active

Suspended

I/O Suspended

Memory

System Memory

F i g . 1 . R T E - / I p r o v i d e s f o r i n p u t b u f f e r i n g a s w e l l a s o u t p u t b u f f e r i n g b y d o i n g I / O f r o m a r e e n t r a n t s u b r o u t i n e . H e r e p r o g r a m A is processing in the reentrant sub routine when it is interrupted and c o n t r o l i s g i v e n t o p r o g r a m B . A t point 'a' program B calls the same reentrant subroutine, causing pro gram A 's work space in memory to b e m o v e d t o s y s t e m m e m o r y .

P r o g r a m B m a k e s r e p e a t e d c a l l s at '£>', 'c', and 'd', but memory is m o v e d o n l y o n c e . W h e n B i s s u s p e n d e d , p r o g r a m A ' s w o r k s p a c e is moved back and it continues in t h e s u b r o u t i n e f r o m t h e p o i n t of suspension.

with a program that was previously saved in the same manner or with a new program that is to be run from its primary entry point.)

A second problem was the need for background swapping. The background in an RTE system is an area of memory usually dedicated to running non- real-time tasks such as languages, editors, loaders, and other support programs. In HP RTE systems be fore RTE-II, background programs could not be swap ped. This was consistent with the primary function of the system being real-time activities, which usually run in the foreground, and not terminal activity. For

RTE-II, we wanted to add terminal activity and batch processing capability, which implies multiple edi tors, a batch monitor, and other non-real-time tasks that should not interfere with the foreground real time activity. Therefore, we have provided the abil ity to swap out a terminal program or the batch moni tor while waiting for an event to occur, such as completion of I/O or a subordinate program.

Third, provision had to be made for resource con trol. To allow several users at different terminals to access resources without interfering with each other, we have provided a locking mechanism. It is con trolled by the system, so if a program is aborted the lock will be removed. There are two types of locks.

In resource number (RN) locking, two or more co operating users assign a number to a resource, such as a section of code, that is to be used by their programs, but by only one at a time (Fig. 2). The operating system is restricted to allowing only one program to lock a given resource at a time and to queueing other requesting programs on the RN unlock. In logical unit (LU) lock ing, a program can lock an I/O device. (A logical unit in the RTE system is a number assigned to some I/O device.) The program has exclusive control of the device until it either unlocks the device or ter minates. This type of locking is very useful if the

I/O device is a line printer while it is not very useful for discs.

To access the multi-terminal capabilities of the sys tem, the user needs to be able to initiate a dialogue from any one of the terminals. This is accomplished by the multi-terminal monitor (MTM). MTM con sists of two very short programs which, when any key is struck on the terminal:

Identify the terminal and send a prompt to the ter minal, which identifies to the user the system ad dress of that terminal

Accept and execute any system command from the terminal

If the command is a program invocation, supply to the program the address of the terminal

Send any message resulting from the execution of the command back to the terminal.

To allow one program to handle more than one ter minal or device, it is necessary that it continue pro cessing while waiting for input/output. This was made possible by the Class I/O system (Fig. 3). In

F i g . 2 . R e s o u r c e n u m b e r ( R N ) l o c k i n g a l l o w s t w o o r m o r e c o o p e r a t i n g p r o g r a m s t o a c c e s s s e n s i t i v e a r e a s o f t h e i r code on a one-at-a-time-only basis. If program A gets to the lock first, B will be suspended until A unlocks that RN, at which t i m e B i s r e a c t i v a t e d . B m a y t h e n l o c k t h e R N , c a u s i n g A t o b e s u s p e n d e d i f i t r e q u e s t s a l o c k o n t h e s a m e R N .

13

© Copr. 1949-1998 Hewlett-Packard Co.

User Program

Class Queue

Head (One per Class)

(C)

(b)

C l a s s

N u m b e r

(d)

User Program

I/O Data Flow

Physical Memory

Move of Class Data

Logical Links

Class Number Pointer

U s e r D e v i c e P o i n t e r

Class Request Flow

(Logical Move)

Fig. 3. The Class I/O system makes it possible for a program t o c o n t i n u e p r o c e s s i n g w h i l e w a i t i n g f o r i n p u t / o u t p u t . W h e n a Class I/O request is made (a), the requesting user program s p e c i f i e s a c l a s s n u m b e r a n d a n I / O d e v i c e . T h e s y s t e m m o v e s t h i s i n f o r m a t i o n t o i t s m e m o r y a n d q u e u e s i t o n t h e s p e c i f i e d I / O d e v i c e ( b ) . T h e I / O d e v i c e d r i v e r t h e n m o v e s information to/from the buffer from/to the device. When the I/O i s c o m p l e t e t h e d r i v e r s i g n a l s t h e s y s t e m w h i c h , b y a l t e r i n g q u e u e p o i n t e r s , l o g i c a l l y m o v e s t h e c o m p l e t e d r e q u e s t t o the proper class queue (c). A user program, which may be the requesting program or another program, may now request in formation from this class queue (d). The system then moves t h e c o n t r o l a n d b u f f e r i n f o r m a t i o n t o t h e p r o g r a m ' s m e m o r y .

A p r o g r a m r e q u e s t i n g c l a s s i n f o r m a t i o n t h a t h a s n o t y e t r e a c h e d t h e c l a s s q u e u e i s s u s p e n d e d u n t i l t h e i n f o r m a t i o n is available.

the Class I/O system we have:

» Separated the I/O initiation and completion indica tions that a program makes and receives.

• Fully buffered I/O requests so the user need not worry about memory management or swappability.

Allowed a user other than the initiator to receive

I/O completion information, provided he knows the security code for the request.

• Provided a built-in dummy I/O device for program- to-program communication so that a program can control several I/O devices while also receiving data from another program.

The class I/O system has been used in HP dis tributed system software,2 in the spool system, and in the multi-terminal monitor. It has proved flexible enough to handle tasks not even remotely related to its originally intended functions.

The maximum number of classes is established at system generation time. Once the class numbers are established the system keeps track of them and as signs them (if available) to any program making a

Class I/O call with the class number parameter set to zero. Once the number has been allocated, the user can keep it as long as desired and use it to make mul tiple Class I/O calls. When the user is finished with the number it can be returned to the system for use by some other class user.

When the class user issues a Class I/O call the sys tem allocates a buffer from system available memory and puts the call parameters in the header of this buffer.

If the request is a WRITE or WRITE/READ the rest of the buffer is filled with the caller's data. If the request is a

READ the buffer will be filled when the I/O takes place.

The buffer is then queued on the specified logical unit. Since the system forms a direct relationship between logical unit numbers and I/O devices, the buffer is actually queued on an I/O device. If this is the only call pending on that device the device driver is called immediately. Otherwise the system calls the driver according to program priority. In any case the program continues immediately without waiting for I/O completion.

After the driver completes its task the system queues the buffer in the completed class queue. If the request was a WRITE only the header is queued.

The system then waits for a GET call to that class number. The header (and data, if any) are then returned to the program that issued the GET call. Notice that it may or may not be the same program that issued the original Class I/O request. The GET issuer has the option of leaving the buffer in the completed class queue so as not to lose the data, or dequeuing it and releasing the class number. Completed requests for a given class number are queued on a first-in/first-out basis.

An example of the use of Class I/O for program-to- program communication is as follows:

• User program PROGA issues a Class WRITE/READ call with the class number parameter set to zero and the logical unit number set to zero. This causes the

•A class WRITE/READ call is treated by the system as a class WRITE in that the buffer space in system a v a i l a b l e m e m o r y i s a l l o c a t e d a n d f i l l e d b e f o r e t h e I / O d r i v e r i s c a l l e d , a n d a s a c l a s s R E A D i n t h a t t h e e n t i r e b u f f e r ( a n d n o t j u s t t h e h e a d e r a s f o r a W R I T E c a l l ) i s q u e u e d a f t e r t h e d r i v e r c o m p l e t e s i t s t a s k

1 4

© Copr. 1949-1998 Hewlett-Packard Co.

Introduction to Real-Time Operating Systems

An operating system is an organized collection of programs t h a t c o m t h e p r o d u c t i v i t y o f a c o m p u t e r b y p r o v i d i n g c o m m o n f u n c t i o n s f o r u s e r p r o g r a m s . E x a m p l e s o f o p e r a t i n g s y s tems for specific purposes are:

• Timesharing (HP 2000)

• Disc Operating Systems (HP DOS-Ill)

• Real-Time Executive Systems (HP RTE-II/III)

A r e a l - t i m e c o m p u t e r s y s t e m m a y b e d e f i n e d a s o n e t h a t

" c o n t r o l s t h e e n v i r o n m e n t b y r e v i e w i n g d a t a , p r o c e s s i n g ( i t ) , a n d t a k i n g a c t i o n o r r e t u r n i n g r e s u l t s s u f f i c i e n t l y q u i c k l y t o a f f e c t t h e f u n c t i o n i n g o f t h e e n v i r o n m e n t a t t h a t t i m e . " 1 T h e f i r s t a p p l i c a t i o n s o f r e a l - t i m e m e a s u r e m e n t a n d c o n t r o l b y computer occurred in the late 1950's and early 1960"s. These p i o n e e r a p p l i c a t i o n s w e r e i n t h e c h e m i c a l a n d p o w e r i n d u s t r i e s a n d i n c o m m a n d a n d c o n t r o l i n t h e m i l i t a r y . T h e i r b a s i c f u n c t i o n s a r e s t i l l t h e b a s i c f u n c t i o n s o f t o d a y ' s i n d u s t r i a l computer systems, such as monitoring of sensors (analog and d i g i t a l ) , p e r i o d i c l o g g i n g , s c i e n t i f i c c a l c u l a t i o n , g e n e r a t i o n o f m a n a g e m e n t r e p o r t s , a n d p r o c e s s c o n t r o l . T h e s o f t w a r e o f t h e s e e a r l y s y s t e m s w a s t a i l o r e d t o e a c h a p p l i c a t i o n ; t h e r e w a s n o d i s t i n c t i o n b e t w e e n w h a t i s t o d a y c a l l e d t h e o p e r a t i n g s y s t e m s o f t w a r e a n d t h e s p e c i f i c a p p l i c a t i o n s o f t w a r e .

A l l s o f t w a r e d e v e l o p m e n t a t t h a t t i m e w a s d o n e i n a s s e m b l y language or machine language, and because of the high price o f t h e c o m p u t e r h a r d w a r e , a s y s t e m c o u l d b e j u s t i f i e d e c o n o m i c a l l y o n l y b y h a v i n g i t p e r f o r m m a n y d i f f e r e n t f u n c t i o n s .

The result was very high system development costs that were n o t s p r e a d o v e r m a n y s y s t e m s , b u t w e r e r e p e a t e d f o r e v e r y n e w a p p l i c a t i o n . O n l y i n t h e m i d d l e 1 9 6 0 ' s d i d t h e r e a l - t i m e o p e r a t i n g s y s t e m a p p e a r a s a s e p a r a t e e n t i t y t h a t c o u l d b e u s e d a s a b u i l d i n g b l o c k f o r e v e r y a p p l i c a t i o n , w i t h c o n s i d e r able savings in development cost.

T h e o p e r a t i n g s y s t e m s o f t w a r e i s p a r t o f t h e s y s t e m s o f t w a r e s u p p l i e d w i t h a c o m p u t e r s y s t e m . S y s t e m s o f t w a r e i n c l u d e s a s s e m b l e r s , c o m p i l e r s , o p e r a t i n g s y s t e m s , l o a d e r s , l i braries, and utilities (such as editors, debuggers, simulators, and diagnostics). These are the software tools needed for the d e v e l o p m e n t o f a p p l i c a t i o n s p r o g r a m s r e q u i r e d i n a p a r t i c u lar system. The operating system is in fact an extension of the c o m p u t e r s y s t e m h a r d w a r e ; i t h e l p s t h e a p p l i c a t i o n s p r o g r a m mer use the computer system resources without detailed knowl edge file the internal operation of I/O drivers, schedulers, file m a n a g e r s , a n d s o o n .

S o m e o f t h e i m p o r t a n t f u n c t i o n s o f r e a l - t i m e o p e r a t i n g s y s t e m s a r e t a s k m a n a g e m e n t ( p r o g r a m s c h e d u l i n g , r e s o u r c e a l l o c a t i o n ) , m e m o r y m a n a g e m e n t , i n p u t / o u t p u t s e r v i c e s , d a t a m a n a g e m e n t ( f i l e m a n a g e m e n t , b a t c h p r o c e s s i n g , I / O s p o o l i n g , l a n g u a g e p r o c e s s o r s , l o a d e r s , e d i t o r s , d e b u g g i n g t o o l s ) , a n d s y s t e m i n t e g r i t y ( p o w e r f a i l p r o t e c t i o n , m e m o r y protection, file security, error detection, etc.).

M a n y o f t h e c h a r a c t e r i s t i c s o f r e a l - t i m e o p e r a t i n g s y s t e m s t h a t b o o s t s p e e d a n d t h r o u g h p u t , s u c h a s m u l t i p r o g r a m m i n g , concurrent I/O operations, system integrity features, and so on, a r e o f a v e r y g e n e r a l n a t u r e a n d a r e p a r t o f m o s t c o m m e r c i a l o p e r a t i n g s y s t e m s t o d a y . E a r l y o b j e c t i o n s t o s u c h a g e n e r a l i z e d a p p r o a c h i n n o n - r e a l - t i m e a p p l i c a t i o n s , s u c h a s l a r g e r c o r e r e q u i r e m e n t s , h a v e m o s t l y d i s a p p e a r e d b e c a u s e o f t h e d r a m a t i c l o w e r i n g o f m e m o r y p r i c e s .

HP RTE Operating System Family

The operating system of HP's first computer, the 21 16A, was t h e B a s i c C o n t r o l S y s t e m ( 8 0 S ) , w h i c h w a s e s s e n t i a l l y a n I / O m o n i t o r . P r o g r a m m i n g w a s d o n e i n H P a s s e m b l y l a n g u a g e o r

H P F O R T R A N i n a m e m o r y - b a s e d e n v i r o n m e n t c a l l e d S y s t e m

Van Diehl

Input/Output (SIO). Since then the operating system software offered with 2100 Series Computers has evolved along several lines:

D O S ( D i s c O p e r a t i n g S y s t e m ) f o r s i n g l e u s e r p r o g r a m m i n g applications

• TODS (Test-Oriented Disc System) for automatic test appli cations

T i m e s h a r e d B A S I C f o r m u l t i p l e u s e r s p r o g r a m m i n g i n

BASIC

> RTE (Real-Time Executive) for real-time multiprogramming.

R T E w a s i n i t i a l l y d e v e l o p e d f o r d a t a a c q u i s i t i o n , m e a s u r e m e n t , a n d c o n t r o l . I t p r o v i d e s t w o e n v i r o n m e n t s f o r t h e u s e r , p h y s i c a l l y s e p a r a t e d i n m e m o r y . B a c k g r o u n d i s f o r p r o g r a m development tasks such as running a compiler or an editor. As t h e t e r m s u g g e s t s , a p r o g r a m r u n n i n g i n t h e b a c k g r o u n d i s a l l o w e d t o r u n w h e n n o t h i n g m o r e i m p o r t a n t n e e d s t o b e r u n .

F o r e g r o u n d i s f o r t i m e - c r i t i c a l o r r e a l - t i m e a p p l i c a t i o n s . F o r e g r o u n d i s p r o t e c t e d f r o m b a c k g r o u n d b y a h a r d w a r e m e m o r y - protect fence, which prevents background programs from mod i f y i n g t h e c o n t e n t s o f a n y f o r e g r o u n d m e m o r y l o c a t i o n , t r a n s ferring control to the foreground, or performing I/O. Any such at t e m p t s a r e i n t e r c e p t e d b y t h e s y s t e m a n d e x a m i n e d f o r l e g i t i macy, providing a high level of integrity for the foreground area.

Programs not currently running may be swapped to disc. Time o r e v e n t s c h e d u l i n g o f p r o g r a m s i s p r o v i d e d . A p r i o r i t y s t r u c ture is provided and the system is optimized for response to the needs of real-time tasks. To further improve interrupt response where necessary, a privileged interrupt capability was added.

With this capability the user can bypass the system entirely to service interrupts from devices chosen to be privileged.

RTE-C, a core-based version ("core" is what we called mem ory in the old days) is a later member of the RTE family, intend e d f o r a w h e r e t h e e n v i r o n m e n t w i l l n o t t o l e r a t e a d i s c , o r w h e r e t h e a d d e d c o s t o f t h e d i s c i s p r o h i b i t i v e . A s i n

RTE, background and foreground areas are provided. Primary differences from RTE are that there is no disc for mass storage, a n d p r o g r a m p r e p a r a t i o n c a n n o t b e p e r f o r m e d c o n c u r r e n t l y with real-time tasks.

Still later, to provide a simpler, more interactive facility for pro g r a m m i n g r e a l - t i m e t a s k s , R T E - B w a s c r e a t e d , o f f e r i n g r e a l time BASIC as a programming language in a very simple mem ory-based operating system.

T o s a t i s f y u s e r s ' d a t a h a n d l i n g r e q u i r e m e n t s a n d t o p r o v i d e a n i m p r o v e d i n t e r f a c e t o t h e s y s t e m , a g e n e r a l - p u r p o s e f i l e m a n a g e r w a s a d d e d t o t h e R T E s y s t e m . 2 A p o w e r f u l d i s t r i b u t e d s y s t e m s c a p a b i l i t y w a s a d d e d t o p e r m i t t h e u s e r t o create networks of systems with an RTE system functioning as the central station.2

T h e R T E - I I s y s t e m ( a r t i c l e , p a g e 1 2 ) w a s d e v e l o p e d t o i m p r o v e R T E ' s p e r f o r m a n c e i n i t s p r i m a r y a p p l i c a t i o n s o f m e a surement and control as well as enhancing its usefulness as a g e n e r a l - p u r p o s e c o m p u t a t i o n a l s y s t e m b y a d d i t i o n o f a b a t c h capability, input and output spooling, a multi-terminal monitor, a n d a n e w e d i t o r . R T E - I I I ( e x t e n d e d m e m o r y ) a n d m u l t i - u s e r real-time BASIC represent the latest additions to the RTE fami l y . R T E - I I I i s d e s c r i b e d i n t h e a r t i c l e o n p a g e 2 1 . M u l t i - u s e r real-time BASIC will be described in a later issue of the Hewlett-

Packard Journal.

References

1 J M a r t i n . " D e s i g n o f R e a l - T i m e C o m p u t e r S y s t e m s , " P r e n t i c e - H a l l , E n g l e w o o d

Cliffs, N.J.. 1967. p.5

2 S D i c k e y . " D i s t r i b u t e d C o m p u t e r S y s t e m s . " H e w l e t t - P a c k a r d J o u r n a l . N o v e m b e r

K e n n e t h A . F o x

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system to allocate a class number, if available, and the request to complete immediately. Logical unit zero is a dummy I/O device.

• When the WRITE/READ call completes, PROGA's data will have been placed in the buffer and this fact recorded in the completed class queue for this class.

• PROGA then schedules PROGB, the program receiv ing the data and passes to PROGB, as a parameter, the class number it obtained. i When PROGB executes it picks up the class number and issues a Class I/O GET call to the class. PROGA's data is then passed from the system buffer to

PROGB' s buffer.

Another application of Class I/O is in the operation of the SPOUT program (see below).

Program Development

Before a newly delivered system can become use ful (unless its intended use is program development) programs must be developed to solve the users' prob lems. The development of programs will, in most cases, continue for the life of the system as the user ex pands or changes his processes.

Program development proceeds as shown in Fig.

4. The program is written and translated into a ma chine-readable format. It enters the language proces sor (compiler or interpreter); if errors are found the source code is edited. The code from the language processor is combined with library subroutines and

New Code

Minor Flow

• — Control

(Linkage

Edit)

Good

Program

F i g . 4 . A m o d e l o f t h e p r o g r a m d e v e l o p m e n t c y c l e , s h o w i n g t h e u t i l i t y p r o g r a m s t h a t p l a y r o l e s i n i t . F o r R T E - I I , m a j o r improvements have been made in the editor and loader, and a n e w b a t c h / s p o o l m o n i t o r h a s b e e n d e v e l o p e d .

linked to the system. The resultant program is tested for correct function. In the rare case where it passes all tests, the program is "developed" and activity on it stops here until a failure is discovered by unsatis fied users or a logic error appears. Fixes are made to the source program to correct logic or design errors or to add features. The development loop now closes by going back through the language processor.

While traversing this loop we invoked a language processor, a loader, the user's program, and an editor.

To ease the path around the loop in RTE-II we pro vide a high-level set of control programs, the batch/ spool monitor. In the RTE-II development project considerable effort went into enhancing the editor, the loader, and the batch control capability.

The RTE-II system has a new program editor, de signed to make it easy to edit programs (it comes in second best on text). The editor is inherently string and line oriented. It can find, replace, and delete strings. It can easily insert, replace, or delete charac

ters in a line. It talks to the file system and it is fast.

The loader was enhanced in control capability, but the primary effort was aimed at improving its speed.

To this end the system generator now provides a dic tionary for all library entry points, and a study of where the loader spent its time led to faster symbol ta ble search routines.

System enhancements for batch/spool consist of an

LU switch capability, a batch clock and a break re quest. LU switch is a mechanism that allows pro grams running under control of the batch monitor to talk to a given logical unit while the actual LU is some other device. The batch monitor sets up the switches in a table that is accessable by the I/O sys tem. Only programs running under the batch moni tor are switched. This allows the batch monitor to switch output for the printer, for example, to a spool file from which it will be printed at a later time. The batch clock is an execution-time clock that is ad vanced every time the system clock is advanced

(each 10 milliseconds), but only if a batch program is running. If the batch clock goes to zero it indicates a run-time limit has been exceeded and the offending program is aborted by the system. Batch elapsed time is not kept, since it is meaningless in a multiprogram ming system. The break request is a system request which sets a flag for the specified program. The pro gram may examine this flag and take any action it deems appropriate. When the batch monitor sees this flag it will abort any job it is running, or, if not in a job, will stop whatever it is doing and go back to the terminal for commands.

Batch/Spool Capability

The RTE-II batch and spooling capability is an ex tension of the file management package of RTE. The

16

© Copr. 1949-1998 Hewlett-Packard Co.

Directory

Access

Schedule with Wait

Program

Call

User

Program

Schedule with Wait

Program Call

Batch

Library

(Utilities)

File

Access

F i g . 5 . R T E - / I b a t c h a n d s p o o l i n g c a p a b i l i t i e s a r e a n e x tension of the RTE file management package, an optional set of programs and utility subroutines. FMGR is the interface be t w e e n t h e u s e r a n d t h e f i l e s y s t e m . D R T R m a n a g e s t h e f i l e d i r e c t o r y . T h e b a t c h l i b r a r y h a n d l e s p r o g r a m c a l l s t o t h e file system.

file management package consists of a set of pro grams and utility subroutines that are physically op tional and independent from the RTE operating sys tem (see Fig. 5). The utilities are callable from user programs. The background program FMCR provides the interactive and/or batch interface between the user and the file system. The program D.RTR manages the file directory.

To add more extensive batch capability and a spooling function the interactive capability of FMGR was extended to provide such features as global param eters, which give the user the ability to write com mand procedures. Second, the FMGR command set was enlarged to provide commands for specific con trol of spooled operation. Finally, programming was added to effect input and output spooling for in creased throughput.

Global parameters may be substituted for param eters in any of the FMGR commands. When the sys tem encounters a global parameter it goes to a lookup table to get the current value of that parameter. Some global parameters may be set by the user and others are used by the system.

A typical transfer file, or command procedure, us ing global parameters might look like this:

:ST,1G::2G, 1G::3G

:PU,1G::2G

:TR

This set of commands could be placed in a file named

MOVE. Then the command :TR, MOVE, TEST, 2, 10 will cause the file named TEST to be moved from car tridge number 2 to cartridge number 10. The user has supplied the values TEST, 2 and 10 for global param eters iG, 2G, and 3G, and these values are put in the lookup table upon execution of the TR command.

Commands added to FMGR allow the user to set global parameters and do arithmetic and logical oper ations on them, to do conditional branching, and to print messages on various devices.

Spooling, or buffering of input and output job streams on the disc, was developed to increase throughput of the system while running tasks in batch mode. The spooling package is an option to the file management package, which itself is an option to RTE.

Input spooling in the RTE system is the reading of jobs from low-speed I/O devices to the disc, from which they are executed. Output spooling is the writ ing of job output to the disc and from there to the I/O devices. Spooling allows jobs to run at disc I/O speed instead of slower card reader or line printer speeds.

Tracing the progress of a batch job through the sys tem makes clearer the interaction between the var ious pieces. Batch operation without spooling is quite simple and can be represented as shown in Fig. 6a.

Note that job commands are read by FMGR directly from the input device and output is done directly to the output devices. This ties up the devices during processing and limits the job to the I/O speeds of these devices.

The addition of spooling to batch operation compli cates the picture. Fig. 6b represents batch operation with the addition of spooling.

The important feature represented by Fig. 6b is that the operations of inspooling, batch processing, and outspooling take place in parallel. Note that in put is now read directly by the inspooler JOB and writ ten to spool files, one job per file. The operator runs

JOB rather than FMGR. First JOB calls SMP to assign a spool access information table and associated unit number to the file and open it for I/O. Thereafter, JOB writes to this assigned unit as if it were a standard I/O device, and the writes are translated to the spool des tination. When a job is completely read in, JOB puts a notation of this job on the job queue (in JOBFIL) and stores its location information in JOBFIL. JOB schedules

FMGR to start processing (unless it is already executing) and then continues to inspool other jobs.

When FMGR is ready to process a job, it searches JOB

FIL for the highest-priority job and prepares it for pro cessing. It sets up spool files for standard input and output units and puts the spool unit numbers into the batch LU switch table, which equates two units for the duration of the batch job. Thereafter, requests to these standard units will be translated to spool un its and ultimately spool files. The program SMP moni tors the created files, maintaining an outspool queue of files (in SPLCON) to be dumped for each device. It sends instructions to SPOUT, which runs continuous ly, by means of Class I/O telling it when to start files or try to lock a device in preparation for outspooling.

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© Copr. 1949-1998 Hewlett-Packard Co.

(a)

W i t h o u t S p o o l i n g

(b)

W i t h S p o o l i n g

I n s p o o l i n g

I n p u t

I n p u t

S p o o l e r

I n p u t

B a t c h P r o c e s s o r

O u t p u t

D e v i c e s

B a t c h P r o c e s s i n g

S p o o l F i l e s

B a t c h

P r o c e s s o r

O u t s p o o l i n g

S p o o l F i l e s

O u t p u t

S p o o l e r

O u t p u t

Devices

f e S P L C O N

I n f o r m a t i o n F l o w

C o n t r o l F l o w

F i g . 6 . I n p u t / o u t p u t w i t h a n d w i t h o u t s p o o l i n g . T o u s e s p o o l ing, the user runs JOB instead of FMGR. JOB writes input to spool files on the disc and stores their locations and priorities in JOBFIL. FMGR then processes the jobs according to priority.

S M P m o n i t o r s t h e s p o o l f i l e s , m a i n t a i n s a n o u t s p o o l q u e u e

(in SPLCON) for each device, and sends instructions to SPOUT, the output program.

Identification of the file SPOUT is dumping and of the destination device is carried in the extra parameters of the class request. Stored in the access table of the file being dumped is the number of I/O requests pend ing. When SPOUT starts dumping a file, it reads and writes (using Class I/O) four records, increasing the pending count each time a record is written. There after, the count is decreased each time a successful completion is indicated and increased (up to 4) each time a record is written. The count determines the program flow between the GET requests and the read/ write loop.

Passage of blocks of information is also carried out through use of class write/read requests to LU#0

(dummy). SPOUT, in addition to detecting comple tion of writes, receives all its operating information through the same GET request. SMP write/reads the

SPOUT control information on the same class that

SPOUT uses to control the I/O devices. SMP also re ceives spool file information for spool setup using a class write/read on a different class.

The batch timer allows FMGR to keep track of the amount of time a job or program takes by sampling the timer contents at the beginning and end of a job.

The user may also set time limits on jobs and pro grams running under the jobs so that these will be ter minated if still running at the end of their limit.

Background swapping is necessary for batch opera tion, since FMGR must run user programs which are most likely background disc resident. This implies that FMGR must be swapped out.

It is batch LU switching that attends to translating

I/O requests generated by batch processing from the

"normal" LU to the spool LU corresponding to the ap propriate spool file. This feature allows transparency of spooled operation to the programs running under batch.

The spooling capability may be tapped from out side the batch stream, although not automatically. A program may spool its output by following very much the same procedure that FMGR must follow to prepare a job to run under spooling.

Several of the new system features of RTE-II have been instrumental in the implementation of spool ing. The resource number capability is used to con trol access to the spool control files. The LU locking capability allows the outspooler (SPOUT) to lock the devices it is dumping to for the duration of time it takes to output a single file. When spooling is used, the output from each job is guaranteed to be dumped in one piece.

Class I/O enables a particular implementation of

SPOUT, which handles simultaneous outspooling to several devices and keeps several I/O requests pend ing for each device. Output to devices is written us ing class write and control requests; completion of these requests is indicated by a successful class GET.

General Enhancements

Besides its multi-terminal and batch/spool capabil ities, RTE-II embodies a number of general and per formance enhancements. General enhancements were made in the areas of memory management, swap control, power-fail/auto-restart, and microcode subroutine replacement.

When doing output to a buffered device the pre vious RTE system would allow all of memory to be used by that one device. This meant for example, that if a file was being punched all free memory would be filled with punch data. Furthermore, each time mem ory became available all contending users would be reactivated regardless of whether there was enough memory to satisfy any of the users. This al lowed a low-priority program to lock out a higher- priority program requiring a larger block of memory.

The low-priority program would use all the short

18

© Copr. 1949-1998 Hewlett-Packard Co.

blocks of memory and thus not allow any larger block to accumulate. To solve this problem the sys tem now keeps track of the amount of memory each waiting program needs and reactivates all programs waiting for memory only when it has enough memory to satisfy the highest-priority waiting program. This al lows high-priority programs to bid successfully for large blocks of memory. The system also enforces up per and lower buffer limits on memory queued on any I/O device. When a program makes an I/O request to a device which already has more than the upper- limit number of words of buffer memory queued on it the program is put in a buffer limit suspension.

When an I/O device completes a request and causes memory to be returned, a check is made to see if the number of words of buffer memory in the device's queue is less than the lower limit. If it is, all programs in buffer limit suspension on this device are reacti vated. This results in a kind of hysteresis that allows lower-priority programs enough time to do useful work before they are swapped out, while still keep ing the I/O device busy (see Fig. 7).

We have also optimized the memory management routine to cut down system overhead. This was done by minimizing code within loops (usually at the ex pense of extra code outside the loops], and by keep ing track of the largest block of memory available to allow rejection of requests for unavailable memory without an exhaustive search. Because constantly keeping track of the largest block could become time- consuming, a modified algorithm is used. Whenever memory is returned a check is made to see if the re sulting block, after mergers with any contiguous mem-

Program

Suspended for Buffer

Limit

T i m e

Fig. 7. Improved memory management is a feature of RTE-II.

The system enforces upper and lower buffer limits on memory queued on any I/O device. A program making an I/O request w i l l b e s u s p e n d e d i f t h e b u f f e r m e m o r y q u e u e d o n t h e r e q u e s t e d d e v i c e e x c e e d s t h e u p p e r l i m i t . S u s p e n d e d p r o g r a m s a r e n o t r e a c t i v a t e d u n t i l t h e q u e u e d m e m o r y d r o p s b e l o w t h e l o w e r l i m i t . T h i s h e l p s g i v e l o w - p r i o r i t y p r o g r a m s t i m e t o d o u s e f u l w o r k b e f o r e b e i n g s w a p p e d o u t .

ory, is larger than the largest known block. If so, the block is the new largest block. We don't change this value when memory is allocated, however. This means the system may have less memory than it thinks it has and therefore it will attempt to find mem ory for a request it cannot satisfy. But it can update the current largest-block information at the end of an unsuccessful allocation attempt and thus prevent any further fruitless searches. This turns out to be more efficient than searching for a new maximum block after each allocation.

When background swapping was implemented it became clear that some programs would not run if they were swapped, usually because of timing con siderations. To solve this problem a memory lock re quest was added. This allows a program to request of the system that it not be swapped out of memory. In some installations this could prove undesirable, so a switch must be set at generation time to allow the sys tem to service the memory lock request. We also found that most background programs used unde clared memory (memory between the last word used by program code and the last word in the program's area) for such things as symbol tables. For this reason a swap option has been included to swap all of the area or only the declared memory. This option is de faulted to all of memory for background programs and to only declared memory for foreground pro grams, but a system request is provided to alter the option.

Power-fail/auto-restart routines were developed which, while independent of specific I/O devices, yet restart all restartable devices. Also, a program is run at power-up which sends a power-failed message to all the terminals. This program is written in FORTRAN and its source code is provided with the system so the user may modify it to do special things for his installation.

The proliferation of microcode subroutine replace ments had gotten to the point where a fair amount of time and memory was spent just calling and execut ing dummy subroutines to replace the invocation with an op-code. For example, when a multiply sub routine was replaced by microcode, the multiply software would be replaced by a dummy subroutine consisting principally of the op-code corresponding to the new microcode. The RTE-II system solved this problem by having the generators and the on-line loader replace the invocations at generation or load time. The user need only type in the entry point and its microcode replacement op-code and the system takes care of the rest.

Performance Enhancements

Several changes were made to the system to im prove performance and reduce system overhead.

19

© Copr. 1949-1998 Hewlett-Packard Co.

A more efficient time-keeping routine keeps the time of day in tens of milliseconds. Time is kept in double-word integer format, cutting the memory re quired from four words to two words. More impor tantly, it puts time in one base (hours was kept in base 24, minutes and seconds in base 60, and tens of milliseconds in base 100). This makes it twice as fast to test programs in the time list and makes updating their next run-time considerably easier and faster.

The dispatching algorithm was modified to cor rect false starts. The system may be loading a pro gram when a higher-priority program is scheduled.

In this case the previous system would finish the load and then swap the program without running it.

RTE-II will either abort the load or, if the program is already in core, simply overlay it — it wasn't run, so the copy on the disc is still intact.

The dispatching algorithm was also modified in several areas to eliminate redundant processing. The system no longer checks for a possible content switch (i.e., changing the executing program) unless a change in some program's status occurs. Also, once a decision has been made that a given program is not swappable, no further swap checks are made for that area on the current pass through the dispatcher. Pre viously all programs contending for an area would force a swap check.

The dispatching algorithm was also modified to de tect when a program being swapped has priority over the contender and, even though not currently exe cuting, is scheduled to run within a short (user- selectable) time. In this case the swap is not done since to do so would likely result in a reswap to get the program back into memory before the contender has any cpu time.

Having done all these things we were worried about the amount of memory used in the system. To address this problem we optimized the operating sys tem code so that, in most cases, it uses less memory than the previous system. We also shortened some of the memory-resident tables, thus freeing consider able memory. The result is that the system is only a lit tle larger than the previous system and does more things faster and better than before.

Acknowledgments

We are indebted to many people who provided guid ance and help during the project. In particular, we wish to acknowledge Prem Kapoor for the work on the loader; Gene Wong for work on memory manage ment and other loose ends; Ray Brubaker, Linda Aver- ett, Marge Dunckle, Gil Seymour, and Dave Snow, who all helped translate the results into a useful prod uct; Van Diehl for his capable product manage ment; Steve Stark, Christopher Clare, Pete Lindes,

Joe Schoendorf, and others, who provided ideas that shaped the final product; Shane Dickey and Earl

Stutes for their help defining and using Class I/O;

Tom Sapones and Dick Cook for work on the editor;

Larry Pomatto for his help and support in providing hardware; Mike Chambreau, Ken Fox, and Gary

Smith for their management; Joe Bailey, John Tru- deau, Doug Baskins, and the rest of the support group for their ideas and prerelease control and test ing efforts. >i

References

1. "Modular Systems for Sensor-Based Data Acquisition and Control," Hewlett-Packard Journal, August 1972, page 15.

2. S. Dickey, "Distributed Computer Systems," Hewlett-

Packard Journal, November 1974.

3. Hewlett-Packard Journal, October 1971.

4. Hewlett-Packard Journal, October 1974.

Adele M. Gadol

I Adele Gadol was responsible for

| the batch/spool portion of RTE-II.

B o r n i n N e w Y o r k C i t y , s h e a t t e n d e d t h e U n i v e r s i t y o f M a s s a chusetts and the University of

Michigan, graduating from the l a t t e r i n 1 9 6 9 w i t h a B S d e gree in mathematics. During the next three years she worked

' a s a p r o g r a m m e r a n d c o n t i n u e d her studies at the University of

Michigan, receiving her MS

I degree in computer, information, and control engineering in 1972.

. She joined HP the same year.

A d e l e a n d h e r h u s b a n d , a n H P s o f t w a r e d e s i g n e r , l i v e i n S a n

Jose, California. She's an active member of the local chapter of

ACM, and enjoys music (she plays flute), tennis, and swimming.

G e o r g e A . A n z i n g e r

1 G e o r g e A n z i n g e r h a s b e e n i m p r o v i n g a n d e x p a n d i n g t h e H P

.RÃE system since 1971. He de-

( v e l o p e d t h e m o v i n g - h e a d s y s t e m

¡ software and the file management package for RTE, and did most of

I the system modifications for RTE-I I .

' George spent four years in the

U.S. Navy before enrolling at the

! University of Wisconsin, where he earned his BSEE degree in 1968.

' He received his MSEE from Stan-

• ford University in 1969 and joined

HP the same year. The Anzingers —

I George and his wife and their two small daughters — make their home in the Santa Cruz Moun tains, a few miles from George's office at the HP Data Systems

Division in Cupertino, California.

2 0

© Copr. 1949-1998 Hewlett-Packard Co.

Real-Time Executive System Manages

Large Memories

RTE-III does everything other HP real-time executive s y s t e m s d o , a n d a d d s l a r g e - m e m o r y m a n a g e m e n t ( u p t o

2 5 6 K w o r d s ) u s i n g H P ' s d y n a m i c m a p p i n g s y s t e m .

by Linda W. Averett

RTE-III IS A MULTI-PARTITION, real-time, multi p r o g r a m m i n g o p e r a t i n g s y s t e m t h a t s u p p o r t s up to 256K words of main memory. The latest in a se ries of upward-compatible, field-proven RTE's for

HP 21MX Computers, RTE-III provides the user with all the features of RTE-II (see article, page 12) plus the following additional features:

• Increased system buffer area

• Increased program area

• More program linkage area

• Greater multiprogramming throughput by allow ing up to 64 disc-resident programs to be simul taneously resident in memory

• Greater user protection via the use of a hardware fence and a memory protect feature.

Uses Dynamic Mapping System

RTE-III uses the dynamic mapping system,1 a hard ware option for HP 21MX Computers, to perform the logical-to-physical mapping necessary to use more than 32K words of physical memory. The dynamic mapping system has a set of four maps, each of which consists of 32 hardware registers and describes a 32K address space in memory. The four maps are the sys tem map, which is automatically enabled on inter rupt, the user map, which is enabled by the system be fore passing control to a user program, and the port A and port B maps, which are automatically enabled during a memory transfer involving the dual-channel port controller (DCPC).

A 15-bit address, sufficient to address 32K words of memory, is used in HP 21MX Computers. When the dynamic mapping system is enabled, this 15-bit address is split into two parts. The lower ten bits of the address become a relative displacement in a page in memory. The upper five bits of the address specify one of the hardware registers in the map that is cur rently enabled. The address of the physical page in memory is picked up from the indicated map register, and the page displacement is appended to it. Thus, the target address is derived by a mapping from a 32K logical memory space to a physical memory as large as 256K words. This mapping process does not slow down memory accesses.

Memory Organization

P h y s i c a l m e m o r y i s o r g a n i z e d i n t o b u i l d i n g blocks (see Fig. 1). The base of the building block structure, beginning at physical page zero in mem ory, consists of the system links and communication area, the operating system, and the resident library.

The first building block is the common area, followed by the memory-resident program area and the system available memory area. The remaining memory is divided into partitions that are used for executing

2 5 6 K

3 2 K

D i s c R e s i d e n t P a r t i t i o n N

P a r t i t i o n N B a s e P a g e

D i s c R e s i d e n t P a r t i t i o n 1

P a r t i t i o n 1 B a s e P a g e

S y s t e m A v a i l a b l e M e m o r y

M e m o r y R e s i d e n t P r o g r a m s

S y s t e m L i n k s . C o m m u n i c a t i o n A r e a .

M e m o r y R e s i d e n t L i n k s

B u i l d i n g

B l o c k N + 4

B u i l d i n g

B l o c k 4

B u i l d i n g

B l o c k 3

B u i l d i n g

B l o c k 2

B u i l d i n g

B l o c k 1

B a s e o f

B u i l d i n g

B l o c k

S t r u c t u r e

F i g . 1 . T h e R T E - I / I r e a l - t i m e e x e c u t i v e o p e r a t i n g s y s t e m manages up to 256K words of physical memory, arranged in to building blocks as shown. Sizes of the building blocks are determined by the user at system generation time within cer tain minimum and maximum limits.

21

© Copr. 1949-1998 Hewlett-Packard Co.

RTE-III Definitions

Map — a set of 32 hardware registers in the dynamic mapping system. Used to translate a logical 32K address space to a

3 2 K s e g m e n t o f a 2 5 6 K p h y s i c a l a d d r e s s s p a c e .

Page — 1K (1024 decimal) words of memory.

DCPC — Dual-channel port controller with two assignable chan n e l s f o r p e r f o r m i n g d i r e c t m e m o r y a c c e s s e s .

Partition — a fixed area in memory consisting of a user-deter mined number of pages. It is used for executing disc-resi d e n t p r o g r a m s .

Disc-Resident Program — a program that resides on the disc a n d m u s t b e l o a d e d i n t o m e m o r y t o b e e x e c u t e d .

Memory-Resident Program — a program that is always resident in main memory.

S w a p â € ” t h e a c t i o n o f w r i t i n g a d i s c - r e s i d e n t p r o g r a m t h a t i s executing in memory onto the disc so another disc-resident p r o g r a m c a n b e l o a d e d a n d e x e c u t e i n t h a t s a m e a r e a . disc-resident programs. The user may determine the size of all these building blocks at system generation time within certain minimum and maximum limits.

The building blocks of physical memory can be arranged into different structures within the logical address space by use of the dynamic mapping sys tem. At any instant a 32K logical address space is de scribed by the map that is enabled. A key benefit is that the building blocks do not all have to fit into this

32K space at the same time. Thus, the individual blocks do not detract from the address space of the other blocks.

Fig. 2 indicates what the 32K address space may look like when the system map or the user map is ena bled. All execution of code takes place under one of these two maps. The two DCPC maps are used only during a high-speed direct memory access.

Multi-Partition System

While RTE-III provides larger user areas by means of the dynamic mapping system, its major benefit is increased multiprogramming throughput. RTE-III can have up to 64 partitions. Thus at any instant, 64 disc-resident programs, in addition to the memory- resident programs, can be resident in memory.

Being able to have more than two disc-resident program execution areas (partitions) decreases the probability of having to do program swapping. It is approximately 100 times faster to switch between two programs that are resident in memory than it is to swap using a 7900A Disc Drive (50 times faster for a

7905A Disc Drive). Thus in a multiprogramming en vironment, multiple partitions can greatly decrease the amount of time necessary to switch between pro grams.

The multiple partitions also improve the response of the RTE multi-terminal monitor (see article, page

12), because it is more likely that there will be mem ory available for the monitor when it is required.

Memory Management

The memory available for program execution is divided into two areas. One is the memory-resident program area, which is established at system genera tion time and does not change, and the other con tains up to 64 partitions for program execution.

Any disc-resident program may be assigned to run in any partition that is large enough. If a disc-resi dent program is not assigned to a partition, it will be dispatched into any partition that is available and is big enough. If a partition is not available, then the al located partitions will be examined to determine if one is swappable.

To give the user more control over which pro grams compete for memory, RTE-III provides for de fining two types of partitions, real-time and back ground. There is no functional difference between these partition types, but unless a program is as signed to a specific partition, it will run in a partition of the same type. In other words, by default, real-time programs will run in real-time partitions, and back ground programs will run in background partitions.

Thus the user has the following capabilities for controlling partitions:

• Up to 64 partitions of varying lengths can be defined

» Partitions can be separated into two types

« Programs may be assigned to a specific partition

• Programs may be locked into a partition

• Partitions may be reserved for assigned programs.

Dispatching

RTE-III keeps track of the type and size, the alloca tion status, and the priority and status of the resident of each partition. When a disc-resident program is ready to be executed, the system checks first to see if the program is already resident in a partition. If it is, the hardware user map registers are loaded with the addresses of the physical memory pages that make up that partition, and the program is given control. If it is not resident, the system checks to see if the pro gram is assigned to a partition. If so, and if that parti tion is free, the program is loaded into it and dis patched. If the partition is not free, the system will determine if a swap is possible.

If the program is not assigned to a partition the sys tem will find the smallest free partition that is long enough for the program. If a free partition does not ex ist, the system looks for the partition that is long enough and contains the lowest-priority resident that qualifies for a swap. If a suitable partition is found, the user map is loaded with the addresses of the mem ory pages in that partition, the swap (or load if the partition was free) is performed, and the program is given control.

2 2

© Copr. 1949-1998 Hewlett-Packard Co.

Described by

System Map

System

Memory

Resident

Program

Three Possible Configurations

Described by User Map

Disc Resident

Program and

Common

Unused Area

Read Write

Protected

Disc Resident

Program, without

Common

32 K

I

System

Available

Memory

Memory

Resident

Program 2

Memory

Resident

Program 1

i

?

è

Disc

Resident

Program

I f

(Common

Optional in

System Map)

1 3 K

Resident Resident Resident Resident

Communication

Area. System

Links and

Resident

P r o g r a m L i n k s

Communication

Area. System

Links and

Resident

Program Links

Communication

Area. System

Links and

Program Links

( 1 ) ( 2 ) ( 3 )

Indicates Possible Memory Protect Fence Settings

When a suitable partition cannot be found, the pro gram will remain scheduled and the system will try to dispatch it the next time it scans the scheduled list. This is why multiple partitions speed up multi programming throughput. The more partitions the system has, the less the probability that a swap will be necessary to execute the program, and the less the probability that the program will have to wait on memory.

Because memory-resident programs are always in memory, the system does not have to locate a parti tion to dispatch these programs. When a memory- resident program is ready to execute, the system loads the user map and gives control to the program.

Fig. 2 shows three possible configurations of the

32K logical address space that can be described by the user map for memory-resident and disc-resident programs.

Communication

Area. System

Links and

Program Links

( 4 )

F i g . 2 . R T E - I I I u s e s t h e d y n a m i c m a p p i n g s y s t e m , a h a r d w a r e o p t i o n f o r H P 2 1 M X C o m p u t e r s , t o c o n f i g u r e e a c h p r o g r a m ' s 3 2 K l o g i c a l m e m o r y s p a c e u s i n g t h e b u i l d i n g b l o c k s o f p h y s i c a l m e m o r y . A l l e x e c u t i o n o f c o d e t a k e s place under either the system map or the user map. Each map is a set o f h a r d w a r e r e g i s t e r s w h o s e c o n t e n t s t e l l h o w t o t r a n s l a t e l o g i c a l m e m o r y a d d r e s s e s t o p h y s i c a l m e m o r y a d d r e s s e s .

Program Protection

RTE-III provides greater program protection than the other RTE systems. The memory protect fence is used, as it is in RTE-II, to provide protection on the lower boundary of the program. This hardware fence is set each time a program is dispatched; it prevents a a user program from writing into any memory loca tion below the fence.

In addition to the memory protect fence, RTE-III protects all pages of memory that a program does not use in the 32K address space described by the user map while the program is executing. This prevents a user program in one partition from destroying a pro gram in another partition.

Input/Output System

Before entry into any driver, RTE-III will deter mine which map, user or system, is necessary to pro cess the I/O. Then the system will load the proper

2 3

© Copr. 1949-1998 Hewlett-Packard Co.

map and enable it. If the device requires a DCPC chan nel, the system will load the proper DCPC map. Thus the standard I/O drivers are not required to do any mapping and therefore are compatible across the en tire RTE line of systems.

The fact that DCPC transfers occur under their own m a p e n h a n c e s m u l t i p r o g r a m m i n g t h r o u g h p u t .

While a program in one partition is I/O suspended during a DCPC transfer, the user map can be set up to describe another program executing in another parti tion. If the DCPC transfer had to take place under the user map, no other program could execute during the transfer. Thus having a map for each DCPC channel in addition to a map for the user program and one for the system increases the efficiency of computer use.

Acknowledgments

RTE-III is a product of the combined efforts of many people. Special thanks go to Ray Brubaker and Eu gene Wong, development engineers, who contributed greatly to the design and development of the product.

Also, Jim Bridges, production engineer, Van Diehl, product manager, Carl Davidson, quality assurance,

Joe Bailey, systems engineer, Joan Martin, technical writer, and Jim Bechtold, technical writer, contribu ted much time and good work toward making RTE-III a reality.

Much appreciation goes to Jack Elward, designer of the dynamic mapping system, and to Cle Riggins,

21MX project manager, for their technical assistance.

Also, Carl Ubis put in a lot of hard work maintain

ing the equipment and setting it up. S

Reference

1. J.S. Elward, ''The Million-Word Minicomputer Main

Memory," Hewlett-Packard Journal, October 1974.

Linda W. Averett

L i n d a A v e r e t t w a s p r o j e c t m a n ager for RTE-III. She came to H P in

1 974 with four years' experience in the design of real-time operating systems. A native of Knoxville,

T e n n e s s e e , s h e g r a d u a t e d f r o m the University of Tennessee in

1970 with a BS degree in engineer ing physics. She's married, lives in Sunnyvale, California, and

- e n j o y s t e n n i s , s w i m m i n g , a n d scuba diving.

H P 9 2 0 0 1 A R e a l - T i m e E x e c u t i v e S y s t e m I I ( R T E - I I )

FEATURES

Foreground and Background multi -use r swapping parli lion S

O p e r a t i o n i n a s l i t t i e a s 1 6 K o t C P U m e m o r y , o r u p t o 3 2 K t o r u s e r s r e a l - t i m e applications and RTE-II supported capabilities

S u p p o r t s c a r t r i d g e d i s c s u b s y s t e m s p r o v i d i n g 4 . 9 l o 1 1 8 M b y t e s o f o n - l i n e storage with optional file management to provide ample capacity (or programs and a fast-access data base

Concurrent processing and program development in FORTRAN II. IV: Conversa t i o n a l M u l t i - U s e r R e a l - T i m e B A S I C ( o p t i o n a l ) . A L G O L , a n d H P A s s e m b l y language.

MuflÃ-- users I access to all system resources, serving multiple users concurrently.

Optional input output spooling to ase lo speed throughput without excessive use of CPU memory for buffering

Powerful interactive editor to aid program development.

Supports coordination of distributed multiprocessor communicalion networks.

S u p p o r t s d a l a c o m m u n i c a t i o n w i t h I B M 3 6 0 . 3 7 0 o r H P 3 0 0 0 .

O R D E R I N G I N F O R M A T I O N

RTE-II 9600 ottered as a choice of A-series operating system options for 9600 systems. RTE-II is also available as follows

9 2 0 0 1 R T E - I I S o f t w a r e P a c k a g e

9 2 0 0 1 - Y 1 3 B a t c h - S p o o l M o n i t o r

9 2 0 0 1 - Y 1 5 M u l t i - U s e r R e a l - T i m e B A S I C

PRICE I U.S.A.:

9 2 0 0 1 R T E - I I . $ 4 0 0 0

9 2 0 0 1 - Y 1 3 B a t c h S p o o l M o n i t o r , S 1 0 0 0

9 2 0 0 1 - Y 1 5 M u l t i - U s e r R e a l - T i m e B A S I C , $ 1 0 0 0 .

H P 9 2 0 6 0 A R e a l - T i m e E x e c u t i v e S y s t e m I I I ( R T E - I I I )

FEATURES

Up to per separate multi-user swapping partitions, up to 19K words per partition for fast response to needs of many multiple users

M a n a g e s 3 2 t o 2 5 6 K o f C P U m e m o r y f o r u s e r ' s r e a l - t i m e a p p l i c a t i o n s a n d

RTE-III supported capabilities

S u p p o r t s c a r t r i d g e d i s c s u b s y s t e m s p r o v i d i n g 4 . 9 t o 1 1 8 M b y t e s o f o n - l i n e storage, with tile management lo provide ample capacity for programs and a fast-access data base.

Concurrent processing and program development in FORTRAN II/IV, Conversa t i o n a l M u l t i - U s e r R e a l - T i m e B A S I C ( o p i i o n a l ) , A L G O L , a n d H P A s s e m b l y language.

Multi-lerrmnai access to all system resources, serving multiple users concurrently.

Input/output spooling lo disc to speed throughput without excessive use of CPU memory for buffering.

Powerful interactive editor to aid program development.

Supports data communication with IBM 360/370 or HP 3000.

ORDERING INFORMATION

R T E - I I I i s o f f e r e d a s a c h o i c e o f A - s e n e s o p e r a t i n g s y s t e m o p t i o n s f o r 9 6 0 0 systems. RTE-III is also available as follows

92060A RTE-III Software Package

92060A-Y15 Multi-User Real-Time BASIC

PRICE IN U.S.A.:

92060A RTE-III. $6000. Includes Batch Spool Monitor

92060A-Y15 Multi-User Real-Time BASIC, $1000.

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