OZ

SERVIOEMANUAL

AND t80Z

SERVICE IlANUAL

PH 13821

Copyright e

1984 by Research Machines Limited

All rights reserved.

Copies of this publication aay be

IUde by customers exclusively for their OWDuse, but otherwise no part of it lUy reproduced, transmittea, t:.ranscribed, stored in a retrieval language or t:.ranslated into any language or computer the prior written permission of Research

Machines Limited, Mill St.

OXford, Bngland. OX2

OBW.

Tel Oxford (0865) 249866.

Research Machines has a policy of cont.inuous development and improvement of it.s products and services, and the right. is reserved to revise t.his manual or to make changes in the computer software describes without not.ice.

Research Machines endeavour t.o ensure the accuracy of this manual and t.hat. t.he

products described perform correctly according to their descriptions.

However Research Machines Limited do not. accept liability for consequences of any error or OIIission.

Additional copies of this publicat.ion may be ordered from

Research Machines Limited at the address above.

Please ask for t.he title as given above.

SBCTION 1

SBCTION2

3

MAIN

8U-CJ!1a1rat~t:..!r

.ft

Ii' ._",,- -,

_,WII

Mode

Mode

SVII~8~.

Read Ports

Write Ports

PCB

SECTION 4

POWER

SUPPLY

Mains Pilter and

.~'V~

••

~~~VA

Converter

3.1

3.2

3.3

3.4

3.5

3.6

4.1

2.1

2.2

2.3

2.4

2.5

2.

Power and Clocks

(

Manual

3.1

3.1

4.

4.1

4.1

4 1

4.2

4.2

4.4

21

2.8

2.13

2 14

2.14

1.

2.

3.

ref

10)

•

flows

TR5 and any base.

• 1

to as from

and

480Z

Once a

• Selected

There from which current the resonant to oscillate.

oscillates appears at the collector.

and an

C1 the base of TR2.

the emitter of TR3 then starts to conduct, the on

C3 flows to C4 and

Thus TRS collector from

, C3

C4 halfturned off) a

1 ) of this sent to the

, the Q no residual

As the must some sort memory is the start of each address

IC

3a} is clocked into

IC scanned.

As 4 is state the end the receives a data.

as are strobe oscillator) and returned to normal when the CPU to all

1.2

r a

JI'

•

I

480Z

'---,-_

...

....

....

•

•

I

U

...

10

CJ

(I

..

3

.

"

•

18

o

...

G

tI

•

II') u

..

o

...

u

I

I-

••

..

1.

1 ref.

D1

MAIN

1 to

1.

2.1

and

80

DR

480Z Main PCB refresh the whole of memory.

2 2

IG

..

N

.....

.

480Z

Main

PCB

480Z Main PCB

SHEET

2 memory map PROM that decodes

It lines to enable RAM as the

PAGE

1 and

ZRD

a

reset

0000 for its initialization, PAGE so that in normal isa 4 x

4-bit that it can be altered under software

1, to

2.3 shows the upon which and MA 7 define the the on the main board

I

MA15 are used when 4164 (

16K block within

16 address lines) and so is the the contents ofER to make

MR, KR, and are used

RAM ICs ( lines of

41 or 4 are decoded will

Lines

JT to and go to RAM

PCB.

Lines MA14 and and select the address of the

256K memory if

14 address lines

8+ for 4164's), and HT

2.4 shows an valid RAM address

Address lines to RAM decodes the bank.

At the two start of to connect A7 connected to to A13 address lines identical and connec~ea started when theZ80

JV to

1:.nr

1 ouan the is disabled disabled the allow 4164 ICs which to

8RFSHB which is allows each half of the 4164's within the 2ms limit to inhibits banks of RAM refresh, derived every 1.5 ma.

RT be refreshed

The latches GT and GV are included to overcome a known as between where of this is the minimum time that RAS must is at its limit between M1 and after the of

5

480Z

RAS

80

MaINR to

480Z

Main

PCB

~

•

• to

-'

.., f t

0

1

1

t

• • G 0

5

•

I \

I

I

\ ......--......

I ,

,

~

it

•

0

....

0

0 0

0 o

-

o o

.ft

GO

N f¥"t

.

.6

Main

PCB

..

•

-

-.

<

III

•

•

,

.7

N

•

..

Main PCB

SHEET 3 describes the onboard from are two banks

Each bank can are may consist up to suit the different

Pour

RC:>M sockets are

PROM, and the link associated

A similar video

4 for the differ·ent

4 of 4 1 or 1 bank

Different firmware and _..,...........,...

and

A 64K be available to enabled

ROM or EPROM can be in ROM is available as

PROM.

accommodated character the ·character available to the

4 video

It first

Mode divided clock.

EOC of to

I

takes 64ns i.e

one number out the line waveform lines of PROM,

CO the PROM receives even addresses 0 to 126.

a area both sides of the screen clocks the row counter

These are fed to the character character us) for use clocks

HR,

R3 is the reset a convenient waveform

( sheet ) to 31 of

IC addesses as line

.e.

counts 0 to

.8

2

480Z

Main

PCB

x

20.48ms

4BOZ Main PCB

• o

I

!

4(

I

t

~

"

z.

)-

-

K

.",

....

-

"

..

-

~

Z

....

•

~

Q

·r

j

:§

"

" ,

~

\.

-

•

III z

-'

...

....

..

Q

·r

!

u...

J,

"

2 0 an

•

N

•

480Z

I

~

• 1 o o o o

•

•

Ie

Ie o

\D

•

N

I

"

U

10

U

480Z Main PCB

.a

...5

~:

2. 2

.,

I

C'J

Main PCB

CPU

can read the contents of

1nll't.]r:UC:t..J..

0I1~S

•

in.t.ruction

line.

An

and additional wait.

t.

a

address

an

.1:1~ll9 e<sge of 4MIIz

"sheet the n11llber charact.er

(

RAM

in a

si~lar

way

1M

the counter JPis t.he

widt.h

t.s

to in the

e

screen

lliiott ....... lliiott".......

ry now neces.ary, is inhibit.ed

eet. are mixed at

2. 3

480Z Main PCB

SHEET

Read

Read

I

1, and are thus time

• onto the bus

3 a data into the latch and data strobes from the bit program read 1.

KBDSTB1

KBDREADY goes to the CTC (sheet 6)

The monitor program reads service routine and stores it in a use the user

•

Write

•

and 5 have latched

Write are cleared must not be

CTC has been set up, and so initialization firmware.

Another is that PAGE

0 and PAGE 1 are 'low' to its instruction from ROMO at address

-sheet 1).

initialization this is so

RAM the monitor to be goes to two fonts.

Write connected to the

ANALOGOUT.

The S102

(read and write • is addressed at the bottom of memory.

NM1EN is for programs and enables

( selects the screen format sheet 4 to select one of is a

DAC the of which can be

(sheet 6) and is available interface is software controlled

2

CR monos tables

2 14

41:SUZ Ma1.n

and JT2 which

• value

of

resistance).

Both

read

SHEET 6

The 810

This or as a

Ch1

Ch2 functions

Is used

to

various use used either

•

time between three network to

to

a sheet

2. 5

ref.

D10830, Sheets

OPTION to

The two banks

can

be linked to to 256K.

1

2

Resolution

480Z PCB

In modes mixed the between colour

3.1

in

480Z PCB medium resolution, levels).

colours can on the

RGB

SHEET

2

BY buffers the data bus to the

I I I data bus when active) • The direction of data is controlled also enabled at the

BY until the HRG

•

CT is time and decodes the lower two address lines to strobe

-

RD3 WRO -

4MHZafter

WRO WR.3

and data stable in go' to be used as strobes.

address out via

FW and GR

X via a enable the writes, is memory

• bus.

The this the main

64 to 79 format· used video on columns column

LCLCK and is

_ _

FU

In medium are paqe

1.

In fiiiiJ'iiiO . . 'iiiO ......... ) chain.

HRG 2 is usedfo·r

and HIRES

set thelllOde

PCB and o o

3.

480Z PCB

..

..

x

-et

~

~

-'

..

Q

:;

~

b

E

N

I

....

I

~

.

Ii t")

•

..

3

--

----

PCB field

100 t.o

103 are enabled t.o

LAO t.o

LA3.

If

LKWR is act.ivat.ed at this t.ime, dat.a lat.ched in WRO can be written to the table.

The CPU memory is or screen is three conditions.

3

In extra dat.a is

'text.' and white on

............................ 010:3 . . . .

) read fromHRG memory must be divided

500ns

PCB.

the shift is enabled and clocked out at 16MHz to action, shown in

3.4, is

BY and

DV are used to resolution for of the clock

4MHZ for value is t.o the value

(0 to 15) may

)

.

per to

The

WRO the time used as a state while

The used to memory.

to ae]rlel~a't.e

address to be this address is data bits in in and OV are disabled be activated to load the the

FBLANK

Note that write lines, and must return to and data lines are still valid.

the main

PCB is

VMEME the aO-character mode, data is used to of data into the shift is taken from the main PCB and enables the

CPU access two extra clock

FBLNK from the main

PCB is

3 6

480Z PCB

M-,

7

--IJII

I

I

I t

I

......-"2"....

("MHZ)

Higt

Ra.

Pixels

--..a

I

I

I

I

I

·:---,2S,..

('MHZ.)

--..

I

I

I

I

I

!--

2S0ns

("-'MlHZ)

3.3

HRG

Modes

3.8

480Z

--

..-

--

--

,....-.

~

---

--

-

--

-

--

--

~

-

-

~

•

I

1

....

•

o

ea

~

..

'"

•

1tI)..

...

480Z

PCB

,...

•

~.

~

0

('III

Ii

~

1

}

-J

'"

+

'0

3.10

480Z

3.

]

4BOZ

5

This sheet shows two dedicated ICs and a CTC:

•

• BS is an for

IEEE interface cont.roller, and from t.he main all the control functions necessary for the int.erface.

Processor the CTC channel O.

The IEEE address can o ).

and

BT are int.erface buffers.

are via as a status in HRG maths funct.ions with a minimum of are CTC channel 1.

group of select is

•

CTC channels 2 and

3 every Bms can used as a real-time clock:

Ch.3

counts the

Ch.2

of Ch. 2

1 second intervals so that the processor counter' in main memory.

3.12

FILTER AND

FLYBACK CONVERTER

4

480Z Power to 05 cathode C65 to • which is used to turn off

TR3 and bias

TR2 base.

As to after rises until it is the off, TR2 turns off due

TR1 then turns off as next. t.urn-off

, until all the energy int.o the circuits of TR2 starts to fall at a and the inductance, is

If there is no off occurs is which circuit drive from T2.

reliable t.he

is the via current at which turn rail, to the breakdown

When t.urned on or off and under on C6 is reduced due to decreased collector current is under all conditions.

to ensure

SNUBBERS transistor current value current which diode

0131 allows

At value due and

C11.

at the of T2 but is on

C1' is maximum TR3 exceeds this value,

022 conducts and is fed back to the and

The

5-volt rail reference of

01

this If the low low and the current in

OC1 will be low..

This power and

C101 are tends to of be to anincrease the initial error condition.

which stabilise

R1

Loads an effective risk rail are a.re

current drawn.

+SV

TYPICAL LOAD

2.5A

.2SA

.OSA

MAX and and maximum of each

4.3

480Z

Power --__

' , r - ' -...

z i:

I

..,

II

~

..

3

•

~

+

<

o~

~-

.,

....

.

4.4

480Z

SBCTION

SBCTION 2

Reset

Interface

SBCTION 3

SBCTION 4

3

U .1.41:1

QJ~IU.I..LIJI

Q a

Pault

480Z Pault

U14.~~OEI1S

Guide

2 •

• 1

2.1

2 1

2.1

2.2

.3

2.3

2.3

2.3

2.4

3.1

4.1

(1)

480ZFault

Guide

1

At and an internal one

An for use as a network station are also

This

LINK 480Z is intended to the RML course for a basic

It serves to:

• introduce the 480Z with a brief block of circuit

•

one of is unable to software via PROMs with a

Q1agn0

1 se) and methods of

• correIators

• conclude with routes flow on fault.

and unit, ( i.e.

• 1

4MHz

One 'wa.it·

•

STEP

Fault

2

SHTS 1..6

the· 380Z

VDUaccess

2.1

• RAM is controlled two bits the four address bits select which of the four banks within a two bits of used to

RAM is to sixteen 16K pages to be processor address space.

to 0 (see later •

• vou table.

This takes addres

8 bus 5 and

A

14) and

- MA17).

Of these, MA16 and MA17

RAM is to be while the of 16K pages any of the any of the four 64K pages of is controlled

The

VOU for both and one 'wait' state is added to all accesses).

The that

VOU is switchable software control between and 80 characters.

However the screen contents will should be on be cleared first.

The

VOU is as and so the screen and should accessed

IN r C

OUT (C),r

OTI OTIR, INI, INIR of cases the character on the screen range

X coordinate ( 0 to to

C will be the

Y coordinate of the and the value in

B be

Character 0,0 is at the left.

The value in r be the character the screen.

Characters

128 to

91 are dim.

from back

KEYBOARD is of or released-the will return an 8-bit number is available for future travel.

etc

( number has treated as the REPEAT

A means that when a a character.

The the seventh bit bit identifies the direction of with ASCII SHIFT, CTRL REPEAT, of function software control.

strobe one of

Characters are and active.

up and i t is and

2.2

480Z

SYSTEM section is one connected to filtered cassette the readable in

18 identical bit for data

80 that it the 380Z

The data an is bit consists monostables can centre read read

SERIAL software and

There is also a 8104 RS232

PORT Port the SIO B.

in latched

380Z if the and

In addition bits, is

Fault Guide

CONTROL PORTS

•

map o

188

198 lAH

•

CTC 20 to

24 to

Port 0

Read

Write

DIL switches

=

RAM ................

10-"' ..........,....

Read Bit

OIL

OIL

DIL table

Write

7

]

6

5

4

2

1 o x x x x

MA16

MAl

MA14 o least two the address within

• Port

Read

Network

Network

Network

Hard USERIO

Soft UHAND

Frame Blank

Blank

Bit

7

4

]

2

1 o

Write

Network

Reset

Soft URAND]

Soft UHAND2

Soft URAND

NMIEN

1 bits in the B table to which the

480Z Pault

•

•

Port

Read

JB2

JB1

JT1

JT2

8102'

8102'

HAND

CAS VOL

CASS IN

Port 3

Read

Write eTC USAGE o

Bit

6

5

4

2

1 o

'8104

Write

Select

ALTCHAR SET

JTRIG

'8102' TXD

CA8MI

CA8WREN

Provides and can

2

Generates

4

SIO USAGE:

,-n~!'I,n~II:I"" A

B

Generates

Network for

8104' RS232 Port baud rates

2MHz timer mode.

125KHz strobe o a

Guide

5

3

Faults in

Those access faults

480Z can be which allow

Front

SIO

2.

cassette.

follows

A flow fault

480Z Fault

Guide

··11...:.

" on Screen

Insert RAM test PROM data address, buses processor, etc.

N

.....

-------~ y

Insert RAM

PROM.

Use scope to observe test.

and

RAM

N y

3.1

3.

a

Fault.

4

Use for

No

2. No Cassette

RAM

No Front

CP,

RAM,

4.

on

ROM

ABUS,

• No

• Locks up

CONCLUSION be

Procedure areas

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