Intel 82540EP Data Sheet
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82540EP Gigabit Ethernet Controller
Networking Silicon
Datasheet
Revision 1.2
April 2003
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Copyright © Intel Corporation, 2002-2003 ii Datasheet
Networking Silicon — 82540EP
Revision History
Date
Apr 2002
Nov 2002
Jan 2003
Apr 2003
Revision
0.25
1.0
1.1
1.2
Notes
Initial Release
Changed document status to Intel Confidential.
Section 1.0. Replaced Block Diagram
Section 2.6. Added Table footnote
Section 4.1, 4.2, 4.3. Replaced tables
Section 5.1. Added Visual Pin Reference
Section 4.4 Removed Power Supply Characteristics; added note to I/O Characteristics
Section 5.0 Replaced Pinout Diagram
Removed confidential status.
Section 1.0. Added product ordering code.
Datasheet iii
82540EP — Networking Silicon
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iv Datasheet
Networking Silicon — 82540EP
Contents
1.0
2.0
3.0
4.0
Introduction......................................................................................................................... 1
1.1
1.2
1.3
Document Scope ...................................................................................................3
Reference Documents........................................................................................... 3
Product Code ........................................................................................................ 3
Features of the 82540EP Gigabit Ethernet Controller........................................................ 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
PCI Features ......................................................................................................... 5
MAC Specific Features.......................................................................................... 5
PHY Specific Features .......................................................................................... 6
Host Offloading Features ...................................................................................... 6
Manageability Features ......................................................................................... 7
Additional Device Features ................................................................................... 8
Technology Features............................................................................................. 8
Signal Descriptions............................................................................................................. 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Signal Type Definitions.......................................................................................... 9
PCI Bus Interface .................................................................................................. 9
3.2.1
PCI Address, Data and Control Signals ................................................... 9
3.2.2
Arbitration Signals .................................................................................. 11
3.2.3
Interrupt Signal ....................................................................................... 11
3.2.4
System Signals....................................................................................... 11
3.2.5
Error Reporting Signals .......................................................................... 11
3.2.6
Power Management Signals ..................................................................12
3.2.7
Impedance Compensation Signals......................................................... 12
3.2.8
SMB Signals........................................................................................... 12
EEPROM and Serial FLASH Interface Signals ................................................... 12
Miscellaneous Signals......................................................................................... 13
3.4.1
LED Signals............................................................................................13
3.4.2
Other Signals..........................................................................................13
PHY Signals ........................................................................................................14
3.5.1
Crystal Signals ....................................................................................... 14
3.5.2
Analog Signals ....................................................................................... 14
Test Interface Signals..........................................................................................15
Power Supply Connections ................................................................................. 15
3.7.1
Digital Supplies....................................................................................... 15
3.7.2
Analog Supplies .....................................................................................15
3.7.3
Ground and No Connects.......................................................................16
3.7.4
Control Signals ....................................................................................... 16
Voltage, Temperature, and Timing Specifications............................................................ 17
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings................................................................................. 17
Recommended Operating Conditions ................................................................. 17
DC Specifications ................................................................................................ 18
AC Characteristics............................................................................................... 21
Timing Specifications ..........................................................................................22
4.5.1
PCI Bus Interface ................................................................................... 22
4.5.2
Link Interface Timing ..............................................................................26
Datasheet v
82540EP — Networking Silicon
5.0
4.5.3
EEPROM Interface................................................................................. 26
Package and Pinout Information ...................................................................................... 27
5.1
5.2
5.3
5.4
5.5
Device Identification ........................................................................................... 27
Package Information ........................................................................................... 28
Thermal Specifications ........................................................................................ 29
Pinout Information ............................................................................................... 30
Visual Pin Reference........................................................................................... 39 vi Datasheet
1.0
Networking Silicon — 82540EP
Introduction
The Intel
®
82540EP Gigabit Ethernet Controller is a single, compact component with an integrated
Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel
®
82540EP allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs
The Intel
®
82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral
Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.
The 82540EP also incorporates the CLKRUN protocol and hardware supported downshift capability to two or three-pair 100 Mb/s operation. These features optimize mobile applications.
The Intel
®
82540EP’s on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management
Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces.
The 82540EP Gigabit Ethernet Controller architecture is designed to deliver high performance and
PCI bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82540EP controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient
PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation.
The 82540EP is packaged in a 15 mm
2
196-ball grid array and is pin compatible with both the
82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller and the 82540EM
Gigabit Ethernet Controller (which does not have added power saving features like CLKRUN).
Datasheet 1
82540EP — Networking Silicon
Data Alignment
Packet Buffer Interface
CSR Register
Access
TX Data
2
Figure 1. Gigabit Ethernet Controller Block Diagram
Datasheet
1.1
1.2
1.3
Networking Silicon — 82540EP
Document Scope
This document contains datasheet specifications for the 82540EP Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:
• 82544EI/82544GC Gigabit Ethernet Controller Software Developer's Manual, Revision 0.25,
Intel Corporation.
• PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group.
•
PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
• IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).
•
IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).
• IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
• 82559 Fast Ethernet Controllers Timing Device Selection Guide, AP-419, Intel Corporation.
• PCI Mobile Design Guide, Rev. 1.1, PCI Special Interest Group
Product Code
The product ordering code for the 82540EP is: RC82540EP.
Datasheet 3
82540EP — Networking Silicon
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4 Datasheet
2.0
2.1
2.2
Networking Silicon — 82540EP
Features of the 82540EP Gigabit Ethernet Controller
PCI Features
Algorithms that optimally use advanced PCI, MWI,
MRM, and MRL commands
CLKRUN# Signal
Features
PCI Revision 2.3 support for 32-bit wide interface at
33 MHz and 66 MHz
CardBus Information Services (CIS) Pointer
Benefits
• Application flexibility for LAN on Motherboard
(LOM) or embedded solutions
• 64-bit addressing for systems with more than 4
Gigabytes of physical memory
• Support for new PCI 2.3 interrupt status/control
• Efficient bus operations
• Enables CardBus operation (when used with external FLASH device and series termination on
PCI bus)
• PCI clock suspension for low power mobile design
MAC Specific Features
Features Benefits
Low-latency transmit and receive queues
IEEE 802.3x compliant flow control support with software controllable pause times and threshold values
• Network packets handled without waiting or buffer overflow.
• Control over the transmissions of pause frames through software or hardware triggering
• Frame loss reduced from receive overruns
Caches up to 64 packet descriptors in a single burst • Efficient use of PCI bandwidth
Programmable host memory receive buffers (256
Bytes to 16 KBytes) and cache line size (16 Bytes to
256 Bytes)
• Efficient use of PCI bandwidth
Wide, optimized internal data path architecture
64 KByte configurable Transmit and Receive FIFO buffers
• Low latency data handling
• Superior DMA transfer rate performance
• No external FIFO memory requirements
• FIFO size adjustable to application
Descriptor ring management hardware for transmit and receive
Optimized descriptor fetching and write-back mechanisms
Mechanism available for reducing interrupts generated by transmit and receive operations
Support for transmission and reception of packets up to 16 KBytes
•
•
•
• Simple software programming model
Efficient system memory and use of PCI bandwidth
Maximizes system performance and throughput
Enables jumbo frames
Datasheet 5
82540EP — Networking Silicon
2.3
2.4
PHY Specific Features
Features
Integrated PHY for 10/100/1000 Mbps full and half duplex operation
IEEE 802.3ab Auto-Negotiation support
IEEE 802.3ab PHY compliance and compatibility
State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and crosstalk cancellation
PHY ability to automatically detect polarity and cable lengths and MDI versus MDI-X cable at all speeds
Benefits
• Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions
• Automatic link configuration including speed, duplex, and flow control
• Robust operation over the installed base of
Category-5 (CAT-5) twisted pair cabling
• Robust performance in noisy environments
• Tolerance of common electrical signal impairments
• Easier network installation and maintenance
• End-to-end wiring tolerance
Host Offloading Features
Features Benefits
Transmit and receive IP, TCP and UDP checksum offloading capabilities
• Lower CPU utilization
Transmit TCP segmentation
Advanced packet filtering
Descriptor ring management hardware for transmit and receive
16 KByte jumbo frame support
Interrupt coalescing (multiple packets per interrupt)
• Increased throughput and lower CPU utilization
• Large send offload feature (in Microsoft*
Windows* XP) compatible
• 16 exact matched packets (unicast or multicast)
• 4096-bit hash filter for multicast frames
• Promiscuous (unicast and multicast) transfer mode support
• Optical filtering of invalid frames
IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags
• Ability to create multiple virtual LAN segments
• Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage
• High throughput for large data transfers on networks supporting jumbo frames
• Increased throughput by reducing interrupts generated by transmit and receive operations
6 Datasheet
2.5
Networking Silicon — 82540EP
Manageability Features
Features
Manageability features: SMB port, ASF 1.0, ACPI,
Wake on LAN, and PXE
On-board SMB port
Compliance with PCI Power Management 1.1 and
ACPI 2.0 register set compliant including:
• D0 and D3 power states
• Network Device Class Power Management
Specification 1.1
• PCI Specification 2.2
SNMP and RMON statistic counters
SDG 3.0, WfM 2.0, and PC2001 compliance
Wake on LAN support
Two or three-pair cable downshift
Benefits
• Network management flexibility
• Enables IPMI and ASF implementations
• Allows packets routing to and from either LAN port and a server management processor
• PCI power management capability requirements for PC and embedded applications
• Easy system monitoring with industry standard consoles
• Remote network management capabilities through
DMI 2.0 and SNMP software
• Packet recognition and wake-up for NIC and LOM applications without software configuration
• Assures link under adverse cable configurations
Datasheet 7
82540EP — Networking Silicon
2.6
2.7
Additional Device Features
Features Benefits
Four activity and link indication outputs that directly drive LEDs
Programmable LED functionality
• Link and activity indications (10, 100, and 1000
Mbps) on each port
• Software definable function (speed, link, and activity) and blinking allowing flexible LED implementations
Internal PLL for clock generation can use a 25 MHz crystal
Four software definable pins
• Lower component count and system cost
JTAG (IEEE 1149.1) Test Access Port built in silicon • Simplified testing using boundary scan
On-chip power control circuitry a
• Reduced number of on-board power supply regulators
• Simplified power supply design in less powercritical applications
• Additional flexibility for LEDs or other low speed
I/O devices
Supports little endian byte ordering for both 32 and 64 bit systems and big endian byte ordering for 64 bit systems
Two or three-pair cable downshift
Provides loopback capabilities
Minimal ballout change from the 82540EM
•
• Portable across application architectures
Supports modular hardware accessories
• Validates silicon integrity
• Pin Compatibility a. If applying the “low-power” EEPROM setting for the 82540EP chip, then only external voltage regulator circuits should be used instead of the on-chip power control circuitry
Technology Features
Features
196-pin Ball Grid Array (TFBGA) package
Pin compatible with 82551QM and 82540EM controllers
Implemented in 0.15u CMOS process
Operating temperature: 0 ° C to 70 ° C (maximum) operating temperature
Heat sink or forced airflow not required
65 ° C to 140 ° C storage temperature range
PCI Signaling: 3.3 V (5 V tolerant) PCI signaling
Typical targeted power dissipation:
• 1.38W @ D0 1000 Mb/s
• 386mW @ D3 100 Mb/s (wake-up enabled)
• <20mW @ D3 wake-up disabled
Benefits
• 15 mm
2
component making LOM designs easier
• Enables 10/100 Mbps Fast Ethernet or 1000 Mbps
Gigabit Ethernet implementations on the same board with only minor stuffing option changes
• Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards
• Simple thermal design
• Lower power requirements for mobile applications
8 Datasheet
Networking Silicon — 82540EP
3.0
Signal Descriptions
Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82540EP controller are electrically defined as follows:
A
P
I
O
TS
Name
STS
OD
Definition
Input. Standard input only digital signal.
Output. Standard output only digital signal.
Tri-state. Bi-directional three-state digital input/output signal.
Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.
An agent driving the STS pin low must actively drive it high for at least one clock before letting it float. The next agent of the signal cannot drive the pin earlier than one clock after it has been released by the previous agent.
Open Drain. Wired-OR with other agents.
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state.
Analog. PHY analog data signal.
Power. Power connection, voltage reference, or other reference connection.
3.2
3.2.1
PCI Bus Interface
When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bidirectional pins except the Power Management Event signal (PME#).
PCI Address, Data and Control Signals
Symbol Type Name and Function
AD[31:0]
TS
The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The
82540EP device uses little endian byte ordering.
During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24] contain the most significant byte (MSB).
Datasheet 9
82540EP — Networking Silicon
Symbol
CBE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL#
DEVSEL# STS
VIO
I
Type
TS
TS
STS
STS
STS
STS
P
Name and Function
Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction,
CBE[3:0]# define the bus command. In the data phase, CBE[3:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data.
CBE0# applies to byte 0 (LSB) and CBE3# applies to byte 3 (MSB).
Parity. The Parity signal is issued to implement even parity across AD[31:0] and
CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase.
When the 82540EP controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases.
Cycle Frame.
The Frame signal is driven by the
82540EP device to indicate the beginning and length of an access and indicate the beginning of a bus transaction.
While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phas
e.
Initiator Ready. Initiator Ready indicates the ability of the 82540EP controller (as bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted.
During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82540EP controller drives IRDY# when acting as a master and samples it when acting as a slave.
Target Ready. The Target Ready signal indicates the ability of the 82540EP controller
(as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted.
During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together. The 82540EP device drives TRDY# when acting as a slave and samples it when acting as a master.
Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82540EP controller drives STOP# to request the bus master to stop the transaction. As a master, the 82540EP controller receives
STOP# from the slave to stop the current transaction.
Initialization Device Select. The Initialization Device Select signal is used by the
82540EP as a chip select signal during configuration read and write transactions.
Device Select. When the Device Select signal is actively driven by the 82540EP, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage.
Note: An external resistor is required between the voltage reference and the VIO pin.
The target resistor value is 100 K
Ω
10 Datasheet
Networking Silicon — 82540EP
3.2.2
3.2.3
3.2.4
3.2.5
Datasheet
Arbitration Signals
Symbol
REQ#
GNT#
LOCK#
I
I
Type
TS
Name and Function
Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point.
Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been granted. This is a point-to-point signal.
Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a target memory device during two or more separate transfers. The 82540EP device does not implement bus locking.
Interrupt Signal
Symbol
INTA#
Type
TS
Name and Function
Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an active low, level-triggered interrupt signal.
System Signals
Symbol
CLK
M66EN
RST#
CLKRUN#
I
I
I
Type
I/O
OD
Name and Function
PCI Clock.
The PCI Clock signal provides timing for all transactions on the PCI bus and
82540EP
device. All other PCI signals, except the Interrupt A timing parameters are defined with respect to this edge.
66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz.
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the
Power Management Event signal (PME#), are floated and all input signals are ignored.
The PME# context is preserved, depending on power management settings.
Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of
RST#.
Clock Run. This signal is used by the system to pause the PCI clock signal. It is used by the 82540EP controller to request the PCI clock. When the CLKRUN# feature is disabled, leave this pin unconnected.
Error Reporting Signals
Symbol
SERR#
PERR#
Type
OD
STS
Name and Function
System Error. The System Error signal is used by the 82540EP controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error.
Parity Error. The Parity Error signal is used by the 82540EP controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82540EP controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.
11
82540EP — Networking Silicon
3.2.6
3.2.7
3.2.8
3.3
Power Management Signals
Symbol
LAN_
PWR_
GOOD
PME#
AUX_PWR I
I
Type
OD
Name and Function
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82540EP. When the signal is low, the 82540EP holds itself in reset state and floats all PCI signals.
Power Management Event. The 82540EP device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management
Control/Status Register or the Advanced Power Management Enable (APME) bit of the
Wake-up Control Register (WUC) is 1b.
Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82540EP device should support the D3cold power state.
Impedance Compensation Signals
Symbol
ZN_COMP
ZP_COMP
Type
I/O
I/O
Name and Function
N Device Impedance Compensation. This signal should be connected to an external precision resistor (to VDD) that is indicative of the PCI trace load. This cell is used to dynamically determine the drive strength required on the N-channel transistors in the
PCI I/O cells.
P Device Impedance Compensation. This signal should be connected to an external precision resistor (to VSS) that is indicative of the PCI trace load. This cell is used to dynamically determine the drive strength required on the P-channel transistors in the
PCI I/O cells.
SMB Signals
Symbol Type
SMBCLK I/O
SMBDATA I/O
SMBALRT# O
Name and Function
SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface.
SMB Data. The SMB Data signal is an open drain signal for serial SMB interface.
SMB Alert. The SMB Alert signal is open drain for serial SMB interface.
EEPROM and Serial FLASH Interface Signals
Symbol
EE_DI
EE_DO
EE_CS
EE_SK
I
Type
O
O
O
Name and Function
EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device.
EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EE_DO includes an internal pull-up resistor.
EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.
EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the
EEPROM interface, which is approximately 1 MHz.
12 Datasheet
Networking Silicon — 82540EP
3.4
3.4.1
Symbol
FL_CE#
FL_SCK
FL_SI
FL_SO I
Type
O
O
O
Name and Function
FLASH Chip Enable Output. Used to enable FLASH device.
FLASH Serial Clock Output .
The clock rate of the serial FLASH interface is approximately 1 MHz.
FLASH Serial Data Input. This pin is an output to the memory device.
FLASH Serial Data Output. This pin is an input from the FLASH memory. It has an internal pullup device.
Miscellaneous Signals
LED Signals
3.4.2
Symbol
LED0 / LINK#
LED1 / ACT#
LED2 / LINK100#
LED3 / LINK1000#
Type
O
O
O
O
Name and Function
LED0 / LINK Up. Programmable LED indication. Defaults to indicate link connectivity.
LED1 / Activity. Programmable LED indication. Defaults to flash to indicate transmit or receive activity.
LED2 / LINK 100. Programmable LED indication. Defaults to indicate link at
100 Mbps.
LED3 / LINK 1000. Programmable LED indication. Defaults to indicate link at
1000 Mbps.
Other Signals
Symbol
SDP[7:6]
SDP[1:0]
Type
TS
Name and Function
Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals.
Note: SDP5 is not included in the group of Software Defined Pins.
Datasheet 13
82540EP — Networking Silicon
3.5
3.5.1
3.5.2
PHY Signals
Crystal Signals
Symbol
XTAL1
XTAL2
I
Type
O
Name and Function
Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It can be connected to either an oscillator or crystal. If a crystal is used, Crystal Two (XTAL2) must also be connected.
Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation. If an external oscillator is used in the design, XTAL2 must be disconnected.
Analog Signals
Symbol
REF
MDI[0]+/-
MDI[1]+/-
MDI[2]+/-
MDI[3]+/-
Type
P
A
A
A
A
Name and Function
Reference. This Reference signal should be connected to VSS through an external
2.49 K
Ω
resistor.
Media Dependent Interface [0].
1000BASE-T : In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X configuration, MDI[0]+/- corresponds to BI_DB+/-.
100BASE-TX : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair.
10BASE-T : In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X configuration, MDI[0]+/- is used for the receive pair.
Media Dependent Interface [1].
1000BASE-T : In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X configuration, MDI[1]+/- corresponds to BI_DA+/-.
100BASE-TX : In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair.
10BASE-T : In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X configuration, MDI[1]+/- is used for the transit pair.
Media Dependent Interface [2].
1000BASE-T : In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X configuration, MDI[2]+/- corresponds to BI_DD+/-.
100BASE-TX : Unused.
10BASE-T : Unused.
Media Dependent Interface [3].
1000BASE-T : In MDI configuration, MDI[3]+/- corresponds to BI_DD+/-, and in MDI-X configuration, MDI[3]+/- corresponds to BI_DC+/-.
100BASE-TX : Unused.
10BASE-T : Unused.
14 Datasheet
3.6
3.7
3.7.1
3.7.2
Networking Silicon — 82540EP
Test Interface Signals
Symbol Type
JTAG_TCK I
JTAG_TDI I
JTAG_TDO O
JTAG_TMS I
JTAG_
TRST#
TEST
I
I
CLKVIEW O
Name and Function
JTAG Clock.
JTAG TDI.
JTAG TDO.
JTAG TMS.
JTAG Reset. This is an active low reset signal for JTAG. This signal should be terminated using a pull-down resistor to ground. It must not be left unconnected.
Factory Test Pin.
Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing.
The clock is selected by register programming.
Power Supply Connections
Digital Supplies
Symbol
VDDO
DVDD
Type
P
P
Name and Function
3.3 V I/O Power Supply.
1.5 V Digital Core Power Supply.
Analog Supplies
Symbol
AVDDH
AVDDL
Type
P
P
3.3 V Analog Power Supply.
2.5 V Analog Power Supply.
Name and Function
Datasheet 15
82540EP — Networking Silicon
3.7.3
3.7.4
Ground and No Connects
Symbol
GND
NC
Type
P
P
Name and Function
Ground.
No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins.
Control Signals
Symbol
CTRL_15
CTRL_25
Type
A
A
Name and Function
1.5V Control. LDO voltage regulator output to drive external pass transistor. If 1.5V is already present in the system, leave output unconnected. To achieve optimal D
3 consumption (<50 mw), leave the output unconnected and use a high-efficiency
power external switching regulator.
2.5V Control. LDO voltage regulator output to drive external pass transistor. If 2.5V is already present in the system, leave output unconnected. To achieve optimal D
3 consumption (<50 mw), leave the output unconnected and use a high-efficiency
power external switching regulator.
16 Datasheet
Networking Silicon — 82540EP
4.0
Voltage, Temperature, and Timing Specifications
Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
4.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
a
Symbol Parameter
DC supply voltage V
DD
V
IN
I
IN
Input voltage
DC input pin current
Min
-0.3
-1
-10
Max
7
V
DD
+ 0.3
10
Unit
V
V mA
T
STG
Storage temperature
-40 125
°
C a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations.
4.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
a
(Sheet 1 of 2)
Symbol Parameter Condition Min Typ
T
OP
Operating
Temperature
0
V
IO
V
DD
VIO Voltage
Range
Periphery
Voltage
Range
3.3V
±
10%
3
3 3.3
Max
70
5.25
3.6
Unit
°
C
V
V
Datasheet 17
82540EP — Networking Silicon
Table 2. Recommended Operating Conditions
a
(Sheet 2 of 2)
Symbol Parameter Condition Min Typ
V
AH
Analog High
VDD Range
3.3V
±
10% 3 3.3
Max
3.6
Unit
V
V
D
Core Digital
Voltage
Range
1.5V
±
5% 1.425
1.5
1.575
V
V
AL
Analog Low
VDD Range
2.5V
±
5% 2.375
2.5
2.625
V a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage.
4.3
DC Specifications
Table 3. DC Characteristics
Symbol
V
DD
(3.3)
V
DD
(2.5)
V
DD
(1.5)
Parameter
DC supply voltage on VDDO or
AVDDH
DC supply voltage on AVDDL
DC supply voltage on DVDD
Min
3.00
2.38
1.43
Typ
3.3
2.5
1.5
Max
3.60
2.62
1.57
Units
V
V
V
Table 4. Power Specifications - D0a
3.3V
2.5V
1.5V
Total
Device
Power unplugged/no link
Typ Icc
(mA)
Max Icc
(mA)
40
20
40
20
100 120
D0a
@10 Mbps
Typ Icc
(mA)
Max Icc
(mA)
55
30
65
35
95 100
@100Mbps
Typ Icc
(mA)
Max Icc
(mA)
65
55
80
60
115 125
@1000Mbps
Typ Icc
(mA)
Max Icc
(mA)
125
145
125
150
400 425
325 mW 400 mW 525 mW 1.38 W 1.5 W
18 Datasheet
Networking Silicon — 82540EP
Table 5. Power Specifications - D3cold
unplugged/no link
Typ Icc
(mA)
Max Icc
(mA)
D3cold - wake-up enabled
@10 Mbps
Typ Icc
(mA)
Max Icc
(mA)
@100Mbps
Typ Icc
(mA)
Max Icc
(mA)
D3cold - wake disabled - max power savings mode disabled
Typ Icc
(mA)
Max Icc
(mA)
D3cold - wake disabled - max power savings mode enabled a
Typ Icc
(mA)
Max Icc
(mA)
3.3V
2.5V
40
20
40
20
55
30
55
30
50
55
50
55
40
20
40
20
6
0.1
8
0.1
1.5V
Total
Device
Power
40
240 mW
40 30
300 mW
35 55
385 mW
60 10
195 mW
10 1
20 mW
1 a. Special Note: To obtain the benefit of max power savings mode, do not use the internal voltage regulator control circuit and external pass transistors. Use external switching regulators for highest efficiency.
Table 6. Power Specifications D(r) Uninitialized
D(r) Uninitialized
(LAN_PWR_GOOD=0)
3.3V
2.5V
1.5V
Total Device
Power
Typ Icc
(mA)
40
40
190
520 mW
Max Icc
(mA)
45
45
200
Table 7. Power Specifications - Complete Subsystem
Complete Subsystem (Reference Design)
Including Magnetics, LED, Regulator Circuits
3.3V
D3cold - wake disabled - max power savings mode disabled
40 40
D3cold wakeenabled @10Mbps
D3cold wakeenabled @100Mbps
Typ Icc
(mA)
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
60 60
D0 @1000Mbps active
D3cold - wake disabled - max power savings mode enabled
Typ Icc
(mA)
Max Icc
(mA)
Typ
Icc
(mA)
60 60 130
Max Icc
(mA)
Typ Icc
(mA)
Max Icc
(mA)
130 6 8
Datasheet 19
82540EP — Networking Silicon
Table 7. Power Specifications - Complete Subsystem
2.5V
1.5V
20
10
20
10
40
30
40
35
80
55
80
60
Subsystem
3.3V current
70 mA 135 mA 200 mA
240
400
245
425
800 mA
0.1
1
0.1
1
10 mA
Table 8. I/O Characteristics
Symbol
V
IL
V
IH
Parameter
Voltage input LOW
Voltage input HIGH
Condition Min
-0.5
2
Typ Max
0.8
V
DD
+0.3
0.4
Unit
V
V
I
V
V
V
OL
OH
SH
OL a
Voltage output LOW
Voltage output HIGH
Schmitt Trigger Hysterysis
Output current LOW
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
Output current HIGH
3mA drivers (TTL3)
6mA drivers (TTL6)
12mA drivers (TTL12)
V
V
V
OL
OL
OL
2.4
0.1
3
6
12
V
V
V mA mA mA
I
OH a
V
OH
V
OH
V
OH
-3
-6
-12 mA mA mA
I
IN
Input Current
TTL inputs
Inputs with pull-down resistors
TTL inputs with pull-up resistors
V
IN
= V
DD
or
V
V
IN
IN
V
SS
= V
= V
DD
SS
-10
150
-150
±
1
10
480
-480
µ
A
µ
A
µ
A
I
OZ
C
IN
3-state output leakage current
Input capacitance
V
OH
= V
DD
V
SS or
Any input and bi-directional buffer
-10
±
1
2.5
10
µ
A pF
C
OUT
Output capacitance
Any output buffer
2 pF
C
PUD
Pull-up/down Resistor value 7.5
20 k
Ω a. TTL3 signals include: EE_DI, EE_SK, EE_CS, and JTAG_TDO.
TTL6 signals include: CLKRUN#, FL_CE#, FL_SCK, FL_SI, and CLK_VIEW.
TTL12 signals include: LED0 / LINK #, LED1 / ACT #, LED2 / LINK100 #, LED3 / LINK1000 #, SDP0, SDP1, SDP6, and SDP7.
20 Datasheet
Networking Silicon — 82540EP
4.4
AC Characteristics
Table 9. AC Characteristics: 3.3 V Interfacing
Symbol
PCICLK
Parameter
Clock frequency in PCI mode
Min Typ Max
66
Value
10
16
18
20
Units pF pF pF pF
Unit
MHz
Table 10. 25 MHz Clock Input Requirements
Symbol Parameter a fi_TX_CLK TX_CLK_IN frequency
Min
25 - 50 ppm
Typ
25
Max
25 + 50 ppm
Unit
MHz a. This parameter applies to an oscillator connected to the Crystal One (XTAL1) input. Alternatively, a crystal may be connected to XTAL1 and XTAL2 as the frequency source for the internal oscillator.
Table 11. Link Interface Clock Requirements
Symbol fGTX a
Parameter
GTX_CLK frequency a. GTX_CLK is used externally for test purposes only.
Min Typ
125
Max Unit
MHz
Table 12. EEPROM Interface Clock Requirements
Symbol Parameter fSK
Min Typ Max
1
Unit
MHz
Table 13. AC Test Loads for General Output Pins
Symbol
CL
CL
CL
CL
Signal Name
TDO
PME#, SDP[7:0]
EE_DI, EE_SK
RX_ACTIVITY, TX_ACTIVITY, LINK_UP
Datasheet 21
82540EP — Networking Silicon
Figure 1. AC Test Loads for General Output Pins
CL
4.5
Timing Specifications
Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design.
4.5.1
4.5.1.1
PCI Bus Interface
PCI Bus Interface Clock
Table 14. PCI Bus Interface Clock Parameters
PCI 66 MHz PCI 33 MHz
Symbol Parameter a
Units
TCYC
TH
TL
CLK cycle time
CLK high time
CLK low time
CLK slew rate
RST# slew rate b
Min
15
6
6
1.5
50
Max
30
4
Min
30
11
11
1
50
Max
4 ns ns ns
V/ns mV/ns a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range.
Figure 2. PCI Clock Timing
Th
0.6 Vcc
Tcyc
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc p-to-p
(minimum)
0.2 Vcc
Tl
22 Datasheet
Networking Silicon — 82540EP
4.5.1.2
PCI Bus Interface Timing
Table 15. PCI Bus Interface Timing Parameters
Symbol
TVAL
TVAL(ptp)
TON
TOFF
TSU
TSU(ptp)
TH
TRRSU
TRRH
PCI 66MHz
Parameter
Min
CLK to signal valid delay: bussed signals
CLK to signal valid delay: pointto-point signals
Float to active delay
Active to float delay
Input setup time to CLK: bussed signals
Input setup time to CLK: point-topoint signals
Input hold time from CLK
REQ64# to RST# setup time
RST# to REQ64# hold time
2
2
2
3
5
0
10* TCYC
0
Max
6
6
14
PCI 33 MHz
Min Max
2
2
2
7
10, 12
0
10* TCYC
0
11
12
28
Units ns ns ns ns ns ns ns ns ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
Figure 3. PCI Bus Interface Output Timing Measurement
V
TH
PCI_CLK
V
TEST
V
TL
Output
Delay
V
TEST
V
STEP
(3.3V Signalling) output current
≤
leakage current
Tri-State
Output
T
ON
T
OFF
Datasheet 23
82540EP — Networking Silicon
Figure 4. PCI Bus Interface Input Timing Measurement Conditions
PCI_CLK
Input
V
TH
V
TEST
T SU
Input
Valid
V
TEST
T
H
V
TEST
V
TL
V
MAX
V
TH
V
TL
Table 16. PCI Bus Interface Timing Measurement Conditions
Symbol
VTH
VTL
VTEST
Parameter
Input measurement test voltage (high)
Input measurement test voltage (low)
Output measurement test voltage
Input signal slew rate
PCI 66 MHz
3.3 v
0.6*VCC
0.2*VCC
0.4*VCC
1.5
Figure 5. TVAL (max) Rising Edge Test Load
Pin
1/2 inch max.
Test
Point
Unit
V
V
V
V/ns
25
Ω
10 pF
24 Datasheet
Networking Silicon — 82540EP
Figure 6. TVAL (max) Falling Edge Test Load
Pin
1/2 inch max.
Test
Point
10 pF
25
Ω
V
CC
Figure 7. TVAL (min) Test Load
Pin
Test
Point
1/2 inch max.
1k
Ω 10 pF
1k
Ω
V
CC
Figure 8. TVAL Test Load (PCI 5 V Signaling Environment)
Pin
1/2 inch max.
Test
Point
50 pF
NOTE:
Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.
Datasheet 25
82540EP — Networking Silicon
4.5.2
Link Interface Timing
Table 17. Rise and Fall Times
Symbol
TR
TF
TR
TF
Parameter
Clock rise time
Clock fall time
Data rise time
Data fall time
Figure 9. Link Interface Rise/Fall Timing
2.0 V
Condition
0.8 V to 2.0 V
2.0 V to 0.8 V
0.8 to 2.0 V
2.0 V to 0.8 V
0.8 V
Min
0.7
0.7
0.7
0.7
Max Unit ns ns ns ns
T
R
T
F
4.5.3
EEPROM Interface
Table 18. Link Interface Clock Requirements
Symbol
TPW
Parameter
EE_SK pulse width
Min Typ
TPERIOD *128
Max Unit ns a. The EEPROM clock is derived from a 125 MHz internal clock.
Table 19. Link Interface Clock Requirements
Symbol Parameter a
Min Typ Max Unit
TDOS EE_DO setup time TCYC*2 ns a.
TDOH EE_DO hold time 0 ns
The EE_DO setup and hold time is a function of the PCI bus CLK cycle time but is referenced to O_EE_SK.
26 Datasheet
Networking Silicon — 82540EP
5.0
Package and Pinout Information
This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring
15mm X 15mm. External product identification is shown in Figure 10 . The nominal ball pitch is
1mm. The pin number-to-signal mapping is indicated beginning with Table 19 .
5.1
Device Identification
Figure 10. 82540EP Device Identification Markings
RC82540EP
YYWW © 'ZZ
Tnnnnnnnn
Country
82540EP
YYWW
Tnnnnnnnn
Product Name
Date Code
Lot Trace Code
(c)’ZZ
Country
Copyright Information
Country of Origin Assembly
NOTE: “
•
“indicates the location of pin 1. It is not an actual mark on the device
Datasheet 27
82540EP — Networking Silicon
5.2
Package Information
The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm
2
. The package dimensions are detailed in Figure 11 . The nominal ball pitch is 1 mm.
Figure 11. 82540EP Mechanical Specifications
28 Datasheet
Networking Silicon — 82540EP
5.3
Thermal Specifications
The 82540EP device is specified for operation when the ambient temperature (TA) is within the range of 0 ° C to 70 ° C.
TC (case temperature) is calculated using the equation:
TC = TA + P (
θ
JA - q JC)
TJ (junction temperature) is calculated using the equation:
TJ = TA + P
θ
JA
P (power consumption) is calculated by using the typical ICC, as indicated in Table 4 of Section 4.0
, and nominal VCC. The thermal resistances are shown in Table 18 .
Table 18. Thermal Characteristics
Symbol Parameter
0
Value at specified airflow (m/s)
1 2 3
Units
θ
JA
θ
JC
Thermal resistance, junction-to-ambient
Thermal resistance, junction-to-case
28.1
6.1
25.0
6.1
23.7
6.1
22.8
6.1
°C/
Watt
°C/
Watt
Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82540EP device is operating under recommended conditions.
Datasheet 29
82540EP — Networking Silicon
5.4
Pinout Information
Table 19. PCI Address, Data, and Control Signals
Signal
PCI_AD[0]
PCI_AD[1]
PCI_AD[2]
PCI_AD[3]
PCI_AD[4]
PCI_AD[5]
PCI_AD[6]
PCI_AD[7]
PCI_AD[8]
PCI_AD[9]
PCI_AD[10]
PCI_AD[11]
PCI_AD[12]
PCI_AD[13]
PCI_AD[14]
PCI_AD[15]
Pin
M2
M3
L1
L2
P3
N3
N2
M1
N5
M5
P4
N4
N7
M7
P6
P5
Signal
PCI_AD[16]
PCI_AD[17]
PCI_AD[18]
PCI_AD[19]
PCI_AD[20]
PCI_AD[21]
PCI_AD[22]
PCI_AD[23]
PCI_AD[24]
PCI_AD[25]
PCI_AD[26]
PCI_AD[27]
PCI_AD[28]
PCI_AD[29]
PCI_AD[30]
PCI_AD[31]
Table 20. PCI Arbitration Signals
REQ#
GNT#
Signal Pin
C3
J3
Table 21. Interrupt Signals
INTA#
Signal Pin
H2
Table 22. System Signals
Signal
CLK
Pin
G1
Signal
M66EN
Table 23. Error Reporting Signals
Signal
SERR#
Pin
A2
Signal
PERR#
Pin
C6
C7
A8
B8
B4
A5
B5
B6
D3
C1
B1
B2
K1
E3
D1
D2
Signal
CBE0#
CBE1#
CBE2#
CBE3#
PAR
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
VIO
IDSEL
Pin
C2 RST#
Signal
Pin
J2
30
Pin
J1
F2
F1
G3
M4
L3
F3
C4
H1
H3
G2
A4
Pin
B9
Datasheet
Networking Silicon — 82540EP
Table 24. Power Management Signals
Pin Signal
LAN_PWR_
GOOD
PME#
A9
A6
Signal
AUX_PWR
CLKRUN#
Table 25. Impedance Compensation Signals
Signal
ZN_COMP
Pin
H4
Signal
ZP_COMP
Pin
J12
C8
Pin
G4
Table 26. SMB Signals
Signal
SMBCLK
Table 28. LED Signals
Signal
LED0 / LINK#
LED1 / ACT#
Pin
A10
Signal
SMBDATA
Pin
C9
Signal
SMBALRT#
Table 27. EEPROM and Serial FLASH Interface Signals
Signal
EE_SK
EE_DO
EE_CS
Pin
M10
N10
P7
Signal
EE_DI
FL_CE#
FL_SI
Pin
P10
M9
M11
Signal
FL_SCK
FLSO
Pin
A12
C11
Signal
LED2 / LINK100#
LED3 / LINK1000#
Pin
B11
B12
Table 29. Other Signals
SDP0
SDP1
Signal Pin
N14
P13
SDP6
SDP7
Signal Pin
N13
M12
Signal
CTRL_15
CTRL_25
Table 30. IEEE Test Signals
Signal
CLK_VIEW
Pin
M8
Pin
B10
Pin
P11
B13
Pin
N9
P9
Datasheet 31
82540EP — Networking Silicon
Table 31. PHY Signals
XTAL1
XTAL2
REF
MDI0-
Signal Pin
K14
J14
B14
C14
Signal
MDI0+
MDI1-
MDI1+
MDI2-
Table 32. Test Interface Signals
Signal
JTAG_TCK
JTAG_TDI
Pin
L14
M13
Signal
JTAG_TDO
JTAG_TMS
Pin
C13
E14
E13
F14
Signal
MDI2+
MDI3-
MDI3+
Pin
M14
L12
Signal
JTAG_RST#
TEST
Pin
F13
H14
H13
Pin
L13
A13
Table 33. Digital Power Signals
Signal
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
H7
H8
H11
J5
J6
J7
E11
E12
G5
G6
G13
H5
H6
Pin
Table 34. Analog Power Signals
Signal
AVDDL (2.5 V)
AVDDL (2.5 V)
Pin
D9
D11
Signal
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
Signal
AVDDL (2.5 V)
K8
K9
K10
K11
L4
L5
J8
J9
J10
J11
K5
K6
K7
Pin Signal
DVDD (1.5V)
DVDD (1.5V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
VDDO (3.3V)
Pin
G12
Signal
AVDDL (2.5 V)
K4
K13
N6
N8
P2
P12
L9
L10
A3
A7
A11
E1
K3
Pin
Pin
L8
32 Datasheet
Networking Silicon — 82540EP
Table 35. Grounds and No Connect Signals
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E4
E5
E6
D7
D8
D13
E2
B3
B7
C10
C12
D4
D5
D6
Pin Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F7
F8
F9
F10
F11
G7
G8
E7
E8
E9
E10
F4
F5
F6
Pin Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K12
L6
L11
M6
N1
N12
P8
G9
G10
G11
G14
H9
H10
K2
Pin
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Signal
H12
J4
J13
L7
N11
P1
P14
A1
A14
C5
D10
D12
D14
F12
Pin
Table 36. Signal Names in Pin Order (Sheet 1 of 6)
Signal Name
NC
SERR#
VDDO (3.3V)
IDSEL
PCI_AD[25]
PME#
VDDO (3.3V)
PCI_AD[30]
LAN_PWR_GOOD
SMBCLK
VDDO (3.3V)
LED0 / LINK#
TEST
NC
PCI_AD[22]
PCI_AD[23]
GND
PCI_AD[24]
Pin
A13
A14
B1
B2
A9
A10
A11
A12
B3
B4
A5
A6
A7
A8
A1
A2
A3
A4
Datasheet 33
82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 2 of 6) (Continued)
Signal Name
PCI_AD[28]
PCI_AD[29]
CLKRUN#
SMBDATA
GND
LED1 / ACT#
GND
MDI0+
MDI0-
PCI_AD[18]
PCI_AD[19]
PCI_AD[20]
GND
GND
GND
GND
PCI_AD[26]
PCI_AD[27]
GND
PCI_AD[31]
RST#
SMBALRT#
LED2 / LINK100#
LED3 / LINK1000#
CTRL_25
REF
PCI_AD[21]
M66EN
REQ#
CBE3#
NC
GND
AVDDL (2.5 V)
NC
AVDDL (2.5 V)
NC
GND
NC
Pin
D4
D5
D6
D7
C14
D1
D2
D3
C10
C11
C12
C13
C6
C7
C8
C9
D8
D9
D10
D11
D12
D13
D14
C2
C3
C4
C5
B12
B13
B14
C1
B5
B6
B7
B8
B9
B10
B11
34 Datasheet
Table 36. Signal Names in Pin Order (Sheet 3 of 6) (Continued)
Signal Name
GND
GND
NC
MDI2+
MDI2-
CLK
VIO
TRDY#
FRAME#
CBE2#
GND
GND
GND
GND
GND
GND
VDDO (3.3V)
GND
PCI_AD[17]
GND
GND
GND
GND
GND
GND
GND
DVDD (1.5V)
DVDD (1.5V)
MDI1+
MDI1-
IRDY#
ZP_COMP
DVDD (1.5V)
DVDD (1.5V)
GND
GND
GND
GND
Pin
F14
G1
G2
G3
F10
F11
F12
F13
F6
F7
F8
F9
F2
F3
F4
F5
G4
G5
G6
G7
G8
G9
G10
E12
E13
E14
F1
E8
E9
E10
E11
E4
E5
E6
E7
E1
E2
E3
Datasheet
Networking Silicon — 82540EP
35
82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 4 of 6) (Continued)
Signal Name
NC
MDI3+
MDI3-
PAR
PERR#
GNT#
NC
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
AUX_PWR
NC
GND
AVDDL (2.5 V)
DVDD (1.5V)
GND
STOP#
INTA#
DEVSEL#
ZN_COMP
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
GND
GND
DVDD (1.5V)
XTAL2
PCI_AD[16]
GND
VDDO (3.3V)
VDDO (3.3V)
DVDD (1.5V)
DVDD (1.5V)
Pin
J10
J11
J12
J13
J6
J7
J8
J9
J2
J3
J4
J5
H12
H13
H14
J1
J14
K1
K2
K3
K4
K5
K6
H8
H9
H10
H11
H4
H5
H6
H7
G11
G12
G13
G14
H1
H2
H3
36 Datasheet
Table 36. Signal Names in Pin Order (Sheet 5 of 6) (Continued)
Signal Name
AVDDL (2.5 V)
DVDD (1.5V)
DVDD (1.5V)
GND
JTAG_TMS
JTAG_RST#
JTAG_TCK
PCI_AD[11]
PCI_AD[12]
PCI_AD[13]
CBE0#
PCI_AD[5]
GND
PCI_AD[1]
CLK_VIEW
FL_CE#
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
DVDD (1.5V)
GND
VDDO (3.3V)
XTAL1
PCI_AD[14]
PCI_AD[15]
CBE1#
DVDD (1.5V)
DVDD (1.5V)
GND
NC
EE_SK
FL_SI
SDP7
JTAG_TDI
JTAG_TDO
GND
PCI_AD[10]
Pin
M6
M7
M8
M9
M2
M3
M4
M5
L12
L13
L14
M1
L8
L9
L10
L11
M10
M11
M12
M13
M14
N1
N2
L4
L5
L6
L7
K14
L1
L2
L3
K7
K8
K9
K10
K11
K12
K13
Datasheet
Networking Silicon — 82540EP
37
82540EP — Networking Silicon
Table 36. Signal Names in Pin Order (Sheet 6 of 6) (Continued)
Signal Name
PCI_AD[9]
PCI_AD[7]
PCI_AD[4]
VDDO (3.3V)
PCI_AD[0]
VDDO (3.3V)
FL_SCK
EE_DO
NC
GND
SDP6
SDP0
NC
VDDO (3.3V)
PCI_AD[8]
PCI_AD[6]
PCI_AD[3]
PCI_AD[2]
EE_CS
GND
FL_SO
EE_DI
CTRL_15
VDDO (3.3V)
SDP1
NC
Pin
P8
P9
P10
P11
P4
P5
P6
P7
P12
P13
P14
N14
P1
P2
P3
N10
N11
N12
N13
N6
N7
N8
N9
N3
N4
N5
38 Datasheet
Networking Silicon — 82540EP
5.5
Visual Pin Reference
•
A B C D E F G H J K L M N P
14
NC
PHY
REF
MDI-
[0]
NC
MDI-
[1]
MDI-
[2]
VSS
MDI-
[3]
XTAL2 XTAL1 JTCK JTDO SDP[0] NC
VSS
MDI+
[1]
MDI+
[2]
1.5V
MDI+
[3]
NC 3.3V
JTRST# JTDI SDP[6] SDP[1]
13
12
11
10
9
8
TEST
LINK
3.3V
SMB
CLK
LAN
PWRGD
AD30
CTRL
25
MDI+
[0]
LINK
1000
LINK
100
SMB
ALRT#
VSS
ACT
LED
VSS
RST#
AD31
SMB
DAT
CLK
RUN#
NC
2.5V
PHY
NC
2.5V
PHY
VSS
1.5V
1.5V
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
2.5V
PHY
VSS
VSS
VSS
VSS
NC
1.5V
VSS
VSS
1.5V
AUX
PWR
1.5V
1.5V
1.5V
1.5V
VSS
1.5V
1.5V
1.5V
1.5V
JTMS SDP[7]
VSS
1.5V
1.5V
2.5V
PHY
FLSH
SI
EESK
FLSH
CE_N
CLK
VIEW
VSS
NC
EEDO
FLSH
SCK
3.3V
3.3V
CTRL
15
EEDI
FLSH
SO
VSS
14
13
12
11
10
9
8
7
3.3V
VSS AD29 VSS VSS VSS VSS 1.5V
1.5V
1.5V
NC AD1 AD0 EECS
7
6
PME# AD27 AD28 VSS VSS VSS 1.5V
1.5V
1.5V
1.5V
VSS VSS 3.3V
AD2
6
5
AD25 AD26 NC VSS VSS VSS 1.5V
1.5V
1.5V
1.5V
1.5V
AD5 AD4 AD3
5
4
3
IDSEL
3.3V
AD24
VSS
CBE# [3]
REQ#
VSS
AD20
VSS
AD17
VSS PCIZP
CBE#
[2]
TRDY#
PCIZN
DEV
SEL#
NC
GNT#
3.3V
3.3V
1.5V
CBE#
[0]
CBE#
[1]
AD13
2
SERR# AD23 M66EN AD19 VSS
FRAME
#
VIO INTA# PERR# VSS AD15 AD12
AD7
AD9
AD10
AD6
AD8
3.3V
4
3
2
1
NC AD22 AD21 AD18 3.3V
IRDY# CLK STOP# PAR AD16 AD14 AD11 VSS NC
1
A B C D E F G H J K L M N P
Figure 12. Ball Grid Array / Pin Reference for 196-TFBGA (thru-the-top view)
Datasheet 39

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