ELTEC BAB 40/60 Automation Board Hardware Manual

PDF

Dokument

Oglas

elektronik mainz

B A B - 4 0 / 6 0

Basic Automation Board

Hardware Manual

Revision 1 A

Revision History BAB-40/60

Rev. Changes Date

1 A First Edition valid for BAB-40/60 Hardware Revision 1.A 01.09.95, G.M. (H.K.)

WARNING !

This equipment generates and can radiate radio frequencies. If not installed in accordance with the instruction manual, it may cause interference to radio communications. The equipment has not been tested for compliance with the limits for class A computing devices, pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against such interference, but temporary usage is permitted as per regulations. Operation of this equipment in a residential area is likely to cause interference, in which case the user, at his own expense is required to take whatever measures may be required to shield the interference.

DISCLAIMER!

The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. ELTEC reserves the right to make changes to any products to improve reliability, function or design. ELTEC does not assume any liability arising out of the application or use of any product or circuit described in this manual; neither does it convey any license under its patent rights nor the rights of others. ELTEC products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify ELTEC of any such intended end use whereupon ELTEC shall determine availability and suitability of its product or products for the use intended.

ELTEC points out that there is no legal obligation to document internal relationships between any functional modules, realized in either hardware or software, of a delivered entity.

This document contains copyrighted information. All rights including those of translation, reprint, broadcasting, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part, are reserved.

EUROCOM is a trademark of ELTEC Elektronik AG. Other brands and their products are trademarks of their respective holders and should be noted as such.

ELTEC Elektronik AG

Galileo-Galilei-Str. 11 Postfach 42 13 63

D-55129 Mainz D-55071 Mainz

Telephone +49 (61 31) 9 18-0

Telefax +49 (61 31) 9 18-1 99

BAB-40/60 Table of Contents

Page

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII

List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX

Scope of Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XI

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XI

Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XII

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .XIII

How to Use this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XV

1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Technical Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3.1

CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2

RAM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.3

PCMCIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.4

EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.5

Graphics/ Keyboard Interface (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.6

Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.7

SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.8

Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.9

CIO Counters/ Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.10

Parameter RAM and Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.11

Revision EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.12

VIC Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.13

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.14

Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hardware Manual I

Table of Contents (Continued) BAB-40/60

Page

1.3.15

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3.16

VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.16.1 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.16.2 VMEbus Master Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.16.3 VMEbus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.17

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.18

BAB Extension Bus (BEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.19

Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.20

Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.4 Definition of Board Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4.1

VMEbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4.2

PCMCIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.3

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.4

SCSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.5

Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.6

MTBF Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.7

Environmental Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.8

Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1.1

SIMM Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1.2

PCMCIA Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1.3

Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.3.1 Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.3.2 Graphic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.4

Serial Interface Level Converter (SILC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1.5

Ethernet Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.1.6

SCSI Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.2 Default Board Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

II Hardware Manual

BAB-40/60 Table of Contents (Continued)

Page

2.3 Jumpers and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3.1

System Controller (J301) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3.2

Serial Interface CHAN.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.3.3

Reset (J1401). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.4

Pin 1 Connection of EPROM (J1605). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.5

EEPROM Write Enable (J1702) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.6

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.6.1 VMEbus Slave Address (S901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3.6.2 Hardware Configuration (S902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3 Programmers Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.1

RAM Access from the Local CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.2

RAM Access from the VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.3

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2.4

RAM Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.5

RAM Access from the BEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.6

RAM Access from ILACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.3 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3.1

System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3.2

VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.2.1 Longword Access to Wordwide Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.2.2 Address Modifier Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.2.3 Read-Modify-Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.2.4 A16 Slave Interface (ICMS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.4 PCMCIA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4.1

Interface Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4.2

Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4.3

Card Control Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.4.4

Card Status Register (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Hardware Manual III

Table of Contents (Continued) BAB-40/60

Page

3.4.5

Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4.6

Window Register (WIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.5 VIC Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.6 Battery-Backed Parameter RAM and Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.6.1

Parameter RAM (NVRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.6.2

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7 CIO Counter / Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.8 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.9 Revision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.10 Cache Coherency and Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.11 Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.11.1

Serial Communication Controller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.11.2

Serial Interface Level Converter (SILC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.11.2.1 SILC Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.12 Ethernet Interface (802.3/10base5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.13 SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.13.1

SCSI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.14 IOC-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.14.1

Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.15 Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.16 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.17 Bus Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.18 System Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.19 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.19.1

Local Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.19.2

VMEbus Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Hardware Manual

BAB-40/60 Table of Contents (Continued)

Page

3.20 Indivisible Cycle Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.20.1

Deadlock Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.20.2

TAS Violation on ‘040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.21 Default Parameters for RMon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.21.1

Group A: I/O Initialization ($0000.0800 - $0000.0AEF) . . . . . . . . . . . . . . . . . . . . . 78

3.21.1.1

VIC Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.21.1.2

SCC Port A Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.21.1.3

SCC Port B Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.21.1.4

CIO Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.21.2

Group B: Address Information ($0000.0AF0 - $0000.0B47). . . . . . . . . . . . . . . . . . 80

3.21.2.1

ICF1 Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.21.2.2

VMEbus A32 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.21.2.3

VMEbus A32 Slave Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.21.2.4

VMEbus Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.21.3

Group C: Hooks ($0000.0B48 - $0000.0B6F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.21.4

Group D: Boot Parameters ($0000.0B70 - $0000.0C57) . . . . . . . . . . . . . . . . . . . . . 82

3.21.4.1

Autoboot Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.21.4.2

Operating System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.21.4.3

SCSI Controller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.21.4.4

SCSI Controller Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.21.4.5

SCSI Logical Unit Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.21.4.6

Special Boot Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.21.4.7

Sector Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.21.4.8

Base Address of RAM/ROM/ PCMCIA Boot . . . . . . . . . . . . . . . . . . . . 84

3.21.4.9

Retry Counter for Network Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.21.4.10 Delay until Auto Starts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.21.4.11 Logical Sector Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.21.4.12 Device Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.21.4.13 Own Internet Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.21.4.14 Internet Boot File Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.21.4.15 BootP Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.21.4.16 Network Boot Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.21.4.17 Server Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.21.5

Group E: Board Information ($0000.0C58 - $0000.0C9B) . . . . . . . . . . . . . . . . . . . 87

3.21.5.1

Character I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.21.5.2

Watchdog Enable Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.21.5.3

Watchdog Time-Out Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.21.5.4

Internal Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Hardware Manual V

Table of Contents (Continued) BAB-40/60

Page

3.21.5.5

Ethernet Node Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.21.5.6

CPU Board Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.21.5.7

RMon Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.21.5.8

Size of Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.21.6

Group F: Video Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.21.6.1

Graphic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.21.6.2

Graphic Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.21.6.3

Display Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.21.6.4

Size of Graphic Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.21.6.5

Size of Display Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.21.6.6

Number of Fore-/Background Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3.21.6.7

Number of Columns and Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.21.6.8

Video Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.21.6.9

Position of Character Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.21.6.10 Video Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.21.6.11 Keyboard Typamatic Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.21.6.12 Keyboard Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.21.7

Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Appendix:

A.1 Mnemonics Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.1.1

Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.1.2

Data Transfer Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.1.3

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

A.2 Address Modifiers on VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

A.3 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

A.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Technical Action Request Form Sheet

Reader Comments Form Sheet

VI Hardware Manual

BAB-40/60 List of Tables

List of Tables

Page

Table 1: CAS2 Operations on the Various Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2: Usable Bandwidth of the RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3: 6-Pin Telephone Jack Connector CHAN.1 (MOUSE/RS 232 PORT X701) . . . . . . . . . . . 14

Table 4: 15-Pin AUI Connector (ETHERNET X801) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5: 9-Pin Min-D Connector (male) CHAN.2 (X702) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6: Pin Assignment of VMEbus Connector (X101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7: Pin Assignment of Connector X102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8: Pin Assignment of Power Connector (X103) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9: Pin Assignment of BGB (X201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10: Pin Assignment of BEB (X222) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11: SCSI Connector 8-bit X103 on ADAP-200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12: Recommended SIMMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13: Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14: J301 (System Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15: J701 (CHAN.2 DCD/DSR Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16: J702 (CHAN.2 DCD/Receive Clock Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17: J703 (DTR/Transmit Clock Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 18: J1401 (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19: J1605 (Pin 1 Connection of EPROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 20: J1702 (EEPROM Write Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 21: Hex Switch S901 (VMEbus Slave Address). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22: Hex Switch S902 (Hardware Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 23: Address Assignment of BAB-40/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 24: Local I/O Address Assignment for BAB-40/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 25: Slave Base Address Register Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26: Enable Slave Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27: Intercommunication Register Location on VMEbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 28: Address Assignment of SRAM/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 29: Address Assignment of the Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 30: Address Assignment of the System CIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 31: Address Assignment of Watchdog Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 32: Watchdog Configuration Register at $FEC5.2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 33: IOC-2 Control Register at $FEC7.00A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 34: I

C Control Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Hardware Manual VII

List of Tables (Continued) BAB-40/60

Page

Table 35: Address Map of the Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 36: Snoop Control Register Layout for BAB-40/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 37: Snoop Control Encoding for BAB-40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 38: Snoop Control Encoding for BAB-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 39: RAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 40: Time Constant Values for SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 41: Address Assignment of the SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 42: Pin Assignment for SILCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 43: Ethernet Controller Address Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 44: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 45: Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 46: System Control Register Layout (System CIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 47: VIC Interrupt Priority Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 48: Local Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 49: Default Parameters of RMon 2.8 located on BAB-40/60 . . . . . . . . . . . . . . . . . . . . . . . . . . 75

VIII Hardware Manual

BAB-40/60 List of Figures

List of Figures

Page

Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2: PCMCIA Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 3: Installation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4: Location of Jumpers, Interface Connectors and Switches . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5: Serial Interface CHAN.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 6: Relative Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 7: PCMCIA Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 8: Card Control Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 9: Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 10: Card Status Register (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 11: Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 12: Window Register (WIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Hardware Manual IX

X Hardware Manual

BAB-40/60

Scope of Delivery

Description:

BAB-40 Basic Automation Board

BAB-60 Basic Automation Board

Scope of Delivery / Options

Order No.:

V-BAB.-A400

V-BAB.-A600

Options

Description:

SCSI SCSI option

Order No.:

V-BAB.-Z001 i

The last letter of the order numbers refers to the hardware revision and is subject to changes. Please contact ELTEC for information about valid order numbers.

Example: V-E16.-B105

Revision number, subject to change!

Hardware Manual XI

Related Products BAB-40/60

Related Products

Description:

Documentation: Hardware Manual BAB-40/60

Service Manual BAB-40/60 including:

Software Manual RMon (W-FIRM-A209)

BEB Specification (V-BEB.-A990)

IOC-2 Data Sheet (V-DTBT-A924)

Z85230 (V-DTBT-A935)

MK48T02/12 (V-DTBT-A907)

Z8536 (V-DTBT-A908)

VIC068 (V-DTBT-B914)

NCR53C710 (V-DTBT-A934)

ILACC AM79C900 (V-DTBT-A925)

Hardware: BAB Graphics Module

ADAP: to adapt signals on P2 to

SCSI (8-bit) and I/O signals

ADAP: to connect AT-keyboard to

PS/2 compatible connector

CONV: Cheapernet/10BaseT MAU

RS 232 SILC

RS 422 SILC

RS 485 SILC

Cable (V.24 for terminal)

Order No.:

V-BAB.-A490

V-BAB.-A491

V-BAB.-A410

V-ADAP-A200

V-ADAP-A210

V-CONV-A500

V-SILC-E200

V-SILC-B300

V-SILC-A400

V-CABL-A144

XII i

The last letter of the order numbers refers to the hardware revision and is subject to changes. Please contact ELTEC for information about valid order numbers.

Example: V-E16.-B105

Revision number, subject to change!

Hardware Manual

BAB-40/60 Conventions

Conventions

If not otherwise specified, addresses are written in hexadecimal notation and identified by a leading dollar sign ("$").

Signal names preceded by a slash ("/"), indicate that this signal is either active low or that this signal becomes active with the trailing edge.

b bit

B byte

K kilo, means the factor 400 in hex (1024 decimal)

M mega, the multiplication with 100 000 in hex (1 048576 decimal)

MHz 1 000 000 Hertz

Board-specific abbreviations:

ASR

AUI

BEB

BGB

BLT

BTO

CAS

CAS2

CLUT

CPU

CSR

Address Substitution Register

Attachment Unit Interface

BAB Extension Bus

BAB Graphic Bus

Block Transfer

Bus Time-out

Column Address Strobe

Compare and Swap 2 Instruction

Color Look-up Table

Central Processing Unit

Control/Status Register

CTS

DAC

DMA

Clear to Send

Digital to Analog Converter

Direct Memory Access

DTE Data Terminal Equipment

EEPROM Electrically Erasable Programmable Read Only Memory

EPROM Erasable Programmable Read Only Memory

ESR

FIFO

FPU

IACK

ICF

ICGS

ICMS

ILACC

IOC-2

Enable Slave Register

First In First Out

Floating Point Unit

Interrupt Acknowledge

Interprocessor Communication Facility

Interprocessor Communication Global Switches

Interprocessor Communication Module Switches

Integrated Local Area Communications Controller

I/O Controller Asic

Hardware Manual XIII

Conventions (Continued) BAB-40/60

SCSI

SCR

SILC

SRAM

SMR

TTL

VIC

VRAM

UAT

PLD

PLL

RAM

RAS

RMC

RTC

RTS

SBR

LAN

LIRQ

MAU

MBAR

MMU

NVRAM

PCB

PCMCIA

Local Area Network

Local Interrupt Request

Medium Attachment Unit

Memory Base Address Register

Memory Management Unit

Nonvolatile RAM

Printed Circuit Board

Personal Computer Memory Card International Association

Programmable Logic Device

Phase Locked Loop

Random Access Memory

Row Address Strobe

Read-Modify-Write Cycle

Real-time Clock

Request to Send

Slave Base Address Register

Small Computer Systems Interface

System Control Register

Serial Interface Level Converter

Static RAM

Slave Mask Register

Transistor Transistor Logic

VMEbus Interface Chip

Video RAM

Unaligned Transfer

XIV Hardware Manual

BAB-40/60 How to Use this Manual

How to Use this Manual

Document Structure This manual is divided into the following chapters:

Chapter 1 Specification contains a list of distinguishing features, a block diagram with a general description, a description of the main building blocks and the board parameters.

Chapter 2 Installation describes the requirements and the step-by-step installation. A table shows the default settings of jumpers and switches followed by a detailed description of adjustable functions.

Chapter 3 Programmer Reference shows the address map and describes the address ranges in detail. Special functions are also described in this chapter.

The Appendix contains references to additional literature, an index, and a glossary and necessary extracts of data sheets.

Document Conventions Font Types:

Font

Helvetica, 8 Pt

Helvetica, 10 Pt

Times, italic

Courier, bold

Times, bold

Use

Tables and drawings

Signal names, formulars

Notes

Program code, function names, commands

Emphasized text, e.g. headlines

Hardware Manual XV

How to Use this Manual (Continued) BAB-40/60 i

Other Conventions:

Indicates information that requires close attention.

Indicates critical information that is essential to read.

Indicates information that is imperative to read. Skipping this material, possibly causes damage to the system.

XVI Hardware Manual

BAB-40/60 1 Specification

1 Specification

1.1 Main Features

•One 68(EC)040/060 CPU at 50 MHz or 66 MHz

•Memory

- PS/2 SIMM memory module (1, 2, 8, 16, 32 MB) for data/program storage (44 MB/s at 33 MHz bus speed)

- 2 KB SRAM and RTC for storage of variable system parameters

MK48T12 (MK48T18/8 KB, DS1644/32 KB)

- Up to 1 MB x 8 K EPROM

•Two PCMCIA sockets on front panel for two type I or II PC Cards or one type III PC Card (Flash, SRAM and ATA-HD only)

•One internal PCMCIA socket (type I, type II, or with some restrictions type III (Flash, SRAM and ATA-HD only))

•Ethernet interface (32-bit ILACC)

•VMEbus Interface Controller:

- System controller and arbiter

- VMEbus interrupter and interrupt handler

- 32-bit slave BLT 20 MB/s

- Master / slave write posting

•IOC-2 gate array:

- 68040 to 68020 bus converter

- Dynamic bus sizing for VMEbus and BEB

- Translation of BLT into bursts on '040 bus to allow snooping of BLT cycles

- Separate arbitration on '040 and '020 bus

- I/O bus interface

- Support for VMEbus UATs to allow snooping

- Interface for a single bytewide EPROM

•Three 16-bit timer / counter

•Two serial ports (RS 232, RS 422, RS 485)

•Smart SCSI-2 (NCR 53C710) interface with burst capability (max.

transfer capacity 10 MB/s) and single-ended 8-bit SCSI data bus

•Two rotary switches for selection of operation modes and base address

•Status display on front panel

•Watchdog timer 130 ms ... 17 min

•BEB for interfacing to various mezzanine busses

•BGB for graphic and keyboard module

Hardware Manual 1

1 Specification BAB-40/60

1.2 General Description

Figure 1: Block Diagram

CPU

68040/060

50/66 MHz

Memory

Module

1-32 MB

Front

Panel

CIO

8536

Slave Operation

Addr.

Mode

I/O Bus

Watchdog

1M x 8

EPROM

32KB/2KB x 8

NVRAM

RTC

Revision

EEPROM

512 x 8

SILC

Serial Line

RS232

Serial

Controller

8530

Ethernet

Controller

ILACC

Keyboard

Graphic

Module 512 KB / 1 MB

VRAM/

Video Contr.

Keyboard

Controller

BGB

NCR53C710

SCSI

Controller

8-bit SCSI-2

IOC-2

VMEbus

Controller

VMEbus

Buffer/Count./

Decoder

VMEbus

Row A

Row C

Row B

PCMCIA2

PCMCIA1

PCMCIA

Controller

PCMCIA0

BEB

2 Hardware Manual

BAB-40/60 1 Specification

The BAB-40/60 is a highly integrated high-performance single-board

VMEbus computer with optional graphics display. It is designed to offer as many features as possible on a single slot VMEbus board. Suitable intelligent or high integrated components are used to achieve this density of computing power.

On the BAB-40 there is one 68040 CPU, clocked at 50 or 66 MHz. Onchip caches for program and data (4 KB capacity each) and the on-chip floating-point units allow 35 MIPS at 66 MHz.

The 68060 CPU on the BAB-60 offers 2.5 times the performance of a

68040 clocked at the same frequency.

Additionally, backward compatibility with existing 68000-family software is guaranteed.

The main memory is placed on a separate PS/2 SIMM memory module.

This easily allows to expand the memory up to 32 MB without any changes necessary at the CPU board. The main memory is directly accessed via the 32-bit processor bus.

The major drawback of the 68040/60 is the deletion of dynamic bus sizing. This requires 68020/30 applications to be modified if they access word devices with longword instructions. The longword accesses have to be split by software into two word accesses which slows down the performance. Instead of this, the IOC-2 hardware generates the needed bus cycles if the addressed device acknowledges a smaller data size than the CPU requested.

One of the main design goals of the BAB-40/60 is efficient use of the

CPU's high speed bus. Thus, the following design rules are established:

•Use of intelligent peripheral devices which are able to perform tasks independent from the main CPU (NCR 53C710, ILACC).

•Independent 68020-like bus for VMEbus, Ethernet or BEB with separate arbitration.

•Minimum interference between CPU bus, ‘020 bus and I/O bus.

•Decoupling of VMEbus and CPU bus via FIFO for BLT.

On traditional designs there could only be one bus master on the whole board at a time. For example, if a BLT was in progress, the CPU was blocked for the duration of the BLT. At the BAB-40/60 the FIFO in the

IOC-2 collects the data while the CPU still accesses the DRAM.

Hardware Manual 3

1 Specification BAB-40/60

In order to enhance system security, the BAB-40/60 incorporates a watchdog timer. It must be retriggered periodically, otherwise the watchdog generates a reset.

Two serial ports are located on the BAB-40/60. One, using a 6-pin shielded RJ11 jack on the front panel, is intended for connection of a terminal or a mouse. The other uses a 9-pin Min-D male connector on the front panel. It can be configured to support either RS 232 or RS 422/485 standard via SILCs (Serial Interface Level Converters).

The integrated real-time clock allows the operating system to provide date and time for revision control. The clock is powered by an internal lithium battery. 2 (8, 32) KB of battery-backed RAM are used for storage of system dependent parameters.

The four LED status display on the front panel indicates the condition of the processor.

Two hex-code switches (software readable) are used by the firmware to set up the operating mode and the VMEbus base address of the board.

The VMEbus interface of the BAB-40/60 uses the VIC068 VMEbus

Interface Controller gate array.

One 1M x 8 EPROM holds the firmware.

The on-board Ethernet interface provides connection to most popular local area networks (LAN).

A sophisticated SCSI-2 interface is also located on the BAB-40/60. The controller chip is very fast and intelligent so that it forms a very efficient

SCSI interface with max. transfer rates of 10 MB/s.

The on-board BAB extension bus (BEB) allows easy hardware extension of the BAB-40/60 using various mezzanine busses.

The BAB graphic bus (BGB) allows flexible extension of the BAB with graphics/keyboard modules.

The three PCMCIA sockets support several types of PC Cards (harddisks,

SRAM, Flash EPROM, ...).

4 Hardware Manual

BAB-40/60

1.3 Technical Details

The BAB-40/60 consists of the following main blocks:

•CPU

•RAM Module

•PCMCIA Interface

•EPROM

•Graphics/Keyboard Interface (optional)

•Ethernet Interface

•SCSI Interface

•Serial I/0

•CIO Counters / Timers

•Parameter RAM and Real-Time Clock

•Revision EEPROM

•VIC Timer

•Watchdog Timer

•Status Display

•Reset

•VMEbus Interface

•Interrupt Sources

•BAB Extension Bus

•Software

•Connectors

1 Specification

Hardware Manual 5

1 Specification

1.3.1

CPU

BAB-40/60

The BAB-40/60 is equipped with Motorola’s 68040/060 CPU, clocked with 50 or 66 MHz. All internal bus operations are synchronous to this clock. The CPU uses burst mode to access the main memory. The BAB-60 uses the 68040 bus mode of the 68060.

The CPU handles all interrupts generated by the VIC.

Non-interruptable read-modify-write cycles (TAS command) are supported between VMEbus and the CPU. RMC cycles from the VMEbus to the local RAM are only indivisible when they are byte size. CAS2 instructions have limited support.

Table 1: CAS2 Operations on the Various Busses

1st op local RAM

'020 bus (BEB)

VMEbus

local RAM

'020 bus (BEB)

VMEbus

local RAM

'020 bus (BEB)

VMEbus

2nd op

local RAM

'020 bus (BEB)

VMEbus

VMEbus no yes yes no indivisible yes yes yes no yes

6 Hardware Manual

BAB-40/60 1 Specification

1.3.2

RAM Module i

The DRAM is accessed by the following sources:

•CPU

•SCSI Controller

•Ethernet Controller

•BEB

•VMEbus

Burst mode is supported for accesses of:

•CPU

•SCSI Controller

•VMEbus BLT

The base address of the DRAM seen from the CPUs is fixed to

$0000.0000. To avoid programming of the MMU, the DRAM is mirrored as non-cacheable RAM.

The base address for accessing the RAM from the VMEbus as well as the window size is programmable. The on-board firmware uses hex switch

S901 to program the VMEbus address decoder and mask registers.

When using A24 addressing from the BEB, to access the BAB-40/60 RAM, the address translation logic has to be programmed to supply the local addresses A(24) to A(26).

The following table summarizes the usable bandwidth of the RAM including precharge and refresh.

Table 2: Usable Bandwidth of the RAM

Bus Clock

DRAM read

DRAM write

33 MHz: (MB/s)

25 MHz: (MB/s)

Hardware Manual 7

1 Specification BAB-40/60

1.3.3

1.3.4

1.3.5

Graphics/

Keyboard

Interface

(Optional)

1.3.6

PCMCIA

Interface

EPROM

Ethernet

Interface

The three socket PCMCIA interface uses a MACH445 PLD. It incorporates several control registers and translates the signals from the

BAB’s ‘020 bus to the three PCMCIA sockets. The data and address lines of the sockets are isolated from the ‘020 bus via buffers. This allows live insertion and removal of PC Cards under certain circumstances (when none of the PC Cards is accessed by the CPU). To ensure that unused areas of a PC Card are read as ‘1’ the data lines of each slot are pulled high. To allow programming of FLASH devices +12 V can be applied to the sockets via optocoupler devices.

The pin assignment of the 32-pin socket corresponds with the JEDEC standard. The socket is designed for use with 32-pin EPROMs only. These

EPROM types range from 1 Mb up to 8 Mb (27C010 to 27C080).

The EPROM access time is programmable via IOC-2 register from 4 to 36 wait-states (60 ns to 810 ns maximum access time).

After reset, the EPROM is mapped to $0000.0000 so the initial stack pointer and reset vector can be read. During initialization, it is mapped to its normal address ($FE80.0000) and the DRAM is located at address

$0000.0000. The EPROM is accessed with six wait-states (120 ns access time) per byte at 33 MHz.

The software in the basic EPROM (RMon) initializes all hardware according to the parameters in the basic EPROM or the NVRAM

($FEC2.0000).

Various graphics/keyboard modules can be installed on the BAB-40/60 via the BGB connector. All modules support a PS/2 compatible keyboard.

The standard module has 1 MB VRAM and displays up to

1024x768 pixels with 4/8 bit per pixel and 60 MHz refresh rate. Up to

800x600 72 Hz refresh rate is possible. The monitor is connected to the module via a standard 15-pin VGA connector.

The Ethernet interface is based on the Integrated Local Area

Communications Controller (ILACC - AM79C900).

A main feature of the ILACC and its on-chip DMA channel is the flexibility and speed of communication. The internal Manchester

Encoder / Decoder of the ILACC is compatible with the IEEE-802.3

specification. Via the AUI connector on the front panel the BAB-40/60 is attached to Ethernet (Cheapernet, 10BaseT) networks.

8 Hardware Manual

BAB-40/60 1 Specification

1.3.7

SCSI Interface Single-ended 8-bit SCSI-2 signals are fed into row A and C of the

VMEbus P2 connector (X102). An ADAP-200 is plugged onto the rear side of the backplane to interface to standard 8-bit SCSI connectors.

The NCR53C710 SCSI controller uses its own code fetching and SCSI data transfer from the DRAM. The processor executes SCSI SCRIPTS to control the actions on the SCSI and the CPU bus. SCRIPTS is a specially designed language for easy SCSI protocol handling. It dramatically reduces the CPU activities. The SCRIPTS processor starts SCSI I/O operations in approximately 500 ns where traditional intelligent host adapters require 2-8 ms.

1.3.8

Serial I/O The BAB-40/60 offers two serial I/O lines, implemented by one Z8530

SCC. CHAN.1 is a RS 232 two wire handshake interface. CHAN.2 uses a removable serial interface level converters (SILC). As shipped, a RS 232 level converter SILC is installed featuring hardware handshake as well as the XON / XOFF protocol. Additional level converter plug-ins for RS 422 and RS 485 are available.

The baud rate generator is driven by 5 MHz, allowing baud rates from

50 b/s to 38.4 kb/s.

1.3.9

CIO Counters/

Timers

The BAB-40/60 offers three independent, programmable 16-bit counters / timers integrated in the CIO.

1.3.10 Parameter

RAM and Real-

Time Clock

The real-time clock is designed with the MK48T12 timekeeper RAM. It combines a 2KBx8 CMOS SRAM (parameter RAM, NVRAM), a bytewide accessible real-time clock, a crystal, and a long-life lithium battery, all in one package. Alternatively, a MK48T18 device can be used which offers 8 KB SRAM or a DS1644 device which offers 32Kx8 KB

SRAM.

1.3.11 Revision

EEPROM

The revision EEPROM is realized by a 512x8B serial EEPROM which offers special board revision information. The lower half size of the

EEPROM is programmed by ELTEC and should not be modified by the user to guarantee board revision consistency. The upper 256 B can be used by the user to store additional information.

Hardware Manual 9

1 Specification BAB-40/60

1.3.12 VIC Timer The VIC contains a timer which can be programmed to output a periodic wave form on LIRQ2. The available frequencies are 50 Hz, 100 Hz, and

1000 Hz. The VIC timer is typically used as a tick timer for multi-tasking operating systems.

1.3.13 Watchdog

Timer

The watchdog timer monitors the activity of the microprocessor. If the microprocessor does not access the watchdog timer within the time-out period of 130 ms to 17 min, a reset pulse is generated. After reset, the watchdog timer is disabled. The time-out period becomes effective after the first access to the watchdog configuration register.

After reset the software can read PA7 of the CIO to distinguish between a watchdog reset and a reset generated by other sources. This watchdog indicator is only cleared by power-up reset, the reset switch, a VMEbus

SYSRESET

, a VIC remote reset, or by a write access to the watchdog.

The time-out period is derived from a quartz oscillator so that tolerances can be neglected.

1.3.14 Status Display The BAB-40/60 features a four LED display on the front panel and displays values from 0 - F.

This status display ($FEC3.0000) is designed as a read / write register and uses the least significant nibble of the byte.

1.3.15 Reset Reset may be initiated by six sources:

•supply voltage drop below 4.75 V or power-up

•reset jumper J1401

•VMEbus

SYSRESET

•VIC remote control reset register

•Watchdog

•CPU RESET instruction

10 Hardware Manual

BAB-40/60 1 Specification

1.3.16 VMEbus

Interface

1.3.16.1 System

Controller

Each BAB-40/60 board offers VMEbus master and slave interfaces.

Additionally, VMEbus system controller functions are available via the

VMEbus gate array (VIC).

The BAB-40/60 features a full slot-one system controller, including

SYSCLK , SYSRESET , bus time-out, IACK daisy chain driver, and a four level arbitration circuit. System controller capabilities are enabled when

J301 is closed.

1.3.16.2 VMEbus

Master

Interface

The master interface of the BAB-40/60 board supports 8, 16, and 32-bit data transfer cycles in A32, A24, and A16 addressing modes.

A special feature is provided to support longword accesses from the local

CPU to D16 VMEbus boards (dynamic bus sizing). Two control lines of the SCR enable longword breaking for the A32 and A24 area.

The VIC chip supplies the VMEbus address modifier signals. This is done by either routing FC0..2 line to AM0..2, or by driving these signals by an internal address modifier source register of the VIC ($FEC0.10B7). The

AM3..5 lines are driven depending on the actual data size, or by the address modifier source register. One output signal of the system control register is used to control this option.

The BAB-40/60 supports slave block transfer cycles.

1.3.16.3 VMEbus Slave

Interface

The BAB-40/60 supports A32 slave access to the DRAM and an A16 slave interface to access the interprocessor communication registers. The addresses for all of the slave interfaces are separately programmable.

1.3.17 Interrupt

Sources

The BAB-40/60 allows full utilization of both the powerful VMEbus interrupt structure and the 68040/060 CPU design.

1.3.18 BAB Extension

Bus (BEB)

The BEB port of the BAB-40/60 can carry slave-only, master-only or master-slave boards. The IRQ line of the BEB is connected to VIC’s

LIRQ5 input. The VIC has to be programmed to generate interrupts on level 2, because only level 2 IACK cycles are routed to the BEB.

Hardware Manual 11

1 Specification BAB-40/60

1.3.19 Software The local BAB-40/60 firmware (RMon) is stored in the on-board

EPROM. RMon provides the basic software layer of the board. Any operating system or application software is based on the RMon and uses its functionality:

•Power-On Initialization

•Configuration

•Various Bootstraps

•Externally Callable I/O Functions

•Application Hooks

Power-On Initialization

After RESET or power-on, the local hardware (VIC, serial I/O, CIO, video, keyboard interface, etc.) has to be initialized by the CPU. The initialization is affected by certain parameters taken either from the onboard NVRAM or from the EPROM (default values). Hex switch S902 selects whether the NVRAM or the default values are to be used.

The NVRAM parameters are certified by a checksum. If the checksum test fails, the default parameters are used independent of the switch setting.

After reset or power-on an automatic selftest routine checks the functional groups of the board and displays its results.

Configuration

The configuration program is completely menu driven. The program interactively shows the configuration parameters and allows their modification:

•I/O Configuration, e.g.: serial I/O, AT-keyboard, on-board video, baud rate, etc.

•Video Mode

•Bootstrap Configuration

•Internet Address of ILACC

•VMEbus Interface Configuration (VIC Programming)

12 Hardware Manual

BAB-40/60 1 Specification

Various Bootstraps

•OS-9 from SCSI Floppy

•OS-9 from SCSI Harddisk

•OS-9 from SCSI Tape

•OS-9 from ROM/RAM Disk

•OS-9 from PCMCIA

•Lynx from Tape

•Lynx from Harddisk

•Lynx from Floppy

•tftp-bootstrap from Ethernet including ARP and RARP protocols

•ROMed application bootstrap, suitable as well for VMEbus-downloaded applications under control of a VMEbus host

External Callable I/O Functions

•Enable/Disable IRQs

•Get Device Status

•Set Device Mode

•Character Raw I/O

•C-like functions getchar, putchar, printf

Application Hooks

Application programs may freely use the externally callable I/O functions and other information provided in the ‘RMon Fixed Public Location’.

Furthermore, a ROMed application can very easily be started interactively or automatically after RESET or power-on from RMon. The application autostart mechanism can be installed simply by setting the respective bootstrap configuration parameters.

Hardware Manual 13

1 Specification BAB-40/60

1.3.20 Connectors Table 3: 6-Pin Telephone Jack Connector CHAN.1

(MOUSE/RS 232 PORT X701)

Pin

Signal

RTS

TxD

GND

RxD

CTS

Description

Request to Send

Transmit Data

Signal Ground

Receive Data

Clear to Send

Table 4: 15-Pin AUI Connector (ETHERNET X801)

Signal

CI-S

CI-A

DO-A

DI-S

DI-A

VC n.c.

CO-S

CI-B

DO-B

DO-S

DI-B

VS n.c.

Pin

Description

Control In circuit Shield

Control In circuit A

Data Out circuit A

Data In circuit Shield

Data In circuit A

Voltage Common

Not connected

Control Out circuit Shield

Control Out circuit B

Data Out circuit B

Data Out circuit Shield

Data In circuit B

Voltage Plus

Voltage Shield

Not connected

14 Hardware Manual

BAB-40/60 1 Specification

Table 5: 9-Pin Min-D Connector (male) CHAN.2 (X702)

Pin

Signal

DCD

RxD

TxD

DTR

GND

DSR

RTS

CTS n.c.

Description

Data Carrier Detect

Receive Data

Transmit Data

Data Terminal Ready

Signal Ground

Data set ready

Request to Send

Clear to Send not connected

Hardware Manual 15

1 Specification i

Table 6: Pin Assignment of VMEbus Connector (X101)

A07

A06

A05

A04

A03

A02

A01

-12 V

+ 5 V

GND

/AS

GND

/IACK

/IACKIN

/IACKOUT

AM4

Row A

D00

D01

D02

D03

D04

D05

D06

D07

GND

SYSCLK

GND

/DS1

/DS0

/WRITE

GND

/DTACK

AM1

AM2

AM3

GND

(SERCLK)

(SERDAT)

GND

/IRQ7

/IRQ6

/IRQ5

/IRQ4

/IRQ3

/IRQ2

/IRQ1

(+5STDBY)

+ 5 V

/BR0

/BR1

/BR2

/BR3

AM0

Row B

/BBSY

/BCLR

/ACFAIL

/BG0IN

/BG0OUT

/BG1IN

/BG1OUT

/BG2IN

/BG2OUT

/BG3IN

/BG3OUT

Pin

A14

A13

A12

A11

A10

A09

A08

+12 V

+ 5 V

A21

A20

A19

A18

A17

A16

A15

Row C

D08

D09

D10

D11

D12

D13

D14

D15

GND

/SYSFAIL

/BERR

/SYSRESET

/LWORD

AM5

A23

A22

Signals in parentheses are not connected.

BAB-40/60

16 Hardware Manual

BAB-40/60 1 Specification

Table 7: Pin Assignment of Connector X102

Signal Row A

Pin

SCSIDB0

SCSIDB2

SCSIDB4

SCSIDB6

SCSIDBP0

GND

/SCSIACK

/SCSIMSG

/SCSIC/D

/SCSII/O

D25

D26

D27

D28

D29

D30

D31

GND

+ 5 V

D18

D19

D20

D21

D22

D23

GND

D24

A28

A29

A30

A31

GND

+ 5 V

D16

D17

A24

A25

A26

A27

Signal Row B

+ 5 V

GND

Reserved

Signal Row C

SCSIDB1

SCSIDB3

SCSIDB5

SCSIDB7

/SCSIATN

GND

/SCSIBSY

/SCSIRST

/SCSISEL

/SCSIREQ

+ 5 V

Hardware Manual 17

1 Specification

Table 8: Pin Assignment of Power Connector (X103)

Pin

Description

Power Good (/ACFAIL)

+5 V

+12 V

-12 V

GND

BAB-40/60

18 Hardware Manual

BAB-40/60 1 Specification

D19

D20

D21

D22

A07

D16

D17

D18

A03

A04

A05

A06

Row A

GND

A01

A02

D23

/DS

/WR

/DSACK1

/BERR

Table 9: Pin Assignment of BGB (X201)

Pin

D27

D28

D29

D30

A15

D24

D25

D26

A11

A12

A13

A14

Row B

A08

A09

A10

D31

A00

/AS

GND

16MHz

A23

64kHz

FC1

FC2

/LIRQ1

/CSKBD

/RESET

2kHz

A19

A20

A21

A22

Row C

A16

A17

A18

BCLK3

GND

+5V

/ISPEN

/CSGRAF

D15

D00

D01

D02

D11

D12

D13

D14

D03

D04

D05

D06

D07

Row E

TDO

TMS1

TCK

/TRST

D08

D09

D10

A31

SIZE0

SIZE1

+5V

GND

+12V

-12V

12VGND

A27

A28

A29

A30

Row D

A24

A25

A26

/DSACK0

/HALT

+5V

GND

TDI

1 2 19 20

Hardware Manual 19

1 Specification BAB-40/60

Pin Signal

1 +12V

2 A0

3 A2

4 A4

5 A6

6 A8

7 A10

8 A12

9 A14

10 GND

11 A16

12 A18

13 A20

14 A22

15 A24

16 A26

17 A28

18 A30

19 +5V

20 FC1

21 SIZE1

22 /CSBEB1

23 /DSACK0

24 /RMC

25 /IRQBEB

Table 10: Pin Assignment of BEB (X222)

Pin Signal

26 /BGACK

27 FC2

28 /WR

29 /HALT

30 /DSACK1

31 GND

32 D0

33 D2

34 D4

35 D6

36 D8

37 D10

38 D12

39 D14

40 GND

41 D16

42 D18

43 D20

44 D22

45 D24

46 D26

47 D28

48 D30

49 +5V

50 Reserved

Pin Signal

51 Reserved

52 +5V

53 D31

54 D29

55 D27

56 D25

57 D23

58 D21

59 D19

60 D17

61 GND

62 D15

63 D13

64 D11

65 D9

66 D7

67 D5

68 D3

69 D1

70 GND

71 /IACKBEB

72 /BRBEB

73 /AS

74 Reserved

75 /DS

85 A27

86 A25

87 A23

88 A21

89 A19

90 A17

91 GND

92 A15

93 A13

94 A11

95 A9

96 A7

97 A5

98 A3

99 A1

100 -12V

Pin Signal

76 /BGBEB

77 /BERR

78 /RESET

79 /CSBEB0

80 SIZE0

81 FC0

82 +5V

83 A31

84 A29

1 100

50 51

20 Hardware Manual

BAB-40/60 1 Specification i

Table 11: SCSI Connector 8-bit X103 on ADAP-200

Pin

Description

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

GND

TERM-PWR

Pin

ACK

RST

MSG

SEL

CIO

REQ

I/O

Description

GND

ATN

GND

BSY

All odd pins of the 50-pin SCSI connector except pin 25 are connected to ground. Pin 25 is left open.

Pin 26 is connected to +5 V via a Shottky diode to supply power to an external SCSI terminator.

Hardware Manual 21

1 Specification

1.4 Definition of Board Parameters

1.4.1

VMEbus •VMEbus interface according to specification ANSI/IEEE

STD 1014-1987 (Rev. D1.4)

•VMEbus Master Capabilities

- MD32

- MRMW8

•VMEbus Slave Capabilities:

- SADO32

- SRMW32

- UAT

- BLT

•Arbiter Options

- PRI, RRS

- BTO 4 µ s to 480 µ s

- SYSCLOCK generation

- BBSY filter

•Requester Options

- Any one of BR(0), BR(1), BR(2) or BR(3)

- Programmable Release when done (RWD)

- Release-on-request (ROR)

- Release-on-bus-clear (ROC)

- Bus capture and hold (BCAP)

- Programmable fair request timer 2 µ s ... 30 µ s.

•Interrupt Handler and Generator Capabilities

- Interrupt handler and generator on IRQ1 to IRQ7.

•Interrupter Options

- Any one of I(n) where 1 ≤ n ≤ 7.

BAB-40/60

22 Hardware Manual

BAB-40/60 1 Specification

•Address Range

- programmable extended/standard/short I/O extended access (A31-A24 and mask) short I/O (A15 -A8)

- Default: extended access 64 MB, short I/O 256 B

1.4.2

PCMCIA •Two type I or II PC Cards or one type III PC Card on the front

•One type I, II, or III PC Card internal. Type III with mechnical restrictions (see Section 2.1.2 ‘PCMCIA Installation’).

•All sockets support Flash, SRAM and ATA harddisk cards with 5 V supply voltage.

•AUI interface according to 802.3

1.4.3

Ethernet

1.4.4

SCSI •SCSI-2 (8 bit single ended)

•Transfer Speed

- asynchronous transfer 5 MB/s

- synchronous transfer 10 MB/s

•2 channels (50 b/s - 38.4 kb/s) 1.4.5

Serial I/O

1.4.6

MTBF Values •8325 h (computed after MTL HDBK-217E)

•111555 h (realistic value from industry standard experience)

Hardware Manual 23

1 Specification BAB-40/60

1.4.7

Environmental

Conditions

•Storage Temperature:

-35 ° C to +85 ° C

•Operating Temperature:

0 ° C to +60 °

•Maximum Operating Humidity:

85% relative

•Air temperature with forced air cooling of approx. 1 m/sec.

1.4.8

Power

Requirements with all/max. options; approx.:

- 4.8 A max.

3.6 A typ.

+5 VDC ± 5 %

- 0.5 A max.

0.3 A typ.

+12 VDC ± 10 % (includes supply of external MAU)

- 0.2 A max.

0.1 A typ.

-12 VDC ± 10 %

24 Hardware Manual

BAB-40/60 2 Installation

2 Installation

2.1 Introduction

•Carefully remove the board from the shipping carton.

- Save the original shipping container and packing material for storing or reshipping the board.

Avoid touching integrated circuits except in an electrostatic free environment. Electrostatic discharge can damage circuits or shorten their lifetime.

•Inspect the board for any shipping damage. If undamaged, the board can be prepared for system installation.

When unplugging boards from the rack or otherwise handling boards, do always observe precautions for handling electrostatic devices.

2.1.1

SIMM

Installation

Since upgrading the BAB-40 to BAB-60 requires some additional components, it is not recommended that this is done by the user.

Please contact ELTEC.

Generally all PS/2 SIMMs from 1 MB to 32 MB with symmetric

RAS/CAS addresses and better than 70 ns access time are suitable for the

BAB-40/60. Since the BAB-40/60 does not use parity checking, SIMMs with or without parity can be used, but SIMMs without parity should be preferred because they are usually cheaper and smaller. It is mandatory that the length of the SIMM board does not exceed 35 mm to fit on the

BAB-40/60.

Hardware Manual 25

2 Installation BAB-40/60

Table 12: Recommended SIMMs

SIMM Size Chip Size

1 MB

2 MB

4 MB

8 MB

16 MB

32 MB

1 M

4 M

1 M

4 M

16 M

4 M

16 M

No. of Chips Chip

Organization

256Kx4

256Kx16

256Kx18

256Kx4

256Kx16

256Kx18

1Mx4

1Mx16

1Mx4

1Mx16

4Mx4

No. of Banks

(RAS) single single single double double double single single double double single double

Before removing or installing the SIMM module switch power off.

The SIMM is simply plugged into the connector (it fits only in one orientation) and is automatically recognized by the RMon (please check the power-on message of the RMon). If RMon hangs with '5' in the LED display or reports the wrong size, installation was not correct or the SIMM is not suitable for the BAB-40/60.

Although the BAB-40/60 RAM design has been optimized for compatibility, layout of the SIMM's PCB and the type of the RAM chips may affect reliability. Therefore, ELTEC can't guarantee operation with all available SIMM modules. It is recommended to use

SIMMs of well-known manufacturers (Fujitsu, Hitachi, Toshiba,

Samsung, TI, ...).

26 Hardware Manual

BAB-40/60 2 Installation

2.1.2

PCMCIA

Installation

The PC Cards can easily be plugged into one of the three sockets when they have the right orientation. To avoid unintended removal of the PC

Cards on the front they can be locked with a metal plate and two screws

M3x6. The internal PC Card can also be fixed to withstand shock and vibration. For correct distance of the PC Card and the PCB, a washer is necessary between the PCB and the holder.

Figure 2: PCMCIA Installation

Holder

PC Card

PCB

Washer

Screw M2.5 x 6

Live insertion and removal of PC Cards is possible while none of the

PC Cards is accessed by the CPU. Since it is not easy to satisfy this condition it is recommended to avoid live insertion and removal.

When a type III PC Card is installed in the internal socket, the

VMEbus specification of the adjacent VMEbus slot is violated so that it must stay free.

Not all type III PC Cards fit into the internal socket. Only 5 V supply voltage cards are supported. For a detailed list of cards and drivers, please contact ELTEC.

Hardware Manual 27

2 Installation BAB-40/60

2.1.3

Board

Installation

The installation of the BAB-40/60 on VMEbus is not complicated. A suitably terminated VMEbus backplane is required. The power supply must meet the specifications described in Section 1.4 ‘Definition of Board

Parameters’. The processor board requires +5 V supply voltage; ± 12 V are needed for the RS 232 serial interface and the Ethernet interface.

2.1.3.1 Serial

2.1.3.2 Graphics

RMon uses CHAN.1 of the SCC. V-CABL-A144 can be used to connect a terminal (9600 baud, 8 bit, 1 stop bit, no parity) via X701 to the

BAB-40/60.

If a graphics module is installed, it requires a VGA monitor and ATkeyboard with PS/2 connector. A standard VGA monitor has to be connected to the 15-pin Sub-D female connector and the keyboard has to be connected to 6-pin female miniature circular (mini-DIN) connector.

Both connectors are located on the front panel. A standard VGA monitor and a standard PS/2 compatible keyboard fit without modification. For connection to an AT-keyboard, ADAP-210 is available.

2.1.4

Serial Interface

Level

Converter

(SILC)

The Serial Interface Level Converter (SILC) modules generally convert

TTL-level signals generated or accepted by the SCC to the appropriate signal levels for external transmission lines. SILC modules for RS 232,

RS 422 and RS 485 are available.

The mechanical outline of the SILC modules allows the changeability of the different SILC modules on the BAB-40/60.

•SILC-200 for RS 232

•SILC-300 for RS 422

•SILC-400 for RS 485

The mechanical part of the installation is very easy. First switch off the

VMEbus system and pull the board out of the rack. If a SILC module is already placed in the connector, remove it carefully. Now plug the new

SILC module into the corresponding connector on the CPU or I/O board.

Consider the polarization of the SILC module. To avoid damage, check that the pin 1 marked on the back of the SILC fits to pin 1 marked on the board.

28 Hardware Manual

BAB-40/60 2 Installation

2.1.5

Ethernet

Installation

2.1.6

SCSI

Installation

A standard Ethernet/Cheapernet MAU or a CONV-500 Cheapernet/

10BaseT MAU can be connected via AUI cable to the 15-pin AUI connector on the front panel of the BAB-40/60. The length of the AUI cable is limited to 50 m. For connections up to about 2 m, flat cable can also be used. In order to avoid HF radiation, this cable should be shielded.

A 8-bit SCSI bus can be connected to X103 of ADAP-200. If the

BAB-40/60 is located at either end of the SCSI bus, the termination must be enabled in the RMon setup menu, otherwise it must be disabled.

Hardware Manual 29

2 Installation

Figure 3: Installation Diagram

S902

S901

U903

X702

X701

X801

VGA

Keyboard

X1101

BAB-40/60

30 Hardware Manual

BAB-40/60 2 Installation

2.2 Default Board Setting

Table 13: Default Settings

Jumpers/Switches

J301

Position closed

Description

System controller enabled. See Section 2.3.1

J701 1 - 2 DCD from X702 connected to SILC. See

J702

J703

1 - 2

3 - 4

1 - 2

DCD from SILC connected to SCC

7.37 MHz connected to SCC receive clock.

Configuration’

DTR from SCC connected to SILC.

J1401

J1605

J1702

S901

S902 open

1 - 2 closed

(J1605)’

Write enable for serial EEPROM, seeSection 2.3.5

VMEbus slave address at $8000.0000, see

Default initialization values, see Section 2.3.6.2

Hardware Manual 31

2 Installation BAB-40/60

Figure 4: Location of Jumpers, Interface Connectors and Switches

32 Hardware Manual

BAB-40/60 2 Installation

2.3 Jumpers and Switches

This section lists all features user-selectable by jumpers and switches. For details, refer to the appropriate descriptions identified in parentheses.

All settings on a dark grey background ( ) indicate default settings.

The BAB-40/60 operates as single board computer in this configuration.

There are only very few jumpers on the BAB-40/60 which typically need no changes after shipping. All other parameters are software programmable. Since the jumper connections are not changed easily, it is strongly recommended that these changes are performed by qualified personal only.

The user should refer to the silkscreen print on the component side of the

BAB-40/60 for the following guidance on jumper area pin identification.

Pin 1 of every jumper area is marked by a beveled corner on the silkscreen outline of the jumper. If you see this corner at the left upper side of the jumper area, then pin 2 is on the right-hand side of pin 1. Pin 3 can be found on the right of pin 2, and so on.

2.3.1

System

Controller

(J301)

Table 14: J301 (System Controller)

Jumper J301 open closed

Function

System controller disabled

System controller enabled

2.3.2

Serial Interface

CHAN.2

Configuration

Table 15: J701 (CHAN.2 DCD/DSR Select)

Jumper J701

1 - 2

2 - 3

Function

DCD of X702 connected to SILC

DSR of X702 connected to SILC

Table 16: J702 (CHAN.2 DCD/Receive Clock Select)

Jumper J702

1 - 2

2 - 3

3 - 4

Function

DCD/DSR from SILC connected to DCD of SCC

DCD/DSR from SILC connected to receive clock of SCC

7.37 MHz connected to receive clock of SCC

Hardware Manual 33

2 Installation BAB-40/60

Table 17: J703 (DTR/Transmit Clock Select)

Jumper J703

1 - 2

2 - 3

Function

DTR of SCC is connected to SILC

Transmit clock of SCC is connected to SILC

5 MHz

PCLK

7.3728 MHz

SCC

TxD

DCD

SYNC

TRxC

RTxC

W/REQ

RxD

RTS

CTS

DTR

Figure 5: Serial Interface CHAN.2 Configuration

SILC

J703

3 J702

TxD

RxD

RTS

CTS

DTR

J701

DSR

DCD

GND

9-pin Sub-D

3 TxD

2 RxD

7 RTS

8 CTS

4 DTR

6 nc

1 DCD

9 nc

5 GND

BAB-40/60 with

SILC-200

34 Hardware Manual

BAB-40/60 2 Installation

2.3.3

Reset (J1401) When J1401 is closed or an external switch is connected to J1401, reset can be generated.

Table 18: J1401 (Reset)

Jumper J1401 open closed

Function

Normal operation

Reset

2.3.4

Pin 1

Connection of

EPROM

(J1605)

This jumper allows to select between EPROMs up to 4 Mbit and 8 Mbit.

Table 19: J1605 (Pin 1 Connection of EPROM)

Jumper J1605

1 - 2

2 - 3

Function

Pin 1 connected to +5 V (< 8 Mbit)

Pin 1 connected to A19 (8 Mbit)

2.3.5

EEPROM

Write Enable

(J1702)

J1702 enables/disables the hardware write protection for the serial

EEPROM. Only the upper 256 B of the EEPROM can be write protected.

Table 20: J1702 (EEPROM Write Enable)

Jumper J1702 open closed

Function

Write protection enabled

Write protection disabled

2.3.6

Switches Both hex switches (S901, S902) are used by RMon for the configuration setup (see RMon manual). They are connected to port B of the CIO.

2.3.6.1 VMEbus Slave

Address (S901)

The hex switch S901 selects the BAB-40/60 slave window address. The size of the A32 slave window is normally 256 MB. This can be changed by the RMon setup menu. The size of the A16 slave window (used for

VIC access) is 256 bytes.

Hardware Manual 35

2 Installation BAB-40/60

Table 21: Hex Switch S901 (VMEbus Slave Address)

Hex Switch

S901

VMEbus Base Address

A32

$F000.0000

$E000.0000

$D000.0000

A16

$F000

$E000

$D000

$1000.0000

Use configuration value

$1000

2.3.6.2 Hardware

Configuration

(S902)

Switch S902 defines the configuration source and the operation mode. For switch position 0, 1, RMon enters an interactive mode. If switch S902 is in position 8 to F, the user program located in the RMon EPROM is called.

Table 22: Hex Switch S902 (Hardware Configuration)

Hex Switch

S902

5 - 7

8 - F

Function

Hardware configuration from basic EPROM

Hardware configuration from SRAM

Reserved for ELTEC

RMon interactive mode on serial port

RMon interactive mode on dual-ported RAM

(local address $C000)

Reserved for ELTEC

Hardware configuration from SRAM and start program in user EPROM

S901 and S902 have no direct influence. A changed position becomes only effective after the next reset (i.e. the software reads the switches and programs the appropriate registers).

36 Hardware Manual

BAB-40/60 3 Programmers Reference

3 Programmers Reference

3.1 Address Map

The BAB-40/60 is designed to utilize the entire 4 GB address range of the

68040/060 chip. Using the address modifier of the VMEbus, the address range may be enlarged by subdivision into data and program areas and / or user and supervisor areas. The BAB-40/60 recognizes two address areas: the local address space and the global VMEbus address space.

Address Range

$0000.0000 - $01FF. FFFF

$0200.0000 - $03FF.FFFF

$0400.0000 - $05FF.FFFF

$0600.0000 - $07FF.FFFF

$0800.0000 - $FBFF.FFFF

$FC00.0000 - $FC3F.FFFF

$FC40.0000 - $FC7F.FFFF

$FC80.0000 - $FCBF.FFFF

$FCC0.0000 - $FCFF.FFFF

$FD00.0000 - $FDFF.FFFF

$FE00.0000 - $FE7F.FFFF

$FE80.0000 - $FEBF.FFFF

$FEC0.0000 - $FECF.FFFF

$FED0.0000 - $FEFF.FFFF

$FF00.0000 - $FFFE.FFFF

$FFFF.0000 - $FFFF.FFFF

1. Y = /TCI driven high, N = /TCI driven low.

2. Y = /TBI driven high, N = /TBI driven low.

3. Caching may be enabled via system control register.

Local RAM

Local RAM (mirrored)

Video RAM

Video RAM (mirrored)

VMEbus Extended

PCMCIA1

PCMCIA2

PCMCIA0

Reserved

BEB0

BEB1

EPROM

Local I/O

Reserved

VMEbus Standard I/O

VMEbus Short I/O

Table 23: Address Assignment of BAB-40/60

Device Cache

VMEbus

Address Modifier local local local local

A32 local local local local

local local

local

A24

A16

Burst

16/8

32/16/8

16/8

Access

Width [b]

32/16/8

16/8

Hardware Manual 37

3 Programmers Reference BAB-40/60

Table 24: Local I/O Address Assignment for BAB-40/60

Address

$FEC0.0000 - $FEC0.7FFF

$FEC0.8000 - $FEC0.FFFF

Device

VIC (D0..7)

VMEbus Decoder (D0..31) from the VMEbus’

Reserved $FEC1.0000 - $FEC1.FFFF

$FEC2.0000 - $FEC2.FFFF

NVRAM/RTC

System CIO $FEC3.0000 - $FEC3.FFFF

$FEC4.0000 - $FEC4.FFFF

Reserved

Watchdog $FEC5.0000 - $FEC5.3FFF

$FEC5.4000 - $FEC5.7FFF

Revision EEPROM

$FEC5.8000 - $FEC5.BFFF

Reserved

$FEC5.C000 - $FEC5.DFFF

Enable slave select (ESR) from the VMEbus’

$FEC5.E000 - $FEC5.FFFF

Snoop Control Register

$FEC6.0000 - $FEC6.3FFF

$FEC6.4000 - $FEC6.7FFF

Keyboard and Video Controller

Serial I/O

$FEC6.8000 - $FEC6.BFFF

ILACC

$FEC6.C000 - $FEC6.FFFF

SCSI Controller

$FEC7.0000 - $FEC7.FFFF

IOC-2

$FEC8.0000 - $FECF.FFFF

Reserved

Size byte

Access read/write lword write

byte byte

read/write read/write

read/write read byte write byte byte write read/write byte read/write lword read/write lword read/write lword read/write

38 Hardware Manual

BAB-40/60 3 Programmers Reference

3.2 DRAM

3.2.1

RAM Access from the Local

CPU i

The base address of the DRAM is fixed to $0000.0000.

After reset, the EPROM is mapped to address $0000.0000. After some initialization the firmware enables the DRAM at $0000.0000 via PA5 of the system CIO.

3.2.2

RAM Access from the

VMEbus

The base address for VMEbus access is specified by the slave base address register (SBR) and the enable slave select register (ESR) of the

BAB-40/60. The SBR is only accessible by the local CPUs by longword write cycles. The SBR is undefined after reset and has to be written before the BAB-40/60 can be accessed from the VMEbus. The ESR is cleared

(disabling all slave accesses) by power-on reset and the reset switch. The

ESR can only be accessed by byte write cycles.

Table 25: Slave Base Address Register Layout

Register

SBR

Address

$FEC0.80F4

31 24

A32

Decoder ext. access

23 unused

16 15

ICF

Decoder short I/O

8 7 unused

Do not use other addresses for the SBR register.

The A32 decoder compares A31 to A24 of the VMEbus with the SBR bits

32 to 24 for VMEbus extended access.

Hardware Manual 39

3 Programmers Reference BAB-40/60

3.2.3

Address

Translation

The ICF1 decoder compares A15 to A8 of the VMEbus with the SBR bits

15 to 8. The ESR register allows separate enabling of the two comparators.

Table 26: Enable Slave Register Layout

Reg.

ESR

Address

$FEC5.C000

7 ... 3 unused

ICF1 (A16)

1 = Decoder enabled

0 = Decoder disabled

1 unused

VEXT (A32)

The address presented by the VMEbus, the BEB, or the ILACC is translated from the '020 bus (A

020

) to the ‘040 bus (A

040

) with the help of the MBAR (memory base address register) and ASR (address substitution register) of the IOC-2. The address on the ‘040 bus is calculated using the following formula:

040

= (MBAR & ASR) + (A

& logical AND operation,

020

& /ASR)

+ logical OR operation, logical complement.

The translation is necessary for snooping of the CPU to keep its caches consistent with the memory.

The translated address must always be in the DRAM. If not, the computer crashes in most cases. For all address lines not driven by the source the corresponding bit position in the ASR must be 1 so that the invalid bits are substituted.

Unfortunately the address translation exists only once for the three address sources (VMEbus, BEB, ILACC). This leads to some restrictions when the DRAM is accessed by A24 addressing from the BEB. In this case only parts of the DRAM can be reached by VMEbus A32 addressing or the

ILACC.

To avoid problems, ELTEC recommends that DMA BEB boards should deliver at least A0 to A26 for operation with the default configuration.

40 Hardware Manual

BAB-40/60 3 Programmers Reference

3.2.4

RAM Mirror In some cases it may be desirable to prevent caching of data that are shared with other devices (BEB, VMEbus, ILACC). In these cases the cache inhibited RAM mirror can be used.

3.2.5

RAM Access from the BEB

Access from the BAB Extension Bus (BEB) is done by using a standard

68k-like requester with three-line handshake ( /BR , /BG , /BGACK ).

During master transfers from the BEB a minimum of 24 address lines

(A0 - A23) have to be driven. For operation with the default configuration

(64 MB slave window) at least A0 to A26 have to be driven (see

Section 3.2.3 ‘Address Translation’).

3.2.6

RAM Access from ILACC

The AM79C900 Ethernet Controller uses DMA transfer cycles to transfer commands, data and status information to and from the DRAM.

Hardware Manual 41

3 Programmers Reference BAB-40/60

3.3 VMEbus Interface

Each BAB-40/60 has a VMEbus master and a VMEbus slave interface.

Additionally, VMEbus system controller functions are available via the

VMEbus gate array (VIC) used on the BAB-40/60 board.

3.3.1

System

Controller

The BAB-40/60 features a full slot-one system controller, including

SYSCLK

SYSRESET

, bus time-out, IACK daisy chain driver, and a four level arbitration circuit. System controller capabilities are enabled by inserting jumper J301.

SYSCLK

SYSRESET

The SYSCLK is always driven if the system controller is enabled.

A low level on this signal resets the internal logic and asserts the local reset for a minimum of

200 ms. If the VIC is configured as system controller, the reset switch on the front panel (S4) asserts the

SYSRESET

for a minimum of 200 ms.

Writing a $F0 to the system reset register of the

VIC at address $FEC0.10E3 resets all registers of the VIC and asserts the

SYSRESET

output for a minimum of 200 ms.

BTO The VIC includes two independent bus time-out modules (BTO) for local cycles and for VMEbus cycles. The VMEbus time-out is only enabled when the VIC is configured as system controller. On VIC reset, the VMEbus time-out period is set to 64 µ s and the local bus time-out period to 32 µ s. This can be altered by programming the transfer time-out register of the VIC at address $FEC0.10A3. Use the

RMon setup menu to change this value.

Four Level Arbiter If the VIC is configured as system controller, the four level arbiter is enabled and programmed by writing into the arbiter / requester configuration register at address $FEC0.10B3. Use the RMon setup menu to change this value.

42 Hardware Manual

BAB-40/60 3 Programmers Reference

3.3.2

VMEbus

Master

Interface

3.3.2.1 Longword

Access to

Wordwide

Slaves

The master interface of the BAB-40/60 board supports 8, 16, and 32-bit data transfer cycles in A32, A24, and A16 addressing modes. For a short overview, see Section 1.4 ‘Definition of Board Parameters’.

Two different control lines of the system CIO enable longword breaking for the A32 and A24/A16 area:

PA3: * 0 : forces A24(A16)/D16 data size on VMEbus

1 : allows A24(A16)/D32 data size on VMEbus

PA4: * 0 : allows A32/D32 data size on VMEbus

1 : forces A32/D16 data size on VMEbus

* specifies the default values set by RMon.

Use the RMon setup menu for changes.

3.3.2.2 Address

Modifier Source

AM3..5 lines are driven depending on the actual data size, or by the address modifier source register. One CIO output signal is used to control this option:

PA2: * 0 : uses CPU and address size dependent modifiers

1 : uses VIC’s address modifier source register

* specifies the default values set by RMon.

Use the RMon setup menu for changes.

For a detailed description of the address modifier values, see Section A.2

‘Address Modifiers on VMEbus’.

3.3.2.3 Read-Modify-

Write Cycles

Read-modify-write cycles, like TAS or CAS2 are supported by the

BAB-40/60.

The CAS2 instruction has only limited support (see Table 1: ‘CAS2

Operations on the Various Busses’). The easiest way to ensure that

CAS2 instructions are indivisible is to have both operands of the

CAS2 instruction within the same memory area (local RAM,

VMEbus, BEB).

Hardware Manual 43

3 Programmers Reference BAB-40/60

3.3.2.4 A16 Slave

Interface

(ICMS)

A very useful feature of the VIC is a set of registers and switches for message passing or event signaling.

There are eight bytewide general-purpose interprocessor communication registers accessible from the VMEbus or the local bus (CPU).

•Registers 0 to 4 are general-purpose dual-port registers.

•Register 5 is a dual-port read-only ID register to identify the VIC and its revision level.

•Register 6 is a module status register which is read-only from the

VMEbus.

•Register 7 provides semaphores for registers 0-4 and several system control functions like a remote reset function.

Four ‘Interprocessor Communication Module Switches’ (ICMS) are provided by the VIC. These are bytewide mailbox switches to signal events by generating an interrupt to the local CPU if accessed from the

VMEbus. To signal dedicated events/messages the ICMS locate a unique set of addresses.

The intercommunication registers within the VIC chip are accessible in

A16 VMEbus address space only.

For programming the ICF decoder registers, see the description of the slave base address register, slave mask register and enable slave select register in Section 3.2.2 ‘RAM Access from the VMEbus’.

Use the RMon setup menu to change the register values. Within the

256-byte space the VIC chip locates several intercommunication registers.

Table 27: Intercommunication Register Location on VMEbus

Register Type

Interprocessor Communication

Registers

Interprocessor Communication

Global Switches

Interprocessor Communication

Module Switches

A07 06

X X

01 AM5..0

# $2D

$2D

$2D or

$29

# : selects register/switch number.

For further information, refer to the VIC068 data sheet.

44 Hardware Manual

BAB-40/60 3 Programmers Reference

3.4 PCMCIA Interface

3.4.1

Interface

Description

The PCMCIA was designed for extension cards on laptop computers. It offers 64 MB of attribute memory, common memory and I/O. The

PCMCIA interface converts CPU signals to PCMCIA signals via PLD.

Memory, I/O and mixed cards can be used. The address and data lines are connected via buffers to the card connector. 10 k Ω pull-ups are connected to the data lines to define a $FF on the data bus if no device on the card is selected. The access time to the card is at least 200 ns and can be extended to up to 12 µ s by using the -

WAIT

signal. The interface supports the dynamic data bus sizing. Longword transfers of the CPU are automatically converted into two word or four byte accesses on the PCMCIA card depending on the address space and the -IOCS16 signal. Pin 16 of the card interface is routed to the IRQ3 pin of the VIC. This pin can be used as interrupt request (

-IREQ

) for I/O cards or to support

+RDY

-BSY handshake in memory applications. The

+RESET

signal is generated depending on the CPU reset signal and bit 3 of the control register. Status change, battery voltage detect, card detect and other features are supported by using control registers.

3.4.2

Address Range

The standard address window for one PCMCIA socket on ELTEC’s CPU boards offers 4 MB. The PCMCIA uses the following relative address space:

Figure 6: Relative Address Space

Relative Address Access to

$40.0000

$30.0000

Socket config.

PCMCIA I/O

$20.0000

common or attribute

$00.0000

I/O

MEMORY

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3 Programmers Reference

The PCMCIA interface offers four configuration registers.

Figure 7: PCMCIA Interface Configuration Registers

Relative Address Access to

$30.0001

$34.0001

$38.0001

$3C.0000

Card Control Register (CCR)

Card Status Register (CSR)

Interrupt Vector Register (IVR)

Window Register (WIR)

BAB-40/60

3.4.3

Card Control

Register (CCR)

This register is used to select the PCMCIA command timing, V and to control the state of the RESET.

voltage,

Figure 8: Card Control Register (CCR)

$30.0001

7 6 5 4 3 2

IEN CT1 CT2 Vpp RST read and write

•IEN

Enable socket interrupt request.

•CT1 and CT2 (Command Timing)

These bits are used to define the minimum command pulse width to the socket interface. The write pulse is one clock shorter than the read pulse.

This is done to generate a longer data hold time for write cycles to the socket interface. For read cycles, the card should be driven valid data one clock before the read command becomes inactive. The complete cycle time (setup + command + recover) for read and write accesses is identical.

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-IOR

-OE

D(x) read

-IOW

-WE

D(x) write

Figure 9: Timing setup

A(x)

-REG

-CE(x)

-IO16 command recovery

Command Timing

CT1 CT2

-IOR or -OR

120 ns

280 ns

440 ns

600 ns

-IOW or -WE

80 ns

240 ns

400 ns

560 ns

The default reset value is '11'. The setup and recovery timings are depending on the base board. The absolute minimum timings are:

Read setup > 60 ns

Read recovery > 20 ns

Write setup > 60 ns

Write recovery > 60 ns

•Vpp (V pp

Enable)

This bit is used to switch the V pp

voltage of the socket interface from

+5 V to +12 V. The default reset value is +5 V ('0').

•RST (Reset)

This bit is used to control the

+RESET

of the card interface and the output enable of the Window Register (WIR). Default reset value is '1'.

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3.4.4

Card Status

Register (CSR)

This register reflects the status of the PCMCIA interface. Ready, Write

Protect, Card Detect, and Battery Status is available from this register.

Figure 10: Card Status Register (CSR)

7 6

$34.0001

RDY WP

4 3

BV2 BV1 read only

•RDY (Ready - Interrupt Request)

This bit reflects the state of the RDY-IREQ pin of the socket. In memory mode, this input indicates the ready-busy state of the card. In I/O mode, it indicates an interrupt request.

•WP (Write Protect - I/O select 16)

This bit reflects the state of the WP-IO16 pin of the socket. In memory mode, this input is the status of the write protect switch of the card. In

I/O mode, it indicates that the I/O address being accessed is capable of

16-bit operation.

•CD (Card Detect)

If this bit is set to '0', it indicates the presence of a card in the socket.

•BV2 (Battery Voltage 2)

In memory mode this bit serves as the BVD2 (battery warning status). In

DMA mode it may be used for DMA request.

•BV1 (Battery Voltage 1)

In memory mode this bit serves as the BVD1 (battery dead status). In

I/O mode, this is the STSCHG (card internal status change).

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3.4.5

Interrupt

Vector Register

(IVR)

This register is used to select the interrupt vector of the PCMCIA. After an interrupt request of a PCMCIA card, the six MSBs of this register are passed to the CPU during an interrupt acknowledge cycle. The two LSBs of the interrupt vector depend on the socket number which requested the interrupt.

Figure 11: Interrupt Vector Register (IVR)

$38.0001

IV7

IV6

IV5

IV4

IV3 write only

IV2

IV1

IV0

•IV2 to IV7 (Interrupt Vector Bit 2 to 7)

This register is used to define the interrupt vector which is transferred to the base board during interrupt acknowledge cycles.

•IV0 to IV1 (Interrupt Vector Bit 0 and 1)

The bits 0 and 1 depend on the socket number which requested the interrupt.

00 PCMCIA1

01 PCMCIA2

10 PCMCIA0

11 Reserved

Only one interrupt vector register exists for all PCMCIA sockets.

Changing the vector for one socket will also affect the other interrupt vectors.

If more than one PC Card requests an interrupt, PCMCIA0 has the highest and PCMCIA1 has the lowest priority.

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3.4.6

Window

Register (WIR)

This register selects the higher address lines, the

REG

signal of the

PCMCIA interface. The output enable of this register is controlled by the

RST bit the CCR. If RST is active ('1'), the output of the WIR is disabled.

REG

is driven to '1', A21 to A25 are '0'. If RST is '0', the WIR is enabled to drive the PCMCIA signals.

Figure 12: Window Register (WIR)

$3C.0000

REG

A25

4 3

A24 A23

2 1

A22 A21 write only

•REG (Register Access)

During memory cycles, this output chooses between attribute (0) and common (1) memory. During I/O cycles, this signal switches between

I/O (0) and DMA (1) access.

•A21 to A25 (Address Lines 21 to 25)

These bits define the socket address lines 21 to 25.

3.5 VIC Timer

The VIC contains a timer which can be programmed to output a periodic wave form on LIRQ2. The frequencies available are 50 Hz, 100 Hz, and

1000 Hz. The timer is enabled and controlled by writing slave select control register 0. The interrupt is enabled and controlled by writing local interrupt control register 2.

The clock tick timer is typically used as a time base for multi-tasking operating systems, such as OS-9 or LynxOS.

If other frequencies are needed, one of the three counters / timers that are included in the CIO may be used. For more details about the timer, refer to the VIC data sheet.

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3.6 Battery-Backed Parameter RAM and Real-Time Clock

The real-time clock is designed with the MK48T12 or MK48T18 timekeeper RAM from SGS Thomson or DS1644 from Dallas. The chip combines a 2KBx8 (8KBx8, 32KBx8) CMOS SRAM (parameter RAM) a bytewide accessible real-time clock, a crystal, and a long life lithium battery, all in one package. The MK48Txx devices have a battery lifetime of approximately 3.7 years when the clock oscillator is running. To extend battery lifetime, the clock oscillator can be stopped. Alternatively a Dallas

DS1642/1643 device can be used, which offers a lifetime of 10 years even if the oscillator is running.

3.6.1

Parameter

RAM

(NVRAM)

The address area of this SRAM is divided into two main parts:

•system dependent parameter data structure, defined by ELTEC to store setup parameters for hardware initialization and boot informations for operating systems,

•eight bytes of the SRAM for the registers of the real-time clock.

Table 28: Address Assignment of SRAM/RTC

Address

$FEC2.0000 - $FEC2.07F7

$FEC2.07F8 - $FEC2.7FF7

$FEC2.7FF8 - $FEC2.7FFF

Description

Reserved for system configuration values.

The structure of the system configuration values is defined in the RMon manual.

Free for user data if DS1644 is installed.

Clock’ for more information.

The S902 hex switch position '0' uses the configuration values stored in the basic EPROM rather than values defined in the SRAM. For more details, see also the RMon description.

If a MK48T18 is installed, J1602 must be changed from position 1-2 to 2-3. If a DS1644 is installed, J1602 must be changed from position

1-2 to 2-3. Additionally, J1606, J1607 must be closed and R1602 must be removed. The Dallas timekeeper RAMs do not offer the feature to check the battery. The SGS Thomson devices allow to check an internal battery OK flag.

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3.6.2

Real-Time

Clock i

The clock features BCD-coded year, month, day, hours, minutes, and seconds as well as a software controlled calibration. For lifetime calculations of the battery, please refer to the data sheet.

Access to the clock is as simple as conventional bytewide RAM access because the RAM and the clock are combined in the same chip.

Table 29: Address Assignment of the Real-Time Clock

MK48T12 Address

$FEC2.7FF8

$FEC2.7FF9

$FEC2.7FFA

$FEC2.7FFB

$FEC2.7FFC

$FEC2.7FFD

$FEC2.7FFE

$FEC2.7FFF

Description

RTC Control Register

Seconds

Minutes

Hour

Day

Date

Month

Year

For further details, see the MK48T12/MK48T18 resp. DS1644 data sheet.

The SRAM/RTC can only be accessed with byte instructions.

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3.7 CIO Counter / Timer

The BAB-40/60 offers three independent, programmable 16-bit counter / timers integrated in the CIO.

Table 30: Address Assignment of the System CIO

Address

$FEC3.0000

$FEC3.0001

$FEC3.0002

$FEC3.0003

Description

Port C Data Register CIO (Status Display)

Port B Data Register CIO (Hex Switches)

Port A Data Register CIO (System Control Register)

Control Register CIO

The peripheral clock of the CIO is connected to a 5 MHz source. The interrupt request outputs of CIO is connected to the LIRQ6 input of the

VIC. Local interrupt control register 6 (LIRQ6) of the VIC has to be programmed for an active low, level-sensitive input. The vector is supplied by the CIO. The VIC has to be programmed to generate interrupts on level 6 to the CPU. Only CPU IACK level 6 cycles are routed to the CIO device.

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3.8 Watchdog Timer

The watchdog timer installed on the BAB-40/60 monitors the activity of the microprocessor. If the microprocessor does not write location

$FEC5.0000 within a certain time-out period, a reset pulse is generated.

After reset, the watchdog timer is disabled.

The watchdog becomes active after writing the desired time-out period to the watchdog configuration register at $FEC5.2000. Also the watchdog has a lock feature. When locked, the watchdog configuration register cannot be changed anymore to prevent unintentionally altering the watchdog period. Only reset is able to unlock the watchdog.

After reset the software can read port A bit 7 of the system CIO to distinguish between a watchdog reset (PA7 = ‘0’) and a reset generated by other sources (PA7 = ‘1’). This watchdog indicator is cleared by power-up reset, the reset switch, a VMEbus SYSRESET , a VIC remote reset, or by a write access to address $FEC5.0000.

Table 31: Address Assignment of Watchdog Registers

Address Description

$FEC3.0002

$FEC5.0000

$FEC5.2000

Port A Data Register System CIO

Watchdog Trigger

Watchdog Configuration

Access

Direction read PA7 write write

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Table 32: Watchdog Configuration Register at $FEC5.2000

$0B

$0C

$0D

$0E

$07

$08

$09

$0A

$0F

$10 - S1F

$03

$04

$05

$06

Value

$00

$01

$02

Function

Disable Watchdog

Enable Watchdog 130 ms

Enable Watchdog 260 ms

Enable Watchdog 520 ms

Enable Watchdog 1.04 s

Enable Watchdog 2.08 s

Enable Watchdog 4.16 s

Enable Watchdog 8.32 s

Enable Watchdog 16.64 s

Enable Watchdog 33.28 s

Enable Watchdog 1 min 6 s

Enable Watchdog 2 min 13 s

Enable Watchdog 4 min 26 s

Enable Watchdog 8 min 52 s

Enable Watchdog 17 min 44 s

Reserved (Watchdog disabled)

Same as $00 - $0F but watchdog becomes locked

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3.9 Revision Information

Revision information is stored on the board to give software the chance to distinguish between different versions and derivates of the BAB-40/60.

The information consists of two parts. First there are bits 3-7 of the

IOC-2’s control register at $FEC7.00A8.

Table 33: IOC-2 Control Register at $FEC7.00A8

Register

ICR

Address

$FEC7.00A8

31 - 8 used for IOC-2 internal purposes

7 - 5

0 0 0 ELTEC initial version

0 0 1

1 0 0 other

EUROCOM-17-1xx/2xx

BAB-40/60-xxx reserved

4 3

0 0 25 MHz

0 1 33 MHz

1 0 40 MHz

1 1 reserved

2 - 0 used for IOC-2 internal

purposes

If bits 5-7 of the ICR are %100, extended revision information is available at the serial EEPROM.

The serial EEPROM is a 512 B FRAM which is used to store ELTEC specific board revision information. For the user, the upper 256 B of the

FRAM are reserved to store additional information.

The lower 256 B of the FRAM contain the extended board revision information. These factory settings must never be modified by the user to guarantee system consistency.

Because the FRAM can only be handled via an I

C bus protocol, data should only be modified using the implemented RMon utilities. For this, see RMon Documentation.

The FRAM is controlled in detail by the signals SDIO and SCLK . These signals can be set via a register at address $FEC5.4000.

Table 34: I 2

C Control Register Layout

Register

Control

Address

$FEC5.4000

7 - 2 1 unused SCLK

SDIO

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Table 35: Address Map of the Serial EEPROM

Usage

$068

$070

$07E

$080

$030

$040

$050

$060

$0C0

$100

Offset

Address

$000

$008

$00A

$00C

$010

$020

256

Size

(Byte)

Initialization

Revision code of structure

Size of CRC calculation

CRC

Board revision information

Option revision information

Serial number

Reserved

Revision codes

Category codes

Text

Reserved

User data

The user data can be stored at address offset $100 - $1FF. To store the user data, see RMon documentation for more information.

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3.10 Cache Coherency and Snooping

To maintain cache coherency in a multi master system, the ‘040/060 has the capability of snooping. Snooping can be enabled via snoop control register at $FEC5.E000 (write only).

Bit 7-5 of the Snoop Control Register are used to select the size of the onboard SIMM module (see Table 39: ‘RAM Size’).

Table 36: Snoop Control Register Layout for BAB-40/60

Register

SNCR

Address

$FEC5.E000

7 - 5

RAM Size

4 - 3 unused

2 unused

SC1

SC0

Table 37: Snoop Control Encoding for BAB-40

Requested Snoop Operation

SC1 SC0 Alternate Bus Master Read Access Alternate Bus Master Write

Access

Inhibit Snooping

Supply Dirty Data and Leave Dirty

Inhibit Snooping

Sink Byte/Word/Longword

Supply Dirty Data and Mark Line Invalid Invalidate Line

Reserved (Snoop Inhibited) Reserved (Snoop Inhibited)

Table 38: Snoop Control Encoding for BAB-60

SC1 SC0

Function

Enable snooping

Inhibit snooping

Table 39: RAM Size

RAM Size 7 - 5

%000

%001

%010

%011

%100

%101

Size

1 MB

2 MB

4 MB

8 MB

16 MB

32 MB

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3.11 Serial I/O

The BAB-40/60 offers two serial I/O lines, implemented by one Z8530

Serial Communication Controllers (SCC). CHAN.1 (SCC channel A and

B at address $FEC6.4000) is hardwired to feature RS 232 two-wire hardware handshake mode, while CHAN.2 uses removable single inline level converters called SILC. As shipped, a RS 232 level converter SILC is installed, which features hardware handshake as well as XON/XOFF protocol.

3.11.1 Serial

Communication

Controller

(SCC)

The operating mode and data format of each channel can be programmed independently. The baud rate generator is driven by the PCLK input at

5 MHz. The time constant values in the following table are based on the clock frequency of 5 MHz.

Table 40: Time Constant Values for SCC

Baud Rate

38400.0

19200.0

9600.0

7200.0

4800.0

3600.0

2400.0

2000.0

1800.0

1200.0

600.0

300.0

150.0

134.5

110.0

75.0

50.0

Time Constant

128

258

519

1040

1160

1418

2081

3123

Error

3.4510 %

2.3003 %

1.9719 %

1.4931 %

1.4449 %

0.9824 %

0.1653 %

0.1645 %

0.2288 %

0.1628 %

0.1615 %

0.0321 %

0.0250 %

0.0321 %

0.0160 %

0.0000 %

Alternatively a 7.3728 MHz oscillator can be used for baudrate generation of channel B (CHAN.2).

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The interrupt request outputs of the SCC is connected to the LIRQ4 input of the VIC.

The Local Interrupt Control Register 4 (LIRQ4) of the VIC has to be programmed for an active low, level sensitive input. The vectors are supplied by the SCC. The VIC has to be programmed to generate interrupts on level 5 to the CPU. Only CPU IACK level 5 cycles are routed to the SCC device.

Table 41: Address Assignment of the SCC

Address

$FEC6.4000

$FEC6.4001

$FEC6.4002

$FEC6.4003

Description

Channel B Control Register SCC

Channel B Date Register SCC

Channel A Control Register SCC

Channel A Data Register SCC

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3.11.2 Serial Interface

Level

Converter

(SILC)

The Serial Interface Level Converter (SILC) modules generally convert

TTL level signals generated or accepted by the SCC to the appropriate signal levels for external transmission lines. SILC modules for the specifications RS 232C, RS 422 and RS 485 are available.

The mechanical outline of the SILC modules allows the changeability of the different SILC modules in the 16-pin pinouts on the BAB-40/60.

SILC-200 for RS 232

EIA standard RS 232 was introduced in 1962 and has been widely used throughout in industry. RS 232 was developed for single ended data transmission at relatively slow data rates (20 Kbit/s) over short distances

(<15m).

SILC-300 for RS 422 (V11)

RS 422 was defined for differential data transmissions at high data rates over long distances and through noisy environment. RS 422 allows data rates up to 10 Mbit/s (12 m) and line lengths up to 1200 m (100 Kbit/s).

The SILC-300 driver is designed to drive a party line with ten receivers.

RS 422 devices cannot be used to construct a truly multipoint bus with multiple driver and receiver. It is V11 compatible. Cable termination is necessary for longer distances.

SILC-400 for RS 485

RS 485 was defined for truly multipoint communication. RS 485 meets all the requirements of RS 422, but in addition, this new standard allows up to

32 drivers and 32 receivers to be connected to a single bus - thus allowing a truly multipoint bus to be constructed. Cable termination is necessary for longer distances.

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3.11.2.1 SILC

Installation

The mechanical part of the installation is very easy. First switch off the

VMEbus system and pull the board on which the SILC module shall be installed or changed out of the rack. If a SILC module is already placed in the connector, remove it carefully. Now plug the new SILC module into the corresponding connector on the CPU or I/O board. Consider the polarization of the SILC module. To avoid damage check that the pin 1 marked on the back of the SILC fits to pin 1 which is marked on the board.

The following table provides information about the functionality of the pins on the SILC modules.

Table 42: Pin Assignment for SILCs

Pin

SILC-200

Signal Description

GND1

/RxD

/TxD

GND2 not connected

/RTS

/CTS not connected

CTS

RxD

GND not connected not connected

TxD

RTS

T(A)

T(B)

I(B)

C(A)

SILC-300

Signal Description

R(B)

R(A)

I(A)

C(B)

CTS

RxD

GND pulled low not connected

TxD

RTS

SILC-400

Signal Description not connected not connected

A not connected not connected not connected

B not connected pulled low

RxD

GND pulled low not connected

TxD pulled low

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3.12 Ethernet Interface (802.3/10base5)

The ILACC’s internal registers are selected by writing the corresponding register number to address $FEC6.8006 and accessed at address

$FEC6.8002. Both addresses must be accessed with word-size instructions.

After initialization and starting, the ILACC operates without any CPU interaction. It transfers prepared data, receives incoming packets and stores them into reserved memory locations. To signal service requests, the ILACC interrupt signal is connected to the VIC’s LIRQ7 input. The

VIC has to be programmed to level-sensitive and has to supply the vector, because the ILACC has no provision built to do so.

Table 43: Ethernet Controller Address Layout

Address

$FEC6.8002

$FEC6.8006

Description

A detailed description of the AM79C900 can be found in the data sheet.

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3.13 SCSI Interface

A Small Computer System Interface (SCSI) controller is built around a

NCR53C710 chip. The full specification (ANSI K3T 9.2) is implemented, supporting all standard SCSI features including arbitration, disconnect, reconnect, and parity.

3.13.1 SCSI Controller The interrupt request line (IRQ) of the SCSI controller is connected to the

LIRQ1 input of the VIC. The NCR53C710 cannot supply its own vector, so the VIC has to be programmed to supply a vector for the SCSI controller. The VIC LICR1 has to be programmed to level-sensitive and has to supply the IRQ vector.

The BAB-40/60 uses Big Endian Bus Mode 2 of the NCR53C710.

According to the SCSI specification, the interconnecting flat cable must be terminated at both ends. On the BAB-40/60 this is done by an active termination chip which can be enabled via PA6 of the system CIO (‘0’ enable, ‘1’ disable). If the BAB-40/60 board is not located at either end of the SCSI bus, the termination must be disabled via setup menu of the

RMon.

A detailed description of the NCR53C710 controller chip can be found in the data sheet.

The first access to the NCR53C710 must set the EA bit in the DCNTL register of the NCR53C710. Accessing the NCR53C710 without the

EA bit set will lock the CPU bus.

The NCR53C710 shares the LICR1 input of the VIC with the keyboard controller.

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3.14 IOC-2

3.14.1 Register Set

ELTEC’s Input/Output Controller (IOC-2) is an ASIC intended to maximize the performance of ELTEC’s CPU boards. The IOC-2 is specially designed as data/address bridge between a 68040-type local bus and VIC068 to support fast VMEbus master/slave block transfers. A second main function is a universal programmable I/O bus interface with an appropriate address decoder.

All 25 IOC-2 registers are read/write accessible using longword transfer cycles only. The internal address decoder reserves an IOC-2 address space of 64 KB. The following register map shows all internal registers and their corresponding register offset address. The complete CPU register address is calculated by:

IOALR value

+ Register OFFSET address

Table 44: Register Map

$70018

$7001C

$70020

$70024

$70028

$7002C

Offset Addr.

Symbol

I/O Bus Interface Registers:

$70000

$70004

IOALR

IODCR0

$70008

$7000C

$70010

$70014

IODCR1

IODCR2

IODCR3

IODCR4

IODCR5

IODCR6

IODCR7

IODCR8

IODCR9

IODCR10

Name

I/O Address Location Register

I/O Device Control Register 0

I/O Device Control Register 1

I/O Device Control Register 2

I/O Device Control Register 3

I/O Device Control Register 4

I/O Device Control Register 5

I/O Device Control Register 6

I/O Device Control Register 7

I/O Device Control Register 8

I/O Device Control Register 9

I/O Device Control Register 10

Reset Value

$FEC0.0000

$0000.0000

1. Default register value: $FEC0.0000

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Table 44: Register Map (Continued)

Offset Addr.

$70030

$70034

$70038

$7003C

$70040

$70044

$70048

Symbol

IODCR11

IODCR12

IOIACR

EBAR0

EMAR0

EDCR0

Name

I/O Device Control Register 11

I/O Device Control Register 12

I/O IACK Control Register reserved

EPROM Begin Address Register 0

EPROM Mask Register 0

EPROM Device Control Register 0

$7004C

$70050

$70054

$70058

- -

EBAR01

EMAR01

EDCR1 reserved

EPROM Begin Address Register 1

EPROM Mask Register 1

EPROM Device Control Register 1

$7005C -

$7009C

- - reserved

Address Bus Interface Registers:

$700A0 MBAR Memory Base Address Register

Address Substitution Register $700A4 ASR

General Control Registers:

$700A8

$700AC

ICR

ITR

IOC-2 Control Register

IOC-2 Test Register

1. xx => IOD(7:0) during reset

Reset Value

$0000.0000

$0000.020F

$0000.0A0F

$0000.0000

$0000.020F

$0000.0A0F

$0000.0000

$FF80.0000

$0000.22xx

$0000.0000

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3.15 Status Display

The BAB-40/60 features a four LED display on the front panel.

This status display is designed as read/write register and uses the least significant nibble of the byte.

As an example, the following sequence illuminates the leftmost two

LEDs: move.b #$0C,$FEC30000 i

The upper four bits of the display are write-enable bits for the lower four bits. Only those bits of the lower nibble are changed where the corresponding bit in the upper nibble is clear.

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3.16 Reset

BAB-40/60

During power-up or after actuation of the reset switch (J1401),

/RESET

is held low for approximately 1 s. If the system controller is enabled, the

VMEbus is also reset because the VIC is configured as the VMEbus system controller. Otherwise

SYSRESET

from the VMEbus is an input.

The reset switch or power-up reset affects all modules and chips on the

BAB-40/60 board, and also the VMEbus SYSRESET line if jumper J301 is inserted.

A remote reset via VIC’s reset register or a VMEbus

SYSRESET

behaves the same way as a power-up reset, except that the VMEbus configuration

(VIC register and master / slave address) is not changed.

Table 45: Reset Conditions

Reset Source

Voltage Drop < 4.75 V or Power-up or Reset Switch J1401

VIC Remote Control Reset or SYSRESET

Watchdog Reset

CPU

Affected Device

CPU, SCC, CIO, Keyboard and Video Controller,

SCSI Controller,

ILACC,

VMEbus SYSRESET (if system controller),

Watchdog Indicator,

VMEbus Slave Decoder

BEB

CPU, SCC, CIO, Keyboard and Video Controller

SCSI Controller,

ILACC,

Watchdog Indicator

BEB

CPU, SCC, CIO, Keyboard and Video Controller,

SCSI Controller,

ILACC

BEB

SCSI Controller,

ILACC

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3.17 Bus Time-Out

The BAB-40/60 features two independent, software-programmable bus time-out modules; one for the local time-out and one for the VMEbus time-out.

Both time-out modules are located in the VIC and are programmed by writing the transfer time-out register ($FEC0.10A3). The time-out period is programmable from 4 µ s to 480 µ s. Local time-out is not generated when waiting for VMEbus mastership. This is programmable within the

VIC chip.

Local time-out is set to 32 µ s and the VMEbus time-out is set to 16 µ s by

RMon. Use the RMon setup menu to change these values.

The VMEbus time-out is generated by the system controller and, therefore, is only used if the VIC is being used as the system controller.

Jumper J301 is used to enable/disable the board’s system controller.

Access to the BEB/BGB triggers the local BTO generator.

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3.18 System Control Register (SCR)

The BAB-40/60 features several status and control bits to monitor and change the system control signals. These are implemented using port lines of the system CIO. Reset initializes all ports as input. The default values are set during the RMon initialization routine.

Table 46: System Control Register Layout (System CIO)

Bit No.

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Type

Input

Output

PB7..0

PC3..0

Input

Output

Name

WDS

SCSITRM

RESCYC

DSCTRL0

DSCTRL1

ASCTRL

CACTRL

INIT

HEXSW

DISPLAY

Description

Watchdog Status

0 = Watchdog Reset

1 = Normal Reset

SCSI Termination

0 = enable termination

1 = disable termination

Reset Cycle

0 = Address Decoder normal operation (default)

1 = Address Decoder reset operation (reset condition)

VMEbus A32 Data Size Control

0 = normal longword operation for A32 (default)

1 = breaks longword cycles into two word cycles

VMEbus A24 Data Size Control

0 = normal longword operation for A24

1 = breaks longword cycles into two word cycles

(default)

VMEbus Address Modifier Source Control

0 = normal operation FC0..2 -> AM3..5

1 = VMEbus Address Modifier from VICs Address Modifier Source Register

VMEbus Cache Control

0 = disables caching of VMEbus data (default)

1 = enables caching of VMEbus data

Initialization Indicator D1401

0 = green

1 = red

Read Hex Switch

Write LEDs on Front Panel i

All outputs of the CIO are pulled high to ensure a valid logic level after reset.

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3.19 Interrupt Sources

All seven priority levels of the VMEbus are implemented. The local modules are served by interrupts without restricting the VMEbus interrupt capacity.

The interrupt handler is a part of the VIC gate array. This device contains seven registers to handle seven VMEbus interrupt sources. Each IRQ line on the VMEbus is enabled and disabled separately. Additionally, the level passed to the CPU is changed for each of these lines through the control registers of the VIC.

The VIC also supports seven local interrupt request inputs, called LIRQ1 to LIRQ7. These lines are connected to several local devices generating an

IRQ (referenced by Table 47: ‘VIC Interrupt Priority Scheme’).

Additionally, the VIC can generate local interrupts from eight interprocessor communication registers, ACFAIL , SYSFAIL , arbitration time-out, posted write cycles, and DMA completion.

To change the IRQ values in the VIC registers, use the RMon setup menu.

Refer to the VIC068 data sheet for more information.

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Table 47: VIC Interrupt Priority Scheme

IRQ

LIRQ7

Error Group IRQ

LIRQ6

LIRQ5

LIRQ4

LIRQ3

LIRQ2

LIRQ1

ICGS Group IRQ

ICMS Group IRQ

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

DMA Status IRQ

VMEbus Interrupt

Acknowledged

Source

ILACC

ACFAIL from VMEbus

Write Post Fail

Arbitration Time-out

SYSFAIL from VMEbus

System CIO

BEB

Serial I/O

PCMCIA Controller

Clock Tick Timer of VIC

SCSI Controller

Keyboard Controller

Interprocessor Communication

Global Switches of VIC

Interprocessor Communication

Module Switches of VIC

VMEbus

VIC DMA Controller

VIC Interrupter

Generated

CPU Level

2 1)

Vector supplied by

VIC

System CIO

BEB

SCC

PCMCIA

VIC

VMEbus

VIC

1. The IRQ levels inside the VIC have to be programmed with the level mentioned in initialization, they may be changed by the user.

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3.19.1 Local Interrupt

Sources

The BAB-40/60 has eight local interrupt sources connected to six VIC inputs (LIRQ1, LIRQ3 to LIRQ7).

Table 48: Local Interrupt Sources

Device

ILACC

System CIO

BEB

Serial I/O

PCMCIA

VIC Timer

SCSI Controller

Keyboard Controller

VIC ACFAIL

VIC Failed Write Post

VIC Arbitration Time-out

VIC SYSFAIL

VIC Interrupter IACK

VIC DMA

VIC ICMS0..ICMS3

VIC ICGS0..ICGS3

VIC Input

LIRQ7

LIRQ6

LIRQ5

LIRQ4

LIRQ3

LIRQ2

LIRQ1

Level

6 1)

Vector

$47

$xx

$42

$41

$48

$49

$4A

$4B

$4C

$4D

$1C - $1F

$10 - $13

1. These levels are not changeable (i.e. fixed in hardware), all other levels are programmable via VIC register. Also all vectors delivered by the VIC are programmable.

VIC

Supplied by

VIC

CIO

BEB board

SCC

PCMCIA

VIC

3.19.2 VMEbus

Interrupt

Sources

Individual interrupt levels are masked dynamically under software control by programming the appropriate VMEbus interrupt control register (ICR1 to ICR7) of the VIC. This feature allows easy implementation of multiprocessor systems. The VMEbus interrupt requests are always active low and level-sensitive.

All VMEbus IRQs are disabled after the initialization of RMon. To change this, use the RMon setup menu. For further details, see the data sheet VIC068.

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3.20 Indivisible Cycle Operation

3.20.1 Deadlock

Resolution

When a CPU performs a locked cycle to the '020 bus (e.g. TAS to the

VMEbus) and someone wants to access the '040 bus from the '020 bus

(e.g. slave access from VMEbus to the local RAM) there is a deadlock situation. On normal reads or writes such a deadlock is resolved by sending a retry acknowledge to the CPU. On locked cycles this does not work because the arbiter does not grant the bus from the current bus master as long as

/LOCK

is active. Such deadlocks are resolved by sending a error acknowledge to the CPU. Then there must be a bus error trap handler that inspects the stack frame whether there was a locked cycle or not. If not, normal bus-error handling is continued. Else the locked cycle is retried by simply performing a RTE instruction. The trap handler also should inspect the VIC's bus error status register whether there was a bus error. If so also normal bus error handling should be done to prevent that the trap handler retries the locked cycle infinitely.

3.20.2 TAS Violation on ‘040

If a semaphore resides in a region that can be cached in the '040 in copyback mode TAS violation can occur via the following sequence:

•the semaphore resides in a dirty cache line in the cache of the '040, and the semaphore is set,

•an alternate master performs the read of a TAS,

•the '040 snoops the read and supplies that the semaphore is set,

•the '040 clears the semaphore (in the cache),

•the alternate master performs the write of the TAS,

•the '040 snoops the write so that the semaphore is set again.

As a result of this the clearing of the semaphore is lost! This can be avoided by using the CAS instruction to clear the semaphore.

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3.21 Default Parameters for RMon

Table 49: Default Parameters of RMon 2.8 located on BAB-40/60

Beginning End

Group A: I/O Initialization

$0800

$0880

$0890

$08B0

$08D0

$0910

$0930

$0950

$087F

$088F

$08AF

$08CF

$090F

$092F

Description

VIC parameter

- reserved -

SCC port A parameters

SCC port B parameters

- reserved -

CIO parameters

- reserved -

SCSI chip parameter

$0952 $0AEF

Group B: Address Information

- reserved -

$0AF0

$0AF2

$094F

$0951

$0AF1 ICF1 address

- reserved -

$0AF3

$0AF4

$0AF6

$0AF7

$0AF5

- reserved -

VME A32 slave address

- reserved -

VME A32 slave size

VME enable bits

- reserved -

$0AF8

$0AF9 $0B47

Group C: Hooks

$0B48 $0B4F

$0B50

$0B64

$0B68

$0B6C

$0B63

$0B67

$0B6B

$0B6F

User hooks

- reserved -

Company name

Board name

Portation

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Table 49: Default Parameters of RMon 2.8 located on BAB-40/60

$0C58

$0C59

$0C5A

$0C5C

$0C5D

$0C5E

$0C62

$0C68

Beginning End

Group D: Boot Parameters

$0B70

$0B71

$0B72

$0B73

$0B74

$0B75

$0B76

$0B78

$0B7C

$0B7D

$0B7E

$0B80

$0B84

$0B88

$0BC8

$0BD8

$0C18

$0C1C

$0C1E

$0C20

$0B83

$0B87

$0BC7

$0BD7

$0C17

$0C1B

$0C1D

$0C1F

$0C4F

$0C50 $0C57

Group E: Board Information

Description

Autoboot flags

Operating system

SCSI controller ID

SCSI controller Hardware

SCSI logical unit number

Special boot flag

Sector size (unused)

Base address for RAM/ROM boot

Own SCSI ID

Retry counter for NetBoot

Delay until autoboot starts

Logical Sector Offset

- reserved -

Drive command

Own internet address

Internet bootfile name (incl. host internet address)

Slave board address

BootP flag

Network boot time-out value

Server name

- reserved -

$0C88

$0C8E

$0C90

$0C96

$0C98

$0C5B

$0C61

$C067

$0C87

$0C8D

$0C93

$0C97

$0CAO

- reserved -

Character I/O port number

- reserved -

Watchdog enable flag

- reserved -

Watchdog time-out period

- reserved -

Internal board information

Ethernet Node ID

Board ID

RMon base address

Local memory size in MB

- reserved -

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Table 49: Default Parameters of RMon 2.8 located on BAB-40/60

$0CB4

$0CC0

$0D00

$0DA0

$0DA1

$0DA2

$0DFC

Beginning End

Group F: Video Descriptor

$0CA0

$0CA1

$0CA2

$0CA6

$0CAA

$0CAF

$0CB1

$0CB3

$0CA9

$0CAD

$0CB0

$0CB2

$0CB7

$0CFF

$0DBF

$00FB

$0DFF

Description

Graphic Mode

Graphic Bit Mode

Display Start Address

Size of Graphic Plane

Size of Display Window

Fore- and Background color

Number of Columns and Lines

Video Descriptor Format

Position of Character Window

Video Timing Parameter

- reserved -

Keyboard typamatic rate/delay

Keyboard language

- reserved -

Checksum

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Type declarations for the following definitions:

1 struct io_data

2 {

3 unsigned char value;

4 unsigned char registerno;

5 };

3.21.1 Group A: I/O

Initialization

($0000.0800 -

$0000.0AEF)

3.21.1.1 VIC

Parameter

❏ Definition: struct io_data vic[0x40];

❏ Description:

Initialization values for VIC registers.

First member is value, second member is VIC register number.

❏ RAM Address: $0000.0800 - $0000.087F

❏ Default Data:

{0x00, 0xab}, {0xf0, 0xaf}, {0x60, 0xb3}, {0x40, 0x57},

{0x10, 0xa7}, {0x46, 0xa3}, {0x00, 0xb7}, {0x12, 0xc3},

{0x82, 0xc7}, {0x16, 0xcb}, {0x82, 0xcf}, {0x00, 0xd3},

{0x00, 0xd7}, {0x00, 0xdb}, {0x00, 0xdf}, {0x80, 0x7f},

{0x81, 0x07}, {0x82, 0x0b}, {0x83, 0x0f}, {0x84, 0x13},

{0x85, 0x17}, {0x86, 0x1b}, {0x87, 0x1f}, {0x1c, 0x53},

{0x77, 0x47}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}

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3.21.1.2 SCC Port A

Parameter

❏ Definition: struct io_data scc1a[0x10];

❏ Description:

Initialization values for SCC, port A.

First member is value, second member is SCC register number.

❏ RAM Address: $0000.0890 - $0000.08AF

❏ Default Data:

{0x80, 0x09}, {0x46, 0x04}, {0xc1, 0x03}, {0xea, 0x05},

{0x56, 0x0b}, {0x0e, 0x0c}, {0x00, 0x0d}, {0x03, 0x0e},

{0x00, 0x0f}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}

3.21.1.3 SCC Port B

Parameter

❏ Definition: struct io_data scc1b[0x10];

❏ Description:

Initialization values for SCC, port B.

First member is value, second member is SCC register number.

❏ RAM Address: $0000.08B0 - $0000.08CF

❏ Default Data:

{0x40, 0x09}, {0x46, 0x04}, {0xc1, 0x03}, {0xea, 0x05},

{0x56, 0x0b}, {0x0e, 0x0c}, {0x00, 0x0d}, {0x03, 0x0e},

{0x00, 0x0f}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}

3.21.1.4 CIO

Parameter

❏ Definition: struct io_data cio1[0x10];

❏ Description:

Initialization values for CIO.

First member is value, second member is CIO register number.

❏ RAM Address: $0000.0910 - $0000.092F

❏ Default Data:

{0x88, 0x40}, {0xff, 0x41}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff},

{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}

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3.21.2 Group B:

Address

Information

($0000.0AF0 -

$0000.0B47)

3.21.2.1 ICF1 Address ❏ Definition: unsigned short icf1_addr;

❏ Description:

Slave address of ICMS in VMEbus short I/O range. Only bits 15-6 are used for A15-A6 of slave address. By default, RMon enables this slave access.

❏ RAM Address: $0000.0AF0 - $0000.0AF1

❏ Default Data:

$8000 i

This value may be overwritten, depending on the setting of hex switch

S901.

3.21.2.2 VMEbus A32

Slave Address

❏ Definition: unsigned short ext_addr;

❏ Description:

Slave address of VMEbus extended I/O range. Only bits 15-4 are used for A31-A20 of slave address. By default, RMon enables this slave access.

❏ RAM Address: $0000.0AF4

❏ Default Data:

$8000 i

This value may be overwritten, depending on the setting of hex switch

S901.

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3.21.2.3 VMEbus A32

Slave Size

❏ Definition: unsigned char ext_size;

❏ Description:

Size of VMEbus slave extended address range in 16 MB.

❏ RAM Address: $0000.0AF7

❏ Default Data:

$04

(64 MB A32 slave window size)

3.21.2.4 VMEbus

Enable Bits

❏ Definition: unsigned char vme_enable;

❏ Description:

VMEbus slave access enable flags bit 2: ICF1, bit 0: extended

All other bits are reserved.

❏ RAM Address: $0000.0AF8

❏ Default Data:

$05

(enables ICF1 and extended)

3.21.3 Group C: Hooks

($0000.0B48 -

$0000.0B6F)

❏ Definition: unsigned long user_hook[6];

❏ Description:

Pointer list to user hooks.

hook[0]: init, hook[1]: entry, hook[2]: reserved, hook[3]: reserved, hook[4]: reserved, hook[5]: reserved, hook[6]: reserved, hook[7]: company name, hook[8]: board name hook[9]: portation.

❏ RAM Address: $0000.0B48 - $0000.0B6F

❏ Default Data:

$FFFF.FFFF, $FFFF.FFFF, $FFFF.FFFF, $FFFF.FFFF,

$FFFF.FFFF, $FFFF.FFFF

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3.21.4 Group D: Boot

Parameters

($0000.0B70 -

$0000.0C57)

3.21.4.1 Autoboot Flag ❏ Definition: unsigned char autoboot;

❏ Description:

Autoboot flags.

Bit 7: Not autoboot,

Bit 1: debug output,

Bit 0: OS-9 debug enable

This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B70

❏ Default Data:

$82

3.21.4.2 Operating

System

❏ Definition: unsigned char os;

❏ Description:

Operating system.

$FF: OS-9,

$FE: LynxOS (bootloader not implemented)

This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B71

❏ Default Data:

$FF

3.21.4.3 SCSI

Controller ID

❏ Definition: unsigned char conid;

❏ Description:

Controller ID. This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B72

❏ Default Data:

$06

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3.21.4.4 SCSI

Controller

Hardware

❏ Definition: unsigned char conhard;

❏ Description:

Controller hardware.

$00: Omti,

$01: SCSI Harddisk,

$02: SCFL,

$03: TEAC SCSI Floppy

This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B73

❏ Default Data:

$01

3.21.4.5 SCSI Logical

Unit Number

❏ Definition: unsigned char lun;

❏ Description:

Logical unit number. Valid values: $00, $20, $40, $60.

This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B74

❏ Default Data:

$00

3.21.4.6 Special Boot

Flag

❏ Definition: unsigned char specboot;

❏ Description:

Special bootstraps

$FF: None,

$FD: Streamer tape,

$FE: Ramdisk,

$FC: Ethernet,

$FB: ROM boot (wait for NMI),

$FA: Direct ROM boot,

$F0: PCMCIA interface

This value is configurable by means of the setup utility.

❏ RAM Address: $0000.0B75

❏ Default Data:

$FF

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3.21.4.7 Sector Size ❏ Definition: unsigned short secsize;

❏ Description:

OS-9 sector size. RMon does not use this value.

❏ RAM Address: $0000.0B76

❏ Default Data:

$FFFF

3.21.4.8 Base Address of RAM/ROM/

PCMCIA Boot

❏ Definition: unsigned long romkerneladdr;

❏ Description:

Base address of ROM kernel, RAM disk or PCMCIA interface.

This value is used for special bootstraps '$FB', '$FA' and '$F0'.

It is configurable by means of the setup utility.

❏ RAM Address: $0000.0B78

❏ Default Data:

$0000.0000

3.21.4.9 Retry Counter for Network

Boot

❏ Definition: unsigned char;

❏ Description:

Retry counter for network boot.

This value is used as counter to call the network bootstrap port until the

RMon is called again.

❏ RAM Address: $0000.0B7D

❏ Default Data:

$00

3.21.4.10 Delay until

Auto Starts

❏ Definition: unsigned short autob;

❏ Description:

This value specifies the delay (seconds) before the autoboot sequence starts.

❏ RAM Address: $0000.0B7E

❏ Default Data:

$0009

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3.21.4.11 Logical

Sector Offset

❏ Definition:

❏ Description: unsigned long lsnoffset;

Logical Sector Offset

❏ RAM Address: $0000.0B80

❏ Default Data:

$0000.0000

3.21.4.12 Device

Command

❏ Definition: unsigned char drive_cmd[0x40];

❏ Description:

Drive commands. The command list for configurated drive will be copied here by the setup utility.

❏ RAM Address: $0000.0B88 - $0000.0BC7

❏ Default Data:

$00, $00, $00, $00, $00, $00, $00, $00,

$00, $00, $00, $00, $00, $00, $00, $00

3.21.4.13 Own Internet

Address

❏ Definition: unsigned char internethost[0x10];

❏ Description:

Internet host address.

Notation: xxx.xxx.xxx.xxx

'xxx': address component (all values ASCII)

This string must always be zero filled for a correct termination. It is configurable by means of the setup utility.

❏ RAM Address: $0000.0BC8 - $0000.0BD7

❏ Default Data:

$30, $2E, $30, $2E, $30, $2E, $30, $00,

$00, $00, $00, $00, $00, $00, $00, $00

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3.21.4.14 Internet

Boot File

Name

❏ Definition: unsigned char internetboot[0x40];

❏ Description:

Boot file address/name.

Notation: xxx.xxx.xxx.xxx:filename

'xxx': address component (all values ASCII)

This string must always be zero filled for a correct termination. It is configurable by means of the setup utility.

❏ RAM Address: $0000.0BD8 - $0000.0C17

❏ Default Data:

$30, $2E, $30, $2E, $30, $2E, $30, $3A,

$00, $00, $00, $00, $00, $00, $00, $00,

$00, $00, $00, $00, $00, $00, $00, $00

3.21.4.15 BootP Flag ❏ Definition: unsigned short bootp;

❏ Description:

This value specifies the network boot port number.

0x0000: TFTP

0x0001: BOOTP

❏ RAM Address: $0000.0C1C

❏ Default Data:

$0000

3.21.4.16 Network

Boot Timeout

❏ Definition: unsigned short nettout;

❏ Description:

Time-out value for network boot.

❏ RAM Address: $0000.0C1E

❏ Default Data:

$0010

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3.21.4.17 Server Name ❏ Definition: unsigned char sname [0x30];

❏ Description:

Server name. This string must always be zero filled for a correct termination.

❏ RAM Address: $0000.0C20 - 0C4F

❏ Default Data:

$00, $00, $00, $00, $00, $00, $00, $00,

$00, $00, $00, $00, $00, $00, $00, $00

3.21.5 Group E:

Board

Information

($0000.0C58 -

$0000.0C9B)

3.21.5.1

Character

I/O Ports

❏ Definition: unsigned char portno;

❏ Description:

Character I/O port. The upper nibble holds the input port number and the lower nibble holds the output port number.

Valid port numbers:

0: Keyboard/Graphic

1: SCC Port A

2: SCC Port B

3: FIFO

❏ RAM Address: $0000.0C59

❏ Default Data:

$00 i

This value may be overwritten, depending on the hex switch S902 setting.

It also will be changed to $11 if no graphic interface is installed.

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3.21.5.2

Watchdog

Enable Flag

❏ Definition: unsigned char wdog_enable;

❏ Description:

Enable watchdog timer.

Bit 0 = 0: watchdog disabled

Bit 0 = 1: watchdog enabled

❏ RAM Address: $0000.0C5C

❏ Default Data:

$00

3.21.5.3

Watchdog

Time-Out

Period

❏ Definition: unsigned long Wdog_time;

❏ Description:

Watchdog time-out period in milliseconds.

❏ RAM Address: $0000.0C5E

❏ Default Data:

$0082

(130 ms time-out)

3.21.5.4

Internal

Board

Information

❏ Definition: unsigned char board_info[0x20];

❏ Description:

ELTEC internal board information for service purposes.

These values should not be modified!!!

❏ RAM Address: $0000.0C68 - $0000.0C87

❏ Default Data:

$30, $41, $41, $31, $31, $31, $30, $30,

$30, $30, $30, $30, $30, $30, $FF, $FF,

$00, $00, $00, $00, $00, $00, $00, $00,

$00, $00, $00, $00, $00, $00, $00, $00

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3.21.5.5

Ethernet

Node

Address

❏ Definition: unsigned char ethernet_addr[6];

❏ Description:

Copy of the boards Ethernet node address. Read from the EEPROM during startup.

❏ RAM Address: $0000.0C88

❏ Default Data:

$FF, $FF, $FF, $FF, $FF, $FF

3.21.5.6

CPU Board

Identification

❏ Definition: unsigned char board_id;

❏ Description:

Unique number for each hardware platform.

Valid values:

13: E16

14: IBAM-30

15 E17

27 E27 or E17-500

40 BAB-40 or BAB-60

This value should not be modified!!!

❏ RAM Address: $C8E

❏ Default Data:

3.21.5.7

RMon Base

Address

❏ Definition: unsigned long rmon;

❏ Description:

Base address of RMon jump table for user-applicable routines.

❏ RAM Address: $0000.0C90

❏ Default Data:

$FE80.0000

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3 Programmers Reference BAB-40/60

3.21.5.8

Size of Local

Memory

❏ Definition: unsigned short memsize;

❏ Description:

Size of local memory in MB found during cold- or warmstart.

This value is changed by RMon.

❏ RAM Address: $0000.0C96

❏ Default Data:

$FFFF

3.21.6 Group F: Video

Descriptor

3.21.6.1

Graphic

Mode

❏ Definition: unsigned char rto_mode;

❏ Description:

Bits 0-3: Internal number used as index in the video descriptor table

Bit 5: Enable Digital output

❏ RAM Address: $0000.0CA0

❏ Default Data:

$00

3.21.6.2

Graphic Bit

Mode

❏ Definition: unsigned char rto_gbm;

❏ Description:

Number of bits per pixel.

Valid values:

$03: 8 bits per pixel

$02: 4 bits per pixel

$01: 2 bits per pixel

$00: 1 bit per pixel

❏ RAM Address: $0000.0CA1

❏ Default Data:

$02

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BAB-40/60 3 Programmers Reference

3.21.6.3

3.21.6.4

Display

Start

Address

Size of

Graphic

Plane

❏ Definition:

❏ Description: unsigned char rto_baseaddr;

Start address of video frame buffer.

❏ RAM Address: $0000.0CA2

❏ Default Data:

$0400.0000

❏ Definition:

❏ Description: unsigned short rto_plnsizx, rto_plnsizy;

Size of graphic plane in X and Y direction.

❏ RAM Address: $0000.0CA6 - $0000.0CA9

❏ Default Data:

2048, 1024

3.21.6.5

Size of

Display

Window

❏ Definition:

❏ Description: unsigned short rto_plnsizx, rto_plnsizy;

Size of window in X and Y direction.

❏ RAM Address: $0000.0CAA - $0000.0CAD

❏ Default Data:

640, 480

3.21.6.6

Number of

Fore-/

Background

Color

❏ Definition: unsigned char rto_fcol, rto_bcol;

❏ Description:

Number of foreground and background color.

Valid values:

0: black

1: navy blue

2: dark green

3: dark cyan

4: dark red

8: grey

9: blue

10: green

11: cyan

12: red

5: dark magenta 13: magenta

6: dark yellow

7: light grey

14: yellow

15: white

❏ RAM Address: $0000.0CAF - $0000.0CB0

❏ Default Data:

0, 15

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3 Programmers Reference BAB-40/60

3.21.6.7

Number of

Columns and Lines

❏ Definition: unsigned char rto_noofclms, rto_nooflins;

❏ Description:

This values define the number of columns and lines of the character window.

❏ RAM Address: $0000.0CB1 - $0000.0CB2

❏ Default Data:

80, 24

3.21.6.8

Video

Descriptor

Format

❏ Definition: unsigned char rto_vdform;

❏ Description:

Format of video descriptor.

Valid values:

$00: No position follows. The character window is placed in the center of the display window.

$01: The following two values specify the position of the character window within the display window.

❏ RAM Address: $0000.0CB3

❏ Default Data: 0

3.21.6.9

Position of

Character

Window

❏ Definition: unsigned short rto_wdworgx, rto_wdworgy;

❏ Description:

Position of the left upper pixel of the character window within the display window.

❏ RAM Address: $0000.0CB4 - $0000.0CB7

❏ Default Data:

0, 0

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BAB-40/60 3 Programmers Reference

3.21.6.10 Video

Timing

Parameter i

❏ Definition: unsigned long rto_param[0x38];

❏ Description:

Video Timing description. The values within this array have the meaning:

RAM Address

$0000.0CC0

$0000.0CC4

$0000.0CC8

$0000.0CCC

$0000.0CD0

$0000.0CD4

$0000.0CD8

$0000.0CDC

$0000.0CE0

$0000.0CE4

$0000.0CE8

$0000.0CEC

$0000.0CF0

$0000.0CF4

$0000.0CF8

Mnemonic pfreq hres hperiod hsync hbporch vres vperiod vsync vbporch syncmode eqlen serlen eqstart eqserin vres[2]

Meaning

Pixel Frequency

Horiz. Resolution

Horiz. Period

Horiz. Sync width

Horiz. Back Porch

Vert. Resolution

Vert. Period

Vert. Sync width

Vert. Back Porch

Sync Mode

Equalization width

Serration width

Equalization start

Equ./Ser. interval reserved

Unit

[Hz]

[pixel]

[lines]

[pixel]

[lines]

The bits of the 'syncmode' ($0000.0CE4) have the following meaning:

Bit Position

0x0000

0x0002

0x0004

0x0008

0x0010

0x0080

Mnemonic

HPOS

VPOS

GSYNC

CSYNC

TSYNC

DBLANKP

Meaning

Horiz. sync is positive

Vert. sync is positive

Sync on Green

Composite Sync

Tessellated Sync

Disable blank pedestal

❏ RAM Address: $0000.0CC0 - $0000.0CFF

❏ Default Data:

2575000, 640, 800, 96, 48, 480, 525, 2, 33,

0x0000, 0, 0, 0, 0, 0, 0,

It depends on the installed graphic module if changes at the video timing parameter also effect the hardware.

Hardware Manual 93

3 Programmers Reference BAB-40/60

3.21.6.11 Keyboard

Typamatic

Rate

❏ Definition: unsigned char kbrate;

❏ Description:

If this location is set to a value other than $FF, it is sent to the keyboard after the set typamatic rate/delay command code ($F3).

❏ RAM Address: $0000.0DA0

❏ Default Data:

$00

(30 codes per second after 250 ms delay)

3.21.6.12 Keyboard

Language

❏ Definition: unsigned char kblang;

❏ Description:

Keyboard language setting.

Valid values:

$FF: American keyboard (vt100)

$FE: German keyboard (vt100)

$EF: American keyboard (mgr)

$EE: German keyboard (mgr)

❏ RAM Address: $0000.0DA1

❏ Default Data:

$FF

3.21.7 Checksum ❏ Definition: unsigned long checksum;

❏ Description:

NVRAM checksum. This value is read only and is set or compared by the RMon commands re or we, respectively.

❏ RAM Address: $0000.0BFC - $0000.0BFF

❏ Default Data:

$FFFF.FFFF

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BAB-40/60

Appendix

Appendix

Hardware Manual 95

A.1 Mnemonics Chart BAB-40/60

A.1 Mnemonics Chart

This is the same mnemonics chart that can be found in the VMEbus

Specification.

A.1.1 Addressing

Capabilities

When the following mnemonic is applied to a board ...

It includes the following addressing capabilities:

A16 A24 A32 ADO

MASTER

MA16

MADO16

MA24

MADO24

MA32

MADO32

SLAVE

SADO16

SADO24

SADO32

LOCATION MONITORS

LMA16

LMA24

LMA32

A.1.2 Data Transfer

Capabilities

Master Data Transfer

When the following mnemonic is applied to a board ...

It means that the MASTER has the following data transfer capabilities:

D08(EO) D16 D32 UAT BLT

MD8

MBLT8

MRMW8

MALL8

MD16

BMBLT16

MRMW16

MALL16

MD32

MBLT32

MRMW32

MALL32

MD32+UAT

MRMW32+UAT

RMW

96 Hardware Manual

BAB-40/60 A.1 Mnemonics Chart

Slave Data Transfer

SD8(O)

SRMW(O)

SD8

SBLT8

SRMW8

SALL8

SD16

SBLT16

SRMW16

SALL16

SD32

SBLT32

SRMW32

SALL32

When the following mnemonic is applied to a board ...

It means that the SLAVE has the following data transfer capabilities:

D08(O) D16 D32 D08(O)

UAT

BLT

RMW

Location Monitor Data Transfer

When the following mnemonic is applied to a board ...

LMBLT32

LMRMW32

LMALL32+UAT

It means that its LOCATION MONITOR has the following capabilities:

D08(O)

D16

D32

UAT

BLT

RMW

A.1.3 Glossary

ADO

UAT

BLT

RMW

Address Only

Unaligned Transfer

Block Transfer

Read/Modify/Write

Both Even and Odd Addresses

Odd Addresses Only

Hardware Manual 97

A.2 Address Modifiers on VMEbus BAB-40/60

A.2 Address Modifiers on VMEbus

Hex Code Address Modifier

5 4 3 2 1 0

H H H H H H

H H H H H L

H H H H L H

H H H H L L

H H H L H H

H H H L H L

H H H L L H

H H H L L L

H H L x x x

H L H H H H

H L H H H L

H L H H L H

H L H H L L

H L H L H H

H L H L H L

H L H L L H

H L H L L L

H L L x x x

L H x x x x

L L H H H H

L L H H H L

L L H H L H

L L H H L L

L L H L H H

L L H L H L

L L H L L H

L L H L L L

L L L x x x

00-07

20-27

10-1F

30-37

Access

Standard Supervisory Ascending

Standard Supervisory Program

Standard Supervisory Data

Undefined

Standard Non-Privileged Ascend

Standard Non-Privileged Program

Standard Non-Privileged Data

Undefined

Short Supervisory I/O

Undefined

Short Non-Privileged I/O

Undefined

Extended Supervisory Ascending

Extended Supervisory Program

Extended Supervisory Data

Undefined

Extended Non-Privileged Ascend

Extended Non-Privileged Program

Extended Non-Privileged Data

Undefined

1 Defined by VMEbus Specification

2 Definition reserved

Note

98 Hardware Manual

BAB-40/60

3 Defined by user

A.2 Address Modifiers on VMEbus

Hardware Manual 99

BAB-40/60 A.3 Index

A.3 Index

Symbols

+RDY/-BSY . . . . . . . . . . . . . . . . . . . . . . . . . 45

+RESET . . . . . . . . . . . . . . . . . . . . . . . . . 45, 47

Address Map . . . . . . . . . . . . . . . . . . . . . . . . . 37 address modifier . . . . . . . . . . . . . . . . . . . 11, 37 address modifier source . . . . . . . . . . . . . 11, 43

Address Translation . . . . . . . . . . . . . . . . . . . 40

Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 66

AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bandwidth of the RAM . . . . . . . . . . . . . . . . . . 7

Board Installation . . . . . . . . . . . . . . . . . . . . . 28

Bootstrap . . . . . . . . . . . . . . . . . . . . . . . . . 12, 13

BTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bus time-out . . . . . . . . . . . . . . . . . . . . . . 11, 69

BV1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

BV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

CAS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 43

CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

CIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 53

Configuration . . . . . . . . . . . . . . . . . . . . . . . . 12

Configuration Registers . . . . . . . . . . . . . . . . 46

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

CT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

CT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Deadlock Resolution . . . . . . . . . . . . . . . . . . . 74 dynamic bus sizing . . . . . . . . . . . . . . . . . . 3, 11

EBAR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

EBAR01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

E (Continued)

EDCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

EDCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

EMAR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

EMAR01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . 8

Four Level Arbiter . . . . . . . . . . . . . . . . . . . . . 42

G getchar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

H hardware handshake . . . . . . . . . . . . . . . . . . . . 9

IACK daisy chain driver . . . . . . . . . . . . . . . . 11

ICF1 decoder . . . . . . . . . . . . . . . . . . . . . . . . . 40

ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . 11

IOALR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IOC-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

-IOCS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

IODCR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IODCR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

IODCR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

-IREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ITR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Hardware Manual 100

A.3 Index (Continued) BAB-40/60

I (Continued)

IV2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IV3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IV4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IV5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IV7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

IVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Local I/O Address Assignment . . . . . . . . . . . 38

Local Interrupt Sources . . . . . . . . . . . . . . . . . 73 locked cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Longword Access to Wordwide Slaves . . . . 43

MAU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 66

MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

MTBF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

NVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 12

Parameter RAM . . . . . . . . . . . . . . . . . . . . . 9, 51

PCMCIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Power-On Initialization . . . . . . . . . . . . . . . . . 12 printf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PS/2 SIMM . . . . . . . . . . . . . . . . . . . . . . . . 3, 25 putchar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 39, 41

RAM Mirror . . . . . . . . . . . . . . . . . . . . . . . . . 41

RDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Read-Modify-Write Cycles . . . . . . . . . . . . . . 43

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . 51

REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Relative Address Space . . . . . . . . . . . . . . . . . 45

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 68

RJ11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

RMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

RMon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ROMed application . . . . . . . . . . . . . . . . . . . . 13

R (Continued)

RS 232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

RS 422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

RS 485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SCRIPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 59

SILC . . . . . . . . . . . . . . . . . . . . . . . . 4, 9, 28, 61

SIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Status Display . . . . . . . . . . . . . . . . . . . . . 10, 67

SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . 11, 42

SYSRESET . . . . . . . . . . . . . . . . . . . . . . . . . . 11

System Control Register . . . . . . . . . . . . . . . . 70

System Controller . . . . . . . . . . . . . . . . . . 11, 42

TAS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 43, 74 tftp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 11, 44

VIC Timer . . . . . . . . . . . . . . . . . . . . . . . . 10, 50

VMEbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

VMEbus extended access . . . . . . . . . . . . . . . 39

VMEbus Interface . . . . . . . . . . . . . . . . . . . . . 11

VMEbus Interrupt Sources . . . . . . . . . . . . . . 73

VMEbus Master Interface . . . . . . . . . . . . . . . 11

VMEbus Slave Interface . . . . . . . . . . . . . . . . 11

Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

-WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Watchdog Timer . . . . . . . . . . . . . . . . . . . 10, 54

WIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

XON / XOFF . . . . . . . . . . . . . . . . . . . . . . . . . . 9

101 Hardware Manual

BAB-40/60 A.4 References

A.4 References

For more information, we recommend the following additional literature:

MC68(EC/LC)040

Microprocessors User’s Manual

MC68(EC/LC)060

M68040UM/AD

M68060UM/AD

Microprocessors User’s Manual

Motorola Ltd.; European Literature Centre;

88Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England

Further specifications and extracts of data sheets are available with the

Service Manual. For ordering information, refer to ‘Related Products’, page XII.

Hardware Manual 102

Oglas

elektronik mainz

Basic Automation Board

Table of Contents

List of Tables

List of Figures

Scope of Delivery

Options

Related Products

Conventions

How to Use this Manual

1 Specification

1.1 Main Features

1.2 General Description

1.3 Technical Details

1.4 Definition of Board Parameters

2 Installation

2.1 Introduction

2.2 Default Board Setting

2.3 Jumpers and Switches

3 Programmers Reference

3.1 Address Map

3.2 DRAM

3.3 VMEbus Interface

3.4 PCMCIA Interface

3.5 VIC Timer

3.6 Battery-Backed Parameter RAM and Real-Time Clock

3.7 CIO Counter / Timer

3.8 Watchdog Timer

3.9 Revision Information

3.10 Cache Coherency and Snooping

3.11 Serial I/O

3.12 Ethernet Interface (802.3/10base5)

3.13 SCSI Interface

3.14 IOC-2

3.15 Status Display

3.16 Reset

3.17 Bus Time-Out

3.18 System Control Register (SCR)

3.19 Interrupt Sources

3.20 Indivisible Cycle Operation

3.21 Default Parameters for RMon

Appendix

A.1 Mnemonics Chart

A.2 Address Modifiers on VMEbus

A.3 Index

A.4 References

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