STMicroelectronics L9305 Datasheet

L9305

Datasheet

Automotive 4-channel valve driver

Features

GADG0203181458PS

TQFP48 exposed pad down (7x7x1 mm)

GAPGPS00337

PowerSSO36 exposed pad down

Product status link

L9305

Product summary

Order code

Package

Packing

Order code

Package

Packing

Order code

Package

Packing

Order code

Package

Packing

L9305EP

PowerSSO36

Tube

L9305EP-TR

PowerSSO36

Tape and reel

L9305QFP

TQFP48

Tray

L9305QFP-TR

TQFP48

Tape and reel

• AEC-Q100 qualified

• 4-channel independent LSD/HSD current controlled drivers

– Integrated current sense path

– Current accuracy (in normal range)

◦ ± 5 mA in 0 to 0.5 A range

◦ ± 1% in 0.5 A to 1.5 A range

– Current accuracy (in extended range)

◦ ± 15 mA in 0 to 0.3 A range

◦ ± 5% in 0.3 A to 0.5 A range

◦ ± 4% in 0.5 A to 2 A range

– Max driver R

DSON

375 mΩ @ 175 °C

– 13-bit current set-point resolution

– Variable and fixed frequency current control

– Programmable dither function

– Selectable driver slew rate control

• Safety features

– High side fail safe ENABLE switch pre-driver with VDS monitoring

– Redundant safe enable path

– Advanced diagnosis and monitoring using BIST

– Temperature sensor and monitoring

– Redundant current sensing for all channels

– Calibration & configuration memory including CRC

– Secure serial communications using address feedback, 5-bit CRC, frame counter & long/short frame detection

– Register verification

• 32-bit SPI communications with 5-bit CRC message verification

• Package options: PWSSO36, TQFP48

• Full ISO26262 compliant, ASIL-D systems ready

Description

The L9305 is a configurable, monolithic solenoid driver IC designed for the control of linear solenoids for automatic transmission, electronic stability control, and active suspension applications. The four channels can be configured as either low side or high side drivers in any combination. The device includes the power transistor, recirculation transistor and current sensing for both the power and recirculation transistor. This architecture guarantees redundancy of the current measurement for each channel.

The regulated current is programmable in the range of 0-1.5 A (normal range), with a resolution of 0.25 mA, or 0-2 A (extended range), with a resolution of 0.33 mA. The user can superimpose configurable dither modulation over the set point current.

DS12774 - Rev 8 - November 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

L9305

A 32-bit CRC protected SPI interface is used for configuration and control of all channels and provides status feedback of all diagnostic functions. An active low reset input, RESN, is used to disable all channels and resets internal registers to their default values. A safe enable path is provided through the EN_DR pin and the integrated Fail Safe Pre-driver. An isolated redundant safety switch-off path ensures that critical internal faults disable the fail safe pre-driver. An active high enable pin,

EN_DR, is used to enable or disable the operation of all channels. When the EN_DR pin is low, all channels are disabled. A fault output pin is provided and can be used to generate an external interrupt to the microcontroller whenever a fault is detected.

The user can map specific faults to the FAULTn pin based on their specific system requirements.

DS12774 - Rev 8 page 2/107

1

Block diagram

Figure 1. Block diagram

L9305

VDDIO

MOSI

MISO

SCLK

CS

VDD

GNDA

GNDD

SPI

Charge Pump

Ch_0

Ch_1

Ch_2

EN_DR

RES

IN0/NDIS0

IN1/NDIS1

IN2/NDIS2

IN3/NDIS3

FAULT

Ch_3

N_FET

HS/LS Pre-Driver

Control & Diag.

L9305 (48 pin version only)

Additional N_FET

HS/LS Pre-Driver Control & Diagnosis

VBATP

VCP1

VCP2

VCP3

VCP4

VCP

VS_SOL_0

LOAD_SOL_0

GND_SOL_0

VS_SOL_1

LOAD_SOL_1

GND_SOL_1

VS_SOL_2

LOAD_SOL_2

GND_SOL_2

VS_SOL_3

LOAD_SOL_3

GND_SOL_3

FS_D0

FS_G0

FS_S0

L9305

Block diagram

GADG2609181252PS

DS12774 - Rev 8 page 3/107

DS12774 - Rev 8

L9305

Block diagram

VDDIO

3.3 V

5.0 V

VDD

5.0 V

Figure 2. PWSSO36 application schematic

Optional EMI filter

68 nF 68 nF

220 nF

L9305

Charge Pump

10 kΩ

MOSI

MISO

SCLK

CS

SPI

FAULT

EN_DR

IN0_NDIS0

IN1_NDIS1

IN2_NDIS2

IN3_NDIS3

RES

10 kΩ

Logic

Ch_0

Ch_1

Ch_2

Ch_3

FS_D

FS_G

100 kΩ

FS_S

VS_SOL_0

VS_SOL_1

VS_SOL_2

VS_SOL_3

LOAD_SOL_0

LOAD_SOL_1

LOAD_SOL_2

LOAD_SOL_3

GND_SOL_0

GND_SOL_1

GND_SOL_2

GND_SOL_3

VBAT

GNDD GNDA GND_SOL

GADG2609181259PS page 4/107

L9305

Block diagram

VDDIO

3.3 V

5.0 V

VDD

5.0 V

10 kΩ

MOSI

MISO

SCLK

CS

SPI

FAULT

EN_DR

IN0_NDIS0

IN1_NDIS1

IN2_NDIS2

IN3_NDIS3

RES

Logic

Figure 3. TQFP48 application schematic

Optional EMI filter

68 nF 68 nF

220 nF

VBAT

L9305

Charge Pump

FS_D2

FS_D3

FS_G2

FS_G3

FS_S2

FS_S3

FS_D0

FS_D1

FS_G0

FS_G1

FS_S0

FS_S1

100 kΩ

100 kΩ

100 kΩ

100 kΩ

10 kΩ

Ch_0

Ch_1

Ch_2

Ch_3

VS_SOL_0

VS_SOL_1

VS_SOL_2

VS_SOL_3

LOAD_SOL_0

LOAD_SOL_1

LOAD_SOL_2

LOAD_SOL_3

GND_SOL_0

GND_SOL_1

GND_SOL_2

GND_SOL_3

GNDD GNDA GND_SOL

GADG2609181302PS

DS12774 - Rev 8 page 5/107

L9305

Pins description

2

Pins description

GND_SOL_1

LOAD_SOL_1

VS_SOL_1

IN_DIS0

IN_DIS1

CS

MOSI

SCLK

MISO

EN_DR

VDDIO

GNDD

RESn

IN_DIS2

IN_DIS3

VS_SOL2

LOAD_SOL2

GND_SOL2

3

4

5

1

2

8

9

6

7

10

11

12

13

14

15

16

17

18

Figure 4. PowerSSO-36 pinout diagram

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

GND_SOL0

LOAD_SOL0

VS_SOL0

VBATP

VC1

VC3

VC4

VC2

VCP

FS_G0

FS_S0

FS_D0

VDD

GNDA

FAULTn

VS_SOL3

LOAD_SOL3

GND_SOL3

Figure 5. TQFP48 pinout diagram

VS_SOL0

LOAD_SOL0

GND_SOL0

NC

NC

NC

FS_D1

FS_S1

FS_G1

GND_SOL1

LOAD_SOL1

VS_SOL1

5

6

7

8

9

3

4

1

2

10

11

12

32

31

30

29

28

36

35

34

33

27

26

25

VS_SOL3

LOAD_SOL3

GND_SOL3

FS_G3

FS_S3

FS_D3

FS_D2

FS_S2

FS_G2

GND_SOL2

LOAD_SOL2

VS_SOL2

GADG2609181330PS

GADG2709181048PS

DS12774 - Rev 8 page 6/107

DS12774 - Rev 8

L9305

Pins description

22

23

24

25

16

17

18

19

20

21

28

29

30

31

26

27

8

9

10

11

12

13

14

15

Pin number

PowerSSO-36

1

2

3

4

5

6

7

Table 1. PowerSSO-36 and TQFP48 pins list

Pin number

TQFP48

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

34

35

36

37

38

39

40

41

42

43

44

45

46

Symbol Function

GND_SOL1 Channel 1 Ground: Ground connection for channel 1 power stage.

LOAD_SOL1 Channel 1 Output

VS_SOL1

Channel 1 Supply Voltage: Connect to Switched Battery Voltage with reverse protection diode

IN_DIS0

IN_DIS1

Parallel Input Channel 0: Input for direct control from external MCU when in SW Mode; Disable channel command when in SW mode

Parallel Input Channel 1: Input for direct control from external MCU when in SW Mode; Disable channel command when in SW mode

CS

MOSI

SCLK

SPI Chip Select Input: SPI communication protocol Chip Select from

MCU to the device. Digital logic level: 5.0V or 3.3V

SPI Data Input: SPI communication protocol input from MCU to the device. Digital logic level: 5.0V or 3.3V

SPI Clock Input: SPI communication protocol clock from MCU to the device. Digital logic level: 5.0V or 3.3V

MISO

EN_DR

VDDIO

GNDD

RESn

SPI Data Output: SPI communication protocol output to MCU from the device. Digital logic level: 5.0V or 3.3V

Enable Driver:

IO Supply: To be connected to 5.0V or 3.3V

Digital Ground: Ground for digital circuits

IN_DIS2

Reset: when HIGH, device out of reset, when LOW, device in reset state

Parallel Input Channel 2: Input for direct control from external MCU when in SW Mode; Disable channel command when in SW mode

IN_DIS3

VS_SOL2

Parallel Input Channel 3: Input for direct control from external MCU when in SW Mode; Disable channel command when in SW mode

Channel 2 Supply Voltage: Connect to Switched Battery Voltage with reverse protection diode

LOAD_SOL2 Channel 2 Output

GND_SOL2 Channel 2 Ground: Ground connection for channel 2 power stage.

GND_SOL3 Channel 3 Ground: Ground connection for channel 3 power stage.

LOAD_SOL3 Channel 3 Output

VS_SOL3

Channel 3 Supply Voltage: Connect to Switched Battery Voltage with reverse protection diode

FAULTn

GNDA

VDD

FS_D0

Fault: when LOW, Fault present, when HIGH, no fault present

Analog Ground: Ground for analog circuits

Supply Voltage: Supply for circuits. Connect to 5.0V supply voltage

Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor

FS_S0

FS_G0

VCP

VC2

VC4

VC3

Fail Safe Source: to be connected to external FET Source used as FS.

VDS monitor

Fail Safe Gate: Gate command for external FET Drain used as FS

Charge Pump Voltage: Connected to Protected Battery Voltage through

External Capacitor

Charge Pump: External Capacitor connection

Charge Pump: External Capacitor connection

Charge Pump: External Capacitor connection page 7/107

DS12774 - Rev 8

L9305

Pins description

Pin number

PowerSSO-36

32

33

34

–

–

35

36

–

–

–

–

–

–

–

–

–

–

–

Pin number

TQFP48

47

48

1

2

3

–

9

8

7

6

5

4

28

29

30

31

32

33

Symbol Function

VC1

VBATP

Charge Pump: External Capacitor connection

Supply Voltage: Connected to Protected Battery Voltage (reverse protection diode and filter against EMC)

VS_SOL0

Channel 0 Supply Voltage: Connect to Switched Battery Voltage with reverse protection diode

LOAD_SOL0 Channel 0 Output

GND_SOL0 Channel 0 Ground: Ground connection for channel 0 power stage.

– Available on TQFP-48 version only

FS_G_1 Fail Safe Gate: Gate command for external FET Drain used as FS

FS_S_1

Fail Safe Source: to be connected to external FET Source used as FS.

VDS monitor

FS_D_1

NC

NC

NC

FS_G2

FS_S2

FS_D2

FS_D3

Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor

Not Used: To be connected to GND.

Not Used: To be connected to GND.

Not Used: To be connected to GND.

Fail Safe Gate: Gate command for external FET Drain used as FS

Fail Safe Source: to be connected to external FET Source used as FS.

VDS monitor

Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor

Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor

FS_S3

Fail Safe Source: to be connected to external FET Source used as FS.

VDS monitor

FS_G_3 Fail Safe Gate: Gate command for external FET Drain used as FS page 8/107

3

3.1

3.2

L9305

Product Characteristics

Product Characteristics

Absolute maximum ratings

This part may be irreparably damaged if taken outside the values specified in the next table. Operation above the absolute maximum ratings may also cause a decrease in reliability. The operating junction temperature range is from -40 °C to +175 °C. The maximum junction temperature must not be exceeded. All voltages are with respect to analog ground pin GNDA.

Table 2. Absolute maximum ratings

Pin name

VBATP

VCP

VC1, VC3

VC2, VC4

VS_SOLx

Type

Global

Local Note: VCP-VBATP<13V, VBATP-VCP<0.3V

Local Note: VCx-VBATP<0.3V

Local Note: VCx-VBATP<13V VBATP-VCx<0.3V

Global

Test condition

LOAD_SOLx

GND_SOLx

VDD

VDDIO

GNDD

FS_D0

FS_G0

Global

Local

Local

Local

Local

Global

Local

Internally shorted to FS_S0 (off phase) Note:

FS_G0-FS_S0<13V

Global Note: FS_S0-FS_G0<0.3V

FS_S0

CS, SCLK, MOSI, EN_DR, RESn,

INx_DISx

MISO, FAULTn

Local

Local

1. 35V AMR over life-time, 40V for ISO-pulse transients (as defined in ISO7637-2 standard).

2. biased condition, -0.3V for unbiased conditions/sleep mode.

Min Typ Max Unit Pin type

-0.3

– 40 V S

-0.3

– 50

-0.3

– 40

V

V

S

O

-0.3

– 50

-0.3

–

40 (1)

V

V

O

S

-0.3

–

40 (1)

V

-0.3

– 0.3

V

-0.3

– 19

-0.3

– 19

V

V

-0.3

– 0.3

V

-0.3

– 40 V

S

S

O

I

S

I

-2 (2)

-2

–

–

50

50

-0.3

– 19

-0.3

– 19

V

V

V

V

O

O

I

O

Latchup trials

Latch-up tests performed according to JEDEC 78 class 2 Level A

DS12774 - Rev 8 page 9/107

3.3

3.4

L9305

ESD performance

ESD performance

Symbol

ESD HBM

ESD HBM

ESD CDM

Corner

ESD CDM

Table 3. ESD Performance

Parameter Test condition

HBM Global pins

ESD according to Human Body Model (HBM),

Q100-002 for all pins; (100pF/1,5kΩ)

HBM all pins

ESD according to Human Body Model (HBM),

Q100-002 for all pins; (100pF/1,5kΩ)

CDM corner pins

ESD according to Charged Device Model (CDM),

Q100-011 Corner pins

CDM all pins

ESD according to Charged Device Model (CDM),

Q100-011 All pins

Min Typ Max Unit Pin

-4 – 4 kV Global

-2 – 2 kV ALL

-750 – 750 V Corner

-500 – 500 V ALL

Temperature range

Table 4. Device operating temperature

R

Th j-a

R

Th j-c

R

Th j-b

R

Th j-a

R

Th j-c

R

Th j-b

Symbol

T amb

T j

T stg

Parameter

Operating ambient temperature

Junction temperature

Storage temperature

T pas

Maximum non/operating temperature during passive lifetime

Thermal Resistance junction to ambient

Thermal Resistance junction to case

Thermal Resistance junction to board

Thermal Resistance junction to ambient

Thermal Resistance junction to case

Thermal Resistance junction to board

–

–

Test condition

Package: PWSSO36

2s2p (4L) board

(2)

Natural convection

Package: TQFP48 (E-pad: 5x5 mm)

2s2p (4L) board

(2)

Natural convection

Min Typ Max

-40

-40

-50

-55

–

–

–

–

–

–

–

–

–

–

22

1

7

27

2

9

135

175

175

150

–

–

–

–

–

–

(1)

Unit Pin

°C

°C

°C

°C

ALL

ALL

ALL

ALL

°C/W ALL

°C/W ALL

1. 175°C are allowed for limited time. Eventual Mission profiles with passive lifetime temperature >150°C have to be evaluated by ST to confirm that product qualification is able to cover the required conditions.

2. JESD51-7

All parameters are guaranteed, and tested, in the temperature range from T j

-40 to 150 °C (unless otherwise specified); the device is still operative and functional at higher temperatures (up to T j

175 °C). Device functionality at high temperature up to T j

= 175 °C is guaranteed by bench validation, electrical parameters are guaranteed by correlation with ATE tests at reduced temperature and adjusted limits (if needed).

DS12774 - Rev 8 page 10/107

4

4.1

4.2

4.3

4.4

L9305

Input / Output

Input / Output

Reset (RESn)

The RESn pin is the reset input for the device. If the RESn pin is low, the device is held in an internal reset state, all outputs channels are disabled, the failsafe pre-drivers are disabled, the FAULTn pin is held low and all registers are reset to their default values. An internal pull down current source will hold the RESn pin low in case the pin is open. RESn pin status is echoed in each SPI frame.

Enable (EN_DR)

The EN_DR pin is used to enable / disable the output stages. When EN_DR pin is low, all channels are disabled, all fail safe pre-drivers are disabled and the FAULTn pin is pulled low if EN_DR is not masked. The EN_DR pin can be connected to a general purpose output pin of the microcontroller or to an alternative safety circuit.

When EN_DR pin is set high, all channels are enabled based on their configuration settings and the fail safe pre-drivers can be controlled through the Fail Safe Configuration Register.

Channel inputs (INx/NDISx)

The INx/NDISx pins serve two purposes depending on the selected load control method. If the load is controlled using the internal closed loop current control circuit (referred to as Hardware Mode), INx/NDISx serves as an enable/disable signal for each channel. When in this mode, if INx/NDISx is high, output control is disabled and when low output control is enabled.

The second operating mode is referred to as Software Mode. When the device is programmed for Software Mode, the INx/NDISx pin serves as the PWM input signal to directly control the output drivers. When INx/NDISx is high, the driving transistor is enabled and the active recirculation transistor is disabled. When INx/NDISx is low, the driving transistor is disabled and the active recirculation transistor is enabled. The driving transistor and active recirculation transistor are dependent on the programmed output configuration, high side or low side. High and

low side configurations are explained in Section 6 Current control drivers

.

Fault (FAULTn)

The device sets the FAULTn pin low upon detecting internal and external faults and while the device is in reset.

The FAULTn pin is open drain and requires an external pull-up resistor connected between VDDIO and the

FAULTn pin. A summary of all faults linked to the state of FAULTn are shown in Table 5 and

Table 6

. Only faults with specified masking register bits can be masked or unmasked by the user. Faults denoted as “None” are automatically linked to FAULTn output status. In addition to the items below, RESn is not masked and is linked to the FAULTn pin by default.

Table 5. Global and external supply fault pin error masking

Digital Ground Loss Fault

FAULTn Masking function

Analog Ground Loss Fault

Fail Safe VDS Fault

EEPROM Trimming Data CRC Error Fault

SPI Timeout Latch Fault

SPI Timeout Fault

VDD Under Voltage Fault

VDD Over Voltage Fault

V3V3A Over Voltage

V3V3D Under Voltage

Register & Data Bit

SERVFLTMSK1, D[15]

SERVFLTMSK1, D[14]

SERVFLTMSK1, D[10]

SERVFLTMSK1, D[8]

SERVFLTMSK1, D[7]

SERVFLTMSK1, D[6]

SERVFLTMSK1, D[4]

None

None

None

DS12774 - Rev 8 page 11/107

4.5

L9305

SPI communications (CS, SCLK, MOSI & MISO)

FAULTn Masking function

V3V3D Over Voltage

Oscillator Stuck

Oscillator Mismatch

Internal Global Register Error

CP Under Voltage Fault

Configuration Register Mismatch Fault

VBATP Over Voltage Fault

Core Over Temperature Fault

SPI Protocol Error Fault

IN 3 Echo Fault

IN 2 Echo Fault

IN 1 Echo Fault

IN 0 Echo Fault

EN_DR Echo Fault

Register & Data Bit

None

None

None

None

SERVFLTMSK1, D[3]

SERVFLTMSK1, D[2]

SERVFLTMSK1, D[1]

SERVFLTMSK1, D[0]

SERVFLTMSK2 D[15]

SERVFLTMSK2 D[4]

SERVFLTMSK2 D[3]

SERVFLTMSK2 D[2]

SERVFLTMSK2 D[1]

SERVFLTMSK2 D[0]

Table 6. Solenoid channel and fail safe fault pin error masking

FAULTn Masking function

E_Sol_Thermal Warning

EEPROM CRC Error on CSA Calibration Data

EEPROM CRC Error on ADC Trimming Bits

PWM check fault

E_Sol_Open Load Fault

E_Sol_Short Fault

E_Sol_ADC Fault

E_LSCLAMP Fault

E_Sol_HS Over Current Fault

E_Sol_LS Over Current Fault

E_Sol Over Temperature Fault

Out of Regulation Fault

GND_SOL Loss Fault

E_RAM_CRC_ERR Fault

E_SOL_HS/LS Fault

E_CFG_REG_FAIL Fault

Register & Data Bit

DRVFLTMSK1,D[15]

DRVFLTMSK1,D[14]

DRVFLTMSK1,D[13]

DRVFLTMSK1,D[12]

DRVFLTMSK1,D[6]

DRVFLTMSK1,D[5]

DRVFLTMSK1,D[4]

DRVFLTMSK1,D[3]

DRVFLTMSK1,D[2]

DRVFLTMSK1,D[1]

DRVFLTMSK1,D[0]

DRVFLTMSK2,D[4]

DRVFLTMSK2,D[3]

DRVFLTMSK2,D[2]

DRVFLTMSK2,D[1]

DRVFLTMSK2,D[0]

SPI communications (CS, SCLK, MOSI & MISO)

The CS, SCLK, MOSI & MISO pins provide serial communications between the device and the microcontroller.

Please see Section 9 SPI for details on SPI features, device register functions and electrical characteristics.

DS12774 - Rev 8 page 12/107

L9305

Input / output electrical specifications

4.6

Input / output electrical specifications

4.75 V ≤ V

DD

≤ 5.5 V; 5.5 ≤ V

BATP pin.

≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noted. All voltages refer to GNDA

Symbol

EN_DR_low

EN_DR_high

EN_DR_hyst

EN_DR_pd

Parameter

Logic input low detection

Logic Input high detection

Input hysteresis voltage

Inter pull down resistance

EN_DR_deglitch

EN_DR_test_low

EN_DR_test_high

EN_DR_test_hyst

INx_DISx_low

INx_DISx_high

INx_DISx_hyst

EN_DR deglitch filter

Logic input low detection

Logic input high detection

Input hysteresis voltage

Logic Input low detection

Logic input high detection

Input hysteresis voltage

INx_DISx_pd Inter pull down resistance

INx_DISx_deglitch_SW Actuation deglitch in SW mode

INx_DISx_deglitch_HW Disable deglitch in HW mode

RESn_low Logic input low detection

RESn_high

RESn_hyst

Logic input high detection

Input hysteresis voltage

RESn_pd

RESn_deglitch

FAULTn_Ileak

Inter pull down resistance

RESn deglitch filter

Leakage current in tri-state condition

FAULTn_low

FAULTn_high

Logic low level

Logic high level

FAULTn_trise

FAULTn_tfall

Table 7. Digital input/output electrical performance

Test condition

–

–

–

–

–

–

–

–

V

IN

< 3V

Guaranteed by scan

–

–

–

VIN < 3V

Guaranteed by scan

Guaranteed by scan

–

VIN < 2.5V

Guaranteed by scan

FAULTn rise time

FAULTn fall time

–

Ext pull-up 4.7k to VDDIO

Ext pull-up 4.7k to VDDIO

Ext pull-up 4.7k to VDDIO,

Cload=20pF,tested by correlation

Ext pull-up 4.7k to VDDIO,

Cload=20pF

Min

–

1.75

0.1

10

10

3

1.2

–

1.75

0.1

10

4.5

9

–

9

0.1

–

1.75

0.1

–

Typ Max Unit Pin

– 0.75

–

– – V

EN_DR

EN_DR

– – V EN_DR

38 70 kΩ EN_DR

–

–

–

–

–

12 µs EN_DR

6

–

–

–

V

V

EN_DR

EN_DR

EN_DR

– 0.75

V INx_DISx

–

–

V INx_DISx

V INx_DISx

38 70 kΩ INx_DISx

3.5

3.9

µs INx_DISx

1.5

1.7

µs INx_DISx

– 0.75

– RESn

–

–

–

–

V

V

RESn

RESn

38 70 kΩ

5 7 µs

RESn

RESn

– 10 – FAULTn

– – 0.4

– FAULTn

VDDIO-0.4

– – V FAULTn

–

–

– 100 ns FAULTn

– 100 ns FAULTn

DS12774 - Rev 8 page 13/107

5

5.1

5.2

5.3

L9305

Power supply

Power supply

Overview

The L9305 has multiple supply pins. Internal circuits are powered from VDD (+5 V) and VBATP (reverse battery protected) while digital I/O pins are powered from VDDIO (3.3 V or 5 V) for consistency with the main microcontroller I/O operation. The charge pump regulator is sourced from VBATP and supplies the necessary voltage source for the high side integrated valve drivers and fail safe pre-drivers.

Battery supply (VBATP)

This pin is the supply for the charge pump and must be connected to the reverse polarity protected battery voltage supply. VBATP input voltage is diagnosed for over voltage conditions. The status of this diagnostic is

readable by SPI. Refer to Section 8.1.2 VBATP supply over voltage for additional information. The following table

summarizes the functional ranges dependent on battery supply voltage.

Table 8. VBATP electrical performance

Symbol

VBATP operational

Parameter

Normal operating voltage range

(1)

VBATP double/load dump High voltage range

VBATP over voltage

VBATP low voltage

Over voltage range

(2)

(3)

Low Voltage Range Cranking

(4)

Test condition Min Typ Max Unit

T amb

= 40 °C, 4.75 V ≤ VDD ≤ 5.5 V 5.5

– 19

T amb

= 27 °C, 4.75 V ≤ VDD ≤ 5.5 V 5.55

– 19

T amb

= 125 °C, 4.75 V ≤ VDD ≤ 5.5 V 5.6

– 19

T amb

≤ 50 °C, 4.75 V ≤ VDD ≤ 5.5 V 19 – 36

V

V

V

V

T amb

≤ 50 °C, 4.75 V ≤ VDD ≤ 5.5 V

T amb

= -40 °C, 4.75 V ≤ VDD ≤ 5.5 V

36

–

T amb

= 27 °C, 4.75 V ≤ VDD ≤ 5.5 V –

T amb

= 125 °C, 4.75 V ≤ VDD ≤ 5.5 V –

–

–

–

–

40

5.5

5.55

5.6

V

V

V

V

1. Device is capable of full functional operation; VBATP must be reversed battery protected

2. Device is capable of full functional operation at Ta ≤ 50 °C with possible degradation of electrical parameters linked to battery line (ex. solenoid slew rate control and current regulation accuracy); There will be no damage to the device, no false operation and input pins will withstand voltage and current defined in Absolute ratings regardless of battery voltage range.

Full functional operation will resume without operator intervention when battery voltage returns to Normal Operating Voltage

Range at Ta ≤ 50 °C.

3. Ta ≤ 50 °C, duration less than 500 ms. There will be no damage to the device, Solenoid channels and Fail Safe switch will be disabled and input pins will withstand voltages and currents defined in Absolute ratings regardless of battery voltage range. Full functional operation will resume with operator intervention, as described in the specification, when battery voltage returns to normal operating voltage range.

4. Device is capable of full functional operation until charge pump is out of under voltage condition with possible degradation of electrical parameters linked to battery line (ex. solenoid slew rate control and current regulation accuracy). Full functional operation will resume without operator intervention when battery voltage returns to normal operating voltage range.

Load supplies (VSOL1, VSOL2, VSOL3 & VSOL4)

The VSOLx pins are connected to the high side of the solenoid load when the output drivers are configured for low side operation. In low side operation, VSOLx provides power to the load and recirculation path through the high side driver. When the output drivers are configured for high side operation, the VSOLx pin becomes the power source for driving the load thru the high side solenoid driver transistor. In this case, load current is recirculated through the corresponding low side driver. VSOLx pins are independent for each solenoid driver

channel. Solenoid driver operation and configuration are detailed in Section 6.4 Solenoid driver and load diagnostic .

DS12774 - Rev 8 page 14/107

5.4

5.5

5.6

5.7

5.8

L9305

Analog and digital supply (VDD)

Analog and digital supply (VDD)

The VDD pin provides the source voltage for all internal analog (V3V3A) and digital (V3V3D) circuits. An internal start-up circuit connected to VDD initializes the internal regulators (V3V3A & V3V3D) once VDD reaches

VDD_UV threshold. V3V3A & V3V3D regulators are monitored for internal power on reset control (POR). VDD input voltage is diagnosed for over and under voltage conditions. The status of this diagnostic is readable by SPI.

Please see Section 8.1.1 VDD over and under voltage diagnostics

.

I/O supply (VDDIO)

VDDIO is the supply for all pins that interface with the external microcontroller. This pin must be connected to a supply with the same voltage used by the microcontroller I/O, 3.3 V or 5.0 V. There is no monitoring function associated with VDDIO.

Power-On reset

An internal power on reset circuit holds the device in a reset state if VDD goes below the under voltage threshold.

The power on reset is released once VDD is within normal operating range for the specified reset filter time

TPOR. The SPI interface can be accessed after the power on reset time.

The fault bit “POR_flag” in the SERVFLT1 register is set, when the device exits the reset state. This bit is cleared automatically, whenever the SERVFLT1 register is accessed. Also RES_echo in PINSTATUS register is set, when the device exits the reset state in case of Power-On reset event, despite the state of RESn pin. The microcontroller can use these bits to determine if an internal or external reset has occurred.

A power on reset (POR) can also occur if any of the internal bandgap regulators or internal analog & digital regulators are diagnosed as over or under voltage. Additional details on these and VDD monitoring can be found

in sections Section 8.1.1

and Section 8.1.4

.

GND (GNDD, GNDA, GND_SOLx)

The L9305 has two low power ground connections, GNDD and GNDA. These connections are for internal analog and digital control circuits. Exposed pad is connected to substrate and to GNDA. GNDD and GNDA are connected through a pair of anti-parallel ESD diodes. The device has 4 power ground connections, GND_SOL0,

GND_SOL1, GND_SOL2 and GND_SOL3. All ground pins have open circuit detection. Additional details on

ground loss detection are shown in Section 8.1.5 GND loss detection .

Charge pump

To effectively bias the high side solenoid drivers and fail safe switch, a charge pump is used to drive the gate voltage above VBATP. The device uses a common charge pump for all channels and is referred to the battery voltage supply connected to the VBATP pin. The charge pump output voltage is present at the VCP pin. The charge pump switching frequency is nominally 470 kHz and its internal control loop reduces emissions by pulse skipping once the targeted operating voltage is reached.

The charge pump circuit requires three external capacitors. A “Tank” capacitor with a recommended value of

220 nF must be connected between the VCP pin and the VBATP pin. Two pump capacitors with recommended values of 68 nF must be connected between the VCP1 and VCP2 pins and also between the VCP3 and VCP4 pins. A built-in monitoring circuit checks if the charge pump output voltage is sufficient to control the high side valve driver. Additional details for charge pump voltage monitoring are shown in

Section 8.1.3 VCP supply under voltage

.

The charge pump voltage is also used as parallel supply to the VDD supply for internal references to avoid ASIC reset at low VDD input.

DS12774 - Rev 8 page 15/107

L9305

Startup & power down sequence

VBATP

Figure 6. Charge pump mechanization

CTANK

C1 C2

X

VC1

X

VC2

X X

VC3

Charge Pump

X

VC4

X

VCP

GADG2709181559PS

5.9

Startup & power down sequence

L9305 begins initialization and execution of all internal diagnostic and self-test functions upon VDD reaching the

VDD_UV threshold. A detailed list of these monitoring functions is summarized in

Section 8 Safety features

.

While the device is initializing, the FAULTn pin remains low. Upon completing initialization, the SPI POR flag is set high (clear on read) to indicate a POR event has occurred and the FAULTn pin remains low until the RESn input is set high. The RESn input can be set high prior to the device completing initialization but the FAULTn pin will not be released until the POR event is complete. This sequence is shown in

Figure 7

. Also RES_echo in PINSTATUS register is set, when the device exits the reset state in case of Power-On reset event, despite the state of RESn pin.

Once the POR event is complete and the RESn input is set high, the device can be configured by the user. All registers maintain RESET default states until both POR is set high and RESn is set by the user.

Figure 7. Startup procedure example

Case #1: RESn released before internal operations completed

VDD

VDD_UV

Case #2: RESn released before internal operations completed

VDD

VDD_UV

Internal Operations Internal Operations

VCP_UV

VCP

VCP_UV

RESn

FAULTn

HiZ

RESn

FAULTn

HiZ

GADG2709181142PS

L9305 power down sequence requires only the VDD supply be disabled. Once the VDD_UV threshold is reached, the solenoid and fail safe pre-driver outputs are disabled. There are no timing dependencies between VDD and

VBATP voltage levels to perform the power down sequence.

DS12774 - Rev 8 page 16/107

L9305

Power supply electrical specifications

5.10

Power supply electrical specifications

4.75V ≤ VDD ≤ 5.5V; 5.5 ≤ VBATP ≤ 19V; -40°C ≤ Tj ≤ 175°C unless otherwise noted. All voltages refer to GNDA pin.

Table 9. Power supply electrical performance

Symbol Parameter Test condition

POR_deglitch

VBATP_stby_cur

VDD_stby_cur

VBATP_on_state_cur

POR analog deglitch

VBATP stby current consumption

VDD stby current consumption

VBATP on state current consumption

VDD_on_state_cur

VDDIO_stby_curr

VDD on state current consumption

VDDIO stby current consumption

VDDIO_on_state_curr

VDDIO on state current consumption

V3V3A

V3V3D fosc_main fosc_aux fosc_mod_freq

Internal analog supply line

Internal digital supply line

Main oscillator frequency

Auxiliary oscillator frequency

Spread spectrum modulation frequency

VDD = 5 V

VDD = 0 V, VDDIO = 5 V

VDD = 5 V, VDDIO = 5 V

Design info, not tested

Design info, not tested

–

–

Design info, not tested fosc_mod_index_min

Spread spectrum minimum modulation index fosc_mod_index_max

Spread spectrum maximum modulation index

VDD = 0 V, VBATP = 13 V

VDD < 0.3 V

VDD = 5 V, VBATP = 13 V, All channels tristated

Guaranteed by scan

Guaranteed by scan

VCP_start tasic_init

CP_freq

VCP_out

VCP_out_min

CP initialization time

Initialization time of ASIC

Charge pump frequency

CP target output voltage

Minimum charge pump output voltage

VBATP = 13 V, CP from VBATP to VBATP+7 V

Time from VDD rising to FAULTn release, RESn HIGH

–

Design info, not tested

I load

= 10 mA, solenoid channels tri-stated, FS disabled, VBATP =

5.5 V

Min

10

–

–

5

20

-1

–

–

–

-5%

-5%

–

-5

2

–

– fosc/34

–

VBATP+7

Typ

18

–

–

10

30

–

–

3.3

3.3

16

16

125

–

–

–

–

–

Max

30

45

1

20

40

1

5

–

–

5%

–

-2

5

1

5

–

Unit

µs

µA

µA mA mA

µA mA

V

V

5% MHz

MHz kHz

%

% ms ms

470

VBATP+9 fosc/34 kHz

– V

V

Pin

POR

VBATP

VDD

VBATP

VDD

VDDIO

VDDIO

V3V3A

V3V3D fosc fosc_aux fosc, fosc_aux fosc, fosc_aux fosc, fosc_aux

CP

VDD,

FAULTN

Cx

CP

CP

DS12774 - Rev 8 page 17/107

6

6.1

L9305

Current control drivers

Current control drivers

The L9305 provides four independent current control channels. Each channel includes the Driver Control Block,

Analog Current Measurement Block and Output Stage. The Output Stage consists of a driving transistor and the recirculation transistor and is user configurable for high side or low side control. When configured as a low side driver, the high side driver recirculates load current. When configured as a high side driver, the low side driver

recirculates load current. Configuration examples are shown in Figure 8 and Section 6 Current control drivers .

Both high and low side paths have independent current sense circuits to ensure accurate current control in either configuration. The high or low side configuration is selected in register, Channelx_CONFIGURATION1, D[3]. The device defaults to low side configuration.

L9305

Figure 8. HS driver (left) and LS driver (right) configuration

Load Supply

L9305

Load Supply

VS_SOL_x VS_SOL_x

INx INx

Current

Control

&

Drivers

LOADx

Current

Control

&

Drivers

EN_DR EN_DR

LOADx

SPI SPI SPI SPI

GND_SOL_x GND_SOL_x

GADG2709181147PS

Calibration and trim data are stored in internal E 2 PROM memory and are used to optimize current control performance. Upon power on reset, the device transfers calibration and trim data into local RAM for use in the Driver Control and Current Measurement blocks. These data are verified using CRC checks, please see

Section 8.4.4 for more details.

Load current can be controlled using the internal closed loop control circuits or directly by the microcontroller as summarized below.

• Hardware current control

– Current Set Point and Switching frequency are programmed through SPI registers

– Device automatically adjusts the PWM Duty cycle to maintain the programmed load current

• Software current control

– Current Set Point and Switching frequency are managed directly by the microcontroller

– L9305 provides average current feedback through SPI and acts only as load driver

Current control configuration and setup are programmed through the SPI interface. Configuration registers

(Channel_x. CONFIGURATION 1 and Channel_x.CONFIGURATION2) can only be modified when the channel is not enabled (SOLENDR).

Hardware current control

Each channel has four operating states, Disabled, Tristate, PWM and Full on. These operating states are dependent on internal registers settings, SOLENDR register, bit D[7:0] and EN_DR and INxDISx input pins. A summary of these settings is shown below. Please note the SOLENDR register assigns 2 bits per channel to select driver operating state, therefore the table below shows only two bits.

DS12774 - Rev 8 page 18/107

DS12774 - Rev 8

L9305

Hardware current control

EN_DR INx

LOW X

HIGH HIGH

HIGH LOW

HIGH LOW

HIGH LOW

HIGH LOW

Table 10. Solenoid driver status in hardware mode

Driver Configuration Status

[1] [0]

0

1

1

X

X

0

1

0

1

X

X

0

Channel Status

Driver Disabled, Off Diagnosis disabled and Masked

Driver in Tristate, Off diagnosis can be switched on

Driver ON in PWM mode,Off Diagnosis disabled and Masked

Driver ON in Full ON mode,Off Diagnosis disabled and Masked

Disabled Mode: Output drivers are disabled, no bias is present on the driver, off-state diagnostics are masked and cannot be enabled; LS clamp feature is inactive, thus, if an overvoltage occurs when driver is disabled, low side mos will not be protected

Tristate Mode: Driver is supplied and kept in a tristate high impedance mode, off state diagnostics can be enabled

PWM Mode: Output drivers are actively regulating load current as programmed, off state diagnostics are disabled.

FULL_ON Mode: Output driver is driven to saturation and is kept on continuously until the mode is changed by the user or a fault occurs.

Figure 9. Hardware control configuration

EN_DR

INx

HS

Current Sense

VS_SOL_x

HS Driver

SPI

Target current

Switching freq.

Control param.

Dither

SPI

Driver

Control

LS Driver

LOADx

GND_SOL_x

LS

Current Sense

GADG2709181150PS

Upon completing channel configuration and set-up as summarized in

Section 6 Current control drivers

, the internal hardware control loop can then be configured for either fixed frequency or variable frequency current control (HW feedback Frequency Mode D[11] in CTRLCFG register). The current control method (HW mod/SW mode) is selectable using register CONFIGURATION1, D[2]. In addition to selecting the control method, the user must program the targeted load current and operating frequency. Load current is programmed through the Current

Set Point Register (SETPOINT) and the operating frequency in the Control Configuration Register (CTRLCFG).

Once the channel is enabled, the device begins to PWM control the load current for the targeted current value.

The device can synchronize channel actuation by enabling all channels with a single SPI write operation.

Actuation control can also be staggered 90 degrees when programmed for fixed frequency control using the

Stagger Enable D[0] bit in SERVENA register.

page 19/107

6.1.1

6.1.2

6.1.3

L9305

Hardware current control

Current set point programming

The targeted average current set point is independently programmable for each channel through the dedicated

SPI register (Channel_x.Current_Set_Point) and it is 13-bit wide. The current resolution is programmable in two resolution steps through the HILOAD bit (D[8] in Channel_x.Configuration1) which will also set the maximum regulated current. Below is a brief summary for using HILOAD to select current range and resolution.

•

•

HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] - Max Avg. Current 1.5 [A].

TargetAverageCurrent = Setpoint 12:0 *0.25 mA

HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] - Max Avg. Current 2.0 [A].

TargetAverageCurrent = Setpoint 12:0 *0.33 mA

The maximum guaranteed ripple current for the device’s specified accuracy is 0.5 [A] peak to peak for HILOAD=0 and 0.66 [A] peak to peak for HILOAD=1, so that the max load current for correct current control is

• 1500 mA + 250 mA = 1750 mA for HILOAD = 0

• 2000 mA + 330 mA = 2330 mA for HILOAD = 1

If the channel is enabled and programmed with 0x0000h current set point, the power output is forced with duty cycle 0 (recirculation path fully on) and the current measurement is disabled; set point codes higher than 0x1770h are reserved for calibration and offset compensation purposes: in case such codes are selected, the accuracy is not guaranteed.

When CHx.SETPOINT=0000 and channel x is controlled Hardware mode (CONFIGURATION1.D[2]=0), then current measurement is disabled and AVGCUR always returns all ‘0’, even if channel x is driven full-on.

PWM switching period programming

The PWM switching period is programmable as shown in the next table, through the dedicated 11-bit field in the

SPI register Channel_x.Control Configuration (CTRLCFG):

PWM code [10:0] hex dec

0x000

0x001

…

0x009

0x00A

0x00B

…

0x681

0x682

0x683

…

0x7FF

0

1

…

9

10

11

…

1665

1666

1667

…

2047

50

55

…

95

100

110

…

16650

16660

16670

16670

16670

Table 11. PWM period and Frequency Programming

Period [µs]

Frequency

[Hz]

20000

18180

…

10520

10000

9090

…

60.06

60.02

60.02

60.02

60.02

Status

Short period/High frequency range

PWM Period = 50 µs + PWM Code D[10:0] * 5 µs

PWM Period = PWM Code D[10:0] * 10 µs

Normal Period/Frequency range.

Values clamped to maximum period of 16.67 ms

Current control loop configuration

Hardware current control feedback Frequency Mode is user programmable for either variable or fixed frequency operation through register Channelx_CTRLCFG, bit D[11].

In fixed frequency current control configuration, the programmed PWM period is exactly the actuated period. The control algorithm and a Proportional-Integral (PI) processing circuit with ramp-compare control the duty cycle.

In variable frequency current control configuration, the programmed PWM period is the target set point for the inner frequency control loop. The control algorithm and a zero crossing integrator control both PWM period and duty cycle. The actual PWM period may differ from the target PWM period, especially during transients.

DS12774 - Rev 8 page 20/107

6.1.4

L9305

Hardware current control

A set of parameters for the loop control is available through SPI registers in order to tune the transient response and settling time of the loop based on the user’s load characteristics. These settings and details are discussed in the following sections.

Fixed frequency control

The fixed frequency control subtracts the current measurement signal from the programmed set point to create the error signal. The proportional and integral amplifiers process the error signal and generate the

PROPORTIONAL and INTEGRAL signals. The processing of PROPORTIONAL and INTEGRAL signals depends on the user programmed values of Kp and Ki in the Channel_x.KGAINS register. The control loop then adds

PROPORTIONAL and INTEGRAL signals and compares the result with ramp generator.

Figure 10. Fixed frequency algorithm

Current

Set Point +

–

Current

Measurement

Kp

(*)

Ki

(*)

+

+

(**)

PROPORTIONAL

INTEGRAL

+

+

PI

Limiter

Z –1

Register

RAMP

Ramp

Generator

Integrator

Comparator

+

–

PWM

(*) Programmable parameter.

(**) The integrator limiter is automatically calculated for Fixed Frequency algorithm. It avoids that the PI signal

exceeds the max. and min. levels of the RAMP signal. This allows fastest loop transient response.

GADG2709181213PS

The LIMITER in the integral path, limits the integral signal automatically to the RAMP signal to ensure the fastest

PWM changes to reduce current over and under shoot. An example of current control block diagram is shown in

Figure 10 .

DS12774 - Rev 8 page 21/107

L9305

Hardware current control

Figure 11. Fixed frequency signals

Tpwm

PWM

(1) (2) (1) (2) (1)

PI t t

6.1.5

Load current t

GADG2709181214PS

In fixed frequency current control, basic operation is dependent on the ramp generator and the PI signal as follows:

•

•

Switch OFF point (1): the PI signal crosses the RAMP signal from high to low, the output driver is switched off and the load CURRENT reaches its maximum peak value.

Switch ON point (2): every clock based TPWM periods, the RAMP signal resets and the output driver is switched on and the load current reaches its minimum peak value.

To optimize current control capability, the user must properly select KP and KI amplitude settings

(Channel_x.KGAINS) for each application.

•

•

KP : parameter controls the amplitude of the Proportional signal and is calculated as: KP = 2

KP_sel

KI : parameter controls the amplitude of the Integral signal and is calculated as: KI = 2

KIsel

•

Variable frequency control

From Figure 12

, the current control loop subtracts the measured current from the programmed set point to derive an error signal. The integral amplifier with gain KI processes the error signal creating the INTEGRAL signal. The frequency control loop subtracts the PWM period set point T

PWM

from the measured PWM period creating a period error signal. The integral amplifier with gain KFI, processes the period error and generates the resulting frequency integral (F_I) output signal.

Variable frequency control operation is dependent on the INTEGRAL signal, F_I signal and zero level signal as follows:

• Switch OFF point: the INTEGRAL signal crosses the F_I signal from high to low, the output driver is switched off and the load CURRENT reaches its maximum peak value.

Switch ON point: the INTEGRAL signal crosses the zero level signal from low to high, the output driver is switched ON, and the load CURRENT reaches its minimum peak value.

The variable frequency control provides a transient mode for optimization of the transient condition behavior.

It eliminates in this way current over/undershoot and allows the fastest reaching of the final frequency. The transient mode is entered in case of a change of current set point (Set Point Change) while the Auto Limit control bit is set. The transient mode is also entered in case the PWM period is longer than a threshold (Long

Period Detection). The 2-bit control input Transition Time (D[15:14] in CTRLCFG register) selects the Long Period

Detection threshold.

DS12774 - Rev 8 page 22/107

DS12774 - Rev 8

L9305

Hardware current control

Figure 12. Variable frequency algorithm

Current Control

Current

Set Point +

–

KI

+

+

Integrator

Register

Z –1

Limit

+

–

Comp

INTEGRAL

+

–

Comp

SET

State machine

PWM

RES

Current

Measurement

Frequency Control

PWM Period

Set Point

–

+

KFI

Current

Measurement

Set Point Change

OR

Long Period Detection

+

+

Initial

Z –1

Register

F_Integrator

F_INTEGRAL

PWM

1.1

1.05

1

0.95

0.9

Load Current Current

Set Point

INTEGRAL

2000

0

-2000

-4000

ZERO

10.9

1.1

F_INTEGRAL

11.1

11.2

11.3

Time (ms)

11.4

11.5

11.6

GADG2709181227PS

•

•

•

•

•

•

In transient mode the integrator limits the INTEGRAL signal within user programmable limits, this guarantees the fastest current transitions between different set points without showing over/undershoot. The integrator limits of variable frequency control are not automatically calculated; the user-programmed parameters POSINTLIM and

NEGINTLIM are available for optimized positive and negative integrator limits.

In transient mode the F_INTEGRAL signal at the frequency integrator output is set to a programmable value with the 3 control bits FINT_START (D[2:0] in KFREQCTRL register), in this way the F_INTEGRAL signal starts close to its final value when exiting from transient mode.

To optimize the controller response for different applications, the following parameters must be programmed by the user:

KI (Channel_x.KGAINS)

KFI (Channel_x.KFREQCTRL)

POSINTLIM & NEGINTLIM (Channel_x.INTGLIM)

Auto Limit (Channel_x.SETPOINT)

Transition Time (Channel_x.CTRLCFG)

Fint_Start (Channel_x.KFREQCTRL)

Programming values can be selected considering the following:

•

•

•

•

•

KI : Integral portion of the loop gain. It can be calculated as KI = 2

KIsel

KFI : Integral portion of the frequency control loop gain. It can be calculated as KFI = 2

KFIsel

POSINTLIM : Positive Integrator Saturation Limit. It can be calculated as POSINTLIM = 2

POSINTLIMsel − 1

NEGINTLIM : Negative Integrator Saturation Limit. It can be calculated as

NEGINTLIM = −2

NEGINTLIMsel − 1

AUTO_LIMIT:

•

– If AUTOL_LIMIT_SEL = 0 → Transient mode is insensitive to changes of Current Set Point

– If AUTOL_LIMIT_SEL = 1 → Any change in the current set point activates the transient mode

FINIT_START:

– If FINIT_START_SEL = 0 → FINIT

START

= 0

– If FINIT_START_SEL >0 → FINIT

START

= NEGINTLIM*2

FINITSTARTsel − 7 page 23/107

6.1.6

6.1.7

6.1.8

L9305

Hardware current control

• TRANSITION TIME : Too long PWM period detection: if the current PWM time exceeds this threshold, the controller enters the transient state. It can be programmed as follows:

– If TRANSITION TIME = 0 → TRANSTIME = 2,5*T

PWM

– If TRANSITION TIME = 1 → TRANSTIME = 4,5*T

PWM

– If TRANSITION TIME = 2 → TRANSTIME = 8,5*T

PWM

– If TRANSITION TIME = 3 → TRANSTIME = 16,5*T

PWM

Chopper offset compensation of current sense amplifier

This function cancels the input offset of the current sense amplifier by converting the DC input offset voltage to an

AC noise at the chopper frequency. Function is normally enabled and can be disabled by the user via SPI register

(OFS_CMP_DIS D[14] in Channel_x.CONFIGURATION1 register).

•

Staggered channel activation

•

•

Staggered channel operation is enabled by the user through the SPI Service Enable register, SERVENA (Stagger

Enable bit D[0]). When staggered operation is enabled and the targeted regulated current is achieved, the PWM switch-on points is staggered per the following sequence:

•

Channel 0 → 0° phase advance; reference channel

Channel 1 → 90° phase advance

Channel 2 → 180° phase advance

Channel 3 → 270° phase advance

This function is specific to fixed frequency current control and is disabled in variable frequency mode.

Parallel mode

The 4 channels can be configured to work in parallel mode to allow regulation of higher current set-points: this option is suitable for example in applications where setting HILOAD = 1 is not enough to match targets.

Channel parallelization can be enabled only for fixed channel pairs:

• ch0 can be put in parallel with ch1 only

• ch2 can be put in parallel with ch3 only

•

•

•

In parallel mode one channel acts as a master (ch0, ch2) and the other as a slave (ch1, ch3): both channel current sense measurements are kept active to measure load current split between channel pair: the two measurements are combined and used to close control loop on master logic only.

Configuration of parallel mode is done through master channel registers and in detail the following master parameters are valid for both channels, overwriting slave channel configuration (if any):

Current set-point,

Dither parameters,

Control loop parameters (Ki, Kp, fix/var frequency mode selector, Kfi, etc…)

•

•

•

•

•

•

As a consequence of the described implementation, the resulting resolution of the current and dither set-point registers is doubled since target value is applied on both channels in parallel: it means that in parallel mode

1 LSB = 0.5 mA instead of default 0.25 mA.

Feedback of measured average current is kept distinguished like in normal operation and available for each channel on its own register with nominal LSB of 0.25 mA. The same applies for HS-LS compare check and applied offset compensation.

The following parameters are kept independent between master and slave channels and particular attention must be paid for proper configuration settings:

HW/SW mode selection

HS/LS configuration

INx/NDISx functionality diagnostic calibration data offset compensation

DS12774 - Rev 8 page 24/107

6.1.9

L9305

Hardware current control

To enable parallel mode the following conditions must be verified, otherwise the channels will be kept independent depending on their own settings:

•

•

Bit 14 and/or Bit15 in SERVENA register must be set to 1 (Bit14 enables parallel mode for ch0-ch1 pair,

Bit15 for ch2-ch3 pair)

SOLENDRV configuration must be equal for selected parallel channel pair

Even if diagnostic is kept independent, faults causing tri-state condition will affect both channels in parallel mode.

Parallel mode is mandatory to use only with maximum slew rate setting and in configuration HILOAD=0. Besides, driver active time (T_ON) must be higher than a minimum value, which directly depends on load current, battery voltage applied to the solenoid and load parameters.

Further guidelines on the usage of this feature are provided in a specific dedicated Application Note.

Dither programming

Dither programming (Channel_x.DITHPGM1 and Channel_x.DITHPGM2) superimposes a triangular amplitude modulation on the current set point as shown in the

Figure 13

.

Figure 13. Dither waveforms definitions

Tdither[s] = 4 · Nstep · Tstep[s]

(1)

(2)

(3)

Tstep[s]

Istep

3 steps 3 steps 3 steps

Example of Nstep = 3

3 steps

Isetpoint

Tdither[s] = 4 · Tstep[s]

(1)

Tstep[s]

Isetpoint

Istep

Example of Nstep = 1

Tdither[s] = 2 · Tstep[s]

Tstep[s]

Isetpoint

Istep

Example of Nstep = 0

GADG2709181243PS

•

•

To implement dither function, the following parameters need to be set according to the user operating requirements.

• Tstep : Dither step time duration is programmable as an integer number of PWM periods as defined by the formula DitℎerStepDuration = Tstep + 1 *Tpwm where:

– Tstep is programmable in Channel_x.DITHPGM2, D[5:0].

•

– T

PWM

is the PWM period programmable in Channel_x.CTRLCFG register, D[10]

Nstep : number of steps in a quarter of a dither period, where:

•

– Nstep is the value programmed in Channel_DITHPGM2 register, D[12:8]

– If Nstep = 0, a square wave dither of 2 steps peak to peak will be generated

Istep : Current step amplitude is programmable in Channel_xDITHPGM1 register, D[7:0] with the same current resolution as the current set point.

– HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] - Max Step Current 63.75[mA];

DitℎerStepCurrent = Istep 7:0 *0.25 mA

– HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] - Max Step Current 84.15[mA].

DitℎerStepCurrent = Istep 7:0 *0.33 mA

Tdither: Dither period calculated as: Tditℎer = 4*Nstep*Tstep

Idither: Peak-to-peak current modulation amplitude calculated as: Iditℎer = 2*Nstep*Istep

Dither can be enabled/disabled via SPI in register Channel_x.DITHPGM1, D[15]. Dither waveform maximum amplitude is limited by the selected current resolution configuration (HILOAD, register CONFIGURATION1, D[15]) as shown below:

HILOAD = 0 → Normal current mode - Max Dither Current Amplitude = ± 250 [mA];

HILOAD = 1 → High current mode - Max Dither Current Amplitude = ± 330 [mA];

DS12774 - Rev 8 page 25/107

L9305

Software current control

6.1.10

6.2

•

•

Dither synchronization

In variable frequency mode, the PWM switch-on events are not clock based and are dependent on frequency control loop response. Therefore variable frequency mode is naturally asynchronous with respect to the dither steps. However, it is still possible to synchronize dither with the variable frequency PWM control by synchronizing with the actual PWM frequency. There are two options to sync the dither waveform. The two sync types are shown below. Please, note that the function is not valid for fixed frequency operation since all dither steps are synchronous with the PWM control frequency.

Dither SYNC Enable - register Channelx_DTHPGM1, bit D[14]

– 0 → Dither synch for variable frequency is disabled

– 1 → Dither synch for variable frequency is enabled

SYNC TYP E – register ChannelxDTHPGM1, bit D[13]

– 0 → All Dither Steps are synchronous with the PWM Period. In this case the time base for Dither Step duration is the actual PWM period rather than the exact target set point PWM period

– 1 → The Dither Period starts synchronous with the actual PWM Period. Only for the initial step in the dither period, the T step

is delayed to the next switch on transition of the PWM period. The time of such initial step may be longer than the programmed period.

Software current control

In this configuration the device works as a driver without internal current control but provides the average measured load current to the MCU through register Channel_x.AVGCUR, bits D[13:0]. With the average current feedback, the MCU can close the current control loop.

Figure 14. Software control configuration

HS

Current Sense

VS_SOL_x

EN_DR

HS Driver

INx

Driver

Control

LOADx

LS Driver

GND_SOL_x

SPI SPI

LS

Current Sense

GADG2709181307PS

To avoid spurious switching of the external loads due to noise spikes on INx pins, a digital filter, LOADx_ton_res and LOADx_toff_res (where “x” is related to selected channel), has been added to these pins.

Since the filter time is applied on each transition of the INx pin signal, OFF to ON and ON to OFF, the effect limits the minimum period or maximum frequency of the signal delivered to the LOADx pin.

Channel state depends on the EN_DR input pin and the value of the Driver Configuration/Status SPI register

(Global.Solenoid Drivers Enable) as shown below.

EN_DR

LOW

HIGH

Table 12. Solenoid driver channel status in hardware mode

Driver configuration status

[1] [0]

X

0

X

0

Channel status

Driver Disabled, Off Diagnosis disabled and Masked

DS12774 - Rev 8 page 26/107

6.3

6.3.1

L9305

Solenoid current control feedback

EN_DR

HIGH

HIGH

HIGH

Driver configuration status

[1]

0

[0]

1

1 0

1 1

Channel status

Driver in Tristate, Off diagnosis can be switched on

Driver ON in PWM mode,Off Diagnosis disabled and

Masked

Driver ON in Full ON mode,Off Diagnosis disabled and Masked

Disabled Mode: Driver is kept disabled. No supply is present onto the driver; off diagnosis is masked and cannot be enabled.

Tristate Mode: Driver is supplied and kept in Tristate: Hi impedance. Off state diagnostics

(Channel_x.Configuration) can be enabled.

PWM Mode: Driver is supplied and on. Off state diagnostics are masked. Load is driven by the PWM signal applied to the INx pin. Depending on the selected configuration (HS or LS mode), the INx polarity is defined as follows:

Table 13. INx polarity

Driver Configuration

LOW Side

(load connected between VS_SOLx pin and LOAD_SOLx pin)

HIGH Side

(load connected between LOAD_SOLx pin and GND_SOLx pin)

Driver Status

Low side FET

High side FET

Low side FET

High side FET

INx Pin Status

HIGH LOW

ON

OFF

OFF

OFF

ON

ON

ON OFF

FULL_ON Mode: Driver is supplied and in FULL_ON mode. In this condition, the driver is kept on continuously, until the FULL_ON mode is removed or a fault occurs.

Solenoid current control feedback

Average current

The solenoid current, as a result of internal current sensing, calibration correction and final average calculation over an entire PWM period, is available for SPI reading from Channel_x.AVGCUR register. Independent of HW or SW mode current control selection, the average current calculation cycle starts at each PWM switch ON event and ends at the next PWM switch ON event. The average current calculated is immediately available to the SPI output register through the dedicated 14-bit field in SPI register Channel_x.AVGCUR.

•

•

HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA]

AverageCurrent = 2Complemet AvgCur 13:0 *0.25 mA

HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA]

AverageCurrent = 2Complemet AvgCur 13:0 *0.33 mA

In case the Driver input signal is stuck high or low for a time period longer than T pwm_max

, the TMOUT warning flag is set in Channel_x.PWMSENSE register and the average current is evaluated only for T pwm_max

. After timeout, the average current and PWM code calculations restart automatically.

When CHx.SETPOINT=0000 and channel x is controlled Hardware mode (CONFIGURATION1.D[2]=0), then the current measurement is disabled and AVGCUR always returns all ‘0’, even if channel x is driven full-on.

DS12774 - Rev 8 page 27/107

6.3.2

6.3.3

6.3.4

L9305

Solenoid current control feedback

Integrator feedback

The current integrator output values are important feedback for proper selection of many control parameters. The device provides integrator feedback through the Channel_x.INTOUT register. The content of Channel_x.INTOUT

register is determined in the Channel_x.INTGLIM register bits D[15:14]. The integrator feedback definition is defined below:

Integrator low threshold:

The integrator such a threshold corresponds to the integrator value at which the PWM toggles from high to low and the output driver switches off. At this point, the load current reaches its max peak level. In variable frequency this level also corresponds to the “F_INTEGRAL” signal at the frequency integrator output. Use this integrator reading to correctly set the “Fint_Start” parameter.

Integrator high threshold:

The integrator such a threshold corresponds to the integrator value at which the PWM toggles from low to high and the output driver switches on. At this point, the load current reaches its min peak level. In variable frequency this level is zero. Use this integrator reading to verify the correct functionality of the variable frequency algorithm.

Integrator minimum level:

The minimum current integrator level. Use this integrator reading to correctly set the “NEGINTLIM” parameter.

Integrator maximum level:

The maximum current integrator level. Use this integrator reading to correctly set the “POSINTLIM” parameter.

•

•

Solenoid PWM period feedback

The actual PWM time period, whether it is generated by the internal logic in hardware mode or by the INx pins in software mode, is internally measured at each PWM rising edge and provided to the MCU for comparison with the programmed value in register Channel_x.PWMSENSE. It is also checked against the minimum period reference

(T pwm_min

) and maximum period reference (T pwm_max

) values. Should the PWM period fall outside these limits, the TMOUT flag is set in SPI register Channel_x.PWMSENSE indicating the control loop is working at an unusual value. If no PWM signal is generated after the maximum reference period (T pwm_max

), the average current is calculated over T pwm_max

period of time.

The PWM period is provided using 15 bits with 1µs resolution, providing feedback for periods exceeding

T pwm_max

values. The PWM period feedback value is obtained by the formula:

PWMPeriod = Cℎannel_x . PWMSENSE . PWMCode μs

T pwm_min

= 40 µs → fpwm_max = 25 kHz

T pwm_max

= 16.667 ms → fpwm_min = 60 Hz

(1)

Out of regulation flag

An out of regulation flag is set when the current controller average error is not zero for a time longer than 8 PWM periods, where the PWM period is the programmed PWM period in SPI register Channel_x.CTRLCFG. The flag is independent for each channel and is only available in Hardware Current Control mode.

DS12774 - Rev 8 page 28/107

6.4

6.4.1

6.4.2

6.4.3

6.4.4

L9305

Solenoid driver and load diagnostic

Solenoid driver and load diagnostic

Thermal protection

Each solenoid channel has a dedicated temperature sensor that continuously monitors the temperature of the

Low Side and of the High Side power transistor. Temperature information is available in the dedicated SPI register

Channel_x.TEMPMON. Register data can be decoded from the SPI frame using the following formula:

(2)

Should channel temperature reach the thermal warning threshold T_WARN, the thermal warning flag is set in the

EXCEPTIONS1 register bit D[15]. The warning flag is latched and is cleared upon SPI read if the thermal warning condition is no longer present.

Should channel temperature continue to rise up to the thermal shutdown threshold T_SD, the related channel is placed in tristate mode (setting the Solenoid Driver Status bits to 01, but keeping the programmed current set-point). This event has a dedicated fault flag in the EXCEPTIONS1 register, bit D[0]. Channel activation is prevented if thermal shut down condition is still present on SPI read. This fault is latched and is cleared upon

SPI read if the fault is no longer present. Channel thermal shutdown temperature has no hysteresis, but user can decide which temperature is low enough to re-enable the channel. In fact, by monitoring Channelx.TEMPMON

register, user can re-enable the channel when TEMPMON reading is below the temperature desired value: thus a further degree of flexibility is provided.

Overcurrent protection

Overcurrent protection is present for each HS and LS solenoid driver. The overcurrent threshold is selectable through SPI register Channel_x.CONFIGURATION1 bit D[6].

Should an overcurrent fault be detected (on HS or on LS), the related channel is put in tri-state (setting the

Solenoid Driver Status bits to 01, but keeping programmed current set-point) and a dedicated diagnostic bit is set in register Channel_x.EXCEPTION1, bits D[2] for HS and D[1] for LS. To restart the channel, the MCU must clear the fault bit by reading the fault register and re-enable the channel.

Supply disconnection

When a solenoid channel is configured for low side operation, current recirculation occurs through the internal high side transistor. If the supply Vs_solX of the high side driver is lost, the voltage at LOAD_SOLx pin can become unpredictable and possibly exceed the absolute rating of the device. To prevent this condition from damaging the device, the low side driver has an integrated clamping circuit to limit the peak voltage.

Should the low side clamping structure be activated during normal operation (i.e. solenoid supply line within normal operating range), the channel is put in tri-state (setting the Solenoid Driver Status bits to 01) and the Low

Side Clamp Active fault flag D[3] is set in the EXCEPTIONS1 register. To restart the channel, the MCU must clear the fault by reading the EXCEPTIONS1 register and re-enable the channel.

Activation of LS clamp during a load dump event could damage the device due to the high energy of load dump event. To avoid this condition, the LS clamp circuitry is automatically disabled when VBATP pin exceeds deep

over-voltage threshold, as defined in Section 8.1.6

.

Off state solenoid diagnostics

The device provides independent off-state diagnostics for each channel. Simplified diagrams are shown in

Figure 15 and Figure 16 below, depending on the chosen configuration.

DS12774 - Rev 8 page 29/107

DS12774 - Rev 8

DIAGOL

DIAGLV

DIAGOL

DIAGLV

Figure 15. Low side configuration diagnostic

L9305

Solenoid driver and load diagnostic

VSx

+

–

HS GATE

DRIVER off state

+

–

VTOPEN

VOUTOPEN + gm

–

I_LS_PU

I_LS_PD

VTGND

LS GATE

DRIVER off state

LOAD

LOADx

RETURNx

GADG2709181312PS

Figure 16. High side configuration diagnostic

VSx

+

–

HS GATE

DRIVER off state

+

–

VTVBAT

VOUTOPEN + gm

–

I_HS_PU

I_HS_PD

VTOPEN

LS GATE

DRIVER off state

LOADx

LOAD

RETURNx

GADG2709181314PS page 30/107

L9305

Valve driver electrical specifications

By default, diagnostic pull up/down current sources are disabled and comparator outputs are masked by internal logic. To enable OFF state diagnostics, the channel must be in tri-state (set in the SOLENDRV register Solenoid

Driver State_x[1:0]=01) and enabled using register Channel_x.CONFIGURATION1, bit [5]. In case the desired channel is put in tri-state after operation a false diagnostic can be sensed due to the time needed to discharge output voltage through the load. To avoid incorrect fault detection, the fault comparators are masked for td_blank filter time. The diagnostic blanking time is programmable through SPI register Channel_x.CONFIGURATION1, bit D[9]. Blanking time is programmable to best align with external load values and ESD capacitor connected to the output pin. Fault conditions are latched and cleared on SPI read, however they do not prevent from enabling the solenoid channels. OFF state diagnostic comparators are the same for both HS and LS configuration and their output is decoded from internal logic to set the SPI fault bits (Channel_x.EXCEPTIONS1) according to the following tables

Comparator output

DIAGOL DIAGLV

0

0

1

1

0

1

0

1

Table 14. LS diagnostic truth table

Fault detection

Normal operation – no fault-

Not possible

Open load

Short to ground

Exception registers

OPEN LOAD SHORT

0

0

1

0

0

0

0

1

Comparator output

DIAGOL DIAGLV

0

0

0

1

1

1

0

1

Table 15. HS diagnostic truth table

Fault detection

Short to Battery

Not possible

Open load

Normal operation – no fault-

Exception registers

OPEN LOAD SHORT

0

0

1

0

1

0

0

0

6.5

Valve driver electrical specifications

4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; VS_SOLx ≤ 19 V; VBATP-1 V ≤ VS_SOLx ≤ VBATP+1 V; -40 °C ≤

T j

≤ 175 °C unless otherwise noted. All voltages refer to GNDA pin.

Table 16. Valve driver power stage electrical parameters

Symbol

Solenoid driver power stage

Parameter Test condition Min Typ Max Unit

Irev_VSx

Irev_LOADx

VSx reverse current

LOADx reverse current

Application note: in the application condition, no impact on other functions, no reset generation

Application note: in the application condition, no impact on other functions, no leakage from nearby pins, no reset generation

-3

-3

–

–

–

–

A

Pin

VS_SOLx

A LOAD_SOLx

VSx_lkg

LOADx_lkg

HS_RdsON

HS_RdsON

VSx current leakage stby

LOADx current leakage tristate

High side RdsON

High side RdsON

Output disabled, VDD = 0 V, VS_SOLx = 13 V

Output disabled, VDD = 5 V, VS_SOLx = 13 V,

LOAD_SOLx = VS_SOLx or GND

T j

= 150 °C, I

LOAD

= 1 A

T j

= 175 °C, I

LOAD

= 1 A

-1

-140 – 100 µA LOAD_SOLx

–

–

– 1 µA VS_SOLx

– 0.33

Ω LOAD_SOLx

– 0.375

Ω LOAD_SOLx

DS12774 - Rev 8 page 31/107

L9305

Valve driver electrical specifications

Symbol Parameter

LS_RdsON

LS_RdsON

Low side RdsON

Low side RdsON

LOAD_SOLx_ton_res ton filter time

LOAD_SOLx_toff_res toff filter time

LOAD_SOLx_SR00

Voltage slew rate

SR00

LOAD_SOLx_SR01

LOAD_SOLx_SR10

Voltage slew rate

SR01

Voltage slew rate

SR10

LOAD_SOLx_SR11

Voltage slew rate

SR11

LOAD_SOLx_ton00_HS ton 00_HS_mode

LOAD_SOLx_ton00_LS ton 00_LS_mode

LOAD_SOLx_ton01_HS ton 01_HS_mode

LOAD_SOLx_ton01_LS ton 01_LS_mode

LOAD_SOLx_ton10 ton 10

LOAD_SOLx_ton11 ton 11

LOAD_SOLx_toff00_HS toff 00_HS_mode

LOAD_SOLx_toff00_LS toff 00_LS_mode

LOAD_SOLx_toff01 toff 01

LOAD_SOLx_toff10_HS toff 10_HS_mode

LOAD_SOLx_toff10_LS toff 10_LS_mode

LOAD_SOLx_toff11 toff 11

Test condition

T j

= 150 °C, I

LOAD

= 1 A

T j

= 175 °C, I

LOAD

= 1 A

Software mode, Guaranteed by scan

Software mode, Guaranteed by scan

20% to 80% & 80% to 20%, VBATP = 13 V, R load

=

6 Ω, C load

= 10 nF

20% to 80% & 80% to 20%, VBATP = 13 V, R load

=

6 Ω, C load

= 10 nF

20% to 80% & 80% to 20%, VBATP = 13 V, R load

=

6 Ω, C load

= 10 nF

20% to 80% & 80% to 20%, VBATP = 13 V, R load

=

6 Ω, C load

= 10 nF

SW mode from INx_DISx to 20% in HS

SW mode from INx_DISx to 80% in LS

SW mode from INx_DISx to 20% in HS

SW mode from INx_DISx to 80% in LS

SW mode from INx_DISx to 20% in HS, from

INx_DISx to 80% in LS

SW mode from INx_DISx to 20% in HS, from

INx_DISx to 80% in LS

SW mode, from INx_DISx to 80% in HS

SW mode, from INx_DISx to 20% in LS

SW mode, from INx_DISx to 80% in HS, from

INx_DISx to 20% in LS

SW mode, from INx_DISx to 80% in HS

SW mode, from INx_DISx to 20% in LS

SW mode, from INx_DISx to 80% in HS, from

INx_DISx to 20% in LS

Min Typ Max Unit

–

–

–

–

0.33

0.375

Ω

Ω

LOAD_SOLx

LOAD_SOLx

3 3.5

3.9

µs LOAD_SOLx

3 3.5

3.9

µs LOAD_SOLx

0.2

0.6

3

6

8

12

4

5

3

3

10

16

8

3

5

3

0.3

1

4

8

–

–

–

–

–

–

–

–

–

–

–

–

0.6

1.8

6

12

16

20

10

13

8

8

22

26

20

8

10

8

V/µs LOAD_SOLx

V/µs LOAD_SOLx

V/µs LOAD_SOLx

V/µs LOAD_SOLx

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

µs

Pin

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

Symbol Parameter

Current control

I reg_range

Current regulation range

I peak_range

I reg_res

Peak Current regulation range

Current regulation resolution

I reg_acc_L

I reg_acc

Current regulation accuracy

Current regulation accuracy

I reg_range

Current regulation range

I peak_range

Peak Current regulation range

Table 17. Current control electrical parameters

Test condition

HILOAD_x = 0, Design info, not tested

HILOAD_x = 0, Design info, not tested

HILOAD_x = 0, Design info, not tested

HILOAD_x = 0, 0A ≤ Ireg ≤ 0.5A

(1)

HILOAD_x = 0, 0.5A < Ireg ≤ 1.5A

(1)

HILOAD_x = 1, Design info, not tested

HILOAD_x = 1, Design info, not tested

Min

-1

0

0

0

–

–

-5

Typ

–

–

0.25

–

–

–

–

Max

1.5

1.75

1

2

2.33

–

5

Unit Pin

A LOAD_SOLx

A LOAD_SOLx mA LOAD_SOLx mA LOAD_SOLx

% LOAD_SOLx

A LOAD_SOLx

A LOAD_SOLx

DS12774 - Rev 8 page 32/107

L9305

Valve driver electrical specifications

Symbol

I reg_acc_L

I reg_acc_L

Parameter

Current regulation accuracy

Current regulation accuracy

Test condition

HILOAD_x = 1, 0 A ≤ I reg

≤ 0.3 A (1)

Min

-15

Typ

–

Max

15

Unit Pin mA LOAD_SOLx

I reg_acc

Current regulation accuracy

HILOAD_x = 1, 0.3A ≤ I reg

≤ 0.5A

(1)

HILOAD_x = 1, 0.5 A < I reg

≤ 2 A

°C

(1) .T

j

= -40

HILOAD_x = 1, 0.5 A < I reg

≤ 2 A. T j

= 27 °C

HILOAD_x = 1, 0.5 A < I reg

≤ 1.3A

(1)

°C

.T

j

= 150

HILOAD_x = 1, 1.3 A < I reg

≤ 2 A

(1) .T

j

= 150

°C

-5

-4

-4

-4

-12

–

–

–

–

–

5

4

4

4

12

%

%

LOAD_SOLx

LOAD_SOLx

Current control – Dither parameters

Dth_ampl Dither T step

amplitude

Dth_num Dither T step

number

Tstep Dither T step

duration

Tdither Dither Period

Current control – PWM parameters

T

PWM_range

PWM period range

T

PWM_res

T

PWM_res_2

PWM period resolution

PWM period resolution

T

PWM_min

PWM period meter min value

T

PWM

Guaranteed by scan

Guaranteed by scan

Guaranteed by scan

Guaranteed by scan

Guaranteed by scan, nominal system clock frequency

TPWM < 100 µs, Guaranteed by scan

TPWM < 100 µs, Guaranteed by scan

–

–

0

0

T

PWM

2*T

PWM

50

4.5

9

36.1

15.04

16.67

1. provided configuration parameters and current control settings are able to allow proper regulation.

–

–

255*I reg_res

31

– 64*T

PWM

– 4*31*64*T

PWM mA LOAD_SOLx step LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

–

5

10

40

20470

5.6

11.1

44.1

18.38

µs LOAD_SOLx

µs LOAD_SOLx

µs LOAD_SOLx

µs LOAD_SOLx ms LOAD_SOLx

Table 18. Valve driver on state diagnostics parameters

Symbol

On state diagnostic

I_HS_ovc0

I_HS_ovc1

I_LS_ovc0

I_LS_ovc1

I_HS_ocv_flt

I_LS_ocv_flt

T_SD_accuracy

T_WARN

T_SD

T_SD_deglitch

HS overcurrent

HS overcurrent

LS overcurrent

LS overcurrent

Parameter

HS overcurrent filter time

LS overcurrent filter time

Temperature ADC accuracy

Temperature warning

Temperature shut down

Digital deglitch filter time

T_WARN_deglitch Digital deglitch filter time

VBATP_ov_th1 VBATP over voltage first threshold

VBATP_ov_th1_deglitch VBATP over voltage digital deglitch

Test condition Min Typ Max Unit Pin

OVC_thres_x=0

OVC_thres_x=1

OVC_thres_x=0

OVC_thres_x=1

Guaranteed by scan

–

–

3

4.3

–

3 –

– -3 A LOAD_SOLx

– -4.5

A LOAD_SOLx

– – A LOAD_SOLx

–

5

A

µs

LOAD_SOLx

LOAD_SOLx

Guaranteed by scan 3 – 5 µs LOAD_SOLx

Design info, not tested -10 –

– 175 –

10

185

°C

°C

Tj_SOLx

Tj_SOLx

–

Guaranteed by scan

185 – 200 °C

7.5

10 12.5

µs

Tj_SOLx

Tj_SOLx

Guaranteed by scan

–

Guaranteed by scan

7.5

10 12.5

µs

27 27.8

29

90 – 120

V

µs

Tj_SOLx

VBATP

VBATP

DS12774 - Rev 8 page 33/107

L9305

Valve driver electrical specifications

Symbol

Vclamp

Vclamp_dly

Vclamp_flt

Eclamp

Eclamp

Parameter Test condition Min Typ Max Unit Pin

LOADx clamp voltage VBATP < 27V 32 35 38

LOADx disable delay by clamp activation detection Design info, not tested – – 2

LOADx clamp detection filter time Guaranteed by scan 3.5

5 7

Energy clamp single pulse

Energy clamp single pulse

I load

= 1 A, T j

= 100 °C –

I load

= 1 A, T j

= 175 °C –

–

–

25

18

V

µs

µs mJ mJ

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

LOAD_SOLx

Table 19. Valve driver LS off state diagnostics parameters

Symbol Parameter

Off state diagnostic – LS configuration

VTGND

VTOPEN

Short to GND threshold voltage

Open load threshold voltage

VOUTOPEN Open load voltage

I_LS_THOPEN Open load threshold current

I_LS_PD Diagnostic pull down current

I_LS_PU Diagnostic pull up current td_blank_0 Blank time 0 td_blank_1 Blank time 1 tflt_diagoff Filter time

Minimum OFF time for correct diagnostic (Blank time 0)

Minimum OFF time for correct diagnostic (Blank time 1)

Test condition Min Typ Max Unit Pin

LS mode, driver tristate, diagnostic on

LS mode, driver tristate, diagnostic on

LS mode, driver tristate, diagnostic on

–

–

–

Bit_blank_x = 0, Guaranteed by scan

Bit_blank_x = 1, Guaranteed by scan

Guaranteed by scan

Application note (esd cap < 12 nF, Bit_blank

= 0)

Application note (esd cap < 6 nF, Bit_blank

= 1)

7.58

–

3.83

–

1.9

2.1

2.3

V LOAD_SOLx

2.7

2.9

3.1

V LOAD_SOLx

2.35 2.5 2.65

V LOAD_SOLx

40 60 80 µA LOAD_SOLx

50 70 90 µA LOAD_SOLx

55 75 95 µA LOAD_SOLx

5 – 7.5

ms LOAD_SOLx

2.5

– 3.75 ms LOAD_SOLx

55 – 80 µs LOAD_SOLx ms LOAD_SOLx ms LOAD_SOLx

Table 20. Valve Driver HS Off State Diagnostic Parameters

Symbol Parameter

Off State Diagnostic – HS Configuration

VTVBAT

VTOPEN

Short to battery threshold voltage

Open load threshold voltage

VOUTOPEN Open load voltage

I_HS_THOPEN Open load threshold current

I_HS_PU Diagnostic pull up current

I_HS_PD Diagnostic pull down current td_blank_0 Blank time 0 td_blank_1 Blank time 1 tflt_diagoff Filter time

Minimum OFF time for correct diagnostic (Blank time 0)

Minimum OFF time for correct diagnostic (Blank time 1)

Test condition Min Typ Max Unit Pin

HS mode, driver tristate, diagnostic on

HS mode, driver tristate, diagnostic on

HS mode, driver tristate, diagnostic on

–

–

–

Bit_blank_x = 0, Guaranteed by scan

Bit_blank_x = 1, Guaranteed by scan

Guaranteed by scan

Application note (esd cap < 12nF, Bit_blank

= 0)

Application note (esd cap < 6nF, Bit_blank

= 1)

2.7

2.9

3.1

V LOAD_SOLx

1.9

2.1

2.3

V LOAD_SOLx

2.35 2.5 2.65

V LOAD_SOLx

30 60 90 µA LOAD_SOLx

55 70 95 µA LOAD_SOLx

60 70 100 µA LOAD_SOLx

5 – 7.5

ms LOAD_SOLx

2.5

– 3.75 ms LOAD_SOLx

55 – 80 µs LOAD_SOLx

7.58

–

3.83

– ms LOAD_SOLx ms LOAD_SOLx

DS12774 - Rev 8 page 34/107

7

L9305

High side fail safe pre-driver

High side fail safe pre-driver

For safety purpose the solenoid loads must be connected to battery line through an external fail safe switch driven by L9305: in case of fault the device must be always able to disconnect external fail safe switch to avoid unwanted energization of solenoid loads. The device provides also diagnostic for external switch, by means of

VDS comparator, to detect overcurrent/short conditions and prevent FET from overheating.

In PWSSO36 package, L9305 provides one fail safe pre-driver channel to control an external high side N-channel safety switch. In TQFP48 package, L9305 provides 4 fail safe pre-driver channels to control 4 external high side N-channel safety switches. The pre-driver protects the external N-channel Mosfet by monitoring the drain to source voltage drop across the Mosfet. The threshold for this diagnostic is programmable by the user in the

FSCONF register, bits D[1:0]. To enable the output driver, set bit D[2]=1 in the FSCONF register. Upon enabling the output driver, fault monitoring is masked for a period of T_FS_VDS_blank and filtered for T_FS_VDS_flt.

Should a fault be detected, the VDS fault flag is set in the SERVFLT1 register, bit D[10]. The fault bit is latched and is clear on read. To re-enable the failsafe pre-driver, the fault must be cleared and the enable bit must be set again through the SPI (FSCONF register).

An external microcontroller can inhibit pre-driver activation by means of the EN_DR input pin: if this pin is driven low the failsafe gate is pulled to ground by an internal switch-off path parallel to the digital one. The internal switch off path is triggered also in case of safety relevant internal faults such as stuck of main clock or overvoltage of the logic core supply voltage.

While the device is in either IDLE or RUNNING mode, EN_DR is set high and FS_EN is set high through an

SPI command, the user can set EN_DR low and verify that the fail-safe switch is disabled thru the parallel safety switch off path by reading the PINSTATUS register SAFETY echo (bit D[7]). The user can also verify the EN_DR status reading the PINSTATUS register, bit D[0].

Figure 17. Fail safe concept

VBATP

FS_Dx

VCP

I

BIAS

I

PU

FS_CMD

FS_Gx

VDS_fault

–

+

I

PD

FS_Sx

DS12774 - Rev 8

The Fail Safe pre-driver can be in the following states:

• FS OFF: Device in Idle State. Fail Safe related registers at their default state. Internal reset state

• FS IDLE: Fail safe disabled. Fail safe related registers preserved but Enable Low. Two cases:

– EN_DR low. Echo on SPI

– Error on FS present. Error on SPI and on FAULT pin, if not masked.

GADG2709181321PS page 35/107

L9305

Fail safe predriver diagnostic

• RUNNING: Fail Safe enabled and running with gate status depending on SPI command register value

The package option codification is stored inside NVM and verified at power up, in case the package option will not allow for multiple fail safe pre-drivers the unused drivers will be kept disabled.

In case of CRC fault during NVM download the default configuration with only one pre-driver enabled will be applied.

7.1

7.2

Fail safe predriver diagnostic

The Fail Safe pre-driver has a VDS monitoring that is used to protect the external FET in case of short circuit to ground. Through SPI registers four different VDS thresholds are programmable (FSCONF register, bits D[1:0]).

Once FS_G0 is driven high, after a blanking time (T_FS_VDS_blank) to allow full turn-on of the external FET, the device starts monitoring the falling differential voltage between FS_D0 and FS_S0: if the differential voltage does not drop below the VDS voltage threshold within the over-current filter time (T_FS_VDS_flt), the device disables the Fail Safe pre-driver and sets the VDS fault flag in the SERVFLT1 register, bit D[10].

The fault SPI bit is latched until read; once the fault condition disappears to re-enable the Fail Safe pre-driver, the fault has to be cleared and the enable bit must be set again via SPI. The Fail Safe operation is inhibited until the fault register is cleared.

Fail safe predriver electrical characteristics

4.75≤ VDD ≤ 5.5; 5.5 V ≤ VBATP ≤ 19 V; VBATP - 1 V ≤ FS_Dx ≤ VBATP+1 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noticed. All voltages refer to AGND pin.

Table 21. Fail safe predriver electrical parameters

Symbol

FS_ON

FS_D_Ileak_dis

FS_Dx_Rpd

Parameter

External FET gate driving for

ON state

FS_OFF

External FET gate driving for

OFF state

FS current source capability FS_Isource

FS_Isink

FS_S_Ibias_IDLE

FS current sink capability

FS_S bias current from CP supply in IDLE state

FS_S_Ibias_RUNNING

FS_S bias current from CP supply in RUNNING state

FS_D leakage current with device in IDLE state

FS_Dx resistor toward FS_Sx pin for VDS threshold generation

FS_D_Ileak_idle

FS_D_Ileak_en_on

FS_D_Ileak_en_on

FS_D leakage current in IDLE mode

FS_D leakage current in ON state

FS_D leakage current in ON state

FS_G – FS_S

FS_G – FS_S

Test condition

FS_G = 0 V

FS_G = VBATP

Fail safe Pre-driver enabled, CMD off,

FS_Dx = VBATP = 13V, VDD = 5V

Fail safe Pre-driver enabled, CMD on, VDD

= 5 V, FS_Dx = VBATP = 13 V

Fail safe Pre-driver disabled, FS_Dx =

VBATP = 13 V, FS_Sx = open, VDD = 0 V

Fail safe Pre-driver disabled, FS_Dx =

VBATP = 13 V, FS_Sx = 0 V, VDD = 0V

Fail safe Pre-driver disabled, CMD on,

FS_Dx = VBATP = 13 V, VDD = 5 V

Fail safe Pre-driver enabled, CMD on,

FS_Dx = VBATP = 13 V, VDD = 5 V

Fail safe Pre-driver enabled, CMD off, FS_D

= VBATP = 13 V, VDD = 5 V

Min Typ Max Unit

7 –

–

0.5

1

3 5

10

1

V

V

1.5

mA

7 mA

-450 -400 -200 µA

-300 -200 -100 µA

-1 – 1 µA

50 140 250 kΩ

250 370 500 µA

140 250 340 µA

250 360 550 µA

FS_VDS_00 VDS_threshold_0 FS_PREDRIVER_TH = 00 0.15 0.25 0.35

V

FS_VDS_01

FS_VDS_10

VDS_threshold_1

VDS_threshold_2

FS_PREDRIVER_TH = 01

FS_PREDRIVER_TH = 10

0.4

0.5

0.6

V

0.65 0.75 0.85

V

FS_Sx

FS_Dx

FS_Dx,

FSx

FS_Dx

FS_Dx

FS_Dx

FS_Dx,

FS_Sx

FS_Dx,

FS_Sx

FS_Dx,

FS_Sx

Pin

FS_Gx,

FS_Sx

FS_Gx,

FS_Sx

FS_Gx

FS_Gx

FS_Sx

DS12774 - Rev 8 page 36/107

Symbol

FS_VDS_11

Parameter

VDS_threshold_3

T_FS_VDS_blank VDS blank time

T_FS_VDS_flt VDS filter time

Test condition

FS_PREDRIVER_TH = 11

Guaranteed by scan

EMI filter, guaranteed by design

L9305

Fail safe predriver electrical characteristics

Min Typ Max Unit

0.9

1 1.1

V

90

100

110 120

600 1000

µs ns

Pin

FS_Dx,

FS_Sx

FS_Dx,

FS_Sx

FS_Dx,

FS_Sx

DS12774 - Rev 8 page 37/107

8

L9305

Safety features

Safety features

The L9305 has several integrated features to enable a reliable functional safety system implementation. A complete list of all monitoring and self-test functions is shown in the next table. The following sections detail these features.

Supply monitors

Global functions internal monitors

Solenoid channel internal monitor

Fail safe

Table 22. Safety monitors and self test summary

Function

Vbat

VCP

VDD

GNDA

GNDD

V3V3AN

V3V3Dig

Trimming Data Error

Global Register Error

SPI

SPI

Core Temperature

Oscillator

Oscillator

GND_SOLx

HS (On state)

LS (On State)

LS Clamp, On State (Only in LS conf)

STG, Off State (Only in LS conf)

Open Load, Off State

STB, Off State (Only in HS conf)

ADC Mismatch

EPROM Calibration Data Error

Trim Data Error

RAM Calibration Data Error

Driver Temperature

Driver Status

Solenoid Register Error

Out of regulation

HS/LS compare

Solenoid Driver Control Loop

VDS protection

Primary monitor

OV

UV

OV & UV

LOSS

LOSS

OV & UV

OV & UV

CRC

Mismatch

Timeout n * Timeout Latch

Over Temperature

Diag Clk stuck-at

Clock Mismatch + Main Clk stuck-at

LOSS

OC

OC

OV (dis. for VB > 27V)

ADC Compare

CRC & Data Compare

CRC

CRC

Over Temperature

Command vs. Actual

Mismatch

Logic Bist

OV

Self test

POR

POR

POR

POR

POR

POR

POR

None

None

None

None

None

None

None

POR & On Demand

None

None

None

On Demand Only

On Demand Only

On Demand Only

Channel on Only

None

None

None

None

On Demand Only

None

On Demand Only

Channel on Only

On Demand Only

None

DS12774 - Rev 8 page 38/107

8.1

8.1.1

8.1.2

8.1.3

L9305

Power supply monitoring and diagnostics

Power supply monitoring and diagnostics

VDD over and under voltage diagnostics

The VDD power supply input pin is continuously monitored for over and under voltage conditions by comparing the input voltage with an independent reference. In addition to the static voltage monitoring function, the L9305 includes a self-test to verify the proper operation of the comparator and fault logic thus preventing latent faults from influencing device operation. The self-test is run automatically after a power on reset event. Upon detecting a fault, the corresponding fault bits are set as summarized below.

Register

SERVFLT1

SERVFLT1

SERVFLT2

SERVFLT2

Table 23. VDD Fault Summary

Location

D4

D5

D6

D7

Bit Name

VDD Under Voltage

VDD Over Voltage

VDD UV Self Test

VDD OV Self Test

A VDD under voltage fault will disable all solenoid drivers and the fail-safe pre-driver. The fault is clear on SPI read but solenoid and fail safe operation must be re-enabled through the SPI.

In case of overvoltage on VDD, fault information is available on SPI, but no action is executed on the solenoid drivers and the fail-safe pre-driver. The fault is clear on SPI read.

VBATP supply over voltage

The VBATP power supply input pin is continuously monitored for an over voltage condition by comparing the input voltage with an independent reference. In addition to the static voltage monitoring function, the L9305 includes a self-test to verify the proper operation of the comparator and fault logic thus preventing latent faults from influencing device operation. The self-test is run automatically after a power on reset event. Upon detecting a fault, the corresponding fault bits are set as summarized below.

Register

SERVFLT1

SERVFLT2

Table 24. VBATP Fault Summary

Location

D1

D4

Bit Name

VBATP over voltage

VBATP over voltage self-test

A VBATP over voltage fault will disable all solenoid drivers and the failsafe pre-driver. The fault is clear on SPI read but solenoid and fail safe operation must be re-enabled through the SPI.

VCP supply under voltage

The VCP charge pump power supply is continuously monitored for an under voltage condition by comparing the input voltage with an independent reference. Upon detecting a fault, the corresponding fault bit is set as summarized below.

Register

SERVFLT1

Table 25. Charge pump fault summary

Location

D3

Bit Name

CP under voltage

A VCP under voltage fault will disable all solenoid drivers and the failsafe pre-driver. The fault is cleared on SPI read but solenoid and fail safe operation must be re-enabled through the SPI.

DS12774 - Rev 8 page 39/107

8.1.4

8.1.5

L9305

Power supply monitoring and diagnostics

Bandgap regulators, internal analog and digital supply monitoring

There are two internal bandgap regulators, main and auxiliary and two internal low voltage regulators, V3VA and V3VD. These regulators are monitored for over and under voltage conditions and a fault on any regulator regardless of the type of the result in a Power On Reset (POR). There are no flags dedicated to these fault conditions other than the POR flag. A POR event resets all registers and disables all solenoids and fail safe. The

POR flag is available as shown below.

Register

SERVFLT1

Table 26. POR fault summary

Location

D9

Bit Name

POR Flag

•

•

In addition to the static voltage monitoring function, the L9305 includes a self-test to verify the proper operation of all comparators and fault logic thus preventing latent faults from influencing the device operation. The self-test function verifies the voltage comparison and logic to ensure the entire path is verified. The self-test is run on demand by setting the ODTEST [D0]. The sequence for initiating the self-test and reading the response is shown below:

•

In ODTEST register set bit D[0] = 1

Monitor ODTEST register bit D[0] for test status, 1 = test in process, 0 = test complete.

If ODTEST register bit D[0] = 1 the test has succeeded; if the test fails device executes a POR and the related bit will be set on SPI register.

GND loss detection

GNDA and GNDD are continuously monitored for loss of ground connection. Ground loss comparators and fault logic are monitored for latent faults using a self-test function. The self-test is automatically performed upon a POR event. Should a ground loss or self-test fault be detected, the corresponding fault bits are set and are summarized below.

Register

SERVFLT1

SERVFLT1

SERVFLT2

SERVFLT2

Table 27. GNDA and GNDD fault summary

Location

D15

D14

D2

D3

Bit Name

GNDD Loss

GNDA Loss

GNDA Loss Self Test

GNDD Loss Self Test

A GNDA or GNDD Loss fault will disable all solenoid drivers and the fail-safe pre-driver. The fault is cleared on

SPI read but solenoid and fail-safe operation must be re-enabled through the SPI.

Each solenoid driver channel has a dedicated ground connection, GND_SOL0, GND_SOL1, GND_SOL2 and

GND_SOL3. Should a fault be detected, the faulted channel will be disabled and fault flag set as shown below:

Register

EXCEPTIONS2

Table 28. Solenoid GND fault summary

Location

D3

Bit Name

Ground Loss

•

•

Each solenoid ground connection is continuously monitored for loss of connection. Each loss of ground monitoring circuit also contains a self-test function that must be requested by the user. The sequence for initiating the self-test and reading the response is shown below:

•

For the desired channel, in CONFIGURATION2 register set bit D[0] = 1

Monitor EXCEPTIONS2 register, bit D[5] for test status, 1 = test in process, 0 = test complete.

Read EXCEPTIONS2 register, bit D[3]; 0 = no fault; 1 = fault

DS12774 - Rev 8 page 40/107

L9305

Power supply monitoring and diagnostics

8.1.6

As stated previously, a fault will disable the associated channel and it must be re-enabled by the user. Solenoid ground loss faults do not disable fail safe and are cleared on SPI read.

Power supply monitoring and diagnostics electrical characteristics

4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noted. All voltages refer to

GNDA pin.

Table 29. Power supply monitoring electrical performance

Symbol Parameter Test condition Min Typ Max Unit Pin

VDD_UV

VDD_UV_hyst

VDD_UV_deglitch

VDD_OV

VDD_OV_hyst

VDD_OV_deglitch

VBATP_OV

CP_UV

V3V3A_uv

V3V3A_ov

V3V3D_uv

V3V3D_ov

(1)

VBATP_OV_hyst

VBATP_OV_deglitch

CP_UV_deglitch

V3V3A_uv_hys

V3V3A_ov_hys

V3V3D_uv_hys

VDD under voltage detection

VDD under voltage hysteresis

Digital filter time

–

–

–

Guaranteed by scan

VDD over voltage detection –

VDD over voltage hysteresis –

Guaranteed by scan Digital filter time

VBATP over voltage detection

VBATP over voltage hysteresis

Digital filter time

Charge Pump under voltage detection

Charge Pump Under Voltage

Filter time

Internal Analog supply under voltage monitor

Internal Analog supply under voltage hysteresis

–

Guaranteed by scan

–

Guaranteed by scan

Design info, not tested

–

3.6

VDD_UV+0.1

9

5.5

VDD_OV-0.1

90

36

VBATP_OV-1

90

VBATP+5

9

2.6

–

–

–

–

–

–

–

–

–

–

–

–

3.9

VDD_UV+0.5

12

7

VDD_OV-0.5

120

–

VBATP_OV-3

120

–

12

–

V

V

V

V

µs

V

µs

V

V3V3A_uv +0.1

– V3V3A_uv +0.5

V

µs

V

V

µs

Internal Analog supply over voltage monitor

Internal Analog supply over voltage hysteresis

Internal Digital supply under voltage monitor

Internal Digital supply under voltage hysteresis

Internal Digital supply over voltage monitor

Design info, not tested

–

Design info, not tested

–

Design info, not tested

3.6

V3V3A_ov -0.1

2.6

V3V3D_uv +0.1

3.6

–

–

–

–

–

4.6

V3V3A_ov -0.5

–

V3V3D_uv +0.5

4.6

V

V

V

V

V

VDD

VDD

VDD

VDD

VDD

VDD

VBATP

VBATP

VBATP

CP

CP

V3V3A

V3V3A

V3V3A

V3V3A

V3V3D

V3V3D

V3V3D

V3V3D_ov_hys

GNDA_lost

GNDA_lost_deglitch

Internal Digital supply over voltage hysteresis

Analog ground lost detection

GNDA deglitch

–

Design info, not tested

Guaranteed by scan

GNDD_lost

GNDD_lost_deglitch

GND_SOLx_lost

Digital ground lost detection

GNDD deglitch

Power ground lost detection

GND_SOLx_lost_deglitch Power ground deglitch

Design info, not tested

Guaranteed by scan

Design info, not tested

Guaranteed by scan

V3V3D_ov -0.1

– V3V3D_ov -0.5

V

0.1

14

0.1

14

0.3

35

–

–

–

–

–

–

0.6

22

0.6

22

1

50

V3V3D

V

µs

GNDA

GNDA

V GNDD

µs GNDD

V GND_SOLx

µs GND_SOLx

1. LS clamp circuitry automatically disabled, see Section 6.4.3

DS12774 - Rev 8 page 41/107

8.2

L9305

Main & reference oscillators

Main & reference oscillators

The L9305 has two internal clock oscillators, main and reference. The main clock oscillator provides the timing and control for all device operating functions. The reference clock oscillator provides the monitoring reference to verify the main oscillator. The monitor is able to check if one of the two oscillators is stuck and if there is a strong frequency mismatch between them. In case the main oscillator isn’t toggling or there is a strong frequency mismatch on it, the monitor will generate an asynchronous activation of a safety switch off path to disable the fail-safe pre-driver: this disable condition will last until fault is recovered.

If a stuck fault on diagnostic oscillator is detected, the device keeps working but reports the corresponding fault through SPI Service Fault 2 register.

Basic implementation of clock monitor is shown in the next figure.

Oscillator monitor is able to detect either stuck condition of one of the two clocks or frequency error of one clock respect the other.

Figure 18. Oscillator monitor

Main Oscillator

0

1

Divider

2 nd Oscillator

0

1

Divider

Clock

Checker

Low Frequency

HighFrequency

Stuck

Clock

Checker

Low Frequency

HighFrequency

Stuck

8.2.1

8.3

GADG2709181324PS.png

Main and reference oscillators electrical characteristics

4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noted. All voltages refer to

GNDA pin.

Table 30. Main and reference oscillator safety parameters

Symbol Parameter

OSCMON_timeout Timeout for stuck detection

OSC_freq_error Max tolerable delta between oscillators

Test condition

Guaranteed by scan

Guaranteed by scan

Min Typ Max Unit

– – 60 µs

-15 – 15 %

Safety switch-off path

In case an over voltage condition is detected on either internal analog or digital supply lines a safety switch-off path is triggered in parallel to the main diagnostic functions. The meaning of this safety path is to ensure a safe state for the system even in case the over voltage condition, caused by overshoot, latent fault, etc., will lead to absolute violation for the internal circuitry: in this catastrophic event the functionality of the device cannot be guaranteed so a high voltage protected circuitry is needed to guarantee the switch-off of the external fail safe transistor(s) and disconnect the safety relevant loads from the main supply line. The safety circuitry is placed in an isolated layout area where no top routing is allowed and a safe distance from other circuits is kept to avoid cross-talk.

The safety off-path is triggered by POR event, main oscillator fault and EN_DR pin low voltage too; safety_fault trigger signal is the asynchronous combination of the main oscillator fault, EN_DR monitor and digital supply overvoltage detection, i.e. the faults that cannot be directly managed by the digital core.

DS12774 - Rev 8 page 42/107

8.3.1

8.4

8.4.1

L9305

Valve drivers

An echo of safety off path activation is fed back to the digital core and mapped on the SPI registers: in this way at power up it is always possible to test the safety off path functionality through EN_DR pin actuation.

Safety switch-off path electrical characteristics

4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noted. All voltages refer to

GNDA pin.

Symbol tSAFETYn echo_deglitch

Table 31. Oscillator safety switch-off path parameter

Parameter

Digital deglitch of safetyn echo

Test condition

Guaranteed by scan

Min Typ Max Unit

0.2

– 1 µs

Valve drivers

To verify current control integrity, various diagnostic tests are integrated throughout the control path and are explained in the following sections.

High side – low side current sense compare

Load current is monitored in both the high side and low side solenoid drivers. The current sensing circuits are independent. The current sense output is multiplexed into an analog to digital converter to close the control loop. To verify the correct current sense functionality, an automatic check between the high and low side current measurements can be made. In the Measured H/L Delta Current register is stored the actual difference between the current sensed from HS and LS circuits, this measured delta current value can be read at power-on by the microcontroller and its value can be written into the Base H/L Delta Current Register, in order to compensate known systematic offsets or delta induced by asymmetrical load transient response and to improve check accuracy. Once the device has the Base H/L Delta Current value recorded, it will continuously monitor the high and low side current values and should the difference exceed the Base H/L Current value, the HS/LS compare fault bit is set (EXCEPTIONS2 register, D[1]). The microcontroller may also perform the same test by simply reading the Measured H/L Delta Current value on a continuous basis and check for deviations.

The current step value is 2 mA per bit. The HS/LS compare fault bit, ie D[1] in the EXCEPTIONS2 register is set high in case the measured current delta exceed the value ± (25 mA + 12.5%*Isetpoint). An example waveform is shown below in

Figure 19 .

The current step value is measured and sensed. Delta values are stored in SPI registers with two’s complement format:

MeasuredDeltaCurrent = 2Complement MeasDeltaCurrent 7:0 *2 mA (3)

Figure 19. HS/LS current compare example

PWM

LS HS LS

Delta

LS→HS

HS LS

Current

1.15

1.1

1.05

1

0.95

0.9

0.85

Delta

HS→LS

Delta(I) = average(Delta

LS→HS,

Delta

HS→LS

)

GADG2709181329PS

DS12774 - Rev 8 page 43/107

8.4.2

8.4.3

8.4.4

8.4.5

L9305

Valve drivers

Solenoid current control ADC check

Each solenoid current control channel uses two independent current sense circuits, one for each HS and LS power stage. The current sense outputs are multiplexed into the ADC for digital processing and load current control. Each channel has a dedicated current measurement ADC and a redundant verification ADC. The verification is continuous during run time operation and requires no activation by the user. The comparison is done independently for each channel. Should the comparison check result in a difference of more than

ADC_CHECK, the Solenoid ADC Mismatch Monitor bit, D[4] in the EXCEPTIONS1 register is set high. The fault is cleared upon reading. A simplified block diagram is shown in the figure below.

Valve currents

1

2

N

ADCx

Figure 20. ADC check block diagram

Current digital conversion

Current digital conversion

+ -

+ -

ADCx

+ -

1

2

N

Valve currents

Current comparison

GADG2709181327PS

Digital control loop logic BIST

•

•

Digital control loop logic test verifies the logic controlling solenoid A/D data calibration and the current control loop. The test is performed independently on each channel. This self-test can be activated only if the channel is in tri-state mode as the control loop is disabled during this test. The sequence for initiating the self-test and reading the response is shown below:

In CONFIGURATION1 register, set Solenoid Logic Bist, bit D[10] =1

Test status and results are available in the EXCEPTIONS1 register, bits D[10:9]

Test results are cleared on register read. If test is running and channel is activated, result is unpredictable since

CONFIGURATION1 register becomes write protected and test cannot be put back in IDLE. In this case it is better to de-activate the test before activating the channel.

Calibration data check

Calibration and trimming data are used to compensate solenoid current control and internal reference circuitry.

Data is stored in internal 8K bit NVM made of 256-bit sectors with the following architecture:

Table 32. NVM memory map

256-bit calibration data field

8 bits CRC 120 bits data 120 bits data 8 bits CRC

Upon Power on Reset (POR), the L9305 downloads calibration data from non-volatile memory into the appropriate local registers. During this process, the data is verified using the 8-bit CRC field. If a CRC failure is detected in data corresponding to analog trim data, the CRC error on CSA Compensation data bit, D[14] is set in the EXCEPTIONS 1 fault register. If a failure is detected in data corresponding to ADC compensation, the

CRC error on A2D trimming data bit, D[13] is set in the EXCEPTIONS 1 fault register. In all cases, the register(s) affected by the faulty data are loaded to “0” to avoid unpredictable operation. Registers loaded with “0” due to a

CRC fault will operate uncalibrated thus having reduced performance.

Diagnostic comparators

All solenoid diagnostic comparators (overcurrent, off-state diagnostic, ground loss) have analog self-tests implemented to detect latent faults. The self-test must be enabled by the user with the channel in tri-state. The self-test is independent for each channel. Should the test fail, a diagnostic fault flag is set and is cleared upon reading the register. Should actuation be requested while the self-test is in process, the self-test will be terminated with an error (EXCEPTIONS1 register, bits D[10:9]) and actuation will be permitted.

DS12774 - Rev 8 page 44/107

L9305

Core over temperature

8.4.6

8.4.7

The typical procedure for running the diagnostic comparator self-test is outlined below:

•

•

•

Disable off-state diagnostics, set CONFIGURATION1 register, D[5] = 0

Enable diagnostics self-test, CONFIGURATION2 register, D[1] = 1

Read results in EXCEPTIONS1 register, D[10:9]

PWM check

The L9305 can verify output driver status with respect to the PWM input signal. This function can only be performed when the channel is enabled and controlling load current. Should a mismatch be detected, the PWM

Check Fault, D[12] is set in the EXCEPTIONS1 register.

Valve driver safety electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VSx ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noticed. All voltages refer to

GNDA pin.

Table 33. Valve driver safety parameters

Symbol

Delta_curr_sense

Parameter

Tolerable mismatch between high side and low side current sense

ADC_checkHILOAD=0

Tolerable mismatch between functional and safety ADCs

ADC_checkHILOAD=1

Tolerable mismatch between functional and safety ADCs t_ADC_blank t_BIST t_BIST t_EEPROM

Test condition

Guaranteed by scan, I

0.8 A

Guaranteed by scan

Self test blanking time Guaranteed by scan

Solenoid digital BIST duration Guaranteed by scan

Analog BIST duration

EEPROM download time

Guaranteed by scan

Guaranteed by scan load

= t_PWM_check t_PWM_check

PWM check masking time

PWM check masking time

SR = 00 Guaranteed by scan

SR = 01 Guaranteed by scan t_PWM_check PWM check masking time

SR = 10/11 Guaranteed by scan

PWM_check_deglitch PWM check fault deglitch time Guaranteed by scan

I_safe_pd

Safety switch off pull down current capability

Design info not tested

Vgs_off_safed

Residual voltage at FS_G pins with safe off path active

Design info not tested in production

Min

-15

-32

-42.7

1

–

3

–

0.9

–

13*64/ f

OSCINT

9*64/ f

OSCINT

5*64/ f

OSCINT

0.2

Typ

–

–

–

–

–

–

–

–

–

–

1.7

–

–

Max

15

32

42.7

4

5

1.8

4

14*64/ f

OSCINT

10*64/ f

OSCINT

6*64/ f

OSCINT

1

–

2

Unit

% LOAD_SOLx mA

Pin mA

µs ms ms ms

– LOAD_SOLx

– LOAD_SOLx

– LOAD_SOLx

µs LOAD_SOLx mA FS_Gx

V FS_Gx

8.5

Core over temperature

The device internal temperature is monitored against overheating. If an over temperature event is detected, all solenoid driver outputs are disabled, their enable bit is cleared and their configuration registers are reset, a fault bit cleared on read is set in the SPI registers (Core Over Temperature D[0] bit in SERVFLT1 register). Once the over temperature condition is removed the fault information must be cleared to restart the outputs. Core over temperature is provided with a hysteresis in order to avoid power-on/power-off oscillations when temperature is around over temperature threshold.

DS12774 - Rev 8 page 45/107

8.5.1

8.6

L9305

IC data verification

Core over temperature electrical characteristics

5.5 V ≤ VBATP ≤ 19 V; 5.5 V ≤ VSx ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noticed. All voltages refer to

GNDA pin.

Table 34. Core thermal monitoring electrical performance

Symbol

CORE_ot

Parameter

CORE over temperature shut down threshold

CORE_ot_hyst CORE over temperature hysteresis

CORE_ot_filt Digital deglitch

Test condition

–

Guaranteed by scan

Min Typ Max Unit

175 – 185 °C

4

9

7

10

10

12

°C

µs

IC data verification

All read/write registers are mirrored thus resulting in a main register and a mirror register. The contents of each register’s main and mirror are verified for consistency. Should a data mismatch between a main read/write register and its mirror register occur, an associated fault bit is set as described below :

• A global register mismatch flag (SERVFLT1, D[2]) is associated to the global registers

– SERVENA

– SOLENDR

•

– TIMEOUTSPICFG

– FSCONF

– SERVFLTMSK1

– SERVFLTMSK2

A channel register mismatch flag (EXCEPTIONS2, D[0]) is dedicated to each channel register bank

– CONFIGURATION1

– CONFIGURATION2

– DITHPGM1

– DITHPGM2

– SETPOINT

– CTRLCFG

– KFREQCTRL

– KGAINS

– INTGLIM

– DRVFLTMASK1

– DRVFLTMASK2

– BASEHLDELTACURR

All the flags are cleared-on-read and refer to the entire register bank. No action is taken when a mismatch arises.

Data mismatch flags can also be mapped to FAULTn pin using SERVFLTMSK1, D[2] for global register and

DRVFLTMSK2, D[0] for channel registers. These flags are masked by default and must be enabled by the users as per their system needs.

DS12774 - Rev 8 page 46/107

9

9.1

L9305

SPI

SPI

The SPI interface is used to configure the device, control the outputs and read diagnostic and status registers.

•

•

•

SPI protocol

The SPI protocol is defined by 32-bit frames with 5 bits of CRC (Cyclic Redundancy Check) for transmit and receive. MOSI frame consists of an 8-bit address, 16-bit data, 5-bit CRC field and a one-bit frame counter. MISO frame consists of SPI error and IC status information, address feedback, 16-bit data and 5-bit CRC field. SPI communication uses various safety mechanisms to ensure high safety level coverage as defined in ISO26262 table D.8:

• 5-bit CRC check (Hamming distance of 3 over 26 bits data)

Frame Counter and Address Feedback

Timeout Monitoring

Short and Long Frame Length

All R/W registers are mirrored (i.e., simultaneously written with the same value) and the content of each main register is verified with its related mirror register. Should a mismatch be detected, a fault flag is set. Details of this

safety feature are summarized in Section 8.6 . The SPI frame format is shown in

Figure 21 .

Figure 21. SPI Frame Format

BIT

MOSI

MISO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RW Page Idx 0 cnt Data[n] CRC

E IERR PageFdbk IndxFdbk Data[n-1] CRC

GADG2709181448PS

The protocol implements Out of Frame response meaning the MISO output frame is related to the previous transmitted MOSI frame as shown in

Figure 22 . The First SPI transfer after power on reset will have a fixed MISO

response consisting in the device ID.

Figure 22. Out of frame response

IC Registers

Data[Add_#n]

Frame #n

R

0 0 0

Add_#n

Add_#n-1

0 0 Data_#n = 0x0000

Data_#n-1 crc crc

RW

0 0

Add_#n+1

0 Add_#n

0

Frame #n+1

0 Data_#n+1 = 0xYYYY

Data_#n crc crc

GADG2709181450PS

Upon power on reset, the first SPI Frame will set all SPI fault bits and address bits to “0” and the data field will contain the device ID as shown in

Figure 23 .

DS12774 - Rev 8 page 47/107

DS12774 - Rev 8

L9305

SPI protocol

Figure 23. SPI frame after Power On Reset

IC Registers

Data[Add_#0]

R

0 0

Frame #0

0

Add_#0 0

Add_fdbk = 0x00

0 Data_#0 = 0xYYYY

Data_fdbk = 0x0000 crc crc

RW

0 0 0

Add_#1

Add_#0

0

Frame #n+1

0 Data_#1 = 0xYYYY

Data_#0 crc crc

GADG2709181452PS

Upon reading a register with Clear on Read fields, the related bits will be cleared only when data has been

completely moved on the next SPI access as shown in Figure 24

.

Figure 24. Clear on Read SPI sequence

IC Registers

IC Registers

Data[Add_#n] [uncleared]

Data[Add_#n] [cleared]

Frame #n

R

0 0 0

Add_#n

Add_#n-1

0 0 Data_#n = 0x0000

Data_#n-1 crc crc

RW Add_#n+1

0 0 0 Add_#n

0

Frame #n+1

0 Data_#n+1 = 0xYYYY

Data_#n crc crc

GADG2709181454PS

Upon register write, data is updated after the frame is completely received and no error has been detected (CRC, frame sequence, frame length). On the next SPI access, MISO data field will contain updated data content from the written register as shown in

Figure 25 .

Figure 25. SPI write sequence

IC Registers

Data[Add_#n]

W

0 0 0

Add_#n

Add_#n-1

0

Frame #n

0 Data__#n = 0xABCD

Data_#n-1 crc crc

RW

0 0 0

Add_#n+1

Add_#n

0

Frame #n+1

0 Data_#n+1 = 0xYYYY

Data_#n = ABCD crc crc

GADG2709181455PS

The SPI interface is supplied by VDDIO pin and consists of the following pins and definitions: page 48/107

9.2

9.3

9.4

L9305

CRC

•

•

Input pins:

– CS: Chip Select Active Low

– SCLK: SPI Clock

– MOSI: Master Output Slave Input. Communication path from MCU to the device

Output pins:

– MISO: Master Input Slave Output. Communication path from the device to the MCU

CRC

Received and transmitted data are verified using a 5-bit CRC field. The CRC is calculated from D[31] of the frame to D[5] excluding frame counter bit, D[21]. The CRC field is checked using 5° degree polynomial and is implemented per the following equation: g(x)= x5 + x2 + 1

If a CRC error is detected, the received frame is ignored and the fault is indicated in the next SPI frame.

In the logic block for CRC calculation, internal logic shift register is initialized all ‘1’: user should take this into account when executing hand calculations for CRC check.

In fact, since internal logic shift register is initialized all ‘1’, most significant 5 bits must be complemented, in addition, as already stated, Bit 21 must be removed and Bit 4 to Bit 0 must be removed for CRC calculation.

For example, in order to calculate CRC for data “0x1820080A”, user should consider the following data:

Data = "11100000000000000001000000"; which should be divided by 100101, then “01010” should result as a CRC.

As a double check that the remainder is 0, user has to concatenate the 01010 to the previous data and then divide by 100101, i.e:

Data = "1110000000000000000100000001010"; and divide by 100101, then ‘0’ will be obtained as a remainder.

SPI errors management

If a communication fault is detected, the SPI error bit (MISO[31]: E bit) is set to “1” and the frame is ignored. The

SPI error bit always refers to the previous SPI frame. The next figure shows the SPI frame sequence for faulted communications.

Figure 26. SPI frame with error on previous SPI frame

IC Registers

SPI Fault Flag Register

Data[Add_#n] [not updated]

W

0 0 0

Add_#n

Frame #n with SPI protocol Error

Add_#n-1

0 0 Data__#n = 0xABCD

Data_#n-1 crc crc

Frame #n+1

RW

1 0 0

Add_#n+1 0 1

Comm. Fault Addr

Data_#n+1 = 0xYYYY

SPI Fault Flag Register crc crc

GADG2709181500PS

SPI timeout monitoring function

An internal monitor detects a failure if the period between communications exceeds the SPI Timeout period. This monitoring function detects loss of the communications between the microcontroller and the device.

If no valid frames are received before the Timeout Configuration period elapses, the SPI Timeout flag is set

(SERVFLT1 register, D[6]) and the FAULTn pin is set low if the corresponding fault mask bit is not set.

The Timeout Configuration value is programmable through a 3-bit SPI field (TIMEOUTSPICFG register, D[4:2]) with a default value of 2 ms. The timer is cleared when a valid SPI frame is received.

DS12774 - Rev 8 page 49/107

9.5

L9305

SPI channel exception field

Dec

2

3

4

0

1

5

6

7

Bin

000

001

010

011

100

101

110

111

Table 35. SPI time out values

SPI Time Out

63 x 8 x 2N [µs]

504

1008

2016

4032

8064

16128

32256

64512

Reset latch function can reset the device to IDLE state if a certain number of timeout events occur. Enable of this function (TIMEOUTSPICFG register, D[1:0] ) and the number of timeout events (TIMEOUTSPICFG register,

D[6:5]) is programmed through SPI.

En_Res_Latch[1]

(Reset Latch enable)

0

0

1

1

Table 36. Reset latch enable state

Dis_Res_Latch[0]

(Reset latch disable)

0

1

0

1

Reset Latch

Disabled

Disabled

Enabled

Disabled

Dec

0

1

2

3

Table 37. Time out reset latch counter values

Bin

00

01

10

11

Time Out Reset Latch Counter [2N+1]

2

4

8

16

SPI channel exception field

MISO frame has 2 bits (IERR) reserved for solenoid channel exceptions. MISO[29] is the OR of all the exceptions related to Channel 0 and Channel 1, while MISO[30] is the OR of all the exceptions related to Channel 2 and

Channel 3.

MISO[29] = (Ch0.Exception1&0xF87F) | (Ch1.Exception1&0xF87F) | Ch0.Exception2 | Ch1.Exception2

MISO[30] = (Ch2.Exception1&0xF87F) | (Ch3.Exception1&0xF87F) | Ch2.Exception2 | Ch3.Exception2

In this way, it is always possible to detect a failure happening on solenoid channel during every SPI communication. Details and clearing of the channel exception can be retrieved by reading the dedicated SPI registers.

DS12774 - Rev 8 page 50/107

L9305

SPI electrical specification

9.6

SPI electrical specification

4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; -40 °C ≤ T j

≤ 175 °C unless otherwise noted. All voltages refer to

GNDA pin.

Symbol

SPI_in_low

Parameter

Logic input low detection

SPI_in_high Logic input high detection

SPI_in_hyst Input hysteresis voltage

Table 38. SPI electrical parameters

Test condition

–

–

–

SPI_in_pd

SPI_in_pu

Internal pull down resistance

Internal pull up resistance

VIN < 2.5 V

VIN < 2.5 V

MISO_Ileak Leakage current in tri-state condition –

MISO_low

MISO_high

MISO_trise

MISO_tfall fclk

Logic low level

Logic high level

MISO rise time

MISO fall time

Transfer Frequency tpcld+tsdo_trans Propagation delay

I sink

= 1 mA

I source

= 1 mA

C load

= 200 pF

C load

= 200 pF

Design info 50% duty cycle, not

tested (1)

SCLK to data at SDO is valid

C load_max parasitics

= 200 pF inlcuding tcsdv tpchdz tsclch thclcl tsclcl thclch tscld thcld tonNCS tclh tcll

NCS=LOW to data at SDO active

NCS L/H to SDO at high impedance

SCLK before NCS low

C load_max

= 200 pF inlcuding parasitics

C load_max

= 200 pF inlcuding parasitics

Design info, not tested

SCLK change L/H after NCS=LOW Design info, not tested

SCLK low before NCS high

SCLK high after NCS high

SDI input setup time

SDI input hold time

Design info, not tested

Design info, not tested

Design info, not tested

Design info, not tested

NCS min. high time

Minimum Time SCLK=HIGH

Minimum Time SCLK=LOW

Design info, not tested

Design info, not tested

Design info, not tested

–

–

–

50

130

50

50

20

–

650

45

45

Min

–

1.75

0.1

–

Typ Max Unit

–

–

–

0.75

–

–

V

V

V

– – 0.4

V

VDDIO-0.4

– – V

–

–

20

40

–

40 80 kΩ

90 180 kΩ

– 10 µA

–

–

–

50

50 ns ns

8 MHz

Pin

CS, MOSI,

SCLK

CS, MOSI,

SCLK

CS, MOSI,

SCLK

MOSI, SCLK

CS

MISO

MISO

MISO

MISO

MISO

SCLK, MOSI,

MISO

– 100 ns

– 200 ns

– 200 ns

–

–

–

–

–

–

–

–

–

–

– ns ns ns ns

– – ns

– 20 ns

–

–

– ns ns ns

SCLK, MISO

CS, MISO

CS, MISO

Cin Input pin capacitance Design info, not tested – – 30 pF

CS, SCLK

CS, SCLK

CS, SCLK

CS, SCLK

MOSI

MOSI

CS

SCLK

SCLK

MOSI, CS,

SCLK

Cout_hiz

MISO output pin capacitance in tristate

Design info, not tested –

1. SPI max frequency may be less depending on the total capacitive load and MCU timing requirements

– 50 pF MISO

DS12774 - Rev 8 page 51/107

9.7

9.8

L9305

SPI registers map table

Figure 27. SPI timings, thresholds 20% to 80% and viceversa

CSN

t sclch t hclcl t clh t cll t sclcl t hclch

SCLK

SDO

t csdv t pcld t

SDO-trans

MSB

t scld t hcld

MSB

t pchdz

LSB

SDI LSB

GADG2609181548PS

SPI registers map table

SPI frame has an 8-bit address field and 16-bit data field, then the available address space consists of up to

256 different registers. Taking into account the logical and physical partition of the functions to be configured and monitored by SPI interface, the address space has been divided in pages of 32 addresses each.

The table below shows the SPI page vs. macro function distribution.

Page ID[binary]

100

101

110

111

000

001

010

011

Table 39. SPI page address mapping

Macro Function

Solenoid Channel 0

Solenoid Channel 1

Solenoid Channel 2

Solenoid Channel 3 unused unused

Global

Fault and Test

Address Space Name

Channel_0_BaseAddress

Channel_1_BaseAddress

Channel_2_BaseAddress

Channel_3_BaseAddress

---

---

Global_BaseAddress

Fault_Test_BaseAddress

SPI Base Address

[hex]

0x00

0x20

0x40

0x60

0x80

0xA0

0xC0

0xE0

[binary]

0000 0000

0010 0000

0100 0000

0110 0000

1000 0000

1010 0000

1100 0000

1110 0000

Global page

Global page contains general control/monitor registers.

Idx [hex]

0x00

0x01

0x02

0x03

0x1F

Table 40. SPI global page register address mapping

Register

Service enable

Solenoid drivers enable

Timeout SPI configuration

Fail safe pre-driver configuration

Chip ID

DS12774 - Rev 8 page 52/107

L9305

Global page

SERVENA

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Service enable

1 0

RW RW R RW RW

Address:

Type:

Reset:

Description:

Global Base Address + 0x00

RW

0x0000

General SERVICE Enable bits

[15] Parallel mode selection for ch2-ch3

[14] Parallel mode selection for ch0-ch1

[13:10] Unused

[9] RAM retrigger

1: Download calibration data from EEPROM.

0: Download complete or inactive

[8] Spread Spectrum Disable:

0: Main Clock Spread Spectrum Enabled

1: Main Clock Spread Spectrum Disabled

[7:1] Unused

[0] Stagger Enable:

1: Stagger Enabled.

0: Stagger Disabled.

Valid only when channel is in Fixed Frequency mode

R RW

DS12774 - Rev 8 page 53/107

L9305

Global page

SOLENDR

15 14 13 12 11 10 9 8 7 6 5 4 3

Solenoid drivers enable

2 1 0

R RW

Address:

Type:

Reset:

Description:

Global Base Address + 0x01

RW

0x0055

Solenoid Driver Configuration

[15:8] Unused

[7:6] Solenoid Driver State, Channel 3

00: Driver Off, OFF State Diagnostics disabled and masked

01 : Driver tristate. OFF DIAG depending on bit on config reg

10: Drives on in PWM. OFF DIAG off and masked

11: Drives on in full-on. OFF DIAG off and masked

[5:4] Solenoid Driver State, Channel 2

00: Driver Off, OFF State Diagnostics disabled and masked

01 : Drives tristate. OFF DIAG depending on bit on config reg

10: Drives on in PWM. OFF DIAG off and masked

11: Drives on in full-on. OFF DIAG off and masked

[3:2] Solenoid Driver State, Channel 1

00: Driver Off, OFF State Diagnostics disabled and masked

01 : Drives tristate. OFF DIAG depending on bit on config reg

10: Drives on in PWM. OFF DIAG off and masked

11: Drives on in full-on. OFF DIAG off and masked

[1:0] Solenoid Driver State, Channel 0

00: Driver Off, OFF State Diagnostics disabled and masked

01: Drives tristate. OFF DIAG depending on bit on config reg

10: Drives on in PWM. OFF DIAG off and masked

11: Drives on in full-on. OFF DIAG off and masked

RW RW RW

DS12774 - Rev 8 page 54/107

L9305

Global page

TIMEOUTSPICFG

15 14 13 12 11 10 9 8 7 6 5 4 3

Timeout SPI configuration

2 1 0

R RW RW RW RW

Address:

Type:

Reset:

Description:

Global Base Address + 0x02

RW

0x0028

SPI TIMEOUT Configuration Register

[15:7] Unused

[6:5] Number of SPI timeout events to force an internal reset

Timeout NR Reset [1:0]; Calculated as 2^(N+1) (e.g., default N= "01", Timeout Events = 4)

[4:2] Maximum time between valid SPI frames before SPI time-out fault flag is set.Timeout Configuration [2:0]: Calculated as follows:

504 x 2N [µs] (e.g., default N=B“010” means 2016 [µs])

[1] Enable Reset Latch - En_Res_Latch[1]:

0: Reset Latch Disabled

1: Reset Latch Enabled

[0] Disable Reset Latch - Dis_Res_Latch[0]

0: Reset Latch Enabled

1: Reset Latch Disabled

DS12774 - Rev 8 page 55/107

L9305

Global page

FSCONF

15 14 13 12 11 10 9 8 7 6 5 4

Fail safe pre-driver configuration

3 2 1 0

R RW RW RW

Address:

Type:

Reset:

Description:

Global Base Address + 0x03

RW

0x0000

Fail Safe Configuration and Enable

[15:12] Unused

[11] FS3 Predriver Enable – FS_3_EN (only TQFP48)

0: Fail Safe Predriver Disabled

1: Fail Safe Predriver Enabled

[10:9] FS3 Predriver Fault Threshold (only TQFP48)

00: 0.25V VDS Threshold

01: 0.5V VDS Threshold

10: 0.75V VDS Threshold

11: 1.0V VDS Threshold

[8] FS2 Predriver Enable – FS_2_EN (only TQFP48)

0: Fail Safe Predriver Disabled

1: Fail Safe Predriver Enabled

[7:6] FS2 Predriver Fault Threshold (only TQFP48)

00: 0.25V VDS Threshold

01: 0.5V VDS Threshold

10: 0.75V VDS Threshold

11: 1.0V VDS Threshold

RW RW RW RW RW

DS12774 - Rev 8 page 56/107

[5] FS1 Predriver Enable – FS_1_EN (only TQFP48)

0: Fail Safe Predriver Disabled

1: Fail Safe Predriver Enabled

[4:3] FS1 Predriver Fault Threshold (only TQFP48)

00: 0.25V VDS Threshold

01: 0.5V VDS Threshold

10: 0.75V VDS Threshold

11: 1.0V VDS Threshold

[2] FS/FS0 Predriver Enable – FS_EN/FS_0_EN

0: Fail Safe Predriver Disabled

1: Fail Safe Predriver Enabled

[1:0] FS/FS0 Predriver Fault Threshold

00: 0.25V VDS Threshold

01: 0.5V VDS Threshold

10: 0.75V VDS Threshold

11: 1.0V VDS Threshold

L9305

Global page

DS12774 - Rev 8 page 57/107

L9305

Global page

CHIPID

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Chip ID

0

Address:

Type:

Description:

Global Base Address + 0x1F

Read Only

Chip Identification Information

Note:

Register Bit Field name/description

[15:7] Unused

[6] Reserved

[5:3] CHIP ID Version

[2:0] CHIP ID SubVersion

Reserved bit [6] should not be used by customer.

Default values

All "0"

0

001

011

Type

Read

Read

Read

Read

DS12774 - Rev 8 page 58/107

9.9

L9305

Fault and test page summary

Fault and test page summary

Idx [hex]

0x00

0x01

0x03

0x04

0x05

0x06

0x1D

Table 41. SPI fault and test page register address mapping

Register

Pin Status

On Demand Tests

Service Fault 1

Service Fault 2

Service Fault Mask 1

Service Fault Mask 2

Communication Faults

DS12774 - Rev 8 page 59/107

L9305

Fault and test page summary

PINSTATUS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Pin status

0

Address:

Type:

Reset:

Description:

Fault Test Base Address + 0x00

R

0b0000000X1XXXXXXX

Echo Input Status & Internal Settings

[15:9] Unused

[8] Busy Echo - Internal signal set high when device is downloading data from EEPROM to various system control registers

[7] SAFETY echo - internal signal set low when the device has disabled the failsafe pre-driver using the parallel shutdown path

[6] FAULTn Pin echo - FAULTn pin status feedback

[5] RES Echo

1: RESn pin is Low

0: RESn pin is high

[4] IN 3 echo: IN3 Pin Status when in HW mode

0: Solenoid Channel 3 Enabled

1: Solenoid Channel 3 Disabled or SW mode selected

[3] IN 2 echo: IN2 Pin Status when in HW mode

0: Solenoid Channel 2 Enabled

1: Solenoid Channel 2 Disabled or SW mode selected

[2] IN 1 echo: IN1 Pin Status when in HW mode

0: Solenoid Channel 1 Enabled

1: Solenoid Channel 1 Disabled or SW mode selected

[1] IN 0 echo: IN0 Pin Status when in HW mode

0: Solenoid Channel 0 Enabled

1: Solenoid Channel 0 Disabled or SW mode selected

[0] EN_DR echo: EN_DR pin status

0: Driver Disabled

1: Driver Enabled

DS12774 - Rev 8 page 60/107

L9305

Fault and test page summary

ODTESTS

15 14 13 12 11 10 9 8 7 6 5 4 3

On demand self tests

2 1 0

R

Address:

Type:

Reset:

Description:

Fault Test Base Address + 0x01

RW

0x0000

Global On Demand Self Tests

[15:1] Unused

[0] V3V3 Self Tests:

1: Start test

0: Test completeShould test fail, POR fault will be latched (SERVFLT1 register).

RW

DS12774 - Rev 8 page 61/107

L9305

Fault and test page summary

SERVFLT1

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Service Fault 1

1 0

RH RH R RH RH R RH RH RH RH RH RH RH RH

Address:

Type:

Type:

Description:

Fault Test Base Address + 0x03

R

0x200

Service Fault register stores Diagnostic flags of enabled services (i.e., Monitors)

[15] Digital Ground Loss (GNDD Loss)

0: No Fault

1: GND_D Loss

Clear on Read

[14] Analog Ground Loss (GNDA Loss)

0: No Fault

1: GND_A Loss

Clear on Read

[13:11] Unused

[10] Fail Safe Pre-driver VDS Fault:

0: No Fault

1: VDS fault detected

Clear on Read

[9] Power On Reset (POR) flag:

0: POR released and flag read

1: POR detected

Clear on Read

[8] EEPROM Trimming data CRC error:

0: No CRC error

1: CRC error

[7] SPI Timeout Latch:

0: No fault

1: SPI Communication Timeout Latch Set

DS12774 - Rev 8 page 62/107

DS12774 - Rev 8

L9305

Fault and test page summary

Clear on Read

[6] SPI Timeout:

0: No fault

1: SPI Communication Timeout

Clear on Read

[5] VDD Over Voltage:

0: No Fault

1: Over Voltage Fault

Clear on Read

[4] VDD Under Voltage:

0: No Fault

1: Under Voltage Fault

Clear on Read

[3] Charge Pump Under Voltage:

0: No Fault

1: Under Voltage Fault

Clear on Read

[2] Configuration Register Monitor Solenoid Drivers Enable, Timeout SPI Config, FS Predriver Config

0: No Fault

1: Register Fault

Clear on Read

[1] VBATP Over Voltage:

0: No Fault

1: Over Voltage Fault

Clear on Read

[0] Core Over Temperature:

0: No Fault

1: Thermal Shutdown

Clear on Read page 63/107

L9305

Fault and test page summary

SERVFLT2

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Service Fault 2

1 0

RH R R RH RH R RH RH RH RH RH

Address:

Type:

Reset:

Description:

Fault_Test_BaseAddress + 0x04

R

0x0000

Service Fault register stores Diagnostic flags of enabled services (i.e., Monitors & Self Tests)

[15] Clamp Diode Inhibit Selftest

Clear on Read

[14] Clamp Diode Inhibit Monitor

[13:8] Unused

[7] VDD OV Selftest

0: No Fault

1: Fault Detected

Clear on Read

[6] VDD UV Selftest

0: No Fault

1: Fault Detected

Clear on Read

[5] Unused

[4] VBAT OV Selftest

0: No Fault

1: Fault Detected

Clear on Read

[3] GNDLOSS D Selftest:

0: No Fault

1: Fault Detected

Clear on Read

[2] GNDLOSS A Selftest:

DS12774 - Rev 8 page 64/107

0: No Fault

1: Fault Detected

Clear on Read

[1] Diag Oscillator Stuck-at Monitor:

0: No Fault

1: Fault Detected

Clear on Read

[0] Main Oscillator Monitor:

0: No Fault

1: Fault Detected

Clear on Read

L9305

Fault and test page summary

DS12774 - Rev 8 page 65/107

L9305

Fault and test page summary

SERVFLTMSK1

15 14 13 12 11 10 9 8 7 6 5 4 3

Service Fault Mask 1

2 1 0

RW RW R RW R RW RW RW R RW RW RW RW RW

Address:

Type:

Reset:

Description:

Fault_Test_BaseAddress + 0x05

RW

0xFFFF

Service Fault Mask register allows the user to map specific fault flags to the FAULTn pin. Setting mask bit high disables (masks) fault from setting FAULTn pin.

[15] Digital Ground Loss:

0: Mask Disabled

1: Mask Enabled

[14] Analog Ground Loss:

0: Mask Disabled

1: Mask Enabled

[13:11] Unused

[10] Fail Safe VDS Fault:

0: Mask Disabled

1: Mask Enabled

[9] Unused

[8] EEPROM Trimming data CRC error:

0: Mask Disabled

1: Mask Enabled

[7] SPI Timeout Latch:

0: Mask Disabled

1: Mask Enabled

[6] SPI Timeout:

0: Mask Disabled

1: Mask Enabled

[5] Unused

[4] VDD Under Voltage:

DS12774 - Rev 8 page 66/107

0: Mask Disabled

1: Mask Enabled

[3] CP Under Voltage:

0: Mask Disabled

1: Mask Enabled

[2] Configuration Register

0: Mask Disabled

1: Mask Enabled

[1] VBATP Over Voltage:

0: Mask Disabled

1: Mask Enabled

[0] Core Over Temperature:

0: Mask Disabled

1: Mask Enabled

L9305

Fault and test page summary

DS12774 - Rev 8 page 67/107

L9305

Fault and test page summary

SERVFLTMSK2

15 14 13 12 11 10 9 8 7 6 5 4 3

Service fault mask 2

2 1 0

R RW R RW R RW RW RW RW RW

Address:

Type:

Reset:

Description:

Fault Test Base Address + 0x06

RW

0xFFFF

Service Fault Mask register allows the user to map specific fault flags to the FAULTn pin. Setting mask bit high disables (masks) fault from setting FAULTn pin.

[15] Unused

[14] Clamp Inhibit Monitor

0: Mask Disabled

1: Mask Enabled

[13:8] Unused

[7] SPI Protocol Error

0: Mask Disabled

1: Mask Enabled

[6:5] Unused

[4] IN3

0: Mask Disabled

1: Mask Enabled

[3] IN2

0: Mask Disabled

1: Mask Enabled

[2] IN1

0: Mask Disabled

1: Mask Enabled

[1] IN0

0: Mask Disabled

1: Mask Enabled

[0] EN_DR

0: Mask Disabled

1: Mask Enabled

DS12774 - Rev 8 page 68/107

L9305

Fault and test page summary

COMMUNICATIONFLTS

15 14 13 12 11 10 9 8 7 6 5 4

SPI communications faults

3 2 1 0

Address:

Type:

Reset:

Description:

Fault_Test_BaseAddress + 0x1D

R

0x0000

SPI communication faults monitors

[15:13] Unused

[12] Frame Counter Error Flag

0: No Fault

1: Wrong Counter Value

[11] CRC Error Flag

0: No Fault

1: CRC Check Fault

[10] Short Frame Flag

0: No Fault

1: Frame bits received < 16

[9] Long Frame Flag

0: No Fault

1: Frame bits received > 16

[8:0] Unused

DS12774 - Rev 8 page 69/107

9.10

Idx [hex]

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x14

0x05

0x06

0x07

0x08

0x09

0x00

0x01

0x02

0x03

0x04

Channel page registers

Table 42. SPI channel page register address mapping

Register

Exceptions 1

Exceptions 2

Configuration 1

Configuration 2

Dither Programming 1

Dither Programming 2

Current Set Point

Control Configuration

Frequency Control

Gains Configuration

Integrator Limit

Average Current

PWM Sense

Driver Fault Mask 1

Driver Fault Mask 2

Base H/L Delta Current

Measured H/L Delta Current

Temperature Monitor

Integrator Output

L9305

Channel page registers

DS12774 - Rev 8 page 70/107

L9305

Channel page registers

EXCEPTIONS1

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Exceptions 1

1 0

RH R R RH RH R RH RH RH RH RH RH RH RH

Address:

Reset

Description:

Channel_X_BaseAddress + 0x00

0x0000

Solenoid Driver Fault Status

[15] Thermal Warning (T_WARN):

0: No Fault

1: Thermal Warning Present

Clear on Read

[14] EEPROM CRC Error on CSA Calibration Data:

0: No Fault

1: CRC Error

Read

[13] EEPROM CRC error on A2D trimming bits:

0: No Fault

1: CRC Error

Read

[12] PWM Check Fault (ON State):

0: No Fault

1: Fault

Clear on Read

[11] PWM Check Comp Mismatch (ON State):

0: No Fault

1: Fault

Clear on Read

[10:9] Solenoid Logic BIST Status: (ADC mismatch, out of regulation, Solenoid driver control loop)

00: Idle

DS12774 - Rev 8 page 71/107

DS12774 - Rev 8

01: BIST running

10: BIST passed

11: BIST failed

Read

[8:7] Solenoid Diag Self Test (OFF State):

00: Self Test pass

01: DIAG_LV comparator fail

10: DIAG OL comparator fail

11: Self Test fail

Clear on Read

[6] Open Load (OFF State):

0: No Fault

1: Open load

Clear on Read

[5] Short Detection (OFF State):

0: No Fault

1: Short Detected

Clear on Read

[4] Solenoid ADC Mismatch monitor:

0: No Fault

1: Mismatch Fault Detected

Clear on Read

[3] LS Clamp Active (ON state):

0: No Fault

1: LS Clamp Activated

Clear on Read

[2] HS Over Current (ON State)

0: No Fault

1: HS Over Current

Clear on Read

[1] LS Over Current (ON State)

0: No Fault

1: LS Over Current

Clear on Read

[0] T_SD: (Thermal Shutdown)

0: No Fault

1: Thermal Shutdown Fault

Clear on Read

L9305

Channel page registers page 72/107

L9305

Channel page registers

EXCEPTIONS2

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Exceptions 2

1 0

R

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x01

RH

0x0000

Solenoid Driver Fault Status

[15:6] Unused

[5] GND_SOL Loss Self Test Status

0: Test Complete

1: Test Running

Clear on Read

[4] Out of regulation

0: No Fault

1: Out of Regulation After 8 PWM Cycles

Clear on Read

[3] GND_SOL loss fault

0: No Fault

1: Solenoid Ground Loss Detected

Clear on Read

[2] RAM CRC error

0: No Fault

1: CRC Fault Detected on RAM Read

Clear on Read

[1] HS/LS compare Fault:

0: No Fault

1: Fault Detected

Clear on Read

[0] Configuration Register Monitor:

0: No Fault

DS12774 - Rev 8

RH RH RH RH RH RH page 73/107

1: Fault Detected

Clear on Read

L9305

Channel page registers

DS12774 - Rev 8 page 74/107

L9305

Channel page registers

CONFIGURATION1

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Configuration 1

1 0

R RW RW R RW RW RW RW RW RW R RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x02

RW

0x0000

Configuration Register provides information related to channel configuration

[15] Unused

[14] OFS_CMP_DIS:

0: Current Sense Offset Compensation Active

1: Current Sense Offset Compensation disabled

[13] CALIBRATION_DIS:

0: Digital Current Sense Calibration Active

1: Digital Current Sense Calibration Disabled

[12:11] Unused

[10] Solenoid Logic BIST:

0: Logic BIST Reset

1: Logic BIST Enabled

[9] Td_Blank:

0: Long Blanking Time

1: Short Blanking Time

[8] HILOAD: Current Sense Scale

0: 1.5A Max Current Range

1: 2.0A Max Current Range

[7] Unused

[6] Overcurrent threshold selection:

0: 4A Theshold

1: 5A Threshold

[5] Enable OFF Diagnosis:

RW

DS12774 - Rev 8 page 75/107

0: Disabled (OFF)

1: Enabled

[4] Unused

[3] Solenoid Load Configuration:

0: Low Side

1: High Side

[2] Current Feedback Control Mode:

0: HW Feedback

1: SW Feedback

[1:0] Output Slew Rate:

00: 0.4V/µs

01: 1.0V/µs

10: 4.0V/µs

11: 8.0V/µs

L9305

Channel page registers

DS12774 - Rev 8 page 76/107

L9305

Channel page registers

CONFIGURATION2

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Configuration 2

1 0

R RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x03

RW

0x0000

Configuration Register for channel configuration self-tests. Before restarting any tests, wait for the register to return to

"0"

[15:2] Unused

[1] Solenoid Diag Self Test: Short, Open Load and PWM Check

0: Self Test Disabled

1: Self Test Enabled

[0] GND_SOL loss self test

0: Self TestDisabled

1: Self Test Enabled

DS12774 - Rev 8 page 77/107

L9305

Channel page registers

DITHPGM1

15 14 13 12 11 10 9 8 7 6 5 4 3

Dither programming 1

2 1 0

RW RW RW

Address:

Type:

Reset:

Description:

R

Channel_X_BaseAddress + 0x04

RW

0x0050

Dither Generator Configuration

[15] Dither Enable:

0: Disabled

1: Enabled

[14] DITHER_SYNC_EN:

0: Disabled

1: Enabled

[13] SYNC TYPE:

0: Dither Synchronization at each Dither Step

1: Dither Synchronization at each dither Period

[12:8] Unused

[7:0] Istep: Current step Value

RW

DS12774 - Rev 8 page 78/107

L9305

Channel page registers

DITHPGM2

15 14 13 12 11 10 9 8 7 6 5 4 3

Dither programming 2

2 1 0

R RW R RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x05

RW

0x028A

Dither Generator Configuration

[15:13] Unused

[12:8] Nstep: Number of steps in a quarter of dither period

[7:6] Unused

[5:0] Tstep: Number of PWM cycles for each dither step

SETPOINT

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Current set point

1 0

RW R RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x06

RW

0x0000

Register stores current setpoint code (HW mode current control). Current Control SETPOINT is coded into 13 bits.

Current value depends on HILOAD bit.

[15] Auto Limit: Activates the transient mode on set point change

0: Inactive

1: Active

[14:13] Unused

[12:0] Current Set Point Code

DS12774 - Rev 8 page 79/107

L9305

Channel page registers

CTRLCFG

15 14 13 12 11 10 9 8 7 6 5 4 3

Control configuration

2 1 0

RW R RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x07

RW

0x0000

[15:14] Transition Time: Too long period detection (if the current PWM time exceeds this threshold, the controller enters the transient state):

00: 2.5 * Tpwm

01 : 4.5 * Tpwm

10: 8.5 * Tpwm

11 : 16.5 * Tpwm

[13:12] Unused

[11] HW feedback Frequency Mode:

0: Fixed Frequency

1: Variable Frequency

[10:0] Target PWM Period Code

DS12774 - Rev 8 page 80/107

L9305

Channel page registers

KFREQCTRL

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Frequency control

1 0

Address:

Type:

Reset:

Description:

R RW

Channel_X_BaseAddress + 0x08

RW

0x002F

Register stores KF, FCIL (Variable frequency forward gain: HW mode current control)

RW

[15:6] unused

[5:3] KFI: Integral Gain of Frequency Control Loop

[2:0] FINT_START: Start value for frequency integrator upon exiting transient mode

KGAINS

15 14 13 12 11 10 9 8 7 6 5 4 3

Gains configuration

2 1 0

Address:

Type:

Reset:

Description:

R RW RW

Channel_X_BaseAddress + 0x09

RW

0x0024

Register stores KI (Integral error gain: HW mode current control) and KP (Proportional error gain: HW mode current control).

[15:6] unused

[5:3] KI: Integral Gain of HW current control loop (fixed & variable freq.)

[2:0] KP: Proportional Gain of HW current control loop (fixed freq. only)

DS12774 - Rev 8 page 81/107

L9305

Channel page registers

INTGLIM

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Integrator limit

1 0

RW R RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0A

RW

0x0000

--

[15:14] INT_OUT_SEL:

00: Integrator Low Threshold

01: Integrator High Threshold

10: Integrator Min Level

11: Integrator Max Level

[13:8] Unused

[7:4] NEGINTLIM

[3:0] POSINTLIM

AVGCUR

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Average current

1 0

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0B

R

0x0000

Stores Average Current Code in 1 PWM period

[15:14] Unused

[13:0] AVGCUR: Average current code (signed) in 1 PWM period

DS12774 - Rev 8 page 82/107

L9305

Channel page registers

PWMSENSE

15 14 13 12 11 10 9 8 7 6 5 4 3 2

PWM sense

1 0

RH R

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0C

RH

0x0000

PWM period out of range flag (TMOUT). PWM code: measured effective PWM period

[15] TMOUT

0: No Fault

1: Fault Detected

Clear on Read

[14:0] PWM Code

DS12774 - Rev 8 page 83/107

L9305

Channel page registers

DRVFLTMASK1

15 14 13 12 11 10 9 8 7 6 5 4 3

Driver fault mask 1

2 1 0

RW RW RW RW RW R RW RW RW RW RW RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0D

RW

0xFFFF

Driver Fault Mask register is an active High Mask register for Driver Faults. Setting mask bit disables corresponding fault from generating interrupt on FAULT pin.

[15] E_SOL_TW: Solenoid Driver Thermal Warning

0: NOT Masked

1: MASKED

[14] EEPROM CRC error on CSA Calibration data Mask:

0: NOT Masked

1: MASKED

[13] EEPROM CRC error on A2D trimming bits Mask:

0: NOT Masked

1: MASKED

[12] PWM Check Fault:

0: NOT Masked

1: MASKED

[11] PWM Check Comp Mismatch:

0: NOT Masked

1: MASKED

[10:7] Unused

DS12774 - Rev 8 page 84/107

DS12774 - Rev 8

[6] E_SOL_OL: Open Load Fault Mask

0: NOT Masked

1: MASKED

[5] E_SOL_SHORT: Solenoid Short Fault Mask

0: NOT Masked

1: MASKED

[4] E_SOL_A2D: Solenoid ADC Mismatch Fault Mask

0: NOT Masked

1: MASKED

[3] E_LSCLAMP: Low Side Clamp Active Fault Mask

0: NOT Masked

1: MASKED

[2] E_SOL_HSOVC: High Side Over Current Fault Mask

0: NOT Masked

1: MASKED

[1] E_SOL_LSOVC: Low Side Over Current Fault Mask

0: NOT Masked

1: MASKED

[0] E_SOL_OT: Solenoid Driver Over Temperature Fault Mask

0: NOT Masked

1: MASKED

L9305

Channel page registers page 85/107

L9305

Channel page registers

DRVFLTMASK2

15 14 13 12 11 10 9 8 7 6 5 4 3

Driver fault mask 2

2 1 0

R RW RW RW RW RW

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0E

RW

0xFFFF

Driver Fault Mask register is an active Hi Mask register for Driver Faults. Setting mask bit disables corresponding fault from generating interrupt on FAULT pin

[15:5] unused

[4] Out of regulation

0: NOT Masked

1: MASKED

[3] GND_SOL loss fault

0: NOT Masked

1: MASKED

[2] RAM CRC error

0: NOT Masked

1: MASKED

[1] E_SOL_HS/LS:

0: NOT Masked

1: MASKED

[0] E_CFG_REG_FAIL:

0: NOT Masked

1: MASKED

DS12774 - Rev 8 page 86/107

L9305

Channel page registers

BSHLDELTACURR

15 14 13 12 11 10 9 8 7 6 5 4 3

Base H/L delta current

2 1 0

R

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x0F

RW

0x0000

Base High Side/Low Side Delta Current

[15:8] Unused

[7:0] Base Delta Current: Base High Side/Low Side Delta Current

RW

DS12774 - Rev 8 page 87/107

L9305

Channel page registers

MEASHLDELTACURR

15 14 13 12 11 10 9 8 7 6 5 4 3

Measure H/L delta current

2 1 0

R

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x10

R

0x0000

Measured H/L Delta current

[15:8] Unused

[7:0] Measured Base Delta Current Between High & Low Side

RW

DS12774 - Rev 8 page 88/107

L9305

Channel page registers

TEMPMON

15 14 13 12 11 10 9 8 7 6 5 4 3

Temperature monitor

2 1 0

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x11

R

0x0000

Temperature Monitor

[15:8] Unused

[7:0] Temperature Monitor: Unsigned

DS12774 - Rev 8 page 89/107

L9305

Channel page registers

INTOUT

15 14 13 12 11 10 9 8 7 6 5 4 3 2

Integrator output

1 0

Address:

Type:

Reset:

Description:

Channel_X_BaseAddress + 0x14

R

0x0000

Integrator Output Monitor

[15:0] Integrator Output Monitor: Unsigned

DS12774 - Rev 8 page 90/107

10

10.1

L9305

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package information

Figure 28. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package outline

BOTTOM VIEW

SECTION A-A

NOT TO SCALE

θ2

θ1

θ3

SECTION B-B

NOT TO SCALE

θ

DS12774 - Rev 8

TOP VIEW

GADG3001181123PS page 91/107

DS12774 - Rev 8

L9305

TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package information

Table 43. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package mechanical data

Symbol aaa bbb ccc ddd e

E

E1

E2

E3 c1

D

D1

D2

D3

R1

R2

S

L

L1

N

A1

A2 b b1 c

Ө

Ө1

Ө2

Ө3

A

0.05

0.95

0.17

0.17

0.09

0.09

Min.

0°

0°

11°

11°

3.4

Dimensions

Typ.

3.5°

12°

12°

1.00

0.22

0.20

9.00 BSC

7.00 BSC

0.50 BSC

9.00 BSC

7.00 BSC

3.4

0.45

0.60

1.00 REF

48

0.08

0.08

0.20

Tolerance of form and position

0.20

0.20

0.08

0.08

Max.

7°

13°

13°

1.20

0.15

1.05

0.27

0.23

0.20

0.16

5.37

5.37

0.75

0.20

Note

11

11

11

4

2, 5

13

14

15

12

15

9, 11

16

1, 7

4

2, 5

13

14

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.

The top package body size may be smaller than the bottom package size up to 0.15 mm.

3.

Datum A-B and D to be determined at datum plane H.

4.

To be determined at seating datum plane C.

5.

Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25

mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.

6.

Details of pin 1 identifier are optional but must be located within the zone indicated.

7.

All dimensions are in millimeters.

page 92/107

L9305

TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package information

8.

No intrusion allowed inwards the leads.

9.

Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5

mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the number of terminal positions for the specified body size.

DS12774 - Rev 8 page 93/107

10.2

L9305

TQFP48 (7x7x1.0 exposed pad down) footprint

TQFP48 (7x7x1.0 exposed pad down) footprint

Figure 29. TQFP48 (7x7x1.0 exposed pad down) footprint

9.7

48 x 0.35

2.4

B

DS12774 - Rev 8

44 x 0.5

A

Notes:

1) This footprint is able to ensure insulation up to 20 Vrms (according to CEI IEC 664-1)

2) The device must be positioned within 0.02 A B

GADG0810180810PS page 94/107

L9305

TQFP48 marking information

10.3

TQFP48 marking information

Figure 30. TQFP48 marking information

Marking area A

Marking area B

Last two digits

ES: Engineering sample

<blank>: Commercial sample

Pin1 Ref.

TQFP 48 TOP VIEW

(not in scale)

GADG0810181047PS_ES

Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS12774 - Rev 8 page 95/107

10.4

L9305

PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package information

PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package information

Figure 31. PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package outline

Bottom view

D1 ggg M C A-B D ggg

M CA-B D

G3 G3

E2

E4

G3

D3 e

// eee C

A A2

A1

N b ddd M CD

D2

A

D

A

C ccc C

SEATING PLANE

Section A-A

θ1

2x f f f CA-B

H

D

θ1 h

S h

θ2

R1

L1

B (see Section B-B)

R

GAUGE PLANE

L2

B

L

θ index area

(0.25D x 0.75E1)

G1x2

E3 pin 1 indicator

2x aaa CD

Top view

7587131_Rev9_EH

1 2 3

G2

B

A

(see Section A-A)

N/2

E1 E

2x N/2 TIPS bbb C

Section B-B

c

(b)

WITH PLATING b1 c1

BASE METAL

GAPGPS03424

Symbol

Ө

Ө1

Ө2

A

Table 44. PowerSSO-36 (exposed pad down) package mechanical data

Min.

0°

5°

0°

2.15

Dimensions

Typ.

-

-

-

-

Max.

8°

10

-

2.45

Note

DS12774 - Rev 8 page 96/107

DS12774 - Rev 8 aaa bbb ccc ddd eee fff ggg

D1

E2

D1

E2

Symbol h

L

G1

G2

G3

E

E1

E2

E3

E4

R1

R2

S

L1

L2

N c c1

D

D1

D2

D3 e

A1

A2 b b1

L9305

PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package information

Dimensions

6.50

4.10

4.90

4.10

Min.

0.00

2.15

0.18

0.13

0.23

0.20

-

-

Typ.

-

-

-

0.2

-

0.20

10.30 BSC

VARIATION

3.65

4.30

0.50 BSC

-

-

-

-

-

0.30

0.55

10.30 BSC

7.50 BSC

VARIATION

2.30

2.90

1.20

1.00

0.80

-

0.70

1.40 REF

0.20 BSC

36

0.30

0.20

-

-

0.25

-

Tolerance of form and position

0.20

0.20

0.08

0.08

0.10

0.20

0.15

VARIATIONS

-

-

-

-

Max.

0.10

2.35

0.32

0.30

0.32

0.30

-

-

-

-

-

7.10

4.70

5.50

4.70

-

-

-

-

-

0.40

0.85

Note

10

7, 8

7, 8

7

7

3, 4

11

3, 4

11

9

6

1, 2

A

B page 97/107

10.5

L9305

PowerSSO-36 marking information

Symbol

Dimensions

Typ.

-

-

Max.

7.50

5.20

Note

D1

E2

Min.

6.90

4.30

C

Notes:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2.

All dimensions are in millimeters.

3.

Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25

mm” per side D and “0.15 mm” per side E1. D and E1 are Maximum plastic body size dimensions including mold mismatch.

4.

The top package body size may be smaller than the bottom package size.

5.

Datum A-B and D to be determined at datum plane H.

6.

“N” is the max number of terminal positions for the specified body size.

7.

The dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip.

8.

Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in exceed of the “b” dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot.

9.

This Chamfer feature is optional. If it is not present, then a PIN 1 identifier must be located within the index area indicated.

10. A1 is defined as the vertical distance from the seating plane to the lowest point on the package body.

11. Dimension D1 and E2 show the minimum allowed for the optional exposed pad. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D1” and “E2” dimensions for each device application.

PowerSSO-36 marking information

Figure 32. PowerSSO-36 marking information

Marking area

Last two digits

ES: Engineering sample

<blank>: Commercial sample

PowerSSO-36 TOP VIEW

(not in scale)

DS12774 - Rev 8

GAPG2904151300PS_ES page 98/107

L9305

PowerSSO-36 marking information

Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS12774 - Rev 8 page 99/107

L9305

Revision history

Date

12-Dec-2018

29-Mar-2019

17-Jul-2019

12-Feb-2020

06-Jul-2020

17-Dec-2020

11-May-2021

25-Nov-2021

2

3

4

5

6

7

8

Table 45. Document revision history

Version

1

Changes

Initial release.

Updated:

Section Product status / summary

;

Section Features .

The confidentiality level is changed from "Restricted" to "Public".

Updated:

Section

Features and Product summary

;

Section 5.7 GND (GNDD, GNDA, GND_SOLx)

;

Table 4. Device operating temperature

;

Table 33. Valve driver safety parameters .

Updated Table 4. Device operating temperature ;

Minor text changes in Features

.

Updated:

Section 9.8.5 CHIPID

;

Section 9.10.3 CONFIGURATION1 .

Minor text changes in Section 8.4.1 High side – low side current sense compare

.

Minor text changes in Section 6.1.8 Parallel mode

.

Typo corrections.

DS12774 - Rev 8 page 100/107

L9305

Contents

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3 Product Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.1

Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2

Latchup trials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3

ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.4

Temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Input / Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1

Reset (RESn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2

Enable (EN_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3

Channel inputs (INx/NDISx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.4

Fault (FAULTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.5

SPI communications (CS, SCLK, MOSI & MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.6

Input / output electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

Battery supply (VBATP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3

Load supplies (VSOL1, VSOL2, VSOL3 & VSOL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.4

Analog and digital supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5

I/O supply (VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.6

Power-On reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.7

GND (GNDD, GNDA, GND_SOLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.8

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.9

Startup & power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.10

Power supply electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Current control drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.1

Hardware current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1.1

6.1.2

Current set point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PWM switching period programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DS12774 - Rev 8 page 101/107

L9305

Contents

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

6.1.8

6.1.9

Current control loop configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fixed frequency control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Variable frequency control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chopper offset compensation of current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 24

Staggered channel activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Dither programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1.10

Dither synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2

Software current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3

Solenoid current control feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3.1

6.3.2

6.3.3

6.3.4

Average current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Integrator feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Solenoid PWM period feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Out of regulation flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4

Solenoid driver and load diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4.1

6.4.2

6.4.3

6.4.4

Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Supply disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Off state solenoid diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5

Valve driver electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 High side fail safe pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

7.1

Fail safe predriver diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2

Fail safe predriver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 Safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

8.1

Power supply monitoring and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

VDD over and under voltage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

VBATP supply over voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

VCP supply under voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Bandgap regulators, internal analog and digital supply monitoring . . . . . . . . . . . . . . . . . . 40

GND loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Power supply monitoring and diagnostics electrical characteristics . . . . . . . . . . . . . . . . . . 41

8.2

Main & reference oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DS12774 - Rev 8 page 102/107

L9305

Contents

8.2.1

Main and reference oscillators electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.3

Safety switch-off path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.3.1

Safety switch-off path electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4

Valve drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

High side – low side current sense compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Solenoid current control ADC check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Digital control loop logic BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Calibration data check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Diagnostic comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PWM check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.4.7

Valve driver safety electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.5

Core over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.5.1

Core over temperature electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.6

IC data verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

9.1

SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.2

CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.3

SPI errors management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.4

SPI timeout monitoring function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.5

SPI channel exception field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.6

SPI electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.7

SPI registers map table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.8

Global page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.9

Fault and test page summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.10

Channel page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

10.1

TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package information . . . . . . . . . . . . . . . . . . . . 91

10.2

TQFP48 (7x7x1.0 exposed pad down) footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

10.3

TQFP48 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.4

PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package information . . . . . . . . 96

10.5

PowerSSO-36 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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Contents

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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List of tables

List of tables

Table 1. PowerSSO-36 and TQFP48 pins list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Device operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Global and external supply fault pin error masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. Solenoid channel and fail safe fault pin error masking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. Digital input/output electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. VBATP electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. Power supply electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Solenoid driver status in hardware mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. PWM period and Frequency Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Solenoid driver channel status in hardware mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13. INx polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 14. LS diagnostic truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. HS diagnostic truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. Valve driver power stage electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17. Current control electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Valve driver on state diagnostics parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 19. Valve driver LS off state diagnostics parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 20. Valve Driver HS Off State Diagnostic Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 21. Fail safe predriver electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 22. Safety monitors and self test summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. VDD Fault Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. VBATP Fault Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Charge pump fault summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 26. POR fault summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27. GNDA and GNDD fault summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 28. Solenoid GND fault summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 29. Power supply monitoring electrical performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 30. Main and reference oscillator safety parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31. Oscillator safety switch-off path parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 32. NVM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 33. Valve driver safety parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 34. Core thermal monitoring electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 35. SPI time out values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 36. Reset latch enable state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 37. Time out reset latch counter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 38. SPI electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 39. SPI page address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 40. SPI global page register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 41. SPI fault and test page register address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 42. SPI channel page register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 43. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 44. PowerSSO-36 (exposed pad down) package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 45. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

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List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. PWSSO36 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. TQFP48 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. PowerSSO-36 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. TQFP48 pinout diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. Charge pump mechanization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Startup procedure example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. HS driver (left) and LS driver (right) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Hardware control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Fixed frequency algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. Fixed frequency signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Variable frequency algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Dither waveforms definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. Software control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. Low side configuration diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. High side configuration diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Fail safe concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18. Oscillator monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19. HS/LS current compare example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 20. ADC check block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. SPI Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22. Out of frame response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 23. SPI frame after Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 24. Clear on Read SPI sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 25. SPI write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 26. SPI frame with error on previous SPI frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 27. SPI timings, thresholds 20% to 80% and viceversa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 28. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 29. TQFP48 (7x7x1.0 exposed pad down) footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 30. TQFP48 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 31. PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package outline . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 32. PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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DS12774 - Rev 8 page 107/107