For complete information on the STM8L101x1 STM8L101x2 STM8L101x3 microcontroller memory, registers and peripherals, please refer to the STM8L reference manual.

The STM8L101x1 STM8L101x2 STM8L101x3devices are members of the STM8L lowpower 8-bit family. They are referred to as low-density devices in the STM8L101x1 STM8L101x2 STM8L101x3 microcontroller family reference manual (RM0013) and in the STM8L Flash programming manual (PM0054).

All devices of the SM8L product line provide the following benefits:

• Reduced system cost

– Up to 8 Kbytes of low-density embedded Flash program memory including up to

2 Kbytes of data EEPROM

– High system integration level with internal clock oscillators and watchdogs.

– Smaller battery and cheaper power supplies.

• Low power consumption and advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency

– Less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode

– Clock gated system and optimized power management

• Short development cycles

– Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.

– Full documentation and a wide choice of development tools

• Product longevity

– Advanced core and peripherals made in a state-of-the art technology

– Product family operating from 1.65 V to 3.6 V supply.

8/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

2 Description

Description

The STM8L101x1 STM8L101x2 STM8L101x3 low-power family features the enhanced

STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming.

All STM8L101xx microcontrollers feature low power low-voltage single-supply program

Flash memory. The 8-Kbyte devices embed data EEPROM.

The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals.

The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.

Features

Flash

RAM

Peripheral functions

Timers

Operating voltage

Operating temperature

Packages

Table 2. STM8L101xx device feature summary

STM8L101xx

2 Kbytes of Flash program memory

4 Kbytes of Flash program memory

8 Kbytes of Flash program memory including up to

2 Kbytes of Data EEPROM

1.5 Kbytes

Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep,

Serial peripheral interface (SPI), Inter-integrated circuit (I²C),

Universal synchronous / asynchronous receiver / transmitter (USART),

2 comparators, Infrared (IR) interface

Two 16-bit timers, one 8-bit timer

1.65 to 3.6 V

UFQFPN20 3x3

-40 to +85 °C

UFQFPN28 4x 4

UFQFPN20 3x3

TSSOP20 4.4 x 6.4

-40 to +85 °C or

-40 to +125 °C

UFQFPN28 4x4

UFQFPN20 3x3

UFQFPN32

LQFP32

DocID15275 Rev 16 9/88

Product overview STM8L101x1 STM8L101x2 STM8L101x3

Figure 1. STM8L101xx device block diagram

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Legend:

AWU: Auto-wakeup unit

Int. RC: internal RC oscillator

I²C: Inter-integrated circuit multimaster interface

POR/PDR: Power on reset / power down reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous / asynchronous receiver / transmitter

IWDG: Independent watchdog

10/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Product overview

The 8-bit STM8 core is designed for code efficiency and performance.

It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.

3.3

Development tools for the STM8 microcontrollers include:

• The STice emulation system offering tracing and code profiling

• The STVD high-level language debugger including C compiler, assembler and integrated development environment

• The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

The STM8L101xx features a nested vectored interrupt controller:

• Nested interrupts with 3 software priority levels

• 26 interrupt vectors with hardware priority

• Up to 29 external interrupt sources on 10 vectors

• Trap and reset interrupts.

DocID15275 Rev 16 11/88

Product overview STM8L101x1 STM8L101x2 STM8L101x3

3.5 Memory

The STM8L101xx devices have the following main features:

• 1.5 Kbytes of RAM

• The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping):

– Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).

– 64 option bytes (one block) of which 5 bytes are already used for the device.

Error correction code is implemented on the EEPROM.

3.6 Low power modes

To minimize power consumption, the product features three low power modes:

• Wait mode: CPU clock stopped, selected peripherals at full clock speed.

• Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit.

• Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. Wakeup is triggered by an external interrupt.

The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog

(IWDG) and Auto-wakeup unit (AWU).

12/88

The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Product overview

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.11 General purpose and basic timers

STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one

8-bit basic timer (TIM4).

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

• Time base generation

• Measuring the pulse lengths of input signals (input capture)

• Generating output waveforms (output compare, PWM and One pulse mode)

• Interrupt capability on various events (capture, compare, overflow, break, trigger)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Beeper

The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.

The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.14 Comparators

The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal

(comparison with ground) or external (comparison to a reference pin voltage).

Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.

DocID15275 Rev 16 13/88

Product overview STM8L101x1 STM8L101x2 STM8L101x3

3.15 USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

3.16 SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.

3.17 I²C

The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I

C bus. It provides multi-master capability, and controls all

I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.

14/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Figure 2. Standard 20-pin UFQFPN package pinout

Pin description

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1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is

available on Port A6 in the Figure 3: 20-pin UFQFPN package pinout for

STM8L101F1U6ATR, STM8L101F2U6ATR and STM8L101F3U6ATR part numbers

DocID15275 Rev 16 15/88

Pin description STM8L101x1 STM8L101x2 STM8L101x3

Figure 3. 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers

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1. Please refer to the warning below.

2. HS corresponds to 20 mA high sink/source capability.

3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR and

STM8L101F3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

16/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Figure 4. 20-pin TSSOP package pinout

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Pin description

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1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Figure 5. Standard 28-pin UFQFPN package pinout

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1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

The COMP_REF pin is not available in this standard 28-pin UFQFPN package. It is

available on Port A6 in the Figure 6: 28-pin UFQFPN package pinout for

STM8L101G3U6ATR and STM8L101G2U6ATR part numbers

DocID15275 Rev 16 17/88

Pin description STM8L101x1 STM8L101x2 STM8L101x3

Figure 6. 28-pin UFQFPN package pinout for STM8L101G3U6ATR and

STM8L101G2U6ATR part numbers

15673$+6

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1. HS corresponds to 20 mA high sink/source capability.

2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

Warning: For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on

32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

18/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Figure 7. 32-pin package pinout

Pin description

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1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package.

2. HS corresponds to 20 mA high sink/source capability.

3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the

STM8L reference manual (RM0013).

DocID15275 Rev 16 19/88

Pin description STM8L101x1 STM8L101x2 STM8L101x3

Type

Table 3. Legend/abbreviation for table 4

I= input, O = output, S = power supply

Level

Input

Output

CM = CMOS

HS = high sink/source (20 mA)

Port and control configuration

Input

Output

Reset state float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

Pin number

Table 4. STM8L101xx pin description

Input Output

Pin name Alternate function

1 1 4 1 1 1 NRST/PA1

(2)

2 2 5 2 2 2 PA2

3 6 3 3 3 PA3

I/O -

I/O

Reset

Port A2

Port A3

PA1

4 4 4 PA4/TIM2_BKIN I/O X X X HS X X Port A4 Timer 2 - break input

5 5 PA5/TIM3_BKIN I/O X X X HS X X Port A5 Timer 3 - break input

3 5 6 PA6/COMP_REF I/O X X X HS X X Port A6

Comparator external reference

4 4 7 6 6 7 V

5 5 8 7 7 8 V

S -

Ground

Power supply

9 8

10 10 11

11 11 12

PD0/TIM3_CH2/

COMP1_CH3

PD1/TIM3_ETR/

COMP1_CH4

PD2/

COMP2_CH3

PD3/

COMP2_CH4

I/O

Port D0

Port D1

Port D2

Port D3

Timer 3 - channel 2 /

Comparator 1 - channel 3

Timer 3 - trigger /

Comparator 1 - channel 4

Comparator 2 channel 3

Comparator 2 channel 4

20/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Pin number

Table 4. STM8L101xx pin description (continued)

Input Output

Pin description

Pin name Alternate function

10 12 12 13

11 13 13 14

PB0/TIM2_CH1/

COMP1_CH1

COMP1_CH2

(3)

PB1/TIM3_CH1/

I/O

(3) X (3)

X HS X X Port B0

X HS X X Port B1

Timer 2 - channel 1 /

Comparator 1 - channel 1

Timer 3 - channel 1 /

Comparator 1 - channel 2

9 9 12 14 14 15

10 10 13 15 15 16

PB2/ TIM2_CH2/

COMP2_CH1/

PB3/TIM2_ETR/

COMP2_CH2

11 11 14 16 16 17 PB4/SPI_NSS

(3)

I/O X X X HS X X Port B2

Timer 2 - channel 2 /

Comparator 2 - channel 1

I/O

(3)

Port B3

Port B4

Timer 2 - trigger /

Comparator 2 - channel 2

SPI master/slave select

I/O X X X HS X X Port B5 SPI clock 12 12 15 17 17 18 PB5/SPI_SCK

13 13 16 18 18 19 PB6/SPI_MOSI

14 14 17 19 19 20 PB7/SPI_MISO

I/O

Port B6

Port B7

I/O X X X HS X X Port D4 -

SPI master out/ slave in

SPI master in/ slave out

20 20 21 PD4

22 PD5 I/O X X X HS X X Port D5 -

23 PD6

24 PD7

15 15 18 21 21 25 PC0/I2C_SDA

16 16 19 22 22 26 PC1/I2C_SCL

I/O X X X HS X X Port D6 -

I/O X X X HS X X Port D7 -

I/O X X T

(4)

Port C0 I2C data

I/O X X T

(4)

Port C1 I2C clock

17 17 20 23 23 27 PC2/USART_RX I/O X X X HS X X Port C2 USART receive

18 18 1 24 24 28 PC3/USART_TX I/O X X X HS X X Port C3 USART transmit

19 19 2 25 25 29

PC4/USART_CK/

CCO

I/O X X X HS X X Port C4

USART synchronous clock / Configurable clock output

DocID15275 Rev 16 21/88

Pin description

Pin number

STM8L101x1 STM8L101x2 STM8L101x3

Table 4. STM8L101xx pin description (continued)

Input Output

Pin name Alternate function

26 26 30 PC5

27 27 31 PC6

20 20 3 28 28 32

PA0

(5)

/SWIM/

BEEP/IR_TIM

(6)

I/O X X X HS X X Port C5 -

I/O X X X HS X X Port C6 -

I/O X X

(5)

X HS

(6)

X X Port A0

SWIM input and output /Beep output/Timer Infrared output

1. Please refer to the warning below.

2. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as a general purpose pin (PA1), it can be configured only as output push-pull, not neither as output opendrain nor as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L reference manual (RM0013).

3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V not implemented).

are

5. The PA0 pin is in input pull-up during the reset phase and after reset release.

6. High sink LED driver capability available on PA0.

Slope control of all GPIO pins can be programmed except true open drain pins and by default is limited to 2 MHz.

Warning: For the STM8L101F1U6ATR, STM8L101F2U6ATR,

STM8L101F3U6ATR, STM8L101G2U6ATR and

STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured.

22/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

5 Memory and register map

Memory and register map

Figure 8. Memory map

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Table 5

lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2. Refer to Table 7

for an overview of hardware register mapping, to Table 6

for details on I/O port hardware registers, and to

Table 8

for information on CPU/SWIM/debug module controller registers.

DocID15275 Rev 16 23/88

Memory and register map STM8L101x1 STM8L101x2 STM8L101x3

Memory area

Table 5. Flash and RAM boundary addresses

Size Start address

RAM

Flash program memory

1.5 Kbytes

2 Kbytes

4 Kbytes

8 Kbytes

0x00 0000

0x00 8000

End address

0x00 05FF

0x00 87FF

0x00 8FFF

0x00 9FFF

Note: 2 Kbytes of Data EEPROM is only available on devices with 8 Kbytes flash program memory.

Address Block

Table 6. I/O Port hardware register map

Register label Register name

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

Port A

Port B

Port C

Port D

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PC_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reset status

0x00

0xxx

0x00

0xxx

0x00

0xxx

0x00

0xxx

0x00

24/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map

Block

Table 7. General hardware register map

Register label Register name Address

0x00 5050

0x00 5051

0x00 5052

0x00 5053

Flash

0x00 5054

0x00 5055 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

0x00 50A6

0x00 50A7

0x00 50A8 to

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2 to

0x00 50BF

0x00 50C0

0x00 50C1 to

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6 to

0x00 50DF

ITC-EXTI

WFE

RST

CLK

FLASH_CR1

FLASH_CR2

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

Flash control register 1

Flash control register 2

Flash Program memory unprotection register

Data EEPROM unprotection register

Flash in-application programming status register

EXTI_CR1

EXTI_CR2

EXTI_CR3

EXTI_SR1

EXTI_SR2

EXTI_CONF

WFE_CR1

WFE_CR2

RST_CR

RST_SR

CLK_CKDIVR

CLK_PCKENR

CLK_CCOR

Reserved area (75 bytes)

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register

WFE control register 1

WFE control register 2

Reserved area (8 bytes)

Reset control register

Reset status register

Reserved area (14 bytes)

Clock divider register

Reserved area (2 bytes)

Peripheral clock gating register

Reserved (1 byte)

Configurable clock control register

Reserved area (25 bytes)

Reset status

0x00

0xX0

0x00

0x01

0x03

0x00

DocID15275 Rev 16 25/88

Memory and register map STM8L101x1 STM8L101x2 STM8L101x3

Address

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 51FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205 to

0x00 520F

0x00 5210

Table 7. General hardware register map (continued)

Block Register label Register name

IWDG

IWDG_KR

IWDG_PR

IWDG_RLR

IWDG key register

IWDG prescaler register

IWDG reload register

AWU

BEEP

AWU_CSR

AWU_APR

AWU_TBR

BEEP_CSR

Reserved area (13 bytes)

AWU control/status register

AWU asynchronous prescaler buffer register

AWU timebase selection register

BEEP control/status register

Reserved area (268 bytes)

SPI

I2C

SPI_CR1

SPI_CR2

SPI_ICR

SPI_SR

SPI_DR

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

SPI data register

I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL

I2C_CCRH

I2C_TRISER

Reserved area (11 bytes)

I2C control register 1

I2C control register 2

I2C frequency register

I2C own address register low

I2C own address register high

Reserved area (1 byte)

I2C data register

I2C status register 1

I2C status register 2

I2C status register 3

I2C interrupt control register

I2C Clock control register low

I2C Clock control register high

I2C TRISE register

Reset status

0xXX

0x00

0xFF

0x00

0x3F

0x00

0x1F

0x00

0x02

0x00

0x02

0x00

26/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map

Table 7. General hardware register map (continued)

Block Register label Register name Address

0x00 521E to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238 to

0x00 524F

USART

USART_SR

USART_DR

USART_BRR1

USART_BRR2

USART_CR1

USART_CR2

USART_CR3

USART_CR4

Reserved area (18 bytes)

USART status register

USART data register

USART baud rate register 1

USART baud rate register 2

USART control register 1

USART control register 2

USART control register 3

USART control register 4

Reserved area (18 bytes)

Reset status

0xC0

0xXX

0x00

DocID15275 Rev 16 27/88

Memory and register map STM8L101x1 STM8L101x2 STM8L101x3

Address

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266 to

0x00 527F

Table 7. General hardware register map (continued)

Block Register label Register name

TIM2

TIM2_CR1

TIM2_CR2

TIM2_SMCR

TIM2_ETR

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2_OISR

TIM2 control register 1

TIM2 control register 2

TIM2 slave mode control register

TIM2 external trigger register

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

TIM2 output idle state register

Reset status

0x00

0xFF

0x00

Reserved area (26 bytes)

28/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map

Address

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296 to

0x00 52DF

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

0x00 528F

0x00 5290

Table 7. General hardware register map (continued)

Block Register label Register name

TIM3

TIM3_CR1

TIM3_CR2

TIM3_SMCR

TIM3_ETR

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3_EGR

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3_OISR

TIM3 control register 1

TIM3 control register 2

TIM3 slave mode control register

TIM3 external trigger register

TIM3 interrupt enable register

TIM3 status register 1

TIM3 status register 2

TIM3 event generation register

TIM3 capture/compare mode register 1

TIM3 capture/compare mode register 2

TIM3 capture/compare enable register 1

TIM3 counter high

TIM3 counter low

TIM3 prescaler register

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

TIM3 capture/compare register 2 high

TIM3 capture/compare register 2 low

TIM3 break register

TIM3 output idle state register

Reset status

0x00

0xFF

0x00

TIM4

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_IER

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

Reserved area (74 bytes)

TIM4 control register 1

TIM4 control register 2

TIM4 Slave mode control register

TIM4 interrupt enable register

TIM4 Status register 1

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register low

0x00

0xFF

DocID15275 Rev 16 29/88

Memory and register map STM8L101x1 STM8L101x2 STM8L101x3

Table 7. General hardware register map (continued)

Block Register label Register name Address

0x00 52E9 to

0x00 52FE

0x00 52FF

0x00 5300

0x00 5301

0x00 5302

IRTIM

COMP

IR_CR

COMP_CR

COMP_CSR

COMP_CCS

Reserved area (23 bytes)

Infra-red control register

Comparator control register

Comparator status register

Comparator channel selection register

Reset status

0x00

Address

Table 8. CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

0x00 7F60

0x00 7F61

0x00 7F6F

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

CPU

CFG

ITC-SPR

(1)

PCE

PCH

PCL

SPH

SPL

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

CFG_GCR Global configuration register

Reserved area (15 bytes)

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

0xFF

Reset status

0x00

0x80

0x00

0x05

0xFF

0x28

0x00

30/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map

Table 8. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register label Register name

Reset status

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

SWIM

SWIM_CSR

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

Breakpoint 1 register extended byte

Breakpoint 1 register high byte

Breakpoint 1 register low byte

Breakpoint 2 register extended byte

Breakpoint 2 register high byte

Breakpoint 2 register low byte

Debug module control register 1

Debug module control register 2

Debug module control/status register 1

Debug module control/status register 2

Enable function register

0x00

1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list

of external interrupt registers.

0xFF

0x00

0x10

0x00

0xFF

DocID15275 Rev 16 31/88

Interrupt vector mapping

6 Interrupt vector mapping

STM8L101x1 STM8L101x2 STM8L101x3

23-

2-3

IRQ

No.

Source block

Description

RESET Reset

TRAP Software interrupt

Reserved

FLASH EOP/WR_PG_DIS

Reserved

AWU Auto wakeup from Halt

Reserved

EXTIB External interrupt port B

EXTID External interrupt port D

EXTI0 External interrupt 0

EXTI1 External interrupt 1

EXTI2 External interrupt 2

EXTI3 External interrupt 3

EXTI4 External interrupt 4

EXTI5 External interrupt 5

EXTI6 External interrupt 6

EXTI7 External interrupt 7

Reserved

Table 9. Interrupt mapping

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Yes

Wakeup from Wait

(WFE mode)

Yes

(1)

Yes

Yes (1)

Yes

Reserved

COMP Comparators

TIM2

Update

/Overflow/Trigger/Break

TIM2 Capture/Compare

TIM3 Update /Overflow/Break

TIM3 Capture/Compare

Reserved

TIM4 Update /Trigger

SPI End of Transfer

Yes

(1)

Yes

(1)

Yes (1)

Yes

(1)

Yes

(1)

Vector address

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

-0x00 8017

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

-0x00 804F

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8060

0x00 8064-

0x00 806B

0x00 806C

0x00 8070

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STM8L101x1 STM8L101x2 STM8L101x3 Interrupt vector mapping

IRQ

No.

Source block

Table 9. Interrupt mapping (continued)

Description

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Wakeup from Wait

(WFE mode)

Vector address

USART

Transmission complete/transmit data register empty

Receive Register DATA

FULL/overrun/idle line detected/parity error

I2C interrupt

(2)

Yes

(1)

0x00 8074

0x00 8078

29 I2C Yes Yes Yes Yes

(1)

0x00 807C

1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to Section Wait for event (WFE) mode in the RM0013 reference manual.

2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

DocID15275 Rev 16 33/88

Option bytes STM8L101x1 STM8L101x2 STM8L101x3

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory.

All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM

address. See Table 10

for details on option byte addresses.

Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug

Manual (UM0470) for information on SWIM programming procedures.

Table 10. Option bytes

Option bits

6 5 4 3 2 1 0

Factory default setting

Addr.

Option name

Option byte

No.

0x4800

0x4807

0x4802

0x4803

0x4808

Read-out protection

(ROP)

UBC (User

Boot code size)

DATASIZE

Independent watchdog option

OPT1

OPT2

OPT3

OPT4

[1:0]

ROP[7:0]

Must be programmed to 0x00

UBC[7:0]

DATASIZE[7:0]

Reserved

IWDG

_HALT

IWDG

_HW

0x00

OPT1

OPT2

Table 11. Option byte description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Refer to Read-out protection section in the STM8L reference manual

(RM0013) for details.

UBC[7:0] Size of the user boot code area

0x00: no UBC

0x01-0x02: UBC contains only the interrupt vectors.

0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected

...

0x7F - Page 0 to 126 reserved for UBC, memory is write protected

Refer to User boot area (UBC) section in the STM8L reference manual

(RM0013) for more details.

UBC[7] is forced to 0 internally by HW.

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STM8L101x1 STM8L101x2 STM8L101x3 Option bytes

OPT3

OPT4

Table 11. Option byte description (continued)

DATASIZE[7:0] Size of the data EEPROM area

0x00: no data EEPROM area

(1)

0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF

(1)

0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF

(1)

...

(1)

0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF

(1)

Refer to Data EEPROM (DATA) section in the STM8L reference manual

(RM0013) for more details.

DATASIZE[7:6] are forced to 0 internal by HW.

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices.

Caution: After a device reset, read access to the program memory is not guaranteed if address

0x4807 is not programmed to 0x00.

DocID15275 Rev 16 35/88

Unique ID STM8L101x1 STM8L101x2 STM8L101x3

STM8L101xx devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

• For use as serial numbers

• For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory

• To activate secure boot processes.

0x4925

0x4926

0x4927

0x4928

0x4929

0x492A

0x492B

0x492C

0x492D

0x492E

0x492F

0x4930

Address

Content description

Table 12. Unique ID registers (96 bits)

Unique ID bits

7 6 5 4 3

X co-ordinate on the wafer

Y co-ordinate on the wafer

Wafer number

Lot number

U_ID[7:0]

U_ID[15:8]

U_ID[23:16]

U_ID[31:24]

U_ID[39:32]

U_ID[47:40]

U_ID[55:48]

U_ID[63:56]

U_ID[71:64]

U_ID[79:72]

U_ID[87:80]

U_ID[95:88]

2 1 0

36/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

9.1.1

Note:

Unless otherwise specified, all voltages are referred to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

The values given at 85 ° C < T

≤ 125 ° C are only valid for suffix 3 versions.

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

A only as design guidelines and are not tested.

= 25 °C, V

= 3 V. They are given

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 9 .

Figure 9. Pin loading conditions

34-,0).

069

DocID15275 Rev 16 37/88

Electrical parameters

9.1.5 Pin input voltage

STM8L101x1 STM8L101x2 STM8L101x3

The input voltage measurement on a pin of the device is described in Figure 10 .

Figure 10. Pin input voltage

34-,0).

9.2

069

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 13: Voltage characteristics

Table 14: Current characteristics

and

Table 15: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile is compliant with the JEDEC JESD47 qualification standard; extended mission profiles are available on demand.

Symbol

Table 13. Voltage characteristics

Ratings Min Max Unit

- V

External supply voltage

Input voltage on true open drain pins

(PC0 and PC1)

(1)

Input voltage on any other pin

(2)

-0.3

4.0

+ 4.0

ESD

Electrostatic discharge voltage

-0.3

4.0

see Absolute maximum ratings (electrical sensitivity) on page 61

1. Positive injection is not possible on these I/Os. V maximum must always be respected. I never be exceeded. A negative injection is induced by V

INJ(PIN)

must

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I injection is induced by V

while a negative injection is induced by V

maximum

value. A positive

38/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Symbol

Table 14. Current characteristics

Ratings Max.

Unit

VDD

VSS

Total current into V

DD power line (source)

Total current out of V

SS ground line (sink)

Output current sunk by IR_TIM pin (with high sink LED driver capability)

Output current sunk by any other I/O and control pin

Output current sourced by any I/Os and control pin

-25 mA

INJ(PIN)

Injected current on true open-drain pins (PC0 and PC1)

(1)

Injected current on any other pin

(2)

Total injected current (sum of all I/O and control pins)

(3)

-5

±5

Σ I

INJ(PIN)

±25

1. Positive injection is not possible on these I/Os. V maximum must always be respected. I never be exceeded. A negative injection is induced by V

INJ(PIN)

must

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I injection is induced by V

while a negative injection is induced by V

maximum

value. A positive

3. When several inputs are submitted to a current injection, the maximum with Σ I

INJ(PIN)

Σ I

INJ(PIN)

maximum current injection on four I/O port pins of the device.

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization

Symbol

STG

Table 15. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to +150

150

Unit

° C

DocID15275 Rev 16 39/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

9.3.1

Subject to general operating conditions for V

and T

General operating conditions

Symbol f

MASTER

(1)

(2)

Table 16. General operating conditions

Parameter

Master clock frequency

Standard operating voltage

Power dissipation at T

A for suffix 6 devices

= 85 °C

Power dissipation at T

A for suffix 3 devices

= 125 °C

Temperature range

Junction temperature range

Conditions

1.65 V ≤ V

< 3.6 V

LQFP32

UFQFPN32

UFQFPN28

TSSOP20

UFQFPN20

LQFP32

UFQFPN32

UFQFPN28

TSSOP20

UFQFPN20

1.65 V ≤ V

< 3.6 V

(6 suffix version)

1.65 V ≤ V

< 3.6 V

(3 suffix version)

-40 °C ≤ T

≤ 85 °C

(6 suffix version)

-40 °C ≤ T

≤

(3 suffix version)

Min

1.65

− 40

- 40

− 40

Max

3.6

288

250

181

196

185

125

105

130

Unit

MHz

V mW

°C

1. f

MASTER

= f

CPU

2. To calculate P

Θ Dmax

) use the formula given in thermal characteristics P

JA in table “Thermal characteristics”

Dmax

=(T

Jmax

-T

)/ Θ

with T

Jmax

in this table and

40/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

9.3.3

Symbol

Table 17. Operating conditions at power-up / power-down

Parameter Conditions Min Typ Max Unit

V t t

VDD

TEMP

POR

(1)(2)

PDR

(1)(2)

rise time rate

Reset release delay V

rising

Power on reset threshold

Power down reset threshold

1.35

1.40

1300

1.65

1.60

(3)

µs/V ms

1. Guaranteed by characterization results.

2. Correct device reset during power on sequence is guaranteed when t

VDD[max]

is respected. External reset

PDR

< V

DD[min]

3. Tested in production.

Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

• All I/O pins in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if explicitly mentioned.

Subject to general operating conditions for V

and T

DocID15275 Rev 16 41/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Table 18. Total current consumption in Run mode (1)

Symbol Parameter Conditions

(2)

Typ

DD (Run)

Supply current in

Run mode

(4) (5)

Code executed from

RAM

Code executed from

Flash f

MASTER

= 2 MHz f

MASTER

= 4 MHz f

MASTER

= 8 MHz f

MASTER

= 16 MHz f

MASTER

= 2 MHz f

MASTER

= 4 MHz f

MASTER

= 8 MHz f

MASTER

= 16 MHz

1. Based on characterization results, unless otherwise specified.

2. All peripherals off, V

from 1.65 V to 3.6 V, HSI internal RC osc., f

CPU

MASTER

3. Maximum values are given for T

= − 40 to 125 °C.

4. CPU executing typical data processing.

5. An approximate value of I

DD(Run)

= f

MASTER

DD(Run)

can be given by the following formula:

x 150 µA/MHz +215 µA.

6. Tested in production.

0.39

0.55

0.90

1.60

0.55

0.88

1.50

2.70

Max

(3)

0.60

0.70

1.20

2.10

(6)

0.70

1.80

2.50

3.50

Unit mA

Figure 11. I

DD(RUN)

vs. V

DD, f

CPU

= 2 MHz Figure 12. I

DD(RUN)

vs. V

, f

CPU

= 16 MHz

1. Typical current consumption measured with code executed from Flash.

42/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Table 19. Total current consumption in Wait mode (1)

Symbol Parameter Conditions Typ Max (2)

DD (Wait)

Supply current in

Wait mode

CPU not clocked, all peripherals off,

HSI internal RC osc. f

MASTER

= 2 MHz 245 f

MASTER

= 4 MHz 300 f

MASTER

= 8 MHz 380 f

MASTER

= 16 MHz 510

1. Based on characterization results, unless otherwise specified.

2. Maximum values are given for T

= -40 to 125 °C.

400

450

600

800

Unit

µA

Figure 13. I

DD(WAIT)

vs. V

, f

CPU

= 2 MHz Figure 14. I

DD(WAIT)

vs. V

, f

CPU

= 16 MHz

1. Typical current consumption measured with code executed from Flash.

DocID15275 Rev 16 43/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Table 20. Total current consumption and timing in Halt and Active-halt mode at

= 1.65 V to 3.6 V (1)(2)

Symbol Parameter Conditions Typ Max Unit

DD(AH)

DD(WUFAH) t

I t

WU(AH)

(3)

DD(Halt)

DD(WUFH)

WU(Halt)

(3)

Supply current in Active-halt mode

LSI RC osc.

(at 37 kHz)

= -40 °C to 25 °C 0.8

= 55 °C 1

= 85 °C

= 105 °C

1.4

3.2

2.9

2.5

7.5

= 125 °C 5.8

Supply current during wakeup time from Active-halt mode

Wakeup time from Activehalt mode to Run mode

CPU

= 16 MHz

6.5

0.35 1.2

(4)

Supply current in Halt mode

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= 125 °C

0.6

2.5

1.8

1 2.5

(4)

6.5

5.4

(4)

Supply current during wakeup time from Halt mode

2 -

Wakeup time from Halt mode to Run mode f

CPU

= 16 MHz 4 6.5

1. T

= -40 to 125 °C, no floating I/O, unless otherwise specified.

2. Guaranteed by characterization results.

3. Measured from interrupt event to interrupt vector fetch.

To get t

for another CPU frequency use t

(FREQ) = t

(16 MHz) + 1.5 (T

FREQ

-T

16 MHz

4. Tested in production.

μ A

μ A mA

μ s mA

μ s

μ A

Figure 15. Typ. I

DD(Halt)

vs. V

DD,

CPU

= 2 MHz and 16 MHz

44/88

1. Typical current consumption measured with code executed from Flash.

DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

9.3.4

Electrical parameters

Current consumption of on-chip peripherals

Measurement made for f

MASTER

= from 2 MHz to 16 MHz

Table 21. Peripheral current consumption

Symbol Parameter Typ. V

= 3.0 V Unit

DD(TIM2)

DD(TIM3)

TIM2 supply current

(1)

TIM3 supply current

(1)

DD(TIM4)

DD(USART)

TIM4 timer supply current

USART supply current (2)

(1)

µA/MHz

DD(SPI)

DD(I²C1)

SPI supply current

I2C supply current

(2)

DD(COMP)

Comparator supply current

(2)

20 µA

1. Data based on a differential I production.

measurement between all peripherals off and a timer counter running at

16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in

2. Data based on a differential I

measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production.

Clock and timing characteristics

Internal clock sources

Subject to general operating conditions for V

and T

High speed internal RC oscillator (HSI)

Symbol Parameter

Table 22. HSI oscillator characteristics (1)

Conditions f

HSI

ACC

HSI

DD(HSI)

Frequency V

= 3.0 V

= 3.0 V, T

= 25 °C

= 3.0 V, -10 °C ≤ T

A Accuracy of HSI oscillator

(factory calibrated)

= 3.0 V, 0 °C ≤ T

= 3.0 V, -10 °C ≤ T

1.65 V ≤

-40 °C ≤ T

≤

3.6 V,

125 °C

HSI oscillator power consumption

1. V

= 3.0 V, T

= -40 to 125 °C unless otherwise specified.

2. Guaranteed by characterization results.

Min

-4.5

(2)

-1

-2.5

(2)

-4.5

(2)

-1.5

(2)

-2

(2)

Typ Max Unit

(2)

1.5

(2)

MHz

(2)

70 100

(2)

µA

DocID15275 Rev 16 45/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Figure 16. Typical HSI frequency vs. V

Figure 17. Typical HSI accuracy vs. temperature, V

= 3 V

Figure 18. Typical HSI accuracy vs. temperature, V

= 1.65 V to 3.6 V

46/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Low speed internal RC oscillator (LSI)

Symbol

Table 23. LSI oscillator characteristics

(1)

Parameter Conditions Min Typ Max f f

LSI drift(LSI)

Frequency -

LSI oscillator frequency drift (2)

0 °C ≤ T

-12

1. V

= 1.65 V to 3.6 V, T

= -40 to 125 °C unless otherwise specified.

2. For each individual part, this value is the frequency drift from the initial measured frequency .

Figure 19. Typical LSI RC frequency vs. V

Unit kHz

= -40 to 125 °C unless otherwise specified.

Table 24. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

Data retention mode

(1)

Halt mode (or Reset) 1.4

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization results.

Flash memory

Symbol

DD t prog

Table 25. Flash program memory

Parameter Conditions

Operating voltage

(all modes, read/write/erase)

Programming time for 1- or 64-byte (block) erase/write cycles (on programmed byte)

Programming time for 1- to 64-byte (block) write cycles (on erased byte) f

MASTER

= 16 MHz

Min Typ

Max

(1)

Unit

1.65

3.6

V ms ms

DocID15275 Rev 16 47/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Table 25. Flash program memory (continued)

Symbol Parameter Conditions

I prog

Programming/ erasing consumption

=+25 °C, V

= 3.0 V

=+25 °C, V

= 1.8 V t

RET

Data retention (program memory) after 10k erase/write cycles at T

= +85 °C

Data retention (data memory) after 10k erase/write cycles at T

= +85 °C

Data retention (data memory) after 300k erase/write cycles at T

= +125 °C

Erase/write cycles (program memory)

Erase/write cycles (data memory)

RET

= 55 °C

= 85 °C

See notes

(1)(2)

See notes (1)(3)

1. Guaranteed by characterization results.

2. Retention guaranteed after cycling is 10 years at 55 °C.

3. Retention guaranteed after cycling is 1 year at 55 °C.

4. Data based on characterization performed on the whole data memory (2 Kbytes).

Min Typ

Max

(1)

(1)

300 (1)(4)

0.7

Unit mA years kcycles

9.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

and T

unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol

V hys

Parameter

Table 26. I/O static characteristics (1)

Conditions Min

Input low level voltage

(2)

Standard I/Os

True open drain I/Os

Input high level voltage

(2)

Standard I/Os

True open drain I/Os

< 2 V

True open drain I/Os

≥ 2 V

Standard I/Os

Schmitt trigger voltage hysteresis

(3)

True open drain I/Os

-0.3

0.70 x V

Typ

200

250

Max

0.3 x V

+0.3

Unit

5.2

5.5

48/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Symbol

Table 26. I/O static characteristics (1) (continued)

Parameter Conditions Min Typ Max

≤ V

Standard I/Os

(5)

I lkg

Input leakage current

(4)

≤ V

True open drain I/Os

200

(5)

≤ V

PA0 with high sink LED driver capability

200

(5)

(7)

Weak pull-up equivalent resistor

I/O pin capacitance

(6)

= V

1. V

= 3.0 V, T

= -40 to 85 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

6. R pull-up equivalent resistor based on a resistive transistor (corresponding I

Figure 22 ).

PU current characteristics described in

7. Guaranteed by design.

Unit nA k Ω pF

Figure 20. Typical V

and V

IH vs. V

(High sink I/Os)

DocID15275 Rev 16 49/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Figure 21. Typical V

and V

IH vs. V

(true open drain I/Os)

Figure 22. Typical pull-up resistance R

vs. V

with V

Figure 23. Typical pull-up current I

vs. V

with V

50/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Output driving current

Subject to general operating conditions for V

DD and T

unless otherwise specified.

Table 27. Output driving current (High sink ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1)

(2)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= +2 mA,

= 3.0 V

= +2 mA,

= 1.8 V

= +10 mA,

= 3.0 V

= -2 mA,

= 3.0 V

= -1 mA,

= 1.8 V

= -10 mA,

= 3.0 V

-0.45

-1.2

0.45

1.2

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 14 and the sum

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in Table 14 and the

sum of I

(I/O ports and control pins) must not exceed I

VDD

Table 28. Output driving current (true open drain ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1)

Output low level voltage for an I/O pin

= +3 mA,

= 3.0 V

= +1 mA,

= 1.8 V

0.45

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 14 and the sum

(I/O ports and control pins) must not exceed I

VSS

I/O

Type

Table 29. Output driving current (PA0 with high sink LED driver capability)

Symbol Parameter Conditions Min Max Unit

(1)

Output low level voltage for an I/O pin

= +20 mA,

= 2.0 V

0.9

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 14 and the sum

(I/O ports and control pins) must not exceed I

VSS

DocID15275 Rev 16 51/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Figure 24. Typ. V

at V

DD ports)

= 3.0 V (High sink Figure 25. Typ. V

at V

= 1.8 V (High sink ports)

Figure 26. Typ. V

at V

= 3.0 V (true open drain ports)

Figure 27. Typ. V

at V

= 1.8 V (true open drain ports)

Figure 28. Typ. V

- V

OH at V

DD sink ports)

= 3.0 V (High Figure 29. Typ. V

- V

OH at V sink ports)

= 1.8 V (High

52/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

NRST pin

The NRST pin input driver is CMOS. A permanent pull-up is present.

PU(NRST)

has the same value as R

(see

Table 26 on page 48

Subject to general operating conditions for V

and T

unless otherwise specified.

Symbol

Table 30. NRST pin characteristics

Parameter Conditions Min Typ

(1)

Max Unit

IL(NRST)

IH(NRST)

OL(NRST)

PU(NRST)

F(NRST) t

OP(NRST)

NF(NRST)

NRST input low level voltage

NRST output pulse width

NRST input not filtered pulse

(1)

NRST input high level voltage

NRST output low level voltage

(1)

NRST pull-up equivalent resistor

NRST input filtered pulse

(3)

(2)

= 2 mA

1.4

300

0.8

-0.8

k Ω ns ns ns

1. Guaranteed by characterization results.

2. The R

pull-up equivalent resistor is based on a resistive transistor ( Figure 30 ). Corresponding I

characteristics are described in

Figure 31 .

PU current

3. Guaranteed by design.

Figure 30. Typical NRST pull-up resistance R

vs. V

DocID15275 Rev 16 53/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Figure 31. Typical NRST pull-up current I pu

vs. V

The reset network shown in Figure 32 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the V

max. level specified in

Table 30 . Otherwise the reset is not taken into account internally. For power consumption-

sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF.

Figure 32. Recommended NRST pin configuration

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&,5&8,7

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567,1

&ILTER

).4%2.!,2%3%4

670/

069

1. Correct device reset during power on sequence is guaranteed when t

VDD[max]

is respected.

2. External reset circuit is recommended to ensure correct device reset during power down, when V

< V

DD[min]

PDR

54/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Serial peripheral interface (SPI)

Unless otherwise specified, the parameters given in Table 31

are derived from tests performed under ambient temperature, f

MASTER

frequency and V

supply voltage conditions summarized in

Section 9.3.1

. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 31. SPI characteristics

Conditions

(1)

Min Max Unit t r(SCK) t f(SCK) t su(NSS)

(2) t h(NSS)

(2) t t w(SCKH)

(2) w(SCKL)

(2) t f

SCK

1/t c(SCK) t t t t t su(MI)

(2) su(SI)

(2) t h(MI)

(2)

(2) h(SI) t a(SO)

(2)(3) t dis(SO)

(2)(4) t v(SO)

(2) v(MO)

(2) h(SO)

(2) h(MO)

(2)

SPI clock frequency

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Master mode

Slave mode

Slave mode f

Master mode,

MASTER

= 8 MHz, f

SCK

= 4 MHz

Master mode

Slave mode

Master mode

Slave mode

Slave mode (after enable edge)

Master mode

(after enable edge)

Slave mode (after enable edge)

Master mode

(after enable edge)

4 x T

MASTER

105

145

3x T

MASTER

1. Parameters are given by selecting 10-MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

MHz ns

DocID15275 Rev 16 55/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Figure 33. SPI timing diagram - slave mode and CPHA = 0

Figure 34. SPI timing diagram - slave mode and CPHA = 1 (1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

56/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Figure 35. SPI timing diagram - master mode (1)

.33INPUT

(IGH

Electrical parameters

TC3#+

#0(!

#0/,

#0(!

#0/,

#0(!

#0/,

#0(!

#0/,

-)3/

).0 54

-/3)

/54054

TSU-)

TW3#+(

TW3#+,

-3 ").

TH-)

- 3"/54

TV-/

") 4).

" ) 4/54

TH-/

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

TR3#+

TF3#+

,3").

,3"/54

AI6

DocID15275 Rev 16 57/88

Electrical parameters

Note:

STM8L101x1 STM8L101x2 STM8L101x3

Inter IC control interface (I2C)

Subject to general operating conditions for V

DD specified.

, f

MASTER

, and T

unless otherwise

The STM8L I 2 C interface meets the requirements of the Standard I 2 C communication protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol

Table 32. I2C characteristics

Parameter

Standard mode

I2C

Min

(2)

Max

(2)

Fast mode I2C

(1)

Unit

Min

(2)

Max

(2) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

(3)

1000

300

1.3

0.6

100

(4)

900

(3)

300

μ s ns t su(STA)

START condition hold time

Repeated START condition setup time

4.0

4.7

0.6

0.6 -

μ s t su(STO) t w(STO:STA)

STOP condition setup time

STOP to START condition time

(bus free)

4.0

4.7

0.6

1.3

μ s s

C b

Capacitive load for each bus line 400

1. f

SCK

must be at least 8 MHz to achieve max fast I

C speed (400 kHz).

2. Data based on standard I

2 C protocol requirement, not tested in production.

400 pF

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal.

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL).

For speeds around 200 kHz, achieved speed can have

For other speed ranges, achieved speed can have

±

5% tolerance

±

2% tolerance

The above variations depend on the accuracy of the external components used.

58/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Figure 36. Typical application with I2C bus and timing diagram 1)

, & %86

6'$

6&/

670/

5(3($7(' 67$57

67$57

VX67$

Z67267$

67$57

6'$

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U6'$

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Z6&/+

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VX6'$

K6'$

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6723

069

1. Measurement points are done at CMOS levels: 0.3 x V

and 0.7 x V

DD.

Symbol

Table 33. Comparator characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

IN(COMP_REF)

I t

V offset

(2)

START

DD(COMP)

Comparator external reference

Comparator input voltage range

Comparator offset error

Startup time (after BIAS_EN)

Analog comparator consumption

Analog comparator consumption during power-down

-0.1

-0.25

-1.25

(1)

+0.25

± 20

(1) mV

µs

µA nA t propag

(2)

Comparator propagation delay

100-mV input step with 5-mV overdrive, input rise time = 1 ns

(1)

1. Guaranteed by design.

2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided:

- Negative injection current on the I/Os close to the comparator inputs

- Switching on I/Os close to the comparator inputs

- Negative injection current on not used comparator input.

- Switching with a high dV/dt on not used comparator input.

These phenomena are even more critical when a big external serial resistor is added on the inputs.

µs

DocID15275 Rev 16 59/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the

LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. Refer to application note Software techniques for improving microcontrollers EMC performance (AN1015).

Table 34. EMS data

Symbol Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

LQFP32, V

= 3.3 V

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

LQFP32, V

= 3.3 V, f

HSI

LQFP32, V

= 3.3 V, f

HSI

60/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 35. EMI data (1)

Max vs.

Symbol Parameter Conditions

Monitored frequency band

Unit

EMI

Peak level

= 3.6 V,

= +25 °C,

LQFP32 conforming to

IEC61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

16 MHz

-3

-6

-5

1 dB μ V

1. Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin).

This test conforms to the JESD22-A114A/A115A standard.

Symbol

Table 36. ESD absolute maximum ratings

Ratings Conditions

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

1. Guaranteed by characterization results.

= +25 °C

2000

500

DocID15275 Rev 16 61/88

Electrical parameters STM8L101x1 STM8L101x2 STM8L101x3

Static latch-up

• LU : 2 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol

Table 37. Electrical sensitivities

Parameter

Static latch-up class

Class

The maximum chip junction temperature (T

Jmax

) must never exceed the values given in

Table 16: General operating conditions on page 40 .

The maximum chip-junction temperature, T

Jmax using the following equation:

, in degrees Celsius, may be calculated

Jmax

= T

Amax

+ (P

Dmax

x Θ

)

Where:

• T

Amax

is the maximum ambient temperature in ° C

• Θ

is the package junction-to-ambient thermal resistance in ° C/W

• P

Dmax

is the sum of P

INTmax

and P

I/Omax

Dmax

= P

INTmax

+ P

I/Omax

)

• P

INTmax

is the product of I

DD and internal power.

, expressed in watts. This is the maximum chip

• P

I/Omax where:

represents the maximum power dissipation on output pins

I/Omax

= Σ (V

) + Σ ((V

DD taking into account the actual V the application.

-V

OH)

OL and

OH of the I/Os at low and high level in

62/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters

Symbol

Table 38. Thermal characteristics (1)

Parameter Value

Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm

Thermal resistance junction-ambient

UFQFPN 32 - 5 x 5 mm

Thermal resistance junction-ambient

UFQFPN 28 - 4 x 4 mm

Thermal resistance junction-ambient

UFQFPN 20 - 3 x 3 mm - 0.6 mm

Thermal resistance junction-ambient

TSSOP 20

102

110

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Unit

°C/W

DocID15275 Rev 16 63/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com

ECOPACK® is an ST trademark.

10.1 UFQFPN32 package information

Figure 37. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline

(5 x 5)

64/88

!/"?-%

1. Drawing is not to scale.

2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Package information b

Table 39. UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

0.500

0.000

0.180

4.900

0.550

0.020

0.152

0.230

5.000

3.500

5.000

0.600

0.0500

0.280

5.100

0.0197

0.0071

0.1929

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.0236

0.0020

0.0110

0.2008

E2 3.400

3.500

3.600

0.1339

L ddd

0.300

0.500

0.400

0.080

0.500

Number of pins

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0118

0.1378

0.0197

0.0157

0.0031

0.1417

0.0197

Figure 38. UFQFPN32 recommended footprint

1. Dimensions are in millimeters.

DocID15275 Rev 16

$%B)3B9

65/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 39. UFQFPN32 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

'DWHFRGH

< ::

5HYLVLRQFRGH

3LQ

LQGHQWLILHU

06Y9

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

66/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Package information

10.2 LQFP32 package information

Figure 40. LQFP32 - 32-pin low profile quad flat package outline (7 x 7)

3%!4).'

0,!.%

CCC #

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

7@.&@7

DocID15275 Rev 16 67/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

Table 40. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data mm inches (1)

Dim.

Min Typ Max Min Typ Max

E3 e

K ccc

N b c

0.050

1.350

0.300

0.090

8.800

6.800

8.800

6.800

0.450

0.0°

1.400

0.370

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

1.600

0.150

1.450

0.450

0.200

9.200

7.200

9.200

7.200

0.3465

0.2677

0.750

7.0°

Number of pins

0.0177

0.0°

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

0.0039

0.0551

0.0146

0.3543

0.2756

0.3622

0.2835

0.0295

7.0°

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

68/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

Figure 41. LQFP32 recommended footprint

Package information

6?&0?6

1. Dimensions are expressed in millimeters.

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 42. LQFP32 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

670/

'DWHFRGH

< ::

5HYLVLRQFRGH

3LQLQGHQWLILHU

06Y9

DocID15275 Rev 16 69/88

Package information STM8L101x1 STM8L101x2 STM8L101x3 samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

Samples to run qualification activity.

10.3 UFQFPN28 package information

Figure 43. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline

(4 x 4 mm)

!

"

3EATING

0LANE

#OX

0INCORNER

% %

0IN)$

$ETAIL:

2O4YP

3EATING

0LANE

!"?-%?6

70/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Package information

Table 41. UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

E e b

L2 ddd

0.500

0.180

0.250

0.300

0.550

0.020

0.152

0.250

4.000

0.500

0.350

0.400

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.600

0.050

0.300

0.450

0.500

0.0098

0.0118

Number of pins

0.0197

0.0071

0.0217

0.0008

0.0060

0.0098

0.1575

0.0197

0.0138

0.0157

0.0031

0.0236

0.002

0.0118

0.0177

0.0197

Figure 44. UFQFPN28 recommended footprint

1. Dimensions are expressed in millimeters.

DocID15275 Rev 16

!"?&0?6

71/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 45. UFQFPN28 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ /

5HYLVLRQFRGH

3LQ

LQGHQWLILHU

< :: 5

'DWHFRGH

06Y9

Samples to run qualification activity.

72/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Package information

10.4 UFQFPN20 package information

Figure 46. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

3LQ (

7239,(:

(

1. Drawing is not to scale.

%277209,(:

GGG

6,'(9,(:

$$B0(B9

DocID15275 Rev 16 73/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

Table 42. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

L5 b e ddd

0.500

0.000

2.900

0.500

0.300

0.180

0.550

0.020

0.152

3.000

2.000

3.000

2.000

0.550

0.350

0.200

0.150

0.250

0.500

0.600

0.050

3.100

0.600

0.400

0.300

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0118

0.0071

0.0197

0.0000

0.1142

0.0217

0.0138

0.0079

0.0059

0.0098

0.0197

0.0217

0.0008

0.060

0.1181

0.0790

0.1181

0.0790

0.0236

0.0157

0.0118

0.0020

0.0236

0.0020

0.1220

Figure 47. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint

74/88

1. Dimensions are expressed in millimeters.

DocID15275 Rev 16

!!?&0?6

STM8L101x1 STM8L101x2 STM8L101x3 Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48. UFQFPN20 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

5HYLVLRQFRGH

3LQ

LQGHQWLILFDWLRQ

< :: 5

'DWHFRGH

06Y9

Samples to run qualification activity.

DocID15275 Rev 16 75/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

10.5 TSSOP20 package information

Figure 49. TSSOP20 - 20-lead thin shrink small package outline

% %

3%!4).'

0,!.%

'!5'%0,!.%

0).

)$%.4)&)#!4)/.

AAA #

B E

76/88

9!?-%?6

Dim.

CP c

(2)

(3) e

A2 b

1. Drawing is not to scale.

Table 43. TSSOP20 - 20-lead thin shrink small package mechanical data mm inches

(1)

Min

0.050

0.800

0.190

0.090

6.400

6.200

4.300

0.450

Typ

1.000

6.500

6.400

4.400

0.650

0.600

1.000

Max

1.200

0.150

1.050

0.300

0.100

0.200

6.600

4.500

0.750

Min

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

Typ

0.0394

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

Max

0.0472

0.0059

0.0413

0.0118

0.0039

0.0079

0.2598

0.1772

0.0295

DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Package information

Table 43. TSSOP20 - 20-lead thin shrink small package mechanical data (continued) mm inches (1)

Dim.

Min Typ Max Min Typ Max k aaa

Number of pins

0°

8°

0.100

0°

8°

0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.

Figure 50. TSSOP20 recommended footprint

1. Dimensions are in millimeters.

DocID15275 Rev 16

9!?&0?6

77/88

Package information STM8L101x1 STM8L101x2 STM8L101x3

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 51. TSSOP20 marking example (package top view)

3URGXFW

LGHQWLILFDWLRQ

3LQ

LQGHQWLILFDWLRQ

/)3

5HYLVLRQFRGH

< :: 5

'DWHFRGH

06Y9

Samples to run qualification activity.

78/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3

11 Device ordering information

Device ordering information

%XAMPLE

Figure 52. STM8L101xx ordering information scheme

34, & 5

0RODUCTCLASS

34-MICROCONTROLLER

&AMILYTYPE

,,OWPOWER

3UBFAMILYTYPE

SUBFAMILY

0INCOUNT

+PINS

'PINS

&PINS

0ROGRAMMEMORYSIZE

+BYTES

0ACKAGE

55&1&0.

4,1&0

0433/0

4EMPERATURERANGE

#TO #

#/-0?2%&AVAILABILITYON5&1&0.AND5&1&0.

!#/-0?2%&AVAILABLE

"LANK#/-0?2%&NOTAVAILABLE

3HIPPING

424APEANDREEL

"LANK4RAY

1. For a list of available options (e.g. memory size, package) and order-able part numbers or for further information on any aspect of this device, please go to www.st.com

or contact the ST Sales Office nearest to you.

DocID15275 Rev 16 79/88

STM8 development tools

12 STM8 development tools

STM8L101x1 STM8L101x2 STM8L101x3

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the

STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition,

STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows the users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.

STice key features

• Occurrence and time profiling and code coverage (new features)

• Program and data trace recording up to 128 KB records

• Read/write on the fly of memory during emulation

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• Power supply follower managing application voltages between 1.62 to 5.5 V

• Modularity that allows the users to specify the components that they need to meet their development requirements and adapt to future requirements

• Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

80/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 STM8 development tools

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual

Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available.

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com

. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of the STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface.

Available toolchains include:

• Cosmic C compiler for STM8 – One free version that outputs up to 32 Kbytes of code is available. For more information, see www.cosmic-software.com.

• Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of code. For more information, see www.raisonance.com.

• STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows the user to assemble and link their application source code.

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on the user’s application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

DocID15275 Rev 16 81/88

Revision history STM8L101x1 STM8L101x2 STM8L101x3

Date

19-Dec-2008

22-Apr-2009

24-Apr-2009

14-May-2009

15-May-2009

Revision

Table 44. Document revision history

Changes

Initial release.

Added TSSOP28 package

Modified packages on first page

COMPx_OUT pins removed

Added Figure 6: 28-pin TSSOP package pinout on page 17

Modified Section 9: Electrical parameters on page 38 .

Updated UBC[7:0] description in Section 7: Option bytes .

Updated low power current consumption on cover page.

Updated

Table 13: Voltage characteristics

Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65

V to 3.6 V

Table 26: I/O static characteristics

Table 30: NRST pin characteristics

, and

Section 9.3.9: EMC characteristics .

Updated PA1/NRST, PC0 and PC1 in Table 4: STM8L101xx pin description

Added ECC feature.

Changed internal RC frequency to 38 kHz.

Updated electrical characteristics in

Corrected title on cover page.

Changed VFQFPN32 to WFQFPN32 and updated Table 39:

UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package

(5 x 5), package mechanical data .

Updated

Table 13 ,

Table 26

, and Table 33 .

Replaced WFQFPN20 3 x 3 mm 0.8 mm package by UFQFPN20

3 x 3 mm 0.6 mm package (first page,

Table 16: General operating conditions on page 40 ,

Table 38: Thermal characteristics on page 63 ,

Section 10.2: Package mechanical data on page 67 )

Added one UFQFPN20 version with COMP_REF

Modified Figure 40: LQFP32 recommended footprint

(1)

on page 69

Added I

PROG

values in Table 25: Flash program memory on page 47

Updated

Table 31: SPI characteristics on page 55

Added STM8L101F3U6ATR part number in

Section 4: Pin description on page 15

and in Figure 47: STM8L101xx ordering information scheme on page 74

82/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Revision history

Date

12-Jun-2009

Table 44. Document revision history (continued)

Revision Changes

Removed TSSOP28 package

Modified consumption value on first page

Added BEEP_CSR (address 00 50F3h) in

Table 7: General hardware register map on page 25

TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN replaced with CLK_PCKENR in

Table 7: General hardware register map on page 25

Added graphs in Section 9: Electrical parameters on page 38

Added t

(AH) and t

(Halt) max values in

Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65

V to 3.6 V on page 44

Modified

Table 20: Total current consumption and timing in Halt and

Active-halt mode at VDD = 1.65 V to 3.6 V on page 44

Updated

Table 22: HSI oscillator characteristics on page 45 ,

Table 23: LSI oscillator characteristics on page 47 and Table 24:

RAM and hardware registers on page 47

Modified

Table 27: Output driving current (High sink ports) on page 51

Removed note 1 in

Table 37: Electrical sensitivities on page 62

Added note to Table 39: UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data on page 67 and

Table 41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data on page 70

DocID15275 Rev 16 83/88

Revision history STM8L101x1 STM8L101x2 STM8L101x3

Date

07-Sep-2009

Table 44. Document revision history (continued)

Revision Changes

Added STM8L101F2U6ATR, STM8L101G2U6ATR and

STM8L101G3U6ATR part numbers

Modified

Section 2: Description on page 9

Modified

Table 2: STM8L101xx device feature summary on page 9

(Flash)

Modified

Figure 1: STM8L101xx device block diagram on page 10

Modified

Section 3.5: Memory on page 12

Added note below

Figure 2: Standard 20-pin UFQFPN package pinout on page 15 and

Figure 5: Standard 28-pin UFQFPN package pinout on page 17

Added

Figure 6: 28-pin UFQFPN package pinout for

STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on page 18

Modified reset values for Px_IDR registers in Table 6: I/O Port hardware register map on page 24

Added

Section 6: Interrupt vector mapping on page 32

Modified OPT numbers in

Section 7: Option bytes

Modified OPT2 in

Table 10: Option bytes

Added

Section 8: Unique ID on page 36

TIM_IR pin replaced with IR_TIM pin

Modified

Table 20: Total current consumption and timing in Halt and

Active-halt mode at VDD = 1.65 V to 3.6 V on page 44

Modified

Figure 15: Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and

16 MHz on page 44

and Figure 19: Typical LSI RC frequency vs.

VDD on page 47

Modified

Table 27: Output driving current (High sink ports) on page 51

Updated

Table 29: Output driving current (PA0 with high sink LED driver capability) on page 51

Modified

: Functional EMS (electromagnetic susceptibility) on page 60

Modified conditions in Table 35: EMI data on page 61

Added note to Figure 37: UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5) on page 67

Modified Figure 41: UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4)

(1)

on page 70

Added Figure 44: UFQFPN20 recommended footprint

(1)

Added Figure 46: TSSOP20 recommended footprint (1)

on page 71

on page 72

CMP replaced with COMP

84/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Revision history

Date

29-Nov-2009

18-Jun-2010

21-Jul-2010

Table 44. Document revision history (continued)

Revision Changes

Modified status of the document (datasheet instead of preliminary data)

Replaced WFQFPN32 with UFQFPN32 and WFQFPN28 with

UFQFPN28.

Modified title of the reference manual mentioned in Section 2:

Description on page 9

Added references to “low-density” in

Section 2: Description on page 9 ,

Section 3.5: Memory on page 12

and in Figure 8: Memory map on page 23

Modified

Figure 8: Memory map on page 23

(unique ID are added)

Table 7: General hardware register map on page 25 : Modified

reserved areas and IR block replaced with IRTIM block

Modified t

TEMP

in Table 17: Operating conditions at power-up / power-down on page 41

Modified

Table 23: LSI oscillator characteristics on page 47

Modified

Table 25: Flash program memory on page 47 (t

PROG

)

Modified

Table 16: General operating conditions on page 40 and

Table 38: Thermal characteristics on page 63

Modified

Section 13: Revision history on page 82

Modified

Introduction

and Description

Modified one reserved area (0x00 5055 to 0x00 509F) in Table 7:

General hardware register map

Modified

Table 4: STM8L101xx pin description

: modified note 2 and removed “wpu” for PC0 and PC1

Removed one note to

Table 22: HSI oscillator characteristics on page 45

Modified first paragraph in Section : NRST pin

Modified OPT3 description in

Table 11: Option byte description

Added note 5 to

Table 18: Total current consumption in Run mode

Modified V

ESD(CDM) in

Table 36: ESD absolute maximum ratings on page 61

Modified

Figure 36: Typical application with I2C bus and timing diagram 1) on page 59

Modified COMP_REF availability information in

Figure 52:

STM8L101xx ordering information scheme on page 79

Modified Section 12.2: Software tools on page 78

Modified

Table 3: Legend/abbreviation for table 4 on page 20 and

Table 4: STM8L101xx pin description on page 20 (for PA0, PA1, PB0

and PB4)

Modified

Table 13: Voltage characteristics on page 38

and Table 14:

Current characteristics on page 39

Modified V

IH in

Table 26: I/O static characteristics on page 48

Added notes below UFQFPN32 package

DocID15275 Rev 16 85/88

Revision history STM8L101x1 STM8L101x2 STM8L101x3

Date

14-Oct-2010

02-Aug-2013

31-Mar-2014

18-Dec-2014

Table 44. Document revision history (continued)

Revision Changes

Added STM8L101F1 devices:

Modified Table 1: Device summary on page 1 ,

Table 2:

STM8L101xx device feature summary on page 9

and Table 5:

Flash and RAM boundary addresses on page 24

Modified warning below Figure 3 on page 16

and below Table 4:

STM8L101xx pin description on page 20

Modified Figure 52: STM8L101xx ordering information scheme on page 79

Modified text above

Figure 32: Recommended NRST pin configuration on page 54

Modified

Figure 32 on page 54

Added “The RAM content is preserved” in halt mode

Section 3.6:

Low power modes

Reformatted

Figure 2: Standard 20-pin UFQFPN package pinout

Figure 3: 20-pin UFQFPN package pinout for STM8L101F1U6ATR,

STM8L101F2U6ATR and STM8L101F3U6ATR part numbers ,

Figure 4: 20-pin TSSOP package pinout , Figure 4: 20-pin TSSOP package pinout , Figure 5: Standard 28-pin UFQFPN package pinout

Figure 6: 28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers

and Figure 7: 32-pin package pinout

Corrected NRST/PA1 pin OD output capability in Table 4:

STM8L101xx pin description and corrected note

and 4.

Added note “Slope control of all GPIO can be programmed except...”

in Table 4: STM8L101xx pin description

Added note under

Table 5: Flash and RAM boundary addresses

Replaced UM0320 with UM0470 in

Section 7: Option bytes

Updated OPT2 and OPT3 in Table 10: Option bytes

Added additional note 2.

references in

Table 22: HSI oscillator characteristics

Added note

under Table 17: Operating conditions at power-up / power-down

and under Figure 32: Recommended NRST pin configuration

Corrected ‘SCK output’ in

Figure 35: SPI timing diagram - master mode

(1)

Added top view in Figure 43: UFQFPN20 3 x 3 mm 0.6 mm package outline

Repositioned the package layout and footprint for all packages.

Replaced “Standard ports” with “High sink ports”

Replaced “TIMx_TRIG” with “TIMx_ETR”

Replaced all ‘"Data guaranteed, each individual device tested in production” notes with “Tested in production”

Updated L3 value on Table 42 , added note 2) and 3) on Table 43

Updated:

–

Figure 46: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

– Table 42: UFQFPN20 - 20-lead ultra thin fine pitch quad flat package (3 x 3 mm) mechanical data .

86/88 DocID15275 Rev 16

STM8L101x1 STM8L101x2 STM8L101x3 Revision history

Date

02-Aug-2016

12-May-2017

Table 44. Document revision history (continued)

Revision Changes

Added:

–

Figure 39: UFQFPN32 marking example (package top view)

–

Figure 42: LQFP32 marking example (package top view)

–

Figure 45: UFQFPN28 marking example (package top view)

–

Figure 48: UFQFPN20 marking example (package top view)

–

Figure 51: TSSOP20 marking example (package top view)

Updated:

–

Section 9.2: Absolute maximum ratings .

Updated:

– All table footnotes from “Data guaranteed by design, not tested in production” to “Guaranteed by design” and “Data based on characterization results, not tested in production” to “Guaranteed by characterization results”

–

Section : Device marking on page 66

–

Section : Device marking on page 69

–

Section : Device marking on page 72

–

Section : Device marking on page 75

–

Section : Device marking on page 78

–

Figure 46: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline

–

Table 42: UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data

DocID15275 Rev 16 87/88

STM8L101x1 STM8L101x2 STM8L101x3

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

88/88 DocID15275 Rev 16

8-bit ultra-low power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART, SPI, I2C

Features

Contents

List of tables

List of figures

1 Introduction

2 Description

3.3

Single wire data interface (SWIM) and debug module

3.5 Memory

3.6 Low power modes

3.11 General purpose and basic timers

16-bit general purpose timers

8-bit basic timer

3.12 Beeper

3.14 Comparators

3.15 USART

3.16 SPI

3.17 I²C

5 Memory and register map

6 Interrupt vector mapping

9.2

Absolute maximum ratings

Total current consumption

Current consumption of on-chip peripherals

Internal clock sources

High speed internal RC oscillator (HSI)

Low speed internal RC oscillator (LSI)

Flash memory

General characteristics

Output driving current

NRST pin

Serial peripheral interface (SPI)

Inter IC control interface (I2C)

±

±

Functional EMS (electromagnetic susceptibility)

Designing hardened software to avoid noise problems

Electromagnetic interference (EMI)

Absolute maximum ratings (electrical sensitivity)

Electrostatic discharge (ESD)

Static latch-up

10.1 UFQFPN32 package information

Device marking

10.2 LQFP32 package information

Device marking

10.3 UFQFPN28 package information

!

"

3EATING

0LANE

3EATING

0LANE

Device marking

10.4 UFQFPN20 package information

Device marking

10.5 TSSOP20 package information

Device marking

11 Device ordering information

12 STM8 development tools

STice key features

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