For complete information on the STM8L001J3 microcontroller memory, registers and peripherals, please refer to the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013).

The STM8L001J3 devices are members of the STM8L low-power 8-bit family. They are referred to as low-density devices in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) and in the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054).

All devices of the SM8L Series provide the following benefits:

• Reduced system cost

– 8 Kbytes of low-density embedded Flash program memory including up to

2 Kbytes of data EEPROM

– High system integration level with internal clock oscillators and watchdogs.

– Smaller battery and cheaper power supplies.

• Low power consumption and advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency

– Less than 150 µA/MHz, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode

– Clock gated system and optimized power management

• Short development cycles

– Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.

– Full documentation and a wide choice of development tools

• Product longevity

– Advanced core and peripherals made in a state-of-the art technology

– Product family operating from 1.8 V to 3.6 V supply.

6/58 DS12153 Rev 4

STM8L001J3

2 Description

Description

Flash

RAM

The STM8L001J3 low-power microcontroller features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultra fast Flash programming.

All STM8L001J3 microcontrollers feature low power low-voltage single-supply program

Flash memory. The 8-Kbyte devices embed data EEPROM.

The STM8L001J3 low power microcontroller is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.

Features

Peripheral functions

Timers

Operating voltage

Operating temperature

Packages

Table 1. STM8L001J3 device feature summary

STM8L001J3

8 Kbytes of Flash program memory including up to

2 Kbytes of Data EEPROM

1.5 Kbytes

Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep,

Serial peripheral interface (SPI), Inter-integrated circuit (I2C),

Universal synchronous / asynchronous receiver / transmitter (USART),

2 comparators, Infrared (IR) interface

Two 16-bit timers, one 8-bit timer

1.8 to 3.6 V

-40 to +125 °C

SO8N

DS12153 Rev 4 7/58

Product overview STM8L001J3

Figure 1. STM8L001J3 device block diagram

SWIM

IR_TIM

COMP1_CH3

COMP_REF

COMP2_CH2

16 MHz int RC

38 kHz int RC

Clock controller

Clocks to core and peripherals

STM8

Core up to 16 MHz

Nested interrupt controller up to 6 external interrupts

Debug module

(SWIM)

Infrared interface

Port A

Port B

Port C

Port D

COMP1

COMP2

DD18

@ V

Power

Volt. reg.

Reset

POR/PDR

Up to 8 Kbytes

Flash memory

(including up to 2 Kbytes data EEPROM)

1.5 Kbytes

SRAM

USART

I²C1 multimaster

SPI

16-bit Timer 2

16-bit Timer 3

8-bit Timer 4

IWDG

AWU

Beeper

= 1.8V to 3.6V

RX, TX

SDA, SCL

MOSI, MISO,

SCK

IR_TIM

TIM3_CH2

BEEP

MS32610V1

Legend:

AWU: Auto-wakeup unit

Int. RC: internal RC oscillator

I2C: Inter-integrated circuit multimaster interface

POR/PDR: Power on reset / power down reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous / asynchronous receiver / transmitter

IWDG: Independent watchdog

8/58 DS12153 Rev 4

STM8L001J3 Product overview

The 8-bit STM8 core is designed for code efficiency and performance.

It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.

3.3

Development tools for the STM8 microcontrollers include:

• The STVD high-level language debugger including C compiler, assembler and integrated development environment

• The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

Recommendations for SWIM pin (pin#1)

As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever.

This initial delay can be removed in the final (locked) code.

If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for the device debug/programming.

The STM8L001J3 features a nested vectored interrupt controller:

• Nested interrupts with 3 software priority levels

• 26 interrupt vectors with hardware priority

• Up to 6 external interrupt sources on 6 vectors

• Trap and reset interrupts.

DS12153 Rev 4 9/58

Product overview STM8L001J3

3.5 Memory

The STM8L001J3 devices have the following main features:

• 1.5 Kbytes of RAM

• The EEPROM is divided into two memory arrays (see the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for details on the memory mapping):

– 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data

EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).

– 64 option bytes (one block) of which 5 bytes are already used for the device.

Error correction code is implemented on the EEPROM.

Recommendation for the device's programming:

The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).

If the device's program memory is empty (0x00 content), it displays the behavior described below:

• After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG

(0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF).

It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz

HSI clock.

• Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed.

The reading of non-existing memory is a random content which can lead to the execution of invalid instructions.

The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more.

Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device.

The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts).

Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop.

10/58 DS12153 Rev 4

STM8L001J3

3.6

Product overview

Low power modes

To minimize power consumption, the product features three low power modes:

• Wait mode: CPU clock stopped, selected peripherals at full clock speed.

• Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit.

• Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The RAM content is preserved. Wakeup is triggered by an external interrupt.

The STM8L001J3 embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

The STM8L001J3 embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog

(IWDG) and Auto-wakeup unit (AWU).

The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.11 General purpose and basic timers

STM8L001J3 devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one

8-bit basic timer (TIM4).

DS12153 Rev 4 11/58

Product overview STM8L001J3

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

• Time base generation

• Measuring the pulse lengths of input signals (input capture)

• Generating output waveforms (output compare, PWM and One pulse mode)

• Interrupt capability on various events (capture, compare, overflow, break, trigger)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Beeper

The STM8L001J3 devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.

The STM8L001J3 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.14 Comparators

The STM8L001J3 features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal

(comparison with ground) or external (comparison to a reference pin voltage).

Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.

3.15 USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

3.16 SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.

12/58 DS12153 Rev 4

STM8L001J3 Product overview

3.17 I2C

The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I2Cbus. It provides multi-master capability, and controls all

I2C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.

DS12153 Rev 4 13/58

Pin description STM8L001J3

Figure 2. STM8L001J3 SO8N pinout

PA0/SWIM/BEEP/IR_TIM/

PC3/USART_TX/

PC4/USART_CK/CCO

PA2/

PA4/TIM2_BKIN/

PA6/COMP_REF

VSS 3

VDD 4

STM8L

PC1/I2C_SCL/

PC2/USART_RX

PB7/SPI_MISO/

PC0/I2C_SDA

6 PB6/SPI_MOSI

PB3/TIM2_ETR/COMP2_CH2/

PB5/SPI_SCK/

PD0/TIM3_CH2/COMP1_CH3

MSv46315V1

Type

Table 2. Legend/abbreviation for table 4

I= input, O = output, S = power supply

Input CM = CMOS

Level

Port and control configuration

Reset state

Output

Input

Output

HS = high sink/source (20 mA) float = floating, wpu = weak pull-up

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

14/58 DS12153 Rev 4

STM8L001J3

Pin number

SO8N

Pin name

Table 3. STM8L001J3 pin description

Input Output

Pin description

Main function

(after reset)

Alternate function

PA0

(1)

/SWIM/BEEP/

IR_TIM

(2)

PC3/USART_TX

PC4/USART_CK/

CCO

PA2

PA4/TIM2_BKIN

PA6/COMP_REF

PD0/TIM3_CH2/

COMP1_CH3

PB3/TIM2_ETR/

COMP2_CH2

PB5/SPI_SCK

PB6/SPI_MOSI

PB7/SPI_MISO

PC0/I2C_SDA

PC1/I2C_SCL

PC2/USART_RX

I/O X

(1)

I/O

I/O X

I/O

(1)

(2)

X HS

X -

X HS

(3)

Port A0

Port A4

SWIM input and output / Beep output/ Timer infrared output

X Port C3 USART transmit

Port C4

USART synchronous clock /

Configurable clock output

Port A2 -

Timer 2 - break input

Port A6

Port D0

Port B3

Comparator external reference

Ground

Power supply

Timer 3 - Channel 2

/ Comparator 1 -

Channel 3

Timer 2 - trigger /

Comparator 2 -

Channel 2

Port B5 SPI clock

Port B6

SPI master out / slave in

X Port B7

SPI master in / slave out

Port C0 I2C data -

Port C1 I2C clock

X Port C2 USART receive

DS12153 Rev 4 15/58

Pin description STM8L001J3

1. The PA0 pin is in input pull-up during the reset phase and after internal reset release. This PA0 default state influences all the GPIOs connected in parallel on pin number 1 (PC3, PC4).

2. High sink LED driver capability available on PA0.

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V

are not implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective internal circuitry and characteristics, V maximum of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC2) which is

Note:

Slope control of all GPIO pins can be programmed except true open drain pins which by default is limited to 2 MHz.

The PA1, PA3, PA5, PB0, PB1, PB2, PB4, PC5, PC6, PD1, PD2, PD3, PD4, PD5, PD6 and

PD7 GPIOs should be configured after device reset, by user software into the in output push-pull mode with output-low state to reduce device consumption and to improve EMC immunity. Those GPIOs are not connected to pins and after device reset are in input floating mode. To configure PA1 pin in output push-pull mode refer to Section “Configuring

NRST/PA1 pin as general purpose output” in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013).

As several pins provide a connection to multiple GPIOs, the mode selection for any of those

GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PA0 is also seen on PC3 and PC4. Push-pull configuration of PA2 is also seen on PA4 and PA6, etc.

16/58 DS12153 Rev 4

STM8L001J3

5 Memory and register map

Memory and register map

Figure 3. Memory map

0x00 0000

RAM

(1.5 Kbytes) (1) including

Stack

(up to 513 bytes) (1)

0x00 05FF

0x00 0600

Reserved

0x00 47FF

0x00 4800

Option bytes

0x00 48FF

0x 004900

0x 004924

0x 004925

0x 004930

0x 004931

Reserved

Unique ID

Reserved

0x00 49FF

0x00 5000

0x00 57FF

0x00 5800

GPIO and peripheral registers(2)

Reserved

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F

0x00 8080

CPU/SWIM/Debug/ITC

Registers

Interrupt vectors

Low-density

Flash program memory

(up to 8 Kbytes) (1) including

Data EEPROM

(up to 2 Kbytes)

0x00 9FFF

MS32621V1

Table 4

lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2. Refer to Table 6

for an overview of hardware register mapping, to Table 5

for details on I/O port hardware registers, and to

Table 7

for information on CPU/SWIM/debug module controller registers.

DS12153 Rev 4 17/58

Memory and register map STM8L001J3

Memory area

Table 4. Flash and RAM boundary addresses

Size Start address

RAM

Flash program memory

1.5 Kbytes

8 Kbytes

0x00 0000

0x00 8000

End address

0x00 05FF

0x00 9FFF

Address

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

Block

Port A

Port B

Port C

Port D

Table 5. I/O Port hardware register map

Register label Register name

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PC_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Reset status

0x00

0xxx

0x00

0xxx

0x00

0xxx

0x00

0xxx

0x00

18/58 DS12153 Rev 4

STM8L001J3 Memory and register map

Block

Table 6. General hardware register map

Register label Register name Address

0x00 5050

0x00 5051

0x00 5052

0x00 5053

Flash

0x00 5054

0x00 5055 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

0x00 50A6

0x00 50A7

0x00 50A8 to

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2 to

0x00 50BF

0x00 50C0

0x00 50C1 to

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6 to

0x00 50DF

ITC-EXTI

WFE

RST

CLK

FLASH_CR1

FLASH_CR2

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

Flash control register 1

Flash control register 2

Flash Program memory unprotection register

Data EEPROM unprotection register

Flash in-application programming status register

EXTI_CR1

EXTI_CR2

EXTI_CR3

EXTI_SR1

EXTI_SR2

EXTI_CONF

WFE_CR1

WFE_CR2

RST_CR

RST_SR

CLK_CKDIVR

CLK_PCKENR

CLK_CCOR

Reserved area (75 bytes)

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register

WFE control register 1

WFE control register 2

Reserved area (8 bytes)

Reset control register

Reset status register

Reserved area (14 bytes)

Clock divider register

Reserved area (2 bytes)

Peripheral clock gating register

Reserved (1 byte)

Configurable clock control register

Reserved area (25 bytes)

Reset status

0x00

0xX0

0x00

0x01

0x03

0x00

DS12153 Rev 4 19/58

Memory and register map

Address

0x00 50E0

0x00 50E1

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 51FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205 to

0x00 520F

0x00 5210

Table 6. General hardware register map (continued)

Block Register label Register name

IWDG

IWDG_KR

IWDG_PR

IWDG_RLR

IWDG key register

IWDG prescaler register

IWDG reload register

AWU

BEEP

AWU_CSR

AWU_APR

AWU_TBR

BEEP_CSR

Reserved area (13 bytes)

AWU control/status register

AWU asynchronous prescaler buffer register

AWU timebase selection register

BEEP control/status register

Reserved area (268 bytes)

SPI

I2C

SPI_CR1

SPI_CR2

SPI_ICR

SPI_SR

SPI_DR

SPI control register 1

SPI control register 2

SPI interrupt control register

SPI status register

SPI data register

I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL

I2C_CCRH

I2C_TRISER

Reserved area (11 bytes)

I2C control register 1

I2C control register 2

I2C frequency register

I2C own address register low

I2C own address register high

Reserved area (1 byte)

I2C data register

I2C status register 1

I2C status register 2

I2C status register 3

I2C interrupt control register

I2C Clock control register low

I2C Clock control register high

I2C TRISE register

STM8L001J3

Reset status

0xXX

0x00

0xFF

0x00

0x3F

0x00

0x1F

0x00

0x02

0x00

0x02

0x00

20/58 DS12153 Rev 4

STM8L001J3 Memory and register map

Table 6. General hardware register map (continued)

Block Register label Register name Address

0x00 521E to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238 to

0x00 524F

USART

USART_SR

USART_DR

USART_BRR1

USART_BRR2

USART_CR1

USART_CR2

USART_CR3

USART_CR4

Reserved area (18 bytes)

USART status register

USART data register

USART baud rate register 1

USART baud rate register 2

USART control register 1

USART control register 2

USART control register 3

USART control register 4

Reserved area (18 bytes)

Reset status

0xC0

0xXX

0x00

DS12153 Rev 4 21/58

Memory and register map STM8L001J3

Address

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266 to

0x00 527F

Table 6. General hardware register map (continued)

Block Register label Register name

TIM2

TIM2_CR1

TIM2_CR2

TIM2_SMCR

TIM2_ETR

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2_OISR

TIM2 control register 1

TIM2 control register 2

TIM2 slave mode control register

TIM2 external trigger register

TIM2 interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

TIM2 output idle state register

Reset status

0x00

0xFF

0x00

Reserved area (26 bytes)

22/58 DS12153 Rev 4

STM8L001J3 Memory and register map

Address

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296 to

0x00 52DF

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

0x00 528F

0x00 5290

Table 6. General hardware register map (continued)

Block Register label Register name

TIM3

TIM3_CR1

TIM3_CR2

TIM3_SMCR

TIM3_ETR

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3_EGR

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3_OISR

TIM3 control register 1

TIM3 control register 2

TIM3 slave mode control register

TIM3 external trigger register

TIM3 interrupt enable register

TIM3 status register 1

TIM3 status register 2

TIM3 event generation register

TIM3 capture/compare mode register 1

TIM3 capture/compare mode register 2

TIM3 capture/compare enable register 1

TIM3 counter high

TIM3 counter low

TIM3 prescaler register

TIM3 auto-reload register high

TIM3 auto-reload register low

TIM3 capture/compare register 1 high

TIM3 capture/compare register 1 low

TIM3 capture/compare register 2 high

TIM3 capture/compare register 2 low

TIM3 break register

TIM3 output idle state register

Reset status

0x00

0xFF

0x00

TIM4

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_IER

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

Reserved area (74 bytes)

TIM4 control register 1

TIM4 control register 2

TIM4 Slave mode control register

TIM4 interrupt enable register

TIM4 Status register 1

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register low

0x00

0xFF

DS12153 Rev 4 23/58

Memory and register map

Table 6. General hardware register map (continued)

Block Register label Register name Address

0x00 52E9 to

0x00 52FE

0x00 52FF

0x00 5300

0x00 5301

0x00 5302

IRTIM

COMP

IR_CR

COMP_CR

COMP_CSR

COMP_CCS

Reserved area (23 bytes)

Infra-red control register

Comparator control register

Comparator status register

Comparator channel selection register

STM8L001J3

Reset status

0x00

Address

Table 7. CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

0x00 7F60

0x00 7F61

0x00 7F6F

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

CPU

CFG

ITC-SPR

(1)

PCE

PCH

PCL

SPH

SPL

Accumulator

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

CFG_GCR Global configuration register

Reserved area (15 bytes)

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

0xFF

Reset status

0x00

0x80

0x00

0x05

0xFF

0x28

0x00

24/58 DS12153 Rev 4

STM8L001J3 Memory and register map

Table 7. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register label Register name

Reset status

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

SWIM

SWIM_CSR

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

Breakpoint 1 register extended byte

Breakpoint 1 register high byte

Breakpoint 1 register low byte

Breakpoint 2 register extended byte

Breakpoint 2 register high byte

Breakpoint 2 register low byte

Debug module control register 1

Debug module control register 2

Debug module control/status register 1

Debug module control/status register 2

Enable function register

0x00

1. Refer to Table 6: General hardware register map on page 19

(addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers.

0xFF

0x00

0x10

0x00

0xFF

DS12153 Rev 4 25/58

Interrupt vector mapping

6 Interrupt vector mapping

STM8L001J3

23-

2-3

IRQ

No.

Source block

Description

RESET Reset

TRAP Software interrupt

Reserved

FLASH EOP/WR_PG_DIS

Reserved

AWU Auto wakeup from Halt

Reserved

EXTIB External interrupt port B

EXTID External interrupt port D

EXTI0 External interrupt 0

EXTI1 External interrupt 1

EXTI2 External interrupt 2

EXTI3 External interrupt 3

EXTI4 External interrupt 4

EXTI5 External interrupt 5

EXTI6 External interrupt 6

EXTI7 External interrupt 7

Reserved

Table 8. Interrupt mapping

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Yes

Wakeup from Wait

(WFE mode)

Yes

(1)

Yes

Yes (1)

Yes

Reserved

COMP Comparators

TIM2

Update

/Overflow/Trigger/Break

TIM2 Capture/Compare

TIM3 Update /Overflow/Break

TIM3 Capture/Compare

Reserved

TIM4 Update /Trigger

SPI End of Transfer

Yes

Yes

Yes

Yes

Vector address

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

-0x00 8017

0x00 8018

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

-0x00 804F

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8060

0x00 8064-

0x00 806B

0x00 806C

0x00 8070

26/58 DS12153 Rev 4

STM8L001J3 Interrupt vector mapping

IRQ

No.

Source block

Table 8. Interrupt mapping (continued)

Description

Wakeup from Halt mode

Wakeup from

Active-halt mode

Wakeup from Wait

(WFI mode)

Wakeup from Wait

(WFE mode)

Vector address

USART

Transmission complete/transmit data register empty

Receive Register DATA

FULL/overrun/idle line detected/parity error

I2C interrupt

(2)

Yes

(1)

0x00 8074

0x00 8078

29 I2C Yes Yes Yes

Yes

(1)

0x00 807C

1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to Section Wait for event (WFE) mode in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013).

2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

DS12153 Rev 4 27/58

Option bytes STM8L001J3

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory.

All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM

address. See Table 9

for details on option byte addresses.

Refer to the How to program STM8L and STM8AL Flash program memory and data

EEPROM programming manual (PM0054) and the STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 9. Option bytes

Option bits

6 5 4 3 2 1 0

Factory default setting

Addr.

Option name

Option byte

No.

0x4800

0x4807

0x4802

0x4803

0x4808

Read-out protection

(ROP)

UBC (User

Boot code size)

DATASIZE

Independent watchdog option

OPT1

OPT2

OPT3

OPT4

[1:0]

ROP[7:0]

Reserved

UBC[7:0]

DATASIZE[7:0]

Reserved

IWDG

_HALT

IWDG

_HW

0x00

OPT1

OPT2

Table 10. Option byte description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

Refer to Read-out protection section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for details.

UBC[7:0] Size of the user boot code area

0x00: no UBC

0x01-0x02: UBC contains only the interrupt vectors.

0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected

...

0x7F - Page 0 to 126 reserved for UBC, memory is write protected

Refer to User boot area (UBC) section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for more details.

UBC[7] is forced to 0 internally by HW.

28/58 DS12153 Rev 4

STM8L001J3

OPT3

OPT4

Option bytes

Table 10. Option byte description (continued)

DATASIZE[7:0] Size of the data EEPROM area

0x00: no data EEPROM area

0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF

0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF

...

0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF

Refer to Data EEPROM (DATA) section in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for more details.

DATASIZE[7:6] are forced to 0 internal by HW.

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

Caution: After a device reset, read access to the program memory is not guaranteed if address

0x4807 is not programmed to 0x00.

DS12153 Rev 4 29/58

Electrical parameters STM8L001J3

8.1.1

Unless otherwise specified, all voltages are referred to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 ∑ ).

Unless otherwise specified, typical data are based on T

A only as design guidelines and are not tested.

= 25 °C, V

= 3 V. They are given

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 4

Figure 4. Pin loading conditions

STM8L PIN

50 pF

MS32617V1

30/58 DS12153 Rev 4

STM8L001J3

8.1.5

Electrical parameters

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 5 .

Figure 5. Pin input voltage

STM8L PIN

8.2

MS32618V1

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 11: Voltage characteristics ,

Table 12: Current characteristics

and

Table 13: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile is compliant with the JEDEC JESD47 qualification standard; extended mission profiles are available on demand.

Symbol

Table 11. Voltage characteristics

Ratings Min Max Unit

- V

ESD

External supply voltage

Input voltage on any pin

(1)

Electrostatic discharge voltage

-0.3

4.0

-0.3

+0.3

see Absolute maximum ratings (electrical sensitivity) on page 51

1. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V injection is induced by V

maximum is respected. If V

while a negative injection is induced by V

maximum

value. A positive

DS12153 Rev 4 31/58

Electrical parameters STM8L001J3

Symbol

Table 12. Current characteristics

Ratings Max.

Unit

VDD

VSS

Total current into V

DD power line (source)

Total current out of V

SS ground line (sink)

Output current sunk by IR_TIM pin (with high sink LED driver capability)

IO Output current sunk by any other I/O and control pin 25 mA

INJ(PIN)

Σ I

INJ(PIN)

Output current sourced by any I/Os and control pin

Injected current on any pin

(1)

Total injected current (sum of all I/O and control pins)

(2)

-25

±5

±25

1. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I injection is induced by V

maximum is respected. If V

while a negative injection is induced by V

maximum

value. A positive

2. When several inputs are submitted to a current injection, the maximum with Σ I

INJ(PIN)

Σ I

INJ(PIN)

maximum current injection on four I/O port pins of the device.

is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization

Symbol

STG

Table 13. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to +150

150

Unit

° C

32/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

8.3.1

Subject to general operating conditions for V

and T

General operating conditions

Symbol f

MASTER

(1)

(2)

Table 14. General operating conditions

Parameter

Master clock frequency

Standard operating voltage

Power dissipation at T

A for suffix 3 devices

= 125 °C

Conditions

1.8 V ≤ V

< 3.6 V

SO8N

Min

1.8

Max

3.6

Unit

MHz

V mW

Temperature range

Junction temperature range

1.8 V ≤ V

< 3.6 V

(3 suffix version)

-40 °C ≤ T

≤ 125 °C

(3 suffix version)

− 40

- 40

125

130

°C

1. f

MASTER

= f

CPU

2. To calculate P

Dmax

) use the formula given in thermal characteristics P

Dmax

=(T

Jmax

-T

)/ Θ

with T

Jmax

in this table and

DS12153 Rev 4 33/58

Electrical parameters STM8L001J3

8.3.3

Symbol

Table 15. Operating conditions at power-up / power-down

Parameter Conditions Min Typ Max Unit

V t t

VDD

TEMP

POR

(1)(2)

PDR

(1)(2)

rise time rate

Reset release delay V

rising

Power on reset threshold

Power down reset threshold

1.35

1.40

1300

1.65

1.60

(3)

µs/V ms

1. Guaranteed by characterization results.

2. Correct device reset during power on sequence is guaranteed when t

VDD[max]

is respected. External reset

PDR

< V

DD[min]

3. Tested in production.

Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

• All I/O pins in input mode with a static value at V

or V

(no load)

• All peripherals are disabled except if explicitly mentioned.

Subject to general operating conditions for V

and T

34/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Table 16. Total current consumption in Run mode (1)

Symbol Parameter Conditions

(2)

Typ

DD (Run)

Supply current in

Run mode

(4) (5)

Code executed from

RAM

Code executed from

Flash f

MASTER

= 2 MHz f

MASTER

= 4 MHz f

MASTER

= 8 MHz f

MASTER

= 16 MHz f

MASTER

= 2 MHz f

MASTER

= 4 MHz f

MASTER

= 8 MHz f

MASTER

= 16 MHz

1. Based on characterization results, unless otherwise specified.

2. All peripherals off, V

from 1.8 V to 3.6 V, HSI internal RC osc., f

CPU

MASTER

3. Maximum values are given for T

= − 40 to 125 °C.

4. CPU executing typical data processing.

5. An approximate value of I

DD(Run)

= f

MASTER

DD(Run)

can be given by the following formula:

x 150 µA/MHz +215 µA.

6. Tested in production.

0.55

0.88

1.50

2.70

0.39

0.55

0.90

1.60

Max

(3)

0.60

0.70

1.20

2.10

(6)

0.70

1.80

2.50

3.50

Unit mA

Figure 6. I

DD(RUN)

vs. V

DD, f

CPU

= 2 MHz Figure 7. I

DD(RUN)

vs. V

, f

CPU

= 16 MHz

1. Typical current consumption measured with code executed from Flash.

DS12153 Rev 4 35/58

Electrical parameters STM8L001J3

Table 17. Total current consumption in Wait mode (1)

Symbol Parameter Conditions Typ Max (2)

DD (Wait)

Supply current in

Wait mode

CPU not clocked, all peripherals off,

HSI internal RC osc. f

MASTER

= 2 MHz 245 f

MASTER

= 4 MHz 300 f

MASTER

= 8 MHz 380 f

MASTER

= 16 MHz 510

1. Based on characterization results, unless otherwise specified.

2. Maximum values are given for T

= -40 to 125 °C.

400

450

600

800

Unit

µA

Figure 8. I

DD(WAIT)

vs. V

, f

CPU

= 2 MHz Figure 9. I

DD(WAIT)

vs. V

, f

CPU

= 16 MHz

1. Typical current consumption measured with code executed from Flash.

36/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Table 18. Total current consumption and timing in Halt and Active-halt mode at

= 1.8 V to 3.6 V (1)(2)

Symbol Parameter Conditions Typ Max Unit

DD(AH)

DD(WUFAH) t

I t

WU(AH)

(3)

DD(Halt)

DD(WUFH)

WU(Halt)

(3)

Supply current in Active-halt mode

LSI RC osc.

(at 37 kHz)

= -40 °C to 25 °C 0.8

= 55 °C 1

= 85 °C

= 105 °C

1.4

3.2

2.9

2.5

7.5

= 125 °C 5.8

Supply current during wakeup time from Active-halt mode

Wakeup time from Activehalt mode to Run mode

CPU

= 16 MHz

6.5

0.35 1.2

(4)

Supply current in Halt mode

= -40 °C to 25 °C

= 55 °C

= 85 °C

= 105 °C

= 125 °C

0.6

2.5

1.8

1 2.5

(4)

6.5

5.4

(4)

Supply current during wakeup time from Halt mode

2 -

Wakeup time from Halt mode to Run mode f

CPU

= 16 MHz 4 6.5

1. T

= -40 to 125 °C, no floating I/O, unless otherwise specified.

2. Guaranteed by characterization results.

3. Measured from interrupt event to interrupt vector fetch.

To get t

for another CPU frequency use t

(FREQ) = t

(16 MHz) + 1.5 (T

FREQ

-T

16 MHz

4. Tested in production.

μ A

μ A mA

μ s mA

μ s

μ A

Figure 10. Typ. I

DD(Halt)

vs. V

DD,

CPU

= 2 MHz and 16 MHz

1. Typical current consumption measured with code executed from Flash.

DS12153 Rev 4 37/58

Electrical parameters

8.3.4

STM8L001J3

Current consumption of on-chip peripherals

Measurement made for f

MASTER

= from 2 MHz to 16 MHz

Table 19. Peripheral current consumption

Symbol Parameter Typ. V

= 3.0 V Unit

DD(TIM2)

DD(TIM3)

TIM2 supply current

(1)

TIM3 supply current

(1)

DD(TIM4)

DD(USART)

TIM4 timer supply current

USART supply current (2)

(1)

µA/MHz

DD(SPI)

DD(I2C1)

SPI supply current

I2C supply current

(2)

DD(COMP)

Comparator supply current

(2)

20 µA

1. Data based on a differential I production.

measurement between all peripherals off and a timer counter running at

16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. not tested in

2. Data based on a differential I

measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production.

Clock and timing characteristics

Internal clock sources

Subject to general operating conditions for V

and T

High speed internal RC oscillator (HSI)

Symbol Parameter

Table 20. HSI oscillator characteristics (1)

Conditions f

HSI

ACC

HSI

DD(HSI)

Frequency V

= 3.0 V

Accuracy of HSI oscillator

(factory calibrated)

= 3.0 V, T

= 25 °C

1.8 V ≤ V

-40 °C ≤ T

≤

≤ 3.6 V,

125 °C

HSI oscillator power consumption

1. V

= 3.0 V, T

= -40 to 125 °C unless otherwise specified.

2. Guaranteed by characterization results.

Min

-5

-7.5

(2)

Typ Max Unit

MHz

7.5

(2)

70 100

(2)

µA

38/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Low speed internal RC oscillator (LSI)

Symbol

Table 21. LSI oscillator characteristics

(1)

Parameter Conditions Min Typ Max f f

LSI drift(LSI)

Frequency -

LSI oscillator frequency drift (2)

0 °C ≤ T

≤ 85 °C

-12

1. V

= 1.8 V to 3.6 V, T

= -40 to 125 °C unless otherwise specified.

2. For each individual part, this value is the frequency drift from the initial measured frequency .

Figure 11. Typical LSI RC frequency vs. V

Unit kHz

= -40 to 125 °C unless otherwise specified.

Table 22. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

Data retention mode

(1)

Halt mode (or Reset) 1.65

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization results.

Flash memory

Symbol

DD t prog

Table 23. Flash program memory

Parameter Conditions

Operating voltage

(all modes, read/write/erase)

Programming time for 1- or 64-byte (block) erase/write cycles (on programmed byte)

Programming time for 1- to 64-byte (block) write cycles (on erased byte) f

MASTER

= 16 MHz

Min Typ

Max

(1)

Unit

1.8

3.6

V ms ms

DS12153 Rev 4 39/58

Electrical parameters STM8L001J3

Table 23. Flash program memory (continued)

Symbol Parameter Conditions

I prog

Programming/ erasing consumption

=+25 °C, V

= 3.0 V

=+25 °C, V

= 1.8 V t

RET

Data retention (program memory) after 10k erase/write cycles at T

= +85 °C

Data retention (data memory) after 10k erase/write cycles at T

= +85 °C

Data retention (data memory) after 300k erase/write cycles at T

= +125 °C

Erase/write cycles (program memory)

Erase/write cycles (data memory)

RET

= 55 °C

= 85 °C

See notes

(1)(2)

See notes (1)(3)

1. Guaranteed by characterization results.

2. Retention guaranteed after cycling is 10 years at 55 °C.

3. Retention guaranteed after cycling is 1 year at 55 °C.

4. Data based on characterization performed on the whole data memory (2 Kbytes).

Min Typ

Max

(1)

(1)

100

(1)

100 (1)(4)

0.7

Unit mA years cycles kcycles

8.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

and T

unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol

V hys

I lkg

(7)

Parameter

Table 24. I/O static characteristics (1)

Conditions Min

Input low level voltage

(2)

Input high level voltage

(2)

Input leakage current (4)

All I/Os

Schmitt trigger voltage hysteresis

(3)

Standard I/Os

True open drain I/Os

≤ V

Standard I/Os

≤ V

True open drain I/Os

Weak pull-up equivalent resistor

I/O pin capacitance

(6)

≤ V

PA0 with high sink LED driver capability

= V

-0.3

0.70 x V

Typ

200

250

(8)

Max

0.3 x V

+0.3

Unit

V mV

(5)

nA k Ω pF

40/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

1. V

= 3.0 V, T

= -40 to 85 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

6. R pull-up equivalent resistor based on a resistive transistor (corresponding I

Figure 14 ).

PU current characteristics described in

7. Guaranteed by design.

8. Capacitance per one GPIO on pin. Complete pin capacitance depends on how many GPIOs are connected on a given pin

(see

Table 3 ). Total pin capacitance is then N x C

(where N = number of GPIOs on a given pin).

Figure 12. Typical V

and V

IH vs. V

(High sink I/Os)

Figure 13. Typical V

and V

IH vs. V

(true open drain I/Os)

DS12153 Rev 4 41/58

Electrical parameters STM8L001J3

Figure 14. Typical pull-up resistance R

vs. V

with V

Figure 15. Typical pull-up current I

vs. V

with V

42/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Output driving current

Subject to general operating conditions for V

DD and T

unless otherwise specified.

Table 25. Output driving current (High sink ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1)

(2)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

= +2 mA,

= 3.0 V

= +2 mA,

= 1.8 V

= +10 mA,

= 3.0 V

= -2 mA,

= 3.0 V

= -1 mA,

= 1.8 V

= -10 mA,

= 3.0 V

-0.45

-1.2

0.45

1.2

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 12 and the sum

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in Table 12 and the

sum of I

(I/O ports and control pins) must not exceed I

VDD

Table 26. Output driving current (true open drain ports)

I/O

Type

Symbol Parameter Conditions Min Max Unit

(1)

Output low level voltage for an I/O pin

= +3 mA,

= 3.0 V

= +1 mA,

= 1.8 V

0.45

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 12 and the sum

(I/O ports and control pins) must not exceed I

VSS

I/O

Type

Table 27. Output driving current (PA0 with high sink LED driver capability)

Symbol Parameter Conditions Min Max Unit

(1)

Output low level voltage for an I/O pin

= +20 mA,

= 2.0 V

0.9

1. The I of I

current sunk must always respect the absolute maximum rating specified in

Table 12 and the sum

(I/O ports and control pins) must not exceed I

VSS

DS12153 Rev 4 43/58

Electrical parameters STM8L001J3

Figure 16. Typ. V

at V

DD ports)

= 3.0 V (High sink Figure 17. Typ. V

at V

= 1.8 V (High sink ports)

Figure 18. Typ. V

at V

= 3.0 V (true open drain ports)

Figure 19. Typ. V

at V

= 1.8 V (true open drain ports)

Figure 20. Typ. V

- V

OH at V

DD sink ports)

= 3.0 V (High Figure 21. Typ. V

- V

OH at V sink ports)

= 1.8 V (High

44/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

8.3.7 Communication interfaces

Serial peripheral interface (SPI)

Unless otherwise specified, the parameters given in

Table 28 are derived from tests

performed under ambient temperature, f

MASTER

frequency and V

supply voltage conditions summarized in

Section 8.3.1

. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter

Table 28. SPI characteristics

Conditions

(1)

Min Max Unit t r(SCK) t f(SCK) t su(NSS)

(2) t h(NSS)

(2) t t w(SCKH)

(2) w(SCKL)

(2) t f

SCK

1/t c(SCK) t t t t t su(MI)

(2) su(SI)

(2) t h(MI)

(2)

(2) h(SI) t a(SO)

(2)(3) t dis(SO)

(2)(4) t v(SO)

(2) v(MO)

(2) h(SO)

(2) h(MO)

(2)

SPI clock frequency

SPI clock rise and fall time Capacitive load: C = 30 pF

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Master mode

Slave mode

Slave mode f

Master mode,

MASTER

= 8 MHz, f

SCK

= 4 MHz

Master mode

Slave mode

Master mode

Slave mode

Slave mode (after enable edge)

Master mode

(after enable edge)

Slave mode (after enable edge)

Master mode

(after enable edge)

4 x T

MASTER

105

145

3x T

MASTER

1. Parameters are given by selecting 10-MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

MHz ns

DS12153 Rev 4 45/58

Electrical parameters

Figure 22. SPI timing diagram - slave mode and CPHA = 0

STM8L001J3

Figure 23. SPI timing diagram - slave mode and CPHA = 1 (1)

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

ai14135b

46/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Figure 24. SPI timing diagram - master mode (1)

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD.

tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136d

DS12153 Rev 4 47/58

Electrical parameters

Note:

STM8L001J3

Inter IC control interface (I2C)

Subject to general operating conditions for V

DD specified.

, f

MASTER

, and T

unless otherwise

The STM8L I 2 C interface meets the requirements of the Standard I 2 C communication protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol

Table 29. I2C characteristics

Parameter

Standard mode

I2C

Min

(2)

Max

(2)

Fast mode I2C

(1)

Unit

Min

(2)

Max

(2) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

4.7

4.0

250

(3)

1000

300

1.3

0.6

100

(4)

900

(3)

300

μ s ns t su(STA)

START condition hold time

Repeated START condition setup time

4.0

4.7

0.6

0.6 -

μ s t su(STO) t w(STO:STA)

STOP condition setup time

STOP to START condition time

(bus free)

4.0

4.7

0.6

1.3

μ s s

C b

Capacitive load for each bus line 400

1. f

SCK

must be at least 8 MHz to achieve max fast I

C speed (400 kHz).

2. Data based on standard I

2 C protocol requirement, not tested in production.

400 pF

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal.

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL).

For speeds around 200 kHz, achieved speed can have

For other speed ranges, achieved speed can have

±

5% tolerance

±

2% tolerance

The above variations depend on the accuracy of the external components used.

48/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

I2C BUS

Figure 25. Typical application with I2C bus and timing diagram (1)

4.7kΩ

100Ω

SDA

SCL

STM8L

Start

SDA t f(SDA)

SCL t r(SDA) t su(SDA) t h(SDA) t h(STA) t w(SCLH) t w(SCLL) t r(SCL) t f(SCL)

Repeated start t su(STA) t w(STO:STA)

Start

Stop t su(STO)

MS32620V2

1. Measurement points are done at CMOS levels: 0.3 x V

and 0.7 x V

DD.

Symbol

Table 30. Comparator characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

IN(COMP_REF)

I t

V offset

(2)

START

DD(COMP)

Comparator external reference

Comparator input voltage range

Comparator offset error

Startup time (after BIAS_EN)

Analog comparator consumption

Analog comparator consumption during power-down

-0.1

-0.25

-1.25

+0.25

± 20

(1)

(1) mV

µs

µA nA t propag

(2) Comparator propagation delay

100-mV input step with 5-mV overdrive, input rise time = 1 ns

2 (1)

1. Guaranteed by design.

2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided:

- Negative injection current on the I/Os close to the comparator inputs

- Switching on I/Os close to the comparator inputs

- Negative injection current on not used comparator input.

- Switching with a high dV/dt on not used comparator input.

These phenomena are even more critical when a big external serial resistor is added on the inputs.

µs

DS12153 Rev 4 49/58

Electrical parameters STM8L001J3

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the

LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Prequalification trials:

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. Refer to application note Software techniques for improving microcontrollers EMC performance (AN1015).

Table 31. EMS data

Symbol Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

SO8N, V

= 3.3 V

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

SO8N, V

= 3.3 V, f

HSI

SO8N, V

= 3.3 V, f

HSI

TBD

50/58 DS12153 Rev 4

STM8L001J3 Electrical parameters

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 32. EMI data (1)

Max vs.

Symbol Parameter Conditions

Monitored frequency band

Unit

EMI

Peak level

= 3.6 V,

= +25 °C,

SO8N conforming to

IEC61967-2

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

16 MHz

TBD

TBD dB μ V

1. Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin).

This test conforms to the JESD22-A114A/A115A standard.

Symbol

Table 33. ESD absolute maximum ratings

Ratings Conditions

Maximum value

(1)

Unit

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

1. Guaranteed by characterization results.

= +25 °C

TBD

DS12153 Rev 4 51/58

Electrical parameters STM8L001J3

Static latch-up

• LU : 2 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol

Table 34. Electrical sensitivities

Parameter

Static latch-up class

Class

TBD

The maximum chip junction temperature (T

Jmax

) must never exceed the values given in

Table 14: General operating conditions on page 33

The maximum chip-junction temperature, T

Jmax using the following equation:

, in degrees Celsius, may be calculated

Jmax

= T

Amax

+ (P

Dmax

x Θ

)

Where:

• T

Amax

is the maximum ambient temperature in ° C

• Θ

is the package junction-to-ambient thermal resistance in ° C/W

• P

Dmax

is the sum of P

INTmax

and P

I/Omax

Dmax

= P

INTmax

+ P

I/Omax

)

• P

INTmax

is the product of I

DD and internal power.

, expressed in watts. This is the maximum chip

• P

I/Omax where:

represents the maximum power dissipation on output pins

I/Omax

= Σ (V

OL the application.

) + Σ ((V

-V

OH) taking into account the actual V

OL and

OH of the I/Os at low and high level in

Symbol

Table 35. Thermal characteristics

(1)

Parameter Value

Thermal resistance junction-ambient SO8N 102

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Unit

°C/W

52/58 DS12153 Rev 4

STM8L001J3 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

Failure analysis and guarantee

The small number of pins available induces limitations on failure analysis depth in case of isolated symptom, typically with an impact lower than 0.1%. Please contact your sales office for additional information for any failure analysis. STMicroelectronics will make a feasibility study for investigation based on failure rate and symptom description prior to responsibility endorsement.

9.1 SO8N package information

Figure 26. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline h x 45˚

A2 A c ccc b e

0.25 mm

GAUGE PLANE k

E1 E

SO-A_V2

1. Drawing is not to scale.

Table 36. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data millimeters inches

(1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

A2 b c

0.100

1.250

0.280

0.170

1.750

0.250

0.480

0.230

0.0039

0.0492

0.0110

0.0067

0.0689

0.0098

0.0189

0.0091

DS12153 Rev 4 53/58

Package information STM8L001J3

Table 36. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data (continued) millimeters inches (1)

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

L e h

L1 ccc

4.800

5.800

3.800

0.250

0°

0.400

4.900

6.000

3.900

1.270

1.040

5.000

6.200

4.000

0.500

8°

1.270

0.100

1. Values in inches are converted from mm and rounded to four decimal digits.

0.1890

0.2283

0.1496

0.0098

0°

0.0157

0.1929

0.2362

0.1535

0.0500

0.0409

0.1969

0.2441

0.1575

0.0197

8°

0.0500

0.0039

Figure 27. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint

0.6 (x8)

54/58

1. Dimensions are expressed in millimeters.

2. Drawing is not to scale.

1.27

DS12153 Rev 4

O7_FP_V1

STM8L001J3 Package information

Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 28. Example of SO8N marking (package top view)

Product identification

8L001J3

R Y WW

Date code

Unmarkable surface

PIN1 reference

Additional information

MSv46327V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS12153 Rev 4 55/58

Ordering information STM8L001J3

Example:

Device family

STM8 microcontroller

Family type

L = Low power

Table 37. Ordering information scheme

STM8 L 001 J 3 M 3

Sub family type

00x = Value line sub-family

001 = Low density

Pin count

J = 8 pins

Program memory size

3 = 8 Kbytes

Package

M = SO8N

Temperature range

3 = -40°C to 125°C

1. For a list of available options (e.g. memory size, package) and order-able part numbers or for further information on any aspect of this device, please go to www.st.com

or contact the ST Sales Office nearest to you.

56/58 DS12153 Rev 4

STM8L001J3 Revision history

Date

06-Jun-2017

04-Oct-2017

04-Jul-2018

10-Sep-2020

Revision

Table 38. Document revision history

Changes

Initial release.

Updated:

– Document’s confidentiality level to public

–

Section 1: Introduction

–

Section 2: Description

–

Section 9: Package information

–

Figure 23: SPI timing diagram - slave mode and CPHA = 1

(1)

–

Figure 24: SPI timing diagram - master mode (1)

–

Figure 25: Typical application with I2C bus and timing diagram (1)

Updated:

–

Recommendations for SWIM pin (pin#1)

Section 3.3: Single wire data interface (SWIM) and debug module

Deleted:

– Figure: Typical HSI frequency vs. VDD

– Figure: Typical HSI accuracy vs. temperature, VDD = 3 V

– Figure: Typical HSI accuracy vs. temperature, VDD = 1.8 V to 3.6 V

Updated:

–

Table 20: HSI oscillator characteristics

DS12153 Rev 4 57/58

STM8L001J3

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

58/58 DS12153 Rev 4