STMicroelectronics STM32L476G-EVAL User Manual

Document

UM1855

User manual

Evaluation board with STM32L476ZGT6 MCU

Introduction

The STM32L476G-EVAL evaluation board is designed as complete demonstration and development platform for STMicroelectronics ARM ® Cortex ® -M4-core-based

STM32L476ZGT6 microcontroller with three I ² C buses, three SPI and six USART ports,

CAN port, SWPMI, two SAI ports, 12-bit ADC, 12-bit DAC, LCD driver, internal 128-Kbyte

SRAM and 1-Mbyte Flash memory, Quad-SPI port, touch sensing capability, USB OTG FS port, LCD controller, flexible memory controller (FMC), JTAG debug port.

STM32L476G-EVAL, shown in Figure 1

, is used as reference design for user application development, although it is not considered as final application.

A full range of hardware features on the board helps users to evaluate all on-board peripherals such as USB, USART, digital microphones, ADC and DAC, dot-matrix TFT LCD,

LCD glass module, IrDA (supported up to version MB1144 C-01 of the board), LDR, SRAM,

NOR Flash memory device, Quad-SPI Flash memory device, microSD card, sigma-delta modulators, smartcard with SWP, CAN transceiver, EEPROM, RF-EEPROM. Extension headers allow connecting daughterboards or wrapping boards.

ST-LINK/V2-1 in-circuit debugger and flashing facility is integrated on the mainboard.

Figure 1. STM32L476G-EVAL evaluation board

1. Picture not contractual.

November 2016 DocID027351 Rev 5

1/101

www.st.com

Contents

2/101

UM1855

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2

Demonstration software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3

Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4

Unpacking recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

ST-LINK/V2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1

2.1.2

Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ST-LINK/V2-1 firmware upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2

ETM trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1

2.3.2

Supplying the board through ST-LINK/V2-1 USB port . . . . . . . . . . . . . . 15

Using ST-LINK/2-1 along with powering through CN22 power jack . . . 16

2.4

Clock references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5

Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6

Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6.1

2.6.2

Boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Bootloader limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7

Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7.1

2.7.2

2.7.3

Digital microphones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Headphones outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Limitations in using audio features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.8

USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM32L476G-EVAL used as USB device . . . . . . . . . . . . . . . . . . . . . . . 23

STM32L476G-EVAL used as USB host . . . . . . . . . . . . . . . . . . . . . . . . 24

Configuration elements related with USB OTG FS port . . . . . . . . . . . . 24

Limitations in using USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9

RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9.1

2.9.2

2.9.3

RS-232 port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

IrDA port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DocID027351 Rev 5

UM1855 Contents

2.9.4

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.10

LPUART port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.11

microSD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.11.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.11.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.12

Motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.12.1

Board modifications to enable motor control . . . . . . . . . . . . . . . . . . . . . 30

2.12.2

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.13

CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.13.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.13.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.14

Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15

LCD glass module daughterboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.15.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.16

TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.17

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.18

Physical input devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.18.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19

Operational amplifier and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19.1

Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.19.2

Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.20

Analog input, output, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.21

SRAM device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.21.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.21.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.22

NOR Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.22.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.22.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.23

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.23.1

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.24

RF-EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.25

Quad-SPI Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.25.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.25.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.26

Touch-sensing button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DocID027351 Rev 5

3/101

Contents UM1855

2.26.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.27

Smartcard, SWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.27.1

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.27.2

Operating voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.28

Near-field communication (NFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.29

Dual-channel sigma-delta modulators STPMS2L . . . . . . . . . . . . . . . . . . 51

2.29.1

STPMS2L presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.29.2

STPMS2L settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.29.3

STPMS2L power metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.29.4

STPMS2L for PT100 measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.29.5

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.30

STM32L476ZGT6 current consumption measurement . . . . . . . . . . . . . . 54

2.30.1

IDD measurement principle - analog part . . . . . . . . . . . . . . . . . . . . . . . 55

2.30.2

Low-power-mode IDD measurement principle - logic part . . . . . . . . . . . 56

2.30.3

IDD measurement in dynamic run mode . . . . . . . . . . . . . . . . . . . . . . . . 58

2.30.4

Calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.1

RS-232 D-sub male connector CN9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.2

Power connector CN22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3

LCD daughterboard connectors CN11 and CN14 . . . . . . . . . . . . . . . . . . 61

3.4

Extension connectors CN6 and CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.5

ST-LINK/V2-1 programming connector CN16 . . . . . . . . . . . . . . . . . . . . . 65

3.6

ST-LINK/V2-1 Standard-B USB connector CN17 . . . . . . . . . . . . . . . . . . . 65

3.7

JTAG connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.8

ETM trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.9

microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.10

ADC/DAC connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.11

RF-EEPROM daughterboard connector CN3 . . . . . . . . . . . . . . . . . . . . . 69

3.12

Motor control connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.13

USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.14

CAN D-sub male connector CN5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.15

NFC connector CN13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Appendix A Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4/101

DocID027351 Rev 5

UM1855 Contents

Appendix B Federal Communications Commission (FCC) and Industry Canada (IC) Compliance Statements. . . . . . . . . . . . . 99

B.1

FCC Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.1.1

B.1.2

B.1.3

Part 15.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Part 15.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Part 15.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.2

IC Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.2.1

B.2.2

Compliance Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Déclaration de conformité. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

DocID027351 Rev 5

5/101

List of tables

List of tables

UM1855

Setting of configuration elements for trace connector CN12 . . . . . . . . . . . . . . . . . . . . . . . 14

Boot selection switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital microphone-related jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Configuration elements related with USB OTG FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9.

Settings of configuration elements for RS-232 and IrDA ports . . . . . . . . . . . . . . . . . . . . . . 26

Table 10.

Hardware settings for LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11.

Terminals of CN18 microSD slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12.

Motor control terminal and function assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13.

Table 14.

LCD-daughterboard-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15.

LCD glass element mapping - segments 0 to 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16.

LCD glass element mapping - segments 10 to 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17.

LCD glass element mapping - segments 20 to 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18.

LCD glass element mapping - segments 30 to 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19.

Access to TFT LCD resources with FMC address lines A0 and A1 . . . . . . . . . . . . . . . . . . 39

Table 20.

Assignment of CN19 connector terminals of TFT LCD panel . . . . . . . . . . . . . . . . . . . . . . . 39

Table 21.

Port assignment for control of LED indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 22.

Port assignment for control of physical input devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 23.

Setting of jumpers related with potentiometer and LDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 24.

SRAM chip select configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 25.

NOR Flash memory-related configuration elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 26.

Configuration elements related with Quad-SPI device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27.

Touch-sensing-related configuration elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28.

Assignment of ports for ST8024CDR control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29.

Configuration elements related with smartcard and SWP . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 30.

CN13 NFC connector terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 31.

JP11 jumper settings during IDD measurement with calibration . . . . . . . . . . . . . . . . . . . . 59

Table 32.

RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support . . . . . . . . . 60

Table 33.

CN11 and CN14 daughterboard connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34.

Daughterboard extension connector CN6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 35.

Daughterboard extension connector CN7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 36.

USB Standard-B connector CN17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37.

JATG debugging connector CN15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 38.

Trace debugging connector CN12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 39.

microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 40.

Analog input-output connector CN8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 41.

RF-EEPROM daughterboard connector CN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 42.

Motor control connector CN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 43.

USB OTG FS Micro-AB connector CN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 44.

CAN D-sub (DE-9M) 9-pins male connector CN5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 45.

NFC CN13 terminal assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 46.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6/101

DocID027351 Rev 5

UM1855

List of figures

List of figures

Figure 1.

STM32L476G-EVAL evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

STM32L476G-EVAL hardware block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3.

STM32L476G-EVAL main component layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4.

USB composite device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

CN22 power jack polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6.

CN20, CN21 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.

PCB top-side rework for motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 8.

PCB underside rework for motor control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 9.

LCD glass module daughterboard in display position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10.

LCD glass module daughterboard in I/O-bridge position . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11.

LCD glass display element mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 12.

NFC board plugged into STM32L476G-EVAL board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 13.

Routing of STPMS2L dual-channel sigma-delta modulators . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 14.

Power measurement principle schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 15.

STPMS2L power metering schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 16.

Temperature measurement principle schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 17.

Schematic diagram of the analog part of IDD measurement . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 18.

Schematic diagram of logic part of low-power-mode IDD measurement . . . . . . . . . . . . . . 57

Figure 19.

Low-power-mode IDD measurement timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 20.

RS-232 D-sub (DE-9M) 9-pole connector (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 21.

Power supply connector CN22 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 22.

USB type B connector CN17 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 23.

JTAG debugging connector CN15 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 24.

Trace debugging connector CN12 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 25.

microSD card connector CN18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 26.

Analog input-output connector CN8 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 27.

RF-EEPROM daughterboard connector CN3 (front view) . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 28.

Motor control connector CN2 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 29.

USB OTG FS Micro-AB connector CN1 (front view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 30.

CAN D-sub (DE-9M) 9-pole male connector CN5 (front view) . . . . . . . . . . . . . . . . . . . . . . 71

Figure 31.

NFC female connector CN13 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32.

STM32L476G-EVAL top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 33.

MCU, LCD daughterboard and I/O expander interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 34.

STM32L476G-EVAL MCU part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 35.

STM32L476G-EVAL MCU part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 36.

LCD glass module daughterboard connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 37.

I/O expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 38.

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 39.

Smartcard, SWP and NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40.

USART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 41.

SRAM and NOR Flash memory devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 42.

TFT LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 43.

Extension connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 44.

Quad-SPI Flash memory device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 45.

microSD card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 46.

Physical control peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 47.

CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 48.

Touch-sensing device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DocID027351 Rev 5

7/101

List of figures UM1855

Figure 49.

USB_OTG_FS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 50.

IDD measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 51.

Audio codec device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 52.

STPMS2L and PT100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 53.

RF-EEPROM and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 54.

Motor control connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 55.

JTAG and trace debug connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 56.

ST-LINK/V2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

8/101

DocID027351 Rev 5

UM1855

1 Overview

Overview

1.1 Features

• STM32L476ZGT6 microcontroller with 1-Mbyte Flash memory and 128-Kbyte RAM

• Four power supply options: power jack, ST-LINK/V2-1 USB connector, USB OTG FS connector, daughterboard

• Microcontroller supply voltage: 3.3 V or range from 1.71 V to 3.6 V

• Two MEMS digital microphones

• Two jack outputs for stereo audio headphone with independent content

• Slot for microSD card supporting SD, SDHC, SDXC

• 4-Gbyte microSD card bundled

• 16-Mbit (1M x 16 bit) SRAM device

• 128-Mbit (8M x 16 bit) NOR Flash memory device

• 256-Mbit Quad-SPI Flash memory device with double transfer rate (DTR) support

• RF-EEPROM with I

C bus

• EEPROM supporting 1 MHz I ² C-bus communication speed

• RS-232 port configurable for communication or MCU flashing

• IrDA transceiver (only supported up to MB1144 C-01 version of the board, no more supported from MB1144 C-02 version)

• USB OTG FS Micro-AB port

• CAN 2.0A/B-compliant port

• Joystick with four-way controller and selector

• Reset and wake-up / tamper buttons

• Touch-sensing button

• Light-dependent resistor (LDR)

• Potentiometer

• Coin battery cell for power backup

• LCD glass module daughterboard (MB979) with 40x8-segment LCD driven directly by

STM32L476ZGT6

• 2.8-inch 320x240 dot-matrix color TFT LCD panel with resistive touchscreen

• Smartcard connector and SWP support

• NFC transceiver connector

• Connector for ADC input and DAC output

• Power-metering demonstration with dual-channel, sigma-delta modulator

• PT100 thermal sensor with dual-channel, sigma-delta modulator

• MCU current consumption measurement circuit

• Access to comparator and operational amplifier of STM32L476ZGT6

• Extension connector for motor control module

• JTAG/SWD, ETM trace debug support, user interface through USB virtual COM port, embedded ST-LINK/V2-1 debug and flashing facility

• Extension connector for daughterboard

DocID027351 Rev 5

9/101

100

Overview UM1855

Demonstration software is preloaded in the STM32L476ZGT6 Flash memory, for easy demonstration of the device peripherals in stand-alone mode. For more information and to download the latest available version, refer to the STM32L476G-EVAL demonstration software available on the www.st.com website.

To order the evaluation board based on the STM32L476ZGT6 MCU, use the order code

STM32L476G-EVAL.

Before the first use, make sure that, no damage occurred to the board during shipment and no socketed components are loosen in their sockets or fallen into the plastic bag.

In particular, pay attention to the following components:

1. Quartz crystal (X2 position)

2. microSD card in its CN18 receptacle

3. RF-EEPROM board (ANT7-M24LR-A) in its CN3 connector

For product information related with STM32L476ZGT6 microcontroller, visit www.st.com website.

10/101

DocID027351 Rev 5

UM1855

2

Hardware layout and configuration

Hardware layout and configuration

Note:

The STM32L476G-EVAL evaluation board is designed around STM32L476ZGT6 target microcontroller in LQFP 144-pin package.

Figure 2 illustrates STM32L476ZGT6

connections with peripheral components.

Figure 3 shows the location of main components

on the evaluation board.

Figure 2. STM32L476G-EVAL hardware block diagram

65$0

125)ODVK

PHPRU\

¶¶FRORU

7)7/&'

4XDG63,

)ODVKP(PRU\

GHYLFH

/&'J/DVV

PRGXOH

[

6WDQGDUG%

86%

FRQQHFWRU

67/,1.9

-7$*WUDFHDQG

6:'FRQQHFWRUV

7RXFKVHQVLQJEXWWRQ

/'5

3RWHQWLRPHWHU

/('

.H\

EXWWRQ

PLFUR6'

FDUG

&$1WUDQVFHLYHU

DQGFRQQHFWRU

)0&

48$'63,

/&'

-7$*

86$57

')6'0

6$,

76&

$'&

2S$PS

&RPSDUDWRU

670/=*7

*3,2

6:3

6',2

0LIDUH

FRQQHFWRU

WUDQVFHLYHU

,U'$

WUDQVFHLYHU

6LJPDGHOWD

PRGXODWRU

6LJPDGHOWD

PRGXODWRU

FRQQHFWRU

3RZHUPHWHU

VHQVRU

WZRGLJLWDO0(06

PLFURSKRQHV

$XGLR

FRGHF

WZRVWHUHR

KHDGSKRQH

RXWSXWV

((3520

5)((3520

FRQQHFWRU

([SDQGHU

6PDUWFDUG

LQWHUIDFH

-R\VWLFN

7)7/&'

FRQWUROOHU

6PDUWFDUG

ZLWK6:3

7)7/&'

WRXFKVFUHHQ

86%SRZHU

VZLWFK

&$1

86%27*)6

86%0LFUR$%

FRQQHFWRU

([WHQVLRQ

FRQQHFWRUVIRU

*3,2V

*3,2

57& %DWWHU\

9UHJXODWRU

WR9

DGMXVWDEOH

UHJXODWRU

0&8

VXSSO\FXUUHQW

PHDVXUHPHQW

0RWRUFRQWURO

FRQQHFWRU

06Y9

If the STM32L476G-EVAL board version is greater than or equal to MB1144 C-02, the IrDA feature is not populated. Any mention of the IrDA feature in this User manual refers to the previous versions of the board (up to MB1144 C-01). The version of the board is written on the sticker placed on bottom side of the board.

DocID027351 Rev 5

11/101

100

Hardware layout and configuration

Figure 3. STM32L476G-EVAL main component layout

7RXFKVHQVLQJ

EXWWRQ

0RWRUFRQWURO

86%27*SRUW

670/=*7

6LJPDGHOWDLQ

&$1

([WHQVLRQ

FRQQHFWRUV

,U'$

1)&

PLFUR6'FDUG

3RZHUMDFN

8OHIW

PLFURSKRQH

)RXU/('V

9''VHWWLQJ

5HVHWEXWWRQ

UM1855

:DNHXSWDPSHU

EXWWRQ

-R\VWLFN

5)((3520

/'5

86$57

/&'JODVVPRGXOH

GDXJKWHUERDUG

&17UDFH

-7$*

7)7/&'

6WDQGDUG%

86%SRUWRI

67/,1.9

+HDGSKRQHV

MDFN

+HDGSKRQHV

MDFN

8ULJKW

PLFURSKRQH

3RWHQWLRPHWHU

06Y9

12/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

2.1 ST-LINK/V2-1

ST-LINK/V2-1 facility for debug and flashing of STM32L476ZGT6, is integrated on the

STM32L476G-EVAL evaluation board.

Compared to ST-LINK/V2 stand-alone tool available from STMicroelectronics,

ST-LINK/V2-1 offers new features and drops some others.

New features:

• USB software re-enumeration

• Virtual COM port interface on USB

• Mass storage interface on USB

• USB power management request for more than 100mA power on USB

Features dropped:

• SWIM interface

The USB connector CN17 can be used to power STM32L476G-EVAL regardless of the ST-LINK/V2-1 facility use for debugging or for flashing STM32L476ZGT6. This holds also when ST-LINK/V2 stand-alone tool is connected to CN12 or CN15 connector and used

for debugging or flashing STM32L476ZGT6. Section 2.3

provides more detail on powering

STM32L476G-EVAL.

For full detail on both versions of the debug and flashing tool, the stand-alone ST-LINK/V2 and the embedded ST-LINK/V2-1, refer to www.st.com

2.1.1 Drivers

Before connecting STM32L476G-EVAL to a Windows 7, Windows 8 or Windows XP PC via

USB, a driver for ST-LINK/V2-1 must be installed. It can be downloaded from www.st.com

In case the STM32L476G-EVAL evaluation board is connected to the PC before installing the driver, the Windows device manager may report some USB devices found on

STM32L476G-EVAL as “Unknown”. To recover from this situation, after installing the dedicated driver downloaded from www.st.com

, the association of “Unknown” USB devices found on STM32L476G-EVAL to this dedicated driver must be updated in the device manager manually. It is recommended to proceed using USB Composite Device line, as

shown in Figure 4

Figure 4. USB composite device

DocID027351 Rev 5

13/101

100

Hardware layout and configuration

2.1.2 ST-LINK/V2-1 firmware upgrade

UM1855

For its own operation, ST-LINK/V2-1 employs a dedicated MCU with Flash memory. Its firmware determines ST-LINK/V2-1 functionality and performance. The firmware may evolve during the life span of STM32L476G-EVAL to include new functionality, fix bugs or support new target microcontroller families. It is therefore recommended to keep ST-LINK/V2-1 firmware up to date. The latest version is available from www.st.com

The connector CN12 can output trace signals used for debug. By default, the evaluation board is configured such that, STM32L476ZGT6 signals PE2 through PE5 are not connected to trace outputs Trace_D0, Trace_D1, Trace_D2, Trace_D3 and Trace_CK of

CN12. They are used for other functions.

Table 1 shows the setting of configuration elements to shunt PE2, PE3, PE4 and PE5 MCU

ports to CN12 connector, to use them as debug trace signals.

Element

Table 1. Setting of configuration elements for trace connector CN12

Setting Use of PE2, PE3, PE4, PE5 terminals of STM32L476ZGT6

R103

SB26

R103 in

SB26 open

R103 out

SB26 closed

Default setting .

PE2 connected to LCDSEG38 and memory address line A23.

PE2 connected to TRACE_CK on CN12. A23 pulled down.

R104

R104 in

Default setting .

PE3 connected to LCDSEG39 and memory address line A19.

R84

SB40

R104 out PE3 connected to TRACE_D0 on CN12. A19 pulled down.

Default setting .

PE4 connected to memory address line A20.

R85

SB38

R86

SB39

R84 in

SB40 open

R84 out

SB40 closed

R85 in

SB38 open

R85 out

SB38 closed

R86 in

SB39 open

R86 out

SB39 closed

PE4 connected to TRACE_D1 on CN12. A20 pulled down.

Default setting .

PE5 connected to memory address line A21.

PE5 connected to TRACE_D2 on CN12. A21 pulled down.

Default setting .

PE6 is used for address bit A22.

PE6 connected to TRACE_D3 on CN12. A22 pulled down.

Warning : Enabling the CN12 trace outputs through hardware modifications described in

Table 1 results in reducing the memory address bus width to 19 address lines and so the

addressable space to 512 Kwords of 16 bits. As a consequence, the on-board SRAM and

NOR Flash memory usable capacity is reduced to 8 Mbits.

14/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

2.3.1

STM32L476G-EVAL evaluation board is designed to be powered from 5 V DC power source. It incorporates a precise polymer Zener diode (Poly-Zen) protecting the board from damage due to wrong power supply. One of the following four 5V DC power inputs can be used, upon an appropriate board configuration:

• Power jack CN22, marked PSU_E5V on the board. A jumper must be placed in PSU

location of JP17. The positive pole is on the center pin as illustrated in Figure 5

• Standard-B USB receptacle CN17 of ST-LINK/V2-1, offering enumeration feature described in

Section 2.3.1

• Micro-AB USB receptacle CN1 of USB OTG interface, marked OTG_FS on the board.

Up to 500mA can be supplied to the board in this way.

• Pin 28 of CN6 extension connector for custom daughterboards, marked D5V on the board.

No external power supply is provided with the board.

LD7 red LED turns on when the voltage on the power line marked as +5V is present. All supply lines required for the operation of the components on STM32L476G-EVAL are derived from that +5V line.

Table 2 describes the settings of all jumpers related with powering STM32L476G-EVAL and

extension board. VDD_MCU is STM32L476ZGT6 digital supply voltage line. It can be connected to either fixed 3.3 V or to an adjustable voltage regulator controlled with RV1 potentiometer and producing a range of voltages between 1.71 V and 3.6 V.

Supplying the board through ST-LINK/V2-1 USB port

To power STM32L476G-EVAL in this way, the USB host (a PC) gets connected with the

STM32L476G-EVAL board’s Standard-B USB receptacle, via a USB cable. This event starts the USB enumeration procedure. In its initial phase, the host’s USB port current supply capability is limited to 100 mA. It is enough because only ST-LINK/V2-1 part of

STM32L476G-EVAL draws power at that time. If the jumper header JP18 is open, the U37

ST890 power switch is set to OFF position, which isolates the remainder of

STM32L476G-EVAL from the power source. In the next phase of the enumeration procedure, the host PC informs the ST-LINK/V2-1 facility of its capability to supply up to

300 mA of current. If the answer is positive, the ST-LINK/V2-1 sets the U37 ST890 switch to

ON position to supply power to the remainder of the STM32L476G-EVAL board. If the PC

USB port is not capable of supplying up to 300 mA of current, the CN22 power jack can be used to supply the board.

Should a short-circuit occur on the board, the ST890 power switch protects the USB port of the host PC against a current demand exceeding 600 mA, In such an event, the LD9 LED lights on.

The STM32L476G-EVAL board can also be supplied from a USB power source not supporting enumeration, such as a USB charger. In this particular case, the JP18 header must be fitted with a jumper as shown in

Table 2

. ST-LINK/V2-1 turns the ST890 power switch ON regardless of enumeration procedure result and passes the power unconditionally to the board.

The LD7 red LED turns on whenever the whole board is powered.

DocID027351 Rev 5

15/101

100

Hardware layout and configuration

2.3.2

UM1855

Using ST-LINK/2-1 along with powering through CN22 power jack

It can happen that the board requires more than 300 mA of supply current. It cannot be supplied from host PC connected to ST-LINK/2-1 USB port for debugging or flashing

STM32L476ZGT6. In such a case, the board can be supplied through CN22 (marked PSU

_E5V on the board).

To do this, it is important to power the board before connecting it with the host PC, which requires the following sequence to be respected:

1. Set the jumper in JP15 header in PSU position

2. Connect the external 5 V power source to CN22

3. Check the red LED LD7 is turned on

4. Connect host PC to USB connector CN17

In case the board demands more than 300 mA and the host PC is connected via USB before the board is powered from CN22, there is a risk of the following events to occur, in the order of severity:

1. The host PC is capable of supplying 300 mA (the enumeration succeeds) but it does not incorporate any over-current protection on its USB port. It is damaged due to overcurrent.

2. The host PC is capable of supplying 300 mA (the enumeration succeeds) and it has a built-in over-current protection on its USB port, limiting or shutting down the power out of its USB port when the excessive current demand from STM32L476G-EVAL is detected. This causes an operating failure to STM32L476G-EVAL.

3. The host PC is not capable of supplying 300 mA (the enumeration fails) so

ST-LINK/V2-1 does not supply the remainder of STM32L476G-EVAL from its USB port

VBUS line.

Figure 5. CN22 power jack polarity

16/101

DocID027351 Rev 5

UM1855

Jumper array

JP17

Power source selector

Hardware layout and configuration

Table 2. Power-supply-related jumper settings

Jumper setting Configuration

JP17

STM32L476G-EVAL is supplied through CN22 power jack (marked PSU_E5V). CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.

3688967/.'9

JP17

STM32L476G-EVAL is supplied through CN1 Micro-AB

USB connector . CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.

3688967/.'9

JP17

3688967/.'9

Default setting .

STM32L476G-EVAL is supplied through CN17

Standard-B USB connector . CN6 extension connector does not pass the 5 V of STM32L476G-EVAL to daughterboard.

Check JP18 setting in Table 2 .

JP17

STM32L476G-EVAL is supplied through pin 28 of CN6 extension connector.

3688967/.'9

JP12

V bat

connection

JP17

3688967/.'9

JP12

STM32L476G-EVAL is supplied through CN22 power jack (marked PSU_E5V). CN6 extension connector passes the 5 V of STM32L476G-EVAL to daughterboard. Make sure to disconnect from the daughterboard any power supply that could generate conflict with the power supply on CN22 power jack.

V bat

is connected to battery.

JP12

Default setting .

V bat

is connected to V

DocID027351 Rev 5

17/101

100

Hardware layout and configuration UM1855

Jumper array

Table 2. Power-supply-related jumper settings (continued)

Jumper setting Configuration

JP2

Default setting .

VDD_MCU (VDD terminals of STM32L476ZGT6) is connected to fixed +3.3 V.

JP2

VDD_MCU connection

JP2

VDD_MCU is connected to voltage in the range from

+1.71 V to +3.6 V, adjustable with potentiometer RV1.

JP10

Default setting .

VDDA terminal of STM32L476ZGT6 is connected with

VDD_MCU.

JP10

VDDA connection

JP10

VDDA terminal of STM32L476ZGT6 is connected to

+3.3 V.

JP1

Default setting .

VDD_USB (VDDUSB terminal of STM32L476ZGT6) is connected with VDD_MCU.

JP1

VDD_USB connection

JP1

VDD_USB is connected to +3.3V.

JP3

Default setting .

VDD_IO (VDDIO2 terminals of STM32L476ZGT6) is connected with VDD_MCU JP3

VDD_IO connection

JP3

JP18

Powering through USB of

ST-LINK/V2-1

JP18

VDD_IO is open.

Default setting .

Standard-B USB connector CN17 of ST-LINK/V2-1 can supply power to the STM32L476G-EVAL board remainder, depending on host PC USB port’s powering capability declared in the enumeration.

Standard-B USB connector CN17 of ST-LINK/V2-1 supplies power to the STM32L476G-EVAL board remainder. Setting for powering the board through

CN17 using USB charger.

18/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Two clock references are available on STM32L476G-EVAL for the STM32L476ZGT6 target microcontroller:

• 32.768 kHz crystal X1, for embedded RTC

• 8 MHz crystal X2, for main clock generator

The main clock can also be generated using an internal RC oscillator. The X2 crystal is in a socket. It can be removed when the internal RC oscillator is used.

Solder bridge

Table 3. X1-crystal-related solder bridge settings

Setting Description

SB41

SB33

Open

Closed

Open

Closed

Default setting .

PC14-OSC32_IN terminal is not routed to extension connector CN7. X1 is used as clock reference.

PC14-OSC32_IN is routed to extension connector CN7.

R87 must be removed, for X1 quartz circuit not to disturb clock reference or source on daughterboard.

Default setting .

PC15-OSC32_OUT terminal is not routed to extension connector CN7.

X1 is used as clock reference.

PC15-OSC32_OUT is routed to extension connector CN7.

R88 must be removed, for X1 quartz circuit not to disturb clock reference on daughterboard.

Solder bridge

SB24

SB23

Table 4. X2-crystal-related solder bridge settings

Setting Configuration

Open

Closed

Open

Closed

Default setting .

PH0-OSC_IN terminal is not routed to extension connector CN7. X2 is used as clock reference.

PH0-OSC_IN is routed to extension connector CN7.

X2 and C54 must be removed, in order not to disturb clock reference or source on daughterboard.

Default setting .

PH1-OSC_OUT terminal is not routed to extension connector CN7. X2 is used as clock reference.

PH1-OSC_OUT is routed to extension connector CN7.

R95 must be removed, in order not to disturb clock reference or source on daughterboard.

Reset signal of the STM32L476G-EVAL board is active low.

DocID027351 Rev 5

19/101

100

Hardware layout and configuration UM1855

Sources of reset are:

• reset button B1

• JTAG/SWD connector CN15 and ETM trace connector CN12 (reset from debug tools)

• through extension connector CN7, pin 32 (reset from daughterboard)

• ST-LINK/V2-1

• RS-232 connector CN9, terminal 8 (CTS signal), if JP9 is closed (open by default)

2.6 Boot

After reset, the STM32L476ZGT6 MCU can boot from the following embedded memory locations:

• main (user, non-protected) Flash memory

• system (protected) Flash memory

• RAM, for debugging

The microcontroller is configured to one of the listed boot options by setting the

STM32L476ZGT6 port BOOT0 level by the switch SW1 and by setting nBOOT1 bit of

FLASH_OPTR option bytes register, as shown in

Table 5

. Depending on JP8, BOOT0 level can be forced high and, SW1 action overruled, by DSR line of RS-232 connector CN9, as

shown in Table 6 . This can be used to force the execution of bootloader and start user Flash

memory flashing process (ISP) from RS-232 interface.

The option bytes of STM32L476ZGT6 and their modification procedure are described in the reference manual RM0351. The application note AN2606 details the bootloader mechanism and configurations.

Switch

SW1

Setting

Table 5. Boot selection switch

Description

Default setting .

BOOT0 line is tied low. STM32L476ZGT6 boots from user Flash memory.

BOOT0 line is tied high. STM32L476ZGT6 boots from system Flash memory (nBOOT1 bit of FLASH_OPTR register is set high) or from

RAM (nBOOT1 is set low).

Jumper

JP8

Setting

JP8

Table 6. Bootloader-related jumper setting

Description

Default setting .

BOOT0 level only depends on SW1 switch position

JP8

BOOT0 can be forced high with terminal 6 of CN9 connector (RS-232

DSR line). This configuration is used to allow the device connected via

RS-232 to initiate STM32L476ZGT6 flashing process.

20/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Boot from system Flash memory results in executing bootloader code stored in the system

Flash memory protected against write and erase. This allows in-system programming (ISP), that is, flashing the MCU user Flash memory. It also allows writing data into RAM. The data come in via one of the communication interfaces such as USART, SPI, I

C bus, USB or

CAN.

Bootloader version can be identified by reading Bootloader ID at the address 0x1FFF6FFE.

The STM32L476ZGT6 part soldered on the STM32L476G-EVAL main board is marked with a date code corresponding to its date of manufacture. STM32L476ZGT6 parts with the date code prior or equal to week 22 of 2015 are fitted with bootloader V 9.0

affected by the limitations to be worked around, as described hereunder. Parts with the date code starting week 23 of 2015 contain bootloader V9.2 in which the limitations no longer exist.

To locate the visual date code information on the STM32L476ZGT6 package, refer to its datasheet (DS10198) available on www.st.com

, section Package Information. Date code related portion of the package marking takes Y WW format, where Y is the last digit of the year and WW is the week. For example, a part manufactured in week 23 of 2015 bares the date code 5 23.

Bootloader ID of the bootloader V 9.0 is 0x90.

The following limitations exist in the bootloader V 9.0:

RAM data get corrupted when written via USART/SPI/I2C/USB interface

Description:

Data write operation into RAM space via USART, SPI, I

C bus or USB results in wrong or no data written.

Workaround:

To correct the issue of wrong write into RAM, download STSW-STM32158 bootloader

V 9.0 patch package from www.st.com

and load "Bootloader V9.0 SRAM patch" to the

MCU, following the information in readme.txt file available in the package.

User Flash memory data get corrupted when written via CAN interface

Description:

Data write operation into user Flash memory space via CAN interface results in wrong or no data written.

Workaround:

To correct the issue of wrong write into Flash memory, download STSW-STM32158 bootloader V 0.9 patch package from www.st.com

and load "Bootloader V9.0 CAN patch" to the MCU, following the information in readme.txt file available in the package.

2.7 Audio

A codec connected to SAI interface of STM32L476ZGT6 supports TDM feature of the SAI port. TDM feature offers to STM32L476ZGT6 the capability to stream two independent stereo audio channels to two separate stereo analog audio outputs, simultaneously.

There are two digital microphones on board of STM32L476G-EVAL.

DocID027351 Rev 5

21/101

100

Hardware layout and configuration UM1855

U35 and U36 on board of STM32L476G-EVAL are MP34DT01TR MEMS digital omnidirectional microphones providing PDM (pulse density modulation) outputs. To share the same data line, their outputs are interlaced. The combined data output of the microphones is directly routed to STM32L476ZGT6 terminals, thanks to the integrated input digital filters.

The microphones are supplied with programmable clock generated directly by

STM32L476ZGT6.

As an option, the microphones can be connected to U29, Wolfson audio codec device,

WM8994. In that configuration, U29 also supplies the PDM clock to the microphones.

Regardless of where the microphones are routed to, STM32L476ZGT6 or WM8994, they can be power-supplied from either VDD or MICBIAS1 output of the WM8994 codec device.

Table 7 shows settings of all jumpers associated with the digital microphones on the board.

Jumper

Table 7. Digital microphone-related jumper settings

Setting Configuration

JP14

Default setting .

PDM clock for digital microphones comes from STM32L476ZGT6

JP14

PDM clock for digital microphones comes from WM8994 codec.

JP16

Default setting .

Power supply of digital microphones is VDD.

JP16

Power supply of digital microphones is generated by WM8994 codec.

22/101

The STM32L476G-EVAL evaluation board can drive two sets of stereo headphones.

Identical or different stereo audio content can be played back in each set of headphones.

The STM32L476ZGT6 sends up to two independent stereo audio channels, via its SAI1

TDM port, to the WM8994 codec device. The codec device converts the digital audio stream to stereo analog signals. It then boosts them for direct drive of headphones connecting to

3.5 mm stereo jack receptacles on the board, CN20 for Audio-output1 and CN21 for

Audio_output2. Figure 6 shows a top view of the CN20 and CN21 headphones jack

receptacles.

The CN21 jack takes its signal from the output of the WM8994 codec device intended for driving an amplifier for loudspeakers. A hardware adaptation is incorporated on the board to make it compatible with a direct headphone drive. The adaptation consists of coupling capacitors blocking the DC component of the signal, attenuator and anti-pop resistors. The loudspeaker output of the WM8994 codec device must be configured by software in linear mode called “class AB” and not in switching mode called “class D”.

The I ² C-bus address of WM8994 is 0b0011010.

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Figure 6. CN20, CN21 top view

+HDGSKRQHVMDFN

5LJKW

FKDQQHO

/HIW

FKDQQHO

*1'

+HDGSKRQHVMDFN

(YDOXDWLRQERDUG

06Y9

2.8

2.8.1

Due to the share of some terminals of STM32L476ZGT6 by multiple peripherals, the following limitations apply in using the audio features:

• If the SAI1_SDA is used as part of SAI1 port, it cannot be used as FMC_NWAIT signal for NOR Flash memory device. However, FMC_NWAIT is not necessary for operating the NOR Flash memory device. More details on FMC_NWAIT are available in

Section 2.22: NOR Flash memory device

• If the SAI1 port of STM32L476ZGT6 is used for streaming audio to the WM8994 codec

IC, STM32L476ZGT6 cannot control the motor.

• If the digital microphones are attached to STM32L476ZGT6, the LCD glass module cannot be driven.

USB OTG FS port

The STM32L476G-EVAL board supports USB OTG full-speed (FS) communication. The

USB OTG connector CN1 is of Micro-AB type.

STM32L476G-EVAL used as USB device

When a “USB host” connection to the CN1 Micro-AB USB connector of STM32L476G-EVAL is detected, the STM32L476G-EVAL board starts behaving as “USB device”. Depending on the powering capability of the USB host, the board can take power from VBUS terminal of

CN1. In the board schematic diagrams, the corresponding power voltage line is called U5V.

Section 2.3

provides information on how to set associated jumpers for this powering option.

The JP19 jumper must be left open to prevent STM32L476G-EVAL from sourcing 5 V to

VBUS terminal, which would cause conflict with the 5 V sourced by the USB host. This may

DocID027351 Rev 5

23/101

100

Hardware layout and configuration

2.8.2

UM1855 happen if the PC6 GPIO is controlled by the software of the STM32L476ZGT6 such that, it enables the output of U1 power switch.

STM32L476G-EVAL used as USB host

When a “USB device” connection to the CN1 Micro-AB USB connector is detected, the

STM32L476G-EVAL board starts behaving as “USB host”. It sources 5 V on the VBUS terminal of CN1 Micro-AB USB connector to power the USB device. For this to happen, the

STM32L476ZGT6 MCU sets the U1 power switch STMPS2151STR to ON state. The LD5 green LED marked VBUS indicates that the peripheral is supplied from the board. The LD6 red LED marked FAULT lights up if over-current is detected. The JP19 jumper must be closed to allow the PC6 GPIO to control the U1 power switch.

In any other STM32L476G-EVAL powering option, the JP19 jumper should be open, to avoid accidental damage caused to an external USB host.

The following STM32L476ZGT6 terminals related with USB OTG FS port control are shared by other resources of the STM32L476G-EVAL board:

• PB12, used as USB over-current input (USBOTG_OVRCR signal); it is shared with

SWP, touch sensing, LCD glass module and motor control resources

• PB13, used as USB power ready input (USBOTG_PRDY signal); it is shared with NFC, touch sensing and LCD glass module resources

• PC6, used as USB power switch control (USBOTG_PPWR signal); it is shared with touch sensing, LCD glass module and motor control

Configuration elements related with the USB OTG FS port, such as jumpers, solder bridges and zero-ohm resistors, shunt the shared ports toward different resources or determine the operating mode of the USB OTG FS port. By default, they are set such as to enable the

USB OTG FS port operation where STM32L476G-EVAL plays USB device role and can be

connected to a USB host. Table 8 gives an overview of all configuration elements related

with the USB OTG FS port. The LCD glass module daughterboard should be connected in

I/O position.

USBOTG_OVRCR and USBOTG_PRDY signals, requiring the PB12 and PB13 ports of

STM32L476ZGT6, are only exploited when STM32L476G-EVAL acts as USB host. That is why, the USB host function of STM32L476G-EVAL is exclusive with alternate functions also requiring PB12 and PB13 ports of STM32L476ZGT6 - NFC, touch sensing, motor control,

SWP.

The PB12 and PB13 ports of STM32L476ZGT6 are not required for the USB OTG FS port operating as USB device.

Element

JP19

Table 8. Configuration elements related with USB OTG FS port

Setting Description

Open

Closed

USB OTG FS port can be connected with a USB host and get power from it. If connected with USB device, STM32L476G-EVAL cannot supply power to it.

Default setting.

USB OTG FS port can be connected with a USB device and supply power to it. It must not be connected with USB host.

24/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 8. Configuration elements related with USB OTG FS port (continued)

Element Setting Description

R36

R39

R38

Out

Default setting

PC6 is shunted to control the U1 power switch, transiting through the

LCD glass module daughterboard connector.

LCD glass module daughterboard should be in I/O position, with SB2 and SB27 open.

PC6 is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing (SB2 closed) or motor control (SB27 closed).

Default setting .

PB12 receives USBOTG_OVRCR signal from U1 power switch, transiting through the LCD glass module daughterboard connector.

SB3 should be open, R109 in, no smartcard in CN23 slot.

PB12 is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing or motor control (SB3 closed).

Default setting .

PB13 receives USBOTG_PRDY signal from CN1 connector, transiting through the LCD glass module daughterboard connector.

SB6 should be open and no daughterboard inserted in CN13 NFC connector.

PB13 s disconnected from the LCD glass module daughterboard connector. It can be shunted to touch sensing (SB6 closed).

• The USB OTG FS port operation as USB host is exclusive with NFC, SWP, LCD glass module, touch sensing, motor control

• The USB OTG FS port operation as USB device is exclusive with LCD glass module, touch sensing, motor control

2.9

The USB-related operating supply voltage of STM32L476ZGT6 (VDD_USB line) must be within the range from 3.0 V to 3.6 V.

RS-232 and IrDA ports

The STM32L476G-EVAL board offers one RS-232 communication port and one IrDA port.

If the STM32L476G-EVAL board version is greater than or equal to

MB1144 C-02, the IrDA transceiver (TFDU6300) is not populated, but it is possible to solder manually the TDFU6300 on U11 footprint to support IRDA feature.

DocID027351 Rev 5

25/101

100

Hardware layout and configuration UM1855

The RS-232 communication port uses the DE-9M 9-pole connector CN9. RX, TX, RTS and

CTS signals of USART1 port of STM32L476ZGT6 are routed to CN9.

Bootloader_RESET_3V3 and Bootloader_BOOT0_3V3 signals can also be routed to CN9, for ISP (in-system programming) support. To route Bootloader_RESET_3V3 to CN9, the

R93 resistor must be removed and the JP9 jumper closed (open by default). To route

Bootloader_BOOT0_3V3 to CN9, the JP8 jumper must be closed.

For configuration elements related with the RS-232 port operation, refer to

Table 6

and

Table 9 .

Section 2.10

brings information on using the LPUART port of STM32L476ZGT6 for RS-232, instead of its USART1 port.

The IrDA communication port uses an IrDA transceiver (U11). Table 9 shows the

configuration elements related with the IrDA port operation

Table 9. Settings of configuration elements for RS-232 and IrDA ports

Element Setting Description

JP15

Default setting.

RS-232 selected: PB7 port of STM32L476ZGT6 receives signal originating from RXD terminal of CN9.

JP15

IrDA selected: PB7 port of STM32L476ZGT6 is connected with RxD terminal of the IrDA transceiver U11.

NFC selected: PB7 port of STM32L476ZGT6 receives NFC_IRQOUT signal from NFC peripheral.

Section 2.28

provides more detail on the

NFC peripheral.

R93, R118,

R116

R158, R119

Out

Required for IrDA operation

2.9.3 Limitations

The operation of RS-232 and IrDA ports is mutually exclusive. The operation of either port is also mutually exclusive with the NFC peripheral operation.

26/101

The RS-232- and IrDA-related operating supply voltage of STM32L476ZGT6 (VDD line) must be within the range from 1.71 V to 3.6 V.

DocID027351 Rev 5

UM1855 Hardware layout and configuration

On top of USART1 port for serial communication, the STM32L476ZGT6 offers LPUART, a low-power UART port.

In the default configuration of STM32L476G-EVAL, the RX and TX terminals of the LPUART port are routed to the USB virtual COM port of ST-LINK/V2-1 and, the RX and TX terminals of USART1 port to the RS-232 connector CN9.

For specific purposes, the TX and RX of the LPUART port of STM32L476ZGT6 can be routed to the RS-232 connector CN9 instead. As RTS and CTS terminals of CN9 keep routed to USART1 port, they may block the LPUART communication flow. To avoid this, set the USART1 hardware flow control off.

The default settings of LPUART are: 115200b/s, 8bits, no parity, 1 stop bit, no flow control.

Table 10. Hardware settings for LPUART

LPUART port use R188 R189 R158 R119

Default setting

USB virtual COM port of ST-LINK/V2-1

RS-232 (RX and TX)

Out

R118 JP15 1-2

Do not care

Out

Do not care

Closed

The CN18 slot for microSD card is routed to STM32L476ZGT6’s SDIO port, accepting SD

(up to 2 Gbytes), SDHC (up to 32 Gbytes) and SDXC (up to 2 Tbytes) cards. One 4-Gbyte microSD card is delivered as part of STM32L476G-EVAL. The card insertion switch is routed to the PA8 GPIO port.

Terminal

Table 11. Terminals of CN18 microSD slot

Terminal name (MCU port) Terminal Terminal name (MCU port)

SDIO_D2 (PC10)

SDIO_D3 (PC11)

SDIO_CMD (PD2)

VDD

SDIO_CLK (PC12)

Vss/GND

SDIO_D0 (PC8)

SDIO_D1 (PC9)

GND

MicroSDcard_detect (PA8)

For microSD card operation, the LCD glass module daughterboard must be plugged into

CN11 and CN14 in I/O-bridge position, as explained in

Section 2.15

2.11.1 Limitations

Due to the share of SDIO port and PA8 terminals, the following limitations apply:

• The microSD card cannot be operated simultaneously with LCD glass module or with motor control.

• The microSD card insertion cannot be detected when the PA8 is used as microcontroller clock output (MCO), one of alternate functions of PA8.

DocID027351 Rev 5

27/101

100

Hardware layout and configuration UM1855

The supply voltage for STM32L476G-EVAL microSD card operation must be within the range from 2.7 V to 3.6 V.

The CN2 connector is designed to receive a motor control (MC) module. Table 12 shows the

assignment of CN2 and STM32L476ZGT6 terminals.

Table 12 also lists the modifications to be made on the board versus its by-default

configuration. See

Section 2.12.1

for further details.

Table 12. Motor control terminal and function assignment

Motor control connector CN2

STM32L476ZGT6 microcontroller

Terminal

Terminal name

Emergency

Stop

GND

Port name Function

PC9

TIM8_BKIN2

GND

PWM_1H

GND

PWM_1L

GND

PWM_2H

GND

PWM_2L

GND

PWM_3H

GND

PWM_3L

Bus Voltage

PC6

PA7

PC7

PB0

PC8

PB1

PC5

TIM8_CH1

GND

TIM8_CH1N

GND

TIM8_CH2

GND

TIM8_CH2N

GND

TIM8_CH3

GND

TIM8_CH3N

ADC12_IN

Alternate function

Board modifications for enabling motor control

Close SB29

Remove MB979 daughterboard

Close SB27

Open SB2

Remove MB979 daughterboard

Close SB19

Open SB18

Remove R66

Close SB30

Open SB4

Remove R33

Close SB15

Open SB14

Remove R62

Close SB28

Remove MB979 daughterboard

Close SB13

Open SB12

Close SB16

Remove MB979 daughterboard

28/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 12. Motor control terminal and function assignment (continued)

Motor control connector CN2

STM32L476ZGT6 microcontroller

Terminal

Terminal name

PhaseA current+

PhaseA current-

PhaseB current+

PhaseB current-

PhaseC current+

PhaseC current-

Port name Function

PC0

PC1

PC2

ADC123_IN

GND

ADC123_IN

GND

ADC123_IN

GND

Alternate function

Board modifications for enabling motor control

Close SB34

Remove MB979 daughterboard

Close SB42

Remove MB979 daughterboard

Close SB36

ICL Shutout

GND

Dissipative

Brake

PFC ind. curr.

+5V

Heatsink

Temp.

PFC Sync

+3.3V

PFC PWM

PFC

Shutdown

Encoder A

PFC Vac

Encoder B

Encoder

Index

PG6

PB2

PC4

PA3

PF9

PF10

PB12

PA0

PA6

PA1

PA2

GPIO

GND

GPIO

ADC12_IN

+5V

ADC12_IN

TIM15_CH1

+3.3V

TIM15_CH2

TIM15_BKIN -

TIM2_CH1 ADC12_IN

ADC12_IN -

TIM2_CH2 ADC12_IN

TIM2_CH3 ADC12_IN

Close SB5

Remove R35

Close SB11

Remove R54

Close SB17

Remove MB979 daughterboard

Close SB22

Remove MB979 daughterboard

Close SB25

Remove R90

Close SB37

Remove R91

Close SB3

Remove MB979 daughterboard

Close SB35

Remove R83

Close SB20

Open SB21

Remove MB979 daughterboard

Close SB32

Remove MB979 daughterboard

Close SB31

Remove MB979 daughterboard

DocID027351 Rev 5

29/101

100

Hardware layout and configuration UM1855

Figure 7 (top side) and

Figure 8 (bottom side) illustrate the board modifications listed in

Table 12 , required for the operation of motor control. Red color denotes a component to be

remove. Green color denotes a component to be fitted.

Figure 7. PCB top-side rework for motor control

30/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Figure 8. PCB underside rework for motor control

2.12.2 Limitations

Motor control operation is exclusive with LCD glass module, Quad-SPI Flash memory device, audio codec, potentiometer, LDR, smartcard, LED1 drive and the use of sigma-delta modulators.

2.13 CAN

The STM32L476G-EVAL board supports one CAN2.0A/B channel compliant with CAN specification. The CN5 9-pole male connector of DE-9M type is available as CAN interface.

A 3.3 V CAN transceiver is fitted between the CN5 connector and the CAN controller port of

STM32L476ZGT6.

The JP4 jumper allows selecting one of high-speed, standby and slope control modes of the

CAN transceiver. The JP6 jumper can fit a CAN termination resistor in.

DocID027351 Rev 5

31/101

100

Hardware layout and configuration

Jumper

JP4

JP6

Setting

JP4

Table 13. CAN related jumpers

Configuration

Default setting

CAN transceiver operates in high-speed mode

JP4

CAN transceiver is in standby mode

JP6

No termination resistor on CAN physical link

JP6

Default setting

Termination resistor fitted on CAN physical link

2.13.1 Limitations

CAN operation is exclusive with LCD glass module operation.

UM1855

The supply voltage for STM32L476G-EVAL CAN operation must be within the range from

3.0 V to 3.6 V.

The CN6 and CN7 headers complement the LCD glass module daughterboard connector, to give access to all GPIOs of the STM32L476ZGT6 microcontroller. In addition to GPIOs, the following signals and power supply lines are also routed on CN6 or CN7:

• GND

• +3V3

• DSV

• RESET#

• VDD

• Clock terminals PC14-OSC32_IN, PC15-OSC32_OUT, PH0-OSC_IN, PH1-OSC_OUT

Each header has two rows of 20 pins, with 1.27 mm pitch and 2.54 mm row spacing. For extension modules, SAMTEC RSM-120-02-L-D-xxx and SMS-120-x-x-D can be recommended as SMD and through-hole receptacles, respectively ( x is a wild card).

2.15 LCD glass module daughterboard

The MB979 daughterboard delivered in the STM32L476G-EVAL package bears a segmented LCD glass module. The daughterboard inserts into CN11 and CN14 extension headers of the main board, each having two rows of pins. The corresponding female

32/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration connectors on the daughterboard have three rows of holes each. One raw is routed to segments of the LCD. The other two rows are interconnected and form a series of jumpers.

The way of inserting the LCD glass module daughterboard into CN11 and CN14 headers determines two functions of LCD glass module daughterboard. In its display function,

STM32L476ZGT6 terminals are routed to LCD segments. In its I/O-bridge function, they are not. Instead, they transit from one row of CN11 pins to the other and from one row of CN14 pins to the other, thanks to interconnections fitted by the LCD glass module daughterboard.

Figure 9 shows how the LCD glass module daughterboard must be positioned for display

function. This position is designated in the document as display position .

Figure 10

shows how the LCD glass module daughterboard must be positioned for I/Obridge function. This position is designated in the document as I/O-bridge position .

The arrow indicates the side of the CN11 and CN14 headers where the extra row of holes of each female counterpart on the LCD glass module daughterboard has to protrude.

When the LCD glass module daughterboard is not plugged in, CN11 and CN14 give access to ports of the target microcontroller.

Figure 36

shows the related schematic diagram.

Table 14 shows the default settings of board configuration elements linked with CN11 and

CN14 extension connectors and LCD glass module daughterboard.

Figure 9. LCD glass module daughterboard in display position

DocID027351 Rev 5

33/101

100

Hardware layout and configuration

Figure 10. LCD glass module daughterboard in I/O-bridge position

UM1855

34/101

LCD segment

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG10

Table 14. LCD-daughterboard-related configuration elements

Element

Setting to enable

LCD glass module

Description

Open

SB20

R66

SB18

SB19

R62

SB14

SB15

R56

R82

SB32

R81

SB31

R78

SB22

R68

SB21

SB12

SB13

R50

SB9

PA1 routed to LCDSEG0

PA1 not routed to motor control

PA2 routed to LCDSEG1

PA2 not routed to motor control

PA3 routed to LCDSEG2

PA3 not routed to motor control

PA6 routed to LCDSEG3

PA6 not routed to Quad-SPI Flash memory device

PA6 not routed to motor control

PA7 routed to LCDSEG4

PA7 not routed to Quad-SPI Flash memory device

PA7 not routed to motor control

PB0 routed to LCDSEG5

PB0 not routed to Quad-SPI Flash memory device

PB0 not routed to motor control

PB1 routed to LCDSEG6

PB1 not routed to Quad-SPI Flash memory device

PB1 not routed to motor control

PB10 routed to LCDSEG10

PB10 not routed to Quad-SPI Flash memory device

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 14. LCD-daughterboard-related configuration elements (continued)

LCD segment

Element

Setting to enable

LCD glass module

Description

SEG11

SEG12

SEG13

SEG18

SEG19

SEG20

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG38

SEG39

Open

SB28

SB29

R103

SB26

R104

R36

SB2

SB27

R33

SB4

SB30

R98

SB36

R99

SB42

R65

SB17

R64

SB16

R48

SB8

R39

SB3

R38

SB6

R97

SB34

PB11 routed to LCDSEG11

PB11 not routed to Quad-SPI Flash memory device

PB12 routed to LCDSEG12

PB12 not routed to Quad-SPI Flash memory device

PB13 routed to LCDSEG13

PB13 not routed to Touch sensing

PC0 routed to LCDSEG18

PC0 not routed to motor control

PC1 routed to LCDSEG19

PC1 not routed to motor control

PC2 routed to LCDSEG20

PC2 not routed to motor control

PC4 routed to LCDSEG22

PC4 not routed to motor control

PC5 routed to LCDSEG23

PC5 not routed to motor control

PC6 routed to LCDSEG24

PC6 not routed to Touch sensing

PC6 not routed to for motor control

PC7 routed to LCDSEG25

PC7 not routed to Touch sensing

PC7 not routed to for motor control

PC8 not routed to motor control

PC9 not routed to motor control

PE2 routed to LCDSEG38

PE2 not routed to Trace

PE3 routed to LCDSEG39

The custom LCD glass module used on MB979 daughterboard is XHO5002B. To optimize the number of driving signals, the display elements are connected to eight common planes called COMx (LCDCOMx in the schematic diagrams), where “x” can be substituted with figures from “0” to “7”. The other pole of each display element is called segment, SEGy

(LCDSEGy in the schematic diagrams), where “y” can be substituted with figures from “0” to

“39”. Each combination of COMx and SEGy addresses one display element.

Table 15

Table 16 , Table 17

and

Table 22 show the LCD element mapping. COMx are ordered in

rows, SEGy in columns. The table cells then display the display element names

DocID027351 Rev 5

35/101

100

Hardware layout and configuration UM1855 corresponding to each COMx and SEGy combination. Names in quoting marks denote

elements forming textual symbols, for example “µA” or “+”. Figure 11 shows the physical

location and shape of each segment on the LCD glass module.

Table 15. LCD glass element mapping - segments 0 to 9

SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9

COM0

COM1

COM2 13b

COM3 13a

COM4

COM5

COM6

COM7

12b

12a

11b

11a

16b

16a

15b

15a

14b

14a

“nA”

19b

19a

18b

18a

17b

17a

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

Table 16. LCD glass element mapping - segments 10 to 19

SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19

“+”

“-”

“µA”

“mA”

10b

10a

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

Table 17. LCD glass element mapping - segments 20 to 29

SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29

36/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 18. LCD glass element mapping - segments 30 to 39

SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39

COM0 10e

COM1 10f

COM2 10c

COM3 10d

COM4

COM5

10j

10i

COM6 10h

COM7 10g

11j

11i

11h

11g

11e

11f

11c

11d

12j

12i

12h

12g

12e

12f

12c

12d

13j

13i

13h

13g

13e

13f

13c

13d

14j

14i

14h

14g

14e

14f

14c

14d

15j

15i

15h

15g

15e

15f

15c

15d

16j

16i

16h

16g

16e

16f

16c

16d

17j

17i

17h

17g

17e

17f

17c

17d

18j

18i

18h

18g

18e

18f

18c

18d

19j

19i

19h

19g

19e

19f

19c

19d

2.15.1 Limitations

LCD glass module operation is exclusive with all other features of the board.

DocID027351 Rev 5

37/101

100

Figure 11. LCD glass display element mapping

)

(

0 1

D D D D D D D D D D D D D D D D D

M M M M M M M M M M M M M M M M M

)

0 1

(

06Y9

UM1855 Hardware layout and configuration

2.16 TFT LCD panel

STM32L476G-EVAL is delivered with MB989P, a daughterboard plugged into the CN19 extension connector. It bears a TFT 2.8-inch color LCD panel with resistive touchscreen and an on-board controller.

Section 2.18

provides further information.

Thanks to level shifters on all signal lines, the TFT LCD panel can operate with the entire operating voltage range of STM32L476G-EVAL.

The TFT LCD panel is attached to the 16-bit data bus and accessed with FMC. The base address is 0x6800 0000, corresponding to NOR/SRAM3 bank1. The panel is selected with

LCD_NE3 chip select signal generated by PG10 port of the STM32L476ZGT6. Address lines A0 and A1 determine the panel resources addressed, as depicted in

Table 19 .

Table 20 gives the CN19 extension connector terminal assignment.

Table 19. Access to TFT LCD resources with FMC address lines A0 and A1

Address A1 A0 Usage

0x6800_0000

0x6800_0002

0x6800_0004

0x6800_0006

Read register

Read Graphic RAM (GRAM)

Write register

Write graphic RAM (GRAM)

CN19 terminal

Table 20. Assignment of CN19 connector terminals of TFT LCD panel

Terminal name

MCU port

CN19 terminal

Terminal name

MCU port

CSN

WRN

RSTN

D11

D13

D15

BL_CONTROL

+3V3

GND

SDO

PG10

PD5

RESET#

PD15

PD1

PE8

PE10

PE12

PE14

PD8

PD10

I/O expander_X-

I/O expander_Y-

D12

D14

BL_GND

+3V3

BL_VDD

RDN

D10

SDI

PE15

PD9

PF0

PD4

PD14

PD0

PE7

PE9

PE11

PE13

I/O expander_X+

I/O expander_Y+

DocID027351 Rev 5

39/101

100

Hardware layout and configuration UM1855

Four general-purpose color LEDs (LD1, LD2, LD3, LD4) are available as light indicators.

Each LED is in light-emitting state with low level of the corresponding control port. They are controlled either by the STM32L476ZGT6 or by the I/O expander IC U32, named

IOExpander1 in the schematic diagram. Table 21

gives the assignment of control ports to the LED indicators.

Table 21. Port assignment for control of LED indicators

User LED Control port Control device

LED1 (Green)

LED2 (Orange)

LED3 (Red)

LED4 (Blue)

PB2

GPIO0

PC1

GPIO2

STM32L476ZGT6

IOExpander1

STM32L476ZGT6

IOExpander1

2.18 Physical input devices

The STM32L476G-EVAL board provides a number of input devices for physical human control. These are:

• four-way joystick controller with select key (B3)

• wake-up/ tamper button (B2)

• reset button (B1)

• resistive touchscreen of the TFT LCD panel

• 10 k Ω potentiometer (RV3)

• light-dependent resistor, LDR (R52)

Table 22 shows the assignment of ports routed to the physical input devices. They are either

ports of the STM32L476ZGT6 or of one of the two I/O expander ICs on the board, named, in the schematic diagrams, IOExpander1 and IOExpander2.

Table 22. Port assignment for control of physical input devices

Input device Control port Control device

Joystick SEL

Joystick DOWN

Joystick LEFT

Joystick RIGHT

Joystick UP

Wake-up/ tamper B2

Reset B1

Resistive touch screen X+

Resistive touch screen X-

Resistive touch screen Y+

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

PC13

NRST

X+

X-

Y+

IOExpander2

STM32L476ZGT6

IOExpander1

40/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 22. Port assignment for control of physical input devices (continued)

Input device Control port Control device

Resistive touch screen Y-

Potentiometer

LDR

Y-

PB4 or PA0

PA0 or PB4

IOExpander1

STM32L476ZGT6

The potentiometer and the light-dependent resistor can be routed, mutually exclusively, to either PB4 or to PA0 port of STM32L476ZGT6.

Table 23 depicts the setting of associated

configuration jumpers.

As illustrated in the schematic diagram in

Figure 46 , the PB4 port is routed, in the

STM32L476ZGT6, to the non-inverting input of comparator Comp2. The PA0 is routed to non-inverting input of operational amplifier OpAmp1. However, depending on register settings, it can also be routed to ADC1 or to ADC2.

Jumper

Table 23. Setting of jumpers related with potentiometer and LDR

Setting Routing

JP5 JP7

JP5

JP7

Potentiometer is routed to pin PB4 of STM32L476ZGT6.

JP5

JP5

JP7

JP5

JP7

JP5

JP7

Default setting.

Potentiometer is routed to pin PA0 of STM32L476ZGT6.

JP7

LDR is routed to pin PB4 of STM32L476ZGT6.

JP5 JP7

JP5

JP7

LDR is routed to pin PA0 of STM32L476ZGT6.

2.18.1 Limitations

The potentiometer and the light-dependent resistor are mutually exclusive.

2.19 Operational amplifier and comparator

STM32L476ZGT6 provides two on-board operational amplifiers, one of which, OpAmp1, is made accessible on STM32L476G-EVAL. OpAmp1 has its inputs and its output routed to

I/O ports PA0, PA1 and PA3, respectively. The non-inverting input PA0 is accessible on the terminal 1 of the JP7 jumper header. On top of the possibility of routing either of the

DocID027351 Rev 5

41/101

100

Hardware layout and configuration UM1855 potentiometer or LDR to PA0, en external source can also be connected to it, using the terminal 1 of JP7.

The PA3 output of the operational amplifier can be accessed on test point TP9. Refer to the schematic diagram in

Figure 46

The gain of OpAmp1 is determined by the ratio of the variable resistor RV2 and the resistor

R121, as shown in the following equation:

Gain

( RV2 ) ÷ ( R121 )

With the RV2 ranging from 0 to 10 k Ω and R121 being 1 k Ω , the gain can vary from 1 to 11.

The R63 resistor in series with PA0 is beneficial for reducing the output offset.

2.19.2 Comparator

STM32L476ZGT6 provides two on-board comparators, one of which, Comp2, is made accessible on STM32L476G-EVAL. Comp2 has its non-inverting input and its output routed to I/O ports PB4 and PB5, respectively. The input is accessible on the terminal 3 of the JP7 jumper header. On top of the possibility of routing either the potentiometer or LDR to PB4, an external source can also be connected to it, using the terminal 3 of JP7.

The PB5 output of the comparator can be accessed on test point TP6. Refer to the schematic diagram in

Figure 46

2.20 Analog input, output, VREF

STM32L476ZGT6 provides on-board analog-to-digital converter, ADC and, digital-to-analog converter, DAC. The port PA4 can be configured to operate either as ADC input or as DAC output. PA4 is routed to the two-way header CN8 allowing to fetch signals to or from PA4 or to ground it by fitting a jumper into CN8.

Parameters of the ADC input low-pass filter formed with R72 and C47 can be modified by replacing these components according to application requirements. Similarly, parameters of the DAC output low-pass filter formed with R73 and C47 can be modified by replacing these components according to application requirements.

The VREF+ terminal of STM32L476ZGT6 is used as reference voltage for both ADC and

DAC. By default, it is routed to VDDA through a jumper fitted into the two-way header CN10.

The jumper can be removed and an external voltage applied to the terminal 1 of CN10, for specific purposes.

42/101

IS61WV102416BLL, a 16-Mbit static RAM (SRAM), 1 M x16 bit, is fitted on the

STM32L476G-EVAL main board, in U2 position. The STM32L476G-EVAL main board as well as the addressing capabilities of FMC allow hosting SRAM devices up to 64 Mbytes.

This is the reason why the schematic diagram in Figure 41

mentions several SRAM devices.

The SRAM device is attached to the 16-bit data bus and accessed with FMC. The base address is 0x6000 0000, corresponding to NOR/SRAM1 bank1. The SRAM device is

DocID027351 Rev 5

UM1855 Hardware layout and configuration selected with FMC_NE1 chip select. FMC_NBL0 and FMC_NBL1 signals allow selecting 8bit and 16-bit data word operating modes.

By removal of R18, a zero-ohm resistor, the SRAM is deselected and the STM32L476ZGT6 ports PD7, PE0 and PE1 corresponding to FMC_NE1, FMC_NBL0 and FMC_NBL1 signals, respectively, can be used for other application purposes.

Resistor

R18

Fitting

Out

Table 24. SRAM chip select configuration

Configuration

Default setting.

SRAM chip select is controlled with FMC_NE1

SRAM is deselected. FMC_NE1 is freed for other application purposes.

2.21.1 Limitations

The SRAM addressable space is limited if some or all of A19, A20, A21, A22 and A23 FMC address lines are shunted to the CN12 connector for debug trace purposes. In such a case, the disconnected addressing inputs of the SRAM device are pulled down by resistors.

Section 2.2

provides information on the associated configuration elements.

The SRAM device operating voltage is in the range from 2.4 V to 3.6 V.

2.22 NOR Flash memory device

M29W128GL70ZA6E, a 128-Mbit NOR Flash memory, 8 M x16 bit, is fitted on the

STM32L476G-EVAL main board, in U5 position. The STM32L476G-EVAL main board as well as the addressing capabilities of FMC allow hosting M29W256GL70ZA6E, a 256-Mbit

NOR Flash memory device. This is the reason why the schematic diagram in Figure 41

mentions both devices.

The NOR Flash memory device is attached to the 16-bit data bus and accessed with FMC.

The base address is 0x6400 0000, corresponding to NOR/SRAM2 bank1. The NOR Flash memory device is selected with FMC_NE2 chip select signal. 16-bit data word operation mode is selected by a pull-up resistor connected to BYTE terminal of NOR Flash memory.

The jumper JP13 is dedicated for write protect configuration.

By default, the FMC_NWAIT signal is not routed to RB port of the NOR Flash memory device, and, to know its ready status, its status register is polled by the demo software fitted in STM32L476G-EVAL. This can be modified with configuration elements, as shown in

Table 25 .

DocID027351 Rev 5

43/101

100

Hardware layout and configuration UM1855

Element

Table 25. NOR Flash memory-related configuration elements

Setting Configuration

JP13

Default setting.

NOR Flash memory write is enabled.

JP13

NOR Flash memory write is inhibited. Write protect is activated.

R53

SB10

R53 In

SB10 open

R53 Out

SB10 closed

Default setting.

PD6 port of STM32L476ZGT6 is used for SAI1_SDA signal and routed to audio codec.

NOR Flash memory device’s status register can be accessed.

PD6 port of STM32L476ZGT6 is used for FMC_NWAIT signal and routed to NOR Flash memory device’s RB port.

NOR Flash memory device’s status register cannot be accessed.

2.22.1 Limitations

• FMC_NWAIT and SAI1_SDA signals are mutually exclusive.

• The NOR Flash memory device’s addressable space is limited if some or all of A19,

A20, A21, A22 and A23 FMC address lines are shunted to the CN12 connector for debug trace purposes. In such a case, the disconnected addressing inputs of the NOR

Flash memory device are pulled down by resistors. Section 2.2

provides information on the associated configuration elements.

NOR Flash memory operating voltage must be in the range from 1.65 V to 3.6 V.

2.23 EEPROM

M24128-DFDW6TP, a 128-Kbit I

C-bus EEPROM device , is fitted on the main board of

STM32L476G-EVAL, in U6 position. It is accessed with I

C-bus lines I2C2_SCL and

I2C2_SDA of STM32L476ZGT6. It supports all I

C-bus modes with speeds up to 1 MHz.

The base I

C-bus address is 0xA0. Write-protecting the EEPROM is possible through opening the SB7 solder bridge. By default, SB7 is closed and writing into the EEPROM enabled.

The M24128-DFDW6TP EEPROM device’s operating voltage must be in the range from

1.7 V to 3.6 V

2.24 RF-EEPROM

RF-EEPROM daughterboard, ANT7-M24LR-A, can be connected to CN3 connector of the

STM32L476G-EVAL board. STM32L476ZGT6 can access the RF-EEPROM in two ways,

44/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration wired through I ² C bus or wireless using 13.56 MHz RF band reserved for RFID and NFC equipment. For wireless access, CR95HF reader daughterboard plugged in the CN13 connector can be used, for example.

I ² C address of RF-EEPROM device is 0xA6.

N25Q256A13EF840E, a 256-Mbit Quad-SPI Flash memory device , is fitted on the

STM32L476G-EVAL main board, in U9 position. It allows evaluating STM32L476ZGT6

Quad-SPI Flash memory device interface.

N25Q256A13EF840E can operate in single transfer rate (STR) and double transfer rate

(DTR) modes.

By default, the Quad-SPI Flash memory device is not accessible.

Table 26 shows the

configuration elements and their settings allowing to access the Quad-SPI Flash memory device. The LCD glass module daughterboard MB979 takes active part in the configuration.

It must be removed from the main board (denoted as “MB979 out”), to operate the Quad-

SPI Flash memory device. Section 2.12: Motor control

provides additional information.

Element

SB12

SB13

MB979

SB14

SB15

MB979

SB18

SB19

MB979

Table 26. Configuration elements related with Quad-SPI device

Setting Configuration

SB12 open

SB13 open

SB12 closed

SB13 open

MB979 out

SB14 open

SB15 open

SB14 closed

SB15 open

MB979 out

SB18 open

SB19 open

SB18 closed

SB19 open

MB979 out

Default setting.

QSPI_D0 data line is not available at Quad-SPI Flash memory device:

PB1 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_D0 data line is available at Quad-SPI Flash memory device:

PB1 port of STM32L476ZGT6 is routed to DQ0 port of Quad-SPI Flash memory device.

Default setting.

QSPI_D1 data line is not available at Quad-SPI Flash memory device:

PB0 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_D1 data line is available at Quad-SPI Flash memory device:

PB0 port of STM32L476ZGT6 is routed to DQ1 port of Quad-SPI Flash memory device.

Default setting.

QSPI_D2 data line is not available at Quad-SPI Flash memory device:

PA7 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_D2 data line is available at Quad-SPI Flash memory device:

PA7 port of STM32L476ZGT6 is routed to DQ2 port of Quad-SPI Flash memory device.

DocID027351 Rev 5

45/101

100

Hardware layout and configuration UM1855

Table 26. Configuration elements related with Quad-SPI device (continued)

Element Setting Configuration

SB21

SB20

MB979

SB9

MB979

SB8

MB979

SB21 open

SB20 open

SB21 closed

SB20 open

MB979 out

SB9 open

SB9 closed

MB979 out

SB8 open

SB8 closed

MB979 out

Default setting.

QSPI_D3 data line is not available at Quad-SPI Flash memory device:

PA6 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_D3 data line is available at Quad-SPI Flash memory device:

PA6 port of STM32L476ZGT6 is routed to DQ3 port of Quad-SPI Flash memory device.

Default setting.

QSPI_CLK clock line is not available at Quad-SPI Flash memory device:

PB10 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_CLK clock line is available at Quad-SPI Flash memory device:

PB10 port of STM32L476ZGT6 is routed to C port of Quad-SPI Flash memory device.

Default setting.

QSPI_CS line is not available at Quad-SPI Flash memory device:

PB11 port of STM32L476ZGT6 is only routed to CN11 connector for the

MB979 daughterboard.

QSPI_CS line is available at Quad-SPI Flash memory device:

PB11 port of STM32L476ZGT6 is routed to S# port of Quad-SPI Flash memory device.

2.25.1 Limitations

Quad-SPI operation is exclusive with LCD glass module and with motor control.

Voltage of Quad-SPI Flash memory device N25Q256A13EF840E is in the range of 2.7 V to

3.6 V.

46/101

The STM32L476G-EVAL evaluation board supports a touch sensing button based on either

RC charging or on charge-transfer technique. The latter is enabled, by default.

The touch sensing button is connected to PB12 port of STM32L476ZGT6 and the related charge capacitor is connected to PB13.

An active shield is designed in the layer two of the main PCB, under the button footprint. It allows reducing disturbances from other circuits to prevent from false touch detections.

The active shield is connected to PC6 port of STM32L476ZGT6 through the resistor

R37.The related charge capacitor is connected to PC7.

Table 27 shows the configuration elements related with the touch sensing function. Some of

them serve to enable or disable its operation. However, most of them serve to optimize the touch sensing performance, by isolating copper tracks to avoid disturbances due to their antenna effect.

DocID027351 Rev 5

UM1855

Element

R39

SB3

R38

SB6

R36

SB2

SB27

R33

SB4

Hardware layout and configuration

Table 27. Touch-sensing-related configuration elements

Setting Configuration

Out

Open

Closed

Out

Open

Closed

Out

Open

Closed

Open

Closed

Out

Open

Closed

Default setting.

PB12 port is routed to CN11 connector for LCD glass module daughterboard.

This setting is not good for robustness of touch sensing.

PB12 port is cut from CN11.

This setting is good for robustness of touch sensing.

Default setting.

PB12 is not routed to motor control.

This setting is good for robustness of touch sensing.

PB12 is routed to motor control.

This setting is not good for robustness of touch sensing.

Default setting. PB13 port is routed to CN11 connector for LCD glass module daughterboard.

This setting is not good for robustness of touch sensing.

PB13 port is cut from CN11.

This setting is good for robustness of touch sensing.

Default setting. PB13 is not routed to sampling capacitor. Touch sensing cannot operate.

PB13 is routed to sampling capacitor. Touch sensing can operate.

Default setting.

PC6 port is routed to CN14 connector for LCD glass module daughterboard.

This setting is not good for robustness of touch sensing.

PC6 port is cut from CN14.

This setting is good for robustness of touch sensing.

Default setting. PC6 is not routed to active shield under the touchsensing button.

This setting is not good for robustness of touch sensing.

PC6 is routed to active shield under the touch-sensing button.

This setting is good for robustness of touch sensing.

Default setting.

PC6 port of STM32L476ZGT6 is not routed to motor control. This setting is good for robustness of touch sensing.

PC6 is routed to motor control.

This setting is not good for robustness of touch sensing.

Default setting.

PC7 port is routed to CN14 connector for LCD glass module daughterboard.

This setting is not good for robustness of touch sensing.

PC7 port is cut from CN14.

This setting is good for robustness of touch sensing.

Default setting. PC7 port of STM32L476ZGT6 is not routed to sampling capacitor of the active shield under the touch-sensing button.

This setting is not good for robustness of touch sensing.

PC7 is routed to sampling capacitor of the active shield under the touch-sensing button.

This setting is good for robustness of touch sensing.

DocID027351 Rev 5

47/101

100

Hardware layout and configuration UM1855

Element

Table 27. Touch-sensing-related configuration elements (continued)

Setting Configuration

SB30

Open

Closed

Default setting.

PC7 port of STM32L476ZGT6 is not routed to motor control.

This setting is good for robustness of touch sensing.

PC7 is routed to motor control. This setting is not good for robustness of touch sensing.

2.26.1 Limitations

Touch sensing button is exclusive with LCD glass module, thermal sensor PT100 via sigmadelta conversion, USB OTG FS port operating as USB host, SWP and NFC.

ST8024CDR, an interface device for 3 V and 5 V asynchronous smartcards, is fitted on the

STM32L476G-EVAL main board, in U30 position. ST8024CDR performs all supply protection and control functions of the smartcard.

ST8024CDR is controlled, on its turn, by STM32L476ZGT6, directly through its ports or indirectly through ports of the U33 I/O expander device (IOExpander2), as shown in

Table 28 .

The SWIO port of the smartcard for single-wire protocol (SWP) communication is managed directly by PB12 port of STM32L476ZGT6.

Table 28. Assignment of ports for ST8024CDR control

Function Control port

ST8024CDR port

5V/3V

I/OUC

XTAL1

OFF

RSTIN

CMDVCC

Smartcard power supply selection pin.

Data I/O line

Quartz crystal or external clock input

Card presence detect

Card reset command input

Activation sequence start command input (active low)

IOexpander2 GPIO7

STM32L476ZGT6 PC4

STM32L476ZGT6 PB0

IOexpander2 GPIO8

IOexpander2 GPIO5

IOexpander2 GPIO6

Table 29 provides information on configuration elements related with smartcard operation.

Refer to Table 8

, Table 12

Table 26 and

Table 27 for complementary information. Bridging

of CN11 and CN14 rows of I/Os can be done by means of the MB979 daughterboard plugged into CN11 and CN14 in I/O-bridge position, as explained in

Section 2.15

48/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Element

Table 29. Configuration elements related with smartcard and SWP

Setting Configuration

R39

SB3

R109

CN11

R62

SB14

SB15

R65

SB17

CN14

R109 in

R39 in

SB3 open

CN11 I/O-bridged

R109 out

R39 in

SB3 open

CN11 I/O-bridged

R39 out

SB3 closed

R39 out

SB3 open

R62 in

SB14 open

SB15 open

CN11 I/O-bridged

R62 out

SB14 closed

SB15 open

R62 out

SB14 open

SB15 closed

R65 in

SB17 open

CN14 I/O-bridged

R65 out

SB17 closed

Default setting.

Smartcard SWP cannot be handled:

PB12 is routed to USB OTG FS port as USBOTG_OVRCR line, on top of being routed to SWIO port of smartcard

Configuration dedicated for USB OTG FS operation.

Smartcard SWP can be handled:

PB12 is routed to SWIO port of smartcard. It is disconnected from any other resource that could affect the SWP operation

Configuration dedicated for smartcard SWP operation

Smartcard SWP cannot be handled:

PB12 is routed to motor control as MC_PFC_Shutdown

Configuration dedicated for motor control operation

Smartcard SWP cannot be handled:

PB12 is only routed to touch-sensing button and it is disconnected from any other resource.

Configuration dedicated for touch-sensing button operation.

Default setting.

Smartcard controller U30 is supplied with clock:

PB0 port is routed to XTAL1 of U30, as SmartCard_CLK line and it is not routed to other resources.

Configuration dedicated for smartcard operation.

Smartcard controller U30 is not supplied with clock:

PB0 is routed to Quad-SPI Flash memory device as QSPI_D1 and it is not routed to other resources.

Configuration dedicated for Quad-SPI Flash memory device operation.

Smartcard controller U30 is not supplied with clock:

PB0 is routed to motor control as MC_PWM_2L line and it is not routed to other resources.

Configuration dedicated for motor control operation.

Default setting.

Smartcard controller gets SmartCard_IO line:

PC4 port of MCU is routed to IOUC port of U30, as SmartCard_IO line and it is not routed to other resources.

Configuration dedicated for smartcard operation.

Smartcard controller does not get SmartCard_IO line:

PC4 port of MCU is routed to motor control as MC0PFC0IndCur line and it is not routed to other resources.

Configuration dedicated for motor control operation.

DocID027351 Rev 5

49/101

100

Hardware layout and configuration UM1855

2.27.1 Limitations

The following limitations apply for the smartcard operation:

• Smartcard operation is mutually exclusive with LCD glass module, Quad-SPI Flash memory device and motor control operation.

• SWP operation is mutually exclusive with LCD glass module, touch-sensing button, motor control and USB OTG FS port operation, if the last operates as USB host. SWP can operate concurrently with USB OTG FS port acting as USB device.

Smartcard operating ranging from V

= 2.7 V to V

= 3.6 V. However, the SWP only operates with the supply voltage of 3.3 V.

2.28 Near-field communication (NFC)

The STM32L476G-EVAL board can host an NFC transceiver board plugged in CN13 extension connector.

Figure 12

illustrates the way of attaching an NFC board.

Figure 12. NFC board plugged into STM32L476G-EVAL board

50/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Table 30 shows the assignment of signals to CN13 connector.

The serial communication with the module plugged in CN13 can either use SPI communication protocol (default) or UART communication protocol.

CN13 terminal

Table 30. CN13 NFC connector terminal assignment

NFC line name MCU port Function

NFC_IRQOUTN or

UART_TX

NFC_IRQINN or

UART_RX

NFC_NSS

NFC_MISO

NFC_MOSI

NFC_SCK

+3V3

GND

PB7

PB6

PF11

PB14

PB15

PB13

Interrupt output for NFC device

Connected to STM32L476ZGT6 UART RX

Interrupt input for NFC device

Connected to STM32L476ZGT6 UART TX

SPI slave select

SPI data, slave output

SPI data, slave input

SPI serial clock

Main power supply/power supply for RF drivers

Ground

2.29 Dual-channel sigma-delta modulators STPMS2L

With its DFSDM interface, the STM32L476ZGT6 microcontroller can directly interact with sigma-delta modulator devices, such as STPMS2L.

STPMS2L comprises two analog measuring channels based on second-order sigma-delta modulators. Typically, it can be used in power metering where both voltage and current need to be known. One channel measures the voltage, the other channel measures the current.

DAT port outputs converted measurement data on the DFSDM_DATIN1 line, received by the STM32L476ZGT6 DFSDM controller. The data from STPMS2L are synchronized with

DFSDM_CKOUT clock generated by the STM32L476ZGT6 DFSDM controller and received on CLK terminal of STPMS2L.

There are two STPMS2L devices on STM32L476G-EVAL, sharing the DFSDM clock. One is wired such as to support a power-metering demonstrator. The other allows measuring temperature using the PT100 sensor.

DocID027351 Rev 5

51/101

100

Hardware layout and configuration

Figure 13. Routing of STPMS2L dual-channel sigma-delta modulators

UM1855

67306/

3RZHUPHWHULQJ

'$7

&/.

')6'0B'$7,1

670/=*7

67306/

7HPSHUDWXUHPHWHULQJ

'$7

&/.

&/.287

WR0(06PLFURSKRQHV

37B'$7,1

')6'0B&.287

06Y9

STPMS2L operating parameters are set through its configuration terminals MS0, MS1, MS2 and MS3. On STM32L476G-EVAL, both devices are configured as follows:

• Voltage channel range: differential voltage +/- 300mV

• Current channel range: differential voltage +/- 300mV

• Internal voltage reference is used

• Input bandwidth: 0 to 1 kHz

• Temperature compensation: flattest +30ppm/°C

• DAT output: voltage and current samples multiplexed

• DATn output: not used

• HW mode selected for settings

STPMS2L in U3 position simulates low-voltage AC power metering, with capacitive load impedance, to give different phase to voltage and current.

52/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Figure 14. Power measurement principle schematic diagram

$&VRXUFH a

6KXQWUHVLVWRU

IRUFXUUHQW

PHDVXUHPHQW

&RPSOH[

LPSHGDQFH

FXUUHQW

WR67306/

GLIIHUHQWLDOLQSXW

YROWDJH

WR67306/

GLIIHUHQWLDOLQSXW

06Y9

A low-voltage AC generator is to be applied by the user as shown in

Figure 14

. The shunt resistor is connected in series with the load to provide current measurement points to one of

STPMS2L input channels. The voltage measurement points for the other input channel are taken across the load.

Figure 15 shows an extract of the corresponding schematic diagram.

Warning: do not connect AC mains!

Test example:

The output of a low-voltage AC generator is connected to CN4, terminals 1 and 3. The amplitude is set between 200 mV and 300 mV and the frequency adjustable between 10 Hz and 100 Hz.

With 34 Hz frequency and the load formed of R27 of 1 k Ω in parallel with C29 of 4.7 µF, the voltage and current phases are theoretically 45 degrees apart.

Figure 15. STPMS2L power metering schematic diagram

STPMS2 power metering

CN4

GND external generator input: pins 1 and 3 voltage of complex load: pins 2 and 3

shunt voltage : pins 1 and 2 current shunt

R26

R27

GND

R+jX Load

C26

100nF

GND

STPMS2L-PUR

CIP

CIN

VIP

VIN

Exposed pad GND

C27

1uF

GND

VDD

DATn

GND

DAT

CLK

MS3

GND

C24

1uF

GND

DocID027351 Rev 5

53/101

100

Hardware layout and configuration UM1855

2.29.4 STPMS2L for PT100 measurement

PT100 is a resistor with temperature-dependent resistance.

Usually, one of two methods is used for measuring temperature with a temperaturedependent resistor. In the first method, a known current is driven through the measuring resistor. The temperature is represented by the voltage measured across the resistor. In the second method, a known voltage is applied on the resistor and the current flowing through is measured, representing the temperature. In these methods, either an accurate current source or an accurate voltage source is required.

With the dual-input measurement with STPMS2L in U4 position, no such accurate current or voltage sources are required. Instead, a precision shunt resistor is required. One channel of the STPMS2L measures the voltage across the precise shunt resistor, representing the current flowing through PT100. The other channel measures the voltage across PT100.

Figure 16. Temperature measurement principle schematic diagram

9''

%LDVLQJUHVLVWRU

6KXQWUHVLVWRUIRUFXUUHQW

PHDVXUHPHQW

FXUUHQW

WR67306/

GLIIHUHQWLDOLQSXW

7HPSHUDWXUHGHSHQGHQW

UHVLVWRU

YROWDJH

WR67306/

GLIIHUHQWLDOLQSXW

With voltage across and current through the PT100 resistor, the STM32L476ZGT6 microcontroller computes resistance PT100.

06Y9

For temperatures lower than +100°C, the temperature is given by the following equation, where PT100 is resistance of the PT100 resistor and T is temperature in degrees centigrade:

( ) ⁄ ( 0.385

)

2.29.5 Limitations

Operating voltage must be in the range from 3.2 V to 3.6 V.

2.30 STM32L476ZGT6 current consumption measurement

STM32L476ZGT6 has a built-in circuit allowing to measure its own current consumption

(IDD) in Run and Low-power modes, except for Shutdown mode.

54/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

It is strongly recommended that, the MCU supply voltage (VDD_MCU line) does not exceed

3.3 V. This is because there are components on STM32L476G-EVAL supplied from 3.3 V that communicate with the MCU through I/O ports. Voltage exceeding 3.3 V on the MCU output port may inject current into 3.3 V-supplied peripheral I/Os and false the MCU current consumption measurement.

2.30.1 IDD measurement principle - analog part

The analog part is based on measuring voltage drop across a shunt resistor, amplified with a differential amplifier. The STM32L476ZGT6 microcontroller supply current is shunted, by jumper settings, to flow through the measurement 1 Ω resistor R135: JP11 terminals 1 and 2 are to be open, terminals 3 and 4 closed. When the transistor T2 is in conductive state, the

MCU supply current is proportional to the voltage across R135. When T2 is in highimpedance state, the MCU supply current is proportional to the voltage across the series of

R135 and R123. The former state is used for measuring the current consumption in dynamic run mode, the latter in low-power mode.

The differential amplifier uses three stages U15B, U15C, U15D of quadruple operational amplifier device U15, TSZ124. The gain is set to 50, so every 1 mA of supply current is represented by additional 50 mV at the U15C output, terminal 8 of U15.

The resistance formed with the series of R135 and R123, when T2 is in high-impedance state, is of 1001 Ω . It makes the voltage on terminal 8 of U15 increase by approximately

50 mV for every µA of MCU power consumption. The full-scale range, with VDD at 1.8 V is about 30 µA.

Even with precision resistors R136, R125, R129, R132 to set the gain of the differential amplifier, the output voltage may theoretically become negative. To avoid the need of negative power supply, a positive offset of about 220 mV is created at the output, at zero current consumption of the MCU. This offset does not need to be precise. Any dispersion is

compensated through a calibration procedure detailed in Section 2.30.4

For allowing the IDD measurement, the jumper in the JP11 header must be placed such as to short its terminals 3 and 4.

DocID027351 Rev 5

55/101

100

Hardware layout and configuration

Figure 17. Schematic diagram of the analog part of IDD measurement

+5V

UM1855

Current direction

VDD from power supply

VDD

Shunt_x1000 3

FDC606P

R135

1[1%] shunts

R123

1K[1%]

GND

R128

22K

C144

100nF

R124

GND

C75

100nF decoupling capacitor close from TSZ124 part

V+

V-

U15A

TSZ124IPT

GND

U15B

TSZ124IPT

R136

3K6 0.1% differential amplifier

U15D

TSZ124IPT

R125

3K6 0.1%

R129

180K 0.1%

U15C

TSZ124IPT

R132

180K 0.1% bypass path current measurement

path

JP11

Current direction

VDD_MCU to MCU

The target microcontroller can only carry out actions for measuring a voltage when in dynamic run mode. This is the reason why, voltage representing the current consumed by the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit, for being exploited by the microcontroller at a later time, when back in dynamic run mode.

The sample-and-hold (S&H) circuit is built with U13 switch, R122 resistor and C73 sampling capacitor.

The measurement of low-power-mode current consumption is started and end by the microcontroller in its dynamic run mode. As, between the start and end event, the microcontroller must transit through one of its low-power modes, an extra logic is required to time and control events during this state. It consists of U14 counter, U16 inverter and the transistor T3.

Figure 18 shows the corresponding schematic diagram.

56/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Figure 18. Schematic diagram of logic part of low-power-mode IDD measurement

U15C

TSZ124IPT

Shunt_x1000

VDD

C76

100nF

U13

I/O

GND

O/I

VCC

VDD

SN74LVC1G66DCKT

C74

100nF

R122

10K

T3 4

VDD

U16

SN74LVC1G04DCKT VDD

U14

Q11

Q12

Q13

GND

74LV4060PW

VCC

Rtc

Ctc

C77

1nF

FDC606P

C72

100nF

VDD

R127

220K

R134

15K

R130

30K

PA5

IDD_Measurement

PC5

IDD_WAKEUP

R137

220K

PF10

IDD_CNT_EN

Oscillator frequency 30KHz

The measurement process consists of 3 phases:

Phase 1 - start and transiting to low-power mode

While in dynamic run mode, the MCU sets IDD_CNT_EN signal on its PF10 port low, starting the measurement process. This makes the counters in U14 start counting the clock pulses generated with an own RC oscillator. At about 150 ms from the start, the Q12 output of U14 goes high, terminating the phase 1. After starting the measurement process, the

MCU transits to low-power mode. The duration of the phase 1 of about 150ms allows the

MCU enough time for transiting into low-power mode.

Phase 2 - sampling

The MCU is now in low-power mode. The phase 2 starts with the Q12 port of U14 going high, 150 ms after the MCU, at that time in dynamic run mode, started the low-power-mode consumption current measurement process. The transistor T2 goes in high-impedance mode, which results in setting the analog part in high sensitivity state, needed for measuring very low currents. The Q13 port of U14 keeps the path between ports I/O and O/I of U13 conductive. The sampling capacitor C73 is charged through the resistor R122 to the voltage at the output of the differential analog amplifier, representing the current consumed by the

MCU in low-power mode. The duration of the phase 2 is about 150 ms. This time is needed to allow the voltage on the sampling capacitor C73 to stabilize.

Phase 3 - exiting low-power mode, measurement and end

The MCU is in low-power mode. The voltage across C73 capacitor is now stabilized so it represents the current consumed by the MCU in low-power mode. The phase 3 starts with setting the U13 path between ports O/I and I/O to non-conductive state, for the voltage across C73 to hold. The same event causes the IDD_WAKEUP signal for the MCU to change state, to signal to the MCU that the voltage on C73 is now ready for being measured. The MCU transits from low-power mode to dynamic run mode. The voltage on

C73 representing the current the MCU consumed when it was in low-power mode, is now measured by the MCU, using the ADC port PA5, and stored. The Q12 port transits to low state at the same time as the Q13 goes high. As a consequence, the analog part of the IDD measurement circuit is back to low-sensitivity mode adapted for measuring the microcontroller supply current in its dynamic run mode. The phase 3 and the whole measurement process ends with the microcontroller setting the IDD_CNT_EN signal back high.

Figure 19 illustrates the timing of the low-power-mode current consumption

measurement process.

DocID027351 Rev 5

57/101

100

Hardware layout and configuration UM1855

Figure 19. Low-power-mode IDD measurement timing

$FWLRQE\ORJLF

$FWLRQE\0&8

0&8RSHUDWLQJPRGH ZƵŶ

6WDUW

SURFHVV

6WDUWORZSRZHU,''

VDPSOLQJ

>ŽǁͲƉŽǁĞƌ

+ROGORZSRZHU,''VDPSOH

:DNH0&8XS ŵĞĂƐƵƌĞŵĞŶƚ

(QG

SURFHVV

ZƵŶ

,''B&17B(1

80&8SRUW3%

/2:B32:(5B(1

8FRXQWHUSRUW4

,''B:$.(83

8FRXQWHUSRUW4

,''B:$.(83

8LQYHUWHUWHUPLQDO

,''PHDVXUHPHQWSURFHVVLQSURJUHVV

KLJK,''UDQJH ORZ,''UDQJH

6 +VZLWFK8FORVHG

KLJK,''UDQJH

8RSHQ

WŚĂƐĞϭ aPV

WŚĂƐĞϮ aPV

WŚĂƐĞϯ

06Y9

2.30.3 IDD measurement in dynamic run mode

In dynamic run mode, the IDD_CNT_EN remains high. The T2 is in conductive state, setting the shunt resistor to 1 Ω . The U13 path from port 1 to 2 is permanently conductive and the voltage on the capacitor C73 follows the MCU current consumption. R122 allows filtering fast changes.

For the measurement to be precise, it is mandatory to perform a calibration before the measurement. The calibration allows subtracting, from the voltage measured across C73,

the offset at the differential amplifier output, described in Section 2.30.1

The calibration procedure consists in measuring the offset voltage when the current through the shunt resistor is zero. The current consumption values measured by the microcontroller are then compensated for offset, by subtracting the now-known offset number from the measured number. Setting the current through the shunt resistor to zero is reached through appropriate setting jumpers in the JP11 jumper header.

58/101

DocID027351 Rev 5

UM1855 Hardware layout and configuration

Calibration procedure and current measurement compensation steps:

• On JP11, short terminals 1 and 2 and open terminals 3 and 4. The current through the shunt resistor is now zero.

•

Run low-power-mode IDD measurement as described in Section 2.30.2

. The value

V offset

measured corresponds to offset of the differential amplifier.

• On JP11, add a second jumper, to short terminals 3 and 4, then remove the jumper from terminals 1 and 2 of JP11. The MCU supply has not been interrupted and the supply current now passes through the shunt resistor.

•

Run low-power-mode IDD measurement as described in Section 2.30.2

. The value

V measured

obtained corresponds to the sum of MCU supply current and the differential amplifier’s offset V offset

• The software computes a V out

number representing the MCU supply current as

V out

= V measured

- V offset

Table 31. JP11 jumper settings during IDD measurement with calibration

Jumper Setting Description

JP11

1 2 3 4

Configuration used to measure V offset

JP11 in VDD position

STM32L476ZGT6 supply current does not flow through shunt resistor.

JP11

1 2 3 4

Configuration to transit from direct to shunted supply to

STM32L476ZGT6, without ever interrupting the MCU supply.

JP11

1 2 3 4

Default setting.

Configuration used to measure the MCU supply current.

JP11 in IDD position

STM32L476ZGT6 supply current flows through shunt resistor.

DocID027351 Rev 5

59/101

100

Connectors

3 Connectors

3.1 RS-232 D-sub male connector CN9

Figure 20. RS-232 D-sub (DE-9M) 9-pole connector (front view)

UM1855

60/101

-36

Table 32. RS-232 D-sub (DE-9M) connector CN9 with HW flow control and ISP support

Terminal Terminal name Terminal Description

RS232_RX (PB7)

RS232_TX (PG12)

GND

Bootloader_BOOT0

Bootloader_RESET

The STM32L476G-EVAL board can be powered from a DC-5V external power supply via

the CN22 jack illustrated in Figure 21 . The central pin of CN22 must be positive.

Figure 21. Power supply connector CN22 (front view)

'&9

*1'

-36

DocID027351 Rev 5

UM1855

3.3

Connectors

LCD daughterboard connectors CN11 and CN14

Two 48-pin male headers CN11 and CN14 are used to connect to LCD glass module daughterboard MB979. The type of connectors, their mutual orientation, distance and terminal assignment are kept for a number of ST MCU evaluation boards. This standardization allows developing daughterboards that can be used in multiple evaluation kits. The width between CN11 pin1 and CN14 pin1 is 700 mils (17.78 mm).

STM32L476ZGT6 ports routed to these two connectors can be accessed on odd CN11 and

CN14 pins (the row of pin 1), when no daughterboard is plugged in.

Daughterboards plugging into CN11 and CN14 must keep the even terminals of CN11 and

CN14 open.

Table 33 shows the signal assignment to terminals.

Odd pin

Table 33. CN11 and CN14 daughterboard connectors

CN11 CN14

MCU port

PB13

PB12

PA15

PB8

PB15

PC2

PA9

PA8

PA10

PB9

PB11

PB10

PB5

PB14

PC1

PC0

PA3

PA2

PB0

PA7

PA6

PB4

Odd pin

MCU port

PC7

PC8

PC9

PD8

PD9

PD10

PD2

PC12

PC11

PC10

PB7

PC4

PC5

PC6

PD11

PD12

PD13

PD14

PD15

PE0

PE1

PE2

DocID027351 Rev 5

61/101

100

Connectors UM1855

Table 33. CN11 and CN14 daughterboard connectors (continued)

CN11 CN14

Odd pin

MCU port

PB3

PB1

Odd pin

MCU port

PE3

PA1

62/101

Pin

Table 34. Daughterboard extension connector CN6

Description

Alternative

Functions

How to disconnect Alternative functions to use on the extension connector

GND

PG6

PA13

PA12

PG8

GND

PG2

PD3

PD0

PD5

PG10

PD7

PF0

PG11

PG13

PG12

PG14

PG15

PF4

CODEC_INT,

MC_ICL_Shutout

Remove R35, Open SB5

TMS/SWDIO

USBOTG_DP Remove R4

LPUART_RX_3V3 Remove R158, R188

A12

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

DFSDM_DATIN1

Do not use Trace connector CN12 and JTAG connector CN15

FMC_NWE

Remove R23

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Cannot be disconnected from SRAM and Flash memory, but is an input for SRAM and Flash memory

LCD_NE3

FMC_NE1

Cannot be disconnected from TFT LCD level shifters U21 and U22, but is an input for TFT

LCD.

Remove R18

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

USART1_CTS_3V3 Remove R93

I2C_SDA

USART1_RTS

I2C_SCL

IOExpander_INT

Remove R58

Remove R116

Remove R61

Remove R228

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

DocID027351 Rev 5

UM1855 Connectors

Table 34. Daughterboard extension connector CN6 (continued)

Pin Description

Alternative

Functions

How to disconnect Alternative functions to use on the extension connector

GND

+3V3

PG7

PA11

PA14

PG5

PG3

PG4

PD1

PD4

PG9

GND

PD6

LPUART_TX

USBOTG_DM

TCK/SWCLK

A15

A13

A14

FMC_NOE

FMC_NE2

SAI1_SDA,

FMC_NWAIT

Remove R119, R189

Remove R3

Do not use Trace connector CN12 and JTAG connector CN15

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R43

Remove R53, open SB10

PF1

D5V

PC13

PF2

PF3

GND

PF5

PB6

Wake-up

USART1_TX

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R244

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R18 to deselect SRAM U2

Remove R43 to deselect Flash memory U5

Remove R118

Pin

Table 35. Daughterboard extension connector CN7

Description

Alternative

Functions

How to disconnect Alternative functions to use on the extension connector

GND

PE14

D11 -

DocID027351 Rev 5

63/101

100

Connectors UM1855

Table 35. Daughterboard extension connector CN7 (continued)

Pin Description

Alternative

Functions

How to disconnect Alternative functions to use on the extension connector

PE12

PE10

PE8

PG1

PB2

GND

PF12

PF11

PE4

PE5

PC14

PF6

PF9

PF10

PH1

PA5

PA0

GND

PE15

PE13

PE11

PE9

PE7

PG0

PF15

PF14

PF13

BOOT0

PE6

PC15

A11

LED1,

MC_DissipativeBrake

Remove R54, SB11

NFC_NSS

A20, TRACE_D1

A21, TRACE_D2

OSC32_IN

SAI1_SDB

Do not connect the NFC daughterboard to connector CN13

Remove R84, SB40

Remove R85, SB38

Remove R87, Close SB41

Remove R105

SAI1_FSB,

MC_PFC_sync

IDD_CNT_EN,

MC_PFC_PWM

OSC_OUT

Remove R90, SB25

Remove R91, SB37

Remove R95, close SB23

IDD_Measurement Remove R69

OpAmp1_INP,

MC_EncA

Remove R83, SB35

D12

D10

A10

BootLoader from

UART

A21, TRACE_D3

OSC32_OUT

Remove JP8

Remove R86, SB39

Remove R88, close SB33

64/101

DocID027351 Rev 5

UM1855

3.5

3.6

Connectors

Table 35. Daughterboard extension connector CN7 (continued)

Pin Description

Alternative

Functions

How to disconnect Alternative functions to use on the extension connector

GND

PF7

PF8

RESET#

PH0

PC3

PA4

VDD

SAI1_MCKB

SAI1_SCKB

OSCIN

VLCD

ADC_DAC

Remove R106

Remove R89

Remove crystal X2, C54, close SB24

Remove R94

Remove R73

ST-LINK/V2-1 programming connector CN16

The connector CN16 is used only for embedded ST-LINK/V2-1 programming, during board manufacture. It is not populated by default and not for use by the end user.

ST-LINK/V2-1 Standard-B USB connector CN17

The USB connector CN17 is used to connect the on-board ST-LINK/V2-1 facility to PC for flashing and debugging software.

Figure 22. USB type B connector CN17 (front view)

DocID027351 Rev 5

65/101

100

Connectors

Terminal

Table 36. USB Standard-B connector CN17

Description Terminal

VBUS(power)

5,6

GND

Shield

Description

3.7 JTAG connector CN15

Figure 23. JTAG debugging connector CN15 (top view)

UM1855

66/101

Terminal

D^ϯϬϳϮϮsϮ

Table 37. JATG debugging connector CN15

Function / MCU port Terminal Function / MCU port

VDD power

PB4

PA15

PA13

PA14

RTCK

PB3

RESET#

DBGRQ

DBGACK

VDD power

GND

DocID027351 Rev 5

UM1855

3.8 ETM trace debugging connector CN12

Figure 24. Trace debugging connector CN12 (top view)

Connectors

Terminal

D^ϯϬϳϮϮsϮ

Table 38. Trace debugging connector CN12

Function / MCU port Terminal Function / MCU port

VDD power

GND

KEY

GND

TMS/PA13

TCK/PA14

TDO/PB3

TDI/PA15

RESET#

TraceCLK/PE2

TraceD0/PE3 or SWO/PB3

TraceD1/PE4 or nTRST/PB4

TraceD2/PE5

TraceD3/PE6

DocID027351 Rev 5

67/101

100

Connectors

3.9 microSD card connector CN18

Figure 25. microSD card connector CN18

(YDOXDWLRQERDUG

UM1855

PLFUR6'

FDUG

&1

Terminal

06Y9

Table 39. microSD card connector CN18

Terminal name (MCU port) Terminal Terminal name (MCU port)

SDIO_D2 (PC10)

SDIO_D3 (PC11)

SDIO_CMD (PD2)

VDD

SDIO_CLK (PC12)

Vss/GND

SDIO_D0 (PC8)

SDIO_D1 (PC9)

GND

MicroSDcard_detect (PA8)

3.10 ADC/DAC connector CN8

Figure 26. Analog input-output connector CN8 (top view) ϭ Ϯ

06Y9

68/101

DocID027351 Rev 5

UM1855

Terminal

Connectors

Table 40. Analog input-output connector CN8

Function / MCU port Terminal Function / MCU port

GND 2 analog input-output PA4

Figure 27. RF-EEPROM daughterboard connector CN3 (front view)

Terminal

069

Table 41. RF-EEPROM daughterboard connector CN3

Terminal name (MCU port) Terminal Terminal name (MCU port)

I2C_SDA (PG13)

I2C_SCL (PG14)

EXT_RESET(PC6)

+3V3

GND

+5 V

3.12 Motor control connector CN2

Figure 28. Motor control connector CN2 (top view)

DocID027351 Rev 5

-36

69/101

100

Connectors

CN2 terminal

Emergency STOP

PWM_1H

PWM_1L

PWM_2H

PWM_2L

PWM_3H

PWM_3L

CURRENT A

CURRENT B

CURRENT C

ICL Shutout

DISSIPATIVE

BRAKE

Description

Table 42. Motor control connector CN2

MCU port

CN2 terminal

MCU port

PC9

PC6

PA7

PC7

PB0

PC8

PB1

PC0

PC1

PC2

PG6

PB2 24

PC5

PC4

+5V power

PFC SYNC

PFC PWM

Encoder A

Encoder B

PF9

PF10

PA0

PA1

PA3

PB12

PA6

PA2

UM1855

Description

GND

BUS VOLTAGE

GND

PCD Ind Current

Heat sink temperature

3.3 V power

PFC Shut Down

PFC Vac

Encoder Index

3.13 USB OTG FS Micro-AB connector CN1

Figure 29. USB OTG FS Micro-AB connector CN1 (front view)

70/101

Terminal

069

Table 43. USB OTG FS Micro-AB connector CN1

Terminal name (MCU port) Terminal Terminal name (MCU port)

VBUS (PA9 & PB13)

D- (PA11)

D+ (PA12)

ID (PA10)

GND

DocID027351 Rev 5

UM1855 Connectors

3.14 CAN D-sub male connector CN5

Figure 30. CAN D-sub (DE-9M) 9-pole male connector CN5 (front view)

-36

Terminal

1,4,8,9

Table 44. CAN D-sub (DE-9M) 9-pins male connector CN5

Terminal name Terminal Terminal name

CANL

3,5,6

CANH

GND

3.15 NFC connector CN13

Figure 31. NFC female connector CN13 (top view)

06Y9

CN13 terminal

Table 45. NFC CN13 terminal assignment

NFC signal

NFC_IRQOUTN or

UART_TX

NFC_IRQINN or

UART_RX

MCU port

PB7

PB6

Description

Interrupt output for NFC

Connected to STM32L476ZGT6 UART RX

Interrupt input for CR95HF

Connected to STM32L476ZGT6 UART TX

DocID027351 Rev 5

71/101

100

Connectors

CN13 terminal

UM1855

Table 45. NFC CN13 terminal assignment (continued)

NFC signal MCU port Description

NFC_NSS

NFC_MISO

NFC_MOSI

NFC_SCK

+3V3

GND

PF11

PB14

PB15

PB13

PB6

PB7

SPI slave select

SPI data, slave output

SPI data, slave input

SPI serial clock

Main power supply/power supply for RF drivers

Ground

72/101

DocID027351 Rev 5

UM1855

Appendix A Schematic diagrams

Schematic diagrams

This section provides design schematics for the STM32L476G-EVAL key features to help users to implement these features in application designs.

This section includes:

•

Overall schematics for the board, see Figure 32

• MCU, LCD daughterboard and I/O expander interfaces, see

Figure 33

•

STM32L476G-EVALMCU part 1, see Figure 34

• STM32L476G-EVAL MCU part 2, see

Figure 35

•

LCD glass module daughterboard connectors, see Figure 36

•

I/O expander, see Figure 37

•

Power supply, see Figure 38

•

Smartcard, SWP and NFC, see Figure 39

•

USART and IrDA, see Figure 40

• SRAM and NOR Flash memory devices, see

Figure 41

•

TFT LCD, see Figure 42

• Extension connector, see

Figure 43

• Quad-SPI Flash memory device,

Figure 44

•

microSD card, see Figure 45

• Physical control peripherals, see

Figure 46

• CAN transceiver, see

Figure 47

• Touch-sensing device, see

Figure 48

• USB_OTG_FS port, see

Figure 49

•

IDD measurement, see Figure 50

•

Audio codec device, see Figure 51

•

STPMS2L and PT100, see Figure 52

• RF-EEPROM and EEPROM, see

Figure 53

•

Motor control connector, see Figure 54

•

JTAG and trace debug connectors, Figure 55

•

ST-LINK/V2-1, see Figure 56

DocID027351 Rev 5

73/101

100

Figure 32. STM32L476G-EVAL top

U_SWP_SmartCard_NFC

SWP_SmartCard_NFC.SchDoc

NFC_IRQOUTN

NFC_IRQINN

USART_IrDA.SchDoc

NFC_IRQINN

NFC_IRQOUTN

LCD_TFT.SchDoc

U_USART_IrDA

U_LCD_TFT

NFC_MOSI

NFC_MISO

NFC_SCK

NFC_NSS

SWP_IO

SmartCard_OFF

SmartCard_IO

SmartCard_CLK

SmartCard_CMDVCC

SmartCard_3/5V

SmartCard_RST

USART1_TX

USART1/IrDA_RX_3V3

USART1_RTS

USART1_CTS_3V3

LPUART_TX

LPUART_RX_3V3

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

U_ST_LINK

ST_LINK.SCHDOC

RESET#

JTAG&Trace.SchDoc

U_JTAG&Trace

RESET#

LPUART_TX

LPUART_RX_3V3

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

Clearance Constraint [Clearance = 10mil] i PCB Rule i PCB Rule

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

TRACE_D0

TRACE_D1

TRACE_D2

TRACE_D3

TRACE_CK

Matched Net Lengths [Tolerance = 100mil] i i

LPUART_TX

LPUART_RX_3V3

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

TRACE_D0

TRACE_D1

TRACE_D2

TRACE_D3

TRACE_CK

RESET#

SRAM&Flash.SchDoc

U_SRAM&Flash

D[0..15]

A[0..23]

FMC_NE1

FMC_NE2

FMC_NWE

FMC_NOE

FMC_NBL0

FMC_NBL1

FMC_NWAIT

FMC_NE1

FMC_NE2

FMC_NBL0

FMC_NBL1

FMC_NWAIT

U_MCU_LCDGlass_Symbol

NFC_MOSI

MCU_LCDGlass_Symbol.SchDoc

NFC_MISO

NFC_SCK

NFC_NSS

SWP_IO

SmartCard_OFF

SmartCard_IO

SmartCard_CLK

SmartCard_CMDVCC

SmartCard_3/5V

SmartCard_RST

LED1

LED2

LED3

LED4

JOY_SEL

JOY_DOWN

USART1_TX

USART1/IrDA_RX_3V3

USART1_RTS

USART1_CTS_3V3

JOY_LEFT

JOY_RIGHT

JOY_UP

Key

Comp2_INP

Comp2_OUT

OpAmp1_INP

OpAmp1_INM

OpAmp1_OUT

ADC_DAC

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

CAN_RX

CAN_TX

TKEY

TKEY_CS

SHIELD

SHIELD_CS

USBOTG_DM

USBOTG_DP

USBOTG_ID

USBOTG_VBUS

USBOTG_OVRCR

USBOTG_PRDY

USBOTG_PPWR

IDD_Measurement

IDD_CNT_EN

IDD_WAKEUP

SAI1_SDA

SAI1_SDB

SAI1_SCKB

SAI1_MCKB

SAI1_FSB

DMIC_DATIN

CODEC_INT

RESET#

U_Extension connector

Extension connector.SCHDOC

RESET#

D[0..15]

A[0..23]

LCD_NE3

FMC_NWE

FMC_NOE

BL_Control

IOExpander_X+

IOExpander_X-

IOExpander_Y+

IOExpander_Y-

PA[0..15]

PB[0..15]

PC[0..15]

PD[0..15]

PE[0..15]

PF[0..15]

PG[0..15]

PH0

D[0..15]

A[0..23]

LCD_NE3

FMC_NWE

FMC_NOE

BL_Control

IOExpander_X+

IOExpander_X-

IOExpander_Y+

IOExpander_Y-

BOOT0

PA[0..15]

PB[0..15]

PC[0..15]

PD[0..15]

PE[0..15]

PF[0..15]

PG[0..15]

PH0

DFSDM_CKOUT

DFSDM_DATIN1

PT100_DATIN

I2C_SDA

I2C_SCL

EXT_RESET

I2C2_SDA

I2C2_SCL

QSPI.SchDoc

MicroSD.SchDoc

U_QSPI

U_MicroSD

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_CLK

QSPI_CS uSD_D0 uSD_D1 uSD_D2 uSD_D3 uSD_CLK uSD_CMD uSD_DETECT

PH1

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_CLK

QSPI_CS uSD_D0 uSD_D1 uSD_D2 uSD_D3 uSD_CLK uSD_CMD uSD_DETECT

MC_EmergencySTOP

MC_PWM_1H

MC_PWM_1L

MC_PWM_2H

MC_PWM_2L

MC_PWM_3H

MC_PWM_3L

MC_CurrentA

MC_CurrentB

MC_CurrentC

MC_ICL_Shutout

MC_DissipativeBrake

MC_PFC_sync

MC_PFC_PWM

MC_EncA

MC_EncB

MC_BusVoltage

MC_PFC_IndCurr

MC_Temperature

MC_PFC_Shutdown

MC_PFC_Vac

MC_EncIndex

LED1

LED2

LED3

LED4

JOY_SEL

JOY_DOWN

U_peripherals peripherals.SchDoc

JOY_LEFT

JOY_RIGHT

JOY_UP

KEY

Comp2_INP

Comp2_OUT

OpAmp1_INP

OpAmp1_INM

OpAmp1_OUT

ADC_DAC VREF+

U_CAN

CAN.SchDoc

CAN_RX

CAN_TX

TKEY

TKEY_CS

SHIELD

SHIELD_CS

U_Touch Sensing

Touch Sensing.SchDoc

U_USB_OTG_FS

USB_OTG_FS.SchDoc

USBOTG_DM

USBOTG_DP

USBOTG_ID

USBOTG_VBUS

USBOTG_OVRCR

USBOTG_PRDY

USBOTG_PPWR

U_IDD_measurement

IDD_Measurement

IDD_measurement.SchDoc

IDD_CNT_EN

IDD_WAKEUP

SAI1_SDA

SAI1_SDB

SAI1_SCKB

SAI1_MCKB

SAI1_FSB

DMIC_DATIN

DFSDM_CKOUT

CODEC_INT

I2C_SDA

I2C_SCL

U_Audio

Audio.SchDoc

U_STPMS2&PT100

DFSDM_CKOUT

STPMS2&PT100.SchDoc

DFSDM_DATIN1

PT100_DATIN

U_RF_I2C_EEPROM

I2C_SDA

RF_I2C_EEPROM.SchDoc

I2C_SCL

EXT_RESET

I2C2_SDA

I2C2_SCL

U_MotorControl

MotorControl.SchDoc

MC_EmergencySTOP

MC_PWM_1H

MC_PWM_1L

MC_PWM_2H

MC_PWM_2L

MC_PWM_3H

MC_PWM_3L

MC_CurrentA

MC_CurrentB

MC_CurrentC

MC_ICL_Shutout

MC_DissipativeBrake

MC_PFC_sync

MC_PFC_PWM

MC_EncA

MC_EncB

MC_BusVoltage

MC_PFC_IndCurr

MC_Temperature

MC_PFC_Shutdown

MC_PFC_Vac

MC_EncIndex

VREF+

U_Power

Power.SchDoc

Note: In all sheets, Italic format is used to differentiate text from schematic Net labels.

Title: Top schematic

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision:

Sheet: 1

C-02 of 25

Figure 33. MCU, LCD daughterboard and I/O expander interfaces

PC[0..15]

PF[0..15]

PG[0..15]

PA[0..15]

PB[0..15]

PD[0..15]

PE[0..15]

A[0..23]

D[0..15]

A[0..23]

D[0..15]

Key

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

SAI1_SDB

SAI1_MCKB

SAI1_SCKB

SAI1_FSB

PH0

PH1

SHIELD

SHIELD_CS

IDD_CNT_EN

CODEC_INT

BOOT0

RESET#

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

TRACE_D0

TRACE_D1

TRACE_D2

TRACE_D3

TRACE_CK

DFSDM_DATIN1

IDD_Measurement

OpAmp1_INP

ADC_DAC

USBOTG_DP

USBOTG_DM

DFSDM_CKOUT

DMIC_DATIN

PT100_DATIN

SmartCard_CLK

SmartCard_IO

USBOTG_VBUS

USBOTG_ID

USBOTG_PRDY

USBOTG_OVRCR

USBOTG_PPWR

IDD_WAKEUP

OpAmp1_INM

OpAmp1_OUT

Comp2_INP

Comp2_OUT

LCDCOM[0..7]

LCDSEG[0..39]

A23

A[16..19]

D[0..15]

LCDCOM[4..6]

LCDSEG[18..20]

LCDSEG[22..27]

A[0..15]

D[0..15]

LCDCOM7

LCDCOM[0..3]

LCDSEG[28..39]

LCDSEG21

LCDSEG[0..17]

A[20..22]

D[0..15]

U_MCU2

MCU2.SchDoc

Key

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

SAI1_SDB

SAI1_MCKB

SAI1_SCKB

SAI1_FSB

PH0

PH1

SHIELD

SHIELD_CS

LCD_NE3

FMC_NE2

NFC_NSS

USART1_RTS

USART1_CTS_3V3

LPUART_TX

LPUART_RX_3V3

IDD_CNT_EN

CODEC_INT

PC[0..15]

PF[0..15]

PG[0..15]

LCDCOM[4..6]

LCDSEG[18..20]

LCDSEG[22..27]

A[0..15]

D[0..15]

BOOT0

RESET#

IOExpander_INT

I2C_SCL

I2C_SDA

MC_EmergencySTOP

MC_PWM_1H

MC_PWM_2H

MC_PWM_3H

MC_BusVoltage

MC_CurrentA

MC_CurrentB

MC_CurrentC

MC_ICL_Shutout

MC_PFC_IndCurr

MC_PFC_sync

MC_PFC_PWM

RESET#

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

TRACE_D0

TRACE_D1

TRACE_D2

TRACE_D3

TRACE_CK

DFSDM_DATIN1

IDD_Measurement

U_MCU

MCU.SchDoc

OpAmp1_INP

ADC_DAC

USBOTG_DP

USBOTG_DM

PA[0..15]

PB[0..15]

PD[0..15]

PE[0..15]

LCDCOM7

LCDCOM[0..3]

LCDSEG[28..39]

LCDSEG21

LCDSEG[0..17]

A[20..22]

D[0..15]

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_CLK

QSPI_CS

SAI1_SDA

TKEY

TKEY_CS

FMC_NOE

FMC_NWE

FMC_NE1

FMC_NWAIT

LED1

USART1_TX

MC_PWM_1L

MC_PWM_2L

MC_PWM_3L

MC_PFC_Shutdown

MC_DissipativeBrake

MC_Temperature

MC_PFC_Vac

MC_EncA

MC_EncB

MC_EncIndex

LCDCOM[0..7]

LCDSEG[0..39]

A23

A[16..19]

D[0..15]

U_LCD_Glass

LCD_Glass.SchDoc

I2C2_SDA

I2C2_SCL

USART1/IrDA_RX_3V3

DFSDM_CKOUT

DMIC_DATIN

PT100_DATIN

SmartCard_CLK

SmartCard_IO

FMC_NBL0

FMC_NBL1

LED3

USBOTG_VBUS

USBOTG_ID

USBOTG_PRDY

USBOTG_OVRCR

USBOTG_PPWR

IDD_WAKEUP

OpAmp1_INM

OpAmp1_OUT

Comp2_INP

Comp2_OUT

NFC_MOSI

NFC_MISO

NFC_SCK

SWP_IO

CAN_RX

CAN_TX uSD_CMD uSD_CLK uSD_D0 uSD_D1 uSD_D2 uSD_D3 uSD_DETECT

LCD_NE3

FMC_NE2

NFC_NSS

USART1_RTS

USART1_CTS_3V3

LPUART_TX

LPUART_RX_3V3

MC_EmergencySTOP

MC_PWM_1H

MC_PWM_2H

MC_PWM_3H

MC_BusVoltage

MC_CurrentA

MC_CurrentB

MC_CurrentC

MC_ICL_Shutout

MC_PFC_IndCurr

MC_PFC_sync

MC_PFC_PWM

QSPI_D0

QSPI_D1

QSPI_D2

QSPI_D3

QSPI_CLK

QSPI_CS

SAI1_SDA

TKEY

TKEY_CS

FMC_NOE

FMC_NWE

FMC_NE1

FMC_NWAIT

LED1

USART1_TX

MC_PWM_1L

MC_PWM_2L

MC_PWM_3L

MC_PFC_Shutdown

MC_DissipativeBrake

MC_Temperature

MC_PFC_Vac

MC_EncA

MC_EncB

MC_EncIndex

I2C2_SDA

I2C2_SCL

USART1/IrDA_RX_3V3

FMC_NBL0

FMC_NBL1

LED3

NFC_MOSI

NFC_MISO

NFC_SCK

SWP_IO

CAN_RX

CAN_TX uSD_CMD uSD_CLK uSD_D0 uSD_D1 uSD_D2 uSD_D3 uSD_DETECT

IOExpander_X+

IOExpander_X-

IOExpander_Y+

IOExpander_Y-

JOY_SEL

JOY_DOWN

JOY_LEFT

JOY_RIGHT

JOY_UP

U_IO_Expandor

IO_Expandor.SchDoc

IOExpander_X+

IOExpander_X-

IOExpander_Y+

IOExpander_Y-

BL_Control

SmartCard_3/5V

SmartCard_CMDVCC

SmartCard_OFF

SmartCard_RST

JOY_SEL

JOY_DOWN

JOY_LEFT

JOY_RIGHT

JOY_UP

IOExpander_INT

LED2

LED4

EXT_RESET

I2C_SCL

I2C_SDA

BL_Control

SmartCard_3/5V

SmartCard_CMDVCC

SmartCard_OFF

SmartCard_RST

LED2

LED4

EXT_RESET

I2C_SCL

I2C_SDA

Title: MCU_LCDGlassl

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision: C-02

Sheet: 2 of 25

Figure 34. STM32L476G-EVAL MCU part 1

LCDCOM[0..3]

LCDCOM7

OpAmp1_INP

MC_EncA

R83 0

SB35

Open by default

LCDSEG1

MC_EncIndex

LCDSEG3

QSPI_D3

MC_PFC_Vac

RESET#

PA2

PA6

A[20..22]

R81

SB31

R68

Open by default

SB21

Open by default

SB20

Open by default

LCDSEG6 PB1

QSPI_D0

MC_PWM_3L

PA[0..15]

PB[0..15]

PD[0..15]

PE[0..15]

R56

SB12

Open by default

SB13

Open by default

D[0..15]

RESET#

LCDCOM[0..3]

LCDCOM7

LCDSEG[0..17]

LCDSEG[28..39]

LCDSEG21

LCDSEG[0..17]

LCDSEG[28..39]

LCDSEG21

LCDSEG0 PA1

MC_EncB

R82 0

SB32

Open by default

LCDSEG2

MC_Temperature

LCDSEG4

QSPI_D2

PA3

PA7

MC_PWM_1L

R78

SB22

Open by default

R66 0

SB18

Open by default

SB19

Open by default

LCDSEG5

QSPI_D1

PB0

MC_PWM_2L

R62 0

SB14

Open by default

SB15

Open by default

LED1

MC_DissipativeBrake

R54 0

SB11

Open by default

LCDSEG10

QSPI_CLK

LCDSEG11

QSPI_CS

PB10

PB11

R50 0

SB9

Open by default

R48 0

SB8

Open by default

R39 0 LCDSEG12 PB12

TKEY

MC_PFC_Shutdown

LCDSEG13

TKEY_CS

PB13

SB3

Open by default

R38 0

SB6

Open by default

ADC_DAC

IDD_Measurement

R69 0

USBOTG_DM

USBOTG_DP

TMS/SWDIO

LCDCOM0

LCDCOM1

LCDCOM2

TCK/SWCLK

TDI

LCDSEG17

U7A

PA0

PA4

PA5

100 PA8

PA9 101

PA10 102

PA11 103

PA12 104

PA13 105

PA14 109

PA15 110

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PA4

PA5

PA6

PA7

PA8

PA0-WKUP1

PA1

PA2

PA3

TDO/SWO

TRST

USART1_TX

LCDSEG7

LCDSEG8

LCDSEG9

LCDSEG21

LCDSEG16

LCDCOM3

LCDSEG14

LCDSEG15

PB4

PB5

PB6

PB7

PB0

PB1

PB2

PB3

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB14

PB15 76

140

133

134

135

136

137

139

STM32L476ZGT6U

PD8

PD9

PD10

PD11

PD4

PD5

PD6

PD7

PD12

PD13

PD14

PD15

PD0

PD1

PD2

PD3

114 PD0

115 PD1

116 PD2

117 PD3

118 PD4

119 PD5

122 PD6

123 PD7

LCDCOM7

PD8

PD9

LCDSEG28

LCDSEG29

PD10

PD11

LCDSEG30

LCDSEG31

PD12 LCDSEG32

PD13 LCDSEG33

PD14

PD15

LCDSEG34

LCDSEG35

DFSDM_DATIN1

FMC_NOE

FMC_NWE

FMC_NE1

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

141 PE0

142 PE1

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

LCDSEG36

LCDSEG37

PE13

PE14

PE15

D10

D11

D12

R53 0

SB10

Open by default

SAI1_SDA

FMC_NWAIT

R103

PE2

SB26

Open by default

LCDSEG38

TRACE_CK

R104

PE3 LCDSEG39

TRACE_D0

R84 0

SB40

R100

100K

Open by default

GND

A20

TRACE_D1

R85 0

SB38

R101

100K

Open by default

GND

A21

TRACE_D2

R86 0 A22

SB39

Open by default

R102

GND

100K

TRACE_D3

Title: MCU

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 3 of 25

Figure 35. STM32L476G-EVAL MCU part 2

PC[0..15]

PF[0..15]

PG[0..15]

D[0..15]

A[0..15]

RESET#

PH0

PH1

LCDSEG[18..20]

LCDSEG[22..27]

LCDSEG[18..20]

LCDSEG[22..27]

LCDCOM[4..6]

LCDSEG18 PC0

MC_CurrentA

LCDSEG19 PC1

MC_CurrentB

LCDSEG20 PC2

MC_CurrentC

R97 0

SB34

Open by default

R98 0

SB36

Open by default

R99 0

SB42

Open by default

TP7 VLCD

VLCD input

LCDSEG22

MC_PFC_IndCurr

LCDSEG23

MC_BusVoltage

LCDSEG24

SHIELD

PC4

PC6

MC_PWM_1H

LCDSEG25

PC5

PC7

SHIELD_CS

MC_PWM_2H

R65 0

SB17

Open by default

R64 0

SB16

Open by default

R36 0

SB2

Open by default

SB27

Open by default

R33 0

SB4

Open by default

SB30

Open by default

LCDSEG26 PC8

MC_PWM_3H

SB28

Open by default

LCDSEG27 PC9

MC_EmergencySTOP

SB29

Open by default

RESET

VDD

R96

[N/A]

C58

1uF

R94 0

LCDCOM4

LCDCOM5

LCDCOM6

C56

2.7pF

Key

R87

U7C

PC3

PC10 111

PC11 112

PC12 113

PC13 7

PC14

PC15

PC4

PC5

PC6

PC7

PC0

PC1

PC2

PC3

PC8

PC9

PC10

PC11

PC12

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

RESET#

C141

100nF

32.768 kHz crystal

C57

R88

2.7pF

NDK NX3215SA-32.768KHZ-EXS00A-MU00525

C54

20pF

C55

20pF

PH0

8MHz (with socket)

R95

390

PH1

PH0-OSC_IN

PH1-OSC_OUT

BOOT0

SW1

R67

10K

JP8

Header 2X1

138

NRST

BOOT0

STM32L476ZGT6U

BOOT0

VDD

BAT60JFILM

JP9

R59

150

BAT60JFILM

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

Header 2X1

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

93 PG8

124 PG9

125 PG10

126 PG11

127 PG12

128 PG13

129 PG14

132 PG15

PG10

PG11

PG12

PG13

PG6

PG7

PG8

PG9

PG14

PG15

PG0

PG1

PG2

PG3

PG4

PG5

A10

A11

A12

A13

A14

A15

PF9

PF10

PF11

PF12

53 PF13

PF14

PF15

PF4

PF5

PF0

PF1

PF2

PF3

18 PF6

PF7

PF8

NFC_NSS

R105

R106

SAI1_SDB

SAI1_MCKB

R89 0

SAI1_SCKB

R90 0

SB25

Open by default

R91 0

SB37

Open by default

SAI1_FSB

MC_PFC_sync

IDD_CNT_EN

MC_PFC_PWM

R34

R58

R61

R57

1K2

R60

1K2

R35 0

SB5

Open by default

LPUART_TX

LPUART_RX_3V3

FMC_NE2

LCD_NE3

USART1_CTS_3V3

USART1_RTS

I2C_SDA

I2C_SCL

IOExpander_INT

CODEC_INT

MC_ICL_Shutout

VDD

Title: MCU2

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision: C-02

Sheet: 4 of 25

Figure 36. LCD glass module daughterboard connectors

LCD Glass Connector

LCDCOM1 PA9

LCDCOM0 PA8

LCDCOM2

LCDCOM3

PA10

PB9

LCDSEG11

LCDSEG10

LCDSEG9

PB11

PB10

PB5

LCDSEG14

LCDSEG13

LCDSEG12

LCDSEG17

LCDSEG16

LCDSEG15

LCDSEG20

LCDSEG19

PB14

PB13

PB12

PA15

PB8

PB15

PC2

PC1

PC0 LCDSEG18

LCDSEG2

LCDSEG1

LCDSEG5

LCDSEG4

LCDSEG3

LCDSEG8

LCDSEG7

LCDSEG6

PA3

PA2

PB0

PA7

PA6

PB4

PB3

PB1

CN11

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

Header 24X2

USBOTG_VBUS uSD_DETECT

USBOTG_ID

CAN_TX

Comp2_OUT

CAN_RX

DFSDM_CKOUT

LED3

DMIC_DATIN

Comp2_INP

VDD

R265

R266

R263 R264

1K2 1K2

R108

R109

I2C2_SDA

I2C2_SCL

NFC_MISO

USBOTG_PRDY

NFC_SCK

USBOTG_OVRCR

SWP_IO

NFC_MOSI

R111 0

OpAmp1_OUT

R107 0

SmartCard_CLK

LCD Glass Connector

CN14

LCDCOM7 PD2

LCDCOM6

LCDCOM5

PC12

PC11

LCDCOM4

LCDSEG21

PC10

PB7

LCDSEG22

LCDSEG23

LCDSEG24

LCDSEG25

LCDSEG26

LCDSEG27

LCDSEG28

LCDSEG29

LCDSEG30

LCDSEG31

PC4

PC5

PC6

PC7

LCDSEG32

LCDSEG33

LCDSEG34

LCDSEG35

LCDSEG36

LCDSEG37

LCDSEG38

LCDSEG39

LCDSEG0

PC9

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PE0

PE1

PE2

PE3

PA1

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

Header 24X2 uSD_CMD uSD_CLK uSD_D3 uSD_D2

R140

R141

R142

USART1/IrDA_RX_3V3

D13

D14

D15

A16

A18

FMC_NBL0

FMC_NBL1

OpAmp1_INM

R143 0

SmartCard_IO

R144 0

IDD_WAKEUP

R145 0

USBOTG_PPWR

R146 0

R147 0

PT100_DATIN uSD_D0

R148 0 uSD_D1

R151 0

R149 0

R150 0

A17

R138

100K

A23

A19

R139

100K

GND

D[0..15]

A23

D[0..15]

A[16..19]

A23

LCDSEG[0..39]

LCDCOM[0..7]

LCDSEG[0..39]

LCDCOM[0..7]

Title: LCD_Glass

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 5 of 25

Figure 37. I/O expander

I2C_SCL

I2C_SDA

IOExpander_INT

PG14

PG13

PG15 R228 0

R229

100K

IOExpander1

VDD

C134

100nF

U32

VCC

Vio

GND

SCLK

SDAT

INT

Data in

A0/Data Out

Y-

X-

Y+

X+

IN3

IN2

IN1

IN0

STMPE811QTR

I2C device address:0x82

R239

100K

IOExpander_Y-

IOExpander_X-

IOExpander_Y+

IOExpander_X+

LED4

LED2

IOExpander2

U33

JOY_SEL

JOY_DOWN

JOY_LEFT

JOY_RIGHT

JOY_UP

SmartCard_RST

SmartCard_CMDVCC

SmartCard_3/5V

VDD

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

SmartCard_OFF

BL_Control

EXT_RESET

C132

100nF

SCL

SDA

VCC

GND

TAB

STMPE1600QTR

INT

R243 10K

R232 10K

R230 10K

Default I2C Address:1000010X

R231 R233 R237

[N/A] [N/A] [N/A]

VDD

Title: IO_Expandor

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision: C-02

Sheet: 6 of 25

Figure 38. Power supply

CN22

DC-10B

U31

ZEN056V130A24LS

SMAJ5.0A-TR C124

100nF

SG CG1

CG2

CG3

BNX002-01

C100

220uF

E5V

+5V

C116

4.7uF

R206

[N/A]

U28

ST1L05BPUR

ADJ

R202

[N/A]

R204

20.5K[1%]

R203 11.8K[1%]

C101

100nF

TP17

+3V3

Power Supply 3.3V

Vout=1.22*(1+R1/R2)

C98

10uF[ESR<0.2ohm]

VDD_MCU

VDD_ADJ

VDD_MCU

C48

100nF

+3V3

Recommendation:

JP17

Header 4X2

+5V

TP10

R165

TP8

VDDA

BEAD

VDDA

C59

1uF

GND GND

C60

100nF connected by shunt of

IDD_measurement circuitry

VDD VDD_MCU

VREF+

LD7

Red

100nF decoupling capacitor for each VDD pin

C41

100nF

U5V_STLINK

C50

100nF

U5V

D5V

JP3

Header 2X1

VDD_MCU

C38

E5V

JP10

JP2

JP1

100nF

C42

100nF

C45

100nF

VDD_USB

C32

1uF

TP5

VDD

TP2

TP4

VDD_IO

VDD_USB

C51

VDD_IO

100nF

C43

100nF

VDD_IO

C46

1uF

TP1 TP11 TP18 TP3

+5V

U34

ST1L05BPUR

C35

100nF

121

106

108

144

U7B

VREF+

VDDA

VDD

VDDUSB

131

VDDIO2

VREF-

VBAT

STM32L476ZGT6U

VSSA

VSS

VDD

107

143

120

130

JP12

3 +

BT1

C140

4.7uF

R240

[N/A]

+3V3

CR1220 holder to use a supercapacitor: remove the jumper, and connect positive terminal of the supercapacitor to pin 2 of the jumper.

U27

LD1117S18TR

Vin Vout

Tab

VDD_USB

C33

1uF

C36

100nF

ADJ

R235

10.2K[1%]

RV1

3386P-503H[5%]

TP16

+1V8

1V8

C107

10uF

+5V

R234

[N/A]

R236

20K[1%]

U26

LD1117STR

Vin

R209

232[1%]

Power Supply VDD_ADJ [1.7V to 3.61V]

Vout

Tab

TP13

VDD_ADJ

C133

100nF

Vout=1.22*(1+R1/R2)

VDD_ADJ

C131

10uF[ESR<0.2ohm]

R207

124[1%]

C114

100nF

+3V6

C99

10uF

Vout=1.25*(1+232/124)=3.589V

TP12

3V6

Title: Power

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 7 of 25

Figure 39. Smartcard, SWP and NFC

SWP_IO

+5V

C135

100nF

PB12

+3V3

C138

4.7uF

+3V3

R216

4K7

C136 100nF

C137 100nF

U30

CLKDIV1

CLKDIV2

5V/3V

PGND

C1+

Vddp

C1-

Vup

PRES

I/O

AUX2

AUX1

CGND

AUX2UC

AUX1UC

I/OUC

XTAL2

XTAL1

OFF

GND

Vdd

RSTIN

CMDVCC

PORADJ

Vcc

RST

CLK

ST8024CDR

C117

R211

10K

R212

10K

R210 0

+3V3

TP14

TP15

R217

10K

100nF

SmartCard Connector

CN23

GND

SWIO

I/O

VCC

RST

CLK

C816

R242

100K

+3V3

R218

10K

SmartCard and SWP

IOExpander1

SmartCard_3/5V

AUX2

AUX1

PC4

PB0

IOExpander1

SmartCard_IO

SmartCard_CLK

SmartCard_OFF

C119

100nF

VDD

C112

4.7uF

R241

100K

R213

100K

+3V3

R214

100K

R215

100K

IOExpander1

SmartCard_RST

SmartCard_CMDVCC

Operating range: 2.7<VDD<3.6V

GND

NFC_MOSI

NFC_NSS

NFC_IRQOUTN

+3V3

PB15

PF11

PB7

C78

100nF

CN13

2 female conn 4X2

PB13

PB14

PB6

NFC kit reference: CR95HF-B

Operating Voltage: +3.3V

NFC

NFC_SCK

NFC_MISO

NFC_IRQINN

Title: SWP_SmartCard_NFC

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision:

Sheet: 8

C-02 of 25

Figure 40. USART and IrDA

Bootloader_BOOT0_3V3

Bootloader_RESET_3V3

USART1_CTS_3V3

PG11

USART1_RTS_3V3

R93 0

USART

+3V3

100nF

C62

C64

100nF

GND

U10

C1+

C1-

C2+

C2-

T1IN

T2IN

T3IN

VCC

GND

V+

V-

T1OUT

T2OUT

T3OUT

R1OUTB

R2OUTB

R1OUT

R2OUT

R3OUT

R4OUT

R5OUT

R1IN

R2IN

R3IN

R4IN

R5IN

23 nEN

ST3241EBPR nSHDN

+3V3

C65

100nF

C63

100nF

GND

C61

100nF

CN9

DB9-male

DSR

RXD

RTS

TXD

CTS

PG8

R158 [N/A]

LPUART_RX_3V3

USART1/IrDA_RX_3V3

LPUART_TX

USART1_TX

USART1_RTS

PB7

PG7 R119 [N/A]

PB6

PG12

R118

R116

R114

100K

JP15

Header 3X2

IRDA_RX

NFC_IRQOUTN

C66

100nF

VDD

R117

100K

VCCB

DIR

+3V3

U12

VCCA

GND

SN74LVC2T45DCUT VDD

C69

100nF

USART1_RTS_3V3

VDD

NFC_IRQINN

IRDA

+3V3

C71

4.7uF

C70

100nF

R115 47

R112 5.1

R113

Note:

TFDU6300 (U11) is not populated on boards manufactured starting from middle 2016 (schematic and board revision C02)

U11

TxD

RxD

Anode (VCC2)

Cathode

VCC1

Vlogic

GND

TFDU6300

C67

4.7uF

C68

100nF

Title:

USART_IrDA

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 9 of 25

Figure 41. SRAM and NOR Flash memory devices

D[0..15]

A[0..23]

D[0..15]

A[0..23]

VDD

PD7

R18

R22

10K

FMC_NE1

FMC_NBL0

FMC_NBL1

PE0

PE1

VDD

FMC_NE2

FMC_NWE

FMC_NOE

FMC_NWAIT

PG9

PD5

PD4

PD6

R43

R41

10K

VDD

R32

10K

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A11

A10

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

BLE

BHE

CE2

VCC

VSS

512kx16: IS61WV51216BLL-10MLI

1Mx16: IS61WV102416BLL

2Mx16: CY7C1071DV33-12BAXI

4Mx16: CY62187EV30LL

IS61WV102416BLL-10MLI

D15

D14

D13

D12

D11

D10

VDD

R25

10K

C31 100nF

C12 100nF

VDD

R28

10K

SRAM

C30

100nF

Operating Voltages :

512x16: IS61WV51216BLL-10MLI VDD: 2.4V to 3.6V

1Mx16: IS61WV102416BLL-10MLI VDD: 2.4V to 3.6V

2Mx16: CY7C1071DV33-12BAXI VDD: 3.0V to 3.6V

4Mx16: CY62187EV30LL VDD: 2.2V to 3.7V

VDD

R133

10K

Default setting: Open

JP13

Header 2X1

A18

A17

A16

A15

A14

A13

A12

A11

A23

A22

A21

A20

A19

A10

A18

A17

A16

A15

A14

A13

A12

A11

A10

A23

A22

A21

A20

A19

BYTE

Vpp/WP

VCC

VCCQ

VSS

M29W128GL70ZA6E

M29W256GL70ZA6E

DQ15A-1

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

D15

D14

D13

D12

D11

D10

C20

100nF

C40

100nF

+3V6

VDD

C18

100nF

C19

100nF

Nor Flash

Operating range: 1.65<VDD<3.6V

Title: SRAM&Flash

Project: STM32L476G-EVAL

Size: A3 Reference:

Date: 10/7/2016

MB1144 Revision: C-02

Sheet: 10 of 25

Figure 42. TFT LCD

BL_Control

TFT LCD

R260

R267

22K

R259

47K

BL_VDD

9013-SOT23

C113

100nF

BEAD

LCD_CSN

LCD_RS

LCD_WRN

LCD_RDN

LCD_RSTN

CN19

WR/SCL

RESET

+3V3

C115

10uF BL_VDD

R223

R219

[N/A]

BL_GND

BL_Control

VDD

VCI

GND

BL_VDD

SDO

SDI

+3V3

PD10

PD11

PD12

PD13

PD14

PD15

PD16

PD17

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

LCD_D0

LCD_D1

LCD_D2

LCD_D3

LCD_D4

LCD_D5

LCD_D6

LCD_D7

LCD_D8

LCD_D9

LCD_D10

LCD_D11

LCD_D12

LCD_D13

LCD_D14

LCD_D15

IOExpander_X-

IOExpander_X+

IOExpander_Y-

IOExpander_Y+

2.8'' LCD TFT board MB989P

+5V

16-bit connector

D[0..15]

A[0..23]

D[0..15]

A[0..23]

VDD VDD

LCD_NE3_BUF

R161

10K

U22

D15

D14

D13

D12

D11

D10

LCD_NE3_BUF 25

VDD

C79

100nF

DIR

R166

10K

LCD_D15

LCD_D14

LCD_D13

LCD_D12

LCD_D11

LCD_D10

LCD_D9

LCD_D8

DIR

VCCA

VCCB

GND

SN74LVC16T245DGGR

LCD_D7

LCD_D6

LCD_D5

LCD_D4

LCD_D3

LCD_D2

LCD_D1

LCD_D0

A1_BUF

C85

100nF

+3V3

LCD_NE3

FMC_NWE

FMC_NOE

RESET#

VDD

U21

LCD_NE3

VDD

C83

100nF

PF0

PG10

PD5

PD4

A0_1DELAY

NE3_1DELAY

OE DIR

VCCA

VCCB

GND

SN74LVC16T245DGGR

VDD

A0_1DELAY

NE3_1DELAY

LCD_WRN

LCD_RDN

LCD_RSTN

A0_2DELAY

NE3_2DELAY

A1_1DELAY

VDD

C84

100nF

+3V3

A0_1DELAY

A0_2DELAY

SB44

Open by default

SB45

Closed by default

NE3_1DELAY

NE3_2DELAY

SB46

Open by default

SB47

Closed by default

NE3_1DELAY

LCD_NE3

SB48

SB49

Closed by default

Open by default

A1_1DELAY

SB50

Closed by default

SB51

Open by default

LCD_RS

LCD_CSN

LCD_NE3_BUF

A1_BUF

Title: LCD_TFT

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 11 of 25

Figure 43. Extension connector

PG6

PA13

PA12

PG8

PG2

PD3

PD0

PD5

PG10

PD7

PF0

PG11

PG13

PG12

PG14

PG15

PF4

Left

CN6

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

9 10

11 12

13 14

15 16

17 18

P1039-2*20MGF-089-1A townes

PG3

PG4

PD1

PD4

PG9

R44

PG7

PA11

PA14

PG5

PD6

PF1

PF2

PF3

PF5

PB6

R80

+3V3

820

D5V

PC13

PC15

PC14

SB33

Open by default

SB41

Open by default

PH1

PH0

SB23

Open by default

SB24

Open by default close to MCU

PF12

PF11

PE4

PE5

PF6

PF9

PF10

PA5

PA0

PE14

PE12

PE10

PE8

PG1

PB2

Right

CN7

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

9 10

11 12

13 14

15 16

17 18

PF7

PF8

PC3

PA4

P1039-2*20MGF-089-1A townes

PE15

PE13

PE11

PE9

PE7

PG0

PF15

PF14

PF13

BOOT0

PE6

R79 820

VDD

RESET#

PH0

PH1

BOOT0

PA[0..15]

PB[0..15]

PC[0..15]

PD[0..15]

PE[0..15]

PF[0..15]

PG[0..15]

RESET#

PH0

PH1

BOOT0

Title:

Extension connector

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision:

Sheet: 12

C-02 of 25

Figure 44. Quad-SPI Flash memory device

VDD

PB11

R71

R74

10K

QSPI_CS

QSPI_D1

PB0

QSPI_D2

PA7

GND

VDD

N25Q256A13EF840E

MICRON

Quad SPI Memory

Operating range: 2.7<VDD<3.6V

C44

100nF

GND

PA6

PB10

PB1

QSPI_D3

QSPI_CLK

QSPI_D0

Title: QSPI

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 13 of 25

Figure 45. microSD card uSD_D1 uSD_D0 uSD_D3 uSD_D2 uSD_CLK uSD_CMD

PC9

PC8

PC11

PC10

PC12

PD2

VDD C90

R175

47K

R182

47K

R185

47K

R176

47K

R178

47K

100nF

CN18

PJS008-2000 (SMS064FF or SMS128FF) uSD_DETECT

PA8

R194

MicroSD card

Operating Voltage: VDD no Lower than 2.7V

ZZ1 micro SD card

Title: MicroSD

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 14 of 25

Figure 46. Physical control peripherals

Comp2_INP

Comp2_OUT

PB4

PB5

Comp2_INP

Comp2_OUT

VDD

RV3

3386P-103(10K)

VDD

R51

8.2K

Potentiometer

LDR

JP5

TP6

COMP2_OUT

Comparator

STM32L

Comp2_INP

PB4

Comp2

PB5

JP7

OpAmp/ADC

Comp2_OUT

R52

VT9ON1

TP9

OA1_OUT

OpAmp1_OUT

PA3

STM32L

OpAmp1

PA0

OpAmp1_INP

R63

PA1 OpAmp1_INM

R120 [N/A]

R121

3 1

RV2

3314J-1-103

Variable gain

VDD

OpAmp1_OUT

OpAmp1_INM

OpAmp1_INP

PA3

PA1

PA0

OpAmp1_OUT

OpAmp1_INM

OpAmp1_INP

ADC_DAC

PA4

CN8

Header 2X1

R73

C47

[N/A]

1 2

R72 0

VDDA

CN10

Header 2X1

R92

C52

100nF

VREF+

Close to MCU on PCB Close to MCU on PCB

VDD

WKUP

ADC&DAC connector and Reference Voltage

R245

220K

R244

330

PC13

KEY

+3V3

LD1

Green

LD2

Orange

LD3

Red

LD4

Blue

WKUP/TAMPER Button LEDs

R258

510

R257

680

R256

680

R255

680

VDD

R251

100

COMMON

Selection

PB2

LED1

I/Oexpander

LED2

PC1

LED3

I/Oexpander

LED4

JOY_SEL

JOY_DOWN

JOY_LEFT

JOY_RIGHT

JOY_UP

DWON

LEFT

RIGHT

MT008-A

Joystick

Potentiometer/LDR

Title: peripherals

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision:

Sheet: 15

C-02 of 25

Figure 47. CAN transceiver

CAN_TX

CAN_RX

PB9 R75 0

PB8 R76 0

VDD

C49

R45

10K

100nF

GND

VCC

SN65HVD230

CANH

CANL

Vref

Operating voltage range: 3.0<VDD<3.6V

R46

VDD

Default setting: 1<->2

Default setting: Open

JP4

JP6

Header 2X1

R55

120

ESDCAN24-2BLY

Optional R70

[N/A]

+3V3

CN5

DB9-male

R77

Title: CAN

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 16 of 25

Figure 48. Touch-sensing device

TKEY_CS

PB13

ESD resistor close to MCU pad

TKEY

SHIELD

SHIELD_CS

PB12

R40

10K

PC6

PC7

R37

C37

22nF(COG)GRM3195C1H223JA01L

C34

220nF

TS1

TS_PAD

<----Touch Sensing diameter 10mm min on active shield diameter 12mm min

Title: Touch Sensing

Project: STM32L476G-EVAL

Size: A4 Reference:

Date: 10/7/2016

MB1144 Revision: C-02

Sheet: 17 of 25

Figure 49. USB_OTG_FS port

+3V3

620

USBOTG_PPWR

PC6

JP19

Header 2X1

+5V

R21

10K

GND

FAULT

OUT

STMPS2151STR

47K

C15

4.7uF

LD6

Red

PB12

USBOTG_OVRCR

U5V

CN1

VBUS

GND

Shield

EXP

475900001

USBOTG_PRDY

USBOTG_VBUS

USBOTG_DM

USBOTG_DP

USBOTG_ID

PB13

PA9

PA11

PA12

PA10 R5 0

Vbus

D+out

D-out

Pup

D+in

D-in

Pd1

Pd2

GND

EMIF02-USB03F2

47K

R261

22K

+3V3

330

LD5

Green

VBUS OK

9013-SOT23 transistor pins numbers follow

SOT23 JEDEC standard,

USB Full Speed operating range voltage: 3.0V<VDDUSB<3.6V

Title: USB_OTG_FS

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 18 of 25

Figure 50. IDD measurement bypass path

Current direction

VDD from power supply

VDD

Shunt_x1000 3

FDC606P

R135

1[1%] shunts

R123

1K[1%] current measurement

path

+5V

GND

R128

22K

C144

100nF

R124

GND

C75

100nF decoupling capacitor close from TSZ124 part

V+

V-

U15A

TSZ124IPT

GND

U15B

TSZ124IPT

R136

3K6 0.1% differential amplifier

U15D

TSZ124IPT

R125

3K6 0.1%

R129

180K 0.1%

U15C

TSZ124IPT

R132

180K 0.1%

Shunt_x1000

VDD

C76

100nF

U13

I/O

GND

O/I

VCC

VDD

SN74LVC1G66DCKT

C74

100nF

R122

10K

T3 4

VDD

PA5

IDD_Measurement

U16

SN74LVC1G04DCKT VDD

U14

Q11

Q12

Q13

GND

74LV4060PW

VCC

Rtc

Ctc

C77

1nF

FDC606P

C72

100nF

VDD

R127

220K

PC5

R137

220K

IDD_WAKEUP

PF10

IDD_CNT_EN

R134

15K

R130

30K

Oscillator frequency 30KHz

JP11

Current direction

VDD_MCU to MCU

Title:

IDD_measurement

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 19 of 25

Figure 51. Audio codec device

VDD

JP16

MICBIAS1

+3V3

VDD

DFSDM_CKOUT

R238 10K

U35

VDD

GND

MP34DT01TR

CLK

DOUT

U36

VDD

GND

MP34DT01TR

CLK

DOUT

+1V8

PC2

+1V8

JP14

SAI1_SCKB

SAI1_FSB

SAI1_SDB

SAI1_SDA

CODEC_INT

R201

R208

R198

R205

R199

PC0

VDD

R200 10K

C108 1uF

DMIC_DATIN

PF8

PF9

PF6

PD6

PG6

U29

LDO1VDD

AVDD1

SPKVDD1

SPKVDD2

AVDD2

CPVDD

DCVDD

DBVDD

LDO2VDD

LDO1ENA

LDO2ENA

VREFC

DMICCLK

BCLK1

LRCLK1

DACDAT1

ADCDAT1

ADCLRCLK1/GPIO1

GPIO3/BCLK2

GPIO4/LRCLK2

GPIO5/DACDAT2

GPIO7/ADCDAT2

GPIO6/ADCLRCLK2

GPIO11/BCLK3

GPIO10/LRCLK3

GPIO8/DACDAT3

GPIO9/ADCDAT3

IN1LP

IN1LN

Default I2C Address:0011010

AGND

SPKGND1

SPKGND2

CPGND

DGND

HP2GND

SDA

SCLK

CS/ADDR

CIFMODE

MCLK1

GPIO2/MCLK2

SPKMODE

REFGND

MICBIAS1

MICBIAS2

VMIDC

HPOUT2N

HPOUT2P

HPOUT1FB

HPOUT1R

HPOUT1L

LINEOUT1N

LINEOUT1P

LINEOUT2N

LINEOUT2P

LINEOUTFB

R197 [N/A]

R222

C125

4.7uF

PG13

PG14

VDD

PF7

C127

4.7uF

R195

R196

IN2LP/VRXN

IN2LN/DMICDAT1

IN1RP

IN1RN

SPKOUTLN

SPKOUTLP

IN2RP/VRXP

IN2RN/DMICDAT2

WM8994ECS/R

SPKOUTRN

SPKOUTRP

CPCA

CPCB

CPVOUTN

CPVOUTP

C102

G7 C104

C103

2.2uF

I2C_SDA

I2C_SCL

SAI1_MCKB

C128

4.7uF

GND

C130

R224

R225

180

4.7uF

C129

4.7uF

R226

R227

180

GND

Operating range: 1.62<VDD<3.6V

R191

CN20

GND

R192

R220

PJ3028B-3

GND

CN21

GND

PJ3028B-3

R221

GND

Title: Audio

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 20 of 25

Figure 52. STPMS2L and PT100

STPMS2 power metering

CN4

GND external generator input: pins 1 and 3 voltage of complex load: pins 2 and 3

shunt voltage : pins 1 and 2 current shunt

R26

R27

GND

R+jX Load

C26

100nF

GND

STPMS2L-PUR

CIP

CIN

VIP

VIN

Exposed pad GND

C27

1uF

GND

VDD

DATn

MS3

DAT

CLK

GND

C25

PT100 measurement using SigmaDelta STPMS2

100nF

VDD current shunt

R29

3K3

R31

100 1%

GND

STPMS2L-PUR

CIP

CIN

R30

PT100

VIP

VIN

C28 1uF

GND

VDD

Exposed pad GND

DATn

GND

DAT

CLK

MS3

GND

C24

1uF

GND

C23

1uF

GND

PD3

PC2

R23 0

DFSDM_DATIN1

DFSDM_CKOUT

Operating range: 3.2<VDD<3.6V

PC7 R24 0

PT100_DATIN

Title: STPMS2&PT100

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 21 of 25

Figure 53. RF-EEPROM and EEPROM

I2C_SDA

I2C_SCL

I2C_SDA

I2C_SCL

RFEEPROM module MB102 A02

I2C address: 0xA6

PG13

PG14

EXT/RFEEPROM Connector

VDD

CN3

GPIO10_IOExpander2

7 8

F206A-2*04MGF-A

SSM-104-L-DH (Samtec)

SB43

Open by default

+5V

EXT_RESET

GND

C39

100nF

VSS

VCC

SCL

SDA

M24128-DFDW6TP

M24C64-FDW6TP

PB10

PB11

VDD GND

R42

10K

SB7

Closed by default

GND

I2C EEPROM

I2C address: 0xA0 operating voltage ranges:

1MHz 64Kbit I2C memory M24C64-FDW6TP: 1.7 to 5.5V

1MHz 128Kbit I2C memory M24128-FDW6TP: 1.7 to 5.5V

I2C2_SCL

I2C2_SDA

Title: RF_I2C_EEPROM

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 22 of 25

Figure 54. Motor control connector

MC_EmergencySTOP

MC_CurrentA

MC_CurrentB

MC_CurrentC

PC9

PC0

PC1

PC2

R11 0

C14

[N/A]

R10 0

C13

[N/A]

R17 0

C10

[N/A]

+3V3

R14

3K3

1nF

MC_PFC_sync

PF9 R15 0

C16

[N/A]

MC_PWM_1H

MC_PWM_1L

MC_PWM_2H

MC_PWM_2L

MC_PWM_3H

MC_PWM_3L

PC6

PA7

PC7

PB0

PC8

PB1

MC_ICL_Shutout

MC_DissipativeBrake

MC_PFC_PWM

MC_EncA

MC_EncB

PG6

PB2

+5V

PF10

PA0

PA1

Motor control connector

CN2

EMERGENCY STOP

PWM_1H

PWM_1L

PWM_2H

PWM_2L

PWM_3H

PWM_3L

PHASE A CURRENT +

PHASE B CURRENT +

PHASE C CURRENT +

ICL shut out

DISSIPATIVE BRAKE

+5V POWER

PFC SYNC

PFC PWM

Encoder A

Encoder B

MC_connector

GND

BUS VOLTAGE

PHASE A CURRENT -

PHASE B CURRENT -

PHASE C CURRENT -

GND

PFC Inductor current

Heatsink Temperature

3.3V Power

PFC Shut down

PFC Vac

Encoder Index

+3V3

[N/A]

SB1

[N/A]

10nF

[N/A]

R13

C11

100nF

R19

100K

PC5

MC_BusVoltage

100nF

PC4

MC_PFC_IndCurr

+3V3

R16

R20

3K3

C17

100nF

PA3

MC_Temperature

PB12

MC_PFC_Shutdown

1nF

R12

PA6

MC_PFC_Vac

[N/A]

PA2

MC_EncIndex

[N/A]

Title: MotorControl

Project: STM32L476G-EVAL

Size: A4 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 23 of 25

Figure 55. JTAG and trace debug connectors

TMS/SWDIO

TCK/SWCLK

TDO/SWO

TDI

TRST

RESET#

RS1

Trace connector

CN12

FTSH-110-01-L-DV

VDD

KEY

R154 0

R162 [N/A]

R156 0

R131 [N/A]

PA13

PA14

PB3

PA15

PB4

VDD

R153 R160 R152 R126

[N/A] [N/A] [N/A] [N/A]

R155

[N/A]

CN15

JTAG

VDD

GND

U17

IO1

GND

IO4

IO2 IO3

ESDALC6V1W5

R163

R164

10K

GND

U18

IO1

GND

IO4

IO2 IO3

ESDALC6V1W5

VDD

R157

[N/A]

R159

10K

JTAG connector

GND

U19

IO1 IO4

GND

IO2 IO3

ESDALC6V1W5

TRACE_D3

TRACE_D2

TRACE_D1

TRACE_D0

TRACE_CK

PE6

PE5

PE4

PE3

PE2

Title: JTAG&Trace

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 24 of 25

Figure 56. ST-LINK/V2-1

C89

20pF 1

+3V3_STLINK

C94

100nF

+3V3_STLINK

8MHz

R181

100K

STLINK virtual comport using LPUART:

R182/R187 not fitted, R58/R178 fitted.

C93

100nF

LPUART_RX_3V3

LPUART_TX

R193

100K

C88

20pF

C87

100nF

R190

100K

R174

PG8

PG7

R189

VDD

C86

100nF

R172

+3V3_STLINK

[N/A]

SWIM_PU_CTRL

OSC_IN

OSC_OUT

STM_RST

+3V3_STLINK

C91

10K

100nF

AIN_1

VBAT

PC13

PC14

PC15

OSC_IN

OSC_OUT

/RST

VSSA

VDDA

PA0

PA1

U2_TX

R188

C97

100nF

U25

VCCA

GND

+3V3_STLINK

C96

100nF

VCCB

DIR

+5V

+3V3_STLINK

R168

100K

SN74LVC2T45DCUT VDD

R169 2K2

JP18

Header 2X1

R187

100K

R170 4K7

GND

E5V

USB_RENUMn

U5V

BAT60JFILM

C80

BAT60JFILM

D7 1uF

U20

Vin

LD3985M33R

Vout

INH

GND BYPASS

+3V3_STLINK

C81

1uF

VDD

VDD_2

VSS_2

JTMS

PA12

PA11

PA10

PA9

PA8

S2_MOSI

S2_MISO

S2_CK

PB12

STM_JTCK_SWCLK

U23

STM32F103CBT6

D5V

BAT60JFILM

GND GND LED_STLINK

VUSB_ST_LINK

BAT60JFILM

+3V3_STLINK

STM_JTMS_SWDIO

STL_USB_DP

STL_USB_DM

T_SWO

LED_STLINK

MCO

PWR_ENn

T_JTMS

T_JTCK

T_SWDIO_IN

VUSB_ST_LINK

C145

R268

R110

100nF

LD9

Red

100K

R262

10K

Power Switch to supply +5V from STLINK USB

GND

U37

ST890CDR

FAULT

C143

100nF

U5V_STLINK

OUT

SET

5 output current limitation : 600mA

ON GND

R184

2K2

Red

R186

4K7

R183

4K7

R253

100

R254

100

R252

AIN_1

Yellow

LD8

HSMF-A201-A00J1

+3V3_STLINK

MCU C95

+3V3_STLINK

VDD C92

TP19

STM_JTMS_SWDIO

STM_JTCK_SWCLK

CN16

[N/A]

100nF

T_SWDIO_IN

T_JTDO

T_SWO

U24

VccA

GND

VccB

DIR

SN74LVC2T45DCUT

100nF

TDO/SWO

+3V3_STLINK

VUSB_ST_LINK

CN17

VCC

D-

D+

GND

SHELL

USB-typeB connector

R180

R179

USB_RENUMn

R173

100

STL_USB_DM

STL_USB_DP

R177

1.5K

R167

10K

R171

36K

9013-SOT23 transistor pins numbers follow

SOT23 JEDEC standard,

USB

T_JTMS

T_NRST

T_JRST

T_JTDI

T_JTCK

TMS/SWDIO

RESET#

TRST

TDI

TCK/SWCLK

Title: ST_LINK

Project: STM32L476G-EVAL

Size: A3 Reference: MB1144

Date: 10/7/2016

Revision: C-02

Sheet: 25 of 25

UM1855 Federal Communications Commission (FCC) and Industry Canada (IC) Compliance

Appendix B Federal Communications Commission (FCC) and Industry Canada (IC) Compliance

Statements

B.1 FCC Compliance Statement

B.1.2

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Part 15.105

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference's by one or more of the following measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and the receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

• Consult the dealer or an experienced radio/TV technician for help.

B.2

Any changes or modifications to this equipment not expressly approved by

STMicroelectronics may cause harmful interference and void the user's authority to operate this equipment.

IC Compliance Statement

B.2.2

Industry Canada ICES-003 Compliance Label: CAN ICES-3 (B)/NMB-3(B)

Déclaration de conformité

Étiquette de conformité à la NMB-003 d'Industrie Canada : CAN ICES-3 (B)/NMB-3(B)

DocID027351 Rev 5

99/101

100

Revision history UM1855

Date

22-Jul-2015

29-Jul-2015

09-Sep-2015

07-Jul-2016

20-Nov-2016

Table 46. Document revision history

Revision Changes

Initial Version

Added Section 2.6.2: Bootloader limitations

Classification change from ST Restricted to Public.

Figure 3 : swap of FAULT and VBUS prints in the upper-left

corner of the board.

Section 2.8.3

: swap of LD5 and LD6.

: modified

Table 13 : JP6 default setting modified.

Section 2.5

and

Section 2.9.1

: JP9 by-default setting added.

Table 31 : JP11 default setting modified and position

information added.

Table 8

: JP19 default setting modified.

Table 42 : CN2 instead of CN1

Section 3.2

: CN2 corrected in CN22

Multiple language or typographical corrections.

Updated Table 33: CN11 and CN14 daughterboard connectors .

Updated:

Introduction , Features ,

Section 2: Hardware layout and configuration ,

Section 2.9: RS-232 and IrDA ports

, since IrDA transceiver is no more supported from board revision C-02.

Updated board schematics in

Section Appendix A: Schematic diagrams .

100/101

DocID027351 Rev 5

UM1855

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DocID027351 Rev 5 101/101

101

UM1855

User manual

Evaluation board with STM32L476ZGT6 MCU

Introduction

Contents

List of tables

List of figures

1 Overview

1.1 Features

2

Hardware layout and configuration

2.1 ST-LINK/V2-1

2.6 Boot

2.7 Audio

2.8

USB OTG FS port

2.9

RS-232 and IrDA ports

2.13 CAN

2.15 LCD glass module daughterboard

2.16 TFT LCD panel

2.18 Physical input devices

2.19 Operational amplifier and comparator

2.20 Analog input, output, VREF

2.22 NOR Flash memory device

2.23 EEPROM

2.24 RF-EEPROM

2.28 Near-field communication (NFC)

2.29 Dual-channel sigma-delta modulators STPMS2L

2.30 STM32L476ZGT6 current consumption measurement

3 Connectors

3.1 RS-232 D-sub male connector CN9

3.3

LCD daughterboard connectors CN11 and CN14

3.5

3.6

ST-LINK/V2-1 programming connector CN16

ST-LINK/V2-1 Standard-B USB connector CN17

3.7 JTAG connector CN15

3.8 ETM trace debugging connector CN12

3.9 microSD card connector CN18

(YDOXDWLRQERDUG

&1

3.10 ADC/DAC connector CN8

3.12 Motor control connector CN2

3.13 USB OTG FS Micro-AB connector CN1

3.14 CAN D-sub male connector CN5

3.15 NFC connector CN13

Appendix A Schematic diagrams

Appendix B Federal Communications Commission (FCC) and Industry Canada (IC) Compliance

Statements

B.1 FCC Compliance Statement

B.2

IC Compliance Statement

Related

STMicroelectronics STM32L476G-EVAL User manual

STMicroelectronics STM32L476G-EVAL User manual

Insignia NS-PH3A4AS 4-Port USB 3.0 Hub Quick Setup Guide

STMicroelectronics STM32CubeL4 User Manual

GigaDevice Semiconductor GD32150R-EVAL User Manual

GD32E230C-EVAL User Manual - GigaDevice Semiconductor

STMicroelectronics STM8L1528-EVAL User Manual

Abov AC33M8128L User Manual

STMicroelectronics STM32746G-EVAL User Manual

STM32L476G Discovery Kit User Manual

STM3210E EVAL Evaluation Board User Manual

STMICROELECTRONICS STMICROELECTRONICS STM32746G-EVAL2 Evaluation Board Operating instructions