The L6599AF is an improved revision of the previous L6599A. It is a double-ended controller specific to series-resonant half bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180 ° out-ofphase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed deadtime inserted between the turn-off of one switch and the turn-on of the other guarantees soft-switching and enables high-frequency operation.

To drive the high-side switch with the bootstrap approach, the IC incorporates a high voltage floating structure able to withstand more than 600 V with a synchronous-driven high voltage

DMOS that replaces the external fast-recovery bootstrap diode.

The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.

At startup, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non-linear to minimize output voltage overshoots; its duration is programmable as well.

At light load the IC may enter a controlled burst mode operation that keeps the converter input consumption to a minimum.

IC functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short-circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP.

An interface with the PFC controller is provided that enables the pre-regulator to be switched off during fault conditions, such as OCP shutdown and DIS high, or during burst mode operation.

DocID028175 Rev 4 3/32

Block diagram

Figure 1. Block diagram

L6599AF

4/32 DocID028175 Rev 4

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L6599AF Pin connection

Figure 2. Pin connection (top view)

Pin no.

Type

Css

DELAY

RFmin

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Table 2. Pin description

Function

Soft-start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5

V, DELAY > 2 V) to make sure it is soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75 V.

Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the

ISEN pin exceeds 0.8 V, the capacitor is charged by an internal 150 µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2 V, the soft-start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops switching and the internal generator is turned off, so that the voltage on the pin decays because of the external resistor. The IC is soft-restarted as the voltage drops below

0.3 V. In this way, under short-circuit conditions, the converter works intermittently with very low input average power.

Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.

Minimum oscillator frequency setting. This pin provides a precise 2 V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler is connected to this pin through a resistor. The value of this resistor sets the maximum operating frequency.

An R-C series connected from this pin to GND sets frequency shift at startup to prevent excessive energy inrush (soft-start).

DocID028175 Rev 4 5/32

Pin connection L6599AF

Pin no.

Type

Table 2. Pin description (continued)

Function

STBY

ISEN

LINE

DIS

GND

LVG

Vcc

Burst mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.24 V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked.

This function realizes burst mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin

(see block diagram). Tie the pin to RFmin if burst mode is not used.

Current sense input. The pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; therefore the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8 V threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases, so limiting the power throughput. Under output short-circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at

1.5 V latches the device off and brings its consumption almost to a “before startup” level.

The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.

Line sensing input. The pin is to be connected to the high voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.24 V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC operation is re-enabled (soft-started) as the voltage exceeds 1.24 V.

The comparator is provided with current hysteresis: an internal 13 µA current generator is

ON as long as the voltage applied at the pin is below 1.24 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal Zener diode. Activating the Zener diode causes the IC to shut down (not latched). Bias the pin between 1.24 and 6 V if the function is not used.

Latched device shutdown. Internally, the pin connects a comparator that, when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings its consumption almost to a “before startup” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.

PFC_STOP

Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for stopping the PFC controller, for protection purposes or during burst mode operation. It goes low when the IC is shut down by DIS>1.85 V, ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V.

The pin is pulled low also when the voltage on the DELAY exceeds 2 V and goes back open as the voltage falls below 0.3 V. During UVLO, it is open. Leave the pin unconnected if not used.

Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A min. sink peak current to drive the lower MOSFET of the half bridge leg. The pin is actively pulled to

GND during UVLO.

Supply voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be useful to get a clean bias voltage for the signal part of the IC.

6/32 DocID028175 Rev 4

L6599AF Pin connection

Pin no.

Type

N.C.

OUT

HVG

VBOOT

Table 2. Pin description (continued)

Function high voltage spacer. The pin is not internally connected to isolate the high voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.

High-side gate-drive floating ground. Current return for the high-side gate-drive current.

Layout carefully the connection of this pin to avoid too large spikes below ground.

High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A min. sink peak current to drive the upper MOSFET of the half bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.

High-side gate-drive floating supply voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate drive. This patented structure replaces the normally used external diode.

DocID028175 Rev 4 7/32

Electrical data L6599AF

4.1

Note:

Absolute maximum ratings

Symbol

BOOT

HVG

OUT dV

OUT

/dt

Vcc

LVG

PFC_STOP

LINEmax

RFmin

---

Ptot

Tstg

Pin

Table 3. Absolute maximum rating

Parameter Value Unit

Floating supply voltage

HVG voltage

Floating ground voltage

Floating ground max. slew rate

IC supply voltage (Icc = 25 mA)

LVG voltage

Maximum voltage (pin open)

Maximum sink current (pin low)

Maximum pin voltage (Ipin  1 mA)

Maximum source current

1 to 6, 8 Analog inputs and outputs

Power dissipation at T

= 70 °C (DIP16)

Power dissipation at T

= 50 °C (SO16)

Junction temperature operating range

Storage temperature

-1 to 618

OUT

-0.3 to V

BOOT

+0.3

-3 up to a value included in the range V

BOOT and V

BOOT

-18

V/ns

Self-limited V

-0.3 to V

+0.3 V

-0.3 to Vcc V

Self-limited A

Self-limited V

-0.3 to 5

0.83

-50 to 150

-55 to 150

°C

°C mA

ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.

Table 4. Thermal data

Symbol Parameter

R th(JA)

Max. thermal resistance junction to ambient (SO16)

Value

120

Unit

°C/W

8/32 DocID028175 Rev 4

L6599AF Electrical characteristics

= - 50 to 125 °C, V

= 15 V, VBOOT = 15 V, C

HVG

= C

LVG

= 1 nF; C

= 470 pF;

RFmin

= 12 k  ; unless otherwise specified.

Parameter

Table 5. Electrical characteristics

Test condition Min.

Typ.

Max.

Unit Symbol

IC supply voltage

Vcc

Off

Hys

Operating range

Turn-on threshold

Turn-off threshold

Hysteresis

Vcc clamp voltage

Supply current

After device turn-on

Voltage rising

Voltage falling

Iclamp = 15 mA

I start-up

I q op q

Startup current

Quiescent current

Operating current

Residual consumption

Before device turn-on

Vcc = Vcc

- 0.2 V

Device on, V

STBY

= 1 V

Device on, V

STBY

= V

RFmin

DIS

> 1.85 V or V

DELAY

> 3.5 V or V

LINE

< 1.24 V or V

LINE

= V clamp

High-side floating gate-drive supply

LKBOOT

LKOUT

DS(on)

BOOT

pin leakage current V

OUT pin leakage current

Synchronous bootstrap diode on-resistance

BOOT

OUT

LVG

= 580 V

= 562 V

= HIGH

Overcurrent comparator

I t

ISEN

LEB

ISENx

ISENdis td

(H-L)

Line sensing

Input bias current

Leading edge blanking

ISEN

= 0 to V

ISENdis

After V

HVG transition

and V

LVG

low-to-high

Frequency shift threshold Voltage rising

(1)

Hysteresis

Latch-off threshold

Voltage falling

Voltage rising

(1)

Delay to output -

Vth

Hys

V clamp

Threshold voltage

Current hysteresis

Clamp level

Voltage rising or falling (1)

LINE

= 1.1 V

LINE

= 1 mA

8.85

10 10.7

11.4

7.45

8.15

8.85

2.55

17 -

0.76

1.44

200 250

1.5

3.5

150

250

300 400

-1

0.8

0.84

50 -

1.5

1.56

300 400

1.2

1.24

1.28

10 13 16

6 8

µA mA mA

µA

µA ns

µA

V mV

V ns

µA



DocID028175 Rev 4 9/32

Electrical characteristics L6599AF

Symbol

Table 5. Electrical characteristics (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

DIS function

DIS

Vth

Oscillator

Input bias current

Disable threshold

DIS

= 0 to Vth

Voltage rising

(1)

D f osc

CFp

CFv

Output duty cycle

Oscillation frequency

Deadtime

Peak value

Valley value

(1)

Both HVG and LVG

RFmin

= 2.7 k 

Between HVG and LVG

REF

Voltage reference at pin 4

Current mirroring ratio

PFC_STOP function

REF

= -2 mA

(1)

I leak

PFC_STOP

High level leakage current V

PFC_STOP

= Vcc, V

DIS

= 0 V

ON-state resistance

PFC_STOP

= 1 mA,

DIS

= 1.5 V

Low saturation level

PFC_STOP

= 1 mA,

DIS

= 1.5 V

Soft-start function

V(Css) = 2 V

ISEN

> V

ISENx

I leak

Open-state current

Discharge resistance

Standby function

DIS

Vth

Hys

Input bias current

Disable threshold

Hysteresis

Delayed shutdown function

I leak

Open-state current

DIS

= 0 to Vth

Voltage falling

(1)

Voltage rising

CHARGE

Charge current

V(DELAY) = 0

DELAY

= 1 V,

ISEN

= 0.85 V

Vth

Threshold for forced operation at max. frequency

Shutdown threshold

Restart threshold

Voltage rising (1)

Voltage rising

(1)

Voltage falling

(1)

-1

1.78

1.85

1.92

58.2

65.8

240 250 260

0.2

0.3

0.4

1.93

1.8

3.9

0.9

2.07

2.2

130 200

120

0.2

0.5

-1

1.2

1.24

1.28

50 -

0.5

100 150 200

1.98

2.05

2.12

3.35

3.5

3.65

0.3

0.33

0.36

µA

% kHz

µA

V mV

µs

A/A

µA



µA



µA

10/32 DocID028175 Rev 4

L6599AF Electrical characteristics

Symbol

Table 5. Electrical characteristics (continued)

Parameter Test condition

Low-side gate driver (voltages referred to GND)

LVGL

LVGH

I sourcepk

I sinkpk t f t r

Output low voltage

Output high voltage

Peak source current

Peak sink current

Fall time

I sink

= 200 mA

I source

= 5 mA

Rise time

UVLO saturation

Vcc = 0 to Vcc

I sink

= 2 mA

High-side gate driver (voltages referred to OUT)

LVGL

LVGH

I sourcepk

I sinkpk t f t r

Output low voltage

Output high voltage

Peak source current

Peak sink current

Fall time

Rise time

HVG-OUT pull-down

1. Values tracking each other.

I sink

= 200 mA

I source

= 5 mA

Min.

Typ.

Max.

Unit

12.8

13.3

-0.3

0.7

12.8

13.3

-0.3

0.7

1.8

1.1

A ns ns

A ns ns k 

DocID028175 Rev 4 11/32

Application information L6599AF

The L6599AF is an advanced double-ended controller specific for resonant half bridge

topology (see Figure 4 ). In these converters the switches (MOSFETs) of the half bridge leg

are alternately switched on and off (180° out-of-phase) for exactly the same time. This is commonly referred to as operation at “50% duty cycle”, although the real duty cycle, that is the ratio of the ON-time of either switch to the switching period, is actually less than 50%.

The reason is that there is an internally fixed deadtime T

inserted between the turn-off of either MOSFET and the turn-on of the other one, where both MOSFETs are off. This deadtime is essential in order for the converter to work correctly: it ensures soft-switching and enables high-frequency operation with high efficiency and low EMI emissions.

To perform converter output voltage regulation the device is able to operate in different modes (

Figure 3 ), depending on the load conditions:

Variable frequency at heavy and medium/light load. A relaxation oscillator (see

Section 6.1: Oscillator for more details) generates a symmetrical triangular waveform,

which the MOSFET switching is locked to. The frequency of this waveform is related to a current that is modulated by the feedback circuitry. As a result, the tank circuit driven by the half bridge is stimulated at a frequency dictated by the feedback loop to keep the output voltage regulated, therefore exploiting its frequency-dependent transfer characteristics.

2. Burst mode control with no or very light load. When the load falls below a value, the converter enters a controlled intermittent operation, where a series of a few switching cycles at a nearly fixed frequency are spaced out by long idle periods where both

MOSFETs are in OFF-state. A further load decrease is translated into longer idle periods and then in a reduction of the average switching frequency. When the converter is completely unloaded, the average switching frequency can go down even to few hundred hertz, therefore minimizing magnetizing current losses as well as all frequency-related losses and making it easier to comply with energy saving recommendations.

Figure 3. Multi-mode operation of the L6599AF

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12/32 DocID028175 Rev 4

L6599AF Application information

Figure 4. Typical system block diagram

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6.1 Oscillator

The oscillator is programmed externally by means of a capacitor (CF), connected from the pin 3 (CF) to ground, that is alternately charged and discharged by the current defined with the network connected to pin 4 (RF min

). The pin provides an accurate 2 V reference with about 2 mA source capability and the higher the current sourced by the pin is, the higher the oscillator frequency is. The block diagram of

Figure 5 shows a simplified internal circuit that

explains the operation.

The network that loads the R

Fmin

pin is generally made up of three branches:

A resistor RF min connected between the pin and ground that determines the minimum operating frequency.

RF max connected between the pin and the collector of the (emitter-grounded) phototransistor that transfers the feedback signal from the secondary side back to the primary side; while in operation, the phototransistor modulates the current through this branch - therefore modulating the oscillator frequency - to perform output voltage regulation; the value of RF max

determines the maximum frequency the half bridge is operated at when the phototransistor is fully saturated.

3. An R-C series circuit (CSS+RSS) connected between the pin and ground that enables a frequency shift to be set up at startup (see

Section 6.3: Soft-start on page 18 ). Note

that the contribution of this branch is zero during steady-state operation.

DocID028175 Rev 4 13/32

Application information

Figure 5. Oscillator internal block diagram

L6599AF

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The following approximate relationships hold for the minimum and the maximum oscillator frequency respectively:

Equation 1 f min



 CF  RF min

; f max



3  CF





RF min

// RF max



After fixing CF in the hundred pF or in the nF (consistently with the maximum source capability of the RF min

pin and trading this off against the total consumption of the device), the value of RF min

and RF max is selected so that the oscillator frequency is able to cover the entire range needed for regulation, from the minimum value f min and maximum load) to the maximum value f max load):

(at minimum input voltage

(at maximum input voltage and minimum

Equation 2

RF min



 CF  f min

; RF max



RF min f max  f min

A different selection criterion is given for R

Fmax

in case burst mode operation at no load is used (see

Section 6.2: Operation at no load or very light load

14/32 DocID028175 Rev 4

L6599AF Application information

Figure 6. Oscillator waveforms and their relationship with gate-driving signals

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Figure 6

the timing relationship between the oscillator waveform and the gate-drive signal, as well as the swinging node of the half bridge leg (HB), is shown. Note that the lowside gate drive is turned on while the oscillator triangle is ramping up and the high-side gate drive is turned on while the triangle is ramping down. In this way, at startup, or as the IC resumes switching during burst mode operation, the low-side MOSFET is switched on first to charge the bootstrap capacitor. As a result, the bootstrap capacitor is always charged and ready to supply the high-side floating driver.

Operation at no load or very light load

When the resonant half bridge is lightly loaded or not loaded at all, its switching frequency is at its maximum value. To keep the output voltage under control in these conditions and to avoid losing soft-switching, there must be some significant residual current flowing through the transformer’s magnetizing inductance. This current, however, produces some associated losses that prevent converter no load consumption from achieving very low values.

To overcome this issue, the L6599AF enables the designer to make the converter operate intermittently (burst mode operation), with a series of a few switching cycles spaced out by long idle periods where both MOSFETs are in OFF-state, so that the average switching frequency can be substantially reduced. As a result, the average value of the residual magnetizing current and the associated losses are considerably cut down, therefore facilitating the converter to comply with energy saving recommendations.

The L6599AF can be operated in burst mode by using pin 5 (STBY): if the voltage applied to this pin falls below 1.24 V, the IC enters an idle state where both gate-drive outputs are low, the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V reference at the RF min

pin stays alive to minimize IC consumption and Vcc capacitor discharge. The IC resumes normal operation as the voltage on the pin exceeds 1.24 V by

50 mV.

To implement burst mode operation the voltage applied to the STBY pin needs to be related to the feedback loop.

Figure 7 (a) shows the simplest implementation, suitable with a narrow

input voltage range (e.g. when there is a PFC front-end).

DocID028175 Rev 4 15/32

Application information L6599AF

Figure 7. Burst mode implementation: a) narrow input voltage range; b) wide input voltage range

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Essentially, RF max

defines the switching frequency f max burst mode operation. Once f max

is fixed, RF max above which the L6599AF enters

is found from the relationship:

Equation 3

RF max



RF min f max  f min

Note that, unlike the f max

considered in the previous section ( Section 6.1: Oscillator ), here

f max

is associated to some load Pout

greater than the minimum one. Pout transformer peak currents are low enough not to cause audible noise.

is such that the

Resonant converter switching frequency, however, depends also on the input voltage;

therefore, in the case of quite a large input voltage range with the circuit of Figure 7

a, the value of Pout

would change considerably. In this case it is recommended to use the

arrangement shown in Figure 7

b, where the information on the converter input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction R

/ (R

+ R

) needed to minimize the change of Pout

B sure to choose the total value R

+ R

much greater than R

LINE pin voltage (see Section 6.6: Line sensing function on page 23

. Make to minimize the effect on the

Whichever circuit is in use, its operation can be described as follows. As the load falls below the value Pout

the frequency tries to exceed the maximum programmed value f max voltage on the STBY pin (V

STBY and the

) goes below 1.24 V. The IC then stops with both gate-drive outputs low, so that both MOSFETs of the half bridge leg are in OFF-state. The voltage

STBY

now increases as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.29 V, the IC restarts switching. After a while, V

STBY

goes down again in response to the energy burst and stops the IC. In this way, the converter works in a burst mode fashion with a nearly constant switching frequency. A further load decrease then causes a frequency reduction, which can go down even to few hundred hertz. The timing diagram of

Figure 8 illustrates this kind of operation, showing the most significant signals.

A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, helps obtain clean operation.

To help the designer meet energy saving requirements even in power-factor-corrected systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599AF allows that the PFC pre-regulator can be turned off during burst mode operation, therefore

DocID028175 Rev 4

L6599AF Application information eliminating the no load consumption of this stage (0.51 W). There is no compliance issue in that, because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load.

To do so, the L6599AF provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst mode operation. This signal is externally used for switching off the PFC controller and the pre-regulator, as shown in

Figure 9 . When the L6599AF is in UVLO, the pin is kept open to let the PFC controller start

first.

Figure 8. Load-dependent operating modes: timing diagram

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Figure 9. How the L6599AF can switch off a PFC controller at light load

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17/32

Application information L6599AF

6.3 Soft-start

Generally speaking, the purpose of soft-start is to progressively increase converter power capability when it is started up, so as to avoid excessive inrush current. In resonant converters the deliverable power depends inversely on frequency, soft-start is then done by sweeping the operating frequency from an initial high value until the control loop takes over.

With the L6599AF converter, soft-startup is simply realized with the addition of an R-C series circuit from pin 4 (RF min

) to ground (see Figure 10 , left).

Initially, the capacitor C

SS in parallel to RF min is totally discharged, so that the series resistor R

and the resulting initial frequency is determined by R

is effectively

and RF min

only, since the optocoupler phototransistor is cut off (as long as the output voltage is not too far away from the regulated value):

Equation 4 f start



3  CF





RF min

// R



The C

capacitor is progressively charged until its voltage reaches the reference voltage

(2 V) and, consequently, the current through R

goes to zero. This conventionally is imposed 5 times by selecting the constants R

·C

. Before reaching 2 V on C ss

, the output voltage should be already close to the regulated value and the feedback loop already taken over, so that it is the optocoupler phototransistor to determine the operating frequency from that moment onwards.

During this frequency sweep phase the operating frequency decays following the exponential charge of C

, that is, initially it changes relatively quickly but the rate of change gets slower and slower. This counteracts the non-linear frequency dependence of the tank circuit that makes the converter power capability change little as frequency is away from resonance and change very quickly as frequency approaches resonance frequency (see

Figure 10

, right).

Figure 10. Soft-start circuit (left) and power vs. frequency curve in a resonant half bridge (right)

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As a result, the average input current smoothly increases, without the peaking that occurs with linear frequency sweep, and the output voltage reaches the regulated value with almost no overshoot.

18/32 DocID028175 Rev 4

L6599AF Application information

Typically, R

and C

are selected based on the following relationships:

Equation 5



RF min f start  f min

; C



3  10

 3

SS where f start

is recommended to be at least 4 times f min

. The proposed criterion for C

is quite empirical and is a compromise between an effective soft-start action and an effective

OCP (see next section). Please refer to the timing diagram of

Figure 10

to see some significant signals during the soft-start phase.

6.4 Current sense, OCP and OLP

The resonant half bridge is essentially voltage-mode controlled; therefore a current sense input only serves as an overcurrent protection (OCP).

Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the primary switch (or switches), in a resonant half bridge the duty cycle is fixed and energy flow is controlled by its switching frequency. This impacts on the way current limitation can be realized. While in PWM-controlled converters energy flow can be limited simply by terminating switch conduction beforehand when the sensed current exceeds a preset threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half bridge the switching frequency, that is, its oscillator frequency must be increased and this cannot be done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the frequency change. This implies that, to have an effective increase able to change the energy flow significantly, the rate of change of the frequency must be slower than the frequency itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that, therefore, the information on the primary current fed to the current sensing input must be somehow averaged. Of course, the averaging time must not be too long to prevent the primary current from reaching too high values.

Figure 11 a couple of current sensing methods are illustrated and are described in the following. The circuit of Figure 11 a is simpler but the dissipation on the sense resistor Rs

might not be negligible, damaging efficiency; the circuit of

Figure 11 b is more complex but

virtually lossless and recommended when the efficiency target is very high.

DocID028175 Rev 4 19/32

Application information L6599AF

Figure 11. Current sensing techniques: a) with sense resistor, b) “lossless”, with capacitive shunt

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The L6599AF is equipped with a current sensing input (pin 6, ISEN) and a sophisticated overcurrent management system. The ISEN pin is internally connected to the input of a first comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If

the voltage externally applied to the pin by either circuit in Figure 11 exceeds 0.8 V, the first

comparator is tripped and this causes an internal switch to be turned on and discharge the soft-start capacitor C

(see Section 6.3: Soft-start ). This quickly increases the oscillator

frequency and thereby limits energy transfer. The discharge goes on until the voltage on the

ISEN pin has dropped by 50 mV; this, with an averaging time in the range of 10/f min

, ensures an effective frequency rise. Under output short-circuit, this operation results in a nearly constant peak primary current.

It is normal that the voltage on the ISEN pin may overshoot above 0.8 V; however, if the voltage on the ISEN pin reaches 1.5 V, the second comparator is triggered, the L6599AF shuts down and latches off with both the gate drive outputs and the PFC_STOP pin low, therefore turning off the entire unit. The supply voltage of the IC must be pulled below the

UVLO threshold and then again above the startup level in order to restart. Such an event may occur if the soft-start capacitor C

is too large, so that its discharge is not fast enough or in the case of transformer magnetizing inductance saturation or a shorted secondary rectifier.

In the circuit shown in Figure 11

a, where a sense resistor Rs in series to the source of the low-side MOSFET is used, note the particular connection of the resonant capacitor. In this way the voltage across Rs is related to the current flowing through the high-side MOSFET and is positive most of the switching period, except for the time needed for the resonant current to reverse after the low-side MOSFET has been switched off. Assuming that the time constant of the RC filter is at least ten times the minimum switching frequency f approximate value of Rs can be found using the empirical equation: min

, the

Equation 6

Rs 

Vs pkx

Crpkx



5  0 .

Crpkx



Crpkx where I

Crpkx

is the maximum desired peak current flowing through the resonant capacitor and the primary winding of the transformer, which is related to the maximum load and the minimum input voltage.

DocID028175 Rev 4

L6599AF Application information

The circuit shown in Figure 11 b can be operated in two different ways. If the resistor R

A series to C

is small (not above some hundred  , just to limit current spiking), the circuit

in operates like a capacitive current divider; C

A is a low-loss type, the sense resistor R

is typically selected equal to Cr/100 or less and

is selected as:

Equation 7



0 .

8  



1 

Crpkx

C r



 and C

is such that R

·C

is in the range of 10 /f min

If the resistor R

in series to C

is not small (in this case it is typically selected in the ten k  ), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr, which, in turn, is related to its current through the reactance of Cr. Again, C

is typically selected equal to Cr/100 or less, not necessarily a low-loss type this time, while R

(provided it is << R

) according to:

Equation 8



0 .

8 

Crpkx



I where the reactance of C

Crpk

= I

Crpkx

. Again, C

) and Cr (X

) should be calculated at the frequency where

is such that R

·C

is in the range of 10 /f min

Whichever circuit is used, the calculated values of Rs or R

should be considered just a first cut value that needs to be adjusted after experimental verification.

OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an output short-circuit, but the output current through the secondary winding and rectifiers under these conditions might be so high as to endanger converter safety if continuously flowing. To prevent any damage during these conditions, it is customary to force the converter’s intermittent operation, in order to bring the average output current to values such that the thermal stress for the transformer and the rectifiers can be easily handled.

With the L6599AF the designer can externally program the maximum time T

that the converter is allowed to run overloaded or under short-circuit conditions. Overloads or shortcircuits lasting less than T

do not cause any other action, therefore providing the system with immunity to short duration phenomena. If, instead, T

is exceeded, an overload protection (OLP) procedure is activated that shuts down the L6599AF and, in the case of continuous overload/short-circuit, results in continuous intermittent operation with a userdefined duty cycle.

DocID028175 Rev 4 21/32

Application information L6599AF

Figure 12. Soft-start and delayed shutdown upon overcurrent timing diagram

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This function is realized with pin 2 (DELAY), by means of a capacitor C

Delay resistor R

Delay

and a parallel

connected to ground. As the voltage on the ISEN pin exceeds 0.8 V the first

OCP comparator, in addition to discharging C

, turns on an internal current generator that sources 150 µA from the DELAY pin and charges C

Delay

. During an overload/short-circuit, the OCP comparator and the internal current source is repeatedly activated and C

Delay

is charged with an average current that depends essentially on the time constant of the current sense filtering circuit on C

SS due to R

Delay much longer.

and the characteristics of the resonant circuit; the discharge

can be neglected, considering that the associated time constant is typically

This operation continues until the voltage on C

Delay

reaches 2 V, which defines the time

. There is no simple relationship that links T determine C

Delay order of 100 ms.

to C

Delay

, therefore it is more practical to

experimentally. As a rough indication, with C

Delay

= 1 µF, T

is in the

Once C

Delay

is charged at 2 V the internal switch that discharges C

is forced low continuously regardless of the OCP comparator output, and the 150 µA current source is continuously on, until the voltage on C

Delay

reaches 3.5 V. This phase lasts:

Equation 9

 10  C

Delay with T

expressed in ms and C

Delay a frequency close to f start

(see

in µF. During this time the L6599AF runs at

Section 6.3: Soft-start

resonant circuit. As the voltage on C

Delay

) to minimize the energy inside the

is 3.5 V, the L6599AF stops switching and the

PFC_STOP pin is pulled low. Also the internal generator is turned off, so that C

Delay slowly discharged by R which takes:

Delay

. The IC restarts when the voltage on C

Delay

is now

is less than 0.3 V,

Equation 10

STOP

 R

Delay

Delay ln 3

 2 .

5 R

Delay

22/32 DocID028175 Rev 4

L6599AF Application information

The timing diagram of Figure 12

voltage of the L6599AF (V

shows this operation. Note that, if, during T

) falls below the UVLO threshold, the IC records the event and does not restart immediately after V

STOP

, the supply

exceeds the startup threshold if V(DELAY) is still higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater than

0.3 V. Note also that, in the case of an overload lasting less than T

SH the next overload is lower if they are close to one another.

, the value of T

for

6.6

The L6599AF is equipped with a comparator having the non-inverting input externally available at pin 8 (DIS) and with the inverting input internally referenced to 1.85 V. As the voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its consumption reduced to a low value. The information is latched and it is necessary to let the voltage on the V

pin go below the UVLO threshold to reset the latch and restart the IC.

This function is useful to implement a latched overtemperature protection very easily by biasing the pin with a divider from an external reference voltage (e.g. pin 4, RF min

), where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or the secondary diode or transformer.

An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an overvoltage condition via an optocoupler.

Line sensing function

This function basically stops the IC as the input voltage to the converter falls below the specified range and lets it restart as the voltage goes back within the range. The sensed voltage can be either the rectified and filtered mains voltage, in which case the function acts as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output voltage of the PFC stage, in which case the function serves as a power-on and power-off sequencing.

L6599AF shutdown upon input undervoltage is accomplished by means of an internal

comparator, as shown in the block diagram of Figure 13 , whose non-inverting input is

available at pin 7 (LINE). The comparator is internally referenced to 1.24 V and disables the

IC if the voltage applied at the LINE pin is below the internal reference. Under these conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the reference. The comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 13 µA current sink is ON as long as the voltage applied at the

LINE pin is below the reference and is OFF if the voltage is above the reference.

This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see below). With voltage hysteresis, instead, fixing one threshold automatically fixes the other, depending on the built-in hysteresis of the comparator.

DocID028175 Rev 4 23/32

Application information

Figure 13. Line sensing function: internal block diagram and timing diagram

L6599AF

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With reference to Figure 11

, the following relationships can be established for the ON

(Vin

) and OFF (Vin

OFF

) thresholds of the input voltage:

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Equation 11

Vin



1 .

 13  10  6 

1 .

L which, solved for R

and R

, yields:

Vin

OFF

 1 .



1 .

Equation 12



Vin

13 

 Vin

 6

OFF ; R

 R

Vin

1 .

OFF

 1 .

While the line undervoltage is active, the startup generator keeps on working but there is no

PWM activity, therefore the V

voltage (if not supplied by another source) continuously oscillates between the startup and the UVLO thresholds, as shown in the timing diagram of

Figure 13

As an additional safety measure (e.g. in case the low-side resistor is open or missing, or in non-power factor corrected systems in case of abnormally high input voltage), if the voltage on the pin exceeds 7 V, the L6599AF is shut down. If its supply voltage is always above the

UVLO threshold, the IC restarts as the voltage falls below 7 V.

The LINE pin, while the device is operating, is a high impedance input connected to high value resistors, therefore it is prone to pick-up noise, which might alter the OFF threshold or give origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this

24/32 DocID028175 Rev 4

L6599AF Application information kind. If the function is not used, the pin must be connected to a voltage greater than 1.24 V but lower than 6 V (worst-case value of the 7 V threshold).

The supply of the floating high-side section is obtained by means of a bootstrap circuitry.

This solution normally requires a high voltage fast recovery diode (D

BOOT charge the bootstrap capacitor C

BOOT

Figure 14

a) to

. In the L6599AF a patented integrated structure, replaces this external diode. It is realized by means of a high voltage DMOS, working in the third quadrant and driven synchronously with the low-side driver (LVG), with a diode in

series to the source, as shown in Figure 14 b.

Figure 14. Bootstrap supply: a) standard circuit; b) internal bootstrap synchronous diode

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The diode prevents any current being able to flow from the VBOOT pin back to V

CC the supply is quickly turned off when the internal capacitor of the pump is not fully

, in case discharged. To drive the synchronous DMOS a voltage higher than the supply voltage V

is necessary. This voltage is obtained by means of an internal charge pump ( Figure 14 b).

The bootstrap structure introduces a voltage drop while recharging CBOOT (i.e. when the low-side driver is on), which increases with the operating frequency and with the size of the external power MOSFET. It is the sum of the drop across the R

(DS)ON

and the forward drop across the series diode. At low frequency this drop is very small and can be neglected but, as the operating frequency increases, it must be taken into account. In fact, the drop reduces the amplitude of the driving signal and can significantly increase the R

(DS)ON external high-side MOSFET and then its conductive loss.

of the

DocID028175 Rev 4 25/32

Application information L6599AF

This concern applies to converters designed with a high resonance frequency (indicatively,

> 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter runs at high frequency at light load, where the current flowing in the MOSFETs of the half bridge leg is low, so that, generally, an R

(DS)ON

rise is not an issue. However, it is wise to check this point anyway and the following equation is useful to compute the drop on the bootstrap driver:

Equation 13

Drop

 I ch arg e

( DS ) on

 V



Q g

T ch arg e

( DS ) on

 V

F where Q g

is the gate charge of the external power MOSFET, R

(DS)ON the bootstrap DMOS (150 W, typ.) and T charge

is the on-resistance of

is the ON-time of the bootstrap driver, which equals about half the switching period minus the deadtime T

. For example, using a MOSFET with a total gate charge of 30 nC, the drop on the bootstrap driver is about 3 V at a switching frequency of 200 kHz:

Equation 14

Drop



2 .

 10

 6

 10

 9

 0 .

27  10

 6

150  0 .

6  2 .

7 V

If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be used, therefore saving the drop on the R

(DS)ON

of the internal DMOS.

26/32 DocID028175 Rev 4

L6599AF Application information

Figure 15. Application example: 90 W AC/DC adapter using L6563H, L6599AF and SRK2000A

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DocID028175 Rev 4 27/32

Package information L6599AF

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com

ECOPACK is an ST trademark.

28/32 DocID028175 Rev 4

L6599AF

7.1 SO16N package information

Figure 16. SO16N package outline

Package information

Symbol

E1 e h

L k ccc

E b c

Table 6. SO16N package mechanical data

Dimensions (mm)

Min.

3.80

0.25

0.40

0.10

1.25

0.31

0.17

9.80

5.80

Typ.

3.90

1.27

9.90

6.00

DocID028175 Rev 4

Max.

4.00

0.50

1.27

8°

0.10

1.75

0.25

0.51

0.25

10.00

6.20

29/32

Package information

Figure 17. SO16N recommended footprint (dimensions are in mm)

L6599AF

30/32 DocID028175 Rev 4

L6599AF Revision history

Date

29-Jul-2015

26-Aug-2015

27-Aug-2015

06-Jun-2017

Revision

Table 7. Document revision history

Changes

Initial release.

Document status promoted from Target specification to Production data.

Updated document title and product features.

Updated

Figure 15 on page 27

(updated title - replaced SRK2000 by

SRK2000A, replaced figure by new figure).

Minor modifications throughout document.

DocID028175 Rev 4 31/32

L6599AF

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

32/32 DocID028175 Rev 4

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