STMicroelectronics L6910 Datasheet

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L6910

L6910A

ADJUSTABLE STEP DOWN CONTROLLER

WITH SYNCHRONOUS RECTIFICATION

■

1 FEATURES

■ OPERATING SUPPLY VOLTAGE FROM 5V

TO 12V BUSES

UP TO 1.3A GATE CURRENT CAPABILITY

ADJUSTABLE OUTPUT VOLTAGE

N-INVERTING E/A INPUT AVAILABLE

0.9V ±1.5% VOLTAGE REFERENCE

VOLTAGE MODE PWM CONTROL

VERY FAST LOAD TRANSIENT RESPONSE

0% TO 100% DUTY CYCLE

POWER GOOD OUTPUT

OVERVOLTAGE PROTECTION

HICCUP OVERCURRENT PROTECTION

200kHz INTERNAL OSCILLATOR

OSCILLATOR EXTERNALLY ADJUSTABLE

FROM 50kHz TO 1MHz

SOFT START AND INHIBIT

PACKAGES: SO-16 & HTSSOP16

■

2 APPLICATIONS

■ SUPPLY FOR MEMORIES AND TERMI-

NATIONS

COMPUTER ADD-ON CARDS

LOW VOLTAGE DISTRIBUTED DC-DC

MAG-AMP REPLACEMENT

3 DESCRIPTION

The device is a pwm controller for high performance

Figure 2. Block Diagram

Figure 1. Packages

SO-16 (Narrow) HTSSOP16 (Exposed Pad)

Table 1. Order Codes

Part Number

L6910

L6910TR

L6910A

L6910ATR

Package

SO-16

SO-16 in Tape & Reel

HTSSOP16

HTSSOP16 in Tape & Reel dc-dc conversion from 3.3V, 5V and 12V buses.

The output voltage is adjustable down to 0.9V; higher voltages can be obtained with an external voltage divider.

High peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20A.

The device assures protections against load overcurrent and overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in HICCUP mode.

V in

5V to 12V

PGOOD

VREF

VCC OCSET

MONITOR

PROTECTION

& REF

OSC

EAREF

OSC

E/A

PWM

BOOT

UGATE

BOOT

LGATE

PGND

GND

VFB

COMP

D03IN1509

May 2005

Rev. 9

1/29

L6910 - L6910A

Table 2. Absolute Maximum Ratings

Symbol

Vcc

BOOT

PHASE

HGATE

PHASE

Vcc to GND, PGND

Boot Voltage

Parameter

T j

T stg

P tot

OCSET, LGATE, PHASE

SS, FB, PGOOD, VREF, EAREF, RT

COMP

Junction Temperature Range

Storage temperature range

Maximum power dissipation at Tamb = 25

Table 3. Thermal Data

Symbol Parameter

R th j-amb

Thermal Resistance Junction to Ambient

(*) Device soldered on 1 S2P PC board

Figure 3. Pins Connection (Top view)

Value

-0.3 to Vcc+0.3

6.5

-40 to 150

SO-16

120

HTSSOP16 HTSSOP16 (*) Unit

110 50

C/W

Unit

VREF

OSC

OCSET

SS/INH

COMP

GND

EAREF

D03IN1510

N.C.

VCC

LGATE

PGND

BOOT

HGATE

PHASE

PGOOD

VREF

OSC

OCSET

SS/INH

N.C.

COMP

GND

D03IN1511

VCC

LGATE

PGND

BOOT

HGATE

PHASE

PGOOD

EAREF

2/29

L6910 - L6910A

Table 4. Pins Function

SO HTSSOP Name

VREF

Description

Internal 0.9V ±1.5% reference is available for external regulators or for the internal error amplifier (connecting this pin to EAREF) if external reference is not available.

A minimum 1nF capacitor is required.

If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.

OSC Oscillator switching frequency pin. Connecting an external resistor (R

) from this pin to

GND, the external frequency is increased according to the equation: f

OSC,RT

= 200K Hz +

4.94 10

Ω

-------------------------

( )

Connecting a resistor (R

) from this pin to Vcc (12V), the switching frequency is reduced according to the equation: f

OSC,RT

= 200K Hz –

-----------------------------

(

⋅

Ω )

If the pin is not connected, the switching frequency is 200KHz.

The voltage at this pin is fixed at 1.23V. Forcing a 50

A current into this pin, the built in oscillator stops to switch.

In Over Voltage condition this pin goes over 3V until that conditon is removed.

OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.

The internal 200

A current generator sinks a constant current through the external resistor. The Over-Current threshold is due to the following equation:

----------------------------------------------

⋅

DSon

4 4

SS/INH The soft start time is programmed connecting an external capacitor from this pin and

GND. The internal current generator forces through the capacitor 10

This pin can be used to disable the device forcing a voltage lower than 0.4V

COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop.

FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop.

Connected to the output resistor divider, if used, or directly to Vout, it manages also overvoltage conditions and the PGOOD signal

GND All the internal references are referred to this pin. Connect it to the PCB signal ground.

EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to

3V) for the PWM regulation or short it to VREF pin to use the internal reference.

If this pin goes under 650mV (typ), the device shuts down.

PGOOD This pin is an open collector output and it is pulled low if the output voltage is not within the above specified thresholds. If not used it may be left floating.

PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit together with OCSET.

HGATE High side gate driver output.

BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc

(cathode vs. boot).

PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device

LGATE This pin is the lower mosfet gate driver output

VCC Device supply voltage. The operative supply voltage ranges is from 5V to 12V.

DO NOT CONNECT V

TO A VOLTAGE GREATER THAN V

N.C.

This pin is not internally bonded. It may be left floating or connected to GND.

3/29

L6910 - L6910A

Table 5. Electrical Characteristics (V cc

= 12V, T

=25°C unless otherwise specified)

Symbol Parameter

V cc

SUPPLY CURRENT

Icc Vcc Supply current

POWER-ON

Turn-On Vcc threshold

Test Condition

OSC = open; SS to GND

Turn-Off Vcc threshold

Rising V

OCSET

threshold

Turn On EAREF threshold

SOFT START AND INHIBIT

Iss Soft start Current

S.S. current in INH condition

OSCILLATOR f

OSC

Initial Accuracy

VOCSET = 4V

SS = 2V

SS = 0 to 0.4V

OSC,RT

Total Accuracy

∆

Vosc Ramp amplitude

REFERENCE

OUT

REF

Output Voltage Accuracy

Reference Voltage

REF

Reference Voltage

ERROR AMPLIFIER

EAREF

N.I. bias current

EAREF Input Resistance

I.I. bias current I

COMP

Common Mode Voltage

Output Voltage

Open Loop Voltage Gain

GBWP Gain-Bandwidth Product

SR Slew-Rate

GATE DRIVERS

HGATE

High Side

Source Current

OSC = OPEN

OSC = OPEN; T j

= 0

to 125

16 K

Ω

< R

to GND < 200 K

Ω

OUT

REF

= V

= 1nF; I

EAREF

Vs. GND

; V

= 3V

= 0V to 3V

COMP = 10pF

EAREF

REF

= V

REF

= 0 to 100

REF

= 1nF; T

= 0 to 125

BOOT

- V

PHASE

= 12V

HGATE

- V

PHASE

= 6V

BOOT

- V

PHASE

= 12V R

HGATE

PGOOD

High Side

Sink Resistance

LGATE

Low Side Source Current

LGATE

Low Side Sink Resistance

Output Driver Dead Time

PROTECTIONS

OCSET

OCSET Current Source

Vcc = 12V; V

Vcc = 12V

LGATE

= 6V

PHASE connected to GND

OCSET

= 4V

Over Voltage Trip (V

/ V

EAREF

) V

Rising

OSC

OSC Sourcing Current

POWER GOOD

> OVP Trip

Upper Threshold (V

/ V

EAREF

) V

Rising

Lower Threshold (V

/ V

EAREF

) V

Falling

Hysteresis (V

/ V

EAREF

PGOOD Voltage Low

Output Leakage Current

)

Upper and Lower threshold

PGOOD

= -4mA

PGOOD

= 6V

Min

4.0

3.8

180

170

-15

0.8

0.5

4.3

4.1

1.24

650

300

0.01

0.4

0.2

4.6

4.4

1.4

750

220

230

0.886

0.900

0.913

0.886

0.900

0.913

-2 +2

0.9

170

108

Typ

200

1.9

1.3

1.1

1.5

200

117

110

Max

0.5

210

230

120

112

Unit mA

KHz kHz

A k

Ω

V dB

MHz

µ s

Ω

Ω ns

% mA

V mV

4/29

L6910 - L6910A

4 DEVICE DESCRIPTION

The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N

Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is used (simply connecting together EAREF and VREF pins). The device allows also using an external reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V/

µ s slew rate that permits to realize high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to

100%. The device protects against over-current conditions entering in HICCUP mode. The device monitors the current by using the r

DS(ON)

of the upper MOSFET(s) that eliminates the need for a current sensing resistor. The device is available in SO16 narrow package.

4.1 Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is typically 50 µ A (F sw

= 200KHz) and may be varied using an external resistor (R

) connected between

OSC pin and GND or V

. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sunk (forced) from (into) the pin.

In particular connecting R

vs. GND the frequency is increased (current is sunk from the pin), according to the following relationship:

6 f

OS C,RT

= 200KHz + -------------------------

(

Ω )

Connecting R

to V

= 12V or to V

= 5V the frequency is reduced (current is forced into the pin), according to the following relationships:

7 f

OS C,RT

= 200KHz – -----------------------------

( K Ω )

= 12V f

OS C,RT

= 200KHz –

---------------------

( K Ω )

= 5V

Switching frequency variation vs. RT are repeated in Fig. 4.

Note that forcing a 50

A current into this pin, the device stops switching because no current is delivered to the oscillator.

Figure 4.

10000

1000

100

RT to GND

RT to VCC=12V

RT to VCC=5V

100

Frequency [kHz]

1000

5/29

L6910 - L6910A

4.2 Reference

A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid instability in the internal linear regulator. It is able to deliver up to 100

A and may be used as reference for the device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed.

Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this pin can range from 0.9V to 3V. It has an internal pull-down (300k

Ω

resistor) that forces the device shutdown if no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is lower than 650mV (typ).

4.3 Soft Start

At start-up a ramp is generated charging the external capacitor C

with an internal current generator. The initial value for this current is of 35

A and speeds-up the charge of the capacitor up to 0.5V. After that it becames

10 µ A until the final charge value of approximatively 4V.

When the voltage across the soft start capacitor (V

) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As V

reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper

MOS begins to switch and the output voltage starts to increase.

No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.

If VCC and OCSET pins are not above their own turn-on thresholds and V

EAREF

is not above 650mV, the Soft-

Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any undervoltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged.

Figure 5. Soft Start (with Reference Present)

Vcc Turn-on threshold

Vcc

Vin

Vin Turn-on threshold

Vss to GND

0.5V

LGATE

Vout

Timing Diagram

Acquisition: CH1 = PHASE; CH2 = V out

;

CH3 = PGOOD; CH4 = V ss

4.4 Driver Section

The driver capability on the high and low side drivers allows using different types of power MOS (also multiple

MOS to reduce the R

DSON

), maintaining fast switching transition.

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.

Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is

6/29

L6910 - L6910A avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the high side turn-off.

The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ V

= 12V and 500mA @ V

= 5V, and the sink peak current is 1.3A @ V

= 12V and 500mA @ V

= 5V.

Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-

Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.

Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)

CH1 = High Side Gate CH4 = Gate Current

Figure 7. Low Side Driver Peak Current. V

= 12V (right) V

= 5V (left)

CH1 = Low Side Gate CH4 = Gate Current

4.5 Monitoring and Protections

The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the powergood output is forced low.

The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.) greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the over-voltage is detected.

7/29

L6910 - L6910A

Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the

DSON

, with the voltage across the external resistor (R

OCS

) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (I

) can be calculated with the following relationship:

OCS

⋅

---------------------------------

R dsON

Where the typical value of I

OCS

is 200

A. To calculate the R

OCS

value it must be considered the maximum

R dsON

(also the variation with temperature) and the minimum value of I

OCS

. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied:

≥ I

OUTMAX

∆

= I

PEA K

Where ∆ I is the inductance ripple current and I

OUTMAX

is the maximum output current.

In case of over current detectionthe soft start capacitor is discharged with constant current (10

A typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode, as shown in figure 8. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on.

Figure 8. Hiccup Mode Figure 9. Inductor Ripple Current vs. Vout

CH1 = SS; CH4 = Inductor current

0 .5

L=1.5

H, Vin=12V

L=2

Vin=12V

L=3

H, Vin=5V

L=3

Vin=12V

L=1.5

Vin=5V

L=2

Vin=5V

1.5

2 .5

O utput V oltage [V ]

3 .5

4.6 Inductor Design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ∆ I

between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship:

L =

V f

– sw

⋅

∆

⋅

---------------

Where f

is the switching frequency, V

is the input voltage and V

OUT

is the output voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with V

= 5V and V

= 12V.

Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required.

8/29

L6910 - L6910A

The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for ∆ I load transient in case of enough fast compensation network response: t application

L ∆ I

– V

OUT t removal

∆ I

OUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.

4.7 Output Capacitor

The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):

∆ V

OUT

= ∆ I

OUT

⋅ ESR

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation:

∆ V

OUT

∆ I

⋅ ( V

INMIN

⋅ L

⋅ D

MAX

– V

OUT

)

Where D

MAX

is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple.

4.8 Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is:

I rms

= I

OUT

D ⋅ ( 1 – D )

Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:

P = ESR I

2 rms

4.9 Compensation Network Design

The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage level (EAREF). The error amplifier output V

COMP

is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of V

at the PHASE node. This wave is filtered by the output filter. The modulator transfer function is the small-signal transfer function of V

OUT

COMP

. This function has a double pole at frequency F

depending on the L-C out

resonance and a zero at F

ESR

depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage V

IN oscillator voltage ∆ V

OSC

divided by the peak-to-peak

9/29

L6910 - L6910A

Figure 10. Compensation Network

∆ V

OSC

OUT

PWM

COMPARATOR

ESR

OUT

C18

C19

C20

EAREF

COMP

D03IN1512

The compensation network consists in the internal error amplifier and the impedance networks Z

(R3, R4 and

C20) and Z

(R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation.

A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst-case component variations when determining phase margin.

To locate poles and zeroes of the compensation networks, the following suggestions may be used:

Modulator singularity frequencies:

E SR

OUT

Compensation network singularity frequency:

P 1

R5 ⋅

⎛

⎝

-----------------------------

C18 + C19

⎞

⎠

( R3 + R4 ) ⋅ C20

– Put the gain R5/R3 in order to obtain the desired converter bandwidth;

– Place ω

before the output filter resonance ω

;

– Place ω

at the output filter resonance ω

;

– Place

at the output capacitor ESR zero

ESR

;

– Place

at one half of the switching frequency;

– Check the loop gain considering the error amplifier open loop gain.

10/29

L6910 - L6910A

Figure 11. Asymptotic Bode Plot of Converter's Gain dB Error Amplifier

R5/R3

Modulator Gain

Ζ1

Ζ2

Compensation Network Gain

ESR

Error Amplifier Closed Loop Gain

5 15A DEMO BOARD DESCRIPTION

The demo board shows the operation of the device in a general purpose application. This evaluation board allows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also be disabled with the switch S1. The V

input rail supplies the device while the power conversion starts from the V

input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has to be closed and a 5V to 12V input can be directly connected to the V

input. The four layers demo board's copper thickness is of 70 µ m in order to minimize conduction losses considering the high current that the circuit is able to deliver.The PGOOD signal is used as a logic level and it's been pulled up to V

because there's no other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin

Maximum Absolute Rating) a 5V reference is required.

Figure 12 shows the demo board's schematic circuit

Figure 12. 15A Demo Board Schematic

VIN

GNDIN

R7 C14

C13

VCC

GNDCC

REFIN

GNDREFIN

+VREF

GNDREF

C17

C16

BOOT

C15

GND

EAREF

OCSET

VREF

C12

C21

OSC

COMP

C19

VFB

C18

R10

R11

SR12

SR13

D03IN1513

Q1-3

UGATE

PHASE

LGATE

PGND

PGOOD

Q4-6

C20

C1-C3

C22

C4-

OUT

0.9

1.2

1.5

1.8

2.5

3.3

5.0

S2 S3 S4 S5

Open Open Open Open

ON Open Open Open

Open ON Open Open

ON ON Open Open

Open Open ON Open

Open Open Open ON

Open Open ON ON

OUT

GNDOUT

PWRGD

11/29

L6910 - L6910A

Table 6. Part List

Reference

R10

R11

R12

R13

C1, C3

C9, C10

C12, C13,

C15, C21

C14

C16

C17

C18

C19

C20

C22

Q2,Q3,Q4,Q6

SWITCH

Table 7. Other Inductor Manufacturer

Manufacturer Series

WÜRTH ELEKTRONIK

PANASONIC

SUMIDA

744318

ETQP6F1R8FA

CDEP134-2R7MC-H

Description

N.C

10K 5% 125mW

4.7K 5% 125mW

1KOhm 5% 125mW

2.7K 5% 125mW

10Ohm 5% 125mW

510Ohm 5% 125mW

N.C

0 Ohm

14K 5% 125mW

6.98K 5% 125mW

2.61K 5% 125mW

1.74K 5 5% 125mW

100

F - 20V

330

F - 6.3V

100nF

1nF

100nF

4.7

F - 16V

1.5nF

15nF

47nF

N.C

Short

H (T50-52B Core, 7T AWG15)

STS11NF30L

1N4148

STPS2L25U

Device L6910

Short

DIP SWITCH 6 POS.

Manufacturer

NEOHM

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

AUX

KEMET

MICROMETALS

Inductor Value (

1.8 to 2.7

1.8

2.7

SMD 0805

RADIAL 10X10.5

SMD7343

SMD0805

SMA6032

SMD0805

SO8

SOT23

SMB

SO16Narrow

Saturation Current (A)

16 to 20

12/29

L6910 - L6910A

Figure 13. PCB and Components Layouts

Component Side

Figure 14. PCB and Components Layouts

Internal Signal GND Layer

Internal Power GND Layer

Figure 15. Efficiency vs Output Current

Solder Side

Output Current (A)

13/29

L6910 - L6910A

Figure 16. Efficiency vs Output Current

100

1 3 5 7 9

Output Current (A)

11 13 15 17

6 COMPONENTS SELECTION

6.1 Inductor Selection

To select the right inductor value, the application conditions must be fixed. For example we can consider:

Vin=12V Vout =3.3V Iout=15A

Considering a ripple of approximately 25% to 30% of Iout, the inductor value will be L=3 µ H.

An iron powder core (TO50-52B) with 7 windings has been chosen.

6.2 Output Capacitors

2 POSCAP capacitors, model 6TPB330M, have been chosen, with a maximum ERS equal to 40m

Ω

each.

Therefore, the resultant ESR is of 20m

Ω

. Considering a current ripple of 4A, the output voltage ripple is:

∆

Vout = 4 · 0.02 = 80mV

6.3 Input Capacitors

For I

OUT

= 15A and D = 0.5 (worst case for input current ripple), the RMS current of the input capacitor is equal to 7.5A.

Two OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m Ω , have been chosen to sustain the ripple. Therefore, the resultant ESR is equal to 13m

Ω

/2 = 6.5m

Ω

. The losses, in worst case, are:

P = ESR · I

2 rms = 366mW

6.4 Over-Current Protection

The current limit can be set to approximately 20A. Substituting the demo board parameters in the relationship reported in the relative section, (I

OSCMIN

=170 µ A; IP = 20A; R that R

OCS

= 510 Ω

DSONMAX

= 9m Ω / 2=4.5m

Ω) it results

14/29

L6910 - L6910A

6.5 APPLICATION SUGGESTIONS FOR HIGHER CURRENTS

For higher output currents, up to 20A, the following configuration can be used (with reference to the demo board schematic):

Q1,Q2,Q3: STS11NF30L

Q4,Q5,Q6: STS17NF3LL

L: 2.5

µ H Magnetic 77121A7 Core 7T 2x AWG16

In these conditions, the following performance have been achieved:

Table 8.

(V)

OUT

(V)

1.2

1.5

1.8

2.5

3.3

OUT

(A)

(%)

(V)

OUT

(V)

1.2

1.5

1.8

2.5

3.3

OUT

(A)

(%)

For currents higher than 20A, bigger mosfets should be selected (e.g. STS25NH3LL) both for the high side and low side (depending on the duty cycle and input voltage).

7 6A DEMO BOARD DESCRIPTION

A compact demo board has been realized to manage currents in the range of 5A-6A .

The external power mosfets are included in a single SO8 package to save space and increase power density.

Two separate rails are provided, for V

and V

. They can be connected together by shorting the jumper J1.

The PGOOD signal is used as a logic level and it's been pulled up to V

because there's no other appropriate voltage available on the demo board. In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is required.

Figure 17. 6A Demo Board Schematic

15/29

L6910 - L6910A

R8 R9

R10

R11

Capacitors

C1,C2

C3,C4

C5,C6,C9

C7,C8

C10

C18

C19

C20

Magnetics

Transistor

Diodes

Device

Table 9. Part List

Reference

Resistor

Description

2K7 Ohm 0805 5% 125mW

1K8 Ohm 0805 5% 125mW

1K Ohm 0805 5% 125mW

10K 5% 125mW

4K7 5% 125mW

2K7 5% 125mW

10 Ohm 5% 125mW

680 Ohm 5% 125mW

2.2 Ohm 5% 125mW

N.C

F 25V

100

F - 6.3V

100nF

1nF

N.C

1.5nF

15nF

47nF

7 µ H (T50-52B Core, 12T AWG 21)

STS8DNF3LL

1N4148

STPS2L25U

Device L6910

Manufacturer

NEOHM

TOKIN

POSCAP 6TPB100M

KEMET

MICROMETALS

Table 10. Other inductor manufacturer

Manufacturer

WÜRTH ELEKTRONIK

PANASONIC

SUMIDA

COILCRAFT

Series Inductor Value (

4.8 to 5.8

744 382

ETQP6F 4.6 to 6.4

6 to 8 CDEP134-H

DO3316P-472HC 4.7

DO3340P 10 to 22

COILTRONICS DR125-8R2 8.2

(Vout = 2.5V)

(Vout = 3.3V)

(Vout = 5V)

SMD 0805

C34Y5U1E106ZTE12

SMD7343

SMD0805

SOT23

SMB

SO16Narrow

Saturation Current (A)

7.5 to 8

9.3 to 7.9

7.2 to 9.6

5.4

8 to 5.5

7.8

16/29

L6910 - L6910A

Figure 18. PCB and Components Layouts

Component Side Solder Side

7.1 Compact Demo Board Performances

Figures 19, 20 show the measured efficiency versus load current for different values of output voltage. The measure has been done at 5V and 12V input. Output voltage has been changed modifying the value of R1 in the demo board as reported in the part list.

Figure 19. Efficiency vs. Output Current

Figure 20. Efficiency vs. Output Current

17/29

L6910 - L6910A

8 15A HTSSOP16 DEMO BOARD DESCRIPTION

A specific Demo Board has been realized for the HTSSOP16 package. The features are the same of the 15A

Demo Board previously described but thermal performance are improved. The PGOOD signal is used as a logic level and it's been pulled up to V

because there's no other appropriate voltage available on the demo board.

In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is required .

Figure 21. 15A HTSSOP16 Demo Board Schematic

VIN

GNDIN

VCC

GNDCC

Ref IN

C16

C17

BOOT OCSET

VCC

C15

GND

U1

L6910A

OSC

EAREF

6 7

C14

C13

UGATE

PHASE

LGATE

PGND

PGOOD

VREF

C21

GNDRef

C19

C18

R10

R11

R12

R13

R14

Q1-3

R15

Q4-6

R16

C23

C20

Vout

0.9

1.2

1.5

1.8

2.5

3.3

5.0

C22

S2 S3 S4 S5

Open Open Open Open

Open Open Open

Open

Open Open

Open

Open Open Open

Open Open

C1- C3

C4 -11

C12

VOUT

GNDOUT

PWRGD

+Vref

GNDref

Table 11. Part List

Reference

R10

R11

R12

R13

R14

R15

R16

C1,C3

C9,C10

Description

N.C

10K 5% 125mW

4.7K 5% 125mW

1K Ohm 5% 125mW

2.7K 5% 125mW

10 Ohm 5% 125mW

560 Ohm 5% 125mW

N.C

0 Ohm

14K 5% 125mW

6.98K 5% 125mW

2.61K 5% 125mW

1.74K 5% 125mW

0 Ohm

N.C

100uF 20V

330uF - 6.3V

Manufacturer

NEOHM

OSCON

20SA100M

POSCAP

6TPB330M

SMD 0805

RADIAL 10X10.5

SMD7343

18/29

L6910 - L6910A

Table 11. Part List

(continued)

Reference

C12,C13,

C15,C21,C16

C14

C17

C18

C19

C20

C22

C23

Q2,Q3,Q4,Q6

SWITCH

Description

100nF

1nF

4.7uF - 16V

1.5nF

15nF

47nF

N.C

Short

3uH T50-52B Core, 7T AWG15

STS11NF30L

1N4148

STPS340U

Device L6910

Short

DIP SWITCH

Table 12. Other inductor manufacturer

Manufacturer

WÜRTH ELEKTRONIK

PANASONIC

SUMIDA

Series

744318

ETQP6F1R8FA

CDEP134-2R7MC-H

Figure 22. PCB and Components Layout

Manufacturer

KEMET

AVX

KEMET

Inductor Value (

1.8 to 2.7

1.8

2.7

SMD0805

SMA6032

SMD0805

MICROMETALS

SO8

SOT23

SMB

HTSSOP16

Saturation Current (A)

16 to 20

Component Side Internal Power GND Layer

Internal Signal GND Layer

Solder Side

19/29

L6910 - L6910A

9 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY

Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact that the trace between the driving chipset and the memory input must be terminated with resistors.

Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable of sourcing and sinking current.

Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is

2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x

L6910. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage.

The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through a resistor divider connected to the 2.5V.

Figure 23. Application idea : DDR Memory Supply

The current required by the memory and the termination supply, depends on the memory type and size.

The figure 24, 25 shows the efficiency of the L6910 for the termination section of the application shown in fig.

23, in sink and source mode. The figures show the efficiency values also when the input voltage is coming directly from the 12V rail.

20/29

L6910 - L6910A

Figure 24. Efficiency vs Output Current Source

Mode

Figure 27. Efficiency vs Output Current Sink

Mode

Figure 25. Efficiency vs Output Current Sink

Mode

9 11 13 15 17

Figure 28. Efficiency vs Output Current Source

Mode

9 11 13 15 17

For very big systems (e.g. servers), the DDR memory termination can require much higher currents, in the range of 10A-15A and more.

Figures 26, 27 and 28, 29 show the efficiency of the

L6910 in sink and source mode, up to 17A both for DDRI and DDRII memories.The measurements have been realized with the 15A demo board. (See pag.11 )

Figure 26. Efficiency vs Output Current Sink

Mode

100

1 3 5 7 9 11 13 15 17

Figure 29. Efficiency vs Output Current Source

Mode

100

1 3 5 7 9 11 13 15 17

21/29

L6910 - L6910A

10 APPLICATION IDEA 2: POSITIVE BUCK-BOOST REGULATOR 3V TO 13.2V

INPUT / 5V 2.5A OUTPUT

In some applications the input voltage changes in a very wide range while the output must be regulated to a fixed value. In this case a Buck-Boost topology can be required in order to keep the output voltage in regulation.

The schematic below shows how to implement a Buck-Boost regulating 5V at the output from both 3.3V and 5V and 12V input buses.

In a Buck-Boost topology the current is delivered to the output during the OFF phase only. So, for a given current limit, the maximum output current depends strongly on the duty cycle. Assuming a 100% efficiency and neglecting the current ripple across the inductor, the relationship betweent the current limit and the maximum output current is the following:

OMAX

= I

LIM

⋅ (

1 – D

)

Where I

LIM

is the current limit and D is the duty cycle of the application.

The worst case is with D

MAX

. Since, in a Buck-Boost application, D is given by the following formula:

D =

-----------------------

+ V

The worst case is with V

INMIN

Obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output current is always lower than the value calculated in the above formula

Figure 30. Positive buck-boost regulator 3V to 13.2V input / 5V 2.5A Output Circuit

VIN (3.3V-5V-12V BUSES)

VCC (12V BUS)

R1 C3

OCSET

VCC

BOOT

GND

OSC

EAREF

U1

L6910/A

5 6

UGATE

PHASE

LGATE

PGND

PGOOD

VREF

C10

C12

C11

C1- C2

VOUT ( 5V 2.5A )

GNDOUT

22/29

L6910 - L6910A

C10

C11

Q1,Q2,Q3

C1,C2

C13,C14

C12,C5,C8

Table 13. Part List

Reference

Description

910 Ohm 5% 125mW

10K 5% 125mW

4.7K 5% 125mW

1K 5% 125mW

2.7K 5% 125mW

1K1

10 Ohm 125mW

100

F - 20V

330

F - 6.3V

100nF

1nF

470nF

4.7

F - 16V

100nF

15nF

1.5nF

47nF

Open

2.5

H (77121A7 Core, Double winding 7 AWG16)

STS11NF30L

STS5P30L

1N4148

STPS3L25U (STPS340U)

Device L6910

Figure 31. Efficiency vs. Output Current

Manufacturer

NEOHM

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

AUX

KEMET

Jumper

MAGNETICS

SMD 0805

RADIAL 10X10.5

SMD7343

SMD0805

SMA6032

SMD0805

SO8

SOT23

SMB (D0144)

SO16 Narrow

23/29

L6910 - L6910A

11 APPLICATION IDEA 3: BUCK-BOOST REGULATOR 3V TO 5.5V INPUT/-5V

3A OUTPUT

In applications where a negative output voltage is required, a standard Buck-Boost topology can be implemented. The considerations related to the maximum output current are the same of the "Positive Buck-Boost" (Application Idea 2).

A particularity of this topology is that the device undergoes a voltage that is the sum of V

and V

OUT

. So, converting 5V to -5V, the device undergoes 10V voltage. It must be checked that the sum of the input and output voltage is lower than the maximum operating input voltage of the device.

Figure 32. buck-boost regulator 3V to 5.5V input / -5V 3A Output Circuit

GND I N = GNDOUT

Table 14. Part List

Reference

C1,C2

C13,C14

C12,C4,C5,C8

24/29

Description

910 Ohm 5% 125mW

10K 5% 125mW

4.7K 5% 125mW

1K Ohm 5% 125mW

2.7K 5% 125mW

1K 5% 125mW

10 Ohm 5% 125mW

100

F - 20V

330

F - 6.3V

100nF

1nF

4.7

F - 16V

100nF

Manufacturer

NEOHM

OSCON 20SA100M

POSCAP 6TPB330M

KEMET

AUX

KEMET

SMD 0805

RADIAL 10X10.5

SMD7343

SMD0805

SMA6032

Table 14. Part List

(continued)

C10

Reference

C11

Q1,Q2

15nF

1.5nF

Description

47nF

Open

2.5

H (77121A7 Core, Double winding 7 AWG16)

STS11NF30L

1N4148

STPS3L25U ( STPS340U)

Device L6910

Figure 33. Efficiency vs. Output Current

KEMET

Manufacturer

KEMET

Jumper

MAGNETICS

L6910 - L6910A

SMD0805

SO8

SOT23

SMB (D0144)

SO16 Narrow

25/29

L6910 - L6910A

Figure 34. HTSSOP16 (Exposed pad) Mechanical Data & Package Dimensions

DIM.

A2 b c mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.8

0.19

0.09

1.0

1.2

0.15

0.047

0.006

1.05

0.031

0.039

0.041

0.3

0.007

0.012

0.2

0.003

0.008

D (*)

E 6.2

E1 (*) 4.3

E2 e

4.9

1.7

1.5

0.45

5.0

6.4

4.4

0.65

0.6

5.1

6.6

4.5

0.192

0.067

0.244

0.169

0.197

0.252

0.173

0.200

0.260

0.177

0.059

0.026

0.75

0.018

0.024

0.029

L1 k

1.0

0˚ (min), 8˚ (max)

0.10

0.039

aaa 0.004

(*) Dimensions D and E1 does not include mold flash or protusions. Mold flash or protusions shall not exeed

0.15mm per side.

OUTLINE AND

MECHANICAL DATA

HTSSOP16

(Exposed Pad)

7419276

26/29

L6910 - L6910A

Figure 35. SO-16 (Narrow) Mechanical Data & Package Dimensions

A a1 a2 b

DIM.

mm inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0.1

1.75

0.25

0.004

0.069

0.009

0.35

0.19

1.6

0.46

0.014

0.25

0.007

0.063

0.018

0.010

C c1

(1)

E e

9.8

5.8

0.5

6.2

(typ.)

0.386

0.228

0.020

0.394

0.244

(1) 3.8

1.27

8.89

4.0

0.150

0.050

0.350

0.157

4.60

0.4

5.30

1.27

0.181

0.150

0.208

0.050

0.62

(max.)

0.024

(1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.)

OUTLINE AND

MECHANICAL DATA

SO16 (Narrow)

0016020 D

27/29

L6910 - L6910A

Table 1. Revision History

Date Revision

January 2004

August 2004

May 2005 9

Description of Changes

Migration from ST-Press to EDOCS dms.

Changed any figures and textes; add. the section “15A HTSSOP16

Demo Board Description”.

Changed the style-look following the new “Corporate Technical

Pubblications Design Guide” rules; and figs 23, 30, 32

Changed the figure 30.

28/29

L6910 - L6910A

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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29/29

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