Method and system for controlling a mixed array of point-of

Method and system for controlling a mixed array of point-of
US007673157B2
(12) United States Patent
(10) Patent N0.:
(45) Date of Patent:
Chapuis et a].
(54)
METHOD AND SYSTEM FOR
CN
2521825
(75) Inventors: Alain Chapuis, Riedikon (CH); Mikhail
Guz, San Mateo, CA (US)
OTHER PUBLICATIONS
“Automated Power Distribution System Hardware”, Anderson et a1.;
Aug. 6, 1989; pp. 579-584.
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 569 days.
(Continued)
(21) App1.N0.: 11/558,848
(22) Filed:
Primary ExamineriThuan N Du
Assistant ExamineriStefan Stoynov
(74) Attorney, Agent, or Firm4O’Melveny & Myers LLP
Nov. 10, 2006
(65)
11/2002
(Continued)
(73) Assignee: Power-One, Inc., Camarillo, CA (US)
Notice:
Mar. 2, 2010
FOREIGN PATENT DOCUMENTS
CONTROLLING A MIXED ARRAY OF
POINT-OF-LOAD REGULATORS THROUGH
A BUS TRANSLATOR
(*)
US 7,673,157 B2
Prior Publication Data
US 2007/0124612 A1
(57)
May 31, 2007
Related U.S. Application Data
A power control system comprises at least one point-of-load
(POL) regulator adapted to provide an output voltage to a
corresponding load and a system controller operatively con
(63) Continuation-in-part of application No. 11/354,550,
?led on Feb. 14, 2006, now Pat. No. 7,266,709, which
is a continuation-in-part of application No. 10/326,
nected to the at least one POL regulator via a data bus and
adapted to send a ?rst data message in a ?rst format to the at
222, ?led on Dec. 21, 2002, now Pat. No. 7,000,125.
(51) Int. Cl.
G06F 1/00
G06F 1/26
F02P 3/02
H02H 7/00
ABSTRACT
least one POL regulator via the data bus. A bus translator is
interposed along the data bus between the at least one POL
regulator and the system controller. The bus translator con
(2006.01)
(2006.01)
(2006.01)
(2006.01)
verts the ?rst data message from the ?rst format to a second
format that is compatible with the at least one POL regulator.
The bus translator is adapted for bi-directional operation to
(52)
U.S. Cl. ..................... .. 713/300; 713/320; 323/371;
361/18
convert a second data message communicated from the at
(58)
Field of Classi?cation Search ............... .. 713/300,
least one POL regulator in the second format to the ?rst
713/320; 323/371; 361/18
See application ?le for complete search history.
format compatible with the system controller. The ?rst and
second data formats may comprise either a digital data format
(56)
or an analog data format. The bus translator may further
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(Continued)
21 Claims, 5 Drawing Sheets
Communication
204\
lnterface 2
POL1
206\
POL2
220\
B
202\
Translator
208\
System
Controller
Pol-3
210\
POL4
Communication
interface 1
US 7,673,157 B2
Page 2
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* cited by examiner
US. Patent
Mar. 2, 2010
Sheet 1 015
US 7,673,157 B2
[14
Intermediate Voltage Bus
48VA BUS
ACID/C
AC
12
A‘
DC/DrC
' Converter
=
POL ——> 1.8V
’
POL "" 2-5V
16
[24
Converter
[26
.7:
>
18/‘:
POL ——~> 3.3V
v
__
Printed Circuit Board
FIG. 1
(Prior Art)
Power Suppiy Controiier
FIG. 2
(Prior Art)
US. Patent
Mar. 2, 2010
Sheet 3 of5
US 7,673,157 B2
1f“?
{106
r
Vi “ML--
V0
Power Conversion Circuit
PG
,/ 144
Sync/Data
okfFaun
f 146
Serial
Interface
A
,
POL
Contro?er
148
/ I
f 159
Default
Hardwired
Con?g.
Settings
FIG. 4
[102
122
Serial Bus
USer_._>-_ ADDR
Al
U
Extern; 132
7
128
/
User
interface
POL :1: Sync/Data
Interface
oknzamt
I
i
‘I
Memory
124
[126 ‘'
Contro?er
————1>———> FE D18
A
A
v f 123
v
Memory
K130
Monitoring
‘-
C.‘
F
C
2 g S :2.
FIG. 5
US. Patent
Mar. 2, 2010
Sheet 4 of5
US 7,673,157 B2
Communication
204\
lnterface 2
=
POL’!
206\
=
POL2
220wr
Bus
202\
Translator
1*
System
208\
i
:
Controller ‘
POL3
2l0\
=
POL4
Communication
lnterface 1
FIG. 6
22O\
_
Bus
' Translator
Communication 204\
‘
230\
_
Bus
' Translator
interface 2
‘
_
POM
'
Communication 206\
‘
‘
Interface 3
_
Pol-2
'
202\
208\
System
i
:
Controller ‘
POL3
210\
=
Communication
Interface 1
FIG. 7
POL4
US. Patent
Mar. 2, 2010
Sheet 5 of5
US 7,673,157 B2
32.9.; ______________________ U
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Phase
i
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i
Synchronization ‘
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US 7,673,157 B2
1
2
METHOD AND SYSTEM FOR
CONTROLLING A MIXED ARRAY OF
POINT-OF-LOAD REGULATORS THROUGH
A BUS TRANSLATOR
the POL regulators. A draWback With such a control system is
that it adds complexity and siZe to the overall electronic
system.
It is also knoWn in the art to include Within an electronic
system various POL regulators of differing types and/ or made
RELATED APPLICATION DATA
by differing manufacturers. These various POL regulators
may be con?gured to receive distinct or proprietary command
This application claims priority as a continuation-in-part
pursuant to 35 U.S.C. § 120 to patent application Ser. No.
11/354,550, ?led Feb. 14, 2006 now US. Pat. No. 7,266,709,
and control instructions, therefore making it impossible to
operate the non-standard POL regulators together Within a
common poWer control system. It is nevertheless desirable to
coordinate the control over a mixed poWer system having a
Which Was in turn a continuation-in-part pursuant to 35
U.S.C. §120 to patent application Ser. No. 10/326,222, ?led
variety of differing types of POL regulators, hoWever, con
ventional distributed poWer system do not provide ?exibility
Dec. 21, 2002 now US. Pat. 7,000,125.
to control such a mixed poWer system.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to poWer control systems, or
more particularly, to a method and system to control, program
and monitor a mixed array of non-standard point-of-load
Thus, it Would be advantageous to have a system and
method for controlling and monitoring plural different types
of POL regulators Within a mixed poWer control system.
SUMMARY OF THE INVENTION
20
regulators using a bus translator.
2. Description of Related Art
With the increasing complexity of electronic systems, it is
common for an electronic system to require poWer provided
at several different discrete voltage and current levels. For
The present invention provides a system and method for
controlling, programming and monitoring plural different
types of POL regulators Within a mixedpoWer control system.
25
example, electronic systems may include discrete circuits that
require voltages such as 3V, 5V, 9V, etc. Further, many of
these circuits require a relatively loW voltage (e.g., 1V), but
With relatively high current (e. g., 100 A). It is undesirable to
deliver relatively high current at loW voltages over a relatively
long distance through an electronic device for a number of
30
high current lines consumes signi?cant circuit board area and
congests the routing of signal lines on the circuit board.
Second, the impedance of the lines carrying the high current
35
40
either a digital data format or an analog data format. The bus
translator may further include a phase synchronization circuit
adapted to synchroniZe operation of the bus translator to a
(“POL”) regulator, i.e., DC/DC converter, at the point of
detected data rate of the data bus or to synchroniZe the opera
45
the level required by the electronic circuit. An electronic
system may include multiple POL regulators to convert the
intermediate bus voltage into each of the multiple voltage
levels. Ideally, the POL regulator Would be physically located
adjacent to the corresponding electronic circuit so as to mini
troller. The bus translator converts the ?rst data message from
the ?rst format to a second format that is compatible With the
at least one POL regulator. The bus translator is adapted for
bi-directional operation to convert a second data message
communicated from the at least one POL regulator in the
second format to the ?rst format compatible With the system
controller. The ?rst and second data formats may comprise
poWer consumption Within the electronic system. Particu
larly, a POL regulator Would be included With each respective
electronic circuit to convert the intermediate bus voltage to
to provide an output voltage to a corresponding load and a
system controller operatively connected to the at least one
POL regulator via a data bus and adapted to send a ?rst data
message in a ?rst format to the at least one POL regulator via
the data bus. A bus translator is interposed along the data bus
betWeen the at least one POL regulator and the system con
reasons. First, the relatively long physical run of loW voltage,
tends to dissipate a lot of poWer and complicate load regula
tion. Third, it is dif?cult to tailor the voltage/ current charac
teristics to accommodate changes in load requirements.
In order to satisfy these poWer requirements, it is knoWn to
distribute an intermediate bus voltage throughout the elec
tronic system, and include an individual point-of-load
In an embodiment of the invention, a poWer control system
comprises at least one point-of-load (POL) regulator adapted
tion of the POL regulator.
A more complete understanding of the method and system
for controlling and monitoring a mixed array of non-standard
point-of-load regulators using a bus translator Will be
afforded to those skilled in the art, as Well as a realiZation of
50
additional advantages and objects thereof, by a consideration
of the folloWing detailed description of the preferred embodi
miZe the length of the loW voltage, high current lines through
ment. Reference Will be made to the appended sheets of
the electronic system. The intermediate bus voltage can be
draWings, Which Will ?rst be described brie?y.
delivered to the multiple POL regulators using loW current
lines that minimiZe loss.
With this distributed approach, there is a need to coordinate
the control and monitoring of the POL regulators of the poWer
BRIEF DESCRIPTION OF THE DRAWINGS
55
FIG. 1 depicts a prior art distributed poWer delivery sys
tem;
system. The POL regulators generally operate in conjunction
With a poWer supply controller that activates, programs, and
monitors the individual POL regulators. It is knoWn in the art
for the controller to use a multi-connection parallel bus to
FIG. 2 depicts a prior art POL control system using a
60
activate and program each POL regulator. For example, the
parallel bus may communicate an enable/ disable bit for tum
FIG. 3 depicts an exemplary POL control system con
structed in accordance With an embodiment of the present
invention;
ing each POL regulator on and off, and voltage identi?cation
(VID) code bits for programming the output voltage set-point
of the POL regulators. The controller may further use addi
tional connections to monitor the voltage/current that is deliv
ered by each POL regulator so as to detect fault conditions of
parallel control bus;
65
FIG. 4 depicts an exemplary POL regulator of the POL
control system;
FIG. 5 depicts an exemplary system controller of the POL
control system;
US 7,673,157 B2
4
3
sWitches 48, 54, 58, and 64. The controller 32 provides con
trol signals to the DC/DC converters 34, 36, 38, and 42 via a
plurality of six-bit parallel buses that each carry an enable/
disable bit and ?ve VID code bits. The VID code bits program
the DC/DC converters for a desired output voltage/current
level. The controller 32 also monitors the performance of the
DC/DC converters 34, 36, 38, and 42 using the sensing resis
tors 46, 52, 56, and 62. Particularly, the controller 32 monitors
the output voltage of each DC/ DC converter by detecting the
voltage at the output side of the sensing resistor, and monitors
FIG. 6 depicts an alternative embodiment of a POL control
system in Which plural non-standard POL regulators commu
nicate With a common system controller using an exemplary
bus translator;
FIG. 7 depicts another alternative embodiment of a POL
control system in Which plural non-standard POL regulators
communicate With a common system controller using plural
exemplary bus translators;
FIG. 8 depicts a block diagram of an exemplary bus trans
lator for communicating betWeen tWo serial data buses; and
FIG. 9 depicts a block diagram of an exemplary bus trans
the output current through the sensing resistor by detecting
the voltage across the sensing resistor. The voltage and cur
rent sensing for each DC/ DC converter requires tWo separate
lines, so eight separate lines are needed to sense the voltage
and current condition of the exemplary four-converter sys
lator for communicating betWeen a serial data bus and an
analog data bus.
DETAILED DESCRIPTION OF THE PREFERRED
EMBODIMENT
tem. Moreover, the controller 32 has a sWitch enable line
connected to the gate terminals of sWitches 48, 54, 58, and 64,
The present invention provides a system and method for
controlling and monitoring POL regulators Within a mixed
poWer control system. In the detailed description that folloWs,
like element numerals are used to describe like elements
by Which the controller 32 can shut off the output from any of
the DC/DC controllers 34, 36, 38, and 42 or control the
turn-on/ off sleW rate.
In an exemplary operation, the controller 32 provides con
illustrated in one or more ?gures.
trol parameters (e. g., output voltage set-point) to the DC/DC
Referring ?rst to FIG. 1, a prior art distributed poWer deliv
ery system is shoWn. The prior art distributed poWer deliver
bus. The controller 32 then activates the DC/ DC converter 34
system includes an AC/DC converter 12 that converts the
available AC poWer into a primary DC poWer source, e. g., 48
volts. The primary DC poWer source is connected to a primary
poWer bus that distributes DC poWer to plural electronic sys
tems, such as printed circuit board 14. The bus may be further
coupled to a battery 18 providing a back-up poWer source for
the electronic systems connected to the primary poWer bus.
When the AC/DC converter 12 is delivering DC poWer into
20
converter 34 via the VID code portion of the six-bit parallel
25
activated, the DC/DC converter 34 converts the poWer bus
voltage (e.g., 48 volts) into a selected output voltage. The
controller 32 then veri?es that the output voltage is the
desired voltage by measuring the voltage via the voltage
30
35
time de?ned by the capacity of the battery 18.
The printed circuit board 14 may further include a DC/DC
converter that reduces the primary bus voltage to an interme
diate voltage level, such as 5 or 12 volts. The intermediate
voltage is then distributed over an intermediate poWer bus
provided to plural circuits on the printed circuit board 14.
Each circuit has an associated point-of-load (“POL”) regula
tor located closely thereby, such as POLs 22, 24, and 26. Each
POL regulator converts the intermediate bus voltage to a loW
40
lines on the printed circuit board 14 are minimized. Moreover,
the intermediate poWer bus can be adapted to carry relatively
then continuously monitor the output voltage and the output
current produced by the DC/DC converter 34 by measuring
the output voltage via the voltage monitoring line and mea
suring the voltage drop across the sensing resistor (i.e., the
voltage differential betWeen the current monitoring line and
the voltage monitoring line). If the controller 32 detects a fault
condition of the DC/DC converter 34 (e.g., output voltage
drops beloW a speci?c threshold), the controller 32 can dis
able and reset the DC/ DC converter. The controller 32 com
municates With the other DC/DC converters 36, 38, and 42 in
the same manner.
45
voltage, high current level demanded by the electronic circuit,
such as 1.8 volts, 2.5 volts, and 3 .3 volts provided by POLs 22,
24, and 26, respectively. It should be appreciated that the
voltage levels described herein are entirely exemplary, and
that other voltage levels could be selected to suit the particular
needs of electronic circuits on the printed circuit board 14. By
locating the POLs 22, 24, 26 close to their corresponding
electronic circuits, the length of the loW voltage, high current
monitoring line. If the output voltage is Within an acceptable
range, it is provided to the load (not shoWn) by activating the
sWitch 48 via the sWitch enable line. The controller 32 can
the primary poWer bus, the battery 18 is maintained in a fully
charged state. In the event of loss ofAC poWer or fault With the
AC/DC converter 12, the battery 18 Will continue to deliver
DC poWer to the primary poWer bus for a limited period of
via the enable/ disable portion of the six-bit parallel bus. Once
A disadvantage With the control system of FIG. 2 is that it
adds complexity and siZe to the overall electronic system by
using a six-bit parallel bus to control each DC/ DC converter
and a separate three-line output connection to monitor the
performance of each DC/DC converter. In other Words, the
50
controller 32 utiliZes thirty-six separate connections in order
to communicate With four DC/ DC converters 34, 36, 38, and
42. As the complexity and poWer requirements of electronic
systems increase, the number of connections to the controller
Will also increase in a linear manner.
55
Referring noW to FIG. 3, a POL control system 100 is
shoWn in accordance With an embodiment of the present
loW current, thereby minimiZing poWer loss due to the line
invention. Speci?cally, the POL control system 100 includes
impedance. But, this distributed poWer delivery system does
a system controller 102, a front-end regulator 104, and a
not provide a Way to monitor and control the performance of
plurality of POL regulators 106, 108, 110, 112, and 114
the POLs 22, 24, 26.
FIG. 2 illustrates a prior art DC/ DC converter control sys
tem having a poWer supply controller 32 and a plurality of
60
poWer-on-load regulators, DC/DC converters, voltage regu
DC/DC converters 34, 36, 38, and 42. The DC/DC converters
34, 36, 38, and 42 are each connected to a poWer bus (as
described above With respect to FIG. 1), Which provides an
input voltage. The DC/ DC converters 34, 36, 38, and 42 each
provide a loW voltage, high current output that passes through
respective sensing resistors 46, 52, 56, and 62 and respective
arranged in an array. The POL regulators depicted herein
include, but are not limited to, point-of-load regulators,
65
lators, and all other programmable voltage or current regulat
ing devices generally knoWn to those skilled in the art. An
intra-device interface is provided betWeen individual ones of
the POL regulators to control speci?c interactions, such as
current share or paralleling, e.g., current share interface
(CS1) provided betWeen POL0 106 and POL1 108, and CS2
US 7,673,157 B2
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6
providedbetWeen POL4 112 and POLn 114. In the exemplary
con?guration shown in FIG. 3, POL0 106 and POL1 108
the normal operating mode of the POL regulator to thereby
minimiZe the need for additional programming signals from
the system controller 102.
The hardWired settings interface 150 communicates With
operate in parallel mode to produce output voltage V0l With
increased current capability, POL2 110 produces output volt
age VO2, and POL4 112 and POLn 114 operate in parallel
mode to produce output voltage V03, though it should be
appreciate that other combinations and other numbers of POL
using the serial interface 144. The hardWired settings inter
face 150 may include as inputs the address setting (Addr) of
regulators could be advantageously utiliZed.
the POL to alter or set some of the settings as a function of the
external connections to program the POL regulator Without
address (i.e., the identi?er of the POL), e.g., phase displace
The front-end regulator 104 provides an intermediate volt
ment, enable/disable bit (En), trim, and VID code bits. Fur
ther, the address identi?es the POL regulator during commu
nication operations through the serial interface 144. The trim
age to the plurality of POL regulators over an intermediate
voltage bus, and may simply comprise another POL regulator.
The system controller 102 and front-end regulator 1 04 may be
integrated together in a single unit, or may be provided as
input alloWs the connection of one or more external resistors
separate devices. Alternatively, the front-end regulator 104
may provide a plurality of intermediate voltages to the POL
regulators over a plurality of intermediate voltage buses. The
system controller 102 may draW its poWer from the interme
to de?ne an output voltage level for the POL regulator. Simi
larly, the VID code bits can be used to program the POL
regulator for a desired output voltage/current level. The
enable/disable bit alloWs the POL regulator to be turned
diate voltage bus.
on/ off by toggling a digital high/loW signal.
The system controller 1 02 communicates With the plurality
of POL regulators by Writing and/ or reading digital data (ei
20
received via either the hardWired settings interface 150 or the
serial interface 144, the POL controller 146 accesses the
ther synchronously or asynchronous) via a uni-directional or
bidirectional serial bus, illustrated in FIG. 3 as the synch/data
bus. The synch/data bus may comprise a tWo-Wire serial bus
(e. g., 12C) that alloWs data to be transmitted asynchronously
or a single-Wire serial bus that alloWs data to be transmitted
The POL controller 146 receives and prioritiZes the set
tings of the POL regulator. If no settings information is
25
parameters stored in the default con?guration memory 148.
Alternatively, if settings information is received via the hard
Wired settings interface 150, then the POL controller 146 Will
synchronously (i.e., synchronized to a clock signal). In order
apply those parameters. Thus, the default settings apply to all
to address any speci?c POL in the array, each POL is identi
?ed With a unique address, Which may be hardWired into the
POL or set by other methods. The system controller 102 also
Wiring. The settings received by the hardWired settings inter
communicates With the plurality of POL regulators for fault
of the parameters that cannot be or are not set through hard
30
management over a second uni-directional or bi-directional
face 150 can be overWritten by information received via the
serial interface 144. The POL regulator can therefore operate
in a stand-alone mode, a fully programmable mode, or a
serial bus, illustrated in FIG. 3 as the OK/fault bus. By group
combination thereof. This programming ?exibility enables a
ing plural POL regulators together by connecting them to a
plurality of different poWer applications to be satis?ed With a
common OK/fault bus alloWs the POL regulators have the
same behavior in the case of a fault condition. Also, the
system controller 102 communicates With a user system via a
35
An exemplary system controller 102 of the POL control
system 100 is illustrated in FIG. 5. The system controller 102
user interface bus for programming, setting, and monitoring
of the POL control system 10. Lastly, the system controller
102 communicates With the front-end regulator 104 over a
separate line to disable operation of the front-end regulator.
An exemplary POL regulator 106 of the POL control sys
40
regulators of FIG. 3 have substantially identical con?gura
45
default con?guration memory 148, and hardWired settings
as monitoring values or neW system settings Would be trans
mitted through the user interface 122. The communication
With the user (or host) may be direct or via a local area
netWork (LAN) or Wide area netWork (WAN). A user may
interface 150. The poWer conversion circuit 142 transforms
an input voltage (Vi) to the desired output voltage (V0)
according to settings received through the serial interface
144, the hardWired settings 150 or default settings. The poWer
includes a user interface 122, a POL interface 124, a control
ler 126, and a memory 128. The user interface 122 sends and
receives messages to/ from the user (or host) via the user
interface bus. The user interface bus may be provided by a
serial or parallel bi-directional interface using standard inter
face protocols, e.g., an 12C interface. User information such
tem 10 is illustrated in greater detail in FIG. 4. The other POL
tion. The POL regulator 106 includes a poWer conversion
circuit 142, a serial interface 144, a POL controller 146,
single generic POL regulator, thereby reducing the cost and
simplifying the manufacture of POL regulators.
access the POL control systems for purposes of monitoring,
controlling and/ or programming the POL control systems by
50
coupling directly to the user interface bus. The user system
conversion circuit 142 may also include monitoring sensors
Would likely include a user interface, such as a graphical user
for output voltage, current, temperature and other parameters
interface (GUI), that enables the display of status information
regarding the POL control systems.
that are used for local control and also communicated back to
the system controller through the serial interface 144. The
poWer conversion circuit 142 may also generate a PoWer
The POL interface 124 transforms data to/from the POL
55
regulators via the synch/data and OK/fault serial buses. The
Good (PG) output signal for stand-alone applications in order
POL interface 124 communicates over the synch/data serial
to provide a simpli?ed monitoring function. The serial inter
bus to transmit setting data and receive monitoring data, and
face 144 receives and sends commands and messages to the
communicates over the OK/fault serial bus to receive inter
rupt signals indicating a fault condition in at least one of the
connected POL regulators. The memory 128 comprises a
non-volatile memory storage device used to store the system
system controller 102 via the synch/data and OK/fault serial
buses. The default con?guration memory 148 stores the
default con?guration for the POL regulator 106, such as for
60
set-up parameters (e. g., output voltage, current limitation
set-point, timing data, etc.) for the POL regulators connected
use in cases Where no programming signals are received
through the serial interface 144 or hardWired settings inter
face 150. For example, the default con?guration may be
selected to cause the POL regulator 106 to operate in a “safe”
condition in the absence of programming signals. Alterna
tively, the default con?guration could be programmed to be
to the system controller 102. Optionally, a secondary, external
65
memory 132 may also be connected to the user interface 122
to provide increased memory capacity for monitoring data or
setting data.
US 7,673,157 B2
7
8
The controller 126 is operably connected to the user inter
face 122, the POL interface 124, and the memory 128. The
controller 126 has an external port for communication a dis
age data (i.e., the measured output voltage) or voltage-com
parison data (e.g., Whether the measured output voltage is
above or beloW the highest desired output voltage, Whether
able signal (FE DIS) to the front-end regulator 104. At start
the measured output voltage is above or beloW the loWest
up of the POL control system 100, the controller 126 reads
from the internal memory 128 (and/or the external memory
desired output voltage, etc.); output-current data, Which may
include actual-output-current data (i.e., the measured output
132) the system settings and programs the POL regulators
current) or current-comparison data (e.g., Whether the mea
sured output current is above or beloW the highest desired
accordingly via the POL interface 124. Each of the POL
regulators is then set up and started in a prescribed manner
output current); temperature-status data, Which may include
based on the system programming. During normal operation,
actual-temperature data (i.e., the measured temperature of a
the controller 126 decodes and executes any command or
POL regulator, or more particularly its heat generating com
message coming from the user or the POL regulators. The
ponents) or temperature-comparison data (e.g., Whether the
temperature of the POL regulator (or its components) is above
controller 126 monitors the performance of the POL regula
tors and reports this information back to the user through the
user interface 122. The POL regulators may also be pro
grammed by the user through the controller 126 to execute
or beloW a knoWn value, etc.), and/ or all other types of POL
speci?c, autonomous reactions to faults, such as over current
or over voltage conditions. Alternatively, the POL regulators
may be programmed to only report fault conditions to the
system controller 102, Which Will then determine the appro
priate corrective action in accordance With prede?ned set
tings, e. g., shut doWn the front-end regulator via the FE DIS
control line.
A monitoring block 130 may optionally be provided to
20
fault monitoring data generally knoWn to those skilled in the
art. It should also be appreciated that fault-monitoring data is
not limited to data representing the existence of a faulty
condition. For example, fault-monitoring data that indicates
that the POL regulator is operating Within acceptable param
eters (e.g., Within an acceptable temperature range) is con
sidered to be Within the spirit and scope of the present inven
tion.
The fault-monitoring data can be used by either the system
controller 102 or the POL controller 146 to monitor and/or
monitor the state of one or more voltage or current levels of 25 control the POL regulator. In other Words, the POL controller
other poWer systems not operably connected to the controller
102 via the synch/data or OK/fault buses. The monitoring
block 130 may provide this information to the controller 126
for reporting to the user through the user interface in the same
manner as other information concerning the POL control
system 100. This Way, the POL control system 100 can pro
146 can use the fault-monitoring data to either provide POL
status information (i.e., data corresponding to a particular
POL regulator or its output) to the system controller 102 or
disable the POL regulator if a particular condition is met (e. g.,
30
vide some backward compatibility With poWer systems that
are already present in an electronic system.
information to an administrator, disable a particular POL
regulator, or store the fault-monitoring data for future use. For
Returning to FIG. 3, the system controller 102 is adapted to
provide initial-con?guration data to each POL regulator (i.e.,
106, 108, 110, 112, 114). It should be appreciated that the
35
initial-con?guration data may include, but is not limited to,
programming data generally knoWn to those skilled in the art.
Once the initial-con?guration data is received, the POL con
troller 146 (see FIG. 4) is adapted to store at least a portion of
the initial-con?guration data in memory. At least a portion of
the stored initial-con?guration data is then used to produce a
desired output. For example, an output may be produced to
include a particular voltage level, a particular sleW rate, etc.,
depending on the type of initial-con?guration data received/
stored.
After the output has been produced, the POL controller 146
is adapted to receive fault-monitoring data (e.g., from an
external device, a sense circuit, etc.). The fault-monitoring
data, Which contains information on the POL regulator or its
output, is then stored in the memory. The POL controller 146,
in response to a condition (e.g., receiving a request, exceeding
a knoWn parameter, having a register’s contents change, etc.),
is then adapted to provide at least a portion of the fault
monitoring data to the system controller 102. It should be
appreciated that the fault-monitoring data may include, but is
example, in one embodiment of the present invention, each
POL regulator includes unique ID data (e.g., serial number,
one or more of the folloWing types of data: output-voltage
set-point-data (i.e., a desired output voltage); output-current
set-point data (i.e., the highest desired output current); loW
voltage-limit data (i.e., the loWest desired output voltage);
high-voltage-limit data (i.e., the highest desired output volt
age); output-voltage-sleW-rate data (i.e., the desired output
sleW rate); enable/disable data (i.e., turning on/off the POL
regulator output); timing data (e.g., turn-on delay, tum-off
delay, fault recovery time, etc.) and/or all other types of POL
the status register changes, the temperature limit has been
exceeded, etc.). Alternatively, the system controller 102 can
use the fault-monitoring data to either provide POL status
40
date of manufacture, etc.) stored in an ID register. This
enables the system controller 102 to provide POL status infor
mation and unique ID data to an administrator.
In another embodiment of the present invention, each POL
regulator further includes at least one sensor circuit. The
sensor circuit is used to produce either the fault-monitoring
data, or data that can be used (e.g., together With information
stored in the memory) to produce the fault-monitoring data. It
45
should be appreciated that the sensor circuit, as described
herein, Will vary (e.g., as to circuitry, location, inputs, etc.)
depending upon the type of information that is being detected.
For example, a sensor circuit that detects current may include
different circuitry, have different inputs, and be placed in a
50
different location than a sensor circuit that detects tempera
ture.
The POL control system 10 enables four different modes of
operation. In the ?rst operational mode, the POL regulators
55
function independently in the absence of a system controller
and Without interaction With other POL regulators. The POL
regulators each include local feedback and control systems to
regulate their oWn performance as Well as control interfaces
to enable local programming. The POL regulators further
60
include default settings in Which they can revert to in the
absence of local programming or data from the system con
troller. In other Words, each of the POL regulators can operate
as a standalone device Without the need for a system control
ler or interactions With another POL regulator.
In the second operational mode, the POL regulators inter
not limited to, one or more of the folloWing types of data:
operate for the purpose of current sharing or interleaving in
the absence of a system controller. The POL regulators com
output-voltage data, Which may include actual-output-volt
municate With each other over the current share interface. The
65
US 7,673,l57 B2
9
10
synch/data line may be used to communicate synchronization
not compatible With the system controller 202, such as due to
difference of data format and/or protocol. POL1 204 and
POL2 206 are each coupled to a separate data bus, Which may
information to permit phase interleaving of the POL regula
tors, in Which the phase is programmed locally by entering an
be serial data or analog (termed Communication Interface 2).
To provide interoperability betWeen Communication Inter
address through hardWired connections. In either the ?rst or
second modes of operation, there Would generally be infor
mation communicated betWeen the POL regulators except for
face 1 and Communication Interface 2, a bus translator 220 is
synchronization; there Would be no need to communicate
interposed therebetWeen. The bus translator 220 Will receive
programming information.
In the third operational mode, the POL regulators operate
the array as a Whole are coordinated by a system controller.
data messages on one of the tWo interfaces, translate the data
messages to the data format and/ or protocol of the other
interface, and then communicate the translated data messages
onto the other interface. The bus translator 220 Would be
The system controller programs the operation of each of the
POL regulators over the synch/data serial bus, and thereby
overrides the predetermined settings of the POL regulators.
adapted to operate bi-directionally, so that data messages
received in either direction Would pass therethrough. With the
bus translator 220 in place, POL1 204 and POL2 206 Would
The synch/data serial bus is further used to communicate
be able to communicate With the system controller 202 as Well
as With POL3 208 and POL4 210 as if they Were all part of a
as an array in Which the behavior of each POL regulator and
synchronization information to permit synchronization and
interleaving of the POL regulators. This operational mode
Would not include interdevice communications over the cur
rent share interface.
Lastly, the fourth operational mode includes both central
20
With exemplary POL regulators POL1 204, POL2 206, POL3
control using the system controller and local control over
certain functionality. This Way, the POL regulators operate as
an array coordinated by a system controller and also interop
erate With each other to perform functions such as current
sharing.
25
In an embodiment of the invention, the POL regulators of a
poWer control system Would each be con?gured in a standard
208, and POL4 210. POL regulators POL3 208 and POL4 210
are compatible With the system controller 202, and the three
elements communicate With each other through a serial data
bus (termed Communication Interface 1). POL1 204 and
POL2 206 are not compatible With the system controller 202,
nor are they compatible With each other, such as due to dif
ference of data format and/ or protocol. POL1 204 is coupled
ized manner so that data communicated betWeen the POL
regulators and the system controller Would have a knoWn
format and protocol that is understood by all elements of the
poWer control system. The selected data format/protocol may
standard poWer control system.
FIG. 7 illustrates another exemplary embodiment of a
mixed poWer control system. As in FIG. 6, the poWer control
system includes a system controller 202 that communicates
30
to a separate data bus (e.g., serial data or analog) (termed
Communication Interface 2), and POL2 206 is coupled to
another separate data bus (e. g., serial data or analog) (termed
be proprietary such that only a single vendor’s POL regula
Communication Interface 3). Bus translator 220 is interposed
tors Would be able to communicate Within the poWer control
betWeen Communication Interfaces 1 and 2, and bus transla
tor 230 is interposed betWeen Communication Interfaces 1
and 3. As in the preceding embodiment, the bus translators
system. Alternatively, the data format/protocol may be
de?ned by an open industry standard, so that different ven
35
dors could produce compatible POL regulators that could
220, 230 Will receive data messages on one of the tWo inter
each operate Within a standardized poWer control system.
faces, translate the data messages to the data format and/or
In certain applications, hoWever, it may be advantageous to
permit the operation of various non-standardized POL regu
protocol of the other interface, and then communicate the
lators Within a common poWer control system, including POL
translated data messages onto the other interface. The bus
40
regulators that are adapted to communicate using different
ally, so that data messages received in either direction Would
pass therethrough. This Way, POL1 204 and POL2 206 Would
be able to communicate With the system controller 202 as Well
data formats or communication protocols, e.g., a mixed or
non-standardized poWer control system. For example, an
electronic system may include various component elements
(e. g., POL regulators) that are provided by different vendors
translators 220, 230 Wouldbe adapted to operate bi-direction
as With each other and With POL3 208 and POL4 210 as if
45
and that are not compatible in data format and/or protocol.
Such a system may include a mix of legacy components that
they Were all part of a standard poWer control system.
It should be appreciated that an actual poWer control sys
tem may have different numbers of POL regulators. In accor
Were provided at an earlier time alongside neWer poWer con
dance With the present invention, the poWer control system
trol system components that are compatible With either a
could include both standard and non- standard POL regulators
proprietary or open-standard data format/protocol. Neverthe
50
less, it Would still be desirable to coordinate the poWer control
throughout the electronic system to achieve the aforemen
tioned bene?ts of centralized control. Accordingly, the fol
loWing embodiments of the invention provide solutions to
permit a mixed poWer control system to interoperate together
Within a common poWer control system through the use of
one or more bus translators. This Would enable the system
controller to communicate control data to the POL regulators
and receive fault monitoring data in return. Moreover, the
embodiments illustrated in FIGS. 6 and 7 re?ected use of an
55
and achieve the same bene?ts of a standardized poWer control
system.
exemplary bus translator in translating and propagating con
trol data ordinarily communicated using the Synch/Data line
(see FIG. 3). It should be appreciated that the same bus
translator device could provide translation and propagation of
Referring to FIG. 6, an exemplary embodiment of a mixed
poWer control system is shoWn. As in the preceding embodi
ments, the poWer control system includes a system controller
202 that communicates With a plurality of POL regulators,
including exemplary POL regulators POL1 204, POL2 206,
signals communicated on the OK/Fault line.
Referring noW to FIG. 8, an exemplary bus translator 220 is
illustrated in greater detail. As described above, the bus trans
lator 220 include tWo bidirectional communication interfaces
POL3 208, and POL4 210. For purposes of this example, POL
regulators POL3 208 and POL4 210 are compatible With the
system controller 202, and the three elements communicate
With each other through a serial data bus (termed Communi
cation Interface 1). In contrast, POL1 204 and POL2 206 are
(termed Communication Interface 1 and 2). Communication
Interface 1 is coupled to transmit/receive unit 222 (compris
ing receive module 222A and transmit module 222B), and
Communication Interface 2 is coupled to transmit/receive
unit 226 (comprising receive module 226A and transmit mod
65
US 7,673,157 B2
11
12
ule 226B). Each transmit/receive unit 222, 226 is in turn
coupled to memory unit 224. The memory unit 224 may
certain advantages of the system have been achieved. It
include a look up table, map, algorithms or other instructions
for translating betWeen data formats/protocols. As generally
tations, and alternative embodiments thereof may be made
Within the scope and spirit of the present invention. The
knoWn in the art, the memory unit 224 may also include
invention is further de?ned by the folloWing claims.
should also be appreciated that various modi?cations, adap
limited data processing logic suitable for controlling opera
What is claimed is:
tion of the memory unit to search for, retrieve, and relay data
values. In an exemplary operation, an incoming data message
1. A poWer control system comprising:
at least one point-of-load (POL) regulator comprising a
arriving from Communication Interface 1 is passed through
POL controller and a poWer conversion circuit adapted
to provide an output voltage to a corresponding load;
receive module 222A to memory unit 224, Whereupon the
data message is translated and forWarded to receive unit
226A, Which passes the translated data message onto Com
a system controller operatively connected to the POL con
troller via a data bus and adapted to send a ?rst data
message in a ?rst format to the POL controller via the
munication Interface 2. The same operation Will occur in the
reverse direction to translate data messages arriving from
Communication Interface 2.
The bus translator 220 may further include a phase syn
data bus; and
a bus translator interposed along the data bus betWeen the
POL controller and the system controller, the bus trans
lator converting the ?rst data message from the ?rst
format to a second format that is compatible With the
chronization circuit 228 to control the timing of operation of
the transmit/receive unit 222 and the memory unit 224. The
phase synchronization circuit 228 could be based on a phase
locked loop circuit or could be interrupt driven. As knoWn in
POL controller;
20
Wherein the POL controller uses at least a portion of the
the art, a phase-locked loop circuit responds to both the fre
?rst data message in the second format to produce, via
quency and the phase of the input signals to automatically
the poWer conversion circuit, the output voltage.
raise or loWer the frequency of a controlled oscillator until it
is matched to the reference in both frequency and phase. The
exemplary phase synchronization circuit 228 Would monitor
the phase and frequency of the incoming data messages
25
received on the Communication Interface 1, and thereby pro
vide a clock signal to the transmit/receive unit 222 and the
memory unit 224 so as to synchronize the timing of their
operation. The phase synchronization circuit 228 may further
provide the clock signal externally of the bus translator 220 so
as to provide synchronization With other external systems,
such as the pulse Width modulators of POL regulators. In the
case of an interrupt-driven phase synchronization circuit 228,
incoming data or synchronization information Would trigger
speci?c actions in the bus translator 220 to assure synchro
nized operation of data translation and propagation.
30
35
FIG. 9 illustrates an alternative embodiment of a bus trans
lator 240. As in the foregoing embodiment, the bus translator
240 includes tWo bidirectional communication interfaces;
hoWever, the ?rst interface (termed Communication Interface
1) is adapted for digital signal communications and the sec
40
45
mats.
50
coupled to memory unit 244, Which operates in substantially
prising:
55
generating initial-con?guration data intended for at least
one point of load (POL) regulator, the at least one POL
regulator comprising a POL controller and a poWer con
version circuit adapted to provide an output voltage to a
same operation Will occur in the reverse direction to translate
include a phase synchronization circuit 248 in order to syn
chronize the operation of the transmit/receive unit 242 and
memory unit 244 to incoming data messages.
Having thus described a preferred embodiment of a
method and system to control, program and monitor a mixed
11. The poWer control system of claim 1, Wherein the ?rst
data message further comprises programming data for the at
least one POL regulator.
12. A method of controlling a poWer control system, com
the same manner as described above. In an exemplary opera
analog data values arriving from the Analog Interface. As in
the preceding embodiment, the bus translator 240 may further
9. The poWer control system of claim 7, Wherein the phase
synchronization circuit is driven by external event signals.
10. The poWer control system of claim 1, Wherein the bus
translator further comprises a memory unit containing
instructions for converting betWeen the ?rst and second for
sion unit 246 (comprising digital-to-analog converter (DAC)
246A and analog-to-digital converter 246B). The transmit/
tion, a data message arriving from Communication Interface
1 is passed through receive module 242A to memory unit 244,
Whereupon the data message is translated and forWarded to
DAC 246A, Which converts the binary message to analog data
values that are then passed onto the Analog Interface. The
detected data rate of the data bus.
looped circuit.
module 242A and transmit module 224B) in the same manner
as in FIG. 8. The Analog Interface is coupled to data conver
receive unit 242 and data conversion unit 246 are each
system controller.
4. The poWer control system of claim 3, Wherein the second
data message further comprises status monitoring data from
the POL controller.
5. The poWer control system of claim 1, Wherein said
second format comprises a digital data format.
6. The poWer control system of claim 1, Wherein said
second format comprises an analog data format.
7. The poWer control system of claim 1, Wherein the bus
translator further comprises a phase synchronization circuit
adapted to synchronize operation of the bus translator to a
8. The poWer control system of claim 7, Wherein the phase
synchronization circuit further comprises a phase-locked
ond interface (termed Analog Interface) is adapted for analog
signal communications. Communication Interface 1 is
coupled to transmit/receive unit 242 (comprising receive
2. The poWer control system of claim 1, Wherein the data
bus further comprises a serial data bus.
3. The poWer control system of claim 1, Wherein the bus
translator is adapted for bi-directional operation to convert a
second data message communicated from the POL controller
in the second format to the ?rst format compatible With the
corresponding load;
60
translating the initial-con?guration data from a ?rst format
to a second format that is compatible With the POL
controller;
propagating the translated initial-con?guration data to the
POL controller; and
65
operating the POL controller to control a characteristic of
array of non-standard point-of-load regulators using a bus
the output voltage in accordance With at least a portion of
translator, it should be apparent to those skilled in the art that
the translated initial-con?guration data.
US 7,673,157 B2
14
13
13. The method of claim 12, further comprising:
second format that is compatible With the POL controller and
propagating the translated ?rst data message POL controller,
generating a data message at the at least one POL regulator
intended for a poWer system controller;
Wherein the POL controller uses at least a portion of the
translated ?rst data message to produce, via a poWer conver
translating the data message from the second format to the
?rst format that is compatible With the poWer system
sion circuit of the at least one POL regulator, the output
voltage.
controller;
17. The bus translator of claim 16, further adapted for
propagating the translated data message to the poWer sys
tem controller; and
operating the poWer control system in accordance With the
translated data message.
14. The method of claim 12, Wherein said second format
comprises a digital data format.
15. The method of claim 12, Wherein said second format
comprises an analog data format.
16. A bus translator for use in a poWer control system
bi-directional operation to convert a second data message
communicated from the at least one POL regulator in the
15
comprising at least one point-of-load (POL) regulator
adapted to provide an output voltage to a corresponding load,
and a system controller operatively connected to the at least
one POL regulator and adapted to send a ?rst data message in
a ?rst format to the at least one POL regulator, the bus trans
lator being interposed betWeen a POL controller of the at least
one POL regulator and the system controller, the bus transla
tor translating the ?rst data message from the ?rst format to a
second format to the ?rst format compatible With the system
controller.
18. The bus translator of claim 16, Wherein said second
format comprises a digital data format.
19. The bus translator of claim 16, Wherein said second
format comprises an analog data format.
20. The bus translator of claim 16, further comprising a
phase synchronization circuit adapted to synchronize opera
tion to a detected data rate of the data bus.
21. The bus translator of claim 16, further comprising a
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memory unit containing stored instructions for converting
betWeen the ?rst and second formats.
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