Microprocessor-based device incorporating a cache for capturing

Microprocessor-based device incorporating a cache for capturing
US006154857A
United States Patent [19]
[11] Patent Number:
Mann
[45]
[54] MICROPROCESSOR-BASED DEVICE
INCORPORATING A CACHE FOR
CAPTURING SOFTWARE PERFORMANCE
PROFILING DATA
Inventor:
Date of Patent:
Embedded System Engineering Show Catalogue, by
Motorola, pp. 52—54, Apr/May 1997.
MEVB Quick Start Guide, by Motorola, pp. 3—5 and 7—2
(admitted prior to Dec. 17, 1997).
Systems Programming, Aug. 1997.
CPU32 Reference Manual, by Motorola, pp. 7—1 through
7—13 (admitted prior to Dec. 17, 1997).
(List continued on next page.)
Appl. No.: 08/992,610
Primary Examiner—John A. Follansbee
Attorney, Agent, or Firm—Akin, Gump, Strauss, Hauer &
Feld, LLP
Dec. 17, 1997
Related US. Application Data
Provisional application No. 60/043,070, Apr. 8, 1997.
Int. Cl.7 ............................ .. H02H 3/05; G01R 31/28
US. Cl. ................................ .. 714/30; 714/38; 714/47
Field of Search ......................... .. 714/30, 34, 35—39,
714/47; 712/227
3,707,725
5,058,114
5,371,689
5,537,541
5,590,354
5,724,505
5,774,724
5,898,873
Nov. 28, 2000
Choosing a Cross—Debugging Methodology, Embedded
Daniel Peter Mann, Austin, Tex.
Assignee: Advanced Micro Devices, Inc.,
Sunnyvale, Calif.
Filed:
6,154,857
[57]
ABSTRACT
A processor-based device incorporating an on-chip trace
cache and supporting circuitry for providing softWare per
formance pro?ling information. A trigger control register is
con?gured to initialize and trigger (start) a ?rst on-chip
References Cited
counter upon entry into a selected procedure. A second
U.S. PATENT DOCUMENTS
the procedure prologue of the selected procedure is entered.
Counter values re?ecting the lapsed execution time of the
trigger control register is used to stop the ?rst counter When
12/1972 Delheim .................................... .. 444/1
10/1991 Kuboki et al. .
12/1994 Tatsuma .
7/1996 Wibecan .......................... .. 395/18321
..... .. 395/800
12/1996 Klapproth et al.
395/18321
3/1998 Argade et al.
6/1998
4/1999
Heisch
........ ..
395/704
Lehr ...................................... .. 395/704
FOREIGN PATENT DOCUMENTS
0316609 A2 5/1989
0316609 A3 5/1989
0636976 A1 2/1995
0762276 A1 3/1997
0849670 A1 6/1998
59-194245 11/1984
European
European
European
European
European
Pat.
Pat.
Pat.
Pat.
Pat.
Off.
Off.
Off.
Off.
Off.
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selected procedure are then stored in the on-chip trace cache.
Similar techniques can be used to measure other parameters
such as interrupt handler execution times. In the disclosed
embodiment of the invention, a second counter is also
provided. The second counter runs continually, but is reset
to Zero folloWing a stop trigger event caused by the second
trigger control register. The stop trigger event also causes the
value of the second counter to be placed in the on-chip trace
cache. This second counter value is useful for obtaining the
frequency of occurrence of a procedure of interest, Whereas
the ?rst counter provides information about the procedure’s
execution time. Either post-processing softWare executing
on a target system, a host system utilizing a debug port, or
off-chip trace capture hardWare can be used to analyZe the
Japan .
pro?le data. Both serial and parallel communication chan
OTHER PUBLICATIONS
nels are provided for communicating the trace information
Kruse, Data Structures and Program Design, Prentice—Hall,
1987, pp. 71—79.
Pentium Processor’s User Manual, Vol. 3: Architecture and
to external devices. The processor-based device thereby
provides a ?exible, high-performance solution for furnishing
softWare performance pro?ling information.
Programming Manual, by Intel Corporation, pp. 17—1
through 17—9, 1994.
21 Claims, 8 Drawing Sheets
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6,154,857
Page 2
OTHER PUBLICATIONS
K5 HDT, e—mail describing K5 HDT, Jan. 11, 1997.
Vanishing Wsibility, Part 2, Embedded Systems Program
ming, Aug. 1997, pp. 113 through 115.
Advanced On—chip Debug for Cola'Fire Developers,
Embedded Systems Programming, Apr/May 1997, pp. 52
through 54.
IBM Corporation, “Tailorable Embedded Event Trace”,
Dec. 1991, pp. 259—261, IBM Technical Disclosure Bulletin,
vol. 34, No. 7B, XP000282573.
Geoff Revill, “Advanced On—chip Debug for ColdFire
Debugging with Real—Time Trace, Embedded Systems Pro
gramming, Aug. 1997, pp. 50 through 58.
Developers”, Embedded System Engineering, Apr./May
1997, pp. 52—54.
U.S. Patent
Nov. 28,2000
Sheet 1 0f8
6,154,857
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U.S. Patent
Nov. 28,2000
Sheet 4 0f 8
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START DEBUG
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WRITE DEBUG
INSTRUCTION T0
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LUADIUNLDAD NEW
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CHECK FINISHED FLAG
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CHECK FINISHED FLAG
FIG. 4
f 410
6,154,857
U.S. Patent
Nov. 28,2000
Sheet 5 0f8
6,154,857
START DEBUG
502
WHITE DEBUG
INSTRUCTION TU
TAP CONTROLLER
r 506
504
LOADIUNLUAD DEBUG
SCAN CHAIN WITH
PENDING BIT SET
<-—_-YES
CMDACK - I?
N0
FIG. 5
U.S. Patent
Nov. 28,2000
Sheet 6 0f8
6,154,857
tsriagrter tsritgoepr
tsriagrter tsrtigoepr tsriagrter tsritgoepr
reset
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U.S. Patent
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6,154,857
1
2
MICROPROCESSOR-BASED DEVICE
INCORPORATING A CACHE FOR
CAPTURING SOFTWARE PERFORMANCE
PROFILING DATA
tions in system memory. Breakpoint registers are used to
generate off-chip trigger pulses that function to start and stop
timers. The serial link, hoWever, does not provide on-chip
softWare performance pro?ling capture capabilities—
additional dedicated pins and external trace capture hard
Ware are required to provide pro?le data.
As mentioned, softWare itself is sometimes instrumented
so that it can be analyZed to collect performance pro?ling
RELATED APPLICATION
This application claims priority to United States applica
tion Ser. No. 60/043,070, ?led Apr. 8, 1997, Which is hereby
incorporated by reference as if set forth in its entirety.
10
BACKGROUND OF THE INVENTION
1. Field of the Invention
to activate counters that track execution times. As a speci?ed
program run call is executed, a jump to an inserted routine
The invention relates to softWare performance pro?ling
support in microprocessors, and more particularly to a
15
microprocessor-based device incorporating an on-chip trace
data.
2. Description of the Related Art
20
softWare procedures Within a softWare program. Perfor
softWare applications. Various techniques for performing
softWare pro?ling are currently used, including many base
don statistical analysis. When performing softWare pro?ling,
25
tors the system buses of the computer system Which is
executing the softWare. Alternatively, softWare can be
“instrumented” or modi?ed to provide pro?ling information
directly to the computer system on Which the softWare is
executed.
The groWth in softWare complexity, coupled With increas
Thus, many current solutions for softWare performance
pro?ling have a variety of hardWare and softWare
limitations, including: the need to instrument code,
increased packaging and development costs, circuit
complexity, and bandWidth matching dif?culties. AloW-cost
execution times and subroutine call linkage are sometimes
captured by external (off-chip) instrumentation that moni
module, the total execution time of the module can be
calculated. Of course, the execution time of a given proce
dure may vary depending on the state of variables Within the
procedure, requiring statistical sampling to be utiliZed.
mance pro?ling can be a very useful tool to a softWare
engineer attempting to optimiZe the execution times of
is performed to mark a counter/timer. The execution time of
a parent procedure that calls other, ancillary procedures can
be determined by subtracting the execution time(s) of the
ancillary procedures from the total execution time of the
parent procedure. By analyZing all of the procedures of a
cache capable of capturing softWare performance pro?le
Software performance pro?ling refers to examining the
execution times, frequencies and calling patterns of different
data. Instrumented code is often generated by a compiler
con?gured to insert pro?ling information in order to analyZe
selected procedures. For example, on procedure call pro
logues and exit epilogues, the compiler may insert code used
30
procedure for capturing pro?le data Would be greatly
desirable, especially because the limitations of the existing
solutions are likely to be exacerbated in the future as internal
processor clock frequencies continue to increase.
SUMMARY OF THE INVENTION
35
Brie?y, a processor-based device according to the present
ing processor clock speeds, has placed neW burdens on
invention includes an on-chip trace cache and supporting
application softWare developers and complicated the task of
performance pro?ling. The costs associated With
developing, debugging and optimiZing neW softWare prod
circuitry for providing softWare performance pro?ling infor
40
ucts is noW a signi?cant factor in processor selection.
Processor features that adequately facilitate softWare debug,
including performance pro?ling, result in shorter customer
development times and increase the processor’s attractive
ness for use Within industry. The need to provide softWare
debug support is particularly acute Within the embedded
In a system according to the present invention, a break
45
often combined With a processor core.
Logic analyZers, read-only memory (ROM) emulators
memory and register contents, as Well as overlay and trace
memory in case system memory is insufficient. HoWever,
use of traditional in-circuit emulators, Which involves inter
facing a custom emulator back-end With a processor socket
to alloW communication betWeen emulation equipment and
the target system, is becoming increasingly dif?cult and
expensive in today’s age of exotic packages and shrinking
50
techniques can be used to measure other parameters such as
interrupt handler execution times.
55
In the disclosed embodiment of the invention, a second
counter is also provided. The second counter runs
continually, but is reset to Zero folloWing a stop trigger event
caused by the second trigger control register. The stop
trigger event also causes the value of the second counter to
60
be placed in the on-chip trace cache. This second counter
value is useful for obtaining the frequency of occurrence of
a procedure of interest, Whereas the ?rst counter provides
information about the procedure’s execution time.
The pro?le data can be analyZed by post-processing
for basic run control. Through a dedicated serial link requir
apply basic code breakpoints by inserting special instruc
point or trigger control register is con?gured to initialiZe and
trigger (start) a ?rst on-chip counter upon entry into a
selected procedure. A second breakpoint or trigger control
register is used to stop the ?rst counter When the procedure
prologue of the selected procedure is entered. Counter
values re?ecting the lapsed execution time of the selected
procedure are then stored in the on-chip trace cache. Similar
product life cycles.
In another approach (the “Background Debug Mode” by
Motorola, Inc.), limited on-chip debug circuitry is provided
ing additional pins, this approach alloWs a debugger/
performance pro?ler to start and stop the target system and
pro?ling information is thereby gathered Without instru
menting code, negatively impacting program execution
speeds, or using expensive off-chip support equipment.
products industry, Where specialiZed on-chip circuitry is
and in-circuit emulators (ICE) are frequently employed to
capture softWare performance pro?ling data. In-circuit emu
lators provide certain advantages over other debug
environments, offering complete control and visibility over
mation. The trace cache gathers information concerning the
execution time spent in selected procedures. Performance
65
softWare resident in the computer system in Which the
selected procedures are executed, by a host system utiliZing
a debug port, or via off-chip trace capture hardWare.
Generally, only one procedure is pro?led at a time. By
6,154,857
3
4
examining the trace cache, the minimum, average, and
or digital signal processor. Preferably, the debug port 100
maximum times spent in a procedure, as Well as other
uses an IEE-1149.1-1990 compliant JTAG interface or other
statistical data, can be determined. One bene?cial aspect of
similar standardiZed serial port interface.
Ahost system H is used to execute debug control softWare
the invention is that the procedure prologue and epilogue are
not required to be modi?ed. HoWever, a compiler can still be
utiliZed to add pro?ling information for use With the present
invention.
Both serial and parallel communication channels are
provided for communicating the trace information to exter
nal devices. In the disclosed embodiment of the invention
112 for transferring high-level commands and controlling
the extraction and analysis of softWare performance pro?l
ing information generated by the target system T. The host
system H and target system T of the disclosed embodiment
10
controllability and observability of the pro?le (or trace)
of the invention communicate via a serial link 110. Most
computers are equipped With a serial or parallel interface
Which can be inexpensively connected to the debug port 100
by means of a serial connector 108, alloWing a variety of
cache are achieved through a softWare debug port that uses
an IEEE-1149.1-1990 compliant JTAG (Joint Test Action
computers to function as a host system H. Alternatively, the
Group) interface or a similar standardiZed interface that is
serial connector 108 could be replaced With higher speed
JTAG-to-netWork conversion equipment. Further, the target
system T can be con?gured to internally analyZe softWare
integrated into the processor-based device.
Thus, a processor-based device supplying a ?exible, high
performance solution for furnishing softWare performance
pro?ling information is provided. The disclosed on-chip
15
performance pro?le data.
Referring noW to FIG. 2, details of the embedded pro
cessor device 102 according to the present invention are
provided. In addition to a processor core 104, FIG. 2 depicts
various elements of an enhanced embodiment of the debug
trace cache also alleviates various of the bandWidth and
clock synchronization problems that arise in many existing
solutions.
port 100 capable of utiliZing and controlling.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be
Trace cache 200. Many other con?gurations are possible,
25
obtained When the folloWing detailed description of the
preferred embodiment is considered in conjunction With the
With providing the on-chip trace cache 200.
folloWing draWings, in Which:
The Trace control circuitry 218 and the trace cache 200 of
FIG. 1 is a block diagram of a softWare debug environ
the disclosed embodiment of the invention can also coop
ment utiliZing a softWare pro?ling and debug solution in
accordance With the present invention;
erate to capture softWare performance pro?ling information.
In addition, the trace control circuitry 218 supports “tracing”
FIG. 2 is a block diagram providing details of an exem
to a trace pad interface port 200 or to the trace cache 200 and
plary embedded processor product incorporating an on-chip
trace cache according to the present invention;
FIG. 3 is a simpli?ed block diagram depicting the rela
35
tionship betWeen an exemplary trace cache and other com
ponents of an embedded processor product according to the
FIG. 4 is a ?oWchart illustrating softWare debug com
mand passing according to one embodiment of the inven
supported in the softWare debug port 100 in the described
embodiment of the invention. The JTAG pins essentially
become a transportation mechanism, using existing pins, to
enter pro?ling and other commands to be performed by the
tion;
FIG. 5 is a ?oWchart illustrating enhanced command
processor core 104. More speci?cally, the test clock signal
45
according to the present invention;
FIG. 6B illustrates the general format of a trace cache
skilled in the art. As discussed in more detail beloW, an
mation in accordance With the invention; and
FIG. 7A—7G illustrate the general format of a variety of
optional trace cache entries for reporting instruction execu
tion information.
Turning noW to the draWings, FIG. 1 depicts an exemplary
softWare debug environment illustrating a contemplated use
of the present invention. A target system T is shoWn con
taining an embedded processor device 102 according to the
present invention coupled to system memory 106. The
embedded processor device 102 incorporates a processor
core 104, a trace cache 200 (FIG. 2), and a debug port 100.
Although not considered critical to the invention, the
embedded processor device 102 may incorporate additional
circuitry (not shoWn) for performing application speci?c
functions, or may take the form of a stand-alone processor
TCK, the test mode select signal TMS, the test data input
signal TDI and the test data output signal TDO provided to
and driven by a J TAG Test Access Port (TAP) controller 204
are conventional JTAG support signals and knoWn to those
entry set for reporting softWare performance pro?ling infor
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENT
provides user control for selectively activating capture of
softWare performance pro?ling data. Other features enabled
by the trace control circuitry 218 include programmability of
synchroniZation address generation and user speci?ed trace
records, as discussed in greater detail beloW.
At a minimum, only the conventional JTAG pins need be
present invention;
passing according to a second embodiment of the invention;
FIG. 6A illustrates performance pro?le counter sequences
as Will become apparent to those skilled in the art, and the
various processor device 102 components described beloW
are shoWn for purposes of illustrating the bene?ts associated
“enhanced” embodiment of the debug port 100 adds the
command acknoWledge signal CMDACK, the break
request/trace capture signal BRTC, the stop transmit signal
STOPTX, and the trigger signal TRIG to the standard JTAG
interface. The additional signals alloW for pinpoint accuracy
55
of external breakpoint assertion and monitoring, triggering
of external devices in response to internal breakpoints, and
elimination of status polling of the JTAG serial interface.
These “sideband” signals offer extra functionality and
improve communications speeds for the debug port 100.
These signals also aid in the operation of an optional parallel
port 214 provided on special bond-out versions of the
disclosed embedded processor device 102.
The JTAG TAP controller 204 accepts standard JTAG
serial data and control via the conventional JTAG signals.
65
When a DEBUG instruction has been Written to the JTAG
instruction register, a serial debug shifter 212 is connected to
the JTAG test data input signal TDI and test data output
6,154,857
5
6
signal TDO, such that commands and data can then be
loaded into and read from debug registers 210. In the
mance pro?ling and other trace information. Additional
information, such as task identi?ers and trace capture stop/
start information, can also be placed in the trace cache 200.
The contents of the trace cache 200 are provided to eXternal
hardWare, such as the host system H, via either serial or
disclosed embodiment of the invention, the debug registers
210 include tWo debug registers for transmitting (TXi
DATA register) and receiving (RXiDATA register) data, an
instruction trace con?guration register (ITCR), and a debug
control status register (DCSR).
parallel trace pins 230. Alternatively, the target system T can
be con?gured to eXamine the contents of the trace cache 200
internally.
A control interface state machine 206 coordinates the
loading/reading of data to/from the serial debug shifter 212
and the debug registers 210. A command decode and pro
cessing block 208 decodes commands/data and dispatches
them to processor interface logic 202 and trace debug
interface logic 216. In addition to performing other
functions, the trace debug interface logic 216 and trace
control logic 218 coordinate the communication of softWare
performance pro?ling and other trace information from the
FIG. 4 provides a high-level ?oW chart of command
passing When using a standard JTAG interface. Upon enter
ing debug mode in step 400, the DEBUG instruction is
Written to the TAP controller 204 in step 402. Next, in step
404, the 38-bit serial value is shifted in as a Whole, With the
command pending ?ag set and desired data (if applicable,
15
trace cache 200 to the TAP controller 204. The processor
typically involves transferring a value betWeen a data reg
ister and a processor register or memory/IO location. After
the command has been completed, the processor 104 clears
interface logic 202 communicates directly With the proces
sor core 104, as Well as the trace control logic 218. As
described more fully beloW, parallel port logic 214 commu
the command pending ?ag and sets the command ?nished
nicates With a control interface state machine 206 and the
?ag, at the same time storing a value in the data ?eld if
debug registers 210 to perform parallel data read/Write
applicable. The entire 38-bit register is scanned to monitor
the command ?nished and command pending ?ags. If the
operations in optional bond-out versions of the embedded
processor device 102.
Before softWare performance pro?ling information is
communicated via the debug port 100 (using only conven
tional JTAG signals), the port 100 is enabled by Writing the
otherWise Zero) in the data ?eld. Control proceeds to step
406 Where the pending command is loaded/unloaded and the
command ?nished ?ag checked. Completion of a command
25
pending ?ag is reset to Zero and the ?nished ?ag is set to one,
the previous command has ?nished. The status of the ?ags
is captured by the control interface state machine 206. A
slave copy of the ?ags status is saved internally to determine
public JTAG instruction DEBUG into a JTAG instruction
register contained Within the TAP controller 204. As shoWn
if the neXt instruction should be loaded. The slave copy is
maintained due to the possibility of a change in ?ag status
betWeen TAP controller 204 states. This alloWs the processor
104 to determine if the previous instruction has ?nished
before loading the neXt instruction.
If the ?nished ?ag is not set as determined in step 408,
beloW, the JTAG instruction register of the disclosed
embodiment is a 38-bit register comprising a 32-bit data
?eld (debugidata[31:0]), a four-bit command ?eld to point
to various internal registers and functions provided by the
debug port 100, a command pending ?ag, and a command
control proceeds to step 410 and the loading/unloading of
?nished ?ag. It is possible for some commands to use bits 35
the 38-bit command is repeated. The command ?nished ?ag
from the debuLdata ?eld as a sub-?eld to eXtend the
is also checked. Control then returns to step 408. If the
number of available commands.
37
5
debugidata
?nished ?ag is set as determined in step 408, control returns
to step 406 for processing of the neXt command. DEBUG
mode is eXited via a typical JTAG process.
1
command
P
Returning to FIG. 2, the aforementioned optional side
O
band signals are utiliZed in the enhanced debug port 100 to
F
provide eXtra functionality. The optional sideband signals
include a break request/trace capture signal BRTC that can
JTAG Instruction Register
This JTAG instruction register is selected by toggling the
45 function as a break request signal or a trace capture enable
signal depending on the status of a bit set in the debug
control/status register. If the break request/trace capture
test mode select signal TMS. The test mode select signal
TMS alloWs the JTAG path of clocking to be changed in the
signal BRTC is set to function as a break request signal, it
is asserted to cause the processor 104 to enter debug mode
scan path, enabling multiple paths of varying lengths to be
(the processor 104 can also be stopped by scanning in a halt
command via the convention JTAG signals). If set to func
tion as a trace capture enable signal, asserting the break
used. Preferably, the JTAG instruction register is accessible
via a short path. This register is con?gured to include a
“soft” register for holding values to be loaded into or
received from speci?ed system registers.
Referring noW to FIG. 3, a simpli?ed block diagram
55
depicting the relationship betWeen the exemplary trace
cache 200 and other components of the embedded processor
device 102 according to the present invention is shoWn. In
one contemplated embodiment of the invention, the trace
cache 200 is a 128 entry ?rst-in, ?rst-out (FIFO) circular
cache. Increasing the siZe of the trace cache 200 increases
the amount of softWare performance pro?le and other
instruction trace information that can be captured, although
the amount of required silicon area may increase.
As described in more detail beloW, the trace cache 200 of
the disclosed embodiment of the invention stores a plurality
of 20-bit (or more) trace entries, such as softWare perfor
request/trace capture signal BRTC enables capturing of trace
information. Deasserting the signal turns trace capture off.
The signal takes effect on the neXt instruction boundary after
it is detected and is synchroniZed With the internal processor
clock. The break request/trace capture signal BRTC may be
asserted at any time.
The trigger signal TRIG is con?gured to pulse Whenever
an internal processor breakpoint has been asserted. The
trigger signal TRIG may be used to trigger an eXternal
65
capturing device such as a logic analyZer, and is synchro
niZed With the trace record capture clock signal TRACE
CLK. When a breakpoint is generated, the event is synchro
niZed With the trace capture clock signal TRACECLK, after
Which the trigger signal TRIG is held active for the duration
of trace capture.
6,154,857
8
7
The stop transmit signal STOPTX is asserted when the
processor 104 has entered DEBUG mode and is ready for
register interrogation/modi?cation, memory or I/O reads and
writes through the debug port 100. In the disclosed embodi
ment of the invention, the stop transmit signal STOPTX 5
re?ects the state of a bit in the debug control status register
(DCSR). The stop transmit signal STOPTX is synchronous
with the trace capture clock signal TRACECLK.
The command acknowledge signal CMDACK is
described in conjunction with FIG. 5, which shows simpli
?ed command passing in the enhanced debug port 100 of
FIG. 2. Again, to place the target system T into DEBUG
-continued
BIT
SYMBOL
DESCRIPTION/FUNCTION
12
TSRO
Sets or clears trace mode on DRO trap
11
1O
9
8
TRACE3
TRACE2
TRACE1
TRACEO
Enables
Enables
Enables
Enables
7
TRON
TCLK[2:O]
Trace
Trace
Trace
Trace
mode
mode
mode
mode
toggling
toggling
toggling
toggling
using
using
using
using
DR3
DR2
DR1
DRO
3
ITM
Trace on/off
Encoded divider ratio between internal processor
clock and TRACECLK
Sets internal or external (bond-out) instruction
2
TINIT
Trace initialization
1
TRIGEN
Enables pulsing of external trigger signal TRIG
10 6:4
tracing mode
mode, a DEBUG instruction is written to the TAP controller
204 in step 502. Control proceeds to step 504 and the
command acknowledge signal CMDACK is monitored by
following receipt of any legacy debug breakpoint;
the host system H to determine command completion status. 15
independent of the Debug Trap Enable function in
the DCSR
This signal is asserted high by the target system T simulta
neously with the command ?nished ?ag and remains high
until the next shift cycle begins. When using the command
acknowledge signal CMDACK, it is not necessary to shift
out the JTAG instruction register to capture the command
O
internal trace buffer or via the external (bond-out)
interface
Instruction Trace Con?guration Register (ITCR)
Another debug register, the debug control/status register
CMDACK transitions high on the next rising edge of the test
clock signal TCK after the command ?nished ?ag has
changed from Zero to one. When using the enhanced JTAG
signals, a new shift sequence (step 506) is not started by the
(DCSR), provides an indication of when the processor 104
has entered debug mode and allows the processor 104 to be
forced into DEBUG mode through the enhanced JTAG
interface. As shown in the following table, the DCSR also
host system H until the command acknowledge signal
CMDACK pin has been asserted high. The command
acknowledge signal CMDACK is synchronous with the test
enables miscellaneous control features, such as: forcing a
ready signal to the processor 104, controlling memory
clock signal TCK. The test clock signal TCK need not be
30
access space for accesses initiated through the debug port,
disabling cache ?ush on entry to the DEBUG mode, the TX
and RX bits, the parallel port 214 enable, forced breaks,
forced global reset, and other functions. The ordering or
CMDACK response.
presence of the various bits in either the ITCR or DCSR is
not considered critical to the operation of the invention.
OPERATING SYSTEM/APPLICATION
COMMUNICATION VIA THE DEBUG PORT 100
35
Also included in debug register block 210 is an instruction
BIT
trace con?guration register (ITCR). This 32-bit register
provides for the enabling/disabling and con?guration of
software performance pro?le and instruction trace debug
SYMBOL
31:12 Reserved
11
TX
available in the TXLDATA register
including various levels of tracing, trace synchroniZation
force counts, trace initialiZation, instruction tracing modes,
10
RX
Indicates that data has been received from the host
and placed in the RXLDATA register
clock divider ratio information, as well as additional func
9
8
tions shown in the following table. The ITCR is accessed
DISFLUSH
SMMSP
accesses initiated through the Debug Port 100
210, or via a reserved instruction.
7
STOP
Indicates whether the processor 104 is in DEBUG
6
FRCRDY
5
BRKMODE
Forces the ready signal RDY to the processor 104 to
be pulsed for one processor clock; useful when it is
apparent that the processor 104 is stalled waiting for
a ready signal from a non-responding device
Selects the function of the break request/trace
4
DBTEN
mode (equivalent to stop transmit signal STOPTX
5O
SYMBOL
DESCRIPTION/FUNCTION
31:30 Reserved
29
RXINTEN
28
TXINTEN
Reserved
Enables interrupt when RX bit is set
Enables interrupt when TX bit is set
27
Indicates that the target system T is ready to
transmit data to the host system H and the data is
available in the TXLDATA register
Indicates that data has been received from the host
26
TX
RX
capture signal BRTC (break request or trace capture
on/off)
55
Disables level 1 tracing
Disables level 0 tracing
23
DISCSB
Disables current segment base trace record
22:16 TSYNC[6:O] Sets the maximum number of Branch Sequence
trace records that may be output by the trace control
block 218 before a synchronizing address record is
forced
15
14
13
DISL1TR
DISLOTR
TSR3
TSR2
TSR1
Sets or clears trace mode on DR3 trap
Sets or clears trace mode on DR2 trap
Sets or clears trace mode on DR1 trap
Enables entry to debug mode or toggle trace mode
enable on a trap/fault via processor 104 registers
DRO-DR7 or other legacy debug trap/fault
mechanisms
3
2
and placed in the RXLDATA register
25
24
Disables cache ?ush on entry to DEBUG mode
Controls memory access space (normal memory
space/system management mode memory) for
5
is the case with the other registers of the debug register block
BIT
DESCRIPTION/FUNCTION
Reserved
Indicates that the target system T is ready to
transmit data to the host system H and the data is
functions. Numerous such functions are contemplated,
through a JTAG instruction register write/read command as
Global enable for instruction tracing through the
0
?nished ?ag status. The command acknowledge signal
clocked at all times, but is ideally clocked continuously
when waiting for a command acknowledge signal
GTEN
6O 1
PARENB
DSPC
Enables parallel port 214
Disables stopping of internal processor clocks in the
Halt and Stop Grant states
FBRK
Forces processor 104 into DEBUG mode at the next
instruction boundary (equivalent to pulsing the
external BRTC pin)
0
65
FRESET
Forces global reset
Debug Control/Status Register (DCSR)
When in cross debug environment such as that of FIG. 1,
it is desirable for the parent task running on the target system
6,154,857
9
10
T to send information to the host platform H controlling it.
This data may consist, for example, of a character stream
In the disclosed embodiment of the invention, a parallel
port 214 is also provided in an optional bond-out version of
the embedded processor device 102 to provide parallel
command and data access to the debug port 100. This
interface provides a 16-bit data path that is multiplexed With
the trace pad interface port 220. More speci?cally, the
parallel port 214 provides a 16-bit Wide bi-directional data
bus (PDATA[15:0]), a 3-bit address bus (PADR[2:9]), a
from a printf() call or register information from a Task’s
Control Block (TCB). One contemplated method for trans
ferring the data is for the operating system to place the data
in a knoWn region, then via a trap instruction cause DEBUG
mode to be entered.
Via debug port 100 commands, the host system H can
then determine the reason that DEBUG mode Was entered,
and respond by retrieving the data from the reserved region.
HoWever, While the processor 104 is in DEBUG mode,
normal processor execution is stopped. As noted above, this
is undesirable for many real-time systems.
This situation is addressed according to the present inven
tion by providing tWo debug registers in the debug port 100
for transmitting (TXiDATA register) and receiving (RXi
parallel debug port read/Write select signal (PRW), a trace
10
valid signal TV and an instruction trace record output clock
TRACECLOCK (TC). Although not shared With the trace
pad interface port 220, a parallel bus request/grant signal
pair PBREQ/PBGNT (not shoWn) are also provided. The
parallel port 214 is enabled by setting a bit in the DCSR.
15
Serial communications via the debug port 100 are not
disabled When the parallel port 214 is enabled.
DATA register) data. These registers can be accessed using
the soft address and JTAG instruction register commands.
As noted, after the host system H has Written a debug
instruction to the JTAG instruction register, the serial debug
shifter 212 is coupled to the test data input signal TDI line
and test data output signal TDO line.
22
21
2O
TV
TC
PRW
19
16
PADR[2:0]
0
PDATA [15:0]
When the processor 104 executes code causing it to
transmit data, it ?rst tests a TX bit in the ITCR. If the TX bit
is set to Zero then the processor 104 executes a processor
instruction (either a memory or I/ O Write) to transfer the data
25
to the TXiDATA register. The debug port 100 sets the TX
bit in the DCSR and ITCR, indicating to the host system H
that it is ready to transmit data. Also, the STOPTX pin is set
Bond-Out Pins/Parallel Port 214 Format
The parallel port 214
doWnloads/uploads to and
HoWever, the parallel port
communications With the
high. After the host system H completes reading the transmit
data from the TXiDATA register, the TX bit is set to Zero.
ATXINTEN bit in the ITCR is then set to generate a signal
is primarily intended for fast
from target system T memory.
214 may be used for all debug
target system T Whenever the
processor 104 is stopped. The serial debug signals (standard
or enhanced) are used for debug access to the target system
T When the processor 104 is executing instructions.
to interrupt the processor 104. The interrupt is generated
only When the TX bit in the ITCR transitions to Zero. When
the TXINTEN bit is not set, the processor 104 polls the
In a similar manner to the J TAG standard, all inputs to the
ITCR to determine the status of the TX bit to further transmit 35 parallel port 214 are sampled on the rising edge of the test
clock signal TCK, and all outputs are changed on the falling
data.
edge of the test clock signal TCK. In the disclosed
embodiment, the parallel port 214 shares pins With the trace
When the host system H desires to send data, it ?rst tests
a RX bit in the ITCR. IF the RX bit is set to Zero, the host
pad interface 220, requiring parallel commands to be initi
system H Writes the data to the RXiDATA register and the
ated only While the processor 104 is stopped and the trace
pad interface 220 is disconnected from the shared bus.
RX bit is set to one in both the DCSR and ITCR. A RXINT
bit is then set in the ITCR to generate a signal to interrupt
the processor 104. This interrupt is only generated When the
RX in the ITCR transitions to one. When the RXINTEN bit
The parallel bus request signal PBREQ and parallel bus
grant signal PBGNT are provided to expedite multiplexing
is not set, the processor 104 polls the ITCR to verify the
of the shared bus signals betWeen the trace cache 200 and the
status of the RX bit. If the RX bit is set to one, the processor 45 parallel port 214. When the host interface to the parallel port
instruction is executed to read data from the RXiDATA
214 determines that the parallel bus request signal PBREQ
register. After the data is read by the processor 104 from the
is asserted, it begins driving the parallel port 214 signals and
RXiDATA register the RX bit is set to Zero. The host
asserts the parallel bus grant signal PBGNT.
When entering or leaving DEBUG mode With the parallel
port 214 enabled, the parallel port 214 is used for the
system H continuously reads the ITCR to determine the
status of the RX bit to further send data.
This technique enables an operating system or application
to communicate With the host system H Without stopping
processor 104 execution. Communication is conveniently
achieved via the debug port 100 With minimal impact to
processor state save and restore cycles. The parallel bus
request signal PBREQ is asserted immediately before the
beginning of a save state sequence penultimate to entry of
DEBUG mode. On the last restore state cycle, the parallel
on-chip application resources. In some cases it is necessary 55 bus request signal PBREQ is deasserted after latching the
to disable system interrupts. This requires that the RX and
TX bits be examined by the processor 100. In this situation,
Write data. The parallel port 214 host interface responds to
the communication link is driven in a polled mode.
its parallel port drivers and deasserting the parallel bus grant
signal PBGNT. The parallel port 214 then enables the debug
trace port pin drivers, completes the last restore state cycle,
asserts the command acknowledge signal CMDACK, and
parallel bus request signal PBREQ deassertion by tri-stating
PARALLEL INTERFACE TO DEBUG PORT 100
Some embedded systems require instruction trace to be
examined While maintaining I/O and data processing opera
tions. Without the use of a multi-tasking operating system,
a bond-out version of the embedded processor device 102 is
preferable to provide the trace data, as examining the trace
cache 200 via the debug port 100 requires the processor 104
to be stopped.
returns control of the interface to trace control logic 218.
When communicating via the parallel port 214, the
65
address pins PADR[2:0] are used for selection of the ?eld of
the JTAG instruction register, Which is mapped to the 16-bit
data bus PDATA[15 :0] as shoWn in the folloWing table:
6,154,857
11
PADR[2:0]
12
Similarly, the store instruction trace cache record com
mand SITCR is used to retrieve and store (in the EAX
register) an indexed record from the trace cache 200. The
contents of the ECX register of the processor core 104 are
used as an offset that is added to the trace cache pointer
ITREC.PTR to create an index into the trace cache 200. The
Data Selection
00 0
No selection (null operation)
0 0 1
4-bit command register; command driven on PDATA[3:0]
0 1 0
High 16-bits of debugidata
0 1 1
100-111
Low 16-bits of debugidata
Reserved
ECX register is post-incremented while the trace cache
pointer ITREC.PTR is unaffected, such that:
10
It is not necessary to update both halves of the debugi
data [31:0] register if only one of the halves is being used
(e.g., on 8-bit I/O cycle data writes). the command pending
?ag is automatically set when performing a write operation
to the four-bit command register, and is cleared when the
command ?nished ?ag is asserted. The host system H can
15
monitor the command acknowledge signal CMDACK to
determine when the ?nished ?ag has been asserted. Use of
the parallel port 214 provides fully visibility of execution
history, without requiring throttling of the processor core
104. The trace cache 200, if needed, can be con?gured for
20
maintained while a task is being traces. Traditionally, the use
of an in-circuit emulator has necessitated that the processor
be stopped before the processor’s state and trace can be
of I/O data processing.
bandwidth matching issues.
25
Additionally, the trace cache 200 is very useful when used
with equipment in the ?eld. If an unexpected system crash
occurs, the trace cache 200 can be examined to observe the
execution history leading up the crash event. When used in
portable systems or other environments in which power
In the disclosed embodiment of the invention, the opera
tion of all debug supporting features, including the trace
cache 200, can be controlled through the debug port 100 or
via processor instructions. These processor instructions may
Extending an operating system to support on-chip trace
has certain advantages within the communications industry.
It enables the system I/O and communication activity to be
examined (unlike ptrace()). This disrupts continuous support
use as a buffer to the parallel port 214 to alleviate any
OPERATING SYSTEM AND DEBUGGER
INTEGRATION
Numerous variations to the format of the LITCR and SITCR
commands will be evident to those skilled art.
consumption is a concern, the trace cache 200 can be
30
disabled as necessary via power management circuitry.
be from a monitor program, target hosted debugger, or
conventional pod-wear. The debug port 100 performs data
EXEMPLARY TRACE RECORD FORMAT
moves which are initiated by serial data port commands
rather than processor instructions.
Operation of the processor core 104 from conventional
pod-space is very similar to operating in DEBUG mode
from a monitor program. All debug operations can be
In the disclosed embodiment of the invention, an instruc
tion trace record is 20 bits wide and consists of two ?elds,
controlled via processor instructions. It makes no difference
whether these instructions come from pod-space or regular
memory. This enables an operating system to be extended to
35
TCODE (Trace Code) and TDATA (Trace Data), as well as
a valid bit V. The TCODE ?eld is a code that identi?es the
type of data in the TDATA ?eld. The TDATA ?eld contains
software performance pro?le and other trace information
used for debug purposes.
40
include additional debug capabilities.
Of course, via privileged system calls such a ptrace(),
20
operating systems have long supported debuggers. However,
the incorporation of an on-chip trace cache 200 now enables
an operating system to offer software performance pro?ling
45
19
V
15
TCODE (Trace Code)
0
TDATA (Trace Data)
and instruction trace capabilities. In a debug environment
according to the present invention, it is possible to enhance
an operating system to support limited trace without the
incorporation of an “external” logic analyzer or in-circuit
emulator.
Instruction Trace Record Format
50
Examples of instructions used to support internal loading
and retrieving of trace cache 200 contents include a load
instruction trace cache record command LITCR and a store
instruction trace cache record command SITCR. The com
mand LITCR loads an indexed record in the trace cache 200,
In one contemplated embodiment of the invention, the
embedded processor device 102 reports performance pro?l
ing data as well as data corresponding to ten other trace
codes as set forth in the following table:
55
as speci?ed by a trace cache pointer ITREC.PTR, with the
TCODE
contents of the EAX register of the processor core 104. The
#
TCODE Type
TDATA
trace cache pointer ITREC.PTR is pre-incremented, such
that the general operation of the command LITCR is as
0000
Missed Trace
Not Valid
0001
Conditional
Branch
Branch Target
Previous
Segment Base
Current
Segment Base
Interrupt
Contains Branch Sequence
follows:
60
0010
0011
0100
In the event that the instruction trace record (see description
of trace record format below ) is smaller that the EAX
record, only a portion of the EAX register is utilized.
65
0101
Contains Branch Target Address
Contains Previous Segment Base Address
and Attributes
Contains Current Segment Base Address
and Attributes
Contains Vector Number of Exception or
Interrupt
6,154,857
14
but is reset to zero following a stop trigger event. The stop
trigger event also causes the value of the second counter to
be placed in the trace cache 200. This second counter value
is useful for obtaining the frequency of occurrence of a
-continued
TCODE
#
TCODE Type
TDATA
0110
Trace
Contains Address of Most Recently Executed
Synchronization
Instruction
0111
Multiple Trace
Contains 2nd or 3rd Record of Entry With
procedure of interest, whereas the ?rst counter provides
information about the procedure’s execution time.
Referring to FIG. 6B, the general format of a trace cache
200 entry set for reporting software performance pro?ling
Multiple Records
1000
Trace Stop
Contains Instruction Address Where Trace
Capture Was Stopped
1001
1010
User Trace
Performance
Pro?le
10
Contains User Speci?ed Trace Data
Contains Performance Pro?ling Data
The trace cache 200 is of limited storage capacity; thus a
certain amount of “compression” in captured trace data is
desirable. In capturing trace data, the following discussion
assumes that an image of the program being traced is
15
available to the host system H. If an address can be obtained
from a program image (Object Module), then it is not
provided in the trace data. Preferably, only instructions
which disrupt the instruction ?ow are reported; and further,
only those where the target address is in some way data
dependent. For example, such “disrupting” events include
20
information in accordance with the invention is shown. As
shown, the count value of the ?rst counter is placed in the
trace cache 200 using a 16-bit value with a TCODE=1010
trace entry. This TCODE=1010 trace entry may be followed
by a TCODE=0111 entry pair containing a 32-bit count
value re?ecting the value of the second counter.
In one embodiment of the invention, the counter fre
quency (i.e., resolution) of the ?rst and second counters is
programmable. Such programmability may allow for better
accuracy when pro?ling very low frequency or high fre
quency events. For example, the following table depicts two
alternate and programmable accumulation frequencies for
the counters:
call instructions or unconditional branch instructions in
which the target address is provided from a data register or
25
other memory location such as a stack.
As indicated in the preceding table, other trace informa
tion that can be captured includes: the target address of a trap
or interrupt handler; the target address of a return instruc
tion; a conditional branch instruction having a target address
Maximum
Maximum
Counter
Duration:
Counter
Duration:
(4x clock scaling)
16-bit
32-bit
60.6 ns/8 cycles
242 ns/32 cycles
4 ms
15.9 ms
260 seconds
1,040 seconds
Counter Frequency
(@ 33 MHZ
Timing
Resolution
bus speed)
1/2 bus speed
30 Vs bus speed
which is data register dependent (otherwise, all that is
needed is a 1-bit trace indicating if the branch was taken or
When entering a privileged level ring zero or ring one, it
not); and, most frequently, addresses from procedure
returns. Other information, such as task identi?ers and trace
capture stop/start information, can also be placed in the trace
35
eliminated from the measured pro?ling values. Two further
support features may also be incorporated, including a
means of enabling/disabling counting and also simulta
neously resetting both count values. This aspect of the
40
switching occurring during a procedure (within a single
task) being monitored. Via a periodic interrupt handler, it is
cache 200. The precise contents and nature of the trace
records are not considered critical to the invention.
Referring now to FIG. 6A, exemplary performance pro?le
counter sequences are illustrated. In a system according to
the present invention, trigger control registers 219 are con
disclosed embodiment invention aids with task context
?gured to start and stop a counter that measures lapsed time
of execution for speci?ed procedures. Although the precise
also possible to examine procedures one at a time.
implementation of the trigger control registers 219 is not
Post-processing software, in conjunction with optional
considered critical to the invention, use of conventional
breakpoint registers (such as any of the debug registers
DRO—DR7 present in some prior microprocessor cores) to
perform the triggering functions is preferred. Further, it
45
50
Referring more speci?cally to FIG. 6A, a ?rst on-chip
?rst counter upon entry into a speci?ed procedure. A second
trigger control register 21% is used to stop the counter upon
55
?rst counter is started by the start trigger, it is initialized to
zero. When the stop trigger is generated as speci?ed by the
second trigger control register 219b, the count value of the
determined (within the limitations of the samples gathered).
test runs. The trace cache 200 allows statistical analysis to be
performed using as many samples as can be stored.
FIG. 7A illustrates an exemplary format for reporting
conditional branch events. The outcome of up to 15 branch
events can be grouped into a single trace entry. The 16-bit
TDATA ?eld (or “BFIELD”) contains 1-bit branch outcome
?rst counter is placed in the trace cache 200 using a
TCODE=1010 trace entry (FIG. 6B). Similar techniques can
at a time. By examining the trace cache 200, the minimum
average and maximum time spent in a procedure can be
Code coverage pro?ling capabilities can also be added to
show speci?c addresses executed and not executed during
trigger control register 219a is con?gured to trigger (start) a
entry into the prologue of the speci?ed procedure. When the
off-chip trace capture hardware, can be utilized to analyze
the pro?le data. Thus, the trace cache 200 is utilized to
gather information concerning the execution time spent in a
selected procedure. Generally, only one procedure is pro?led
should be noted that in the disclosed embodiment of the
invention normal instruction execution is not interrupted
while pro?ling information is gathered.
is also sometimes desirable to stop all counting (both
counters). This enables system calls and interrupts to be
60
trace entries, and is labeled as a TCODE=0001 entry. The
be used to measure other parameters such as interrupt
TDATA ?eld is initially cleared except for the left-most bit,
handler execution times. As described above, the trigger
control registers 219 can also be used to pulse the trigger
which is set to 1. As each new conditional branch is
encountered, a new one bit entry is added on the left and any
other entries are shifted to the right by one bit.
signal TRIG and to select program addresses where execu
tion trace is to start and stop.
In the disclosed embodiment of the invention, a second
counter is also used. The second counter runs continually,
65
Using a 128 entry trace cache 200 allows 320 bytes of
information to be stored. Assuming a branch frequency of
one branch every six instructions, the disclosed trace cache
6,154,857
15
16
200 therefore provides an effective trace record of 1,536
instructions. This estimate does not take into account the
occurrence of call, jump and return instructions.
The trace control logic 218 monitors instruction execution
via processor interface logic 202. When a branch target
address must be reported, information contained Within a
TDATA ?eld corresponding to a TCODE=0111 entry con
tains the high 16-bits of the previous segment base address,
While the associated TCODE=0111 entry contains the loW
15 or 4 bits (depending on Whether the instruction is
executed in real or protected mode). The TCODE=0111
entry also includes bits indicating the current segment siZe
(32-bit or 16-bit), the operating mode (real or protected), and
a bit indicating Whether paging is being utiliZed. Segment
current conditional branch TDATA ?eld is marked as com
plete by the trace control logic 218, even if 15 entries have
not accumulated. As shoWn in FIG. 7B, the target address (in
a processor-based device 102 using 32-bit addressing) is
then recorded in a trace entry pair, With the ?rst entry
information generally relates to the previous segment, not a
10
sor core 104.
(TCODE=0010) providing the high 16-bits of the target
address and the second entry (TCODE =0111) providing the
loW 16-bits of the target address. When a branch target
address is provided for a conditional jump instruction, no
1-bit branch outcome trace entry appears for the reported
branch.
USER SPECIFIED TRACE ENTRY
15
There are circumstances When an application program or
operating system may Wish to add additional information
into a trace stream. For this to occur, an x86 instruction is
STARTING AND STOPPING TRACE CAPTURE
Referring noW to FIG. 7C, it may be desirable to start and
current (target) segment. Current segment information is
obtained by stopping and examining the state of the proces
20
preferably provided Which enables a 16-bit data value to be
placed in the trace stream at a desired execution position.
The instruction can be implemented as a move to I/O space,
With the operand being provided by memory or a register.
stop trace gathering during certain sections of program
execution; for example, When a task context sWitch occurs.
When the processor core 104 executes this instruction, the
When trace capture is stopped, no trace entries are entered
user speci?ed trace entry is captured by the trace control
logic 218 and placed in the trace cache 200. As shoWn in
into the trace cache 200, nor do any appear on the bond-out
25
pins of the trace port 214. Different methods are contem
FIG. 7F, a TCODE=1001 entry is used for this purpose in the
plated for enabling and disabling trace capture. For example,
disclosed embodiment of the invention. This entry might
provide, for example, a previous or current task identi?er
an x86 command can be provided, or an existing x86
command can be utiliZed to toggle a bit in an I/O port
location. Alternatively, on-chip trigger control registers 219
can be con?gured to indicate the addresses Where trace
When a task sWitch occurs in a multi-tasking operating
30
system.
capture should start/stop. When tracing is halted, a trace
SYNCHRONIZATION OF TRACE DATA
entry (TCODE=1000, TCODE=0111) recording the last
When executing typical softWare on a processor-based
device 102, feW trace entries contain address values. Most
entries are of the TCODE=0001 format, in Which a single bit
indicates the result of a conditional operation. When exam
ining a trace stream, hoWever, data can only be studied in
relation to a knoWn program address. For example, starting
With the oldest entry in the trace cache 200, all entries until
an address entry are of little use. Algorithm synchroniZation
typically begins from a trace entry providing a target
address.
trace address is placed in the trace stream. When tracing is
resumed, a trace synchroniZation entry (TCODE=0110,
TCODE=0111) containing the address of the currently
executing instruction is generated.
It may be important to account for segment changes that
occur While tracing is stopped. This situation can be partially
resolved by selecting an option to immediately folloW a
35
40
TCODE=1000 entry With a current segment base address
entry (TCODE=0100, TCODE=0111), as shoWn in FIG. 7C.
A con?guration option is also desirable to enable a current
segment base address entry at the end of a trace prior to
entering Debug mode. By contrast, it may not be desirable
to provide segment base information When the base has not
changed, such as When an interrupt has occurred.
Referring to FIG. 7D, folloWing the occurrence of an
45
If the trace cache 200 contains no entries providing an
address, then trace analysis cannot occur. This situation is
rare, but possible. For this reason, a synchroniZation register
TSYNC is provided in the disclosed embodiment to control
the injection of synchroniZing address information. If the
synchroniZation register TSYNC is set to Zero, then trace
synchroniZation entries are not generated.
asynchronous or synchronous event such as an interrupt or
trap, a TCODE=0101 trace entry is generated to provide the
address of the target interrupt handler. HoWever, it is also
desirable to record the address of the instruction Which Was
interrupted by generating a trace synchroniZation (TCODE=
0110) entry immediately prior to the interrupt entry, as Well
as the previous segment base address (TCODE=0011). The
trace synchroniZation entry contains the address of the last
instruction retired before the interrupt handler commences.
SEGMENT CHANGES
TSYNC (Trace Synchronization)
55
Trace Entry SynchroniZation Entry Control Register
FIG. 7G depicts a trace synchroniZation entry. In
FIG. 7E illustrates a trace entry used to report a change in 60 operation, a counter register is set to the value contained in
the synchroniZation register TSYNC Whenever a trace entry
segment parameters. When processing a trace stream, trace
address values are combined With a segment base address to
containing a target address is generated. The counter is
decremented by one for all other trace entries. If the counter
determine an instruction’s linear address. The base address,
as Well as the default data operand siZe (32 or 16-bit mode),
reaches Zero, a trace entry is inserted (TCODE=0110) con
are subject to change. As a result, the TCODE=0011 and 65 taining the address of the most recently retired instruction
0111 entries are con?gured to provide the information
(or, alternatively, the pending instruction). In addition, When
necessary to accurately reconstruct instruction ?oW. The
a synchroniZing entry is recorded in the trace cache 200, it
6,154,857
17
18
2. The processor-based device of claim 1, the trace control
also appears on the trace pins 220 to ensure suf?cient
circuitry further comprising:
availability of synchronizing trace data for full-function ICE
equipment.
a second softWare pro?le counter coupled to the trace
memory,
Trace entry information can also be expanded to include
data relating to code coverage or execution performance.
the second softWare pro?le trigger control register further
con?gurable to initialiZe the second softWare pro?le
This information is useful, for example, for code testing and
performance tuning. Even Without these enhancements, it is
counter upon execution of the additional predetermined
softWare instruction(s), Wherein initialiZation of the
desirable to enable the processor core 104 to access the trace
cache 200. In the case of a microconrroller device, this
feature can be accomplished by mapping the the trace cache
200 Within a portion of I/O or memory space. Amore general
second softWare pro?le counter causes its count value
10
trace memory.
approach involves including an instruction Which supports
moving trace cache 200 data into system memory.
Thus, a processor-based device providing a ?exible, high
performance solution for furnishing softWare performance
pro?ling information has been described. The processor
based device incorporates an trace cache capable of captur
15
ing and providing the pro?ling information. Both serial and
parallel communication channels are provided for commu
nicating the pro?ling information to external devices. The
disclosed on-chip trace cache alleviates various of the band
Width and clock synchroniZation problems that arise in many
existing solutions, and also alloWs less expensive external
The foregoing disclosure and description of the invention
are illustrative and explanatory thereof, and various changes
in the siZe, shape, materials components, circuit elements
speci?ed interrupt handler.
5. The processor-based device of claim 1, Wherein the
incrementation frequency of the ?rst counter is program
mable betWeen at least tWo values.
25
prising:
a communication channel connected betWeen the trace
the illustrated circuitry and construction and method of
operation may be made Without departing from the spirit of
the invention.
What is claimed is:
1. An electronic processor-based device adapted to
execute a series of softWare instructions, the processor
memory and selected ones of the pins to provide for
transmission of softWare performance pro?ling infor
mation from the trace memory to external devices.
35
8. The processor-based device of claim 7, Wherein the
communication channel comprises a parallel interface
betWeen the trace cache and selected ones of the pins.
9. The processor-based device of claim 7, Wherein the
communication channel comprises a serial interface
betWeen the trace memory and selected ones of the pins.
ing:
a processor core; and
a trace memory coupled to the processor core for storing
softWare performance pro?ling information related to
softWare instructions executed by the processor core,
the trace memory comprising a series of storage
elements, each storage element adapted to store soft
Ware performance pro?ling information, the trace
memory being con?gured to maintain the most recent
6. The processor-based device of claim 1, Wherein the
trace memory is a ?rst-in, ?rst-out (FIFO) circular buffer.
7. The processor-based device of claim 1, further com
Wiring connections and contacts, as Well as in the details of
based device being provided With pins to permit connection
to external conductors, the processor-based device compris
3. The processor-based device of claim 1, Wherein the
predetermined softWare instruction(s) indicates entry into a
speci?ed softWare procedure, and Wherein the additional
predetermined softWare instruction(s) indicates an exit from
a speci?ed softWare procedure.
4. The processor-based device of claim 1, Wherein the
predetermined softWare instruction(s) indicates entry into a
speci?ed interrupt handler, and Wherein the additional pre
determined softWare instruction(s) indicates an exit from the
capture hardWare to be utiliZed When such hardWare is
employed.
immediately prior to initialiZation to be stored in the
45
10. The processor-based device of claim 9, Wherein the
serial interface is essentially compliant With a serial inter
face standard.
11. The processor-based device of claim 10, Wherein the
serial interface is essentially compliant With an the IEEE
1149.1-1990 JTAG interface standard.
12. A method for providing softWare performance pro?l
ing information With a processor-based device having a
information; and
trace control circuitry to gather the softWare performance
pro?ling information and to provide the softWare per
processor core that is executing a series of softWare
formance pro?ling information to the trace memory,
providing a trace memory Within the processor-based
device, the trace memory comprising a series of storage
instructions, comprising the steps of:
the trace control circuitry comprising:
elements adapted to store softWare performance pro?l
ing information, the trace memory being con?gured to
a ?rst softWare pro?le counter coupled to the trace
memory;
maintain the most recent information;
a ?rst softWare pro?le trigger counter register coupled
to the ?rst softWare pro?le counter, the ?rst softWare
55
related to softWare instructions executed by the pro
cessor core, the generating step comprising the steps of:
pro?le trigger control register con?gurable to acti
vate the ?rst softWare pro?le counter upon execution
providing a softWare pro?le counter;
activating the softWare pro?le counter upon execution
of a softWare predetermined instruction(s);
of a predetermined softWare instruction(s); and
a second softWare pro?le trigger control register
coupled to a ?rst softWare pro?le counter, the second
deactivating the softWare pro?le counter upon execu
tion of an additional predetermined softWare
softWare pro?le trigger control register con?gurable
to deactivate the ?rst softWare pro?le counter upon
execution of an additional predetermined softWare
instruction(s), the softWare performance pro?ling
instruction(s),
Wherein deactivation of the ?rst softWare pro?le
counter causes its count value to be stored in the
trace memory.
generating softWare performance pro?ling information
65
information comprising the count value of the soft
Ware pro?le counter folloWing its deactivation; and
storing the softWare performance pro?ling information in
the trace memory storage elements.
6,154,857
19
20
13. The method of claim 12, wherein the predetermined
software instruction(s) indicates entry into a speci?ed soft
Ware procedure, and Wherein the additional predetermined
an electronic processor-based device adapted to execute a
series of softWare instructions the processor-based
device comprising:
pins for connecting to external conductors;
softWare instruction(s) indicates an exit from a speci?ed
softWare procedure.
a processor core;
14. The method of claim 12, Wherein the predetermined
softWare instruction(s) indicates entry into a speci?ed inter
rupt handler, and Wherein the additional predetermined
softWare instruction(s) indicates an exit from the speci?ed
a trace memory coupled to the processor core for
interrupt handler.
storing softWare performance pro?ling information
related to softWare instructions executed by the pro
cessor core, the trace memory comprising a series of
10
15. The method of claim 12, Wherein the incrementation
frequency of the ?rst softWare pro?le counter is program
the trace memory being con?gured to maintain the
most recent information; and
mable betWeen at least tWo values.
trace control circuitry to gather the softWare perfor
16. The method of claim 12, Wherein the generating step
comprises:
15
a ?rst softWare pro?le counter coupled to the trace
memory;
upon execution of a predetermined softWare instruction
a ?rst softWare pro?le trigger counter register
coupled to the ?rst softWare pro?le counter, the
?rst softWare pro?le trigger control register con
?gurable to activate the ?rst softWare pro?le
(s), the softWare performance pro?ling information
comprising the retrieved count value.
17. The method of claim 16, further comprising the step
of initialiZing the softWare pro?le counter and repeating the
step of retrieving the count value to generate additional
18. The method of claim 12, further comprising the steps
mance pro?ling information and to provide the soft
Ware performance pro?ling information to the trace
memory, the trace control circuitry comprising:
providing a softWare pro?le counter; and
retrieving the count value of the softWare pro?le counter
softWare performance pro?ling information.
storage elements, the storage elements adapted to
store softWare performance pro?ling information,
counter upon execution of a predetermined soft
Ware instruction(s); and
25
a second softWare pro?le trigger control register
coupled to a ?rst softWare pro?le counter, the
of:
second softWare pro?le trigger control register
providing a communication channel from the trace
con?gurable to deactivate the ?rst softWare pro?le
memory to the debug system;
counter upon execution of an additional predeter
communicating the softWare performance pro?ling infor
mation from the trace memory to the debug system via
the communication channel.
19. The method of claim 18, Wherein the communication
channel utiliZed in the communication step is a serial
interface.
20. The method of claim 18, Wherein the communication
channel utiliZed in the communication step is a parallel
interface.
21. A softWare development environment for generating
and analyZing softWare performance pro?ling information,
comprising:
mined softWare instruction(s),
Wherein deactivation of the ?rst softWare pro?le counter
causes its count value to be stored in the trace memory;
and
35
a host system communicatively coupled to the pins of
the processor-based device for receiving softWare
performance pro?ling information from the trace
memory, the host system including softWare for
analyZing the softWare performance pro?le informa
tion.
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