SH6622A

SH6622A

Mask 4-bit Microcontroller

Features

SH6610C-based single-chip 4-bit microcontroller

ROM: 4K X 16 bits

RAM: 160 X 4 bits (Data memory)

Operation voltage: 2.2V - 6.0V (Typical 3.0V or 5.0V)

22 CMOS bi-directional I/O pins

4-level subroutine nesting (including interrupts)

One 8-bit auto re-load timer/counter

Warm-up timer for power on reset

Powerful interrupt sources:

- Internal interrupt (Timer0)

- External interrupts: PortB & PortC (Falling edge)

Oscillator (code option)

- X`tal oscillator: 32.768KHz ~ 4MHz

- Ceramic resonator: 400K ~ 4MHz

- RC oscillator: 400K ~ 4MHz

- External clock: 30K ~ 4MHz

Instruction cycle time:

- 4/32.768KHz (

≈ 122us) for 32.768KHz OSC clock

- 4/4MHz (= 1us) for 4MHz OSC clock

Two low power operation modes: HALT and STOP

Built-in watchdog timer (code option)

General Description

SH6622A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K program ROM, Timer and

I/O Port.

Pin Configuration

PORTE.2

PORTE.3

PORTF.1

PORTA.2

PORTA.3

T0

RESET

GND

PORTB.0

PORTB.1

PORTB.2

PORTB.3

PORTD.0

PORTD.1

10

11

12

13

14

7

8

9

1

2

3

4

5

6

28

27

22

21

20

26

25

24

23

19

18

17

16

15

PORTE.1

PORTE.0

PORTF.0

PORTA.1

PORTA.0

OSCI

OSCO

V

DD

PORTC.3

PORTC.2

PORTC.1

PORTC.0

PORTD.3

PORTD.2

1 V2.4

Block Diagram

SH6622A

OSCI OSCO

RESET

XTAL/RC

OPTION ROM

RC

OSC

CPU

WATCHDOG

TIMER (3-BIT)

8-BIT TIMER

(UP COUNTER)

TIMER

INTERRUPT

WDT TIME

OUT

PRESCALER

REG

ROM

4096 X 16BIT

DATA RAM

160 X 4BIT

PORTA (4 BITS)

PORTB (4 BITS)

PORTC (4 BITS)

PORTD (4 BITS)

PORTE (4 BITS)

PORTF (2 BITS)

PORTA [3:0]

PORTB [3:0]

PORTC [3:0]

PORTD [3:0]

PORTE [3:0]

PORTF [1:0]

Pin Description

GND V

DD

Pin No. Designation

27, 28, 1, 2 PE.0 - PE.3

26, 3 PF.0 - PF.1

24, 25, 4, 5 PA.0 - PA.3

6 T0

7

RESET

T0

I/O

I/O Bit programmable I/O

I/O Bit programmable I/O

I/O Bit programmable I/O

I

Descriptions

Timer Clock/Counter input pin (Schmitt Trigger input)

I Reset input (active low) (Schmitt Trigger input)

9 - 12 PB.0 - PB.3

13 - 16

17 - 20

PD.0 - PD.3

PC.0 - PC.3

21 V

DD

22 OSCO

23 OSCI

I/O Bit programmable I/O. Vector Interrupt (Active falling edge)

I/O Bit programmable I/O

I/O Bit programmable I/O. Vector Interrupt (Active falling edge)

P

O

Power supply pin

OSC output pin, There is a signal with a frequency of F

osc

/4 for RC mode

I OSC input pin, connected to crystal, ceramic or external resistor

2

SH6622A

Function Description

1. CPU

The CPU contains the following function blocks: Program

Counter, Arithmetic Logic Unit (ALU), Carry Flag,

Accumulator, Table Branch Register, Data Pointer (INX,

DPH, DPM, and DPL), and Stack.

1.1. PC (Program Counter)

The Program Counter is used to address the 4K program

ROM. It consists of 12-bits: Page Register (PC11), and

Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5,

PC4, PC3, PC2, PC1, PC0).

The program counter normally increases by one (+1) with every execution of an instruction except in the following cases:

(1) When executing a jump instruction (such as JMP, BA0,

BC),

(2) When executing a subroutine call instruction (CALL),

(3) When an interrupt occurs,

(4) When the chip is at the INITIAL RESET mode.

The program counter is loaded with data corresponding to each instruction. The unconditional jump instruction (JMP) can be set at 1-bit page register for higher than 2K.

1.2. ALU and CY

ALU performs arithmetic and logic operations. The ALU provides the following functions:

Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI,

SBI)

Decimal adjustment for addition/subtraction (DAA, DAS)

Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)

Decision (BA0, BA1, BA2, BA3, BAZ, BC)

Logic Shift (SHR)

The Carry Flag (CY) holds the ALU overflow, which the arithmetic operation generates. During an interrupt servicing or call instruction, the carry flag is pushed into the stack and restored back from the stack by the RTNI instruction. It is unaffected by the RTNW instruction.

1.3. Accumulator

Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with ALU, data transfer between the accumulator and system register, or data memory can be performed.

1.4. Stack

A group of registers are used to save the contents of CY &

PC (11-0) sequentially with each subroutine call or interrupt.

It is organized in 13 bits X 4 levels. The MSB is saved for CY.

4 levels are the maximum allowed for subroutine calls and interrupts.

The contents of Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). Stack is operated on a first-in, last-out basis. This 4-level nesting includes both subroutine calls and interrupts requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4, and the bottom of stack will be shifted out.

2. ROM

The SH6622A can address up to 4096 X 16 bit of program area from $000 to $FFF.

Service routine as starting vector address.

Vector Address Area ($000 to $004)

The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address.

Address Instruction

$000H JMP instruction

$001H NOP

$002H JMP instruction

$003H NOP

$004H JMP instruction

Function

Jump to RESET service routine

Reserved

Jump to TIMER0 service routine

Reserved

Jump to PBC service routine

3

SH6622A

3. RAM

Built-in RAM consists of general-purpose data memory and system register. Direct addressing in one instruction can access d ata memory and system register.

The following is the memory allocation map:

$000 - $01F: System register and I/O.

$020 - $0BF: Data memory (160 X 4 bits).

The configuration of system Register

Address Bit3 Bit2 Bit1 Bit0 R/W

$00

$01

-

-

IET0

IRQT0

-

-

IEP

IRQP

R/W

R/W

Remarks

Interrupt enable flags

Interrupt request flags

$04 TL0.3 TL0.2 TL0.1 TL0.0 R/W Timer0 load/counter register low digit

$05 TH0.3 TH0.2 TH0.1 TH0.0 R/W Timer0 load/counter register high digit

$07 LPD3 LPD2 LPD1 LPD0 W

LPD Enable Control (LPD3 - 0):

1010: LPD Enable (Default);

0101: LPD Disable

$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA

$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB

$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC

$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD

$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE

$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W

$0F INX.3 INX.2 INX.1 INX.0 R/W

$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W

Table Branch Register

Pseudo index register

Data pointer for INX low nibble

$13 - $15

$16

$17

$1B

PA3OUT PA2OUT

PB3OUT PB2OUT

- -

PA1OUT

PB1OUT

PF1OUT

PA0OUT

PB0OUT

PF0OUT

W

W

W

W

W

Set PORTA to be output port

Set PORTB to be output port

Set PORTC to be output port

Set PORTD to be output port

Set PORTE to be output port

Set PORTF to be output port

Bit0:T0 signal edge;

Bit1: T0 signal source

Bit3: WDT time-out (write 1 only) $1E WDT - - - W

* System Register $00 - $12 (except $07H). Please refer to "SH6610C User’s manual".

4

SH6622A

Low Power Detection (LPD)

The LPD function is to monitor the supply voltage and applies an internal reset in the microcontroller at the time of battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated by software control.

High reliability is not required.

Power supply voltage V

DD

= 2.2 to 6.0 V

Operating ambient temperature T

A

= -20℃ to + 70℃

Functions of LPD Circuit

The LPD circuit has the following functions:

Generates an internal reset signal when V

DD

≤

V

LPD

.

Cancels the internal reset signal when V

DD

> V

LPD

.

Here, V

DD

: power supply voltage, V

LPD

: LPD detect voltage, it is about 1.6 - 1.7V and lower than V

DD

-MIN (2.2V).

LPD Control Register

The LPD circuit is controlled by software enable flag.

$07 LPD3 LPD2 LPD1 LPD0 W

Remark

LPD Enable Control (LPD3 - 0):

1010: LPD Enable (Default);

0101: LPD Disable

LPD3﹑ LPD2﹑ LPD1﹑ LPD0﹕ LPD Enable/Disable flag

5

System Register $16 - $1B

Address Bit3 Bit2 Bit1 Bit0 R/W

$16

$17

PA3OUT

PB3OUT

PA2OUT

PB2OUT

PA1OUT

PB1OUT

PA0OUT

PB0OUT

W

$1A PE3OUT PE2OUT PE1OUT PE0OUT W

$1B - - PF1OUT PF0OUT W

W

W

W

Remarks

Set PORTA to be output port

Set PORTB to be output port

Set PORTC to be output port

Set PORTD to be output port

Set PORTE to be output port

Set PORTF to be output port

SH6622A

Equivalent Circuit for a Single I/O Pin

V

DD

DATA D

DATA

Q

AND

WRITE

CK

SET

QB

RESET

DATA IN

I/O PIN

READ

CONTROL

D Q

PXXOUT

WRITE

CK RESET QB

OR

GND

RESET

PAXOUT, PBXOUT, PCXOUT, PDXOUT, PEXOUT (X = 0, 1, 2, 3), PFXOUT (X = 0, 1)

1: Use as an output buffer.

0: Use as an input buffer (Power on initial).

T0 & WDT

System Register $1C

Remark

$1C - - T0S T0E W

Bit0: T0 signal edge

Bit1: T0 signal source

T0E: T0 signal edge.

0: Increment on low-to-high transition T0 pin (Power on initial).

1: Increment on high-to-low transition T0 pin.

T0S: T0 signal source.

0: OSC 1/4 (Power on initial).

1: Transition on T0 pin.

6

SH6622A

TOE

T0

OSC/4

T0S

0

1

M

U

X

EOR

BUILT-IN RC

OSCILLATOR

TIMER0 (8 BITS)

3

TM0 [2:0]

WDT ENABLE

( USER OPTION )

WDT & WARM

UP COUNTER

3

WDT TIMEOUT

System Register $1E

$1E WDT - - - W

Remark

Bit3:WDT time-out bit (write one only)

The input clock of watchdog timer is generated by a built-in RC oscillator. So that the WDT will always run even in the STOP mode. SH6622A generates a RESET condition when watchdog is time-out. Watchdog can be enabled or disabled permanently by user option. To prevent it from time-out and generating a device RESET condition, you should write this bit as "1" before timing-out. The WDT has a time-out period of more than 7ms (V

DD

= 5V). If longer time-out periods are desired, a prescaler with a divide ratio of up to 1:2048 can be assigned to the WDT under software controlled by writing to the TM0 register.

Prescaler divide ratio (valid for V

DD

= 5V):

TM0.2 TM0.1 TM0.0

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 0

1:1

1:2

1:4

1:8

1:32

1:128

1:512

1:2048 (Power on initial)

Timer-out period

7ms

14ms

28ms

56ms

224ms

896ms

3,584ms

14,336ms

RC OSC

0.875ms

INTERNAL

SCALER_1

/8

WDT TIME

OUT PERIOD

7ms

/1

W D T

PRESCALER TM0

/2

/4 /8 /32 /128 /512 /2048

FINAL WDT

TIME OUT

PERIOD

7

4. Timer0

SH6622A has one 8-bit timer. The time/counter has the following features:

. 8-bit timer/counter

. Readable and writeable

. Automatic reloadable counter

. 8-prescaller scale is available

. Internal and external clock select

. Interrupt on overflow from $FF to $00

. Edge select for external event

Following is a simplified timer block diagram:

SH6622A

Fosc/4

T0C

SYSTEM CLOCK

PRE-SCALER

8-BIT COUNTER

T0

T0M

T0E

T0S

4.1. Configuration and Operation

Timer-0 consists of an 8-bit write-only timer load register

(TL0L, TL0H), and an 8-bit read-only timer counter (TC0L,

TC0H). The counter and load register both have low order digits and high order digits. The timer counter can be initialized by writing data into the timer load register (TL0L,

TL0H). Load register programming: Write the low-order digit first and then the high-order digit. The timer counter is loaded with the content of load register automatically when the high order digit is written or counter counts overflow from $FF to

$00.

Timer Load Register: Since the register H would control the physical READ and WRITE operation. Please follow these rules:

Read Operation:

High nibble first;

Low nibble followed.

Load Reg. L

8-bit timer counter

Latch Reg. L

Load Reg. H

Low nibble first;

High nibble to update the counter.

4.2. Timer0 Interrupt

The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to wake CPU from HALT mode.

8

SH6622A

4.3. Timer0 mode register

The timer can be programmed in several different prescaler ratios by setting Timer Mode register (TM0). The 8-bit counter counts prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown in table1. These mode registers select the input pulse sources into the timer.

Table 1. Timer 0 Mode Register ($02)

TM0.2 TM0.1 TM0.0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Prescaler Divide Ratio Ratio N

/2

11

/2

9

512

/2

7

128

/2

5

32

/2

3

8

/2

4

4

/2

1

2

/2

0

1

4.4. External Clock/Event T0 as Timer0 Source

When external clock/event input is used for TM0, it is synchronized with CPU system clock. Therefor the external source must follow certain constrains. The output from T0M multiplex is T0C. It is sampled by system clock in instruction frame cycle.

Therefore it is necessary for T0C to be high at least 2 t

OSC

and low at least 2 t

OSC

. When prescaler ratio selects /20, T0C is the same as the system clock input. Therefore the requirements are as follows:

T0H = T0CH = T0 high time

≥ 2 t

OSC

+ T

T0L = T0CL = T0 low time

≥ 2 t

OSC

+ T

When other prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical.

Then:

T0C high time = T0C low time =

N *

2

T0

Where

T0 = Timer0 input period

N = prescaler value

The requirement is , therefore:

N * T 0

2

≥ 2 t

OSC

+ T

4 * t

OSC

N

+ 2

Δ

T

The limitation is applied for T0 period time only. The pulse width is not limited by this equation. It is summarized as follows:

+

2

∆

T

N

9

SH6622A

5. Port Interrupt

PBC interrupt (PORTB & PORTC, 8bits) is falling edge active. It means that if an interrupt request (IEx is set to 1 and one port bit is high go low) is been touched and that the condition is the other port bits are high level. Only input port can generate interrupt.

6. System Clock and Oscillator

System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals.

Instruction cycle time

(1) 4/32.768KHz (

≈ 122us) for 32.768KHz system clock

(2) 4/4MHz (

≈ 1us) for 4MHz system clock

Oscillator

(1) Crystal oscillator: 32.768KHz - 4MHz.

C1

Crystal

32.768K ~ 4MHz

C1, C2 Setting :

Crystal 32.768KHz :

C1, C2 < 56p (V

DD

= 5V);

C1, C2 < 56p (V

DD

= 3V).

Crystal 4MHz :

C1, C2 < 33p (V

DD

= 5V);

C1, C2 < 10p (V

DD

= 3V).

C2

(2) Ceramic resonator: 400KHz - 4MHz.

C1

Ceramic

400K ~ 4MHz

C1, C2 Setting :

Ceramic 400KHz :

20p < C1, C2 < 470p (V

DD

= 5V);

20p < C1, C2 < 150p (V

DD

= 3V).

Ceramic 4MHz :

20p < C1, C2 < 100p (V

DD

= 5V);

C1, C2 < 10p (V

DD

= 3V).

C2

(3) RC oscillator: 400KHz - 4MHz.

V

DD

R

OSCI

OSCO

Fosc/4

(4) External input clock: 30KHz - 4MHz.

OSCI

External clock source

OSCO

10

SH6622A

Initial State

Hardware After power on reset

Program counter $000

CY Undefined

Data memory

System register

Undefined

Undefined

AC Undefined

Timer counter 0

Timer load register 0

WDT counter

WDT prescaler

I/O ports

LPD3 ~ 0

0

0

Input

1010 (Enable LPD)

T0S T0E 00

WDT 0

11

SH6622A

Instruction Set

All instructions are one cycle and one word instructions. The characteristic is memory-oriented operation.

Arithmetic and Logical Instruction

Accumulator Type

Mnemonic

ADC X (, B)

ADCM X (, B)

ADD X (, B)

ADDM X (, B)

SBC X (, B)

SBCM X (, B)

SUB X (, B)

SUBM X (, B)

EOR X (, B)

EORM X (, B)

OR X (, B)

ORM X (, B)

AND X (, B)

ANDM X (, B)

SHR

Instruction Code

00000 0bbb xxx xxxx

00000 1bbb xxx xxxx

00001 0bbb xxx xxxx

00001 1bbb xxx xxxx

00010 0bbb xxx xxxx

00010 1bbb xxx xxxx

00011 0bbb xxx xxxx

00011 1bbb xxx xxxx

00100 0bbb xxx xxxx

00100 1bbb xxx xxxx

00101 0bbb xxx xxxx

00101 1bbb xxx xxxx

00110 0bbb xxx xxxx

00110 1bbb xxx xxxx

11110 0000 000 0000

Function

AC

← Mx + AC + CY

AC, Mx

← Mx + AC + CY

AC

← Mx + AC

AC, Mx

← Mx + AC

AC

← Mx + -AC + CY

AC, Mx

← Mx + -AC + CY

AC

← Mx + -AC + 1

AC, Mx

← Mx + -AC + 1

AC

← Mx ⊕ AC

AC, Mx

← Mx ⊕ AC

AC

← Mx | AC

AC, Mx

← Mx | AC

AC

← Mx & AC

AC, Mx

← Mx & AC

0

→ AC [3]; AC [0] →CY;

AC shift right one bit

Flag Change

CY

CY

CY

CY

CY

CY

CY

CY

CY

Immediate Type

Mnemonic

ADI X, I

ADIM X, I

SBI X, I

SBIM X, I

EORIM X, I

ORIM X, I

ANDIM X, I

Instruction Code

01000 iiii xxx xxxx

01001 iiii xxx xxxx

01010 iiii xxx xxxx

01011 iiii xxx xxxx

01100 iiii xxx xxxx

01101 iiii xxx xxxx

01110 iiii xxx xxxx

Function

AC

← Mx + I

AC, Mx

← Mx + I

AC

← Mx + -I +1

AC, Mx

← Mx + -I + 1

AC, Mx

← Mx ⊕ I

AC, Mx

← Mx | I

AC, Mx

← Mx & I

Flag Change

CY

CY

CY

CY

* In the assembler ASM66 V1.0, EORIM mnemonic is EORI. However, EORI has the operation identical with EORIM. Same for the ORIM with respect to ORI, and ANDIM with respect to ANDI.

Decimal Adjustment

Mnemonic

DAA X

DAS X

Instruction Code

11001 0110 xxx xxxx

11001 1010 xxx xxxx

Function

AC; Mx

← Decimal adjustment for add.

AC; Mx

← Decimal adjustment for sub.

Flag Change

CY

CY

12

Transfer Instruction

Mnemonic

LDA X (, B)

STA X (, B)

LDI X, I

Control Instruction

Mnemonic

BAZ X

BNZ X

BC X

BNC X

BA0 X

BA1 X

BA2 X

BA3 X

Instruction Code

00111 0bbb xxx xxxx

00111 1bbb xxx xxxx

01111 iiii xxx xxxx

Instruction Code

10010 xxxx xxx xxxx

10000 xxxx xxx xxxx

10011 xxxx xxx xxxx

10001 xxxx xxx xxxx

10100 xxxx xxx xxxx

10101 xxxx xxx xxxx

10110 xxxx xxx xxxx

10111 xxxx xxx xxxx

CALL X 11000 xxxx xxx xxxx

RTNW H; L

RTNI

HALT

STOP

JMP X

TJMP

NOP

Where,

11010 000h hhh llll

11010 1000 000 0000

11011 0000 000 0000

11011 1000 000 0000

1110p xxxx xxx xxxx

11110 1111 111 1111

11111 1111 111 1111

AC Accumulator

-AC Complement of accumulator

CY

Mx

Carry flag

Data memory p

ST

ROM page = 0

Stack

AC

← Mx

Function

Mx

← AC

AC, Mx

← I

Function

PC

← X if AC = 0

PC

← X if AC ≠ 0

PC

← X if CY = 1

PC

← X if CY ≠ 1

PC

← X if AC (0) = 1

PC

← X if AC (1) = 1

PC

← X if AC (2) = 1

PC

← X if AC (3) = 1

ST

← CY; PC + 1

PC

← X (Not including p)

PC

←ST; TBR ← hhhh;

AC

← llll

CY; PC

← ST

PC

← X (Include p)

PC

← (PC11-PC8) (TBR) (AC)

No Operation

⊕

|

& bbb

TBR

SH6622A

Flag Change

Flag Change

CY

Logical exclusive OR

Logical OR

Logical AND

RAM bank = 000

Table Branch Register

13

Option

Code Option

1. OSC:

osc2 osc1 osc0

0 0 0

1 0 0

1 1 0

1 0 1

1 1 1

2. WDT_EN:

0: Enable (Default);

1: Disable.

OSC type

External (Default)

RC

X’tal 400K - 4MHz

Ceramic

X’tal 32.768KHz

SH6622A

14

Absolute Maximum Rating*

DC Supply Voltage . . . . . . . . . . . . . . .-0.3V to +7.0V

Input Voltage . . . . . . . . . . . . . . . -0.3V to V

DD

+ 0.3V

Operating Ambient Temperature . . . . -10℃ to +60℃

Storage Temperature . . . . . . . . . . . .-55℃ to +125℃

SH6622A

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics (V

DD

= 5.0V GND = 0V, T

A

= 25℃, F

OSC

= 4MHz, unless otherwise specified.)

Condition

Operating Voltage

Operating Current

V

DD

4.5 6 V

I

OP

1

Stand by Current (HALT) I

SB1

0.5

Stand by Current (STOP) I

SB2

1

µA

Input Low Voltage V

IL1

GND

All output pins unloaded,

LPD off (If LPD on, I

SB2X

= I

SB2

+ 3

µA)

WDT off (If WDT on, I

SB2X

= I

SB2

+ 15

µA)

0.2 X V

DD

V I/O ports, pins tri-state

Input Low Voltage

Input Low Voltage

Input High Voltage

Input High Voltage

Input High Voltage

Input Leakage Current

Input Leakage Current

Input Leakage Current

Input Leakage Current

Output High Voltage

Output Low Voltage

V

IL2

GND 0.15 X V

DD

V RESET , T0

V

IL3

GND 0.15 X V

DD

V OSCI (Driven by external clock)

V

IH1

0.8 X V

DD

V

DD

V I/O ports, pins tri-state

V

I

I

I

IH2

IL2

IL4

IL5

0.85 X V

-5

-3

-3

DD

V

IH3

0.85 X V

DD

I

IL1

-1

V

DD

V

V

DD

V OSCI (Driven by external Clock)

1 I/O ports, GND < V

I/O

< V

DD

1 5

µA

GND < V

RESET

< V

DD

1 3

µA

T0, GND < V

t0

< V

DD

1 3

µA

For OSCI

V

OH

V

DD

- 0.7 V

I/O ports, I

OH

= -10mA, V

DD

= 6.0V

OSCO

RC

, I

OH

= -0.7mA, V

DD

= 6.0V

V

OL

GND + 0.6 V

I/O ports, I

OL

= 20mA, V

DD

= 6.0V

OSCO

RC

, I

OL

= 1.6mA, V

DD

= 6.0V

15

SH6622A

AC Electrical Characteristics (V

DD

= 5.0V GND = 0V, T

A

= 25℃, F

OSC

= 4MHz, unless otherwise specified.)

Oscillator start time

Oscillator start time

T

OSC1

T

OSC2

1 s

Condition

X’tal Osc = 32.768KHz, V

DD

= 5.0V

20 ms Ceramic Osc = 400KHz, V

DD

= 5.0V

Oscillator start time T

OSC3

2 ms RC Osc = 400KHz, V

DD

= 5.0V

WDT period T

WDT

7 18 ms

DD

= 5.0V

Frequency stability (crystal)

Frequency variation(crystal)

∆ F/F

∆ F/F

Frequency stability(ceramic)

∆ F/F

Frequency Variation (RC)

∆ F/F

±

1

10

0.1

20

PPM Crystal oscillator: [F(5.0) - F(4.5)]/F(5.0)

PPM Crystal oscillator: C1 = C2 = 5 - 30P

%

%

Ceramic resonator Osc: [F(5.0) - F(4.5)]/F(5.0)

Include supply voltage and chip to chip variation

User Notice:

Max. Current into V

DD

= 50mA;

Max. Current out of V

SS

= 150mA

Max. Output current sunk by any I/O port = 25mA;

Max. Output current sourced by any I/O port = 20mA

Max. Output current sunk by all ports (A, B, C, D, E, F) = 50mA;

Max. Output current sourced by all ports (A, B, C, D, E, F) = 40mA

16

SH6622A

DC Electrical Characteristics

(V

DD

= 3.0V, GND = 0V, T

A

= 25℃, F

OSC

= 4MHz, unless otherwise specified)

Operating Voltage

Operating Current

Stand-by Current (HALT)

Stand-by Current (STOP)

Input Low Voltage

Input Low Voltage

Input Low Voltage

Input High Voltage

Input High Voltage

Input High Voltage

Input Leakage Current

Input Leakage Current

Input Leakage Current

Input Leakage Current

Output High Voltage

Output Low Voltage

Condition

V

DD

2.2

I

OP

0.7

All output pins unloaded

(Execute NOP instruction)

I

SB1

0.2 mA

I

SB2

V

IL1

GND

1 2

µA

0.2 X V

DD

V

All output pins unloaded,

LPD off (If LPD on, I

SB2X

= I

SB2

+ 3

µA)

WDT off (If WDT on, I

SB2X

= I

SB2

+ 5

µA)

I/O ports, pins tri-state

V

IL2

V

IL3

GND

GND

V

IH1

0.8 X V

DD

0.15 X V

DD

V RESET , T0

0.15 X V

DD

V

V

DD

V

OSCI (Driven by external clock)

I/O ports, pins tri-state

V

V

IH3

0.85 X V

DD

I

IL1

-1 1 I/O ports, GND < V

I/O

< V

DD

I

IL2

-5 5 GND < V

RESET

< V

DD

I

IL4

-3 µA T0, GND < V

t0

< V

DD

I

IL5

-3

µA

For OSCI

V

OH

V

DD

- 0.7 V

I/O ports, I

OH

= -7mA, V

DD

= 3V

OSCO

RC

, I

OH

= -0.7mA, V

DD

= 3V

V

IH2

OL

0.85 X V

DD

V

DD

V

V

DD

V OSCI (Driven by external Clock)

GND + 0.4 V

I/O ports, I

OL

= 8mA, V

DD

= 3V

OSCO

RC

, I

OL

= 1.0mA, V

DD

= 3V

AC Electrical Characteristics

(V

DD

= 3.0V, GND = 0V, T

A

= 25℃, F

OSC

= 4MHz, unless otherwise specified)

Oscillator start time

Oscillator start time

Oscillator start time

WDT period

Frequency stability (crystal)

Frequency variation (crystal)

Frequency stability (ceramic)

Frequency Variation (RC)

Condition

T

OSC1

T

OSC2

1 s Crystal Osc = 32.768KHz, V

DD

= 3.0V

35 ms Ceramic Osc = 400KHz, V

DD

= 3.0V

T

OSC3

5 ms RC Osc = 400KHz, V

DD

= 3.0V

T

WDT

7 18 ms = 3.0V

∆ F/F

∆ F/F

∆ F/F

∆ F/F

±

1

10

0.1

20

PPM Crystal oscillator: [F(3.0) - F(2.7)]/F(3.0)

PPM Crystal oscillator: C1 = C2 = 5 ~ 30P

%

%

Ceramic resonator OSC:[F(3.0) - F(2.7)]/F(3.0)

Include supply voltage and chip to chip variation

Operation frequency vs. I

SB1

I

SB1X

= (Frequency/4MHz) X I

SB1

Operation frequency vs. lOP

I

OPX

= (Frequency/4MHz) X I

OP

32K Max. Halt current

32KHz Halt current < 5uA@3V; (WDT is disabled)

17

AC Characteristics

T

CY

T

IW

T

IWH

T

IWL

Instruction cycle time

T0 input width

High pulse width

LOW pulse width

Timing Waveform

T0 Input Waveform

TiwH TiwL

SH6622A

1 122

(T

CY

+ 40)/N

1/2 t

IW

1/2 t

IW

µs ns ns ns

N = Prescaler divide ratio

T0

Tiw

RC OSCO Timing Waveform

Built-in RC Oscillator

RC - OSC

PORT

OSCO - RC

T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 T4 T5

T6

RESET

OSC

WDT

Built-in RC

Tosc1

(Tosc2, Tosc3)

Twdt

18

Typical RC oscillator Resistor vs. V

DD

: (for reference only)

SH6622A

F = 400KHz

480

460

440

420

400

2.0

4.0

V

DD

(Volts)

6.0

Typical RC oscillator Frequency vs. V

DD

: (for reference only)

45

40

35

30

25

2.0

410

400

390

380

370

360

350

2.0

3.0

V

DD

(Volts)

4.0

5.0

4200

4000

3800

3600

3400

3200

3000

2.0

F = 4MHz

3.0

V

DD

(Volts)

4.0

3.0

V

DD

(Volts)

4.0

5.0

5.0

Typical RC oscillator Resistor vs. Frequency: (for reference only)

R-F (V

DD

= 3.0V)

500

450

400

350

300

250

200

150

100

50

0

100 1000

F (KHz)

10000

19

Application Circuit (for reference only)

AP1:

(1) Operating voltage: 3.0V.

(2) Oscillator: Crystal 32.768KHz.

(3) For high reliability, C1 is better to be added.

(4) PORTA - F: I/O

47K

Ω

22K

V

DD

T0

RESET

C1

0.1

µ

GND

AP2

(1) Operating voltage: 5.0V.

(2) Oscillator: Ceramic resonator 400KHz.

(3) For high reliability, C1 is better to be added.

(4) T0 input timer clock / counter

(5) PORTA - F: I/O

T0

V

DD

47K

Ω

RESET

0.1

µ

C1

GND

AP3

(1) Operating voltage: 5.0V.

(2) Oscillator: RC 400KHz.

(3) For high reliability, C1 is better to be added.

(4) PORTA - E: I/O

V

DD

22KΩ

T0

47KΩ

RESET

C1

0.1µ

GND

OSCI

OSCO

PORTA

~

PORTF

OSCI

OSCO

PORTA

~

PORTF

OSCI

OSCO

PORTA

~

PORTF

470KΩ

1000pF

I/O

I/O

100P

100P

I/O

20p

20p

20

SH6622A

AP4

(1) PORTA - C: as scan KEYBOARD (32 keys)

(2) PORTD - F: I/O

Pull-high resistor

47K

Ω

I/O

PORTD

~

PORTF

PC0

PC1

PC2

PC3

PB0

PB1

PB2

PB3

PA0

PA1

PA2

PA3

V

DD

SH6622A

21

SH6622A

AP5 (Weight Scale)

(1) Operating voltage: 5.0V

(2) Oscillator: Ceramic resonator 4MHz

(3) Port A0: External interrupt input for ON/OFF switch

(4) Port E2, E3, F1, A2: S4 - S1 analog switch control signals that control Vil to be charged and discharged by both the reference voltage (Vref) and the amplified voltage (Vo). The charged and discharged times are determined by the values of C1, R4 and the threshold voltage of T

0

input pin and the ADC resolution could be up to 8 bit

(5) Other Ports: Sink seven-segment LED current directly. 0 - 199 can be displayed in this configuration

V

DD

V

DD

Load

Cell

Vi

R2

R1

R2

R5

R3

R3

R4

Vo

Vref

S1

S2

Instrumentation Amplifier

V o

= (1 + 2R

2

/R

1

) (R

4

/R

3

) V i

R6

47K

0.1u

Vi1

S3

C1 S4

100

Ω

S1

S2

S3

S4

3

4

5

6

7

1

2

10

11

8

9

12

13

14

PE2

PE3

PF1

PA2

PA3

T0

RESET

GND

PB0

PB1

PB2

PB3

PD0

PD1

PE1

PE0

PF0

PA1

PA0

OSCI

OSCO

V

DD

PC3

PC2

PC1

PC0

PD3

PD2

23

22

21

20

19

18

17

28

27

26

25

24

16

15

V

DD

ON/OFF

C

1

2

120P - 470P

XC1

C

120P - 470P a b c d e f g a b c d e f g a b c d e f g

22

AP6:

Reset Protection Circuit 1

V

DD

33K

10K

40K

RESET

RESET will be pulled to GND when V

DD

goes lower than Zener voltage + 0.7V.

AP7:

Reset Protection Circuit 2

V

DD

R1

10K

RESET

R2

40K

RESET will be pulled to GND when (V

DD

X

R1/(R1 + R2)) is lower than 0.7V

SH6622A

23

Bonding Diagram

PC3

V

DD

OSCO

OSCI

P

C

2

19

P

C

1

18

P

C

0

P

D

3

17 16

P

D

2

P

D

1

15 14

P

D

0

13

G

N

D

2

P

B

3

12

P

B

2

P

B

1

11 10

20

21

GND3

22

23

SH6622A

G

N

D

1

NC

24 25 26 27 28 1

P

A

0

P

A

1

P

F

0

P

E

0

P

E

1

P

E

2

2

P

E

3

3

P

F

1

4 5

P

A

2

P

A

3

8

7

6

T

0

P

B

0

9

GND

RESET

NOTE:

1. GND1, GND2 & GND3 BONDING TO GROUND.

2. SUBSTRATE CONNECTED TO GROUND.

Pad No Designation X Y Pad No Designation

GND1 164.40

SH6622A

X

unit:

µm

Y

6 T0

7

RESET

8 GND

700.60 -441.40

21 V

DD

-713.70

GND3 -717.05

22 OSCO -717.05

23 OSCI

GND2 213.75

24

SH6622A

Ordering Information

Part No. Package Packing

Tray

Tube

Tube

Q

S

T

L

M

N

V

W

X

D

F

H

J

K

Note:

(1) “-yyxxx”: “yy” means 2 bits option and “xxx” means 3 bits code seriary number. If the product is OTP type and in blank order, those bits should be none.

(2) The data after mark “/” in Part No. block is the package and packing information for ordering.

(3) The size of those package types are showed in “Package Information” (Page26 - Page27).

(4) Any other package or packing request, please refer to following table.

Package Packing

DIP

R

Normal package size and in tray packing

QFP

U

Normal package size and in tube packing

CHIP

CER-DIP

SKINNY

A

D

L

Normal package size and in tape & reel packing

Larger package size and in tray packing

Larger package size and in tube packing

PLCC

SOP

OTHER

GOOD DIE ON WAFER

SOJ

TO92

VSOP/TSOP

WAFER

TSSOP

B

T

S

Smaller package size and in tube packing

N

Larger package size and in tape & reel packing

Smaller package size and in tray packing

Smaller package size and in tape & reel packing

25

Package Information

DIP-28L Outline Dimensions

D

28

15

1

S

14

E

Base Plane

Mounting Plane

α

B

B

1 e

1 e

A

Symbol

A

A

1

A

2

B

B

1

Dimensions in inches

0.175 Max.

0.010 Min.

0.130

± 0.005

0.018 + 0.004

- 0.002

0.060 + 0.004

- 0.002 e

1

L

α

C

D

E

E

1

e

A

S

0.010 + 0.004

1.388 Typ. (1.400 Max.)

0.310

± 0.010

0.288

± 0.005

0.100

± 0.010

0.130

± 0.010

0

° ~ 15°

0.350

± 0.020

0.055 Max.

Dimensions in mm

4.45 Max.

0.25 Min.

3.30

± 0.13

0.46 + 0.10

- 0.05

1.52 + 0.10

- 0.05

0.25 + 0.10

35.26 Typ. (35.56 Max.)

7.87

± 0.25

7.32

± 0.13

2.54

± 0.25

3.30

± 0.25

0

° ~ 15°

8.89

± 0.51

1.40 Max.

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E

1

does not include resin fins.

3. Dimension S includes end flash.

SH6622A

unit: inches/mm

26

28 15 e

1

~ ~~

SH6622A

inches/mm

1 b 14

L

Detail F e

1

D s

Seating Plane e

D y

See Detail F

Symbol

A

A

1

A

2

b e e

1

H

E

L

L

E

S y

θ c

D

E

Dimensions in inches

0.112 Max.

0.004 Min.

0.098

± 0.005

0.016 + 0.004

- 0.002

0.010 + 0.004

0.713

0

± 0.020

0.331

± 0.010

0.050

± 0.006

0.429 NOM.

0.465

± 0.012

0.036

± 0.008

0.067

± 0.008

0.047 Max.

0.004 Max.

° ~ 10°

Dimensions in mm

2.85 Max.

0.10 Min.

2.49

± 0.13

0.41 + 0.10

- 0.05

0.25 + 0.10

18.11

± 0.51

8.41

± 0.25

1.27

± 0.15

10.90 NOM.

11.81

± 0.31

0.91

± 0.20

1.70

± 0.20

1.19 Max.

0.10 Max.

0

° ~ 10°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension e

1

is for PC Board surface mount pad pitch design only.

4. Dimension S includes end flash.

L

E

27

SH6622A

Data Sheet Revision History

Version Content Date

2.4 Add package and packing information in ordering information Jul. 2004

2.3

2.2

Change RC Frequency Variation to ±20%

Add Reset Protection Circuit (AP6 and AP7)

1.0 Original

Apr. 2002

Feb. 2002

Jul. 1999

28