RL78/G10 Datasheet
Datasheet
RL78/G10
R01DS0207EJ0100
Rev.1.00
Apr 15, 2013
RENESAS MCU
True Low Power Platform (as low as 46 µA/MHz), 2.0 to 5.5V Operation,
1 to 4 Kbyte Flash for General Purpose Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 2.0 to 5.5 V operation from a single supply
• Stop (RAM retained): 0.56 µA
• Operating: 46 µA /MHz
Extended-Function Timers
• Multi-function 16-bit timers: Up to 4 channels
• Interval timer: 12-bit, 1 channel (only for 16-pin product)
• 15 kHz watchdog timer : 1 channel
RL78-S1 Core
• Instruction execution: 78 % of instructions can be
executed in 1 to 2 clock cycles
• CISC architecture (Harvard) with 3-stage pipeline
• Multiply: 8 x 8 to 16-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 2 clock cycle
• 1-wire on-chip debug function
Rich Analog
• ADC: Up to 8 channels, 10-bit resolution,
3.4 µs conversion time
• Supports 2.4 V
• 1 x comparator (only for 16-pin product)
Main Flash Memory
• Density: 1 to 4 Kbyte
• Flash memory rewritable voltage: 4.5 to 5.5 V
RAM
• 128 to 512 Byte size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 20 MHz with +/-2 % accuracy over voltage (2.0 to
5.5 V) and temperature (-20 to +85°C)
• Pre-configured settings: 20 MHz, 10 MHz, 5 MHz,
2.5 MHz, and 1.25 MHz
Reset and Supply Management
• Selectable power-on reset (SPOR) generator
with 4 setting options
Safety Features
• Detects execution of illegal instruction
• Detects watchdog timer program loop
General Purpose I/O
• High-current (up to 20 mA per pin)
• Open-drain, internal pull-up support
External Interrupt
• External interrupt input: 4
• Key interrupt input: 6
Operating Ambient Temperature
• Standard: -40 to +85°C
Package Type and Pin Count
• SSOP: 10 and 16 pin
Multiple Communication Interfaces
• 1 x I2C master
2
• 1 x I C multi-master (only for 16-pin product)
• 1 x UART (7-, 8-bit)
• Up to 2 x CSI/SPI (7-, 8-bit)
* There is difference in specifications between every product.
Please refer to specification for details.
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RL78/G10
CHAPTER 1 OUTLINE
 ROM, RAM capacities
Flash ROM
RAM
10 pins
4 KB
512 B
−
R5F10Y47ASP
Note 2
2 KB
256 B
R5F10Y16ASP
R5F10Y46ASP
Note 2
1 KB
128 B
R5F10Y14ASP
R5F10Y44ASP
Note 2
Notes 1.
16-pin products only
2.
Under development
Remark
16 pins
The functions mounted depend on the product. See 1.6 Outline of Functions.
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RL78/G10
CHAPTER 1 OUTLINE
1.2 List of Part Number
Figure 1-1. Classification of Part Number
Part No. R 5 F 1 0 Y 1 7 A x x x S P #V0
Packaging style
#V0 : Tray
#X0 : Embossed Tape
Package type:
SP : SSOP, 0.65 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications, operating ambient temperature : -40 C to 85 C
ROM capacity:
4 : 1 KB
6 : 2 KB
7 : 4 KB
Pin count:
1 : 10-pin
4 : 16-pin
RL78/G10 group: 10Y
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Pin count
10 pins
16 pins
Package
Part Number
10-pin plastic LSSOP
R5F10Y16ASP#V0, R5F10Y16ASP#X0
(4.4 × 3.6 mm, 0.65mmpitch)
R5F10Y14ASP#V0, R5F10Y14ASP#X0
16-pin plastic SSOP
R5F10Y47ASP
Note
(4.4 × 5.0 mm, 0.65mmpitch)
R5F10Y46ASP
Note
R5F10Y44ASP
Note
Note Under development
Caution The part number represents the number at the time of publication.
Be sure to review the latest part number through the target product page in the Renesas Electronics
Corp.website.
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RL78/G10
CHAPTER 1 OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 10-pin products
• 10-pin plastic LSSOP (4.4 × 3.6)
P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01)
P125/KR1/RESET
P137/TI00/INTP0
VSS
VDD
1
2
3
4
5
10
9
8
7
6
P04/ANI3/TI01/TO01/KR5
P03/ANI2/TO00/KR4/(INTP1)
P02/ANI1/SCK00/SCL00/PCLBUZ0/KR3
P01/ANI0/SI00/RXD0/SDA00/KR2
P00/SO00/TXD0/INTP1
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
1.3.2 16-pin products
• 16-pin plastic SSOP (4.4 × 5.0)
P41/TI03/INTP2
1
16
P07/SDAA0/TO03/ANI6/SCK01
P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01)
P125/KR1/RESET
2
3
15
14
P06/SCLA0/INTP3/ANI5/SI01
P05/ANI4/TI02/TO02/SO01
P137/TI00/INTP0
4
5
6
13
12
11
P04/ANI3/TI01/TO01/KR5/IVREF0
P03/ANI2/TO00/KR4/(INTP1)/IVCMP0
7
8
10
9
P01/ANI0/SI00/RXD0/SDA00/KR2
P00/SO00/TXD0/INTP1
P122/X2/EXCLK/(INTP2)
P121/X1/(INTP3)
VSS
VDD
P02/ANI1/SCK00/SCL00/PCLBUZ0/KR3/VCOUT0
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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RL78/G10
CHAPTER 1 OUTLINE
1.4 Pin Identification
ANI0 to ANI6
: Analog Input
INTP0 to INTP3
: External Interrupt Input
KR0 to KR5
: Key Return
P00 to P07
: Port 0
P40, P41
: Port 4
P121, P122, P125
: Port 12
P137
: Port 13
PCLBUZ0
: Programmable Clock Output/ Buzzer Output
EXCLK
: External Clock Input
X1, X2
: Crystal Oscillator
IVCMP0
: Comparator Input
VCOUT0
: Comparator Output
IVREF0
: Comparator Reference Input
RESET
: Reset
RxD0
: Receive Data
SCK00, SCK01
: Serial Clock Input/Output
SCL00, SCLA0
: Serial Clock Output
SDA00, SDAA0
: Serial Data Input/Output
SI00, SI01
: Serial Data Input
SO00, SO01
: Serial Data Output
TI00 to TI03
: Timer Input
TO00 to TO03
: Timer Output
TOOL0
: Data Input/Output for Tool
TxD0
: Transmit Data
VDD
: Power Supply
VSS
: Ground
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RL78/G10
CHAPTER 1 OUTLINE
1.5 Block Diagram
1.5.1 10-pin products
PORT 0
5
P00 to P04
TAU0 (2 ch)
TI00 /TO00
ch00
TI01 /TO01
ch01
SAU0 (1 ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCL00
SDA00
IIC00
TOOL0
PORT 4
P40
PORT 12
P125
PORT 13
P137
Code flash: 2 KB
Buzzer/clock
output control
Interrupt
control
PCLBUZ0
Key return
6 ch
6
KR0 to KR5
Interrupt
control
2 ch
2
INTP0, INTP1
RL78-S1
RAM
256 B
8-/10-bit
A/D converter
4 ch
ANI0 to ANI3
Watchdog timer
Low-speed
on-chip
oscillator
On-chip
debugger
Clock generator
+
Reset generator
BCD
adjustment
Selectable
power-onreset
Low-speed
on-chip
oscillator
15 kHz
VDD
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Apr 15, 2013
RESET
High-speed
on-chip
oscillator
1.25 to 20
MHz
VSS
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RL78/G10
CHAPTER 1 OUTLINE
1.5.2 16-pin products
TAU0 (4 ch)
TI00 / TO00
ch00
TI01 / TO01
ch01
TI02 / TO02
ch02
TI03 / TO03
ch03
PORT 0
8
P00 to P07
PORT 4
2
P40, P41
PORT 12
3
P121, P122, P125
PORT 13
SAU0 (1 ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01
SCL00
SDA00
IIC00
Code flash: 4 KB
Buzzer/clock
output control
Interrupt
control
RL78-S1
RAM
512 B
On-chip
TOOL0
RESET
Clock generator
+
Reset generator
On-chip debugger
Main OSC
1 to 20 MHz
BCD
adjustment
SCLA0
SDAA0
IICA0
PCLBUZ0
Key return
6 ch
6
KR0 to KR5
Interrupt
control
4 ch
4
INTP0 to INTP3
8-/10-bit
A/D converter
8 ch
Watchdog timer
12-bit interval
timer
ANI0 to ANI6
Low-speed
on-chip
oscillator
X1 X2/EXCLK
Selectable
power-onreset
Low-speed
on-chip
oscillator
15 kHz
VDD
IVREF0
IVCMP0
VCOUT0
P137
High-speed
on-chip
oscillator
1.25 to 20
MHz
VSS
COMP
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RL78/G10
CHAPTER 1 OUTLINE
1.6 Outline of Functions
This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
Item
10-pin
R5F10Y16ASP
16-pin
R5F10Y14ASP
R5F10Y47ASP
R5F10Y46ASP
R5F10Y44ASP
Code flash memory
2 KB
1 KB
4 KB
2 KB
1 KB
RAM
256 B
128 B
512 B
256 B
128 B
Main
High-speed system
system
clock
X1, X2 (crystal/ceramic) oscillation, external
—
main system clock input (EXCLK):
clock
1 to 20 MHz: VDD = 2.7 to 5.5 V
1 to 5 MHz: VDD = 2.0 to 5.5 V
High-speed on-chip
• 1.25 to 20 MHz (VDD = 2.7 to 5.5 V)
oscillator clock
• 1.25 to 5 MHz (VDD = 2.0 to 5.5 V)
Low-speed on-chip oscillator
clock
15 kHz (TYP)
General-purpose register
8-bit register × 8
Minimum instruction execution
time
0.05 μs (20 MHz operation)
Instruction set
• Data transfer (8 bits)
• Adder and subtractor/logical operation (8 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation
(set, reset, test, and Boolean operation), etc.
I/O port
Timer
Total
8
14
CMOS I/O
6 (N-ch open-drain output (VDD tolerance): 2)
10 (N-ch open-drain output (VDD tolerance): 4)
CMOS input
2
4
16-bit timer
2 channels
4 channels
Watchdog timer
1 channel
12-bit interval timer
—
1 channel
Timer output
2 channels (PWM output: 1)
4 channels (PWM outputs: 3
Clock output/buzzer output
Note 1
)
1
2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation)
Comparator
—
1
8-/10-bit resolution A/D converter
4 channels
Serial interface
[10-pin products] CSI: 1 channel/simplified I C: 1 channel/UART: 1 channel
8 channels
2
2
[16-pin products] CSI: 2 channels/simplified I C: 1 channel/UART: 1 channel
2
I C bus
Vectored
interrupt
sources
—
1 channel
Internal
8
14
External
3
5
Key interrupt
6
Reset
•
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by selectable power-on-reset
Note 2
Internal reset by illegal instruction execution
Internal reset by data retention lower limit voltage
Selectable power-on-reset circuit
Detection voltage: 2.0 V/2.4 V/2.7 V/4.0 V
On-chip debug function
Provided
Power supply voltage
VDD = 2.0 to 5.5 V
Operating ambient temperature
TA = - 40 to + 85 °C
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RL78/G10
CHAPTER 1 OUTLINE
Notes 1.
The number of outputs varies, depending on the setting of channels in use and the number of the master
2.
The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction
(see 6.8.3 Operation as multiple PWM output function in the RL78/G10 User’s Manual).
execution not issued by emulation with the on-chip debug emulator.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Cautions 1. This chapter explains the electrical specifications of two products, the R5F10Y16ASP and the
R5F10Y14ASP.
2. Electrical specifications for the 16-pin products are T. B. D. because these products are under
development.
3. The RL78/G10 has an on-chip debug function, which is provided for development and evaluation. Do
not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
4. The pins mounted depend on the product. Refer to 2.1 Port Functions and 2.2.1 Functions for each
product in the RL78/G10 User’s Manual.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings
(TA = 25°C)
Parameter
Supply Voltage
Symbols
Conditions
Ratings
−0.5 to +6.5
VDD
Input Voltage
VI1
Output Voltage
VO1
Output current, high
IOH1
Output current, low
Operating ambient
Unit
V
−0.3 to VDD + 0.3
Per pin
IOL1
Note
V
−0.3 to VDD + 0.3
V
−40
mA
Total of all pins
P40
−40
mA
-140 mA
P00 to P04
−100
mA
40
mA
Per pin
Total of all pins
P40
40
mA
140 mA
P00 to P04
100
mA
TA
−40 to +85
°C
Tstg
−65 to +150
°C
temperature
Storage temperature
Note
Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. The reference voltage is VSS.
2.2 Oscillator Characteristics
2.2.1 On-chip oscillator characteristics
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
High-speed on-chip oscillator oscillation
clock frequency
Parameters
Conditions
fIH
MIN.
TYP.
MAX.
Unit
1.25
20
MHz
Notes 1, 2
High-speed on-chip oscillator oscillation
TA = -20 to +85°C
-2.0
+2.0
%
clock frequency accuracy
TA = -40 to -20°C
-3.0
+3.0
%
Low-speed on-chip oscillator oscillation
clock frequency
fIL
15
kHz
Note 3
Low-speed on-chip oscillator oscillation
-15
+15
%
clock frequency accuracy
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 2 of option byte (000C2H).
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
3.
This only indicates the oscillator characteristics.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
IOH1
Output current,
high
MIN.
Conditions
P00, P01, P02 to P04, P40
Per pin
Note 1
P40
Total
P00, P01, P02 to P04
TYP.
Total
Note 3
Note 3
-10.0
IOL1
P00 to P04, P40
P40
Total
P00 to P04
Total
Note 3
Note 3
mA
mA
2.7 V ≤ VDD < 4.0 V
-2.0
mA
2.0 V ≤ VDD < 2.7 V
-1.5
mA
4.0 V ≤ VDD ≤ 5.5 V
-50.0
mA
2.7 V ≤ VDD < 4.0 V
-10.0
mA
2.0 V ≤ VDD < 2.7 V
-7.5
mA
-60.0
mA
Per pin
Note 4
Unit
-10.0
Total of all pins
low
Note 2
4.0 V ≤ VDD ≤ 5.5 V
Note 3
Output current,
MAX.
20.0
Note 2
mA
4.0 V ≤ VDD ≤ 5.5 V
20.0
mA
2.7 V ≤ VDD < 4.0 V
3.0
mA
2.0 V ≤ VDD < 2.7 V
0.6
mA
4.0 V ≤ VDD ≤ 5.5 V
80.0
mA
2.7 V ≤ VDD < 4.0 V
12.0
mA
2.0 V ≤ VDD < 2.7 V
2.4
mA
100.0
mA
Note 3
Total of all pins
Input voltage, high
VIH1
0.8 VDD
VDD
V
Input voltage, low
VIL1
0
0.2 VDD
V
Output voltage, high
VOH1
4.0 V ≤ VDD ≤ 5.5 V
IOH =-10 mA
VDD-1.5
V
IOH =-3.0 mA
VDD-0.7
V
2.7 V ≤ VDD ≤ 5.5 V
IOH =-2.0 mA
VDD-0.6
V
2.0 V ≤ VDD ≤ 5.5 V
IOH =-1.5 mA
VDD-0.5
4.0 V ≤ VDD ≤ 5.5 V
IOL = 20 mA
1.3
V
IOL = 8.5 mA
0.7
V
IOL = 3.0 mA
0.6
V
IOL = 1.5 mA
0.4
V
IOL = 0.6 mA
0.4
V
Note 5
Output voltage, low
VOL1
V
Note 6
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD ≤ 5.5 V
Input leakage
ILIH1
VI = VDD
1
µA
ILIL1
VI = VSS
-1
µA
RU
VI = VSS
100
kΩ
current, high
Input leakage
current,low
On-chip pull-up
10
20
resistance
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
Do not exceed the total current value.
3.
This is the output current value under conditions where the duty factor ≤ 70%.
The output current value when the duty factor > 70% can be calculated with the following expression (when
changing the duty factor to n%).
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80 % and IOH = - 10.0 mA
Total output current of pins = (- 10.0 × 0.7)/(80 × 0.01) ≅ - 8.7 mA
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80 % and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
4.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
5.
The value under the condition which satisfies the high-level output current (IOH1).
6.
The value under the condition which satisfies the low-level output current (IOL1).
Cautions 1.
2.
Remark
P00 and P01 do not output high level in N-ch open-drain mode.
The maximum value of VIH of P00 and P01 is VDD even in N-ch open-drain mode.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.3.2 Supply current characteristics
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply current
Symbol
Note 1
IDD1
Note 2
IDD2
Note 3
WDT supply current
Conditions
Operating
Basic
mode
operation
MIN.
TYP.
MAX.
fIH = 20 MHz
VDD = 3.0 V, 5.0 V
0.91
Normal
fIH = 20 MHz
VDD = 3.0 V, 5.0 V
1.57
2.04
operation
fIH = 5 MHz
VDD = 3.0 V, 5.0 V
0.85
1.15
fIH = 20 MHz
VDD = 3.0 V, 5.0 V
350
820
fIH = 5 MHz
VDD = 3.0 V, 5.0 V
290
600
0.56
2.00
HALT mode
IDD3
STOP mode
IWDT
fIL = 15 kHz
IADC
During conversion at the
VDD = 5.0 V
1.30
highest speed
VDD = 3.0 V
0.50
VDD = 3.0 V
Unit
mA
0.31
µA
µA
µA
Note 4
ADC supply current
Note 5
Notes 1.
1.90
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the watchdog timer, A/D converter, I/O port, and on-chip pull-up/pulldown resistors.
2.
During HALT instruction execution by flash memory.
3.
When the high-speed on-chip oscillator is stopped.
4.
Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the
watchdog timer operates.
5.
Current flowing only to the A/D converter. The current value of the RL78 microcontrollers is the sum of IDD1
or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fIH: High-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.4 AC Characteristics
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items
Symbol
Instruction cycle (minimum
TCY
instruction execution time)
TI00, TI01 input high-level
tTIH, tTIL
MIN.
Conditions
PCLBUZ0 output frequency
RESET low-level width
MAX.
Unit
Main system clock
2.7 V ≤ VDD ≤ 5.5 V
0.05
0.8
µs
(fMAIN) operation
2.0 V ≤ VDD ≤ 5.5 V
0.2
0.8
µs
1/fMCK +
Noise filter is not used
width, low-level width
TO00, TO01 output frequency
TYP.
ns
10
fTO
fPCL
4.0 V ≤ VDD ≤ 5.5 V
10
MHz
2.7 V ≤ VDD < 4.0 V
5
MHz
2.0 V ≤ VDD < 2.7 V
2.5
MHz
4.0 V ≤ VDD ≤ 5.5 V
10
MHz
2.7 V ≤ VDD < 4.0 V
5
MHz
2.0 V ≤ VDD < 2.7 V
2.5
MHz
tRSL
10
µs
Remark fMCK: Timer array unit operation clock frequency
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
TI/TO Timing
tTIH
tTIL
TI00, TI01
1/fTO
TO00, TO01
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
Interrupt Request Input Timing
tINTH
tINTL
INTP0, INTP1
Key Interrupt Input Timing
tKR
KR0 to KR5
RESET Input Timing
tRSL
RESET
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.5 Serial Communication Characteristics
2.5.1 Serial array unit
(1) UART mode
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
Theoretical value of the
MAX.
Unit
fMCK/6
bps
3.3
Mbps
maximum transfer rate
fCLK = fMCK = 20 MHz
UART mode connection diagram
Rx
TxD0
RL78
microcontroller
User’s device
Tx
RxD0
UART mode bit width (reference)
1/transfer rate
High-/low-bit width
Baud rate error tolerance
TxD0
RxD0
Remark
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(2) CSI mode (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
2.7 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK
SCKp high-/low-level width
tKH1, tKL1
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD ≤ 5.5 V
tKCY1/2-50
ns
2.7 V ≤ VDD ≤ 5.5 V
47
ns
2.0 V ≤ VDD ≤ 5.5 V
110
ns
19
ns
2.0 V ≤ VDD ≤ 5.5 V
SIp setup time (to SCKp↑)
Note 1
SIp hold time (from SCKp↑)
Note 2
Delay time from SCKp↓ to SOp
output
tSIK1
tKSI1
tKSO1
C = 30 pF
200
ns
800
ns
tKCY1/2-18
ns
Note 4
25
ns
Note 3
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Remarks 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(3) CSI mode (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY2
SCKp high-/low-level width
tKH2,
Conditions
2.7 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
fMCK = 20 MHz
8/fMCK
ns
fMCK ≤ 10 MHz
6/fMCK
ns
2.0 V ≤ VDD < 2.7 V
6/fMCK
ns
2.0 V ≤ VDD ≤ 5.5 V
tKCY2/2
ns
2.7 V ≤ VDD ≤ 5.5 V
1/fMCK +
ns
tKL2
Note 1
SIp setup time (to SCKp↑)
tSIK2
20
2.0 V ≤ VDD < 2.7 V
1/fMCK +
ns
30
SIp hold time (from SCKp↑)
Note 2
tKSI2
2.0 V ≤ VDD ≤ 5.5 V
1/fMCK +
ns
31
Delay time from SCKp↓ to SOp
output
tKSO2
C = 30 pF
Note 4
Note 3
2.7 V ≤ VDD ≤ 5.5
2/fMCK + 50
ns
2/fMCK + 110
ns
V
2.0 V ≤ VDD < 2.7
V
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
Remarks 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (mn = 00))
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
CSI mode connection diagram
SCK
SCK00
RL78
microcontroller
SI00
SO User’s device
SO00
SI
CSI mode serial transfer timing
(When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCK00
tSIK1, 2
SI00
tKSI1, 2
Input data
tKSO1, 2
SO00
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Output data
Page 20 of 28
RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2
(4) Simplified I C mode
(TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
SCLr clock frequency
Symbol
fSCL
Conditions
MIN.
2.0 V ≤ VDD ≤ 5.5 V,
MAX.
400
Note 1
Unit
kHz
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = "L"
tLOW
2.0 V ≤ VDD ≤ 5.5 V,
1150
ns
1150
ns
2.0 V ≤ VDD ≤ 5.5 V,
1/fMCK +
ns
Cb = 100 pF, Rb = 3 kΩ
145
Cb = 100 pF, Rb = 3 kΩ
Hold time when SCLr = "H"
tHIGH
2.0 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
Data setup time (reception)
Data hold time (transmission)
tSU: DAT
tHD: DAT
2.0 V ≤ VDD ≤ 5.5 V,
Note 2
0
355
ns
Cb = 100 pF, Rb = 3 kΩ
Notes 1.
2.
The value must also be equal to or less than fMCK/4.
Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the N-ch open drain output (VDD tolerance) mode for the SDAr pin by using the port output mode
register 0 (POM0).
Remarks 1. Rb [Ω]: Communication line (SDAr) pull-up resistance, Cb [F]: Communication line (SCLr, SDAr) load
capacitance
2. r: IIC number (r = 00)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2
Simplified I C mode connection diagram
VDD
Rb
SDA
SDA00
RL78
microcontroller
User’s device
SCL
SCL00
2
Simplified I C mode serial transfer timing
1/fSCL
tLOW
tHIGH
SCL00
SDA00
tHD : DAT
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tSU : DAT
Page 22 of 28
RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
(Target ANI pin : ANI0 to ANI3)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
Zero-scale error
Full-scale error
EFS
Note 1
Differential linearity error
Note 1
Analog input voltage
Notes 1.
2.
10-bit resolution
10-bit resolution
ILE
10-bit resolution
DLE
10-bit resolution
MAX.
Unit
10
bit
VDD = 5 V
±1.7
±3.1
Note 2
VDD = 3 V
±2.3
±4.5
Note 2
10-bit resolution
EZS
Note 1
Integral linearity error
10-bit resolution
tCONV
Note 1
TYP.
8
AINL
Conversion time
MIN.
LSB
LSB
2.7 V ≤ VDD ≤ 5.5 V
3.4
18.4
µs
2.4 V ≤ VDD ≤ 5.5 V
4.6
18.4
µs
VDD = 5 V
±0.19
Note 2
VDD = 3 V
±0.39
Note 2
%FSR
VDD = 5 V
±0.29
Note 2
%FSR
VDD = 3 V
±0.42
Note 2
%FSR
VDD = 5 V
%FSR
±1.8
Note 2
LSB
VDD = 3 V
±1.7
Note 2
LSB
VDD = 5 V
±1.4
Note 2
LSB
VDD = 3 V
±1.5
Note 2
LSB
VAIN
0
VDD
V
Excludes quantization error (±1/2 LSB).
This is the characteristic evaluation value plus or minus 3. These values are not used in the shipping
inspection.
2.6.2 SPOR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
Detection supply voltage
VSPOR0
VSPOR1
VSPOR2
VSPOR3
Minimum pulse width
Note
Note
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
4.08
4.28
4.45
V
Power supply fall time
4.00
4.20
4.37
V
Power supply rise time
2.76
2.90
3.02
V
Power supply fall time
2.70
2.84
2.96
V
Power supply rise time
2.44
2.57
2.68
V
Power supply fall time
2.40
2.52
2.62
V
Power supply rise time
2.05
2.16
2.25
V
Power supply fall time
2.00
2.11
2.20
V
TSPW
300
µs
Time required for the reset operation by the SPOR when VDD becomes under VSPDR.
2.6.3 Power supply voltage rising slope characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Power supply voltage rising slope
R01DS0207EJ0100 Rev.1.00
Apr 15, 2013
Symbol
SVDD
Conditions
MIN.
TYP.
MAX.
Unit
54
V/ms
Page 23 of 28
RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.6.4 Data retention power supply voltage characteristics
(TA = −40 to +85°C, Vss = 0 V)
Parameter
Data retention power supply voltage
Symbol
VDDDR
Conditions
MIN.
1.9
TYP.
MAX.
Unit
5.5
V
range
Caution Data is retained until the power supply voltage becomes under the minimum value of the data
retention power supply voltage range. Note that data in the RAM and RESF registers might not be
cleared even if the power supply voltage becomes under the minimum value of the data retention
power supply voltage range.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.7 Flash Memory Programming Characteristics
(TA = 0 to + 40°C, 4.5 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Code flash memory
rewritable times
Notes 1.
Symbol
Cerwr
Conditions
Retained for 20 years.
MIN.
TA = + 85°C
TYP.
MAX.
1000
Unit
Times
Notes 1, 2, 3
1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the
rewrite.
2.
When using flash memory programmer.
3.
These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
2.8 Dedicated Flash Memory Programmer Communication (UART)
(TA = 0 to + 40°C, 4.5 V ≤ VDD ≤ 5.5V, VSS = 0 V)
Parameter
Symbol
Conditions
Transfer rate
Remark
MIN.
TYP.
115,200
MAX.
Unit
bps
The transfer rate during flash memory programming is fixed to 115,200 bps.
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RL78/G10
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.9 Timing of Entry to Flash Memory Programming Modes
Parameter
Symbol
How long from when an external
tSUINIT
Conditions
MIN.
TYP.
SPOR reset must end before the external
MAX.
Unit
100
ms
reset ends.
reset ends until the initial
communication settings are
specified
How long from when the TOOL0
tSU
SPOR reset must end before the external
10
μs
1
ms
reset ends.
pin is placed at the low level until
an external reset ends
How long the TOOL0 pin must be
tHD
SPOR reset must end before the external
reset ends.
kept at the low level after an
external reset ends
<1>
<2>
<4>
<3>
RESET
tHD
Mode setting
one-byte data
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (SPOR reset must end before the external reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of entry to the flash memory programming mode by UART reception.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100
ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until an external reset ends (MIN. 10 μ s)
tHD:
How long to keep the TOOL0 pin at the low level from when the external reset ends
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Page 26 of 28
RL78/G10
CHAPTER 3 PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1 10-pin products
R5F10Y16ASP, R5F10Y14ASP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP10-4.4x3.6-0.65
PLSP0010JA-A
P10MA-65-CAC-2
0.05
V
detail of lead end
6
10
T
I
P
5
1
L
U
V
A
W
W
F
H
G
J
S
E
B
C
N S
D
M M
NOTE
Each lead centerline is located within 0.13 mm
of its true position (T.P.) at maximum material
condition.
K
(UNIT:mm)
ITEM
A
B
DIMENSIONS
3.60 ±0.10
0.50
C
0.65 (T.P.)
D
0.24 ± 0.08
E
0.10 ± 0.05
F
1.45 MAX.
G
1.20 ± 0.10
H
I
6.40 ± 0.20
4.40 ± 0.10
L
1.00 ± 0.20
+ 0.08
0.17
− 0.07
0.50
M
0.13
N
0.10
J
K
T
+5 °
3° 3 °
−
0.25 (T.P.)
U
0.60 ± 0.15
P
V
0.25 MAX.
W
0.15 MAX.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0207EJ0100 Rev.1.00
Apr 15, 2013
Page 27 of 28
RL78/G10
CHAPTER 3 PACKAGE DRAWINGS
3.2 16-pin products
R5F10Y47ASP, R5F10Y46ASP, R5F10Y44ASP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-SSOP16-4.4x5-0.65
PRSP0016JC-A
P16MA-65-FAA-2
0.08
D1
D
detail of lead end
9
16
A3
E
1
c
8
L
Lp
ZD
bp
x M S
HE
A
A2
L1
S
S
(UNIT:mm)
A1
y S
e
ITEM
DIMENSIONS
D
5.00 ± 0.15
D1
5.20 ± 0.15
E
4.40 ± 0.20
HE
6.40 ± 0.20
A
1.725 MAX.
A1
0.125 ± 0.05
A2
1.50
A3
0.25
e
bp
c
0.65
0.22 + 0.08
0.07
0.15 + 0.03
0.04
L
0.50
Lp
0.60 ± 0.10
L1
x
y
1.00 ± 0.20
ZD
0.13
0.10
+ 5°
3° 3°
0.325
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0207EJ0100 Rev.1.00
Apr 15, 2013
Page 28 of 28
Revision History
RL78/G10 Data Sheet
Rev.
Date
Page
1.00
Apr 15, 2013
-
Description
Summary
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
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