DX1 User Manual - Blue Chip Technology
DX1
Single Board Computer
User Manual
DX1
User Manual
Document Part N°
Document Reference
Document Issue Level
0127-0173
DX\..\0127-0173.doc
2.0
Manual covers PCBs identified
Issue 2.x & 3.x
(x is any digit)
All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or
otherwise, without the prior permission, in writing, from the publisher. For permission in the UK
contact Blue Chip Technology.
Information offered in this manual is correct at the time of printing. Blue Chip Technology accepts
no responsibility for any inaccuracies. This information is subject to change without notice.
All trademarks and registered names acknowledged.
Blue Chip Technology Ltd.
Chowley Oak, Tattenhall
Chester, Cheshire
CH3 9EX
Telephone : 01829 772000 Facsimile : 01829-772001
Amendment History
Issue
Level
1.7
Issue
Date
Author
Amendment Details
11/05/95
06/06/95
PMD
Corrections to Version 1.6
1.8
MM
1.9
04/06/96
EGW
2.0
11/04/96
EGW
Video Driver Information added
(ECN95/079)
Added EMC information to Technical
Section (ECN96/060). Update to J13 link
selection for 9054 & 9154 frequency
synthesisers (ECN 96/107). External
battery voltage modified (was 3.6 V). New
front sheet. Previous filename was
DXMAN1_9.doc
Minor corrections. New frequency
synthesiser jumper settings (J13) for Iss 3
PCBs. Solid State Disk section updated.
ECN97/011 refers.
Contents
INTRODUCTION............................................................................................... 1
SPECIFICATION ............................................................................................... 3
ON-BOARD FEATURES ............................................................................................ 3
MEMORY OPTIONS .................................................................................................5
POWER REQUIREMENT ........................................................................................... 6
ELECTROMAGNETIC COMPATIBILITY ...................................................................... 6
ENVIRONMENT ....................................................................................................... 8
EMC SPECIFICATION ............................................................................................. 8
PHYSICAL............................................................................................................... 8
BIOS ..................................................................................................................... 9
System BIOS ...................................................................................................... 9
Video BIOS...................................................................................................... 10
Keyboard BIOS ............................................................................................... 10
Expansion ROMs............................................................................................. 10
AMI HI-FLEX SYSTEM BIOS............................................................................... 11
Features .......................................................................................................... 11
Hot Keys .......................................................................................................... 11
AMIBIOS Power-on Self Test.......................................................................... 12
POST Error Messages and Beep Codes .......................................................... 12
AMIBIOS SET-UP ............................................................................................... 13
Standard CMOS Set-up ................................................................................... 13
Advanced CMOS Set-up .................................................................................. 13
Advanced Chipset Set-up................................................................................. 13
Dx-1 Extended Set-up...................................................................................... 13
Utilities............................................................................................................ 13
Running the AMIBIOS Set-up ......................................................................... 14
Accessing Set-up.............................................................................................. 14
Set-up Key Use ................................................................................................ 15
Using the CMOS Set-up Program ................................................................... 17
Date................................................................................................................. 19
Time................................................................................................................. 19
Floppy Disk Configuration.............................................................................. 19
Hard Disk Configuration ................................................................................ 19
Display ............................................................................................................ 19
Keyboard ......................................................................................................... 19
Using the Advanced CMOS Set-up.................................................................. 20
Help Screens.................................................................................................... 21
Typematic Rate Programming, Typematic Rate Delay and Typematic Rate .. 21
Above 1MB Memory Test ................................................................................ 21
Blue Chip Technology Ltd
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Contents
Memory Test Tick Sound .................................................................................21
Memory Parity Error Check ............................................................................21
Hit <DEL> Message Display ..........................................................................21
Hard Disk Type 47 RAM Area .........................................................................22
Wait for <F1> If any Error .............................................................................22
System Boot Up Num Lock ..............................................................................22
Numeric Processor Test...................................................................................22
Floppy Drive Seek at Boot ...............................................................................22
System Boot Up Sequence................................................................................23
External Cache Memory ..................................................................................23
Internal Cache Memory ...................................................................................23
Turbo Switch Function ....................................................................................23
Fast Gate A20 Option ......................................................................................23
Password Checking Option .............................................................................24
ROM Shadow...................................................................................................24
Boot Sector Virus Protection ...........................................................................24
Using the Advanced Chipset ............................................................................25
Using the DX-1 Extended Set-up .....................................................................34
Programming Option.......................................................................................34
On-Board Floppy Drive...................................................................................35
On-Board IDE Drive .......................................................................................35
First Serial Port Address .................................................................................35
Second Serial Port Address .............................................................................35
Parallel Port Address ......................................................................................35
Parallel Port Mode ..........................................................................................36
IRQ Active State ..............................................................................................36
First Serial Port Mode.....................................................................................36
First Serial Port 485 Mode..............................................................................36
Second Serial Port Mode .................................................................................36
Second Serial Port 485 Mode ..........................................................................36
Quick Disk Boot Rom ......................................................................................36
SSD Boot Rom .................................................................................................36
CardTrick Boot Rom........................................................................................37
BIOS Extensions ..............................................................................................37
Auto Configuration with Defaults....................................................................37
Change Passwords ..........................................................................................37
Bypassing Password Support ..........................................................................37
Enabling Password Support ............................................................................37
If a Password is Used ......................................................................................37
Password Storage ............................................................................................38
Password Options Control Prompt..................................................................38
Using a Password ............................................................................................38
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Blue Chip Technology Ltd
Contents
Auto Detect Hard Disk .................................................................................... 38
Write to CMOS and Exit.................................................................................. 39
Do Not Write to CMOS and Exit ..................................................................... 39
DX1 PERIPHERAL COMPONENTS ............................................................ 40
VIDEO .................................................................................................................. 40
IBM Standard Video Modes ............................................................................ 41
Cirrus Logic Extended Video Modes............................................................... 41
VIDEO DRIVERS ................................................................................................... 42
VIDEO DRIVER INSTALLATION INSTRUCTIONS ....................................................... 42
WATCHDOG TIMER .............................................................................................. 43
E²PROM.............................................................................................................. 43
SERIAL PORTS ...................................................................................................... 44
BYTE WIDE SSD USER SOCKETS ......................................................................... 45
BATTERY ............................................................................................................. 46
MEMORY MAP ..................................................................................................... 47
Typical Memory Map for a 1MByte DX1 ........................................................ 47
DISK DRIVES ........................................................................................................ 48
Floppy Drives.................................................................................................. 48
Hard Drives (IDE) ......................................................................................... 49
HARD DISK TYPES ............................................................................................... 49
ISA BUS & VESA LOCAL BUS DETAILS ................................................... 51
ISA BUS SIGNAL DESCRIPTIONS .......................................................................... 51
VESA LOCAL BUS ............................................................................................... 56
Description...................................................................................................... 56
VL-Bus Signal Definitions ............................................................................... 56
BCT DX1 SBC I/O ADDRESS MAP ..................................................................... 61
INTERRUPT ASSIGNMENTS ................................................................................... 62
DMA ASSIGNMENTS ............................................................................................ 62
APPENDIX A .................................................................................................... 63
POST ERROR CODES ........................................................................................... 63
APPENDIX B .................................................................................................... 67
CONFIGURATION JUMPERS ................................................................................... 67
APPENDIX C .................................................................................................... 69
CONNECTOR DETAILS .......................................................................................... 69
P1: FLOPPY (34 WAY HEADER) ............................................................................ 69
P2: HARD DRIVE (40 WAY HEADER) .................................................................... 70
P3: COM 2 (10 WAY HEADER).............................................................................. 70
Blue Chip Technology Ltd
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Contents
P4: RS422/485 S ERIAL (10 WAY HEADER)...........................................................71
P5: PARALLEL (26 WAY HEADER).........................................................................71
P6: FEATURE (26 WAY HEADER) ..........................................................................72
P7: VIDEO (15 WAY CONDENSED D TYPE)............................................................72
P8: POST (12 WAY HEADER).................................................................................72
P9: MOUSE (6 PIN MINI DIN)................................................................................73
P10: SSD CONNECTOR (8 WAY HEADER).............................................................73
P11: COM 1 (9 WAY D) ........................................................................................73
P12: PERIPHERAL (20 WAY HEADER)...................................................................73
P13: KEYBOARD (6 PIN MINI DIN) .......................................................................74
P14: BATTERY (4 WAY HEADER)..........................................................................74
P15: BACKPLANE UTILITY CONNECTOR (10 WAY HEADER) .................................74
P16: AT EXPANSION CONNECTOR .......................................................................75
P17: PC/XT EXPANSION CONNECTOR .................................................................76
ISA BUS XT CONNECTIONS .................................................................................77
ISA BUS AT CONNECTIONS .................................................................................78
VESA LOCAL BUS CONNECTOR ..........................................................................79
(MCA STYLE GOLD EDGE CONNECTOR)................................................................79
APPENDIX D.....................................................................................................81
CMOS RAM MAP ...............................................................................................81
APPENDIX E.....................................................................................................89
CHIPSET REGISTERS..............................................................................................89
APPENDIX F .....................................................................................................93
SOLID STATE DISK OPERATION (SSD)..................................................................93
Quick Disk SSD ...............................................................................................93
Programming the Flash. ..................................................................................93
Programming the SRAM..................................................................................94
DAUGHTER BOARD SSD.......................................................................................95
APPENDIX G ....................................................................................................96
CONNECTOR AND JUMPER LINK PCB POSITIONS..................................................96
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Blue Chip Technology Ltd
Introduction
Page 1
INTRODUCTION
This manual describes the Blue Chip Technology (BCT) DX1 processor card.
There are several versions of the card; these will be identified where appropriate.
We strongly recommend that you study this manual carefully before attempting to
change the configuration. Whilst all necessary information is available in this
manual we would recommend that, unless you are confident, you contact your
supplier to effect any changes. This card uses the UMC 82C491 & 82C493 VLSI
devices, they provide a complete AT compatible environment with VESA
VL-Bus ä compatible local bus support.
WARNING
The devices on this card can be fatally damaged by static electricity. Ensure that
you touch a suitable ground to discharge any static build up before touching the
card. This should be repeated if the handling is for any length of time.
Information offered in this manual is correct at the time of printing. Blue Chip
Technology accept no responsibility for any inaccuracies. This information is
subject to change without notice.
If this product proves to be defective, Blue Chip Technology is only obliged to
replace or refund the purchase price at Blue Chip Technology's discretion.
Please contact our Customer Support Department for assistance.
Blue Chip Technology Ltd
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Page 2
Introduction
Limitations of Liability
In no event shall Blue Chip Technology be held liable for any loss, expenses or
damages of any kind whatsoever, whether direct, indirect, incidental or
consequential, arising from the design or use of this product or the support
materials supplied with this product.
Trademarks
IBM, PC, AT and PS/2 are trademarks of International Business Machines
Corporation.
AMI Hi-Flex BIOS is a trademark of American Megatrends Inc.
Intel is a registered trademark of Intel Corporation
80486SX, 80486DX are registered trademarks of the Intel Corporation
VESA VL-Bus is a registered trademark of the Video Electronics Standards
Association.
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Blue Chip Technology Ltd
Specification
Page 3
SPECIFICATION
The BCT DX1 CPUs are single slot high performance computers that provide
100% IBM PC/AT compatibility. They offer the very highest level of integration
currently available on an AT plug-in card.
In addition they support on board VL-Bus SVGA controller and will support up
to two additional VL-Bus expansion slot.
On-board Features
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Choice of 25MHz 80486SX, 33MHz 80486DX, 66MHz 80486DX2,
80486DX4/100 or P24T microprocessor
Optional 256K Direct mapped (one way set associative) write back cache
memory with software control via set-up menu
Up to 64MB of DRAM memory, supports 1MB x 36, 4MB x 36, 8MB x 36
and 16MB x 36 SIMM modules
High performance memory Page Interleave access
AMI BIOS with built in set-up program
Hardware EMS support (LIM 3.2 & 4.0 compatible)
Selectable Shadow RAM for system & video BIOS
Selectable Bus speed
Automatic or Manual Peripheral Configuration
Local bus SVGA controller with GUI accelerator and up to 2MB of video
memory & VESA VL-bus connector
On board optional solid state disk up to 2 MBytes of flash and 512K bytes of
battery backed SRAM
I.D.E. controller (2 drives)
Floppy controller (Intel 8272 compatible) supporting 360KB, 720KB,
1.2MB, 1.44MB & 2.88MB drives
2 asynchronous serial ports (16C550 compatible) software selectable as
RS232C or RS485 (selectable as either full or half duplex)
Bi-directional parallel port
AT compatible keyboard port
PS/2 Mouse port (check configuration)
Customer "sign-on" information held in EEPROM
POST header
Software selectable Watchdog timer
On-board "Power Good" generation
On-board speaker with additional external drive circuitry
Blue Chip Technology Ltd
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Page 4
·
·
Specification
On-board Lithium battery
Multi layer PCB using Surface Mount Technology (SMT)
The DX1 can support memory configurations from 1MB up to 64MB. This is
achieved by offering 4, 72 pin SIMM carriers that can take modules in size from
256K x 36 bits data and (32, 4 parity bits) to 16MB x 36 bits.
The DX board can also accommodate SIMM units without parity. However
please ensure that the BIOS is set correctly for this condition.
The following table shows the memory configurations supported by the DX1.
Always ensure that you observe full static precautions before attempting to
handle the DX1 and memory modules.
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Blue Chip Technology Ltd
Specification
Page 5
Memory Options
Option
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Bank 0
256K
256K
256K
256K
1M
1M
1M
1M
1M
1M
1M
1M
1M
1M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
16M
Bank 1
256K
256K
256K
256K
256K
256K
1M
1M
1M
1M
1M
1M
256K
256K
256K
1M
1M
1M
1M
1M
1M
4M
4M
4M
4M
4M
4M
4M
4M
4M
4M
-
Bank 2
256K
256K
256K
256K
256K
256K
1M
1M
1M
256K
256K
256K
256K
1M
1M
1M
256K
256K
1M
1M
1M
4M
4M
4M
4M
-
Bank 3
256K
256K
256K
256K
1M
256K
256K
256K
1M
256K
256K
1M
256K
1M
4M
-
Total DRAM
1MB
2MB
3MB
4MB
4MB
5MB
6MB
7MB
8MB
9MB
10MB
12MB
13MB
16MB
16MB
17MB
18MB
19MB
20MB
21MB
22MB
24MB
25MB
28MB
32MB
33MB
34MB
36MB
37MB
40MB
48MB
49MB
52MB
64MB
64MB
Note:
·
·
·
·
The four banks are made up of four 72 pin SIMM carriers
All SIMMs must have an access time of 70ns or faster
(e.g. 60ns)
All SIMMs modules quoted above are 32 bits wide (4 bytes)
SIMMs modules without parity can be used with the BIOS set accordingly
Blue Chip Technology Ltd
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Page 6
Specification
Power Requirement
The DX1 requires +5Vdc only. The actual current consumption varies with
configuration. The following table should be used as a guideline to the total
power requirement.
CPU Option
486SX
486DX
486DX2
486DX4
Speed
25 MHz
33 MHz
66 MHz
100 MHz
Typical Current
2.8A
3.0A
3.7A
Contact BCT
All the above requirements are for DX1 configurations fitted with 4MB of
DRAM.
Electromagnetic Compatibility
This product meets the requirements of the European EMC Directive
(89/336/EEC) and is eligible to bear the CE mark.
It has been assessed operating in a Blue Chip Technology Icon industrial PC.
However, because the board can be installed in a variety of computers, certain
conditions have to be applied to ensure that the compatibility is maintained. It
meets the requirements for an industrial environment (Class A product) subject to
those conditions.
· The board must be installed in a computer system which provides screening
suitable for the industrial environment.
· Any recommendations made by the computer system manufacturer/supplier
must be complied with regarding earthing and the installation of boards.
· The board must be installed with the backplate securely screwed to the
chassis of the computer to ensure good metal-to-metal (i.e. earth) contact.
· Most EMC problems are caused by the external cabling to boards. It is
imperative that any external cabling to the board is totally screened, and that
the screen of the cable connects to the metal end bracket of the board and
hence to earth. It is recommended that round screened cables with a braided
wire screen are used in preference to those with a foil screen and drain wire.
Use metal connector shells which connect around the full circumference of
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Blue Chip Technology Ltd
Specification
Page 7
the screen; they are far superior to those which earth the screen by a simple
“pig-tail”.
· The keyboard will play an important part in the compatibility of the processor
card since it is a port into the board. A fully compatible keyboard must be
used otherwise the keyboard itself may radiate or behave as if keys are
pressed when subject to interference. Under these circumstances it may be
beneficial to add a ferrite clamp on the keyboard lead as close as possible to
the connector. A suitable type is the Chomerics type H8FE-1004-AS.
· Ensure that the screens of any external cables are bonded to a good RF earth
at the remote end of the cable.
Failure to observe these recommendations may invalidate the EMC compliance.
Warning
This is a Class A product. In a domestic environment this product
may cause radio interference in which case the user may be
required to take adequate measures.
Blue Chip Technology Ltd
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Page 8
Specification
Environment
Operating Temperature
Storage Temperature
Relative Humidity
0°C to 60°C.
-20°C to 70°C.
90% non-condensing.
EMC Specification
A Blue Chip Technology Icon industrial PC fitted with this card meets the
following specification:
Emissions
Immunity
EN 55022:1995
Radiated
Conducted
EN 50082-2:1995 incorporating:
Electrostatic Discharge
Radio Frequency Susceptibility
Fast Burst Transients
Class A
Class A & B
IEC 801-2:1991
Performance Criteria A
ENV 50140:1993
Performance Criteria A
IEC 801-4:1988
Performance Criteria A
Physical
Size
01270173.doc
339 x 122mm
Occupies one AT/VESA slot
Blue Chip Technology Ltd
BIOS
Page 9
BIOS
Overview
There are several types of Basic Input Output Systems (BIOS) in a PC system.
System BIOS
This controls the local electronics. It also provides the interface to the hardware
for the operating system.
Video BIOS
This controls the interface between the video hardware and the computer.
Keyboard BIOS
This controls the keyboard matrix operation, interacts with switches, LEDs, etc.
and communicates with the PC.
Each of these BIOS's will now be described :
System BIOS
The primary function of the System BIOS is to provide a series of software
interrupts, functions and sub functions that perform specific system tasks; such as
writing or reading to and from disks and video screens.
The operating system uses the System BIOS as the route to communicate and
control the microprocessor and its immediate peripherals. This exchange of data
occurs via a strict protocol .
The secondary function of the System BIOS is the series of tests and
initialisations that occur after power-on. The results of these operations are
written to the POST display (if fitted) as they are completed, thereby indicating
its progress.
Blue Chip Technology Ltd
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Page 10
BIOS
The System BIOS on the DX1 is contained in a 128KB EPROM; of this space
the System BIOS occupies 64KB. The EPROM is located at address F0000 hex
and continues to FFFFF hex. The supplier of the BIOS is AMI, currently the
leading supplier of PC BIOS's in the world. BCT have selected this supplier
because of their experience, support and commitment to future developments in
this critical area of a PC/AT design.
Video BIOS
The Video BIOS acts as an interface between the System BIOS and the video
hardware. It is critical that this interface is compatible, fast and reliable. The
Video BIOS provides a relatively high level of access to the hardware. The onboard video hardware on the DX1 is based on the Cirrus Logic
GD5424/26/28/29. This device offers proven VGA compatibility as well as
providing enhanced GUI acceleration in a single device. It is supported by up to
2MB of video memory. The Video BIOS co-exists in the System BIOS EPROM
but locates in the address range C0000 to C7FFF hex.
Keyboard BIOS
The Keyboard BIOS is contained in the 8042 (or 8742) keyboard controller. This
device provides a parallel interface to the microprocessor bus allowing a bidirectional streams of data to be passed between the PC and the keyboard. The
BIOS is programmed into the 8042. It occupies none of the memory map.
Expansion ROMs
Most PCs allow add-on cards to be inserted into the backplane. If software is
required to control the electronics on the card the supplier may choose to provide
this software in the form of an expansion ROM or adapter ROM. On power-on
the PC, once initialised, checks for the presence of ROMs within the memory
space of C8000 to DFFFF hex. If present the code within the ROM is run and the
specific hardware on the card controlled accordingly. In addition this software
can then be used as the interface to the electronics by the operating system;
thereby acting as an extension to the System BIOS for the new electronics.
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Blue Chip Technology Ltd
BIOS
Page 11
AMI Hi-Flex System BIOS
Features
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Keyboard Speed Switching
Enable Cache Memory
Memory Detection
Password Support
Auto detection of IDE Hard Drive Parameters
Auto detection of Processor Type and Speed
Auto detection of Memory Size and Type
Customisation of the System
User definable Hard Disk Types
PS/2 Mouse Support
Boot Sector Virus Support
Local Peripheral Support
Shadow RAM Support
Keyboard Typematic Rate and Delay
Num Lock Power-on Status
Fast Gate A20 Support
Hot Keys
The Hi-Flex AMIBIOS provides hot keys to switch speed and cache operation.
These key operations are:
<Ctrl>,<Alt> and <+>
<Ctrl>,<Alt> and <->
<Ctrl>,<Alt>,<Shift> and <+>
<Ctrl>,<Alt>,<Shift> and <->
<Ctrl>,<Alt> and <DEL>
Selects High Speed
Selects Low Speed
Enables External Cache
Disables External Cache
Causes a Soft Reset
All keys should be pressed together.
Blue Chip Technology Ltd
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Page 12
BIOS
AMIBIOS Power-on Self Test
The Hi-Flex AMIBIOS provides all IBM standard POST routines as well as
enhanced AMIBIOS routines. All POST checkpoint codes are written to the
POST display at I/O location 80 hex (if fitted). See the POST error codes
Appendix A.
POST Error Messages and Beep Codes
If the BIOS cannot configure the display controller it will communicate the
identification of fatal errors (except error code 8) via a series of beeps. These
errors will only occur during power-on tests. The beep codes are as follows:
Beeps
1
2
3
4
Error Messages
Refresh Failure
Parity Error
Base 64KB Memory Failure.
Timer not Operational.
5
6
7
Processor error.
8042 - Gate A20 Failure.
Processor Exception Interrupt
Error.
Display Memory Read/Write
Error.
ROM Checksum Error.
8
9
10
11
CMOS Shutdown Register
Read/Write Error.
Cache Memory Bad - Do Not
Enable Cache
Description
Memory Refresh circuitry faulty.
Parity error in the first 64KB of memory.
Memory failure in the first 64KB.
Timer 1 is not functioning. Alternatively,
memory in the first 64KB faulty.
CPU error.
BIOS cannot switch to protected mode.
CPU generated an exception interrupt
error.
Video adapter is not responding or its
memory is faulty.
ROM checksum embedded in the ROM
does not match the calculated value.
The shutdown register in the CMOS
RAM failed. Check access to CMOS.
The cache memory test failed. Cache
memory is disabled. Do not press
<CTRL> <ALT> <SHIFT> <+> to enable
cache memory.
What to do if the DX1 Beeps
If the system beeps......
1,2 or 3 times
6 times
4,5,7,8,9,10 or 11
01270173.doc
then....
Re-seat the SIMMs. If the DX1 still
beeps, replace the SIMMs checking the
access time.
Check the keyboard connections. If the
beeps persist change the keyboard.
Contact Blue Chip Technology
Blue Chip Technology Ltd
BIOS
Page 13
AMIBIOS Set-up
The Hi-Flex AMIBIOS Set-up utility is divided into five parts:
Standard CMOS Set-up
The Hi-Flex AMIBIOS Standard CMOS Set-up permits the user to configure and
set system components such as floppy drives, hard disk drives, time and date,
monitor type and keyboard. These options are discussed on page 17.
Advanced CMOS Set-up
The Advanced CMOS Set-up allows the user to configure more advanced parts
of memory operation and peripheral support. These options are discussed on
page 20.
Advanced Chipset Set-up
The Advanced Chipset configures the UMC 82C491 specific features and is
discussed further on page 25.
Dx-1 Extended Set-up
The DX-1 Extended Set-up configures the on-board floppy, IDE, serials and
parallel devices. These are all controlled by the SMC 37C663 device. In addition
it provides configuration of the Quick Disk SSD and Daughter Board SSD
facilities. These options are discussed further on page 34.
Utilities
The AMIBIOS provides support for Password security access. This will be
discussed further on page 37.
Blue Chip Technology Ltd
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Page 14
BIOS
Running the AMIBIOS Set-up
The system parameters (such as amount of memory, disk drives, video displays
and numeric co-processors) are stored in CMOS RAM. When the DX1 is turned
off, a back-up battery on-board the DX1 provides power to the CMOS RAM,
thereby retaining the system parameters.
Each time the DX1 is powered-on, it is configured with these values, unless the
CMOS RAM has been corrupted. The AMIBIOS Set-up resides in the ROM
BIOS and is available each time the DX1 is switched on.
If, for some reason, the CMOS RAM becomes corrupted, the system is re
configured with the default values stored in the System BIOS. There are two sets
of BIOS values stored in the BIOS: the BIOS default values and the Power-On
default values.
The Power-on default settings consist of the safest set of parameters. These
settings should be used if the system is behaving erratically. They should work in
the majority of cases but do not provide optional system performance
characteristics.
Accessing Set-up
Set-up is accessed by pressing the 'DEL' key on the keyboard when the screen
displays the message:
Hit <DEL> if you want to run Set-up
If you press 'DEL' too late, reset the DX1 and try again.
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Blue Chip Technology Ltd
BIOS
Page 15
Set-up Key Use
Keystroke
Esc
®,¬,­ and ¯
<PgUp> and
<PgDn>,
<Ctrl><PgUp>,
<Ctrl><PgDn>
<F1>
<F2>
<F3>
<F5>
<F6>
<F7>
<F10>
Action
Returns to the previous screen.
Move the cursor from one option to the next.
Modify the default value of the options for the highlighted parameter.
If there are fewer than 10 options, <Ctrl><PgUp> and <Ctrl><PgDn>
operate like <PgUp> and <PgDn>.
<Ctrl> can also be used to increment a setting.
Displays help.
Changes background colours.
Changes foreground colours.
Restores the values resident when the current Set-up session began.
These values are taken from the CMOS RAM if it was uncorrupted at
the start of the session. Otherwise, the AMIBIOS Set-up default values
are used.
Loads all features in the Advanced CMOS Set-up/Advanced Chipset
Set-up with the AMIBIOS Set-up defaults.
Loads all features in the Advanced CMOS Set-up/Advanced Chipset
with the Power-On defaults.
Saves all the changes made to Set-up and continues the boot process.
The DX1 AMIBIOS Set-up main Menu is shown below. The options are selected
by using the ­ and ¯ keys and then pressing <Enter> .
AMIBIOS SET-UP PROGRAM - BIOS SET-UP UTILITIES
Copyright 1993 (c) American Megatrends, Inc. All Rights Reserved
STANDARD CMOS SET-UP
ADVANCED CMOS SET-UP
ADVANCED CHIP SET SET-UP
DX-1 EXTENDED SET-UP
AUTO CONFIGURATION WITH BIOS DEFAULTS
AUTO CONFIGURATION WITH POWER ON DEFAULTS
PERIPHERAL SET-UP
CHANGE PASSWORD
AUTO DETECT HARD DISK
HARD DISK UTILITY
WRITE TO CMOS AND EXIT
DO NOT WRITE TO CMOS AND EXIT
Standard CMOS Set-up for changing Time, Date, Hard Disk Type, etc.
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BIOS
Each option is described in detail on the pages identified as follows:
Main Menu Option
Described on Page
STANDARD CMOS SET-UP
ADVANCED CMOS SET-UP
ADVANCED CHIP SET SET-UP
DX-1 EXTENDED SET-UP
AUTO CONFIGURATION WITH BIOS DEFAULTS
AUTO CONFIGURATION WITH POWER ON DEFAULTS
CHANGE PASSWORD
AUTO DETECT HARD DISK
HARD DISK UTILITY
WRITE TO CMOS AND EXIT
DO NOT WRITE TO CMOS AND EXIT
17
20
25
34
37
37
37
38
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Using the CMOS Set-up Program
The default condition for the CMOS Set-up Menu is as shown below. This menu
sets the basic system parameters, such as date, time, floppy disk and hard disk
types. By using the ¬­¯® keys you can select the parameter to be changed.
Once positioned on the parameter to be modified the <PgUp> and <PgDn> keys
rotate the available options. The value selected when the menu is exited is the
one that will be written to CMOS, should you decide to commit your changes to
CMOS.
ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
º
AMIBIOS SETUP PROGRAM - STANDARD CMOS SETUP
º
º
(C)1993 American Megatrends Inc., All Rights Reserved
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
º
º
º Date (mn/date/year): Tue, Jan 01 1980
Base Memory : 640KB
º
º Time (hour/min/sec): 00 : 00 : 00
Ext. Memory : 4096 KB
º
º
Cyln Head WPcom LZone Sect Size
º
º Hard Disk C: Type : Not Installed
º
º Hard Disk D: Type : Not Installed
º
º Floppy Drive A:
: 1.44 MB, 3«"
ÉÍÍÍÑÍÍÍÑÍÍÍÑÍÍÍÑÍÍÍÑÍÍÍÑÍÍ͹
º Floppy Drive B:
: Not Installed
ºSun³Mon³Tue³Wed³Thu³Fri³Satº
º Primary Display
: VGA/PGA/EGA
ÌÍÍÍØÍÍÍØÍÍÍØÍÍÍØÍÍÍØÍÍÍØÍÍ͹
º Keyboard
: Installed
º 30³ 31³ 1³ 2³ 3³ 4³
5º
º
ÇÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄĶ
º
º 6³ 7³ 8³ 9³ 10³ 11³
12º
º
ÇÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄĶ
º
ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
Í» º 13³ 14³ 15³ 16³ 17³ 18³ 19º
º º Month : Jan, Feb,.....Dec
º
ÇÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄĶ
º º Date : 01, 02, 03,...31
º º 20³ 21³ 22³ 23³ 24³ 25³
26º
º º Year : 1901, 1902,...2099
º
ÇÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄĶ
º
ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ͼ º 27³ 28³ 29³ 30³ 31³ 1³ 2º
º
ÇÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄĶ
º
º 3³ 4³ 5³ 6³ 7³ 8³
9º
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BIOS
ȵ ESC:Exit ¯®­¬:Select F2/F3:Color PU/PD:Modify
ÆÊÍÍÍÏÍÍÍÏÍÍÍÏÍÍÍÏÍÍÍÏÍÍÍÏÍÍͼ
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Page 19
Date
This entry allows you to set the Date, Month and Year. Ranges for each value
are shown in the lower left corner of the CMOS Set-up Screen.
Time
This entry allows you to set the Hours, Minutes and Seconds. The clock operates
in 24 hour mode; that means that for a PM time add 12 to the hour
e.g. enter 6:35 PM as 18:35:00.
Floppy Disk Configuration
The DX1 supports None, 360KB, 720KB, 1.2MB, 1.44MB & 2.88MB drives.
The BIOS supports two drives A: and B:
Hard Disk Configuration
Two hard disk drives are supported directly by the BIOS, C: and D:. Each drive
can select drive types from 1 to 46. In addition type 47 is user definable allowing
customised parameters for the drive to be entered. Both drives can be set to a
different type 47 if required. To set the values for type 47 use the ¬,­,¯ and ®
keys to select the appropriate field and then type in as required. A complete list
of the 46 hard disk type is contained in the Technical Reference section of this
manual on page 49.
Display
This entry allows the user to select MDAä (monochrome), CGAä or
EGA/PGA/VGA display controllers.
If your system is to operate without a display then select Disabled. Failure to do
this will result in an error being generated during the power-on diagnostics check.
Keyboard
The DX1 keyboard interface can be connected to either AT or PS/2 keyboards.
The default setting is Enabled. If your system is to operate without a keyboard
then select Disabled. Failure to do this will result in an error being generate
during the power-on diagnostics check.
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BIOS
Using the Advanced CMOS Set-up
The default condition for the Advanced CMOS Set-up Menu is as shown below.
By using the ¬­¯® keys you can select the parameter to be changed. Once
positioned on the parameter to be modified the <PgUp> and <PgDn> keys rotate
the available options. The value selected when the menu is exited is the one that
will be written to CMOS, should you decide to commit your changes to CMOS.
ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
º
AMIBIOS SETUP PROGRAM - ADVANCED CMOS SETUP
º
º
(C)1993 American Megatrends Inc., All Rights Reserved
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍËÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
º Typematic Rate Programming : Enabled º BootSector Virus Protection: Disabled º
º Typematic Rate Delay (msec): 500
º CPU Internal Clock Mode
: 1X
º
º Typematic Rate (Chars/Sec) : 30
º IDE Block Mode Transfer
: Disabled º
º Above 1 MB Memory Test
: Disabledº IDE Standby mode
: Disabled º
º Memory Test Tick Sound
: Enabled º Auto Key-Lock Timeout
: Disabled º
º Memory Parity Error Check : Enabled º
º
º Hit <DEL> Message Display : Enabled º
º
º Hard Disk Type 47 RAM Area : 0:300 º
º
º Wait For <F1> If Any Error : Enabled º
º
º System Boot Up Num Lock
: On
º
º
º Numeric Processor Test
: Enabled º
º
º Weitek Processor
: Absent º
º
º Floppy Drive Seek At Boot : Enabled º
º
º System Boot Up Sequence
: A:, C: º
º
º System Boot Up CPU Speed : High
º
º
º External Cache Memory
: Enabled º
º
º Internal Cache Memory
: Enabled º
º
º Password Checking Option : Setup º
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÊÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
ÌÍÍÍÍÍ͵ ESC:Exit ¬­®¯:Sel (Ctrl)Pu/Pd:Modify F1:Help F2/F3:Color
ÆÍÍÍÍÍÍ͹
ÈÍÍÍÍÍÍ͵ F5:Old Values F6:BIOS Setup Defaults F7:Power-On Defaults
ÆÍÍÍÍÍÍͼ
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Page 21
Help Screens
Help can be invoked at any time by pressing <F1>.
Typematic Rate Programming, Typematic Rate Delay and Typematic Rate
The control of Typematic Rate Programming allows the auto repeat and delay
before repeat to be selected. The defaults are as shown above. The Typematic
Rate Delay describes the delay before auto repeat starts. The Typematic Rate is
the frequency of the key generation once in auto repeat.
Above 1MB Memory Test
By enabling this test any RAM above 1MB will be exercised by the POST
diagnostics thereby taking longer to boot. If your DX1 is not fitted with more
than 1MB of RAM or you wish to shorten the boot time set this option to
disabled. If you wish to ensure maximum DRAM integrity then set this option to
Enabled.
Memory Test Tick Sound
This option selects whether an audible indication of the presence of memory
during the POST is generated or not. Once either <ESC> or <DEL> is depressed
the audio is disabled
Memory Parity Error Check
This option selects whether the parity circuit is active on the system RAM. We
strongly recommend that this is set to enabled at all times thereby providing
communication of any RAM corruption. If this option is not required select
disabled. This option must be set if you are using SIMM units without parity bits
i.e. 32 bits wide.
Hit <DEL> Message Display
Disabling this option removes this message prompt from appearing during
power-up. This may be required when you do not wish to draw attention to
existence of the Setup Menus within the BIOS. The default is enabled.
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BIOS
Hard Disk Type 47 RAM Area
As described in the Set-up details previously the AMIBIOS supports type 47 user
definable input. This data is stored at either:
0:300h in lower system RAM
or
The top 1KB of applications memory
If the latter is selected the information will be stored in shadow RAM if
shadowing is enabled.
Wait for <F1> If any Error
If any of the tests run during the POST cause an error then this message will be
displayed. If this message is enabled then after displaying it the DX1 will halt
waiting for <F1> to be pressed. If you expect errors during the POST or do not
wish the boot to be halted if any error occurs then disable this option.
System Boot Up Num Lock
If you wish the numeric keypad to be active after a boot then select ON. If,
however, you wish the ¬,­,¯ and ® keys to be available after power-up then
set this option to OFF.
Numeric Processor Test
This option enables or disables the AMIBIOS test for a maths co-processor. The
settings are Enabled or Disabled.
Floppy Drive Seek at Boot
If enabled, a seek is performed on floppy drive A: at system boot time. The
options are Enabled or Disabled. By disabling this option the boot time can be
reduced. If very old 360KB drives are used it may be necessary to enable this
option to ensure that the heads are recalibrated before any data is accessed.
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System Boot Up Sequence
The default boot sequence is drive A: and then C:. This would mean that if drive
A: is not ready then the boot occurs from C:. The alternative is to boot from drive
C: and if C: is not ready then drive A. Hence the settings are either:
A:, C: or C:, A:.
External Cache Memory
The default is Enabled. If your DX1 is configured with external cache (256KB)
then this will then be used. The option is to Disable the cache.
Internal Cache Memory
This option enables the CPU internal cache memory. The settings are Enabled or
Disabled. The BIOS Set-up default is Enabled.
Turbo Switch Function
This option enables the externally mounted hardware Turbo switch. the settings
are Enabled or Disabled. The default is Enabled. Always ensure that a switch is
connected when the setting is Enabled so that noise does not cause false selection
of speed states.
Fast Gate A20 Option
Gate A20 controls the method of accessing memory addresses above 1 MB by
enabling or disabling access to the processor line A20. To provide XT
compatibility address line A20 must always be low and therefore the option
should be Disabled. However, some applications both enter protected mode and
shut down through the BIOS. For this software, Gate A20 must be constantly
enabled and disabled via the keyboard controller (8042), which slows down the
processing.
Fast Gate A20 is another method for handling Gate A20 using the UMC491
internal circuitry. It speeds programs that constantly change from addressing
conventional memory to addressing memory addresses above 1MB (from real
mode to protected mode and back). Network operating systems in particular
benefit from this enhanced circuitry.
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BIOS
Password Checking Option
This option enables a password check every time the systems boots or Set-up is
executed. The settings are Always or Set-up. If Always is selected the user
password prompt appears every time the system is turned on. If Set-up is chosen,
the password prompt appears if Set-up is executed.
ROM Shadow
ROM shadow is a technique in which the BIOS code is copied from slower ROM
to faster RAM. The BIOS is then executed from the RAM.
For each of the areas of memory identified in the Set-up table the option is there
to Enable or Disable shadowing for that particular area. The default is that both
the Video and System areas are shadowed. Care must be taken where expansion
cards are occupying an area that is set for shadowing. If the expansion card has
its own internal RAM located at the address that is shadowed then its operation
will be corrupted (examples are network cards). For such cards the setting should
be Disabled.
Boot Sector Virus Protection
When enabled, the BIOS issues a warning when any program or Virus issues a
Disk Format command or attempts to write to the boot sector of the hard disk.
The settings are Enabled or Disabled.
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Using the Advanced Chipset
The default condition for the Advanced Chipset Set-up Menu is as shown below.
By using the ¬­¯® keys you can select the parameter to be changed. Once
positioned on the parameter to be modified the <PgUp> and <PgDn> keys rotate
the available options. The value selected when the menu is exited is the one that
will be written to CMOS, should you decide to commit your changes to CMOS.
ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
º
AMIBIOS SETUP PROGRAM - ADVANCED CHIPSET SETUP
º
º
(C)1993 American Megatrends Inc., All Rights Reserved
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍËÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
º AUTO Config Function
: Enabled º Memory Remapping
: Enabled º
º
Cache Read Option
: 3-1-1-1 º F Segment Shadow RAM
: Into-486 º
º
Cache Write Option : 1 W.S. º E Segment Shadow RAM
: Disabled º
º
DRAM Type
: FastPageº C000-C3FF Shadow RAM
: Into-486 º
º
DRAM Wait State(s) : 1 W.S. º C400-C7FF Shadow RAM
: Into-486 º
º
Keyboard Clock Select: CPUCLK/4º C800-CBFF Shadow RAM
: Disabled º
º
AT Clock Select
: CPUCLK/4º CC00-CFFF Shadow RAM
: Disabled º
º
IO Recovery Time
: 5/3 BCLKº D000-D3FF Shadow RAM
: Disabled º
º
Hold PD Bus
: 1~2 T º D400-D7FF Shadow RAM
: Disabled º
º Refresh Cycle
: Slow
º D800-DBFF Shadow RAM
: Disabled º
º CoProcessor Ready
: Delay 1Tº DC00-DFFF Shadow RAM
: Disabled º
º Check ELBA# Signal
: in T2 º Refresh Divider
: 1
º
º Non-Cacheable Block1 Enable: Disabledº Data Location of Local Bus : PD Bus º
º Non-Cacheable Block-1 Size : 4MB
º LOWA20#,RC Emulation
: Both
º
º Non-Cacheable Block-1 Base : 0KB
º Stretch 0WS# Signal Option : Do Not º
º Non-Cacheable Block2 Enable: Disabledº Hardware Parity Check
: Enabled º
º Non-Cacheable Block-2 Size : 16MB
º
º
º Non-Cacheable Block-2 Base : 0KB
º
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÊÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
ÌÍÍÍÍÍÍ͵ ESC:Exit ¯®­¬:Sel (Ctrl)Pu/Pd:Modify F1:Help F2/F3:Color
ÆÍÍÍÍÍÍ͹
ÈÍÍÍÍÍÍ͵ F5:Old Values F6:BIOS Setup Defaults F7:Power-On Defaults
ÆÍÍÍÍÍÍͼ
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BIOS
Auto Config Function
The settings are Auto or Manual. If this option is set to Enabled, the following
ADVANCED CHIPSET SET-UP options are automatically configured to
optimal settings by AMIBIOS based on the DX1 and CPU frequency:
Cache Read Option,
Cache Write Option,
DRAM Type,
DRAM Wait State(s),
Keyboard Clock Select,
AT Clock Select, and
IO Recovery Time of ISA/PCB.
Hold PD Bus,
Cache Read Option
The settings are 3-2-2-2, 3-1-1-1, or 2-1-1-1.
Cache Write Option
This option sets the number of wait states inserted before all write operations to
secondary cache memory. The settings are 0 W/S, 1 W/S, or 2 W/S. The BIOS
Set-up default is 1 W/S. The Power-On default is 2 W.S.
DRAM Type
This option specifies the type of DRAM used for system memory. The settings
are Page Mode or Fast Page.
DRAM Wait State(s)
This option sets the number of wait states inserted before all DRAM system
memory operations. The settings are 0 W.S., 1 W.S., or 2 W.S.
Keyboard Clock Select
This option sets the source of the keyboard clock. The settings are CPUCLK/6,
CPUCLK/5, CPUCLK/4, CPUCLK/3, CPUCLK/2, 9.5 MHz, or 7.2 MHz.
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AT Clock Select
This option sets the source of the AT Clock (ATCLK). The settings are
CPUCLK/6, CPUCLK/5, CPUCLK/4, CPUCLK/3, CPUCLK/2, CPUCLK/8, or
7.2 MHz.
IO Recovery Time
The settings are 0/0 BCLK, 1/1 BCLK, 2/2 BCLK, 3/3 BCLK, 5/2 BCLK, 7/3
BCLK, 9/3 BCLK, 12/3 BCLK, 5/5 BCLK, 7/7 BCLK, 9/9 BCLK, or
12/12BCLK.
Hold PD Bus
The settings are 1~2 T or 2~3 T.
Refresh Cycle
The settings are Slow or Fast.
Coprocessor READY
This option sets the length of the delay of the coprocessor READY# signal. The
settings are Delay 1T or No Delay.
Check ELBA# Signal
This option sets the length of the delay before the ELBA# signal is checked. The
settings are in T1 or in T2.
Non-cacheable Block1 Enable
Non-cacheable Block2 Enable
If disabled, the contents of the specified block of system memory cannot be
written to or read from cache memory. These options permit the user to specify
an area of memory (Block-1 or Block-2) that cannot be cached. The settings are
Enabled or Disabled.
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BIOS
Non-cacheable Block-1 Base
Non-cacheable Block-2 Base
These options set the base address (or beginning) of areas of memory whose
contents cannot be written to or read from cache memory. The base address must
begin on a boundary equal to the Non-cacheable Block Size setting. The settings
are 0 KB through 16384 KB.
Memory Remapping
If this option is enabled, the contents of system memory between A0000h and
FFFFFh that have not been shadowed to RAM from ROM are moved to the top
of system memory. The settings are Enabled or Disabled.
E Segment Shadow RAM
This option specifies if the contents of the ROM memory segment from E0000 EFFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
01270173.doc
Description
The contents of E0000h - EFFFFFh are shadowed from ROM to
RAM and can be written to or read from the internal cache
memory on the 486, but not to external (secondary) cache
memory.
The contents of E0000h - EFFFFFh are shadowed from ROM to
RAM and can be written to or read from cache memory.
The contents of E0000h - EFFFFFh cannot be shadowed from
ROM to RAM and cannot be written to or read from cache
memory.
The contents of E0000h - EFFFFFh are shadowed from ROM to
RAM but cannot be written to or read from cache memory.
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F Segment Shadow RAM
This option specifies if the contents of the ROM memory segment from F0000 FFFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of F0000h - FFFFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of F0000h - FFFFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of F0000h - FFFFFFh cannot be shadowed from ROM to
RAM and cannot be written to or read from cache memory.
The contents of F0000h - FFFFFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
C000-C3FF Shadow RAM
This option specifies if the contents of the ROM memory area from C0000 C3FFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of C0000h - C3FFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of C0000h - C3FFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of C0000h - C3FFFFh cannot be shadowed from ROM to
RAM and cannot be written to or read from cache memory.
The contents of C0000h - C3FFFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
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BIOS
C400-C7FF Shadow RAM
This option specifies if the contents of the ROM memory area from C4000 C7FFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of C4000h - C7FFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of C4000h - C7FFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of C400h - C7FFFh cannot be shadowed from ROM to
RAM and cannot be written to or read from cache memory.
The contents of C400h - C7FFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
C800-CBFF Shadow RAM
This option specifies if the contents of the ROM memory area from C8000 CBFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
01270173.doc
Description
The contents of C8000h - CBFFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of C8000h - CBFFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of C8000h - CBFFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of C8000h - CBFFFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
Blue Chip Technology Ltd
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Page 31
CC00-CFFF Shadow RAM
This option specifies if the contents of the ROM memory area from CC000 CFFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of CC000h - CFFFFFh are shadowed from ROM to
RAM and can be written to or read from the internal cache memory on
the 486, but not to external (secondary) cache memory.
The contents of CC000h - CFFFFFh are shadowed from ROM to
RAM and can be written to or read from cache memory.
The contents of CC000h - CFFFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of CC000h - CFFFFFh are shadowed from ROM to
RAM but cannot be written to or read from cache memory.
D000-D3FF Shadow RAM
This option specifies if the contents of the ROM memory area from D0000 D3FFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of D0000h -D3FFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of D0000h - D3FFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of D0000h - D3FFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of D0000h - D3FFFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
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BIOS
D400-D7FF Shadow RAM
This option specifies if the contents of the ROM memory area from D4000 D7FFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of D4000h -D7FFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of D4000h - D7FFFFh are shadowed from ROM to RAM
and can be written to or read from cache memory.
The contents of D4000h - D7FFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of D4000h - D7FFFFh are shadowed from ROM to RAM
but cannot be written to or read from cache memory.
D800-DBFF Shadow RAM
This option specifies if the contents of the ROM memory area from D8000 DBFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
01270173.doc
Description
The contents of D8000h -DBFFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of D8000h - DBFFFFh are shadowed from ROM to
RAM and can be written to or read from cache memory.
The contents of D8000h - DBFFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of D8000h - DBFFFFh are shadowed from ROM to
RAM but cannot be written to or read from cache memory.
Blue Chip Technology Ltd
BIOS
Page 33
DC00-DFFF Shadow RAM
This option specifies if the contents of the ROM memory area from DC000 DFFFFh are shadowed to RAM and if these contents can be stored in cache
memory.
Setting
Into-486
Cached
Disabled
Enabled
Description
The contents of DC000h -DFFFFFh are shadowed from ROM to RAM
and can be written to or read from the internal cache memory on the
486, but not to external (secondary) cache memory.
The contents of DC000h - DFFFFFh are shadowed from ROM to
RAM and can be written to or read from cache memory.
The contents of DC000h - DFFFFFh cannot be shadowed from ROM
to RAM and cannot be written to or read from cache memory.
The contents of DC000h - DFFFFFh are shadowed from ROM to
RAM but cannot be written to or read from cache memory.
Refresh Divider
The settings are 1, 2, 4, 8, 16, 32, or 64.
Data Location of Local Bus
The settings are ISA Bus or PD Bus.
LOWA20#, RC Emulation
The settings are None, GA20, or Both.
Stretch 0WS# Signal Option
The settings are Do Not or ½ ATCLK.
Hardware Parity Check
When this option is set to Enabled, the AMIBIOS enables the hardware parity
check. The settings are Enabled or Disabled.
Blue Chip Technology strongly advise that this is enabled to improve data
integrity at all times when using SIMM units with parity bits i.e. 36 bits.
Blue Chip Technology Ltd
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BIOS
Using the DX-1 Extended Set-up
The default condition for the DX-1 Extended Set-up Menu is as shown below. By
using the ¬­¯® keys you can select the parameter to be changed. Once
positioned on the parameter to be modified the <PgUp> and <PgDn> keys rotate
the available options. The value selected when the menu is exited is the one that
will be written to CMOS, should you decide to commit your changes to CMOS.
ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
º
AMIBIOS SETUP PROGRAM - DX1 SETUP
º
º
(C)1993 American Megatrends Inc., All Rights Reserved
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍËÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
º Programming Option
: Auto
º
º
º On-Board Floppy Drive
: Enabled º
º
º On-Board IDE Drive
: Enabled º
º
º First Serial Port Address : 3F8H
º
º
º Second Serial Port Address : 2F8H
º
º
º Parallel Port Address
: 378H
º
º
º IRQ Active State
: High
º
º
º Parallel Port Mode
: Normal º
º
º First Serial Port Mode
: RS232 º
º
º First Serial Port 485 Mode : FULL
º
º
º Second Serial Port Mode
: RS232 º
º
º Second Serial Port 485 Mode: FULL
º
º
º Quik Disk Boot ROM
: Disabledº
º
º SSD Boot ROM
: Disabledº
º
º CardTrick Boot ROM
: Disabledº
º
º BIOS Extensions
: Disabledº
º
º
º
º
º
º
º
ÌÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÊÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ͹
ÌÍÍÍÍÍÍ͵ ESC:Exit ¯®­¬:Sel (Ctrl)Pu/Pd:Modify F1:Help F2/F3:Color
ÆÍÍÍÍÍÍ͹
ÈÍÍÍÍÍÍ͵ F5:Old Values F6:BIOS Setup Defaults F7:Power-On Defaults
ÆÍÍÍÍÍÍͼ
Programming Option
The options are Manual and Automatic. During the POST the BIOS identifies all
peripherals in the system. If automatic mode is selected then the items shown in
the previous screen plot will be mapped around those found by the POST. This
mode will override all the settings shown in the screen plot.
In manual mode you have control as to how the following functions are
configured.
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BIOS
Page 35
On-Board Floppy Drive
This option enables the floppy controller on the DX1. This setting can either be
Enabled or Disabled.
On-Board IDE Drive
This option enables the IDE controller on the DX1. This setting can either be
Enabled or Disabled.
First Serial Port Address
This option allows the first serial port address to be configured as either:
03F8h (Com1), 03E8h (Com3), or Disabled
The interrupt selection will be made automatically to:
Com1 and 3 will be Interrupt 4
Disabled will remove the Interrupt connection.
Second Serial Port Address
This option allows the second serial port address to be configured as either:
02F8h (Com2), 02E8h (Com4) or Disabled
The interrupt selection will be made automatically to:
Com 2 and 4 will be Interrupt 3
Disabled will remove the Interrupt connection.
Parallel Port Address
This option allows the parallel port address to be configured as:
03BCh (LPT1), 0378h (LPT1), 0278h (LPT2) or
Disabled
The interrupt selection is made using J11:
For LPT1 J11 should be set to across 1-2 (Interrupt 7)
For LPT2 J11 should be set to across 2-3 (Interrupt 5)
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BIOS
Parallel Port Mode
This option can be either Normal or Extended. Normal setting is for standard
printer operation. Extended setting provides bi-directional operation.
IRQ Active State
This option can be set as either High or Low.
First Serial Port Mode
The DX-1 provides software control of the serial port modes. The settings can be
RS232 or RS485(422). The power-up condition of both serial ports is controlled
by the BIOS Set-up. The default is RS232. Please note that RS485 connections
for both the serial ports are made through a special connector (P4).
First Serial Port 485 Mode
Once the serial mode is set to RS485 the port can be configured as either Half or
Full duplex. Half duplex is a 2 wire implementation whilst Full duplex is a 4 wire
system. The default is Full.
Second Serial Port Mode
The DX-1 provides software control of the serial port modes. The settings can be
RS232 or RS485(422). The power-up condition of both serial ports is controlled
by the BIOS Set-up. The default is RS232. Please note that RS485 connections
for both the serial ports are made through a special connector (P4).
Second Serial Port 485 Mode
Once the serial mode is set to RS485 the port can be configured as either Half or
Full duplex. Half duplex is a 2 wire implementation whilst Full duplex is a 4 wire
system.
Quick Disk Boot Rom
This option allows the selection of the On-board Flash & SRAM Solid State Disk
(SSD) located in two 32 pin bytewide sockets found below the EPROM device.
SSD Boot Rom
This option allows the selection of the optional Daughter Board Flash & SRAM
Solid State Disk (SSD) unit if fitted to connectors P17 (XT) & P10 (SSD).
Note:
The Quick Disk Silicon Disk and the Daughter Board Silicon Disk
options should not be Enabled at the same time. This will cause an
error during power-up.
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BIOS
Page 37
CardTrick Boot Rom
This option allows the selection of the Flash device to act as a bootable disk
drive. Please contact Blue Chip Technology for further information.
BIOS Extensions
The DX-1 provides Solid State Disk (SSD) BIOS support via an Expansion
ROM located at memory addresses C800:0 to CBFF:F (16KB). This BIOS
Expansion ROM must be enabled for either the On-board SSD or Daughter
Board SSD devices to operate. If you do not require SSD operation you should
Disabled this option, thereby releasing 16KB of higher memory.
Auto Configuration with Defaults
By selecting this option you automatically configure the system using the default
values. These values are worst case values for system performance, but are the
most stable values in the harsh conditions where we expect our products to be
used. If you experience any erratic problems with DX1 we strongly suggest that
you configure with default values and test the system again.
Change Passwords
The Hi-Flex AMIBIOS has an optional password feature. The system can be
configured so that you have to enter a password every time the system boots or
when the AMIBIOS Set-up is executed.
Bypassing Password Support
You can bypass the password support by pressing <Enter> when the password
prompt appears.
Enabling Password Support
The password check option is enabled in Advanced CMOS Set-up by choosing
either Always or Set-up. The password, which can up to 6 characters in length, is
stored in CMOS RAM.
If a Password is Used
You must type correctly the current password when
'enter CURRENT Password'
Blue Chip Technology Ltd
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BIOS
appears. After the current password has been correctly entered, the user is asked
to retype it.
If the password information is incorrect, an error message appears. If the new
password confirmation is entered without error, the end user presses <Esc> to
return to the Main Set-up Menu.
Password Storage
The password is stored in CMOS RAM after Set-up completes. The next time the
systems boots, you must enter the password if the password function is present
and has been enabled.
Password Options Control Prompt
Enter CURRENT Password
appears if the Password Option is enabled.
When and if the prompt appears is dependent upon the options chosen in the
Advanced CMOS Set-up. If Always was set the prompt appears every time the
system is powered on. If Set-up was set the prompt will not appear when the
system is powered on, but is displayed when Set-up is run.
Using a Password
You should keep a record of the new password when the password is changed. If
you forget the password and password protection is enabled; the only way to boot
the system will be to disable the CMOS RAM. This is achieved on the DX1 by
setting J15 across pins 2-3 (CLR) for approximately 2 minutes. Ensure that J15 is
reset across position 1-2 (NORM) before powering on the system.
Note: All CMOS RAM contents will be lost as a result of this action.
It is important that you keep a record of any changes you make to
any of the Set-up screens so that they will not be lost forever.
Auto Detect Hard Disk
This option detects the hard disk parameters for non-standard hard disk drives
ESDI or IDE interfaces. It displays the parameters that it detects and allow the
you to accept or reject the parameters. If accepted, these parameters are displayed
for the hard disk drive in Standard CMOS Set-up.
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BIOS
Page 39
Note that when an Auto Detect is run on a drive which is not present (drive D: in
most systems) then there will be a delay before the test is completed. Pressing
the ESC key will override this delay.
Write to CMOS and Exit
The configuration settings in Standard Set-up, Advanced CMOS Set-up,
Advanced Chipset Set-up, Peripheral Set-up, Password and Auto Detect Hard
Disk are stored in the CMOS RAM when this option is selected. A CMOS RAM
checksum is calculated and written to CMOS RAM; control is then passed to the
BIOS. You are asked to confirm or deny the action by entering either <Y> or
<N>. Press <Y> and <Enter> to save the new system parameters and continue
the boot process. Press <N> and <Enter> to return to the Main Menu.
Do Not Write to CMOS and Exit
This option passes control to the ROM BIOS without writing any changes to the
CMOS RAM.
Press <Y> and <Enter> to continue the boot process without saving any system
parameters changed in Set-up. Press <N> and <Enter> to return to the Main
Menu.
Blue Chip Technology Ltd
01270173.doc
Page 40
DX1 Peripheral Components
DX1 PERIPHERAL COMPONENTS
Video
The DX1 Single Board Computer has an on-board VESA Local Bus Super VGA
controller. This is achieved using one of the following Cirrus Logic video
controllers :CL-GD5424/26/28/29. The chip used will depend upon your order
specifications.
The Video Controllers provide the following features:
·
·
·
·
·
·
·
·
·
·
·
100% hardware and software compatibility with IBMÔ VGA display
standards.
VESA Local Bus interface
Hardware cursor up to 64 x 64 pixels
Enhanced BLT Engine for GUI acceleration
Resolutions up to 1280 x 1024 x 64K colours (2MB Video Memory
required)
High performance Write Buffer architecture
1MByte Video Memory standard.
Order Time Option of 2MBytes of Video Memory avaiable.
Feature connector support
32 bit Display memory interface
132 column Text mode support
Extensive drivers are available for DOS, Windows 3.1 & OS/2.0
Should you require to disable the on-board video circuitry this can be
achieved by setting J12 to position 1-2 (DIS).
The analogue video output is presented on the condensed 15 way D-type
connector P7 located on the rear panel of the DX1. The feature connector, P6,
is a 26 way pin header located towards the top right corner of the DX1.
The following tables identify the video modes supported by the on-board video
controller and BIOS. As well as describing the resolutions and colours offered by
a mode it also presents the horizontal and vertical frequencies that will be
presented to the attached monitor in the selected mode. Please take great care to
ensure that the selected mode can be supported by your monitor, paying
particular attention to interlaced and non-interlaced modes.
01270173.doc
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DX1 Peripheral Components
Page 41
IBM Standard Video Modes
Mode
No.
VESA
No.
Colours
Char v
Row
Char
Cell
Screen
Format
Display
Mode
0,1
2,3
4,5
6
7
D
E
F
10
11
12
13
0,1
2,3
4,5
6
7
D
E
F
10
11
12
13
16/256K
16/256K
4/256K
2/256K
Mono
16/256K
16/256K
Mono
16/256K
2/256K
16/256K
256/256K
40 x 25
80 x 25
40 x 25
80 x 25
80 x 25
40 x 25
80 x 25
80 x 25
80 x 25
80 x 30
30 x 30
40 x 25
9 x 16
9 x 16
8x8
8x8
9 x 16
8x8
8 x 14
8 x 14
8 x 14
8 x 16
8 x 16
8x8
360 x 400
720 x 400
320 x 200
640 x 200
720 x 400
320 x 200
640 x 200
640 x 350
640 x 350
640 x 480
640 x 480
320 x 200
Text
Text
Graphics
Graphics
Text
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Horiz
Freq
KHz
31.5
31.5
31.5
31.5
31.5
31.5
31.5
31.5
31.5
31.5
31.5
31.5
Vert
Freq
Hz
70
70
70
70
70
70
70
70
70
60
60
70
31.5
31.5
31.5
35.2
37.8
48.1
35.2
37.9
48.1
35.5
48.3
56
58
31.5
37.9
35.5
48.3
56
58
70
70
70
56
60
72
56
60
72
87*
60
70
72
60
72
87*
60
70
72
Cirrus Logic Extended Video Modes
14
54
55
58,6A
58,6A
58,6A
5C
5C
5C
5D*
5D
5D
5D
5F
5F
60*
60
60
60
10A
109
102
102
102
103
103
103
104
104
104
104
101
101
105
105
105
105
16/256K
16/256K
16/256K
16/256K
16/256K
16/256K
256/256K
256/256K
256/256K
16/256K
16/256K
16/256K
16/256K
256/256K
256/256K
256/256K
256/256K
256/256K
256/256K
Blue Chip Technology Ltd
132 x 25
132 x 43
132 x 25
100 x 37
100 x37
100 x 37
100 x 37
100 x 37
100 x 37
128 x 48
128 x 48
128 x 48
128 x 48
80 x 30
80 x 30
128 x 48
128 x 48
128 x 48
128 x 48
8 x 16
8x8
8 x 14
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
8 x 16
1056 x 400
1056 x 350
1056 x 350
800 x 600
800 x 600
800 x 600
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1024 x 768
640 x 480
640 x 480
1024 x 768
1024 x 768
1024 x 768
1024 x 768
Text
Text
Text
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
01270173.doc
Page 42
64
64
65
65
66
66
67
6C*
6D*
71
74*
DX1 Peripheral Components
111
111
114
114
110
110
113
106
112
-
64K
64K
64K
64K
32K #
32K #
32K #
16/256K
256/256K
16M
64K
160 x 64
160 x 48
80 x 30
-
8 x 16
8 x 16
8 x 16
-
640 x 480
640 x 480
800 x 600
800 x 600
640 x 480
640 x 480
800 x 600
1280 x 1024
1280 x 1024
640 x 480
1024 x 768
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
Graphics
31.5
37.9
35.2
37.8
31.5
37.9
31.5
48
48
31.5
35.5
60
72
56
60
60
72
56
87*
87*
60
87*
denotes INTERLACED modes
# denotes 32K Direct-Colour/256 colour Mixed Mode
Shaded modes required 2MBytes of video memory fitted.
*
Video Drivers
Blue Chip Technology provide drivers for a wide range of operating systems and
popular applications. Diskettes containing drivers required for DOS & Windows
are shipped with the DX board. For other operating systems please contact Blue
Chip Technology.
Video driver installation instructions
To identify the type of video adapter present on your BCT DX1 CPU card:
From the MS-DOS command line run IDCHIP.EXE from the ‘Display drivers
& utilities’ diskette to determine the video chipset in use.
Select either the 5424 or the 5428/9 ‘MS-Windows 3.1 Drivers’ diskette
depending upon the type of chipset detected (you will not require the
other ‘MS-Windows 3.1 Drivers’ diskette).
Proceed to install the application drivers, utilities and Windows drivers as
required from the two remaining diskettes - by running INSTALL.EXE
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DX1 Peripheral Components
Page 43
Watchdog Timer
The DX1 is fitted with a simple hardware Watchdog function. It can be enabled
or disabled via software allowing the user to decide whether their application
requires protection against potential processor failure or not.
The Watchdog is controlled as follows:
I/O Hex
0101
Access
Write Only
Operator
Bit 1
0101
Read Only
Byte
Action
0 - Disable Watchdog operation
1 - Enable Watchdog operation
Read every 500mS to reset timer
If the Watchdog is enabled and I/O location 0101 hex is not read within 500ms
(500ms to 2s variation possible) the Watchdog will generate a Reset to both the
DX1 and the AT bus.
To ensure the Watchdog function is disabled on power-up/reset, a write to bit 1
of I/O location 0101H is required
MOV
MOV
OUT
DX,0101
A1, 02
DX,AL
Once enabled I/O location 0101 HEX should be read at least every 500ms
(500ms to 2 s variation possible) If this location is not read action the time-out
period a Reset will be generated to both the DX1 and the AT backplane.
E²PROM
The E²PROM is accessed through a single register at port 100HEX
The E²PROM's individual control lines are arranged as follows:
Port 100 hex
7 6
5
4
3
2
Data In
1
Clock for serial data
0
Chip Select / Data Out
Blue Chip Technology includes drivers for this function on the diskettes supplied
with the DX if you wish to access this device.
Blue Chip Technology Ltd
01270173.doc
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DX1 Peripheral Components
Serial Ports
The DX1 provides 2 serial ports. Both these ports offer 16C550 type controll
including 16 byte buffers for enhanced throughput. Both channels can be
configured as either RS232 or RS485 interfaces.
The two on board serial ports can be configured as RS232 or RS485 by writing
to I/O port 104 hex.
On power-up both the serial ports default as set in the DX-1 Extended SetUp screen in the BIOS.
Control Bit
Control Bit
Selection
0
1
0
1
0
1
0
1
Bit 0
Bit 0
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Area Of Influence
Full Duplex COM 1
Half Duplex COM 1 (485 mode)
Full Duplex COM 2
Half Duplex COM 2 (485 mode)
RS232 mode COM 1
RS485 mode COM 1
RS232 mode COM 2
RS485 mode COM 2
Port 104 hex
7
6
5
01270173.doc
4
3
232/485
COM 2
2
232/485
COM 1
1
COM 2 F/H
0
COM1 F/H
Blue Chip Technology Ltd
DX1 Peripheral Components
Page 45
Byte Wide SSD User Sockets
The two 32 pin Bytewide user sockets can be used for SRAM or FLASH devices.
Each device is mapped into an 16K page in memory and a page register selects
which 16K page within the device is currently accessible.
Socket 1 is mapped to memory address E000:0000 (top socket)
Socket 2 is mapped to memory address E400:0000 (bottom
socket)
The page control register is located at port 102Hex
Bits 0 - 4 of port 102 select one of 32 pages
Bit 5 of port 102 enables the VPP for FLASH devices when SET
There is also a device enable register at port 103Hex which will enable the
memory decode for the user sockets
Bit 0 Bit 1 Bit 2 -
0 = Enable socket 1 (E000 -> E3FF) ,
1 = disable socket 1
0 = Enable socket 2 (E400-> E7FF),
1 = disable socket 2
0 = Enable external SSD (E800->EBFF),
1 = disable external SSD
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DX1 Peripheral Components
Battery
The DX1 is fitted with an on-board Lithium battery (bottom left hand corner of
DX board). This battery provides power for the Real Time Clock, CMOS RAM
and any installed SRAM on the DX1 or its Daughter Board when there is no
power applied to the board. Under normal conditions the battery should last for
several years.
Great care should be taken with this battery; under NO circumstances should: ·
·
·
·
·
·
·
the outputs be shorted
be exposed to temperatures in excess of 100°C
be burned
be immersed in water
be unsoldered
be recharged
be disassembled
If the battery is mistreated in any way there will be a possibility of fire,
explosion. and harm.
The DX1 makes provision for an external battery to be fitted at connector P14.
This should have an output of 6 Volts, capacity of 1.8AH and be fitted with a
10K series resistor for safety.
Please see the Appendix covering the Configuration Jumpers for further details.
Backplane
The DX1 is capable of driving upto a 14 slot multilayer backplane with the
appropriate termination.
Backplanes are available with three possible types of termination:
None
Resistive
RC
- Not recommended for backplanes with more than 2/3 slots
- Recommended for small backplanes (<12 slots)
- Preferred.
The actual values of termination depend upon the particular installation. Please
contact Blue Chip Technology for assistance.
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Memory Map
Typical Memory Map for a 1MByte DX1
1MB
100000
FFFFF
BIOS/Shadow BIOS
Available for Expansion adapters
Optional SSD BIOS
Byte Wide Socket 2
Byte Wide Socket 1
F0000
EC000
E8000
E4000
E0000
DFFFF
Available
For
Expansion
adapters
Optional SSD BIOS Extension
Video BIOS/Shadow BIOS
640KB
CBFFF
C8000
C0000
BFFFF
Video
Memory
Array
A0000
9FFFF
Base Memory
00000
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DX1 Peripheral Components
Disk Drives
Floppy Drives
The DX1 has built in support for two floppy disk drives. These drives can be any
permutation of the following:
Capacity
360KB
720KB
1.2MB
1.44MB
2.88MB
Drive Size
5¼"
3½"
5¼"
3½"
3½"
The BIOS Set-up allows you to configure the drives for your installation.
A standard PC 34 way ribbon cable with twisted lines can be connected to two
drives both set as drive 1 (as opposed to 0). This is possible because the IBM
convention twists the drive select and motor control lines between the two drive
connections.
Remember that only one drive in the chain should be terminated. That should be
the drive furthest from the DX1. Without correct termination drive operation can
be unreliable. In high noise environments it may be necessary to use shielded
ribbon cable. Do not extend the cable length beyond 1 metre.
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Hard Drives (IDE)
The BCT DX1 SBC provides support for two IDE hard disk drives. The built in
BIOS support allows each drive to be selected from 46 different drive types.
In addition type 47 can be configured specifically to your requirements for each
of the two drives.
The built in Auto detection utility can be invaluable in providing an efficient
way of establishing the type of drive connected without requiring reference to
drive manuals.
Hard Disk Types
Hard disk drive types are identified by the following parameters:
Parameter
Type
Cylinders
Heads
Write
Precompensation
Landing
Zone
Sectors
Capacity
Description
A designation for a hard disk drive with predefined parameters
The number of cylinders in the disk drive.
The number of heads.
The size of a sector gets progressively smaller as the track diameter
diminishes. Yet each sector must still hold 512 bytes. Write
precompensation circuitry difference in sector size by boosting the
write current for sectors on inner tracks. This parameter is the track
number where write precompensation begins.
The number is the cylinder location where the heads normally park
when the system is shut down.
The number of sectors per track. Hard drives that use MFM have 17
sectors per track. RLL drives have 26 sectors per track. RLL and ESDI
drives have 34 sectors per track. SCSI and IDE drives may have even
more sectors per track.
The formatted capacity of the drive based on the following formula:
(Number of heads) * (Number of cylinders) * (Number of sectors per
cylinder) * (512 bytes per sector)
A table of the 46 standard hard disk types is shown on the following page.
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DX1 Peripheral Components
Type
No. of
Cylinders
No. of
Heads
Write Precompensation
Landing
Zone
No. of
Sectors
Size
MB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
306
615
615
940
940
615
462
733
900
820
855
855
306
733
4
4
6
8
6
4
8
5
15
3
5
7
8
7
305
615
615
940
940
615
511
733
901
820
855
855
319
733
17
17
17
17
17
17
17
17
17
17
17
17
17
17
10
20
31
62
47
20
31
30
112
20
35
50
20
43
612
977
977
1024
733
733
733
306
925
925
754
754
699
823
918
1024
1024
1024
612
1024
1024
615
987
987
820
977
981
830
830
917
1224
4
5
7
7
5
7
5
4
7
9
7
11
7
10
7
11
15
5
2
9
8
8
3
7
6
5
5
7
10
15
15
128
300
300
512
512
65535
256
65535
65535
65535
65535
65535
128
65535
Not Available
0
300
65535
512
300
300
300
0
0
65535
754
65535
256
65535
918
65535
65535
1024
128
65535
512
128
987
987
820
977
981
512
65535
65535
65535
663
977
977
1023
732
732
733
336
925
925
754
754
699
823
918
1024
1024
1024
612
1024
1024
615
987
987
820
977
981
830
830
918
1223
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
20
41
57
60
30
43
30
10
54
69
44
69
41
68
53
94
128
43
10
77
68
41
25
57
41
41
41
48
69
114
152
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ISA BUS & VESA LOCAL BUS DETAILS
ISA Bus Signal Descriptions
The following is a description of the ISA Bus signals. All signal lines are TTL
compatible.
AEN (O)
'Address Enable' is used to degate the microprocessor and other devices from the
I/O channel to allow DMA transfers to take place. When this line is active, the
DMA controller has control of the address bus, the data-bus Read command lines
(memory and I/O), and the Write command lines (memory and I/O).
BALE (O) (Buffered)
'Address latch enable' is provided by the bus controller and is used on the system
board to latch valid addresses and memory decodes from the microprocessor. It
is available to the I/0 channel as an indicator of a valid microprocessor or DMA
address (when used with 'AEN'). Microprocessor addresses SA0 through SAl9
are latched with the falling edge of 'BALE.' 'BALE' is forced high during DMA
cycles.
CLK (O)
This is the system clock. The clock has a 50% duty cycle. This signal should only
be used for synchronisation. It is not intended for uses requiring a fixed
frequency.
-DACKO through -DACK3 and -DACKS through -DACK7 (O)
-DMA Acknowledge 0 through 3 and 5 through 1 are used to acknowledge DMA
requests (DRQ0 through DRQ7). They are active low.
-DRQ0 through DRQ3 and DRQ5 through DRQ7 (I)
DMA Requests 0 through 3 and 5 through 7 are asynchronous channel requests
used by peripheral devices and the I/O channel microprocessors to gain DMA
service (or control of the system). They are prioritised, with DRQ0 having the
highest priority and DRQ7 having the lowest. A request is generated by bringing
a DRQ line to an active level. A DRQ line must be held high until the
corresponding 'DMA Request Acknowledge'(DACK) line goes active. DRQ0
through DRQ3 will perform 8 -bit DMA transfers; ‘DRQ5' through DRQ7 will
perform l6 bit transfers.
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-I/O CHCK (I)
'-I/O channel check' provides the system board with parity (error) information
about memory or devices on the I/O channel. When this signal is active, it
indicates an uncorrectable system error.
I/O CHRDY (I)
'I/O channel ready' is pulled low (not ready) by a memory or I/O device to
lengthen I/O or memory cycles. Any slow device using this line should drive it
low immediately upon detecting its valid address and a Read or Write command.
Machine cycles are extended by an integral number of clock cycles. This signal
should be held low for no more than 2.5 microseconds.
-I/O CS16 (I)
'-I/O 16 bit Chip Select' signals the system board that the present data transfer is a
16 bit, 1 wait state, I/O cycle. It is derived from an address decode. '- I/O CS 16'
is active low and should be driven with an open collector or tri-state driver
capable of sinking 20 mA.
-IOR (I/O)
‘-I/O Read' instructs an I/O device to drive its data onto the data bus. It may be
driven by the system microprocessor or DMA controller, or by a microprocessor
or DMA controller resident on the I/O channel. This signal is active low.
-IOW (I/O)
‘I/O Write' instructs an I/O device to read the data on the data bus. It may be
driven by any microprocessor or DMA controller in the system. This signal is
active low.
IRQ3 to IRQ7, IRQ9 to IRQ12 and IRQ14 to 15 (I)
Interrupt Requests 3 through 7, 9 through 12, and 14 through 15 are used to
signal the microprocessor that an I/0 device needs attention. The interrupt
requests are prioritised, with IRQ9 through IRQ12 and IRQ14 through IRQ15
having the highest priority (IRQ9 is the highest) and IRQ3 through IRQ7 having
the lowest priority (IRQ7 is the lowest). An interrupt request is generated when
an IRQ line is raised from low to high. The line must be held high until the
microprocessor acknowledges the interrupt request (Interrupt Service routine).
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LA17 through LA23 (I/O)
These signals (unlatched) are used to address memory and I/O devices within the
system. They give the system up to 16MB of address ability. These signals are
valid when ‘BALE' is high. LA17 through LA23 are not latched during
microprocessor cycles and therefore do not stay valid for the whole cycle. Their
purpose is to generate memory decodes for 1 wait- state memory cycles. These
decodes should be latched by I/O adapters on the falling edge of ‘BALE. ' These
signals also may be driven by other microprocessors or DMA controllers that
reside on the I/O channel.
-Master (I)
This signal is used with a DRQ line to gain control of the system. A processor or
DMA controller on the I/O channel may issue a DRQ to a DMA channel in
cascade mode and receive a '- DACK'. Upon receiving the '- DACK', an I/O
microprocessor may pull '- Master' low, which will allow it to control the system
address, data, and control lines (a condition known as tri-state). After '- Master' is
low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write
command. If this signal is held low for more than 15 microseconds, system
memory may be lost because of a lack of refresh.
-MEMCS16 (I)
'-MEM 16 Chip Select' signals the system board if the present data transfer is a 1
wait-state, 16 bit, memory cycle. It must be derived from the decode of LA17
through LA23. '-MEM CS 16' should be driven with an open collector or tri-state
driver capable of sinking 20 mA.
OSC (O)
‘Oscillator' (OSC) is a high speed clock with a 70 nanosecond period (14.31818
MHz). This signal is not synchronous with the system clock. It has a 50 % duty
cycle.
0WS (I)
The ‘Zero Wait State' (0WS) signal tells the microprocessor that it can complete
the present bus cycle without inserting any additional wait cycles. In order to run
a memory cycle to a 16 bit device without wait cycles, ‘0WS' is derived from an
address decode gated with a Read or Write command. In order to run a memory
cycle to an 8 bit device with a minimum of two wait states, ‘0WS' should be
driven active on system clock after the Read or Write command is active gated
with the address decode for the device. Memory Read and Write commands to a
8 bit device are active on the falling edge of the system clock. ‘0WS' is active
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ISA & VESA Bus Details
low and should be driven with an open collector or tri-state driver capable of
sinking 20 mA.
-Refresh (I/O)
This signal is used to indicate a refresh cycle and can be driven by a
microprocessor on the I/O channel.
Reset Drive (O)
‘Reset drive' is used to reset or initialise system logic at power up time or when
the power supply drops below its minimum level. This signal is active high.
SA0 through SAl9 (I/O)
Address bits 0 through 19 are used to address memory and I/O devices within the
system. These twenty address lines, in addition to LA17 through LA23, allow
access of up to 16MB of memory. SA0 through SAl9 are gated on the system bus
when ‘BALE' is high and are latched on the falling edge of ‘BALE. ' These
signals are generated by the microprocessor or DMA Controller. They also may
be driven by other microprocessors or DMA controllers that reside on the I/O
channel.
SBHE (I/O)
‘Bus High Enable' (system) indicates a transfer of data on the upper byte of the
data bus, SD8 through SD15. 16 bit devices use 'SBHE' to condition data bus
buffers tied to SD8 through SD15.
SD0 through SD15 (I/O)
These signals provide data bus bits 0 through 15 for the microprocessor,
memory, and I/O devices. D0 is the least significant bit and Dl5 is the most
significant bit. All 8 bit devices on the I/O channel should use D0 through D7 for
communications to the microprocessor. The l6 bit devices will use D0 through
D15. To support 8 bit devices, the data on D8 through D15 will be gated to D0
through D7 during 8 bit transfers to these devices. 16 bit microprocessor transfers
to 8 bit devices will be converted to two 8 bit transfers.
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-SMEMR (O)- MEMR (I/O)
These signals instruct the memory devices to drive data onto the data bus. 'SMEMR' is active only when the memory decode is within the low lMB of
memory space. '- MEMR' is active on all memory read cycles. '- MEMR' may be
driven by any microprocessor or DMA controller in the system. '- SMEMR' is
derived from 'MEMR' and the decode of the low lMB of memory. When a
microprocessor on the I/O channel wishes to drive '- MEMR', it must have the
address lines valid on the bus for one system clock period before driving 'MEMR' active. Both signals are active low.
-SMEMW (O)- MEMW (I/O)
These signals instruct the memory devices to store the data present on the data
bus. '- SMEMW' is active only when the memory decode is within the low 1 MB
of the memory space. '- MEMW' is active on all memory write cycles. '- MEMW'
may be driven by any microprocessor or DMA controller in the system. 'SMEMW' is derived from '- MEMW' and the decode of the low lMB of memory.
When a microprocessor on the I/O channel wishes to drive '- MEMW', it must
have the address lines valid on the bus for one system clock period before driving
'- MEMW' active. Both signals are active low.
T/C (O)
‘Terminal Count' provides a pulse when the terminal count (end of) for any DMA
channel is reached.
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ISA & VESA Bus Details
VESA Local Bus
Description
With the ever increasing performance demands of complex software applications
the PCs 8MHz ISA bus can become a bottleneck. By connecting peripheral
devices onto the processors local bus this bottleneck can be freed, opening up the
bus to the full processor bandwidth. Typical peripheral devices which benefit
from local bus are video, disks and LAN network adapters.
The DX1 is designed to be VESA VL-Bus compatible providing on board local
bus SVGA with a GUI accelerator and a VL-Bus expansion slot.
The VL-Bus specification states that up to 3 VL-Bus devices can be supported.
As the DX board has on board VL Video control a further 2 VL-Bus devices can
be added to the VL expansion slot.
Connection to this expansion slot can be achieved using Blue Chip Technology
passive backplanes.
VL-Bus Signal Definitions
RESET# - System Reset
This low asserted signal is a master reset that is asserted after system
power up and prior to any valid CPU cycles. It is driven by the DX1
card to all bus masters and targets. There is no guaranteed relationship
between the rising or falling edges of RESET# and the phase of LCLK.
LCLK - Local CPU Clock
The LCLK VL-Bus clock signal is a 1X clock that follows the same
phase as the 486 CPU. LCLK is driven by the DX1 to all VL-Bus
masters and targets. The rising edge of the clock signifies the change of
CPU states.
RDYRTN# - Ready Return
RDYRTN# establishes a handshake so the VL-Bus target knows when
the cycle has ended. RDYRTN# is driven by the DX1 to all VL-Bus
masters and targets.
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For DX1 cards with CPU speeds up to 33MHz, RDYRTN# is asserted
on the same LCLK as LRDY#. At CPU speeds greater than 33MHz,
RDYRTN# will trail LRDY# due to clock re synchronisation. During
DMA or system IO bus master cycles, the VL-Bus controller asserts
RDYRTN# for one LCLK cycle when the DMA or system IO bus
master command ends.
WBACK# - Write Back
WBACK# is currently reserved for future use on write back cache
systems.
This pin is tied high on the DX1 card.
ID[0..4] - Identifier pins
These pins allow the VL-Bus target to identify the type and speed of the
host CPU. The settings are static levels and for the DX1 processor are
set as follows:
ID0= 0 ID1=1
ID2=1
ID3=1
ID4=0
: 486 CPU.
: 0 wait state write.
: Fit link J16 for CPU speed > 33MHz.
: Reserved.
ADR[0..31] - Address Bus
The address bus furnishes the physical memory or IO port address to the
VLbus target. During VL-Bus master cycles the VLbus device acting as
bus master drives the addres bus If no VLbus target claims the transfer,
the VLbus controller drives the VLbus master address to the system.
DAT[0..31] - Data Bus
This is a bi-directional data path between VL-Bus devices and the CPU.
During read transfers the active VL-Bus target drives data onto the
DAT[0..31]. If the read is initiated from a system IO bus master or
DMA, the data is driven onto the system IO bus by the VL-Bus
controller. During write transfers the CPU, DMA slave, or bus master
drives data onto the data bus. BE[0..3] determine which byte lane(s) of
the data bus are valid.
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BE[0..3]# - Byte Enables
The byte enables indicate which byte lanes of the 32 bit data bus are
involved with the current VL-Bus transfer. BE[0..3]# are driven by the
CPU for all CPU initiated transfers. During system IO bus master or
DMA cycles the VL-Bus controller drives BE[0..3]# according to the
values of address bits 0 ,1 and SBHE#. During VL-Bus master transfers
the active bus master device drives BE[0..3}].
M/IO# - Memory/ IO Status
This CPU output indicates the type of access currently executing. A
memory cycle is indicated by M/IO# driven high, a low indicates an IO
cycle. M/IO# is driven by the CPU for all CPU initiated cycles. During
system IO bus master or DMA cycles the VL-Bus controller drives
M/IO# according to the values of MEMR#, MEMW#, IOR# and IOW#.
During VL-Bus master transfers the active bus master device drives
M/IO#.
W/R# - Write or Read Status
This CPU output indicates the type of access currently executing. A
write cycle is indicated by W/R# driven high, a low indicates an read
cycle. W/R# is driven by the CPU for all CPU initiated cycles. During
system IO bus master or DMA cycles the VL-Bus controller drives
W/R# according to the values of MEMR#, MEMW#, IOR# and IOW#.
During VL-Bus master transfers the active bus master device drives
W/R#.
D/C# - Data or Code Status
The data/code status signal indicates whether the current cycle is
transferring data or code. During VL-Bus master transfers the VL-Bus
acting as bus master drives D/C#.
BLAST# - Burst Last
This signal indicates that the next time BRDY# is asserted the burst
cycle will complete. During VL-Bus master transfers the VL-Bus acting
as bus master drives BLAST#. A VL-Bus master that does not support
burst transfers must drive this signal low whenever it controls the VLBus.
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ADS# - Address data Strobe
During ISA DMA or ISA bus master transfers the VL-Bus controller
acts as the active host on behalf of the ISA bus. ADS# is strobed by the
VL-Bus controller for one clock cycle after the address bus and status
lines are valid on the VL-Bus. During VL-Bus master transfers ADS# is
strobed by the active VL-Bus master for one clock cycle after the
address and status lines are valid.
LEADS# - Local External Address Data Strobe
The VL-Bus controller or active VL-Bus master asserts this signal
whenever an address is present on the VL-Bus that performs a CPU
cache invalidation cycle. A VL-Bus master must drive this signal while
it owns the bus.
LGNT# - Local Bus Grant
LGNT# is used in conjunction with LREQ# to establish a VL-Bus
arbitration protocol. When the VL-Bus device asserts LREQ#, the VLBus controller responds by asserting LGNT#. The active VL-Bus device
then has control of the bus and may own the bus until it no longer needs
the bus or the VL-Bus controller removes LGNT# to preempt the active
VL-Bus master.
LKEN# - Local Cache Enable
This signal is asserted if the current VL-Bus cycle is cacheable. It is
always driven by the cache controller. If LKEN# is asserted one clock
before LRDY# and held until RDYRTN# is asserted during the last read
in a cache line, the line is placed in the CPU cache.
LDEV# - Local Device
This VL-Bus target output signals the VL-Bus that the current cycle is a
VL-Bus cycle. The VL-Bus controller samples the LDEV# on the rising
edge of LCLK one cycle after ADS#. If the System bus controller
detects LDEV# asserted, the current does not start a system IO bus
cycle. For cache-hit and DRAM cycles, LDEV# is ignored.
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LRDY# - Local Ready
LRDY# begins the handshake that terminates the current
active bus cycle. The active LBT drives this LRDY# only during the
time of the cycle that it has claimed as its own. While the VL-Bus is
inactive, LRDY# is pulled high by the DX1. Since the VL-Bus is
normally a not ready bus, the CPU must wait until LRDY# is asserted
low to terminate an active VL-Bus cycle.
LBS16# - Local Bus Size 16
LBS16# forces the CPU or VL-Bus master to run multiple 16 bit
transfers to a VL-Bus target that cannot accept 32 bit data transfers in a
single clock cycle. It is a shared signal driven only by the active VL-Bus
target. While the VL-Bus is inactive this signal is pulled high.
BRDY# - Burst Ready
BRDY# terminates the current active burst cycle. BRDY# is syncronised
to LCLK and is asserted low one LCLK period at the end of each burst
transfer. If LRDY# and BRDY# are asserted at the same time, BRDY#
is ignored and the current burst cycle returns to non-burst cycles. Tri
state control of BRDY# follows the same rules as LRDY#. While the
VL-Bus is inactive this signal is pulled high.
LREQ# - Local Request
LREQ#, used in conjunction with LGNT#, is used by a VL-Bus device
to gain control of the VL-Bus and become an active local bus master.
When the VL-Bus device asserts LREQ#, the VL-Bus controller
responds by asserting LGNT#. The VL-Bus then has control of the VLBus and may hold the bus until the VL-Bus controller removes LGNT#.
While the VL-Bus is inactive this signal is pulled high.
IRQ9 - Interrupt Request Line 9
IRQ9 line is a high-asserted, level triggered interrupt that is electrically
connected to the IRQ9 on the ISA bus.
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BCT DX1 SBC I/O Address Map
Hex Range
0000 - 00lF
0020 - 003F
0040 - 005F
0060 - 006F
0070 - 007F
0080 - 008F
00A0 - 00BF
00C0 - 00DF
00F0
00F1
00F8 - 00FF
0100 - 010F
01F0 - 01F8
0200 - 0207
0278 - 027F
0208 - 021A
02E8 - 02EF
02F8 - 02FF
0300 - 031F
0360 - 036F
0378 - 037F
0380 - 038F
03A0 - 03AF
03B0 - 03DF
03E8 - 03EF
03F0 - 03F7
03F8 - 03FF
Blue Chip Technology Ltd
Device
DMA Controller 1
Interrupt Controller 1, Master
Timer & Index registers for UMC491
8042 (Keyboard & Mouse)
Real Time Clock, NMI Mask
POST & DMA Page Register
Interrupt Controller 2, Slave
DMA Controller 2
Clear Maths Coprocessor Busy
Reset Maths Coprocessor
Maths Coprocessor
Watchdog, E²PROM, Byte Wide Socket
& Software selection of serial ports
Hard (Fixed) Disk Controller
Games port
Parallel Printer Port 2
EMS Page registers ( either 208 or 218,
etc.)
Serial Port 4
Serial Port 2
Prototype Card
Reserved
Parallel Printer Port 1
SDLC, Bi-synchronous 2
Bi-synchronous 1
Video Adapter
Serial Port 3
Floppy Diskette Controller
Serial Port 1
Occupied by
DX1 (default)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
N
N
Y
N
Y
N
N
Y
N
N
Y
N
Y
Y
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ISA & VESA Bus Details
Interrupt Assignments
Interrupt
NMI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Device
Occupied on
DX1 (default)
Y
Y
Y
N
Y
Y
N
Y
Y
Y
N
N
N
Y
N
Y
N
Parity Check (generates IOCHCK on error)
Timer
Keyboard (Output Buffer Full)
Cascaded from Interrupt 9
Serial Port 2 (also 4, 6 & 8 if sharing interrupts)
Serial Port 1 (also 3, 5 & 7 if sharing interrupts)
Parallel Port 2
Floppy Diskette Controller
Parallel Port 1
Real Time Clock
VGA controller
Unassigned
Unassigned
PS/2 Mouse
Unassigned
Hard (Fixed) Disk Controller
Unassigned
DMA Assignments
DMA
Channel
0
1
2
3
4
5
6
7
01270173.doc
8/16 bit
Peripherals
8 bit
8 bit
8 bit
8 bit
16 bit
16 bit
16 bit
16 bit
Device
Used for Refresh Circuitry
Available
Diskette Drive
Available
Cascaded to 1st DMA controller
Available
Available
Available
Occupied on
DX1 (default)
Y
N
Y
N
Y
N
N
N
Blue Chip Technology Ltd
Appendix A
Page 63
APPENDIX A
POST Error Codes
The BIOS performs a Power On Self Test after a reset or reboot. During the
POST the microprocessor indicates the state of the test by writing codes to the
I/O port address 80 hex. The DX1 offers on-board decode of this information and
can drive the option POST display without modification. The following codes
indicate the progress of the microprocessor during the test.
Code
(Hex)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
20
21
22
23
Description
Processor register test starting. NMI disabled next.
NMI disabled. Power-on delay starting.
Power-on delay complete. Keyboard initialisation.
Keyboard initialisation complete.
Checking soft or cold start via keyboard SYS bit.
Enabled ROM. Calculating BIOS checksum.
Sending BAT command to the keyboard controller.
BAT command sent.
BAT verified.
Keyboard command code byte sent.
Keyboard command data byte sent.
Keyboard controller blocked and unblocked.
Keyboard controller NOP command complete.
CMOS RAM shutdown register test passed.
CMOS RAM checksum complete and the DIAG byte is written.
CMOS RAM initialised.
CMOS RAM status register initialised.
DMA and Interrupt controllers disabled.
Video display disabled.
UMC491 initialisation complete. Auto memory detection complete.
8254 timer channel 2 test half complete.
8254 timer channel 2 test complete.
8254 timer channel 1 test complete.
8254 timer channel 0 test complete.
Memory refresh started.
Memory refresh toggling test completed.
Memory refresh test at 15uS completed.
Start 64KB base memory test.
Memory address line test completed.
Memory parity toggling completed.
Base 64KB memory read/write test passed.
Blue Chip Technology Ltd
01270173.doc
Page 64
Appendix A
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
01270173.doc
System configuration before vector initialisation completed.
Interrupt vector initialisation completed.
8042 input port read. Turbo initialisation completed.
Global data initialisation done.
Initialisation complete.
Monochrome mode is set.
Colour mode set.
Parity toggle completed.
Initialise for video ROM done.
Video ROM check complete.
Complete video ROM processing.
No EGA or VGA adapter has been found.
Video display read/write test completed.
Video display read/write or retrace test failed.
Alternate video display read/write test passed.
Video display check completed.
Verification of video adapter done.
Video display mode set.
BIOS ROM data area check completed.
Cursor setting for power-on message done.
Display power-on message.
New cursor position has been read and saved.
BIOS identification string displayed.
Hit "DEL" message displayed.
Prepare virtual mode test.
Verifying display memory completed.
Descriptor tables prepared.
Entered virtual mode.
Interrupts are enabled if the diagnostics switch is on.
Data initialised for memory wrap around check.
Memory wrap around check completed. Memory size check completed.
Memory test patterns written to extended RAM.
Memory test patterns written to conventional RAM.
Memory size below 1MB established.
Memory size above 1MB established.
BIOS ROM data area check completed.
Memory below 1MB cleared via a soft reset.
Memory above 1MB cleared via a soft reset.
Memory test started. No soft reset was performed.
Memory size display has begun. The display is updated during the test.
Memory test below 1MB is completed.
Memory size has been adjusted for memory relocation above 1MB.
Memory test above 1MB complete.
CPU registers saved.
Blue Chip Technology Ltd
Appendix A
54
55
56
57
58
59
60
61
62
63
64
65
66
67
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
Page 65
CPU in real mode. Shutdown successful.
CPU registers restored.
Gate A20 address line disabled.
BIOS ROM data area check partially complete.
BIOS ROM data area check complete.
"Hit DEL" message has been cleared.
DMA page register test passed.
Display memory test completed.
DMA controller 1 test passed.
DMA controller 2 test passed.
BIOS ROM data area check partially complete.
BIOS ROM data area check complete.
DMA controllers 1&2 programmed.
8259 interrupt controller initialisation done.
Keyboard test started.
Keyboard reset command passed.
Keyboard controller interface test done.
Command byte written and global initialisation complete.
Lock key checking done.
Memory size check done.
Password has been checked.
Programming before Setup complete.
Returned from Setup program and cleared the screen.
Programming after Setup completed.
The power-on screen message is displayed.
The "Wait..." message is displayed.
System and video BIOS shadowing successful.
Setup options are programmed.
Mouse test and initialisation done.
Floppy Disk check identify that the drive needs initialising.
Floppy Disk configuration complete.
Hard Disk presence check completed.
Hard Disk configuration completed.
BIOS ROM data area check partially complete.
BIOS ROM data area check fully completed.
Memory size adjusted because of mouse support and hard disk type 47.
Display memory verified.
Pre-initialisation for expansion ROM operation completed.
Expansion ROM control test completed.
Initialisation for option ROM test completed.
Set timer data area and parallel printer base address.
Set asynchronous base addresses.
Initialisation for coprocessor test completed.
Coprocessor partially initialised.
Blue Chip Technology Ltd
01270173.doc
Page 66
Appendix A
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
00
01270173.doc
Coprocessor initialised.
Extended keyboard flags checked.
Keyboard ID command issued.
Keyboard ID flag reset has been done.
Cache memory test completed.
Soft error test completed.
Keyboard typematic rate is set.
Memory wait states set.
Screen cleared.
NMI and parity enabled.
Initialisation before E0000H adapter ROM control invoked.
E0000H adapter ROM control completed.
System configuration displayed. Passing control to INT 19H bootstrap
Loader now.
Blue Chip Technology Ltd
Appendix B
Page 67
APPENDIX B
Configuration Jumpers
Jumper
J1 and
J2
J3
J4
Area of Influence
Bypass Links for 5 volt and 3.3 volt
CPU operation.
ALE signal to IDE hard disk drive
J5
IDE Ground Link
Connects pin 34 of P2 to ground.
Serial port 1 RS485 termination
J6
Serial port 2 RS485 termination
J7
J9
This link will be hard wired and is
not to be altered without first
consulting Blue Chip Technology.
This link will be hard wired and is
not to be altered without first
consulting Blue Chip Technology.
On-board speaker Enable
J10
J11
Power Save Switch
Printer Interrupt selection
J12
On-board Video Controller
J13
CPU speed selection
A 4 by 2 row of pins exists on the
PCB. To select the required
processor frequency fit the links as
per the table.
J8
Link
AB, CD
EF, GH
None
1-2
None
1-2
None
1-2
None
1-2
None
1-2
2-3
None
1-2
2-3
None
1-2
None
1-2
2-3
None
1-2
2-3
Action
Fit ALL for 5 volt CPU,
Remove ALL for 3.3 volt CPU.
No ALE connected to IDE
interface
ALE connected to IDE interface
Pin 34 floats
Pin 34 is grounded
No termination on-board
100R & 100nF across I/P
No termination on-board
100R & 100nF across O/P
Not Allowed
Not Allowed
Factory Hard Wired
Not Allowed
Factory Hard Wired
Factory Hard Wired
On-board audio disabled
On-board audio enabled
Do not use
No interrupt selected
LPT1 (IRQ 7) selected
LPT2 (IRQ 5) selected
Not Allowed
Disabled
Enabled
Processor Frequency
20MHz
J13
= link present
= link absent
25MHz
J13
33MHz
J13
Blue Chip Technology Ltd
01270173.doc
Page 68
J14
J15
J16
Appendix B
Selects either Internal or External
Battery supply.
CMOS Memory clear
Either selects to power CMOS or
clears the CMOS and SRAM
VESA local bus speed.
01270173.doc
1-2
2-3
None
1-2
2-3
None
1-2
Selects External Battery
Selects Internal Battery
Not Allowed
Battery Connected
Clears CMOS and SRAM
VESA LB operation <=33MHz
VESA LB operation >33MHz
Blue Chip Technology Ltd
Appendix C
Page 69
APPENDIX C
Connector Details
P1: Floppy (34 way header)
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Signal
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Blue Chip Technology Ltd
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Signal
+RPM/Low Current
Not used
Not used
-Index
-Motor 0
-Drive select 1
-Drive select 0
-Motor 1
+Direction
-Step
-Write Data
-Write Gate
-Track 0
-Write Protect
-Read Data
+Head Select
+Disk Change
01270173.doc
Page 70
Appendix C
P2: Hard Drive (40 way header)
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
-Reset
Data bit 7 (HD)
Data bit 6 (HD)
Data bit 5 (HD)
Data bit 4 (HD)
Data bit 3 (HD)
Data bit 2 (HD)
Data bit 1 (HD)
Data bit 0 (HD)
0 Volts DC (Ground)
Not used
-IO Write (HD)
-IO Read (HD)
Not used
Not used
IRQ14
Address 1 (HD)
Address 0 (HD)
-Chip Select 0 (HD)
IDE LED Drive
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
0 Volts DC (Ground)
Data bit 8 (HD)
Data bit 9 (HD)
Data bit 10 (HD)
Data bit 11 (HD)
Data bit 12 (HD)
Data bit 13 (HD)
Data bit 14 (HD)
Data bit 15 (HD)
Not used
0 Volts DC (Ground)
0 Volts DC (Ground)
0 Volts DC (Ground)
ALE (HD)
0 Volts DC (Ground)
IOCS16
Ground/Float (via link)
Address 2 (HD)
-Chip Select 1 (HD)
0 Volts DC (Ground)
P3: Com 2 (10 way header)
Pin No.
1
3
5
7
9
01270173.doc
Signal
-Data Carrier Detect
Receive Data
Transmit Data
-Data Terminal Ready
0 Volts (Ground)
Pin No.
2
4
6
8
10
Signal
-Data Set Ready
-Ready To Send
-Clear To Send
-Ringing Indicator
Not used
Blue Chip Technology Ltd
Appendix C
Page 71
P4: RS422/485 Serial (10 way header)
Pin No.
1
3
5
7
9
Signal
+ve Receive Data 1
-ve Receive Data 1
+ve Transmit Data 1
-ve Transmit Data 1
0 Volts (via 10KW)
Pin No.
2
4
6
8
10
Signal
+5 Volts (via 10KW)
+ve Receive Data 2
-ve Receive Data 2
+ve Transmit Data 2
-ve Transmit Data 2
P5: Parallel (26 way header)
Note: This pinout is different from the normal 25 way 'D' type itself.
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
Signal
-Strobe
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
-Acknowledge
Busy
Paper Empty
Select (Output)
Blue Chip Technology Ltd
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
-Auto Feed XT
-Error
-Initialise
-Select (input)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Not Used
01270173.doc
Page 72
Appendix C
P6: Feature (26 way header)
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
Signal
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Enable Video
Enable Sync
Enable DAC Clock
Not Used
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Not Used
Not Used
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
Pixel Data 0
Pixel Data 1
Pixel Data 2
Pixel Data 3
Pixel Data 4
Pixel Data 5
Pixel Data 6
Pixel Data 7
Video Clock
Blanking
Horizontal Sync
Vertical Sync
0 Volts (Ground)
P7: Video (15 way condensed D type)
Pin No.
1
3
5
7
9
11
13
15
Signal
Analogue RED
Analogue BLUE
0 Volts (Ground)
0 Volts (Ground)
Not Used
Not Used
Horizontal Sync
Not Used
Pin No.
2
4
6
8
10
12
14
Signal
Analogue GREEN
Not Used
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Not Used
Vertical Sync
P8: Post (12 way header)
Pin No.
1
3
5
7
9
11
01270173.doc
Signal
AT Data bit 0
AT Data bit 2
AT Data bit 4
AT Data bit 6
POST decode
+5 Volts
Pin No.
2
4
6
8
10
12
Signal
AT Data bit 1
AT Data bit 3
AT Data bit 5
AT Data bit 7
0 Volts (Ground)
Blue Chip Technology Ltd
Appendix C
Page 73
P9: Mouse (6 pin mini DIN)
Pin No.
1
3
5
Signal
Mouse Data
0 Volts (Ground)
Mouse Clock
Pin No.
2
4
6
Signal
Not Used
+5 Volts (fused)
Not Used
P10: SSD Connector (8 way header)
Pin No.
1
3
5
7
Signal
+5 Volts
+5 Volts
BUSY
SMEMW/R
Pin No.
2
4
6
8
Signal
DEVSEL
PAGESEL2
CS_SSD
SYSRST
P11: Com 1 (9 way D)
Pin No.
1
3
5
7
9
Signal
-Data Carrier Detect
Transmit Data
0 Volts (Ground)
-Ready To Send
-Ringing Indicator
Pin No.
2
4
6
8
Signal
Receive Data
-Data Terminal Ready
-Data Set Ready
-Clear To Send
P12: Peripheral (20 way header)
Pin No.
1
3
5
7
9
11
13
15
17
19
Signal
Audio +ve
Reset +ve
High Speed LED +ve
Keylock +ve
Power LED +ve
Turbo Switch +ve
IDE LED +ve
+5V (fused)
+3.6 Volt Battery
Keyboard Data
Blue Chip Technology Ltd
Pin No.
2
4
6
8
10
12
14
16
18
20
Signal
Audio -ve
Reset -ve (Ground)
High Speed LED -ve
Keylock -ve (Ground)
Power LED -ve (Ground)
Turbo Switch -ve (Ground)
IDE LED -ve
0 Volts (Ground)
0 Volts Battery (Ground)
Keyboard Clock
01270173.doc
Page 74
Appendix C
P13: Keyboard (6 pin mini DIN)
Pin No.
1
3
5
Signal
Keyboard Data
0 Volts (Ground)
Keyboard Clock
Pin No.
2
4
6
Signal
Not Used
+5 Volts (fused)
Not Used
P14: Battery (4 way header)
Pin No.
1
2
3
4
Signal
+3.6 Volts DC
Not used (key)
0 Volts (Ground)
0 Volts (Ground)
P15: Backplane Utility Connector (10 way header)
Pin No.
1
3
5
7
9
01270173.doc
Signal
Reset +ve
High Speed LED +ve
Power LED +ve
Keylock +ve
Turbo Switch +ve
Pin No.
2
4
6
8
10
Signal
Reset -ve (Ground)
HS LED -ve (Ground)
Power LED -ve (Ground)
Keylock -ve (Ground)
Turbo Switch -ve (Ground)
Blue Chip Technology Ltd
Appendix C
Page 75
P16: AT Expansion Connector
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
Signal
-SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Blue Chip Technology Ltd
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Signal
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
+5 Volts
-Master
0 Volts (Ground)
01270173.doc
Page 76
Appendix C
P17: PC/XT Expansion Connector
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
01270173.doc
Signal
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
Signal
0 Volts (Ground)
Resetdrv
+5 Volts
IRQ9
-5 Volts
DREQ2
-12 Volts
-0WS
+12 Volts
0 Volts (Ground)
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REF
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5 Volts
OSC
0 Volts (Ground)
Blue Chip Technology Ltd
Appendix C
Page 77
ISA Bus XT Connections
A= Large gold fingers under P17 on main Component side
B= Large gold fingers under P17 on passive Component side
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
Signal
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Blue Chip Technology Ltd
Pin No.
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
Signal
0 Volts (Ground)
Resetdrv
+5 Volts
IRQ9
-5 Volts
DREQ2
-12 Volts
-0WS
+12 Volts
0 Volts (Ground)
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REF
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5 Volts
OSC
0 Volts (Ground)
01270173.doc
Page 78
Appendix C
ISA Bus AT Connections
C= Large gold fingers under P16 on main Component side
D= Large gold fingers under P16 on passive Component side
Pin No.
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
01270173.doc
Signal
-SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Pin No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Signal
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
+5 Volts
-Master
0 Volts (Ground)
Blue Chip Technology Ltd
Appendix C
Page 79
VESA Local Bus Connector
(MCA style gold edge connector)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Signal Side A
Data 00
Data 02
Data 04
Data 06
Data 08
GND
Data 10
Data 12
VCC
Data 14
Data 16
Data 18
Data 20
GND
Data 22
Data 24
Data 26
Data 28
Data 30
VCC
Address 31
GND
Address 29
Address 27
Address 25
Address 23
Address 21
Address 19
GND
Address 17
Address 15
VCC
Address 13
Address 11
Address 09
Address 07
Address 05
GND
Address 03
Blue Chip Technology Ltd
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Signal Side B
Data 01
Data 03
GND
Data 05
Data 07
Data 09
Data 11
Data 13
Data 15
GND
Data 17
VCC
Data 19
Data 21
Data 23
Data 25
GND
Data 27
Data 29
Data 31
Address 30
Address 28
Address 26
GND
Address 24
Address 22
GND
Address 20
Address 18
Address 16
Address 14
Address 12
Address 10
Address 08
GND
Address 06
Address 04
WBACK#
BE0#
01270173.doc
Page 80
Appendix C
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
01270173.doc
Address 02
No connection
RESET#
D/C#
M/IO#
W/R#
RDYRTN#
GND
IRQ9
BRDY#
BLAST#
ID0
ID1
GND
LCLK
VCC
LBS16#
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VCC
BE1#
BE2#
GND
BE3#
ADS#
LRDY#
LDEV#
LREQ#
GND
LGNT#
VCC
ID2
ID3
ID4
LKEN#
LEADS#
Blue Chip Technology Ltd
Appendix D
Page 81
APPENDIX D
CMOS RAM Map
A map of CMOS RAM as configured by the AMIBIOS for the Blue Chip
Technology DX1 SBC is shown in the following table.
Description
00h - 0Fh
10h
Standard IBM AT compatible RTC and Status Register data definitions.
Floppy Drive Type
Bits 7-4 Drive A: Type
0
No Drive
1
360 KB Drive
2
1.2 MB Drive
3
720 KB Drive
4
1.44 MB Drive
5
2.88 MB Drive
Bits 3-0 Drive B: Type (bit settings same as A)
11h
12h
Bit 7
Mouse Support Option
(1 = Enabled)
Bit 6
Above 1 MB Memory Test
(1 = Enabled)
Bit 5
Memory Test Tick Sound
(1 = Enabled)
Bit 4
Memory Parity Error Check (1 = Enabled)
Bit 3
Hit <DEL> Message Display (1 = Enabled)
Bit 2
Hard Disk Type 47 RAM Area
Bit 1
Wait for <F1> if Any Error
Bit 0
System Boot Up Num Lock (1 = Enabled)
(1 = 0:300h)
(1 = Enabled)
Hard Disk Data
Bits 7-4 Hard Disk Drive C: Type
0
No drive
1-14
Hard drive Type 1-14
16
Hard Disk Type 16-255 (actual Hard Drive Type is in CMOS RAM 1Ah)
Bits 3-0 Hard Disk Drive D: Type (Same as C:)
Blue Chip Technology Ltd
01270173.doc
Page 82
13h
Appendix D
Bit 7
Typematic Rate Programming(1 = Enabled)
Bits 6-5 Typematic Rate Delay (in milliseconds)
00
250 ms
01
500 ms
10
750 ms
11
100 ms
Bits 4-2 Typematic Rate (in characters per second)
14h
000
6 cps
001
8 cps
010
10 cps
011
12 cps
100
15 cps
101
20 cps
110
24 cps
111
30 cps
Equipment Byte
Bits 7-6 Number of Floppy Drives
00b
1 Drive
01b
2 Drives
10b-11b
Reserved
Bits 5-4 Monitor Type
00b
Not CGA or MDA
01b
40x25 CGA
10b
80x25 CGA
11b
MDA (Monochrome)
Bit 3
Display Enabled
Bit 2
Keyboard Enabled
(1 = Enabled)
Bit 1
Math coprocessor Installed
(1 = Enabled)
Bit 0
Floppy Drive Installed
(0 = On)
(1 = Enabled)
15h
Base Memory (in 1 KB increments), Low Byte
16h
Base Memory (in 1 KB increments), High Byte
17h
Extended Memory (in 1 KB increments), Low Byte
18h
Extended Memory (in 1 KB increments), High Byte (Max 15 MB)
19h
Hard Disk C: Drive Type
0-15
Reserved
16-255
Hard Drive Type 16-255
1Ah
Hard Disk D: Drive Type (Same as Drive C: above)
1Bh
User-Defined Drive C: - # of Cylinders, Low Byte
1Ch
User-Defined Drive C: - # of Cylinders, High Byte
1Dh
User-Defined Drive C: - Number of Heads
1Eh
User-Defined Drive C: - Write Precompensation Cylinder, Low Byte
1Fh
User-Defined Drive C: - Write Precompensation Cylinder, High Byte
20h
User-Defined Drive C: - Control Byte (80h if # of heads is equal or greater than 8)
21h
User-Defined Drive C: - Landing Zone, Low Byte
22h
User-Defined Drive C: - Landing Zone, High Byte
01270173.doc
Blue Chip Technology Ltd
Appendix D
Page 83
23h
User-Defined Drive C: - # of Sectors
24h
User-Defined Drive D: - # of Cylinders, Low Byte
25h
User-Defined Drive D: - # of Cylinders, High Byte
26h
User-Defined Drive D: - Number of Heads
27h
User-Defined Drive D: - Write Precompensation Cylinder, Low Byte
28h
User-Defined Drive D: - Write Precompensation Cylinder, High Byte
29h
User-Defined Drive D: - Control Byte (80h if # of heads is equal or greater than 8)
2Ah
User-Defined Drive D: - Landing Zone, Low Byte
2Bh
User-Defined Drive D: - Landing Zone, High Byte
2Ch
User-Defined Drive D: - # of Sectors
2Dh
Configuration Options
Bit 7
Weitek Processor
(1 = Present)
Bit 6
Floppy Drive Seek At Boot
(1 = Enabled)
Bit 5
System Boot Up Sequence
(1 = A:, C:)
Bit 4
System Boot Up CPU Speed (1 = High)
Bit 3
External Cache Memory
(1 = Enabled)
Bit 2
Internal Cache Memory
(1 = Enabled)
Bit 1
Fast Gate A20 Option
(1 = Enabled)
Bit 0
Turbo Switch Function
(1 = Enabled)
2Eh
Standard CMOS Checksum, High Byte
2Fh
Standard CMOS Checksum, Low Byte
30h
Extended Memory, Low Byte
31h
Extended Memory, High Byte (Maximum 15 MB)
32h
Century Byte (BCD value for the century)
33h
Information Flag
Bit 7
BIOS Size
(1 = 128 KB)
Bits 6-0 Reserved
34h
Bit 7
Boot Sector Virus Protection (1 = Enabled)
Bit 6
Password:
0
Always
1
Setup
Bit 5
Adaptor ROM Shadow C800,16K
(1 = Enabled)
Bit 4
Adaptor ROM Shadow CC00,16K
(1 = Enabled)
Bit 3
Adaptor ROM Shadow D000,16K
(1 = Enabled)
Bit 2
Adaptor ROM Shadow D400,16K
(1 = Enabled)
Bit 1
Adaptor ROM Shadow D800,16K
(1 = Enabled)
Bit 0
Adaptor ROM Shadow DC00,16K
(1 = Enabled)
Blue Chip Technology Ltd
01270173.doc
Page 84
35h
36h
Appendix D
Bit 7
Adaptor ROM Shadow E000,16K
(1 = Enabled)
Bit 6
Adaptor ROM Shadow E400,16K
(1 = Enabled)
Bit 5
Adaptor ROM Shadow E800,16K
(1 = Enabled)
Bit 4
Adaptor ROM Shadow EC00,16K
(1 = Enabled)
Bit 3
System BIOS Shadow F000,64K
(1 = Enabled)
Bit 2
Video ROM Shadow C000, 16K
(1 = Enabled)
Bit 1
Video ROM Shadow C400,16K
(1 = Enabled)
Bit 0
Numeric Processor Test
(1 = Enabled)
Bit 7
IDE Block Mode Transfer
0
Disabled
1
Enabled
Bits 6-5 CPU Internal Clock Mode
00
Bit 4
2X
01
1X
IDE Standby Mode
0
Disabled
1
Enabled
Bits 3-0 Auto KeyLock Timeout
37h
38h - 3Dh
0000
Disabled
0001
1 Min.
0010
2 Min.
0011
3 Min.
0100
4 Min.
0101
5 Min.
0110
6 Min.
0111
7 Min.
1000
8 Min.
1001
9 Min.
1010
10 Min.
1011
11 Min.
1100
12 Min.
1101
13 Min
1110
14 Min.
1111
15 Min.
Reserved
Encrypted Password
3Eh
Extended CMOS Checksum, High Byte (includes 34h - 3Dh)
3Fh
Extended CMOS Checksum, Low Byte (includes 34h - 3Dh)
40h
Reserved
01270173.doc
Blue Chip Technology Ltd
Appendix D
41h
Bit 7-6
Page 85
Cache Read Option
01
3-2-2-2
11
2-1-1-1
10
3-1-1-1
10
1 W.S.
10
1 W.S
Bits 5-4 Cache Write Option
Bit 3
Bit 2
01
2 W.S.
11
0 W.S.
Refresh Cycle
0
Slow
1
Fast
DRAM Type
0
PageMode
1
FastPage
Bits 1-0 DRAM Wait State(s)
42h
Bit 7
Bit 6
43h
Bit 6
Bit 5
01
2 W.S
11
0 W.S.
Non-Cacheable Block-2 Enable
0
Disabled
1
Enabled
Non-Cacheable Block-1 Enable
0
Disabled
1
Enabled
CoProcessor Ready
0
Delay 1T
1
No Delay
Check ELBA# Signal
0
in T1
1
in T2
44h
Bits 3-0 Non-Cacheable Block-1 Base
45h
Reserved
46h
Bits 7-0 Non-Cacheable Block-1 Size
47h
Reserved
48h
Bits 5-4 Non-Cacheable Block-2 Base
49h
Reserved
4Ah
Bits 7-0 Non-Cacheable Block-2 Size
4Bh
Bit 7
Memory Remapping
Blue Chip Technology Ltd
0
Disabled
1
Enabled
01270173.doc
Page 86
4Ch
Appendix D
Bits 7-6 F Segment Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 E Segment Shadow RAM
4Dh
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 7-6 C000-C3FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 C400-C7FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 3-2 C800-CBFF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 1-0 CC00-CFFF Shadow RAM
4Eh
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 7-6 D000-D3FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 D400-D7FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 3-2 D800-DBFF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 1-0 DC00-DFFF Shadow RAM
4Fh
Reserved
50h
Bit 6
00
Disabled
01
Enabled
10
Cached
11
Into-486
Hold PD Bus
0
1~2 T
1
2~3 T
Bits 5-0 Refresh Divider
01270173.doc
000000
64
000001
1
000010
2
000011
4
000100
8
000101
16
000110
32
Blue Chip Technology Ltd
Appendix D
51h
Page 87
Bits 5-3 Keyboard Clock Select
000
CPUCLK/6
001
CPUCLK/5
010
CPUCLK/4
011
CPUCLK/3
100
CPUCLK/2
110
9.5 MHz
111
7.2 MHz
Bits 2-0 AT Clock Select
52h
Bit 7
000
CPUCLK/6
001
CPUCLK/5
010
CPUCLK/4
011
CPUCLK/3
100
CPUCLK/2
110
7.2 MHz
111
CPUCLK/8
Data Location of Local Bus
0
ISA Bus
1
PD Bus
Bits 6-5 LOWA20#, RC Emulation
Bit 4
00
None
10
Both
01
GA20
Stretch 0WS# Signal Option
0
Do Not
1
½ ATCLK
Bits 3-0 IO Recovery Time of ISA/PCB
53h
Reserved
54h
Bit 6
Bit 5
55h - 5Fh
0000
0/0 BCLK
0001
1/1 BCLK
0010
2/2 BCLK
0011
3/3 BCLK
0100
5/3 BCLK
0101
7/3 BCLK
0110
9/3 BCLK
0111
12/3 BCLK
1100
5/5 BCLK
1101
7/7 BCLK
1110
9/9 BCLK
1111
12/12BCLK
AUTO Config Function
0
Disabled
1
Enabled
Hardware Parity Check
0
Disabled
1
Enabled
Reserved
60h
Bits 7-0 Device-1 Timeout
61h
Bits 7-0 Device-2 Timeout
62h
Bits 7-0 Device-3 Timeout
63h
Bits 7-0 Device-4 Timeout
64h
Bits 7-0 Device-5 Timeout
Blue Chip Technology Ltd
01270173.doc
Page 88
65h -7Fh
01270173.doc
Appendix D
Reserved
Blue Chip Technology Ltd
Appendix E
Page 89
APPENDIX E
Chipset Registers
The AMIBIOS for the Blue Chp Technology DX1 SBC sets the following values
in the chipset registers.
Offset
54h
Description
Bit 6
Bit 5
C1h
Bit 7-6
AUTO Config Function
0
Disabled
1
Enabled
Hardware Parity Check
0
Disabled
1
Enabled
Cache Read Option
01
3-2-2-2
11
2-1-1-1
10
3-1-1-1
10
1 W.S.
10
1 W.S
Bits 5-4 Cache Write Option
Bit 3
Bit 2
01
2 W.S.
11
0 W.S.
Refresh Cycle
0
Slow
1
Fast
DRAM Type
0
PageMode
1
FastPage
Bits 1-0 DRAM Wait State(s)
C2h
Bit 7
Bit 6
01
2 W.S
11
0 W.S.
Non-Cacheable Block-2 Enable
0
Disabled
1
Enabled
Non-Cacheable Block-1 Enable
Blue Chip Technology Ltd
0
Disabled
1
Enabled
01270173.doc
Page 90
Appendix E
C3h
Bit 6
Bit 5
CoProcessor Ready
0
Delay 1T
1
No Delay
Check ELBA# Signal
0
in T1
1
in T2
C4h
Bits 3-0 Non-Cacheable Block-1 Base
C5h
Reserved
C6h
Bits 7-0 Non-Cacheable Block-1 Size
C7h
Reserved
C8h
Bits 5-4 Non-Cacheable Block-2 Base
C9h
Reserved
CAh
Bits 7-0 Non-Cacheable Block-2 Size
CBh
Bit 7
CCh
Memory Remapping
0
Disabled
1
Enabled
Bits 7-6 F Segment Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 E Segment Shadow RAM
CDh
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 7-6 C000-C3FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 C400-C7FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 3-2 C800-CBFF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 1-0 CC00-CFFF Shadow RAM
01270173.doc
00
Disabled
01
Enabled
10
Cached
11
Into-486
Blue Chip Technology Ltd
Appendix E
CEh
Page 91
Bits 7-6 D000-D3FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 5-4 D400-D7FF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 3-2 D800-DBFF Shadow RAM
00
Disabled
01
Enabled
10
Cached
11
Into-486
Bits 1-0 DC00-DFFF Shadow RAM
CFh
Reserved
D0h
Bit 6
00
Disabled
01
Enabled
10
Cached
11
Into-486
Hold PD Bus
0
1~2 T
1
2~3 T
Bits 5-0 Refresh Divider
D1h
000000
64
000001
1
000010
2
000011
4
000100
8
000101
16
000110
32
Bits 5-3 Keyboard Clock Select
000
CPUCLK/6
001
CPUCLK/5
010
CPUCLK/4
011
CPUCLK/3
100
CPUCLK/2
110
9.5 MHz
111
7.2 MHz
Bits 2-0 AT Clock Select
Blue Chip Technology Ltd
000
CPUCLK/6
001
CPUCLK/5
010
CPUCLK/4
011
CPUCLK/3
100
CPUCLK/2
110
7.2 MHz
111
CPUCLK/8
01270173.doc
Page 92
Appendix E
D2h
Bit 7
Data Location of Local Bus
0
ISA Bus
1
PD Bus
Bits 6-5 LOWA20#, RC Emulation
Bit 4
00
None
10
Both
01
GA20
Stretch 0WS# Signal Option
0
Do Not
1
½ ATCLK
Bits 3-0 IO Recovery Time of ISA/PCB
0000
0/0 BCLK
0001
1/1 BCLK
0010
2/2 BCLK
0011
3/3 BCLK
0100
5/3 BCLK
0101
7/3 BCLK
0110
9/3 BCLK
0111
12/3 BCLK
1100
5/5 BCLK
1101
7/7 BCLK
1110
9/9 BCLK
1111
12/12BCLK
D3h
Reserved
E0h
Bits 7-0 Device-1 Timeout
E1h
Bits 7-0 Device-2 Timeout
E2h
Bits 7-0 Device-3 Timeout
E3h
Bits 7-0 Device-4 Timeout
E4h
Bits 7-0 Device-5 Timeout
01270173.doc
Blue Chip Technology Ltd
Appendix F
Page 93
APPENDIX F
Solid State Disk Operation (SSD)
Quick Disk SSD
The BCT DX-1 provides two byte wide sockets that allow one Flash and one
SRAM devices to be fitted on the main PCB. These Solid State Disks can be
used in a virtually identical manner as normal floppy disk drives. The advantages
of the SSD are that their environmental specifications are much superior to
mechanical drives, they occupy no extra space and they are much faster.
The two byte wide sockets are located at IC20 (Flash) and IC27 (SRAM). The
Flash device can selected between a 128KB, 256KB, 512KB, 1MB or 2MB 32
pin DIL component. The SRAM device can be either 128KB or 512KB in size,
again with a 32 pin DIL profile. Please see the preferred parts at the end of this
Appendix for further details.
To enable either the Flash and/or SRAM devices:
1.
2.
3.
4.
5.
6.
7.
8.
From a Power-up, Reset or <CTRL><ALT><DEL> enter the BIOS Set-up
by pressing <DEL> when the ‘Press DEL to enter Setup’ message is
displayed.
Enter the Standard CMOS Set-Up and configure the floppy and hard drives
as required. For simplicity let us assume that all drives are Disabled.
Escape back to the main menu and enter the DX-1 Peripheral Management
Set-up.
Set the Quik Disk Boot ROM option to Enabled.
Ensure that the SSD Boot ROM option is Disabled.
Ensure that the CardTrick Boot ROM option is disabled.
Set the BIOS Extensions to Enabled.
Escape back to the main menu and press <F10> to save and Exit.
Programming the Flash.
1.
Create a bootable floppy disk containing the image that is to be programmed
into the flash disk.
2.
Boot the system and ensure that the Quik Disk Boot ROM is enabled and
that one of floppy disk drives is enabled as a 1.44MB drive.
Blue Chip Technology Ltd
01270173.doc
Page 94
3.
Appendix F
Boot the system to DOS and at the DOS prompt run the PROGFLAS.EXE
utility provided on the DX-1 Flash Software diskette. The syntax for
running PROGFLAS is:
PROGFLAS <DRIVE>
Where <DRIVE> specifies the floppy disk drive that contains the disk image
i.e. A: or B:
4.
As PROGFLAS executes it will display the message ‘Formatting flash
disk...’ and then ‘Programming sector n of x. Where n is the current sector
and x is the total number of sectors to be programmed.
5. When programming is complete the floppy disk drive can be removed and
when the system is rebooted it will boot off the flash disk.
Programming the SRAM
The SRAM can be formatted using the MS-DOS format utility and can then be
accessed as a normal floppy disk drive using the standard DOS file handiling
functions, COPY, DEL, etc.
01270173.doc
Blue Chip Technology Ltd
Appendix F
Page 95
Daughter Board SSD
The BCT DX-1 provides the facility for a Daughter Board SSD to be fitted to
connectors P11 and P13. This Solid State Disk can be used in a virtually identical
manner as normal floppy disk drives. The advantages of the SSD are that their
environmental specifications are much superior to mechanical drives, they
occupy no extra space and they are much faster.
The Daughter Board SSD allows up to 4MBytes of Flash and 512KBytes of
SRAM to be fitted. Various configurations of the card are available, please
contact BCT for further details.
1.
2.
3.
4.
5.
6.
7.
From a Power-up, Reset or <CTRL><ALT><DEL> enter the BIOS Set-UP
(see page 14 for information on how to enter the BIOS Set-Up).
Enter the Standard CMOS Set-Up and configure the floppy and hard drives
as required. For simplicity let us assume that all drives are Disabled.
Escape back to the main menu and enter the DX-1 Extended Set-Up.
Set the Daughter Board Disk option to Enabled.
Ensure that the Quick Disk Silicon Disk option is Disabled.
Set the C800 - CBFF Internal ROM (SSD expansion BIOS) to Enabled.
Escape back to the main menu and press <F10> to save and Exit.
Blue Chip Technology Ltd
01270173.doc
Page 96
Appendix G
APPENDIX G
Connector and Jumper Link PCB Positions
A diagram showing the positions of the various connectors and links, follows:
01270173.doc
Blue Chip Technology Ltd
Appendix G
P7
Page 97
P11
P9
P13
F3
F1
P5
P6
RS4
P17
J12
P4
J11
J5 J6
RS3
P10
P3
RS2
J4
J3
J10
J9
RS1
P16
P2
BIOS FLASH
EPROM Socket
SRAM
Socket
P8
J8
J13
J7
CPU
P1
g
e
c
a
Reg1
h J2
f
d
b J1
J16
J15
F2
Mod
P12 P15
Build
1
2
3
4
Battery
J14
Serial
No.
P14
LS1
Blue Chip Technology Ltd
01270173.doc
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