User manual | Freescale Motor Control Software Library

July 19, 2013

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Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,

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1. Select Target Motor

PMSM, IM, BLDC, SRM, DC…………….

2. Select Control Algorithm and Target Performance

Sensorless, Sensored

, Target Control Response…….

3. Select Target MCU

Core, Core Speed, ADC performance, Vcc

Level….

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0. Read & Understand Datasheet, Reference Manual and Errata

1. Peripheral Setting :

ADC, PWM, Timer……

2. Implementation Motor Control Algorithm :

Vector Control, Encoder

Interface…..

3. Tuning Motor performance :

PI Gain Tuning..

4. Application Implementation :

Washing Machine, Robot….

5. Application Tuning

6. TEST and Debugging

7. TEST and Debugging

8. TEST and Debugging

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1. Peripheral Setting : ADC, PWM, Timer……

ProcessorExpert, Quick Start(GCT)

2. Implementation Motor Control Algorithm :

Vector Control, Encoder Interface…..

FSL Library, ProcessorExpert

3. Tuning Motor performance :

PI Gain Tuning.. freemaster

4. Application Implementation :

Washing Machine, Robot….

FSL Library, ProcessorExpert

5. Application Tuning freemaster

Implementation & Setting

Monitoring

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• GUI

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Memory Manager

• Dynamic allocation

Feature Phone Library

• CallerID type 1&2,

CallerID Parser,

Generic Echo Cancellor

DSP Library

• FIR, IIR, FFT, Auto

Correlation, Bit

Reversal

Telephony Libraries

• AEC, AGC, Caller ID,

• CAS, CPT, CTG, DTMF

• G165, G168, G711

• G723, G726, G729

Modem Libraries

• V.8bis, V.21, V.22bis,

V.42bis

Security Libraries

• RSA, DES, 3DES,

Motor Control

• BLDC, ACIM, SR motor specific algorithms

• General purpose algorithms

Math Libraries

• Matrix, Fractional, Vector

• Trigonometric

Tools Library

• Cycle Count, FIFO,

FileIO, Test

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• Can change Bean name

• Select a pin

• Configure pin properties:

− Enable/disable pullup

− Open drain/pushpull

Must configure the

Init. Direction to

Output

and

Select a value at initialization

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• What is QuickStart?

• QuickStart Low-level Drivers

•

Project Stationary

•

Graphical Configuration Too

• QuickStart Highlights

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•

Quick Start = Easy-to-use SW Development Environment

Set of

Low-level Drivers

for

all Peripheral

Modules

C-language structures of peripheral memory space

Unified way of accessing peripheral registers

Highly optimized to achieve an

optimal assembly

generated

Ready-touse Project Templates (“Project Stationery”)

Compiler configurations (RAM-debug, Flash-standalone targets)

Processor start-up code

Interrupt tables or Interrupt Dispatcher

Debugger initialization files

Graphical

Configuration Tool

User-friendly insight to processor configuration (cont.)

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•

Graphical Configuration Tool

Edits post-reset processor configuration graphically

Configuration saved/read from a single ANSI C header file

GUI to configuration bits of all peripheral module registers

•

Possible conflict warnings

Pin-out view of processor I/O pins

•

Sample Applications

Demonstrating usage of GCT, processor peripheral modules and low-level drivers

•

User Manual

Low-level drivers & tools guide

Latest device User Manual

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•

CodeWarrior Integration

Quick Start project stationery is installed directly into the CW

Support for CW debugger and Flash Programmer

GCT invoked from CW IDE

•

Other Tools

MPC500/MPC5500 supports makefile-based tools

(Diab, Green Hills)

Lauterbach Debugger

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• ArchIO

– global symbol

−

Provides a C interface (structure type) to all peripheral and core registers mapped in data memory

−

All registers are accessed via this structure - no need to know and specify the concrete addresses of the registers to write or read

−

ArchIO - declared in the arch.h file

−

ArchIO structure definition

 ArchIO defined as the extern variable

 Its address defined by a directive in linker command file

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typedef volatile struct

{

arch_sTimer TimerA;

arch_sTimer TimerB_unused;

arch_sADC

arch_sPWM

Adc;

Pwm;

arch_sIntc Intc;

arch_sSIM Sim;

arch_sCOP Cop;

arch_sPLL Pll;

arch_sLVI Lvi;

/* TMRA_BASE 0xF000 */

/* ADC_BASE 0xF080 */

/* PWM_BASE 0xF0C0 */

/* INTC_BASE 0xF0E0 */

/* SIM_BASE 0xF100 */

/* COP_BASE 0xF120 */

/* PLL_BASE 0xF130 */

/* LVI_BASE 0xF140 */

UWord16 reserved4[0xFF0600];

arch_sEOnCE EOnCE; /* EOnCE_BASE 0xFFFF00 */

} arch_sIO;

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• COP structure

– defined in arch.h file

typedef volatile struct

{

ARCH_REG2(UWord16, copctl, ControlReg);

ARCH_REG2(UWord16, copto, TimeoutReg);

ARCH_REG2(UWord16, copctr, ServiceReg);

ARCH_REG1(UWord16, reserved[13]);

} arch_sCOP;

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• arch.h file

– extern declaration of ArchIO variable

/* The location of the following structure is defined in linker.cmd */ extern arch_sIO ArchIO;

•

Linker command file

– address assignment to the structure

FArchIO = ADDR(.x_onchip_peripherals);

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•

• Example of read/write operation using ArchIO structure

UWord16 RegValue; // variable definition

RegValue = ArchIO.TimerA.Channel0.HoldReg; // read register

ArchIO.TimerA.Channel0.CompareReg1 = 0x8000; // write number to reg

Example of the same operation as previous case using

periphMemRead and periphMemRead macros

UWord16 RegValue; // variable definition

RegValue = periphMemRead(&ArchIO.TimerA.Channel0.HoldReg); periphMemWrite(0x8000 , &ArchIO.TimerA.Channel0.CompareReg1);

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• What is QuickStart?

• QuickStart Low-level Drivers

•

Project Stationary

•

Graphical Configuration Too

• QuickStart Highlights

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

Quick Start Low-level Drivers

− Full control over and full access to all processor resources

− Unifies access to peripheral memory space (

ioctl call)

− Registers are not accessed directly, although this is still possible

−

ioctl calls are optimally compiled macros or functions

ioctl(SCI_0, SCI_SET_BAUDRATE, SCI_BAUD_9600)

Module identifier

Command to perform

Command

Parameter

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•

• ioctl

– Input Output Control ioctl

– general syntax

•

ioctl(

module_ID , cmd_name , cmd_spec_param

);

module_ID

– module identifier

 Predefined symbolic constant corresponding to names of peripheral modules

 Example: GPIO_A, GPIO_B, ADC, ADC_A, ADC_B, PWM, PWM_A,

PWM_B, COP, etc.



The base address of the peripheral module

List of module identifiers

– “*.h” corresponding to managed peripheral

 Example: gpio.h, adc.h, pwm.h, sci.h, spi.h, qtimer.h, etc.

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•



cmd_name

– specifies action performed on a peripheral module



Command is depended to performed operation

List of commands

– “*.h” corresponding to managed peripheral

 Example: gpio.h, adc.h, pwm.h, sci.h, spi.h, qtimer.h, etc.

Set of commands for each peripheral

•

Example for pwm.h:

PWM_SET_PRESCALER

•

PWM_SET_RELOAD_FREQUENCY

PWM_FAULT_INT_ENABLE

Etc.



Self-explaining name of commands

 No need to dive into deep documentation studying

INIT command

– essential command for each peripheral

Example: COP_INIT, ADC_INIT, PWM_INIT, GPIO_INIT, etc.

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•

cmd_spec_param

– command specific parameter

 Specifies other data required to execute the command

 In general, it can be

 Pointer to the structure

 NULL value



 Variable-value in dependency with the specific command

List of recommended parameters

– “*.h” corresponding to managed peripheral

 Example: gpio.h, adc.h, pwm.h, sci.h, spi.h, qtimer.h, etc.

 Example for pwm.h:

• #define PWM_PRESCALER_DIV_1 0

•

#define PWM_PRESCALER_DIV_2 1

#define PWM_PRESCALER_DIV_4 2

#define PWM_PRESCALER_DIV_8 3

Etc.

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• ioctl command - macro

•

#define ioctl(

, cmd , prm ) ioctl## cmd ((

),( prm ))

Macro definition

– periph.h

• fd



Peripheral module base address

 Address assigned from ArchIO structure

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•

Example for GPIO

– general command

 gpio.h



#define GPIO_A (&ArchIO.PortA

) // GPIO_A base address

 User source code - *.c



ioctl( GPIO_A , GPIO_SET_PIN , BIT_0 );

 periph.h



#define periphBitSet(mask, addr) (*(addr) |= (mask))

 gpio.h



#define ioctl GPIO_SET_PIN (pGpioBase, param ) periphBitSet ( param , &(( pGpioBase )->dr))

 Compiler result

– assembly code

ioctl( GPIO_A , GPIO_SET_PIN , BIT_0 );

P:0000414A: 8254F1510001 bfset # 1 ,X:0x00f151

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• Example for GPIO

– INIT command

 gpio.h



#define GPIO_A (&ArchIO.PortA

) // GPIO_A base address

 User source code - *.c



ioctl( GPIO_A , GPIO_INIT , NULL );

 gpio.h



void gpioInit(arch_sPort *pGpioBase); // declaration



#define ioctl GPIO_INIT ( pGpioBase , param) gpioInit ( pGpioBase )

 gpioInit() function execution

 Function definition - gpio.c

 Usually executed just ones during chip initialization

 Performs setting stored in appconfig.h file

 appconfig.h file modified by GCT (Graphical Configuration Tool)

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•

Why not to use direct access to peripheral registers?

− Most of

ioctl calls are “macroized” to direct register access anyway (either read/write or bit-set/bit-clear instructions used)

− Some registers do need special attention,

ioctl usage brings kind-of

abstraction and transparency to an application code while still being optimally compiled

Exercise

Suppose you want to clear DIRQ bit only, while not modifying the rest of the register. Also you must not clear the HIRQ and XIRQ bits.

What C or assembly statement will you use on 56F800E? solution on the next slide...

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#define DECCR_DIRQ 0x0010

/* DIRQ bit constant */

ArchIO.Decoder0.deccr

/* register in the peripheral structure */

C-language:

ArchIO.Decoder0.deccr = DECCR_DIRQ;

56F800E Assembler: asm ( move.w #>16,X:0x00f180 );

• DIRQ gets cleared ... OK

• XIRQ and HIRQ remain unchanged ... OK

• All other bits get reset! ... Wrong

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#define DECCR_DIRQ 0x0010

/* DIRQ bit constant */

ArchIO.Decoder0.deccr

/* register in the peripheral structure */

C-language:

ArchIO.Decoder0.deccr |= DECCR_DIRQ;

56F800E Assembler:

asm ( bfset #0x10,X:0x00f180 );

• DIRQ gets cleared ... OK

• Other register bits unchanged ... OK

• XIRQ or HIRQ gets reset if they read as “1”

(i.e. when interrupt request is pending!)

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#define DECCR_DIRQ 0x0010

/* DIRQ bit constant */

#define DECCR_HIRQ 0x8000

/* HIRQ bit constant */

#define DECCR_XIRQ 0x0100

/* XIRQ bit constant */

ArchIO.Decoder0.deccr

/* register in the peripheral structure */

C-language:

ArchIO.Decoder0.deccr &= ~(~(DECCR_DIRQ) &

(DECCR_HIRQ | DECCR_XIRQ));

Better work with QuickStart and use the

56F800E Assembler: asm ( bfclr #0x8100,X:0x00f180 ); ioctl(DEC_0, DEC_INT_REQUEST_CLEAR, DEC_DECCR_DIRQ);

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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• Full control over all processor resources

•

Real-world application development know-how inside

− transparent solution to tricky register access

− higher abstraction and code readability without loosing performance

•

Delivered as source code

• Fully tested and documented

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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• What is QuickStart?

• QuickStart Low-level Drivers

•

Project Stationary

•

Graphical Configuration Too

• QuickStart Highlights

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

CodeWarrior concept of creating a new project

−

CodeWarrior “clones” the project template and creates a ready-touse skeleton of a new application

− In Quick Start, a dedicated project stationery exists for each processor and evaluation board (EVB)

 Processors differ in memory layout, peripheral modules etc.

 For a given processor, more than one EVB may exist, differing in how the processor is connected with external components

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

Multiple Compiler configurations per project

−

RAM-based debugging targets

−

Standalone Flash-based (release) targets

− CPU Simulator target

Start-up code, Board Initialization, Interrupt tables

Linker Command Files

− provide the linker with information about how to arrange a

C-code in memory

Debugger Configuration Files

− Making the EVB ready for RAM-based debugging

− Making the EVB ready for Flash Programmer

− Memory description files

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and

• What is QuickStart?

• QuickStart Low-level Drivers

•

Project Stationary

•

Graphical Configuration Tool

• QuickStart Highlights

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

A desktop application for MS Windows

−

Used to edit the ANSI C-compatible application configuration header file (typically appconfig.h for QuickStart applications)

Pre-defined keystroke makes GCT open up the appconfig.h of the current project

Metrowerks CodeWarrior IDE

#include “appconfig.h”

#defines used to initialize peripherals

TM appconfig.h file

Graphical Configuration Tool

Read & Write access to appconfig.h

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and

•

A single macro constant per peripheral register

Configuration summary comments

Read / Write in GCT

− Enables manual editing of the

appconfig.h file

− Copy & paste migrating to other CPUs

− GCT supports importing of module configuration within a single project or between projects

•

Private section in appconfig.h file

− Users put other global symbols & definitions here

− The file can be a real application configuration file

(not only the processor configuration)

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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• Different Control Page for each Peripheral Module

Module Configuration Page

Clocks Summary

Registers Summary

Warnings Summary

Peripheral Modules Tree

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

Direct Register Value View

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Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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•

Conflict Warnings

Warning detail

GPIO A6 mode bad

More detailed warning description

Timer Pin #0 is not set to Timer mode in GPIO_A6

More detailed warning description

Module QT_A0 is configured for use but its peripheral clock is disabled

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and

• What is QuickStart?

• QuickStart Low-level Drivers

•

Project Stationary

•

Graphical Configuration Tool

• QuickStart Highlights

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC,

Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and

•

Highlights

•

− QuickStart helps users to get familiar with the processor quickly



GCT helps to understand individual bits of peripheral registers

Sample applications demonstrate how to access the peripheral modules

− QuickStart helps users to jump in the SW development quickly



A ready-to-use project stationery to start a new project

GCT immediately available

− No performance penalty when using QuickStart



 Optimal code, each instruction matters

Suitable for hard real-time applications (motor control)

Source files available, everything under control, no hidden code

Quality

−

Developed under CMM-Level 3 certified process