Bussystems Chapter 2

Bussystems Chapter 2

The I

2

C Bus

Introduction

The I

2

C-bus is a de facto world standard that is now implemented in over 1000 different

ICs manufactured by more than 50 companies. Additionally, the versatile I

2

C-bus is used in a variety of control architectures such as System Management Bus (SMBus), Power

Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), and

Advanced Telecom Computing Architecture (ATCA).

I

2

C-bus features

In consumer electronics, telecommunications and industrial electronics, there are often many similarities between seemingly unrelated designs. For example, nearly every system includes:

• Some intelligent control, usually a single-chip microcontroller

• General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM,

EEPROM, real-time clocks or A/D and D/A converters

• Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, temperature sensors, and smart cards

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To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips

Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter IC or I

2

C-bus. All I

2

C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I

2

C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits.

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Here are some of the features of the I

2

C-bus:

• Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).

• Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as mastertransmitters or as master-receivers.

• It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.

• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode

Plus, or up to 3.4 Mbit/s in the High-speed mode.

• On-chip filtering rejects spikes on the bus data line to preserve data integrity.

• The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance may be allowed under some conditions.

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Definition of I

2

C-bus terminology

Transmitter the device which sends data to the bus

Receiver the device which receives data from the bus

Master the device which initiates a transfer, generates clock signals and terminates a transfer

Slave the device addressed by a master

Multi-master more than one master can attempt to control the bus at the same time without corrupting the message

Arbitration procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is y device addressed is considered a slave.

Synchronization procedure to synchronize the clock signals of two or more devices

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The I

2

C-bus protocol

Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. An LCD driver may be only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed

Is considered a slave.

The I

2

C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers, let’s consider the case of a data transfer between two microcontrollers connected to the

I

2

C-bus.

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SDA and SCL logic levels

Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I

2

C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V

DD

. Input reference levels are set as 30 % and 70 % of

V

DD

; V

IL is 0.3V

DD and V

IH is 0.7V

DD

.

Some legacy device input levels were fixed at V

IL require this 30 %/70 % specification.

= 1.5 V and V

IH

= 3.0 V, but all new devices

Data validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or

LOW state of the data line can only change when the clock signal on the SCL line is LOW.

One clock pulse is generated for each data bit transferred.

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START and STOP conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to

LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to

HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical.

For the remainder of this document, therefore, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is articularly relevant.

Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition.

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Byte format

Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

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Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses including the acknowledge 9th clock pulse are generated by the master.

The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse (see Figure 4). Set-up and hold times (specified in Section 6) must also be taken into account.

When SDA remains HIGH during this 9th clock pulse, this is defined as the Not

Acknowledge signal. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. There are five conditions that lead to the generation of a NACK:

1. No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge.

2. The receiver is unable to receive or transmit because it’s performing some real-time function and is not ready to start communication with the master.

3. During the transfer the receiver gets data or commands that it does not understand.

4. During the transfer, the receiver cannot receive any more data bytes.

5. A master-receiver needs to signal the end of the transfer to the slave transmitter.

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The slave address and R/W bit

Data transfers follow the format shown in the left figure. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W)—a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ) (refer to the right figure). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.

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START byte

Microcontrollers can be connected to the I

2

C-bus in two ways. A microcontroller with an on-chip hardware I

2

C-bus interface can be programmed to be only interrupted by requests from the bus. When the device does not have such an interface, it must constantly monitor the bus via software. Obviously, the more times the microcontroller monitors, or polls the bus, the less time it can spend carrying out its intended function.

There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling.

In this case, data transfer can be preceded by a start procedure which is much longer than normal. The start procedure consists of:

• A START condition (S)

• A START byte (0000 0001)

• An acknowledge clock pulse (ACK)

• A repeated START condition (Sr).

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After the START condition S has been transmitted by a master which requires bus access, the START byte (0000 0001) is transmitted. Another microcontroller can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the START byte is detected. After detection of this LOW level on the SDA line, the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization.

A hardware receiver will reset on receipt of the repeated START condition Sr and will therefore ignore the START byte.

An acknowledge-related clock pulse is generated after the START byte. This is present only to conform with the byte handling format used on the bus. No device is allowed to acknowledge the START byte.

Bus clear

In the unlikely event where the clock (SCL) is stuck LOW, the preferential procedure is to reset the bus using the HW reset signal if your I

2

C devices have HW reset inputs. If the

I

2

C devices do not have HW reset inputs, cycle power to the devices to activate the mandatory internal Power-On Reset (POR) circuit.

If the data line (SDA) is stuck LOW, the master should send 9 clock pulses. The device that held the bus LOW should release it sometime within those 9 clocks. If not, then use the

HW reset or cycle power to clear the bus.

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The I

2

C Bus Library

Wire Library

This library allows you to communicate with I

2

C / TWI devices. On the Arduino, SDA (data line) is on analog input pin 4, and SCL (clock line) is on analog input pin 5.

Functions

begin () begin (address) requestFrom (address, count) beginTransmission (address) endTransmission () send () byte available () byte receive () onReceive (handler) onRequest (handler)

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2,2 KΩ

Connection of I

2

C Master and Slave

5 V

3 5

SDA

SCL

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14

I

2

C Bus Extender 82B715

DESCRIPTION

The 82B715 is a bipolar integrated circuit intended for application in I

2

C bus systems. While retaining all the operating modes and features of the I

2

C system it permits extension of the practical separation distance between components on the I

2

C bus by buffering both the data (SDA) and the clock (SCL) lines.

The I

2

C bus capacitance limit of 400pF restricts practical communication distances to a few meters. Using one 82B715 at each end of longer cables reduces the cable loading capacitance on the I

2

C bus by a factor of 10 times and may allow the use of low cost general purpose wiring to extend bus lengths.

PHILIPS Data Sheet

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Minimum Sub-System with 82B715

PHILIPS Data Sheet

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Tasks for I

2

C

• The master sends a sign to the slave

• The slave answers with the next ASCII sign

• Input of the sign via keyboard of the PC

• Output to LCD (first row: sign of the master; second row: sign from the slave)

• Watch the signals on SDA and SCL on a scope

(sending a repeating a signal continuously)

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