PX1 User Manual - Blue Chip Technology
PX1
Single Board PC
User Manual
PX1
User Manual
Document Part N°
Document Reference
Document Issue Level
0127-1019
PX1\..\01271019.doc
1.3
Manual covers PCBs with the following Issue N°
1.x
(x is any digit)
All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or otherwise,
without the prior permission, in writing, from the publisher. For permission in the UK contact Blue Chip
Technology.
Information offered in this manual is believed to be correct at the time of printing. Blue Chip
Technology accepts no responsibility for any inaccuracies. The information contained herein is subject
to change without notice. There are no express or implied licences granted herein to any intellectual
property rights of Blue Chip Technology Ltd.
All trademarks and registered names acknowledged.
Blue Chip Technology Ltd.,
Chowley Oak, Tattenhall,
Chester, Cheshire,
CH3 9EX
Telephone : 01829 772000 Facsimile : 01829 772001
Amendment History
Issue
Level
0.1
0.2
1.0
1.1
1.2
1.3
Issue
Date
17/04/96
06/06/96
02/10/96
20/03/97
Author
20/10/97
SEJ
BH
EGW
EGW
EGW
Amendment Details
First Draft Issue
Revised & formatted
First Approved Issue
Updated for Issue 1.0 PCB (previously Rev C & C.1)
Additions to manual see ECN 97/100
CONTENTS
INTRODUCTION .......................................................................................... 1
MANUAL OBJECTIVES................................................................................. 1
LIMITATIONS OF LIABILITY....................................................................... 1
PRECAUTIONS............................................................................................... 2
ELECTRO-STATIC DISCHARGES ............................................................... 2
ON-BOARD BATTERY ................................................................................. 2
RELATED PUBLICATIONS ........................................................................... 3
TRADEMARKS............................................................................................... 3
USER GUIDE ................................................................................................. 5
OVERVIEW..................................................................................................... 5
BOARD LEVEL FEATURES......................................................................... 6
CPU ............................................................................................................. 6
PROCESSOR UPGRADE ............................................................................. 7
SECOND LEVEL CACHE ............................................................................ 7
SYSTEM MEMORY....................................................................................... 7
BUS EXPANSION SLOTS............................................................................. 8
ELECTROMAGNETIC COMPATIBILITY..................................................... 8
SPECIFICATION........................................................................................... 10
HARDWARE DESCRIPTION .................................................................... 10
PERIPHERAL COMPONENT INTERCONNECT (PCI) PCISET .................. 11
82437FX TRITON SYSTEM CONTROLLER (TSC) ..................................... 12
82438FX TRITON DATA PATH (TDP) ....................................................... 12
82371FB PCI ISA/IDE ACCELERATOR (PIIX) .......................................... 12
IDE SUPPORT ........................................................................................... 12
SMC 37C932 SUPER I/O CONTROLLER ..................................................... 14
FLOPPY CONTROLLER ............................................................................ 14
KEYBOARD INTERFACE .......................................................................... 14
REAL TIME CLOCK, CMOS RAM AND BATTERY.................................... 15
S3 GRAPHICS SUBSYSTEM ........................................................................ 15
RESOLUTIONS SUPPORTED.................................................................... 16
BIOS .............................................................................................................. 16
SETUP UTILITY ......................................................................................... 17
PCI SUPPORT............................................................................................ 17
ISA PLUG AND PLAY ................................................................................ 17
AUTO-CONFIGURATION CAPABILITIES ................................................ 17
ADVANCED POWER MANAGEMENT....................................................... 18
SLEEP MODE SUPPORT........................................................................... 18
Blue Chip Technology Ltd.
01271019.doc
CONTENTS
SECURITY FEATURES ..............................................................................19
CONNECTORS..............................................................................................19
BACK PANEL CONNECTORS ...................................................................19
ON-BOARD CONNECTORS.......................................................................20
BUS CONNECTORS...................................................................................22
JUMPERS.......................................................................................................22
CPU FREQUENCY SELECTION J1 & J11.................................................22
ON-BOARD VIDEO J6 ...............................................................................24
CMOS BATTERY SOURCE (CLEAR CMOS) J13........................................24
ISA BUS CLOCK J12..................................................................................24
MMX SETTINGS J10 ..................................................................................24
TABLE OF JUMPERS ................................................................................25
STATUS LEDS ............................................................................................26
USER-INSTALLABLE UPGRADES..............................................................27
SYSTEM MEMORY.....................................................................................27
REAL TIME CLOCK BATTERY REPLACEMENT ......................................28
CPU UPGRADE .........................................................................................28
GRAPHICS MEMORY UPGRADE..............................................................28
SOFTWARE DESCRIPTION ......................................................................28
BIOS SETUP..................................................................................................29
OVERVIEW OF THE SETUP MENU SCREENS ..........................................29
MAIN SCREEN...........................................................................................29
OVERVIEW OF THE SETUP KEYS ............................................................32
STANDARD SETUP....................................................................................32
ADVANCED CMOS SETUP........................................................................34
ADVANCED CHIPSET SETUP...................................................................38
POWER MANAGEMENT SETUP ...............................................................39
PCI / PNP SETUP.......................................................................................42
PERIPHERAL SETUP ................................................................................45
DISKONCHIP 2000 SUPPORT ...................................................................49
1. PREFACE ..................................................................................................49
2. OPERATING THE DISKONCHIP .............................................................50
2.1 INSTALLING THE DISKONCHIP 2000 ................................................50
2.2 CONFIGURING THE DISKONCHIP 2000 AS THE BOOT DEVICE ....50
2.3 CONFIGURING THE DISKONCHIP 2000 AS THE FIRST DRIVE .......51
BIOS EXTENSIONS SOFTWARE INTERFACE...........................................52
ENABLING BIOS EXTENSIONS.................................................................52
ACCESSING INT 50H FUNCTIONS ...........................................................52
INT 50H FUNCTION DEFINITIONS ..........................................................53
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Blue Chip Technology Ltd.
CONTENTS
APPENDICES............................................................................................... 55
ADDRESS MAPS .......................................................................................... 56
MEMORY MAP .......................................................................................... 56
I/O MAP ..................................................................................................... 56
PCI CONFIGURATION SPACE MAP ........................................................ 58
INTERRUPTS & DMA CHANNELS............................................................ 59
CONNECTORS ............................................................................................. 60
BACK PANEL CONNECTORS ................................................................... 60
INTERNAL I/O HEADERS ......................................................................... 61
FLOPPY DISK DRIVE CONNECTOR P2 (34 WAY HEADER).................... 62
POWER CONNECTOR P5 (4 WAY 5¼" DISK DRIVE CONNECTOR) ....... 63
ECP/EPP PARALLEL PORT P6 (26 WAY HEADER).................................. 64
BATTERY CONNECTOR P17 (4 WAY HEADER) ....................................... 67
BUS CONNECTORS................................................................................... 67
ERROR MESSAGES ..................................................................................... 72
AMIBIOS ERROR BEEP CODES ............................................................... 73
AMIBIOS ERROR CODES ON THE POST DISPLAY ................................. 74
AMIBIOS ERROR MESSAGES ................................................................... 79
ISA NMI MESSAGES.................................................................................. 81
PCI CONFIGURATION ERROR MESSAGES............................................. 81
BOARD LAYOUT ......................................................................................... 83
Blue Chip Technology Ltd.
01271019.doc
COMPANY PROFILE
COMPANY PROFILE
Blue Chip Technology is the leading specialist PC product manufacturer in
UK/Europe.
Blue Chip Technology provides innovation with quality design and
manufacturing from a single source.
Based in the North West, our purpose built complex contains one of the most
advanced research and development facility, engineering workshop and
production lines.
Specialising in the provision of industrial computing and electronic solutions
for a wide range of UK and European organisations, Blue Chip Technology
has one of the UK's largest portfolios of industrial PCs, peripherals and data
acquisition cards. This extensive range of products, coupled with our
experience and expertise, enables Blue Chip Technology to offer an industrial
processing solution for any application. The PX1 Single Board PC is the
latest addition to our portfolio, providing a cost effective product development
and volume production tool for OEMs.
A unique customisation and specialised system integration service is also
available, delivering innovative solutions to customers problems. The
company's success and reputation in this area has led to a number of large
design and manufacturing projects for companies such as BNFL, Aston
Martin, JaguarSport and British Gas.
British Standards Institute approval (BS EN 9001) means that all of Blue
Chip Technology's design and manufacturing procedures are strictly
controlled, ensuring the highest levels of quality, reliability and performance.
Blue Chip Technology are also committed to the single European market and
continue to invest in the latest technology and skills to provide high
performance computer and electronic solutions for a world-wide customer
base.
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Blue Chip Technology Ltd.
PX1 USER MANUAL
INTRODUCTION
PAGE 1
INTRODUCTION
MANUAL OBJECTIVES
This manual describes in detail the Blue Chip Technology PX1 Single Board
processor card.
We have tried to include as much information as possible but we have not
duplicated information that is provided in the standard IBM Technical
References, unless it proved to be necessary to aid in the understanding of the
PX1 Single Board PC.
The manual is sectioned into logical parts and includes a User Guide which
will help the non technical get the unit up and running. A Troubleshooting
Guide is also included to help when things go wrong.
We strongly recommend that you study this manual carefully before
attempting to interface with PX1 or change the standard configurations.
Whilst all the necessary information is available in this manual we would
recommend that unless you are confident, you contact your supplier for
guidance.
Please be aware that it is possible to create configurations within the CMOS
RAM that make booting impossible. If this should happen, clear the CMOS
settings, (see the description of the Jumper Settings for details).
If you have any suggestions or find any errors concerning this manual and
want to inform us of these, please contact our Customer Support department
with the relevant details.
LIMITATIONS OF LIABILITY
In no event shall Blue Chip Technology be held liable for any loss, expenses
or damages of any kind whatsoever, whether direct, indirect, incidental or
consequential, arising from the design or use of this product or the support
materials supplied with this product. If this product proves to be defective,
Blue Chip Technology is only obliged to replace or refund the purchase price
at Blue Chip Technology's discretion according to their Terms and
Conditions of Sale.
Blue Chip Technology Ltd.
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PAGE 2
INTRODUCTION
PX1 USER MANUAL
PRECAUTIONS
It is imperative that precautions are taken to avoid electro-static discharges,
or any maltreatment of the on-board battery.
ELECTRO-STATIC DISCHARGES
The devices on this card can be totally destroyed by static electricity.
Ensure that you take necessary static precautions, ideally wear an approved
wrist strap or touch a suitable ground to discharge any static build up. This
should be repeated if the handling is for any length of time.
When carrying the board around, please place it into the non-conductive
bag in which it came. This will prevent any static electricity build up.
ON-BOARD BATTERY
This board is fitted with a Lithium battery. Great care should be taken with
this type of battery. Under NO circumstances should :
• the outputs be shorted
• be exposed to temperatures in excess of 100°C
• be burnt
• be immersed in water
• be unsoldered
• be recharged
• be disassembled
If the battery is mistreated in any way there is a very real possibility of fire,
explosion, and harm.
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PX1 USER MANUAL
INTRODUCTION
PAGE 3
RELATED PUBLICATIONS
The following publications will provide useful information related to the
Standard Personal Computer and can be used in conjunction with this
manual.
• IBM Personal Computer AT Technical Reference, 1502494, IBM, 1984.
• IBM Personal System/2 and Personal Computer BIOS Interface Technical
Reference, 15F0306, IBM, 1987.
• The Programmers PC Sourcebook, Microsoft
• The Winn L. Rosch Hardware Bible, Brady
• PC104 Consortium Technical Specification
TRADEMARKS
IBM, PC, AT and PS/2 are trademarks of International Business Machines
Corporation (IBM).
AMI Hi-Flex BIOS is a trademark of American Megatrends Inc.
Intel is a registered trademark of the Intel Corporation.
All 80x86 and Pentium processors are registered trademarks of Intel
Corporation.
MSDOS and WINDOWS are registered trademarks of the Microsoft
Corporation.
PC/104 is a registered trademark of the PC/104 Consortium.
Blue Chip Technology Ltd.
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PAGE 4
01271019.doc
INTRODUCTION
PX1 USER MANUAL
Blue Chip Technology Ltd.
PX1 USER MANUAL
USER GUIDE
PAGE 5
USER GUIDE
OVERVIEW
The Blue Chip Technology PX1 single board PC sets new standards for
integration of the latest advances in processor, memory, and I/O technologies.
The PX1 complies with the new PICMG form factor providing ISA, PCI and
PC/104 bus interfaces on a single PC/AT plug-in card. The PICMG single
board PC is an ideal platform for the increasing requirements of today's and
tomorrow's embedded applications.
The flexible PICMG design will accept Pentium processors operating at 75,
90, 100, 120, 133, 150, 166 and 200 MHz. The user may install 256 KB of
asynchronous Cache, or 256 KB or 512 KB of Pipeline Burst Cache RAM in
the form of a COAST (Cache On A STick) Module. The memory sub-system
is designed to support up to 128 MB of EDO DRAM (for improved
performance) or standard Fast Page DRAM in standard 72-pin SIMM
sockets. A Type 7 Pentium OverDrive socket provides upgrades for future
OverDrive processors.
The PX1 single board PC utilises Intel’s Triton 82430 PCIset to provide
increased integration and performance over other single board PC designs.
The Triton PCIset contains an integrated PCI Bus Mastering IDE controller
with two high performance IDE interfaces allowing up to four IDE devices
(such as hard drives, CD-ROM readers, etc.). The SMC 37C932 Super I/O
controller integrates the standard PC I/O functions: floppy interface, two
FIFO serial ports, one EPP/ECP capable parallel port, a Real Time Clock,
keyboard and mouse (PS/2) controller.
The PX1 also provides for driving up to three external PCI local bus slots.
These provide a high bandwidth data path for data-movement intensive
functions such as video or networking. Up to fourteen ISA slots may be
driven to complete the I/O capability.
In addition to superior hardware capabilities, a full set of software drivers and
utilities are available to allow advanced operating systems such as
Windows™ 95 to take full advantage of the hardware capabilities. Features
such as bus mastering IDE, Windows™ 95-ready Plug and Play, Advanced
Power Management (APM) are available for the PX1.
Blue Chip Technology Ltd.
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USER GUIDE
PX1 USER MANUAL
BOARD LEVEL FEATURES
• Socket-7 Pentium™ Processor socket supporting 75 - 166 MHz
operation
• On-board 3.3 V CPU voltage regulator
• Intel Triton 82430 PCISet chipset:
82437FX System Controller (TSC)
82438FX Data Path (TDP)
82371FB PCI ISA/IDE Accelerator (PIIX)
• 256KB or 512 KB PipeLine Burst Level 2 cache or 256 KB
Asynchronous Level 2 cache using plug-in COAST connector
• Four SIMM sockets providing up to 128 MByte of EDO or FPM
DRAM
• S3 Trio PCI graphics controller with:
1 MByte standard video memory
Plug-in option for 2MByte
Video feature connector
• PICMG compliant PCI, ISA & PC/104 expansion busses
• SMC 37C932 I/O controller providing:
Dual PCI IDE interfaces
Dual floppy interface
Dual 16C550 RS-232/422/485 serial interfaces
EPP/ECP bi-directional parallel interface
• Real-time clock with on-board battery
• PS/2 mouse and keyboard connectors
• On-board Solid State Disk - Flash and SRAM
• Security microcontroller providing power monitoring and reset
control
• On-board status LEDs
• Drive for up to 14 ISA, 3 PCI expansion slots and 3 PC/104 cards
CPU
The PX1 single board PC is designed to operate with Pentium Processors
running at 3.3, 3.45 or 3.6 Volts. An on-board voltage regulator circuit
provides the required voltage for the processor from the 5 volt output of a
standard PC power supply. On-board jumpers enable the use of VRT
specified processors. Pentium processors which run internally at 75, 90,
100, 120, 133, 150, 166, 180 and 200 MHz are supported.
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USER GUIDE
PAGE 7
The Pentium processor maintains full backward compatibility with the
8086, 80286, i386 and Intel486 processors. It supports both read and
write burst mode bus cycles, and includes separate 8 KB on-chip code and
8 KB data caches which employ a write-back policy. Also integrated into
the Pentium processor is an advanced numeric co-processor which
significantly increases the speed of floating point operations, whilst
maintaining backward compatibility with i486DX math co-processor and
complying to ANSI/IEEE standard 754-1985.
PROCESSOR UPGRADE
The PX1 single board PC has a 321-pin Zero Insertion Force (ZIF)
processor socket (socket 7) that provides users with an OverDrive processor
upgrade path. OverDrive processors being developed for use with socket 7
will provide performance beyond that delivered by the originally installed
Pentium Processor.
SECOND LEVEL CACHE
The Pentium processor's internal cache can be complemented by a second
level cache using the COAST connector. Pipeline Burst SRAM provides
performance similar to expensive Synchronous Burst SRAMs for only a
slight cost premium over the slower performing Asynchronous SRAMs.
With the Triton chipset, the performance level of Pipeline Burst and
Synchronous SRAMs is identical.
SYSTEM MEMORY
The PX1 single board PC provides four 72-pin SIMM sites for memory
expansion. The sockets support 1M x 32 (4 MB), 2M x 32 (8 MB), 4M x 32
(16 MB), and 8M x 32 (32 MB) single-sided or double-sided SIMM
modules. Minimum memory size is 8 MB and maximum memory size,
using four 8M x 32 SIMM modules, is 128 MB. Memory timing requires
70 ns fast page devices or, for optimum performance, 60nS EDO DRAM. If
the memory bus speed is 60 MHz or slower (75MHz, 90MHz, 120MHz,
150MHz or 180MHz Pentium Processor speed), 70ns EDO DRAM may be
used. If the memory bus speed is 66 MHz, 60 ns DRAM should be used.
Additionally, 36-bit SIMM modules may be used, but parity generation and
checking are not supported. EDO DRAM is designed to improve DRAM
read performance.
The four sockets, identified as SIMM-1, -2, -3 & -4 on the PCB layout
diagram at the end of the manual, are arranged as Bank A and Bank B.
Blue Chip Technology Ltd.
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USER GUIDE
PX1 USER MANUAL
Each bank consists of two sockets, providing a 64-bit wide data path. Both
SIMMs in a bank must be of the same memory size and type, although the
memory type and size may be different between Banks A and B. It is even
possible to have 70 ns Fast Page DRAM in one bank and 60 ns EDO
DRAM in the other, in which case each bank is independently optimised
for maximum performance. At least one Bank must be populated. Bank A
only, Bank B only, or both banks may be populated. There are no jumper
settings required for the memory size or type, which is automatically
detected by the system BIOS.
BUS EXPANSION SLOTS
The PX1 is designed for use in a passive backplane providing expansion
slots for add-in cards. There may be up to 14 ISA bus expansion connectors
and three PCI expansion connectors. One slot is shared by both types of
connector - this is reserved for the PX1 processor card. All PCI expansion
slots accept PCI bus master cards, and fully support the PCI specification
version 2.0.
In addition, the board incorporates a set of PC/104 connectors to allow up
to three PC/104 expansion units to be fitted on board without occupying a
bus slot in the backplane.
PCI 3.3 VOLT CAPABILITIES
Support for 3.3 Volts to the PCI connectors requires a power supply with
a 3.3V DC output. The PICMG power connector definition has 3 pins
reserved for 3.3V. The PX1 on-board voltage regulator only provides
3.3V (or 3.45, or 3.6V) to the CPU, Triton chipset, and cache. No other
on-board resources require 3.3V.
ELECTROMAGNETIC COMPATIBILITY
This product meets the requirements of the European EMC Directive
(89/336/EEC) and is eligible to bear the CE mark.
It has been assessed operating in a Blue Chip Technology ICON industrial
PC. However, because the board can be installed in a variety of computers,
certain conditions have to be applied to ensure that the compatibility is
maintained. Subject to those conditions, it meets the requirements for an
industrial environment (Class A product).
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USER GUIDE
• The board must be installed in a computer system chassis which
provides screening suitable for the industrial environment.
• Any recommendations made by the computer system
manufacturer/supplier must be complied with regarding earthing and
the installation of boards.
• The board must be installed with the backplate securely screwed to the
chassis of the computer to ensure good metal-to-metal (i.e. earth)
contact.
• Most EMC problems are caused by the external cabling to boards. It is
imperative that any external cabling to the board is totally screened, and
that the screen of the cable connects to the metal end bracket of the
board and hence to earth. It is recommended that round screened cables
with a braided wire screen are used in preference to those with a foil
screen and drain wire. Use metal connector shells which connect
around the full circumference of the screen: they are far superior to
those which earth the screen by a simple “pig-tail”.
• The keyboard will play an important part in the compatibility of the
processor card since it is a port into the board. Similarly, it will affect
the compatibility of the complete system. A fully compatible keyboard
must be used otherwise the complete system could be degraded. The
keyboard itself may radiate or behave as if keys are pressed when subject
to interference. Under these circumstances it may be beneficial to add a
ferrite clamp on the keyboard lead as close as possible to the connector.
A suitable type is the Chomerics type H8FE-1004-AS.
• Ensure that the screens of any external cables are bonded to a good RF
earth at the remote end of the cable.
Failure to observe these recommendations may invalidate the EMC
compliance.
Warning
This is a Class A product. In a domestic environment this
product may cause radio interference in which case the user
may be required to take adequate measures.
Blue Chip Technology Ltd.
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USER GUIDE
PX1 USER MANUAL
SPECIFICATION
PX1 Power
Requirement
+5 V ± 5%
+12 V ± 5%
+3.3 V ± 5%
-5 V ± 5%
-12 V ± 5%
Typical System
Consumption
35 Watts
Required for processor operation.
Only required with security / monitor
micro-controller option.
 Not required for board operation.
 The ISA, PC104 & PCI voltage
 rails are linked, on board.
Pentium 100, 16 MB RAM, 256 KB
L2 cache, 3½" FDD, 540 MB HDD
Temperature
Non-Operating -40°C to +70°C
Operating
+0°C to +55°C
(min. airflow of 200 lpm)
Shock
Non-Operating Half sine, 2ms, 1 m drop
Vibration
Non-Operating 5 Hz - 500 Hz, 3.1 g RMS random
Operating
10 Hz - 500 Hz, 1.0 g RMS random
EMC
Emissions
Immunity
EN55022 (A)
EN50082-2 in a Blue Chip ICON
Industrial PC Chassis
MTBF
Calculated
72,000 Hrs
Dimensions
Board only
338 x 122 mm
Power Consumption figures given are for a typical configuration.
This information is preliminary and is provided only as a guide to
calculating approximate total system power usage when additional
resources are added.
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HARDWARE DESCRIPTION
HARDWARE DESCRIPTION
PERIPHERAL COMPONENT INTERCONNECT (PCI) PCISET
The Intel Triton 82430FX PCIset consists of the 82437FX Triton System
Controller (TSC), two 82438FX Triton Data Path (TDP) devices, and one
82371FB PCI ISA/IDE Accelerator (PIIX) bridge chip. The Triton PCIset
provides the following functions:
• CPU interface control
• Integrated L2 write-back cache controller
– Pipelined Burst SRAM
– 256KB or 512KB Direct Mapped
• Integrated DRAM controller
– 64-bit path to Memory
– Support for EDO and Fast Page DRAM
– 8 MB to 128 MB main memory
• Fully synchronous PCI bus interface
– 25/30/33 MHz
– PCI to DRAM > 100 MBytes/sec
– PCI to DRAM posting of 12 Dwords
– 5 Dword buffers for CPU to PCI write posting
– 4 Dword buffers for PCI to Memory bus master cycles
– Support for up to 5 PCI masters
• Interface between the PCI bus and ISA bus
• Integrated fast IDE interface
– Support for up to 4 devices
– PIO Mode 4 transfers up to 16MB/sec
– Integrated 8 x 32-bit buffer for PCI IDE burst transfers
• Enhanced Fast DMA controller
• Interrupt controller and steering
• Counters/Timers
• SMI interrupt logic and timer with Fast On/Off mode
Note: Not all chipset functions are utilised in the design of the PX1, in
particular only three off board PCI expansion slots are available.
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PX1 USER MANUAL
HARDWARE DESCRIPTION
82437FX TRITON SYSTEM CONTROLLER (TSC)
The 82437FX provides all control signals necessary to drive a second level
cache and the DRAM array, including multiplexed address signals. It also
controls system access to memory and generates snoop controls to maintain
cache coherency.
82438FX TRITON DATA PATH (TDP)
There are two 82438FX components which provide data bus buffering and
dual port buffering to the memory array. Controlled by the 82437FX, the
82438FX devices add one load each to the PCI bus and perform all the
necessary byte and word swapping required. Memory and I/O-write buffers
are included in these devices.
82371FB PCI ISA/IDE ACCELERATOR (PIIX)
The 82371FB provides the interface between the PCI and ISA buses and
integrates a dual channel fast IDE interface capable of supporting up to 4
devices. The 82371FB integrates seven 32-bit DMA channels, five 16-bit
timer/counters, two 8-channel interrupt controllers, PCI-to-AT interrupt
mapping circuitry, NMI logic, ISA refresh address generation, and PCI/ISA
bus arbitration circuitry together all on one device.
IDE SUPPORT
The PX1 single board PC provides two independent high performance busmastering PCI IDE interfaces capable of supporting PIO Mode 3 and Mode
4 devices. The system BIOS supports Logical Block Addressing (LBA) and
Extended Cylinder Head Sector (ECHS) translation modes as well as
AT API (e.g. CD-ROM) devices on both IDE interfaces. Detection of IDE
device transfer rate and translation mode capability is automatically
determined by the system BIOS.
In the Windows™ 95 environment, a driver can allow the IDE interface to
operate as a PCI bus master capable of supporting PIO Mode 4 devices with
transfer rates up to 16MB/sec while minimising the system demands upon
the processor. Normally, programmed I/O operations require a substantial
amount of CPU bandwidth. In true multi-tasking operating systems like
Windows™ 95, the CPU bandwidth freed up by using bus mastering IDE
can be used to complete other tasks while disk transfers are occurring.
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PAGE 13
Microsoft will provide this driver for Windows™ 95, other software
vendors may make drivers available for other operating systems.
Detailed information on the PCIset is available in the Intel 82430 PCISet
data sheet.
Blue Chip Technology Ltd.
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HARDWARE DESCRIPTION
PX1 USER MANUAL
SMC 37C932 SUPER I/O CONTROLLER
Control for the integrated serial ports, parallel port, floppy drive, RTC and
keyboard controller is incorporated into a single component, the SMC
37C932. This component provides:
• Two NS16C550-compatible UARTs with send/receive 16 byte FIFO
• Multi-mode bi-directional parallel port
- Standard mode; IBM and Centronics compatible
- Enhanced Parallel Port (EPP) with BIOS/Driver support
- High Speed mode; Extended Capabilities Port (ECP) compatible
• Industry standard floppy controller with 16 byte data FIFO (2.88 MB
floppy support)
• Integrated Real Time Clock
• Integrated 8042 compatible keyboard controller
The 37C932 is normally configured by the BIOS automatically, however
configuration of these interfaces is possible via the CMOS Setup program that
can be invoked during boot-up. The serial ports can be enabled as COM1,
COM2, or disabled. The parallel port can be configured as normal, extended,
EPP/ECP, or disabled. The floppy interface is configurable.
Header connectors located near the top of the board allow cabling to use these
interfaces.
FLOPPY CONTROLLER
The 37C932 is software compatible with the DP8473 and 82077 floppy disk
controllers.
The floppy interface can be configured for 360 KB or 1.2 MB 5¼" media or
for 720 KB, 1.44 MB, or 2.88 MB 3½" media in the BIOS setup. By
default, the Floppy A interface is configured for 1.44 MB and Floppy B is
disabled.
KEYBOARD INTERFACE
PS/2 keyboard/mouse connectors are located on the back panel side of the
single board PC. The 5V lines to these connectors are protected by a fuse.
Care must be taken to turn off the system power before installing or
removing a keyboard or mouse, otherwise the fuse may rupture, and result
in a return-to-base repair.
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HARDWARE DESCRIPTION
PAGE 15
The integrated 8042 microcontroller contains the AMI Megakey
keyboard/mouse controller code which, besides providing traditional
keyboard and mouse control functions, supports Power-On/Reset (POR)
password protection. The POR password can be defined by the user in the
Setup program. The keyboard controller also provides the facility for a
<CTRL><ALT><DEL> "hot key" sequence to perform a system software
reset. It performs this by jumping to the beginning of the BIOS code and
running the POST operation.
REAL TIME CLOCK, CMOS RAM AND BATTERY
The integrated Real Time Clock (RTC) is DS1287 and MC146818
compatible and provides a time of day clock, 100-year calendar with alarm
features. The RTC can be set via the BIOS SETUP program. The RTC also
supports 242 bytes of battery-backed CMOS RAM in two banks which is
reserved for BIOS use. The CMOS RAM can be set to specific values or
cleared to the system default values using the BIOS SETUP program. Also,
the CMOS RAM values can be cleared to the system defaults by using a
configuration jumper on the single board PC. The appendix lists the jumper
configurations.
An on-board Lithium battery provides power to the RTC and CMOS
memory. The battery has an estimated lifetime of three years if the board
remains unpowered. When the system is powered up, power is drawn from
the PICMG supply to extend the life of the battery.
S3 GRAPHICS SUBSYSTEM
The PX1 single board PC is provided with an S3 Trio64V SVGA graphics
controller with 1 MB of graphics memory upgradeable to 2 MB. The graphics
DRAM can be upgraded to 2 MB by installing two 256kB x 16, SOJ memory
devices in the provided sockets. The Trio64V has a 64-bit graphics engine
that provides acceleration for scaling the video display without compromising
picture quality or frame rate. The on-chip RAMDAC/clock synthesiser is
capable of output pixel data rates of 135 MHz providing non-interlaced screen
resolutions of up to 1280 x 1024 x 256 colours at 75 Hz with 2MB of DRAM.
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Hardware acceleration for graphics functions such as BitBLTs with ROPs,
2-point line draws, trapezoidal and polygon fills, clipping and cursor support
provide high performance operation under Windows™ and other GUI
environments. In addition, a fast linear addressing scheme reduces the
software overhead by mapping the display memory into the CPU’s upper
memory address space and allowing direct CPU access to the display memory.
The PX1 single board PC supports the 26-pin VESA feature connector for
synchronising graphics output with an external NTSC or PAL signal and a
shared frame buffer interface to maximise multi-media performance. PX1
also supports other VESA standards such as the VESA DPMS protocol to put
a DPMS compliant monitor into power saving modes and the VESA Display
Data Channel (DDC2B) which permits transfer of monitor identification and
resolution support data for ease of use.
RESOLUTIONS SUPPORTED
RESOLUTION
640 x 48 0x 4
640 x 480 x 8
640 x 480 x 16
640 x 480 x 24
800 x 600 x 8
800 x 600 x 16
800 x 600 x 24
1024 x 768 x 8
1024 x 768 x 16
1280 x 1024 x 4
1280 x 1024 x 8
1 MB
DRAM
X
X
X
X
X
X
X
2 MB
DRAM
X
X
X
X
X
X
X
X
X
X
X
REFRESH RATE (HZ)
60, 72, 75, 85
60, 72, 75
60, 72, 75
56, 60, 72, 75, 85
60, 72, 75
60, 72, 75
43(Interlaced), 60, 70, 75, 85
43(Interlaced), 60, 70, 75
45(Interlaced), 60, 72, 75
45(Interlaced), 60, 72, 75
BIOS
The PX1 single board PC uses an AMI System BIOS and an S3 Video BIOS
both of which are stored in EPROM. In addition to the System and Video
BIOSes, the EPROM also contains the Setup utility, Power-On Self Tests
(POST), and the PCI auto-configuration utility. This single board PC supports
system BIOS shadowing, allowing the BIOS to execute from 64-bit on-board
write-protected DRAM.
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The BIOS displays a sign-on message during POST identifying the type of
BIOS and a revision code.
SETUP UTILITY
The ROM-based Setup utility allows the configuration to be modified
without opening the system for most basic changes. The Setup utility is
accessible only during the Power-On Self Test (POST) by pressing the
<DEL> key after the POST memory test has started and before boot begins.
A prompt may be enabled that informs users to press the <DEL> key to
access Setup.
PCI SUPPORT
The AMI BIOS supports Version 2.0 of the PCI BIOS specification.
Support is also provided for Version 1.0 of the PCI bridge specification.
PCI-to-PCMCIA bridging can also be supported using third party
expansion cards.
ISA PLUG AND PLAY
The AMI BIOS incorporates ISA Plug and Play capabilities as defined by
the Plug and Play Release 1.0A specification (Plug and Play BIOS
Version 1.0A, ESCD Version 1.02). This allows auto-configuration of Plug
and Play ISA cards, and resource management for non-Plug and Play (or
legacy) ISA cards, when used in conjunction with Plug and Play aware
operating systems (such as Windows™ 95).
AUTO-CONFIGURATION CAPABILITIES
The auto-configuration utility operates in conjunction with the system
Setup utility to allow the insertion and removal of PCI and ISA Plug and
Play cards to the system without user intervention (Plug & Play). When the
system is turned on after adding a PCI or ISA Plug and Play card, the BIOS
automatically configures interrupts, DMA channels, I/O space, and memory
space. The user does not have to configure jumpers or worry about
potential resource conflicts. Because PCI and ISA Plug and Play cards use
the same interrupt resources as ISA cards, the user can specify the
interrupts used by ISA add-in cards in the Setup utility.
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If using Windows™ 95, the auto-configuration utility only initialises the
devices required to boot up, Windows™ 95 initialises all the other devices
since it is a Plug and Play aware operating system.
ADVANCED POWER MANAGEMENT
The PX1 AMI BIOS supports power management through System
Management Mode (SMM) interrupts to the CPU and Advanced Power
Management (APM Version 1.1). In general, power management
capabilities will allow the system to be put into a power managed, Stand-by
mode either by entering a user configurable hot-key sequence on the
keyboard, or by the expiration of a hardware timer which detects system
inactivity for a user-configurable time. When in the Stand-by mode, the
PX1 single board PC reduces power consumption by using the power
saving capabilities of the Pentium processor and also running down hard
drives and turning off DPMS compliant monitors. Add-in cards supplied
with APM-aware drivers can also be put into a power managed state for
further energy savings. The ability to respond to external interrupts is fully
maintained while in Stand-by mode, allowing the system to service requests
(such as in-coming Fax’s or network messages) while unattended, albeit
slowly until the system wakes up.
SLEEP MODE SUPPORT
When Advanced Power Management (APM) is activated in the System
BIOS and the Operating System’s APM driver is loaded, Sleep mode
(Stand-By) can be entered in one of three ways.
Sleep/Resume may be activated by using either a momentary-action sleep
switch in the UTILS header, a keyboard hot-key sequence, or by a time-out
of the system inactivity timer. Both the keyboard hot-key and the inactivity
timer are programmable in the BIOS setup (timer is set to 10 minutes by
default). To re-activate the system, or “Resume”, the user simply uses the
keyboard or mouse, or presses the sleep switch. Note that mouse activity
will only “wake up” the system if a mouse driver is loaded. While the
system is in Stand-By or “Sleep” mode it is fully capable of responding to,
and servicing external interrupts, even though the monitor will only turn on
if a user interrupt occurs as mentioned above.
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SECURITY FEATURES
SUPERVISOR PASSWORD
If enabled, the supervisor password protects all sensitive Setup options
from being changed by a user unless the password is entered (see
appendix).
If the password is forgotten, it may be cleared by turning off the system
and clearing the CMOS RAM.
USER PASSWORD
The User Password feature provides access to all setup options that do not
require the supervisor password. The User Password feature also
provides security during the boot process. The User Password can be
enabled using the Setup utility. (At boot-up, the system will complete the
operating system boot up process, but keyboard and mouse operation will
be locked until the User Password is entered. See the Security Menu
section of the appendix for more details.)
If the password is forgotten, it can be cleared by turning off the system
and clearing the CMOS RAM..
CONNECTORS
Three sets of connectors are incorporated on the PX1 PC board. These
provide connectivity to standard external peripherals (monitor, keyboard,
etc.), in-chassis peripherals (disk drives, etc.), and bus devices. A complete
table of the available connectors and their pin-outs is given in the appendices.
The PC board layout at the end of the manual shows their positions.
BACK PANEL CONNECTORS
The back panel provides external access to the VGA, PS/2 mouse, keyboard
and the first serial communications port interfaces. All the connectors
follow the industry standard. The diagram shows the general location of
the connectors.
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VGA (P12)
PS/2 Mouse (P13)
RS232 Serial 1 (P15)
PS/2 Keyboard (P18)
ON-BOARD CONNECTORS
There are connectors on-board for Floppy Disk Drive, IDE, and VESA
feature connector. There are also sockets for graphics memory upgrade (if
graphics is present), SIMMs, and external battery.
Connectors are provided for the following peripheral functions:
• Second serial comms port RS232 and RS485;
• Parallel port;
• Floppy disk drives;
• Primary and secondary IDE devices.
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HARDWARE DESCRIPTION
In addition, connectors provide for:
• An external battery, for battery-backed SRAM installations;
• Power supply connection, for stand-alone no backplane applications ;
• Front panel components (switches, LED, speaker, etc.). This utility
connector is described in more detail below;
• On-board programming of the EPLD. This is for manufacture only,
and is not a user connection.
UTILITY CONNECTOR
The PX1 PC board provides connectors to support functions which would
normally be located within the enclosure, and also duplicate connections
for some of the external interfaces (System Speaker, System Reset
Switch, , Keyboard, Power LED Hard Drive Activity LED, an External
Battery and a Sleep/Resume switch).
SPEAKER
An on-board Piezo speaker is included. It may be disabled by removing a
link on jumper, J3. An off-board speaker may be connected to the header
(P9 pins 1 & 2) and driven independently of the on-board buzzer. The
speaker provides error beep code information during the Power-On Self
Test if the system cannot use the video interface.
RESET
Two pins of header P9 (pins 3 & 4) may be connected to a momentary
normally open SPST switch. When the switch is closed, the system will
perform a hard reset and run the POST.
IDE LED
Two pins of header P9 (pins 13 & 14) may be connected to an LED to
provide a light when an IDE hard drive connected to the on-board IDE
controller is active.
SLEEP/RESUME SWITCH
Two pins of header P9 (pins 11 & 12) may be connected to a momentaryaction, normally-open SPST switch. The switch may be used to toggle
the PC in and out of SMM modes (i.e. Sleep / Resume).
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BUS CONNECTORS
The board incorporates the standard PC/AT 16-bit ISA bus, and PCI bus
connectors to passive backplanes. Additionally, the board has one set of
PC104/AT sockets for on-board expansion. See the appendices for the pinout details. Note that the PCI connector details the signals at the PX1
processor connector. These are different for each PCI slot on a backplane.
JUMPERS
Jumpers are used on the board to select various options. Some of the jumpers
are factory set to suit particular semiconductor options. These must not be
disturbed, or damage to the board may ensue. Refer to the board layout
drawing at the end of the manual for the positions of the various jumpers.
CPU FREQUENCY SELECTION J1 & J11
The external CPU bus operates at frequencies of 50, 60 and 66 MHz but is
scaled up internally giving a range of CPU frequencies of 75 to 166 MHz.
There are four links ( in two locations) involved in CPU frequency
selection: J1 and J11. Link J11 selects the host CPU operating frequency of
50, 60 and 66 MHz. Link J1 selects the clock scaling (multiplying) factor.
Link J1 is latched by the CPU on reset and used to configure the CPU phase
locked loop oscillator. This allows higher speed processors to be clocked
down (e.g. running a P133 as a P100), but over clocking processors is not
recommended as it will degrade the reliability of the device over time. Note
also that there are internal differences between each of the CPU types, i.e.
there are register differences between a P100 and a P133, it is not simply
silicon grading as was the case for 486 type CPUs.
INTERNAL CPU CLOCK SPEED J1
These jumpers sets the internal CPU clock speed to either 1½, 2, 2½ or
3 times that of the external CPU clock speed. These jumpers should be
configured depending on the speed of the processor.
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HARDWARE DESCRIPTION
CPU CLOCK
MULTIPLIER
1.5 x
2x
2.5 x
3x
PAIR
A
Open
Open
Link
Link
PAIR
B
Open
Link
Link
Open
EXTERNAL CPU CLOCK SPEED J11
This jumper block sets the CPU's external operating frequency to memory
at 50, 60, or 66 MHz. The default setting depends on the specific memory
and type of Pentium processor installed. It is used in conjunction with
J1.
EXTERNAL
BUS FREQ.
50 MHz
60 MHz
66 MHz
Reserved
PAIR
A
Link
Link
Open
Open
PAIR
B
Link
Open
Link
Open
SUMMARY OF LINK SETTINGS
CPU
CORE
SPEED
(MHZ)
75
90
100
120
133
150
166
HOST
BUS
SPEED
(MHZ)
50
60
66
60
66
60
66
Blue Chip Technology Ltd.
PCI
BUS
SPEED
(MHZ)
25
30
33
30
33
30
33
HOST
CLK
SCALING
FACTOR
1.5
1.5
1.5
2
2
2.5
2.5
J1
A
J1
B
J11
A
J11
B
Open
Open
Open
Open
Open
Link
Link
Open
Open
Open
Link
Link
Link
Link
Link
Link
Open
Link
Open
Link
Open
Link
Open
Link
Open
Link
Open
Link
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ON-BOARD VIDEO J6
The PX1 is equipped with a link (J6) to allow the user to disable the onboard video when external video adapters are being used. If a PCI video
adapter is fitted into a system, the on-board video will be automatically
disabled without having to fit a jumper on J6.
J6 must be fitted when using ISA based VGA adapter boards in a PX1
based system.
CMOS BATTERY SOURCE (CLEAR CMOS) J13
This jumper is used to clear the CMOS RAM in the event that the contents
become corrupt. It selects the source of backup power to the CMOS RAM,
and also allows the CMOS to be cleared down to the default settings.
Fitting the link to the “CLR” position with the power off, allows on-board
capacitors to discharge and will reset the CMOS memory. The jumper
should then be returned to the “NORM” position to restore normal
operation.
ISA BUS CLOCK J12
This jumper changes the clock frequency of the ISA bus. The effect of this
jumper on the ISA clock depends upon the setting of the CPU clock speed
jumpers. With the jumper linked, the clock frequency is divided by 8. With
the jumper open, the clock frequency is divided by 6, resulting in a higher
ISA bus frequency. The default setting for this jumper is “Linked”. In
general, this jumper should only be removed if higher ISA performance is
required, and the ISA expansion cards can handle the faster bus clock. (A
clock frequency of greater than 8.33 MHz violates the ISA specification,
although many ISA cards are designed to support higher clock frequencies.)
BUS FREQUENCY
50 MHz
60 MHz
66 MHz
ISA BUS SPEED
JUMPER LINKED
JUMPER OPEN
(÷8)
(÷6)
6.25 MHz
8.33 MHz
7.5 MHz
10 MHz
8.33 MHz
11 MHz
MMX SETTINGS J10
If an MMX CPU is used the links J10 x 3 must be set to VRT. Classic
pentiums must use the standard setting.
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HARDWARE DESCRIPTION
TABLE OF JUMPERS
JUMPER
J1
AREA OF INFLUENCE
Selects the internal CPU clock
speed.
Use in conjunction with J11
J2
COM-2 RS485 Termination
J3
On-board Speaker
J4
Video Memory Type.
J5
DRAM and Cache Voltage Select
J6
On-board video select
J7
Selects BIOS ROM Type
J8
BIOS Memory Type
J9
CPU Core Voltage Select
J10
CPU I/O Voltage Select
(3 links)
Select External Bus Frequency.
J11
Use in conjunction with J1
J12
J13
Selects ISA Bus Speed.
Bus speed depends on Bus
Frequency.
CMOS Battery Support
LINK
A
B
O O
O
L
L
L
L
O
None
Link
None
Link
FPM
EDO
3V
5V
None
Link
None
Link
None
1-2
2-3
None
2.9
3.3
3.45
3.6
VRT
STD
A
B
L
L
L O
O
L
O O
None
Link
ACTION
(External CPU speed)
x 1.5
x2
x 2.5
x3
Unterminated
Terminated by 100R + µ1
Disabled
Enabled
Fast Page Memory
Extended Data Out Memory
3 Volt
5 Volt (Default)
Enabled
Disabled
EPROM (Default)
Flash PROM
Factory setting only.
5 V Flash or EPROM (Default)
12 V Flash
Reserved
Not Allowed
2V9 CPU core
3V3 CPU core
3V45 CPU core
3V6 CPU core
VRT CPU (J10)
Standard CPU
External Bus Frequency
50 MHz
60 MHz
66 MHz
Reserved
(Bus speed) / 6
(Bus speed) / 8
None
CLR
NORM
Not Allowed
Clear CMOS RAM
Use on-board battery
In the table “L” indicates the presence of a link, “O” the absence.
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STATUS LEDS
Along the top edge of the PCB on the reverse side is a row of LEDs. These
are arranged in groups to indicate the status of various board functions:
P.O.S.T. DISPLAY
Red LEDs D10 to D17 inclusive display the Power On Self Test (POST)
data byte. Diode D17 represent the LSB and D10 the MSB. The LED is
illuminated when the POST data bit is 1. See the Appendix for details of
the error codes.
POWER SUPPLY INDICATORS
Green LEDs D5-D9 inclusive show the presence of the power supplies.
Each LED is illuminated when the appropriate voltage is present.
D9
D8
D7
D6
D5
Host CPU IO and chipset supply (3.3 Volts)
+ 5 Volt (Vcc) supply
+ 12 Volt supply
- 12 Volt supply
- 5 Volt supply
IDE ACTIVITY DISPLAY
Yellow LED D4 indicates primary and secondary IDE activity (Hard disk
or CD-ROM) and is illuminated when active.
SYSTEM RESET STATUS
Red LED D3 indicates the system reset status. The LED is illuminated
when in held in reset.
MONITOR MICROCONTROLLER STATUS
Yellow LED D2 indicates the status of the monitor microcontroller (if
fitted). The LED is illuminated when a fault condition has occurred.
WATCHDOG TIMER STATUS
Yellow LED D1 indicates the watchdog time out status. The LED is
illuminated when a timeout has occurred.
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HARDWARE DESCRIPTION
USER-INSTALLABLE UPGRADES
SYSTEM MEMORY
The table shows the possible memory combinations. The PX1 will support
both Fast Page DRAM or EDO DRAM SIMMs, but they cannot be mixed
within the same memory bank. If Fast Page DRAM and EDO DRAM
SIMMs are installed in separate banks, each bank will be optimised for
maximum performance.
Parity generation and detection are NOT
supported, but parity SIMMs (x36) may be used.
SIMM requirements are 70ns Fast Page Mode or 60nS EDO DRAM (70 ns
EDO may be used with a 60 MHz or slower external CPU clock) with tinlead connectors.
SIMM 1,2 (BANK A)
SIMM TYPE (AMOUNT)
1M X 32 (4 MB)
1M X 32 (4 MB)
1M X 32 (4 MB)
1M X 32 (4 MB)
1M X 32 (4 MB)
2M X 32 (8 MB)
2M X 32 (8 MB)
2M X 32 (8 MB)
2M X 32 (8 MB)
2M X 32 (8 MB)
4M X 32 (16 MB)
4M X 32 (16 MB)
4M X 32 (16 MB)
4M X 32 (16 MB)
4M X 32 (16 MB)
8M X 32 (32 MB)
8M X 32 (32 MB)
8M X 32 (32 MB)
8M X 32 (32 MB)
8M X 32 (32 MB)
SIMM 3,4 (BANK B)
SIMM TYPE (AMOUNT)
Empty
1M X 32 (4 MB)
2M X 32 (8 MB)
4M X 32 (16 MB)
8M X 32 (32 MB)
Empty
1M X 32 (4 MB)
2M X 32 (8 MB)
4M X 32 (16 MB)
8M X 32 (32 MB)
Empty
1M X 32 (4 MB)
2M X 32 (8 MB)
4M X 32 (16 MB)
8M X 32 (32 MB)
Empty
1M X 32 (4 MB)
2M X 32 (8 MB)
4M X 32 (16 MB)
8M X 32 (32 MB)
TOTAL SYSTEM
MEMORY
8 MB
16 MB
24 MB
40 MB
72 MB
16 MB
24 MB
32 MB
48 MB
80 MB
32 MB
40 MB
48 MB
64 MB
96 MB
64 MB
72 MB
80 MB
96 MB
128 MB
Note: SIMMs may be parity (x 36) or non-parity (x 32)
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EDO DRAM
Extended Data Out (or Hyper Page) DRAM is designed to improve the
DRAM read performance. EDO DRAM holds the memory data valid
until the next CAS# falling edge, unlike standard fast page mode DRAM
which tri-states the memory data when CAS# negates to precharge for
the next cycle. With EDO, the CAS# precharge overlaps the data valid
time, allowing CAS# to negate earlier while still satisfying the memory
data valid window time.
REAL TIME CLOCK BATTERY REPLACEMENT
The on-board battery may be replaced using a Crompton Eternacell type
T048AA9 lithium battery, or equivalent. This battery has a 1000 mAh
rating.
CPU UPGRADE
A Type 7 Zero Insertion Force (ZIF) socket provides users with a
performance upgrade path to the Pentium Overdrive Processors.
GRAPHICS MEMORY UPGRADE
The PX1 single board PC has 1 MB of Fast Page DRAM installed for
graphics. Two SOJ type sockets (IC4 & IC5 on the underside of the board)
provide for upgrade of the graphics DRAM. Two 256K x 16, 60 ns DRAMs
may be installed to provide a total of 2 MB of graphics DRAM. Note these
must be installed in pairs.
The DRAM must be of the “Dual CAS” type and not the “Dual Write” type.
Suitable types are:
Toshiba:
NEC:
Hitachi:
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TC514260BJ-60
µPD424260LE-60
HM514260CJ-6
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SOFTWARE DESCRIPTION
BIOS SETUP
This section details the BIOS CMOS Setup Utility. The parameters described
below are based on BIOS version 1.10; other BIOS versions may differ from
the description below as new features are added.
OVERVIEW OF THE SETUP MENU SCREENS
The Setup program initially displays the Main menu screen. In each screen
there are options for modifying the system configuration. Select a sub-menu
screen by pressing the up <↑> or down <↓> arrow keys, followed by <Enter>.
Within the menu use the up <↑> or down <↓> keys to select an item, then use
<PgUp> or <PgDn> to modify it. For certain items, pressing <Enter> will
bring up a subscreen. After you have selected an item, use the <PgUp> or
<PgDn> keys to modify the setting.
MAIN SCREEN
Shows the following menu:
Standard Setup
Advanced CMOS Setup
Advanced Chipset Setup
Power Management Setup
PCI / PnP Setup
Peripheral Setup
Auto Detect Hard Disk
Change User Password
Change Supervisor Password
Auto Configuration with Optimal Settings
Auto Configuration with Fail Safe Settings
Save Settings and Exit
Exit without Saving
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Their operation is as follows:
STANDARD SETUP
For setting up and modifying basic items such as floppy disk drives, hard
drives, and system time & date.
ADVANCED CMOS SETUP
For modifying the more advanced features of the PC (e.g. system bootup
options).
ADVANCED CHIPSET SETUP
For modifying hardware level options.
POWER MANAGEMENT SETUP
For specifying the “Green PC” features such as IDE and VGA timeouts.
PCI / PNP SETUP
For specifying Plug and Play options (e.g. IRQ assignments).
PERIPHERAL SETUP
For specifying the system peripheral options such as serial and parallel
port modes.
AUTO DETECT HARD DISK
Automatically determines the parameters of any IDE devices connected,
and sets up the parameters for “USER DEFINED” drives.
CHANGE USER PASSWORD
Allows the password for the user level options to be set or changed. This
option cannot be changed unless a supervisor password has been set.
CHANGE SUPERVISOR PASSWORD
Allows the password for the supervisor level options to be changed.
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AUTO CONFIGURATION WITH OPTIMAL SETTINGS
Resets the CMOS setup options to a high performance configuration. The
optimal default settings are best case values and should optimise the
system performance. If CMOS RAM is corrupted, the optimal settings
are loaded automatically.
AUTO CONFIGURATION WITH FAIL SAFE SETTINGS
Resets the CMOS setup options to a lower performance but guaranteed
working configuration. The fail safe settings provide far from optimal
system performance, but are the most stable settings. Use these settings
as an diagnostics aid if the system is performing erratically.
SAVE SETTINGS AND EXIT
When selected, this allows you to save the change to CMOS and exit the
Setup program. You can also press the <F10> key anywhere in the Setup
program to do this.
EXIT WITHOUT SAVING
When selected, this allows you to exit the Setup program without saving
any changes. This means that any changes made while in the Setup
program will be discarded and NOT SAVED. Pressing the <Esc> key in
any of the four main screens will do this.
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OVERVIEW OF THE SETUP KEYS
SETUP KEY
<F1>
<Esc>
<PgUp>
<PgDn>
<↑>
<↓>
<←> <→>
<F5>
<F6>
<F10>
DESCRIPTION
Pressing the <F1> key brings up a help screen for the currently
selected item.
Pressing the <Esc> key takes you back to the previous screen.
Pressing it in the Main, Advanced, Security, or Exit screen allows you
to Exit Discarding Changes (see later in this chapter).
Pressing either key moves the selection of the current item up or down
the available options.
Pressing the up <↑> key changes the selection to the previous item or
option.
Pressing the down <↓> key changes the selection the to the next item
or option.
Pressing the left <←> or right <→> keys in the Main, Advanced,
Security, or Exit menu screens changes the menu screen. Pressing
either key in a subscreen does nothing.
Pressing the <F5> key allows you to Load Setup Defaults (see later in
this chapter).
Pressing the <F6> key allows you to Discard Changes (see later in this
chapter).
Pressing the <F10> key allows you to Exit Saving Changes (see later
in this chapter).
STANDARD SETUP
This section describes the Setup options found on the standard setup screen.
SYSTEM DATE
When selected, this allows you to set the current date by specifying a
date, month and year.
SYSTEM TIME
When selected, this allows you to set the current time by entering values
for hours, minutes and seconds..
FLOPPY A: TYPE
When selected, this allows you to cycle through the available options to
specify the physical size and capacity of the diskette drive. The options
are Disabled; 360 KB, 5.25-inch; 1.2 MB, 5.25-inch; 720 KB, 3.5-inch;
1.44/1.25 MB, 3.5-inch; 2.88 MB, 3.5-inch. The default is 1.44 MB, 3.5inch.
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FLOPPY B: TYPE
When selected, this allows you to cycle through the available options to
specify the physical size and capacity of the diskette drive. The options
are Disabled, 360 KB, 5.25-inch; 1.2 MB, 5.25-inch; 720 KB, 3.5-inch;
1.44/1.25 MB, 3.5-inch; 2.88 MB, 3.5-inch. The default is Disabled.
PRIMARY IDE MASTER
This reports if a primary master IDE hard disk is connected to the system
and allows for the configuration of drive parameters.
When selected, this allows the manual configuration of the hard drive or
have the system auto configure it. The options are Auto Configured, User
Definable and Disabled. There are also options for IDE CD-ROM and
46 predefined hard drive types. If you select User Definable then the
Number of Cylinders, Number of Heads, and Number of Sectors can each
be modified. The default for this is “Auto”.
PRIMARY IDE SLAVE
This reports if a primary slave IDE hard disk is connected to the system.
It is configured exactly as described under Primary IDE Master above.
The default is “Not Installed”.
SECONDARY IDE MASTER
This reports if a secondary master IDE hard disk is connected to the
system. It is configured exactly as described under Primary IDE Master
above. The default is “Not Installed”.
SECONDARY IDE SLAVE
This reports if a secondary slave IDE hard disk is connected to the
system. It is configured exactly as described under Primary IDE Master
above. The default is “Not Installed”.
NUMBER OF CYLINDERS
If Hard Disk Type is set to User Definable, you must type the correct
number of cylinders for your hard disk. If Hard Disk Type is set to Auto
Configured, this reports the number of cylinders for your hard disk and
cannot be modified.
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NUMBER OF HEADS
If Hard Disk Type is set to User Definable, you must type the correct
number of heads for your hard disk. If Hard Disk Type is set to Auto
Configured, this reports the number of heads for your hard disk and
cannot be modified.
NUMBER OF SECTORS
If Hard Disk Type is set to User Definable, you must type the correct
number of sectors for your hard disk. If Hard Disk Type is set to Auto
Configured, this reports the number of sectors for your hard disk and
cannot be modified.
BOOT SECTOR VIRUS DETECTION
If set to “Enabled” this will flag a warning when the boot sector of a hard
disk drive is changed. The options are “Enabled” and “Disabled”. The
default is “Disabled”.
ADVANCED CMOS SETUP
QUICK BOOT
Set this option to “Enabled “ to instruct the BIOS to boot quickly.
If set to “Enabled” the BIOS does not test memory above 1 MB and the
BIOS does not wait up to 40 seconds for a READY signal from the hard
drive. If the READY signal is not received immediately from the IDE
drive, it is not configured (as if it was absent). The default is “Disabled”.
BOOTUP SEQUENCE
This option specifies the sequence of the boot drives (floppy drive A:,
hard drive C:, or a CD-ROM drive). The settings are:
C: A: CD-ROM
A: C: CD-ROM
CD-ROM C: A:
The default is A: C: CD-ROM.
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BOOT CPU SPEED
Allows the system’s boot speed to be set. The options are “Low” and
“High”. The optimal setting is “High”, the fail-safe is “Low”. If High is
selected, boot-up occurs at full speed. If Low is selected, the board
operates at a slower speed (approximately equivalent to 25 MHz PC-AT).
Default is low.
BOOT UP NUM LOCK
Allows you to set the start up state of “Num Lock” on your keyboard. The
options are “On” and “Off”. The default is On.
FLOPPY DRIVE SEEK
Set this option to specify floppy drive A: will perform a seek operation on
system boot. are “Enabled” and “Disabled”. The default setting is
enabled.
MOUSE SUPPORT
When this option is enabled the BIOS will support a PS/2 style mouse.
The options are “Enabled” and “Disabled”. The default setting is
enabled.
SYSTEM KEYBOARD
This option specifies that a keyboard is attached to the computer. The
settings are Present or Absent. The Optimal and Fail-Safe default
settings are Present.
PRIMARY DISPLAY
This option specifies the type of display monitor and adapter in the
computer. The settings are Mono, CGA40, CGA80, EGA/VGA, or
Absent. The Optimal and Fail-Safe default settings are VGA/EGA.
PASSWORD CHECK
This option enables password checking every time the computer is
powered on or every time Setup is executed. If Always is chosen, a user
password prompt appears every time the computer is turned on. If Setup
is chosen, the password prompt appears if Setup is executed.
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OS/2 COMPATIBLE MODE
Set this option to Enabled to permit AMIBIOS to run with IBM OS/2.
The settings are Enabled or Disabled. The default settings are Disabled.
WAIT FOR F1 IF ERROR
AMIBIOS POST error messages are followed by:
Press <F1> to continue
If this option is set to Disabled, AMIBIOS does not wait for you to press
the <F1> key after an error message. The settings are Disabled or
Enabled. The Optimal and Fail-Safe default settings are Enabled.
HIT DEL MESSAGE DISPLAY
Set this option to Disabled to prevent
Hit <DEL> if you want to run Setup
from appearing on the first AMIBIOS screen when the computer boots.
The settings are Disabled or Enabled. The Optimal and Fail-Safe default
settings are Enabled.
INTERNAL CACHE
This option specifies the caching algorithm used for L1 internal cache
memory. The settings are :
SETTING
Disabled
WriteBack
(default)
WriteThru
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DESCRIPTION
Neither L1 internal cache memory on the CPU or L2 secondary
cache memory is disabled
Use the write-back caching algorithm
Use the write through caching algorithm
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EXTERNAL CACHE
This option specifies the caching algorithm used for L2 secondary
(external) cache memory. The settings are :
SETTING
Disabled
WriteBack
WriteThru
DESCRIPTION
L2 cache is disabled
L2 cache is write back. (Deafult)
L2 cache is write through
SYSTEM BIOS SHADOW CACHEABLE
When this option is set to Enabled, the contents of the F0000h system
memory segment can be read from or written to L2 secondary cache
memory. The contents of the F0000h memory segment are always copied
from the BIOS ROM to system RAM for faster execution.
The settings are Enabled or Disabled. The Optimal default setting is
Enabled. The Fail-Safe default is Disabled. Default is Enabled.
C000, 16K Shadow
C400, 16K Shadow
C800, 16K Shadow
CC00, 16K Shadow
D000, 16K Shadow
D400, 16K Shadow
D800, 16K Shadow
DC00, 16K Shadow
These options control the location of the contents of the 16KB blocks of
ROM beginning at the specified memory location. If no adapter ROM is
using the named ROM area, this area is made available to the local bus.
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The settings are :
SETTING
Enabled
Cache
Disabled
DESCRIPTION
The contents of C0000h - C3FFFh are written to the same
address in system memory (RAM) for faster execution.
The contents of the named ROM area are written to the same
address in system memory (RAM) for faster execution, if an
adapter ROM will be using the named ROM area. Also, the
contents of the RAM area can be read from and written to cache
memory.
The video ROM is not copied to RAM. The contents of the video
ROM cannot be read from or written to cache memory.
The default setting is Cache for C000 and C400; disabled for the
remainder.
In the AMIBIOS for the Intel Triton chipset, the E000h page is used as
ROM during POST, but shadowing is disabled and the ROM CS# signal
is disabled to make the E000h page available on the local bus.
ADVANCED CHIPSET SETUP
MEMORY HOLE
Use this option to specify an area in memory that cannot be addressed on
the ISA bus. The settings are Disabled, 512-640K or 15-16MB. The
default setting is Disabled.
INSTALLED MEMORY
Use this option to specify the total amount of memory installed in the
system when using the memory hole. This option should ONLY be used
with OS/2. The options are Disabled, 32MB, and 64MB. The optimal
and fail safe defaults are Disabled.
DRAM SPEED
Specify the RAS access speed of the SIMMs installed in the motherboard
as system memory. The settings are 60nS or 70nS. The default is 70nS.
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Caution
If you have installed SIMMs with different speeds in the motherboard,
select the speed of the slowest SIMM. You must always use SIMMs
that have the same speed within each memory bank.
IRQ12/M MOUSE FUNCTION
Set this option to Enabled to specify that IRQ12 will be used for the
mouse. The settings are Disabled or Enabled. The Optimal and FailSafe default settings are Enabled.
8-BIT I/O RECOVERY TIME (SYSCLK)
This option specifies the length of the delay (in units of SYSCLKs)
inserted between consecutive 8-bit I/O operations. The settings are
1,2,3,4,5,6,7, or 8. the Optimal and Fail-Safe default settings are 8.
16-BIT I/O RECOVERY TIME (SYSCLK)
This option specifies the length of the delay (in SYSCLKs) inserted
between consecutive 16-bit I/O operations. The settings are 1,2,3,4,5,6,7
or 8. The Optimal and Fail-Safe default settings are 4.
POWER MANAGEMENT SETUP
POWER MANAGEMENT / APM
Set this option to Enabled to enable the power management and APM
(advanced Power Management) features.
The settings are Enabled, Disabled or Inst-On. The default settings are
Disabled.
INSTANT ON SUPPORT
If this option is set in Power Management / APM it allows the computer
to go to full power on mode when leaving a power-conserving state.
AMIBIOS uses the RTC Alarm function to wake the computer at a prespecified time. The settings are 1 to 14 minutes, or Disabled. The
default settings are Disabled.
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GREEN PC MONITOR POWER STATE
This option specifies the power management state that the Green PCcompliant video monitor enters after the specified period of display
inactivity has expired. The settings are, Off, Standby, or Suspend. The
default settings are Standby.
VIDEO POWER DOWN MODE
This option specifies the power management state that the video
subsystem enters after the specified period of display inactivity has
expired. The settings are Disabled, Standby or Suspend. The default
settings are Disabled.
HARD DISK POWER DOWN MODE
This option specifies the power management state that the hard disk
drive enters after the specified period of display inactivity has expired.
The settings are Disabled, Standby, or Suspend. The default settings are
Disabled.
HARD DISK TIMEOUT (MIN)
This option specifies the length of a period of hard disk inactivity. When
this period expires, the hard disk drive enters the power-conserving mode
specified in the Hard Disk Power Down Mode option described above.
The settings are Disabled, 1 Min (minutes), and all one minute intervals
up to and including 15 Min. The default settings are Disabled.
STANDBY TIMEOUT
This option specifies the length of the period of system inactivity when
the computer is in Full-On mode before the computer is placed in
Standby mode. In Standby mode, some power use is curtailed. The
settings are Disabled, 1 Min, 2 Min and all one minute intervals up to
and including 15 Min. The default settings are Disabled.
SUSPEND TIMEOUT
This option specifies the length of the period of system inactivity when
the computer is already in Standby mode before the computer is placed in
Suspend mode. In Suspend mode, nearly all power use is curtailed. The
settings are Disabled, 1 Min, 2 Min, and all one minute intervals up to
and including 15 Min. The default settings are Disabled.
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SLOW CLOCK RATIO
This option specifies the speed at which the system clock runs in power
saving modes. The settings are expressed as a ratio between the normal
clock speed and the power down clock speed. The settings are 1:1, 1:2
(half as fast as normal), 1:4 ((the normal clock speed), 1:8, 1:16, 1:32,
1:64, or 1:128. The default setting is 1:8.
DISPLAY ACTIVITY
This option specifies if AMIBIOS is to monitor activity on the display
monitor for power conservation purposes. When this option is set to
Monitor and there is no display activity for the length of time specified in
the value in the Full-On to Standby Timeout (Min) option, the computer
enters a power saving state. The settings are Monitor or Ignore. The
default settings are Ignore.
IRQ 3, 4, 5, 7, 9, 10, 11, 12, 13, 14, 15
These options enable event monitoring. When the computer is in a
power saving mode, activity on the named interrupt request line is
monitored by AMIBIOS. When any activity occurs, the computer enters
Full On mode.
Each of these options can be set to Monitor or Ignore. The settings are:
IRQ 3
IRQ 4
IRQ 5
IRQ 7
IRQ 9
IRQ 10
IRQ 11
IRQ 12
IRQ 13
IRQ 14
IRQ 15
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OPTIMAL
Monitor
Monitor
Ignore
Monitor
Ignore
Ignore
Ignore
Monitor
Ignore
Monitor
Monitor
FAIL-SAFE
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
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PCI / PNP SETUP
PLUG AND PLAY AWARE OS
Set this option to Yes if the operating system installed in the computer is
Plug and Play-aware. AMIBIOS only detects and enables PnP ISA
adapter cards that are required for system boot. The Windows 95
operating system detects and enables all other PnP-aware adapter cards.
Windows 95 is PnP-aware. Set this option to No if the operating system
(such as DOS, OS/2, Windows 3.x) does not use PnP. You must set this
option correctly or PnP-aware adapter cards installed in your computer
will not be configured properly. The settings are No or Yes. The
Optimal and Fail-Safe default settings are No.
PCI BURST MODE
Set this option to Enabled to enable PCI burst mode. The settings are
Disabled or Enabled. The Optimal default setting is Enabled. The FailSafe default setting is Disabled.
PCI CONCURRENCY
Set this option to “Enable” to allow PCI peer to peer cache concurrency.
Options are Enabled or Disabled. The default is Enabled.
PCI LATENCY TIMER (IN PCI CLOCKS)
This option sets latency of all PCI devices on the PCI bus. The settings
are in units equal to PCI clocks. The settings are 32, 64, 96, 128, 160,
192, 224, or 248. The Optimal and Fail-Safe default settings are 64.
ALLOCATE IRQ TO PCI VGA
Use this option to specify whether the PCI device initialisation code
within the BIOS should allocate an IRQ to the PCI VGA controller.
Setting this option to YES reduces the available IRQ lines to the rest of
the system by 1. The options are Yes or No. The optimal and fail safe
defaults are No.
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PCI VGA PALETTE SNOOP
This option must be set to Enabled if any ISA adapter card installed in
the computer requires VGA palette snooping. The settings are Disabled
or Enabled. The Optimal and Fail-Safe default settings are Disabled.
PCI IDE BUS/MASTER
Set this option to Enabled to specify that the IDE controller on the PCI
local bus has bus mastering capability. The settings are Disabled or
Enabled. The Optimal and Fail-Safe default settings are Disabled.
OFFBOARD PCI IDE CARD
This option specifies if an offboard PCI IDE controller adapter card is
used in the computer. You must also specify the PCI expansion slot on
the motherboard where the offboard PCI IDE controller card is installed.
If an offboard PCI IDE controller is used, the on-board IDE controller on
the motherboard is automatically disabled. The settings are Disabled,
Auto, Slot1, Slot2, Slot3, or Slot 4.
If Auto is selected, AMIBIOS automatically determines the correct
setting for this option. The Optimal and Fail-Safe default settings are
Auto.
In the AMIBIOS for the Intel Triton chipset, this option forces IRQ 14
and 15 to a PCI slot on the PCI local bus. This is necessary to support
non-compliant PCI IDE adapter cards.
OFFBOARD PCI IDE PRIMARY IRQ
This option specifies the PCI interrupt used by the primary IDE channel
on the offboard PCI IDE controller. The settings are Disabled, INTA,
INTB, INTC, INTD or Hardwired. The Optimal and Fail-Safe default
settings are Disabled.
OFFBOARD PCI IDE SECONDARY IRQ
This option specifies the PCI interrupt used by the secondary IDE
channel on the offboard PCI IDE controller. The settings are Disabled,
INTA, INTB, INTC, INTD or Hardwired. The Optimal and Fail-Safe
default settings are Disabled.
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DMA CHANNELS 0, 1, 3, 5, 6, 7
These options specify the bus to which the DMA channel is allocated.
These options determine if AMIBIOS should remove a DMA channel
from the available pool passed to BIOS configurable devices. The
available pool is determined by reading the ESCD NVRAM. If more
DMA channels must be removed from the pool, the end user can use
these PCI/PnP Setup options to remove the channel by assigning the
option to the ISA/EISA setting. Onboard I/O is configurable by
AMIBIOS. The DMA channels used by onboard I/O are configured as
PCI/PnP.
The default settings are:
OPTIMAL
Channel 0
PnP
Channel 1
PnP
Channel 3
ISA/EISA
Channel 5
PnP
Channel 6
PnP
Channel 7
PnP
FAILSAFE
PnP
PnP
ISA/EISA
PnP
PnP
PnP
IRQ 3, 4, 5, 7, 9, 10, 11, 14, 15
These options specify the bus that the named interrupt request lines
(IRQs) are used on. These options allow you to specify IRQs for use by
legacy ISA adapter cards.
These options determine if AMIBIOS should remove an IRQ from the
pool of available IRQs passed to BIOS configurable devices. The
available IRQ pool is determined by reading the ESCD NVRAM. If
more IRQs must be removed from the pool, the end user can use these
PCI/PnP Setup options to remove the IRQ by assigning the option to the
ISA/EISA setting. Onboard I/O is configurable by AMIBIOS. The IRQs
used by onboard I/O are configured as PCI/PnP.
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The optimal and fail-safe settings are:
IRQ 3
IRQ 4
IRQ 5
IRQ 7
IRQ 9
IRQ 10
IRQ 11
IRQ 14
IRQ 15
OPTIMAL
ISA/EISA
ISA/EISA
PnP
ISA/EISA
PnP
PnP
PnP
PnP
PnP
FAILSAFE
ISA/EISA
ISA/EISA
PnP
ISA/EISA
PnP
PnP
PnP
PnP
PnP
RESERVED MEMORY SIZE
This option specifies the size of the memory area reserved for legacy ISA
adapter cards.
The settings are Disabled, 16K, 32K, or 64K. The Optimal and Fail-Safe
default settings are Disabled.
RESERVED MEMORY ADDRESS
This option specifies the beginning address (in hex) of the reserved
memory area. The specified ROM memory area is reserved for use by
legacy ISA adapter cards.
The settings are C0000, C4000, C8000, CC000, D0000, D4000, D8000,
DC000. The Optimal and Fail-Safe default settings are C8000.
PERIPHERAL SETUP
Peripheral Setup options are displayed by choosing the Peripheral Setup
icon from the WINBIOS Setup main menu. All Peripheral Setup options
are described in this section.
ONBOARD PCI IDE
This option specifies the onboard IDE controller channels that will be
used. The settings are Primary, Secondary, Both or Disabled. The
Optimal and Fail-Safe default settings are Both.
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ONBOARD FDC
This option enables the floppy drive controller on the PC board. The
settings are Auto, Enabled or Disabled. The default setting is Auto.
ONBOARD SERIAL PORT1
This option enables serial port 1 on the board and specifies the based I/O
port address for serial port 1.
The settings are Auto, 3F8h, 3E8h, 2F8h, 2E8h, or Disabled.
default setting is Auto.
The
ONBOARD SERIAL PORT2
This option enables serial port 2 on the board and specifies the base I/O
port address for serial port 2.
The settings are Auto, 3F8h, 3E8h, 2F8h, 2E8h, or Disabled.
default setting is Auto.
The
ONBOARD PARALLEL PORT
This option enables the parallel port on the board and specifies the
parallel port based I/O port address. The settings are Auto, 378h, 278h,
3BCh, or Disabled. The default setting is Auto.
PARALLEL PORT MODE
This option specifies the parallel port mode. ECP and EPP are both bidirectional data transfer schemes that adhere to the IEEE P1284
specifications. The settings are :
SETTING
Normal
Bi-Dir
EPP
ECP
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DESCRIPTION
The normal parallel port mode is used. This is the default
setting.
Use this setting to support bi-directional transfers on the parallel
port.
The parallel port can be used with devices that adhere to the
Enhanced Parallel Port (EPP) specification. EPP uses the
existing parallel port signals to provide asymmetric bi-directional
data transfer driven by the host device.
The parallel port can be used with devices that adhere to the
Extended Capabilities Port (ECP) specification. ECP uses the
DMA protocol to achieve transfer rates of approximately 2.5Mbs.
ECP provides symmetric bi-directional communications.
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PARALLEL PORT IRQ
Selects which IRQ is assigned to the parallel port. Available options are
Auto, 5, or 7. The default is Auto.
PARALLEL PORT DMA
This option is only available if the setting for the Parallel Port Mode
option is ECP.
The settings are Auto, None, DMA CH 0, DMA CH 1, DMA CH 2, or
DMA CH 3. (CH = channel). The default setting is Disabled.
HARDWARE IO PORT BASE ADDRESS
This specifies the base address of the PX1 configuration and control
registers. The permissible options are:
100 hex, 300 hex, 400 hex, 500 hex, 600 hex, 700 hex, 800 hex, 900 hex,
A00 hex, B00 hex, C00 hex, D00 hex, E00 hex, and F00 hex. Note the
absence of 200 hex in the list. The default is 100 hex.
SERIAL PORT 2 MODE
Specifies whether the second serial port will be used as RS232 or RS485.
Options are RS232 and RS485. The optimal and fail safe defaults are
RS232.
RS485 DUPLEX MODE
Specifies whether the second serial port will be used as full or half duplex
when running in RS485 mode. This option is only available when the
options ‘Serial Port 2 Mode’ is set to RS485. The options are FULL or
HALF. The Optimal and Fail Safe defaults are FULL.
FEATURE CONNECTOR
Specifies whether the S3 feature connector is enabled or disabled. The
options are Enabled and Disabled. The Optimal and Fail Safe defaults
are Disabled.
If set to enabled and a device is not connected to the feature connector the
display will blank when the feature connector is initialised.
When the feature connector is enabled the S3 VGA Controller will only
use 1MB of video memory limiting the resolutions available.
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BIOS EXTENSIONS
Specifies whether the PX1 BIOS extensions are available. See the
section “BIOS Extensions Software Interface” for details of the functions
available. The options are Enabled and Disabled. The optimal and fail
safe defaults are Disabled.
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DISKONCHIP 2000 SUPPORT
The PX-1 supports the use of M-Systems DiskOnChip 2000 Flash Module,
the notes below detail the use of the device, please consult the user manual
if any more detail is required.
1. PREFACE
This note describes how to integrate the DiskOnChip 2000 with PC
compatible systems. The DiskOnChip 2000 is a single chip FlashDisk
designed to plug into a standard 32-pin EEPROM socket. The DiskOnChip
2000 should be mapped into an 8KByte window in the BIOS expansion
address space of the PC, which is usually located between address 0C0000H
to 0EFFFFH.
The DiskOnChip 2000 contains a built-in copy of the M-Systems industrystandard TrueFFS software, which makes the DiskOnChip operate as a
standard disk drive. The DiskOnChip 2000 can contain the operating
system in it to allow systems to boot without a hard disk. The DiskOnChip
2000 can also be configured as the boot device in systems with a hard disk
(see below “Configuring the DiskOnChip 2000 as the first drive”).
The DiskOnChip is a self-contained device. The installation of the
DiskOnChip does not require any software installation. The design of the
DiskOnChip allows for full upward and downward compatibility. While
available today in capacities of 2 to 72MBytes, future DiskOnChip devices
with higher densities, will be fully compatible with standard DiskOnChip
sockets. The basic design of the DiskOnChip actually supports an unlimited
capacity.
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2. OPERATING THE DISKONCHIP
2.1 INSTALLING THE DISKONCHIP 2000
When installing or removing the DiskOnChip, be sure to first touch a
grounded surface to discharge any static electricity from your body. Use the
following procedure to install the DiskOnChip:
Align pin 1 on the DiskOnChip with pin 1 of Flash socket.
Push the DiskOnChip into the socket carefully until it is fully seated.
Check to make sure the DiskOnChip is installed securely, and there are no
bent pins.
Caution: The DiskOnChip may be permanently damaged if installed
incorrectly!
To install the DiskOnChip as drive C on a system without a hard disk, set
the CMOS setup of drive C to “not installed” (indicating that no physical
magnetic disk is installed), and reboot the computer. The DiskOnChip 2000
will install as drive C. The DiskOnChip needs to be formatted with the
System files in order for it to be a bootable drive. See “Configuring the
DiskOnChip as the BOOT device” below.
To install the DiskOnChip as drive D on a system with a hard disk, just
reboot the system, and the DiskOnChip will install as drive D.
To install the DiskOnChip as Drive C on a system with a hard disk, see
below “Configuring the DiskOnChip as the first drive”.
2.2 CONFIGURING THE DISKONCHIP 2000 AS THE BOOT
DEVICE
In order to configure the DiskOnChip as the boot device, the operating
system files need to be copied into it. Copying the operating system files
into DiskOnChip Should be done like in any other hard disk. The following
is an example of a typical initialization process:
Set the DiskOnChip as a regular drive in your system (not a boot drive).
Install a bootable floppy diskette in drive A and boot the system.
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SOFTWARE DESCRIPTION
At the DOS prompt, type SYS C: to transfer the DOS system files to the
DiskOnChip (assuming the DiskOnChip is installed as drive C).
Copy any files needed into the DiskOnChip.
Remove the floppy diskette and reboot the system. The system will boot
from the DiskOnChip, and will allow you to run and access any files that
have been copied into the DiskOnChip.
2.3 CONFIGURING THE DISKONCHIP 2000 AS THE FIRST DRIVE
The DiskOnChip can be configured to be installed as the last drive
(default), or as the first drive in the system. When configured as the last
drive, the DiskOnChip is installed as disk D if there is another hard drive
installed, and as drive C if no other hard disk is installed. When configured
as the first drive, the DiskOnChip is always installed as drive C. The
DiskOnChip is shipped from the factory, configured to install as the last
drive. To configure the DiskOnChip to be installed as the first drive,
proceed as follows:
Boot the system and make sure the DiskOnChip is installed correctly as
drive D
At the DOS prompt type: DUPDATE D: /FIRST /S:DOC2000.EXB
After re-booting the system, the DiskOnChip will appear as drive C:
Blue Chip Technology Ltd.
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PX1 USER MANUAL
SOFTWARE DESCRIPTION
BIOS EXTENSIONS SOFTWARE INTERFACE
The BIOS extensions provide the programmer with access to some of the
additional functionality provided through the hardware on the PX-1 board.
This is achieved through the use of a software interrupt (int 50h) and a
description of the functions available is described below.
ENABLING BIOS EXTENSIONS
Boot the PX-1 card and enter the BIOS set-up by pressing the DEL key.
Select ‘Peripheral Set-up’
Set the ‘BIOS Extensions’ to enabled.
Save the settings and exit set-up to let the system reboot.
ACCESSING INT 50H FUNCTIONS
Most high level languages allow access to software interrupts through a
particular function call. The user loads a particular function code into the
AH register followed by a specific set of parameters in the other registers
before executing the interrupt.
For example, in Quick Basic
' Read E2 Data via interrupt 50 call
$include:'QB.BI'
DIM INARY%(7),OUTARY%(7)
CONST AX=0,BX=1,CX=2,DX=3,BP=4,SI=5,DI=6,FL=7
INARY%(AX) = &H0400
' Read e2 data
INARY%(BX) = &H31
' address &H31
CALL INT86OLD(&H50,INARY%(),OUTARY%())' Call the APEX
' service
PRINT "E2 ADDRESS &H31 CONTAINS: ";OUTARY%(DX)
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SOFTWARE DESCRIPTION
PAGE 53
and similarly in C :#include <stdio.h>
#include <dos.h>
#define APEX 0x50
void main(void)
{
union REGS regs;
regs.x.ax = 0x0400;
/* read e2 */
regs.x.bx = 0x31;
/* address 0x31 */
int86(APEX, &regs, &regs);
printf("e2 Address 0x31 contains %x\n",regs.x.dx);
}
INT 50H FUNCTION DEFINITIONS
This covers version 1.3 of the BIOS extensions. Other versions may have
additional functions available.
AH = 00H EXTENDED WATCHDOG ENABLE
The SMC932 Ultra IO controller provided a programmable watchdog
that can be used to monitor the system health and reset the system should
the application stop working and not refresh the watchdog.
Input parameters:
AH = 00h
DL = Watchdog period
00h = disabled,
01h = 1min,
FFh = 255mins
DH = Extended functions
Bit 0 route time out to reset, Set to 1 the system will
reset when the watchdog times out. Set to 0 the
watchdog will need to be polled to detect a timeout.
Return values:
Returns with the carry flag clear.
AH = 01H EXTENDED WATCHDOG RESET
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SOFTWARE DESCRIPTION
PX1 USER MANUAL
Issuing this command will reset the watchdog within the SMC932 Ultra
IO controller to start timing down again.
Input Parameters:
AH = 01h
Return values:
None
AH = 02H EXTENDED WATCHDOG STATUS
This will return the status of the SMC932 Ultra IO watchdog for systems
that are polling the status.
Input parameters:
AH = 02h
Return values:
AL = Watchdog status
00h = Watchdog OK
FFh = Watchdog time out
Carry flag mirrors the status of the SMC932 time out bit
AH = 03H RESERVED
This function is reserved for future use.
AH = 04H RESERVED
This function is reserved for future use.
AH = 05H WATCHDOG ENABLE
This function enables the simple 500ms watchdog.
Input parameters:
AH = 05h
Return values:
Returns with the carry flag clear.
AH = 06H WATCHDOG TICK
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SOFTWARE DESCRIPTION
PAGE 55
This function resets the count on the 500ms watchdog.
Input parameters:
AH =06h
Return values:
Returns with the carry flag clear
AH = 07H GET HARDWARE IO BASE ADDRESS
This function returns the value of the locatable hardware IO base address.
Input parameters:
AH = 07h
Return values:
AX = Hardware IO Base address.
AH = 08H GET BIOS EXTENSION VERSION
This function returns the BIOS extension version number.
Input parameters:
AH = 08h
Return values:
AH = Major version number
AL = Minor revision number
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APPENDICES
PX1 USER MANUAL
APPENDICES
ADDRESS MAPS
MEMORY MAP
ADDRESS
RANGE
(DECIMAL)
1024K - 131072K
896K - 1023K
ADDRESS
RANGE
(HEX)
100000 - 8000000
E0000 - FFFFF
127M
128K
880K - 895K
848K - 879K
800K - 847K
DC000 - DFFFF
D4000 - DBFFF
C8000 - D3FFF
16K
32K
48K
640K - 799K
A0000 - C7FFF
160K
639K
9FC00 - 9FFFF
1K
512K - 638K
0K - 511K
80000 - 9FBFF
00000 - 7FFFF
127K
512K
SIZE
DESCRIPTION
Extended Memory
AMI System BIOS
(not available for UMB)
Solid State Disk Pages
BIOS Extensions
Available HI DOS memory
(open to ISA and PCI bus)
On-board video memory and
BIOS
Extended BIOS Data
(moveable by QEMM, 386MAX)
Extended conventional
Conventional
I/O MAP
The following table lists the I/O addresses used by single board PC devices.
Some of these devices (e.g. graphics) may not be present in all
configurations. Some devices (serial ports, parallel ports etc.) may be
configured for various addresses or disabled. These I/O locations are listed
in the Variable Resources column.
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APPENDICES
ADDRESS
(HEX)
0000 - 000F
0020 - 0021
002E - 002F
0040 - 0043
0060
0061
0064
0070, bit 7
0070, bits 6:0
0071
0080 - 008F
00A0 - 00A1
00B2 - 00B3
SIZE
Bytes
16
2
2
4
1
1
1
1 bit
7 bits
1
16
2
2
00C0 - 00DE
00F0
0100 - 0107
0170 - 0177
01F0 - 01F7
0200 - 0207
0278 - 027B
02E8 - 02EF
02F8 - 02FF
0376
0377
0378 - 037F
03B0 - 03BB
03BC - 03BF
03C0 - 03DF
03E8 - 03EF
03F0 - 03F5
03F6
03F7 (Write)
03F7, bit 7
03F7, bits 6:0
03F8 - 03FF
LPT + 400h
31
1
8
8
8
8
4
8
8
1
1
8
4
4
16
8
6
1
1
1 bit
7 bits
8
3
04D0 - 04D1
0CF8 - 0CFC*
0CF9
0CFC - 0CFF
FFA0 - FFA7
FFA8 - FFAF
FF00-FF07
2
4
1
4
8
8
8
FIXED RESOURCES
PAGE 57
VARIABLE
RESOURCES
PIIX - DMA 1
PIIX - Interrupt Controller 1
Ultra I/O configuration registers
PIIX - Timer 1
Keyboard Controller Data Byte
PIIX - NMI, speaker control
Kbd Controller, CMD/STAT Byte
PIIX - Enable NMI
87C307PIIX RTC, Address
87C307PIIX RTC, Data
PIIX - DMA Page Register
PIIX - Interrupt Controller 2
PIIX - APM Control / Status
Interrupt Controller 2
PIIX - DMA 2
Reset Numeric Error
Reserved for Board Confign.
Secondary IDE Channel
Primary IDE Channel
Gameport Joystick
Parallel Port 2
Serial Port 4
Serial Port 2
Sec IDE Chan Cmd Port
Sec IDE Chan Stat Port
Parallel Port 1
S3 Trio64V
Parallel Port 3
S3 Trio64V
Serial Port 3
Floppy Channel 1
Pri IDE Chan Cmnd Port
Floppy Chan 1 Cmd
Floppy Disk Chg Chan 1
Pri IDE Chan Status Port
Serial Port 1
ECP regs, LPT base +
400h
Edge/Level INTR Control Reg.
PCI Config Address Reg.
Turbo & Reset control Reg.
PCI Config Data Reg
1ary Bus MasterIDE regs
2ary Bus Master IDE regs
IDE Bus Master Reg.
*only accessible by DWORD accesses.
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PX1 USER MANUAL
APPENDICES
PCI CONFIGURATION SPACE MAP
The Triton chipset uses Configuration Mechanism 1 to access the PCI
configuration space. The PCI Configuration Address register is a 32-bit I/O
register located at 0CF8h, the PCI Configuration Data register is a 32-bit
I/O register located at 0CFCh. The PCI Configuration Address register is
only accessible by a DWORD access, the PCI Configuration Data register is
accessible by DWORD, WORD or BYTE accesses.
ACCESS TO I/O CONFIGURATION SPACE USING
MECHANISM #1
1. Using a DWORD write command, output the required I/O
configuration address to I/O port CF8H
2. Using a DWORD read or write command, read or write data from the
I/O port CFCH
NOTE: Any address output to CF8H is always on a 4 byte (DWORD)
boundary. You can read or write any BYTE, WORD or DWORD in the
four byte range by using the correct offset as follows:
DWORD @ CFCh
WORD @ CFCh or CFEh
BYTE @ CFCh, CFDh, CFEh or CFFh
CONFIGURATION ADDRESS REGISTER BIT DEFINITION
BIT
31
30 - 24
23 -16
15 - 11
10 - 8
7-2
1
0
FUNCTION / SETTING
1
RESERVED
BUS NUMBER
DEVICE NUMBER
FUNCTION NUMBER
REGISTER NUMBER
0
0
CONFIG SPACE ENABLE FLAG (Bit 31): Always 1 to indicate I/O
access is to configuration space.
RESERVED (Bits 30-24): Always 00h
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APPENDICES
BUS NUMBER (Bits 23-16): Always 00h unless a bridge card is installed
in a PCI slot
DEVICE NUMBER (Bits 15-11): Used to indicate a specific PCI device.
The Triton TSC has a predefined device number of 00000h. The PIIX
and four PCI slots also have specific device numbers, that device number
is determined by which PCI Address/Data line is connected to the
device’s ID SEL pin. Table E-1 details the specific mapping information.
FUNCTION NUMBER (Bits 10-8): Used to indicate a specific function
in multifunction PCI devices. The PIIX is the only multi-function device
on PX1 located on the single board PC. Use 00h for the basic PIIX device
and 01h for the PCI IDE BUS MASTER FUNCTION. For a multifunction PCI add-in card, refer to the card’s documentation to determine
the allowable function numbers.
REGISTER NUMBER (Bits 7-2): Defines one of 64 DWORD locations
for a specific PCI device.
Note that Bits 1 and 0 must always be 0h for DWORD access.
The table below lists the PCI bus and device numbers used by the single
board PC. It also lists the data range that must be written to the I/O
Configuration Address register to access the device.
DEVICE
TSC
PIIX
PIIX-IDE BUS MASTER
S3 Trio 64V+
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
BUS/DEVICE
/ FUNCTION
00 / 00 / 0
00 / 07 / 0
00 / 07 / 1
00 / 08 / 0
00 / 14 / 0
00 / 13 / 0
00 / 12 / 0
ID
SEL
N/A
AD18
AD18
AD19
AD31
AD30
AD29
I/O CONFIG ADDRESS
REGISTER
8000 0000 - 8000 00FC
8000 3800 - 8000 38FC
8000 3900 - 8000 39FC
8000 4000 - 8000 40FC
8000 8800 - 8000 88FC
8000 8600 - 8000 86FC
8000 8400 - 8000 84FC
INTERRUPTS & DMA CHANNELS
The following tables list the Interrupt and DMA Channel configuration
options for on-board devices. The serial ports, parallel ports, and IDE
controller can be configured using SETUP, or any other Plug and Play
resource manager (such as the Windows™ 95 Device Manager). The
Graphics interrupt is assigned by the auto-configure utility during boot up.
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APPENDICES
IRQ
NMI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DMA
0
1
2
3
4
5
6
7
PX1 USER MANUAL
RESERVED
INTERRUPTS
I/O Channel Check
Interval Timer
Keyboard buffer full
Cascade interrupt
from slave PIC
Serial 2 (COM2)
Serial 1 (COM1)
Parallel 2 (LPT2)
Floppy Controller
Parallel (LPT1)
Real time clock
Monitor Micro
(if present)
PS/2 Mouse
(if present)
Math co-processor
Primary E-IDE
Secondary E-IDE
RESERVED
Floppy
Cascade channel
CONNECTORS
BACK PANEL CONNECTORS
The back panel houses four connectors for the video, RS232
communications port, PS/2 mouse and PS/2 keyboard.
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APPENDICES
VIDEO CONNECTOR P12 (15 WAY CONDENSED D-TYPE)
PIN NO.
1
3
5
7
9
11
13
15
SIGNAL
Analogue RED
Analogue BLUE
0 Volts (Ground)
0 Volts (Ground)
Not Used
Not Used
Horizontal Sync
Not Used
PIN NO.
2
4
6
8
10
12
14
SIGNAL
Analogue GREEN
Not Used
0 Volts (Ground)
0 Volts (Ground)
0 Volts (Ground)
Not Used
Vertical Sync
PS/2 MOUSE PORT P13 (6 WAY MINI-DIN)
PIN NO.
1
3
5
SIGNAL
Mouse Data
Ground
Mouse Clock
PIN NO.
2
4
6
SIGNAL
Not Used
+5 Volts (fused)
Not Used
RS232 SERIAL PORT 1 P15 (9 WAY D-TYPE)
PIN NO.
1
3
5
7
9
SIGNAL
Data Carrier Detect
-Transmit Data
Ground
-Ready To Send
Ringing Indicator
PIN NO.
2
4
6
8
SIGNAL
-Receive Data
-Data Terminal Ready
-Data Set Ready
-Clear To Send
PS/2 KEYBOARD PORT P18 (6 WAY MINI-DIN)
PIN NO.
1
3
5
SIGNAL
Keyboard Data
Ground
Keyboard Clock
PIN NO.
2
4
6
SIGNAL
Not Used
+5 Volts (fused)
Not Used
INTERNAL I/O HEADERS
The board has a number of internal peripheral connectors:
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PX1 USER MANUAL
APPENDICES
PRIMARY IDE CONNECTOR P1 (40 WAY HEADER)
PIN NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SIGNAL
-Reset
Data bit 7 (HD)
Data bit 6 (HD)
Data bit 5 (HD)
Data bit 4 (HD)
Data bit 3 (HD)
Data bit 2 (HD)
Data bit 1 (HD)
Data bit 0 (HD)
Ground
Drive Request
-IO Write (HD)
-IO Read (HD)
Drive Ready
Drive Acknowledge
IRQ14
Address 1 (HD)
Address 0 (HD)
-Chip Select 0 (HD)
IDE LED Drive
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SIGNAL
Ground
Data bit 8 (HD)
Data bit 9 (HD)
Data bit 10 (HD)
Data bit 11 (HD)
Data bit 12 (HD)
Data bit 13 (HD)
Data bit 14 (HD)
Data bit 15 (HD)
Not used
Ground
Ground
Ground
Not Used
Ground
Not Used
1 Kohm to Ground
Address 2 (HD)
-Chip Select 1 (HD)
Ground
FLOPPY DISK DRIVE CONNECTOR P2 (34 WAY HEADER)
PIN N°
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
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SIGNAL
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
PIN N°
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
SIGNAL
+RPM/Low Current
Not used
Not used
-Index
-Motor 0
-Drive select 1
-Drive select 0
-Motor 1
+Direction
-Step
-Write Data
-Write Gate
-Track 0
-Write Protect
-Read Data
+Head Select
+Disk Change
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APPENDICES
RS485 SERIAL PORT 2 P3 (10 WAY HEADER)
PIN NO.
1
3
5
7
9
SIGNAL
+Rx FDX
-Rx FDX
+Tx FDX,
+Rx/+Tx HDX
-Tx FDX,
-RX/-Tx HDX
-Term. 10 K to Gnd
PIN NO.
2
4
6
SIGNAL
+Term. 10 K to +5V
No Connect
No Connect
8
No Connect
10
No Connect
RS232 SERIAL PORT 2 P4 (10 WAY HEADER)
Pin N°°
1
3
5
7
9
Signal
-Data Carrier Detect
-Receive Data
-Transmit Data
-Data Term Ready
Ground
Pin N°°
2
4
6
8
10
Signal
-Data Set Ready
-Ready To Send
-Clear To Send
-Ringing Indicator
Not used
POWER CONNECTOR P5 (4 WAY 5¼" DISK DRIVE CONNECTOR)
PIN N°°
1
2
3
4
SIGNAL
+12 Volts DC (Not required for PX1 operation.
Only required for PC/104 cards that need +12V).
Ground
Ground
+5 Volts DC (Pin 4 is at top left corner of board)
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PX1 USER MANUAL
APPENDICES
ECP/EPP PARALLEL PORT P6 (26 WAY HEADER)
PIN N°°
1
3
5
7
9
11
13
15
17
19
21
23
25
SIGNAL
-Strobe
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
-Acknowledge
Busy
Paper Empty
Select (Output)
PIN N°°
2
4
6
8
10
12
14
16
18
20
22
24
26
SIGNAL
-Auto Feed XT
-Error
-Initialise
-Select (input)
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not Used
IN SYSTEM EPLD PROGRAM P7 (6 WAY HEADER)
(Reserved for manufacturing use only. No user connection)
PIN NO.
1
3
5
01271019.doc
SIGNAL
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data In
PIN NO.
2
4
6
SIGNAL
JTAG Test Data Out
+5 Volt
Ground
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PX1 USER MANUAL
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APPENDICES
SECONDARY IDE CONNECTOR P8 (40 WAY HEADER)
PIN NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
SIGNAL
-Reset
Data bit 7 (HD)
Data bit 6 (HD)
Data bit 5 (HD)
Data bit 4 (HD)
Data bit 3 (HD)
Data bit 2 (HD)
Data bit 1 (HD)
Data bit 0 (HD)
Ground
Drive Request
-IO Write (HD)
-IO Read (HD)
Drive Ready
Drive Acknowledge
IRQ15
Address 1 (HD)
Address 0 (HD)
-Chip Select 0 (HD)
IDE LED Drive
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SIGNAL
Ground
Data bit 8 (HD)
Data bit 9 (HD)
Data bit 10 (HD)
Data bit 11 (HD)
Data bit 12 (HD)
Data bit 13 (HD)
Data bit 14 (HD)
Data bit 15 (HD)
Not used
Ground
Ground
Ground
Not Used
Ground
Not Used
1 Kohm to Ground
Address 2 (HD)
-Chip Select 1 (HD)
Ground
UTILITY CONNECTOR P9 (20 WAY HEADER)
PIN N°°
1
3
5
7
9
11
13
15
17
19
SIGNAL
Audio +ve
Reset +ve
High Speed LED +ve
Keylock +ve
Power LED +ve
Turbo Switch +ve
IDE LED +ve
+5V (fused)
+3.6 Volt Battery
Keyboard Data
Blue Chip Technology Ltd.
PIN N°°
2
4
6
8
10
12
14
16
18
20
SIGNAL
Audio -ve
Reset -ve (Ground)
High Speed LED -ve
Keylock -ve (Ground)
Power LED -ve (Ground)
Turbo Switch -ve (Ground)
IDE LED -ve
0 Volts (Ground)
0 Volts Battery (Ground)
Keyboard Clock
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PX1 USER MANUAL
APPENDICES
SECURITY/MONITOR MICROCONTROLLER P10 (10 WAY
HEADER)
(Reserved for future use)
PIN NO.
1
3
5
7
9
SIGNAL
Ext Temp Sensor Signal
Fault LED
Serial Security Key I/p
No Connect
No Connect
PIN
NO.
2
4
6
8
10
SIGNAL
Ext Temp Sensor Ground
Ext Temp Sensor +5 V
Ground
Ground
Ground
VESA VIDEO FEATURE CONNECTOR P11 (26 PIN HEADER)
PIN NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
SIGNAL
Ground
Ground
Ground
Enable Video
Enable Sync
Pixel Clock Enable
Red
Ground
Ground
Ground
Ground
Green
Blue
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
SIGNAL
Data P0
Data P1
Data P2
Data P3
Data P4
Data P5
Data P6
Data P7
Pixel Clock
Blank
Horizontal Sync
Vertical Sync
Ground
COAST CACHE CONNECTOR P16
This is an industry-standard connector for Cache On A Stick. The
COAST connector is a 160-pin socket which is designed to prevent
reversed fitting of the cache module.
Please note that each cache module is designed specifically for each
chipset i.e. there are cache modules specific to the 430FX Triton chipset.
The available options for the PX1 cache are 256kbyte asynchronous, 256
or 512KByte of synchronous Pipeline burst, or none.
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APPENDICES
BATTERY CONNECTOR P17 (4 WAY HEADER)
Pin N°°
1
2
3
4
Signal
+3.6 Volts DC
Not used (key)
Ground
Ground
BUS CONNECTORS
ISA BUS XT CONNECTIONS
A= Large gold fingers on main component side
B= Large gold fingers on reverse side
PIN NO.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
SIGNAL
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Blue Chip Technology Ltd.
PIN NO.
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
SIGNAL
Ground
Resetdrv
+5 Volts
IRQ9
-5 Volts
DREQ2
-12 Volts
-0WS
+12 Volts
Ground
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REF
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5 Volts
OSC
Ground
01271019.doc
PAGE 68
PX1 USER MANUAL
APPENDICES
ISA BUS AT CONNECTIONS
C= Large gold fingers on main component side
D= Large gold fingers on reverse side
PIN NO.
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
01271019.doc
SIGNAL
-SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
PIN NO.
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
SIGNAL
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
+5 Volts
-Master
Ground
Blue Chip Technology Ltd.
PX1 USER MANUAL
PAGE 69
APPENDICES
PC104 PC/XT CONNECTOR P20 (64 WAY SOCKET)
SIDE A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SIGNAL
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Ground
Blue Chip Technology Ltd.
SIDE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SIGNAL
Ground
Resetdrv
+5 Volts
IRQ9
-5 Volts
DREQ2
-12 Volts
-0WS
+12 Volts
Ground
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REF
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
T/C
BALE
+5 Volts
OSC
Ground
Ground
01271019.doc
PAGE 70
PX1 USER MANUAL
APPENDICES
PC104 PC/AT CONNECTOR P19 (40 WAY SOCKET)
SIDE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
01271019.doc
SIGNAL
Ground
-SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
No Connection
SIDE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SIGNAL
Ground
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
+5 Volts
-Master
Ground
Ground
Blue Chip Technology Ltd.
PX1 USER MANUAL
PAGE 71
APPENDICES
PCI CONNECTORS
PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A32
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
Blue Chip Technology Ltd.
SIGNAL NAME
GND
+12V
No Connect
No Connect
Vcc
PCIINT3PCIINT1Vcc
CLK3
Vcc
CLK4
GND
GND
GNT2#
SPCIRSTVcc
GNT1#
GND
REQ3#
AD30
3.3V
AD28
AD26
GND
AD24
GNT3#
3.3V
AD22
AD20
GND
AD18
AD16
3.3V
FRAMEGND
TRDYGND
STOP3.3V
SDONE
SBOGND
PAR
AD15
3.3V
AD13
AD11
GND
AD9
KEY
PIN
SIGNAL NAME
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B32
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
No Connect
GND
No Connect
Vcc
Vcc
PCIINT2PCIINT4REQ4#
REQ2#
GNT4#
GND
GND
CLK1
GND
CLK2
GND
REQ1#
Vcc
AD31
AD29
GND
AD27
AD25
3.3V
CBE3AD23
GND
AD21
AD19
3.3V
AD17
CBE2GND
IRDY3.3V
DEVSELGND
PLOCKPERR3.3V
SERR3.3V
CBE1AD14
GND
AD12
AD10
GND
01271019.doc
PAGE 72
PX1 USER MANUAL
APPENDICES
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
KEY
CBEO3.3V
AD6
AD4
GND
AD2
AD0
Vcc
SREQ64Vcc
Vcc
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
AD8
AD7
3.3V
AD5
AD3
GND
AD1
Vcc
SACK64Vcc
Vcc
NOTE: The PCI connector details shown here are for the PX1 processor card.
The PCI connectors of a backplane differ slightly, some pins having a position
dependent signal.
01271019.doc
Blue Chip Technology Ltd.
PX1 USER MANUAL
PAGE 73
ERROR MESSAGES
ERROR MESSAGES
AMIBIOS ERROR BEEP CODES
The BIOS performs a Power On Self Test (POST) after a reset or reboot. If
errors occur during the POST, the microprocessor indicates the status of the
test by writing codes to the I/O port at address 80 Hex. If the BIOS cannot
find and configure the display controller then the errors are communicated
through a series of audible beeps (by the speaker drive circuit). Fatal
errors, which prevent the system from continuing the boot process, will
produce beep codes.
Other errors are displayed textually.
Messages, in the following subsection.
For these see AMIBIOS Error
BEEPS
1long, 3
short
1
ERROR MESSAGE
Video failure
DESCRIPTION
A connection to a monitor was not detected.
Refresh Failure
2
3
Parity Error
Base 64 KB Memory
Failure
Timer Not
Operational
Processor Error
8042 - Gate A20
Failure
Processor Exception
Interrupt Error
Display Memory
Read/Write Error
ROM Checksum
Error
CMOS Shutdown
Register Rd/Wrt
Error
Cache Error /
External Cache Bad
The memory refresh circuitry on the single board PC
is faulty.
Parity is not supported on this product, will not occur.
Memory failure in the first 64 KB.
4
5
6
7
8
9
10
11
Blue Chip Technology Ltd.
Memory failure in the first 64 KB of memory, or
Timer 1 on the single board PC is not functioning.
The CPU on the single board PC generated an error.
The keyboard controller (8042) may be bad. The
BIOS cannot switch to protected mode.
The CPU generated an exception interrupt.
System video adapter is either missing or its memory
is faulty. This is not a fatal error.
ROM checksum value does not match the value
encoded in BIOS.
The shutdown register for CMOS RAM failed.
The external cache is faulty.
01271019.doc
PAGE 74
PX1 USER MANUAL
ERROR MESSAGES
AMIBIOS ERROR CODES ON THE POST DISPLAY
As the BIOS performs the POST after a reset or reboot, the microprocessor
indicates the status of the test by writing codes to the I/O port at address
80 Hex. The PX1 unit provides an on-board decode of this information
displaying the code on on-board LEDs. It can also drive an optional POST
display without modification. The following codes indicate the progress of
the microprocessor during the power on test.
UNCOMPRESSED INIT CODE CHECKPOINTS
CODE
(HEX)
D0
D1
D3
D4
D5
D6
D7
01271019.doc
DESCRIPTION
NMI is Disabled. CPU ID saved. Init code Checksum verification
starting.
To do DMA init, Keyboard controller BAT test, start memory refresh and
going to 4GB flat mode.
To start Memory sizing.
To come back to real mode. Execute OEM patch. Set stack.
E000 ROM enabled. Init code is copied to segment 0 and control to be
transfered to segment 0.
Control is in segment 0. To check <CTRL><HOME> key and verify
main BIOS checksum. If either <CTRL><HOME> is pressed or main
BIOS checksum is bad, go to check point E0 else goto check point D7.
Main BIOS runtime code is to be decompressed and control to be
passed to main BIOS in shadow RAM.
Blue Chip Technology Ltd.
PX1 USER MANUAL
ERROR MESSAGES
PAGE 75
BOOT BLOCK RECOVERY CODE CHECKPOINTS
CODE
(HEX)
E0
E1
E2
E6
ED
EE
EF
F0
F1
F2
F3
F4
F5
FB
FC
FD
FF
DESCRIPTION
On-Board Floppy Controller (if any) is initialised. To start base 512K
memory test.
To initialise interrupt vector table.
To initialise DMA and interrupt controllers.
To enable floppy and timer IRQ, enable internal cache.
Initialize floppy drive.
Start looking for a diskette in drive A: and read 1st sector of the
diskette.
Floppy read error.
Start searching ‘AMIBOOT.ROM’ file in root directory.
‘AMIBOOT.ROM’ file not present in root directory.
Start reading FAT table and analyze FAT to find the clusters occupied
by ‘AMIBOOT.ROM’ file..
Start reading ‘AMIBOOT.ROM’ file cluster by cluster.
‘AMIBOOT.ROM’ file not of proper size.
Disable internal cache.
Detect Flash type present.
Erase Flash.
Program Flash.
Flash program successful. BIOS is going to restart.
RUNTIME CODE IS UNCOMPRESSED IN F000 SHADOW RAM
CODE
(HEX)
03
05
06
07
08
0B
0C
0E
0F
10
11
12
13
14
19
DESCRIPTION
NMI is Disabled. To check soft reset/power-on.
BIOS stack set. Going to disable Cache if any.
POST code to be uncompressed.
CPU init and CPU data area init to be done.
CMOS checksum calculation to be done next.
Any initialisation before keyboard BAT to be done next.
KB controller I/B free. To issue the BAT command to keyboard controller.
Any initialisation after KB controller BAT to be done next.
Keyboard command byte to be written.
Going to issue Pin-23,24 blocking/unblocking command.
Going to check pressing of <INS> , <END> key during power-on.
To init CMOS if “Init CMOS in every boot” is set or <END> key is pressed.
Going to disable DMA and Interrupt controllers.
Video display is disabled and port-B is initialised. Chipset init about to
begin.
8254 timer test about to start.
About to start memory refresh test.
Blue Chip Technology Ltd.
01271019.doc
PAGE 76
CODE
(HEX)
1A
23
24
25
27
28
2A
2B
2C
2D
2E
2F
30
31
32
34
37
38
39
3A
40
42
43
44
45
46
47
48
49
4B
4C
4D
4E
4F
01271019.doc
ERROR MESSAGES
PX1 USER MANUAL
DESCRIPTION
Memory Refresh line is toggling. Going to check 15us ON/OFF time.
To read 8042 input port and disable Megakey GreenPC feature. Make
BIOS code segment writeable.
To do any setup before Int vector init.
Interrupt vector initialisation about to begin. To clear password if necessary.
Any initialisation before setting video mode to be done.
Going for monochrome mode and colour mode setting.
Different BUSes init (system, static, output devices) to start if present.
To give control for any setup required before optional video ROM check.
To look for optional video ROM and give control.
To give control to do any processing after video ROM returns control.
If EGA/VGA not found then do display memory R/W test.
EGA/VGA not found. Display memory R/W test about to begin.
Display memory R/W test passed. About to look for the retrace checking.
Display memory R/W test or retrace checking failed. To do alternate Display
memory R/W test.
Alternate Display memory R/W test passed. To look for the alternate display
retrace checking.
Video display checking over. Display mode to be set next.
Display mode set. Going to display the power on message.
Different BUSes init (input, IPL, general devices) to start if present.
Display different BUSes initialisation error messages.
New cursor position read and saved. To display the Hit <DEL> message.
To prepare the descriptor tables.
To enter in virtual mode for memory test.
To enable interrupts for diagnostics mode.
To Initialize data to check memory wrap around at 0:0.
Data initialised. Going to check for memory wrap around at 0:0 and finding
the total system memory size.
Memory wrap around test done. Memory size calculation over. About to go
for writing patterns to test memory.
Pattern to be tested written in extended memory. Going to write patterns in
base 640k memory.
Patterns written in base memory. Going to find out amount of memory
below 1M memory.
Amount of memory below 1M found and verified. Going to find out amount
of memory above 1M memory.
Amount of memory above 1M found and verified. Check for soft reset and
going to clear memory below 1M for soft reset. (If power on, go to check
point# 4Eh).
Memory below 1M cleared. (SOFT RESET) Going to clear memory above
1M.
Memory above 1M cleared. (SOFT RESET) Going to save the memory size.
(Goto check point# 52h).
Memory test started. (NOT SOFT RESET) About to display the first 64k
memory size.
Memory size display started. This will be updated during memory test.
Going for sequential and random memory test.
Blue Chip Technology Ltd.
PX1 USER MANUAL
CODE
(HEX)
50
51
52
53
54
57
58
59
60
62
65
66
7F
80
81
82
83
84
85
86
87
88
89
8B
8C
8D
8F
91
95
96
97
ERROR MESSAGES
PAGE 77
DESCRIPTION
Memory testing/initialisation below 1M complete. Going to adjust displayed
memory size for relocation/ shadow.
Memory size display adjusted due to relocation/ shadow. Memory test above
1M to follow.
Memory testing/initialisation above 1M complete. Going to save memory size
information.
Memory size information is saved. CPU registers are saved. Going to enter
in real mode.
Shutdown successful, CPU in real mode. Going to disable gate A20 line
and disable parity/NMI.
A20 address line, parity/NMI disable successful. Going to adjust memory
size depending on relocation/shadow.
Memory size adjusted for relocation/shadow. Going to clear Hit <DEL>
message.
Hit <DEL> message cleared. <WAIT...> message displayed. About to start
DMA and interrupt controller test.
DMA page register test passed. To do DMA#1 base register test.
DMA#1 base register test passed. To do DMA#2 base register test.
DMA#2 base register test passed. To program DMA unit 1 and 2.
DMA unit 1 and 2 programming over. To Initialize 8259 interrupt controller.
Extended NMI sources enabling is in progress.
Keyboard test started. clearing output buffer, checking for stuck key, to
issue keyboard reset command.
Keyboard reset error/stuck key found. To issue keyboard controller interface
test command.
Keyboard controller interface test over. To write command byte and init
circular buffer.
Command byte written, Global data init done. To check for lock-key.
Lock-key checking over. To check for memory size mismatch with CMOS.
Memory size check done. To display soft error and check for password or
bypass setup.
Password checked. About to do programming before setup.
Programming before setup complete. To uncompress SETUP code and
execute CMOS setup.
Returned from CMOS setup program and screen is cleared. About to do
programming after setup.
Programming after setup complete. Going to display power on screen
message.
First screen message displayed. <WAIT...> message displayed. PS/2
Mouse check and extended BIOS data area allocation to be done.
Setup options programming after CMOS setup about to start.
Going for hard disk controller reset.
Hard disk controller reset done. Floppy setup to be done next.
Floppy setup complete. Hard disk setup to be done next.
Init of different BUSes optional ROMs from C800 to start.
Going to do any init before C800 optional ROM control.
Any init before C800 optional ROM control is over. Optional ROM check and
control will be done next.
Blue Chip Technology Ltd.
01271019.doc
PAGE 78
CODE
(HEX)
98
99
9A
9B
9C
9D
9E
A2
A3
A4
A5
A7
A8
A9
AA
AB
B0
B1
00
01271019.doc
ERROR MESSAGES
PX1 USER MANUAL
DESCRIPTION
Optional ROM control is done. About to give control to do any required
processing after optional ROM returns control and enable external cache.
Any initialisation required after optional ROM test over. Going to setup timer
data area and printer base address.
Return after setting timer and printer base address. Going to set the RS-232
base address.
Returned after RS-232 base address. Going to do any initialisation before
Coprocessor test
Required initialisation before Coprocessor is over. Going to Initialize the
Coprocessor next.
Coprocessor initialised. Going to do any initialisation after Coprocessor test.
Initialisation after Coprocessor test is complete. Going to check extd
keyboard, keyboard ID and num-lock. Keyboard ID command to be
Going to display any soft errors.
Soft error display complete. Going to set keyboard typematic rate.
Keyboard typematic rate set. To program memory wait states.
Going to enable parity/NMI.
NMI and parity enabled. Going to do any initialisation required before giving
control to optional ROM at E000.
Initialisation before E000 ROM control over. E000 ROM to get control next.
Returned from E000 ROM control. Going to do any initialisation required
after E000 optional ROM control.
Initialisation after E000 optional ROM control is over. Going to display the
system configuration.
To uncompress DMI data and execute DMI POST init.
System configuration is displayed.
Going to copy any code to specific area.
Copying of code to specific area done. Going to give control to INT-19 boot
loader.
Blue Chip Technology Ltd.
PX1 USER MANUAL
ERROR MESSAGES
PAGE 79
AMIBIOS ERROR MESSAGES
Textual error messages are displayed in the following format:
ERROR Message Line 1
ERROR Message Line 2
For most displayed error messages, there is only one message. If a second
message appears, it is "RUN SETUP". If this message occurs, press <F1> to
run Setup Utility. The table of messages is shown on the next page.
Blue Chip Technology Ltd.
01271019.doc
PAGE 80
PX1 USER MANUAL
ERROR MESSAGES
ERROR
MESSAGE
EXPLANATION
8042 Gate - A20
Error
Address Line Short!
Cache Memory
Bad, Do Not Enable
Cache!
CH-2 Timer Error
CMOS Battery State
Low
CMOS Checksum
Failure
Gate A20 on the keyboard controller (8042) is not working. Replace the 8042.
CMOS System
Options Not Set
CMOS Display
Type Mismatch
CMOS Memory
Size Mismatch
CMOS Time and
Date Not Set
Diskette Boot
Failure
Display Switch Not
Proper
DMA Error
DMA #1 Error
DMA #2 Error
FDD Controller
Failure
HDD Controller
Failure
INTR #1 Error
INTR #2 Error
Invalid Boot
Diskette
Keyboard Is
Locked...Unlock It
Keyboard Error
KB/Interface Error
Off Board Parity
Error
On Board Parity
Error
Parity Error ????
01271019.doc
Error in the address decoding circuitry on the single board PC.
Cache memory is defective. Replace it.
Most AT systems include two timers. There is an error in timer 2.
CMOS RAM is powered by a battery. The battery power is low. Replace the
battery.
After CMOS RAM values are saved, a checksum value is generated for error
checking. The previous value is different from the current value. Run AMIBIOS
Setup.
The values stored in CMOS RAM are either corrupt or non-existent. Run
Setup.
The video type in CMOS RAM does not match the type detected by the BIOS.
Run AMIBIOS Setup.
The amount of memory on the single board PC is different than the amount in
CMOS RAM. Run AMIBIOS Setup.
Run Standard CMOS Setup to set the date and time in CMOS RAM.
The boot disk in floppy drive A: is corrupt. It cannot be used to boot the
system. Use another boot disk and follow the screen instructions.
The display jumper is not implemented on this product, this error will not
occur.
Error in the DMA controller.
Error in the first DMA channel.
Error in the second DMA channel.
The BIOS cannot communicate with the floppy disk drive controller. Check all
appropriate connections after the system is powered down.
The BIOS cannot communicate with the hard disk drive controller. Check all
appropriate connections after the system is powered down.
Interrupt channel 1 failed POST.
Interrupt channel 2 failed POST.
The BIOS can read the disk in floppy drive A:, but cannot boot the system. Use
another boot disk.
The keyboard lock on the system is engaged. The system must be unlocked to
continue.
There is a timing problem with the keyboard. Set the Keyboard option in
Standard CMOS Setup to Not Installed to skip the keyboard POST routines.
There is an error in the keyboard connector.
Parity error in memory installed in an expansion slot. The format is:
OFF BOARD PARITY ERROR ADDR (HEX) = (XXXX)
Where “XXXX” is the hex address where the error occurred.
Parity is not supported on this product, this error will not occur.
Parity error in system memory at an unknown address.
Blue Chip Technology Ltd.
PX1 USER MANUAL
PAGE 81
ERROR MESSAGES
ISA NMI MESSAGES
ISA NMI MESSAGE
Memory Parity Error at
XXXXX
I/O Card Parity Error at
XXXXX
DMA Bus Time-out
EXPLANATION
Memory failed.
If the memory location can be determined, it is displayed as
XXXXX. If not, the message is Memory Parity Error ????.
An expansion card failed.
If the address can be determined, it is displayed as XXXXX.
If not, the message is I/O Card Parity Error ????.
A device has driven the bus signal for more than
7.8 microseconds.
PCI CONFIGURATION ERROR MESSAGES
The following PCI messages are displayed as a group with bus, device and
function information.
<'NVRAM Checksum Error, NVRAM Cleared'>, \ ; String
<'System Board Device Resource Conflict'>, \ ; String
<'Primary Output Device Not Found'>, \ ; String
<'Primary Input Device Not Found'>, \ ; String
<'Primary Boot Device Not Found'>, \ ; String
<'NVRAM Cleared By Jumper'>, \ ; String
<'NVRAM Data Invalid, NVRAM Cleared'>, \ ; String
<'Static Device Resource Conflict'>, \ ; String
The following messages chain together to give a message such as:
"PCI I/O Port Conflict: Bus: 00, Device 0D, Function: 01".
If and when more than 15 PCI conflict errors are detected, the log full
message is displayed.
<'PCI I/O Port Conflict:'>, \ ; String
<'PCI Memory Conflict: '>, \ ; String
<'PCI IRQ Conflict: '>, \ ; String
<' Bus '>, \ ; String
<', Device '>, \ ; String
<', Function '>, \ ; String
<'PCI Error Log is Full.'>, \ ; String
<'Floppy Disk Controller Resource Conflict '>, \ ; Text
Blue Chip Technology Ltd.
01271019.doc
PAGE 82
ERROR MESSAGES
PX1 USER MANUAL
<'Primary IDE Controller Resource Conflict '>, \ ; Text
<'Secondary IDE Controller Resource Conflict '>, \ ; Text
<'Parallel Port Resource Conflict '>, \ ; Text
<'Serial Port 1 Resource Conflict '>, \ ; Text
<'Serial Port 2 Resource Conflict '>, \ ; Text
01271019.doc
Blue Chip Technology Ltd.
PX1 USER MANUAL
PAGE 83
BOARD LAYOUT
Blue Chip Technology Ltd.
127-172
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