ADSP-21060C/LC Data sheet

ADSP-21060C/LC Data sheet
a
ADSP-21060 Industrial SHARC®
DSP Microcomputer Family
ADSP-21060C/ADSP-21060LC
SUMMARY
High Performance Signal Processor for Communications, Graphics, and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch, and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
Industrial Temperature Grade Hermetic Ceramic QFP
Package
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced CQFP Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit FixedPoint Data Format
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and BitReverse Addressing
4 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel
with Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
TWO INDEPENDENT
DUAL-PORTED BLOCKS
32 x 48-BIT
PROCESSOR PORT
ADDR
DATA
ADDR
DAG1
DAG2
8 x 4 x 32
8 x 4 x 24
I/O PORT
DATA
DATA
DATA
DM ADDRESS BUS
IOD
48
24
IOA
17
EXTERNAL
PORT
ADDR BUS
MUX
32
7
TEST &
EMULATION
ADDR
ADDR
PROGRAM
SEQUENCER
PM ADDRESS BUS
JTAG
BLOCK 1
INSTRUCTION
CACHE
BLOCK 0
DUAL-PORTED SRAM
CORE PROCESSOR
TIMER
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
32
MULTIPROCESSOR
INTERFACE
PM DATA BUS
BUS
CONNECT
(PX)
48
DATA BUS
MUX
DM DATA BUS 40/32
48
HOST PORT
DATA
REGISTER
FILE
MULTIPLIER
16 x 40-BIT
IOP
REGISTERS
(MEMORY MAPPED)
BARREL
SHIFTER
ALU
CONTROL,
STATUS &
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
I/O PROCESSOR
Figure 1. Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
NOTE: The 5 V timing numbers are finalized. The 3.3 V timing numbers are
subject to change.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
␣␣
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADSP-21060C/ADSP-21060LC
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-2106xs Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
240 Mbytes/s Transfer Rate Over Parallel Bus
240 Mbytes/s Transfer Rate Over Link Ports
DMA Controller
10 DMA Channels for Transfers Between ADSP-2106x
Internal Memory and External Memory, External
Peripherals, Host Processor, Serial Ports, or Link
Ports
Background DMA Transfers at 40 MHz, in Parallel with
Full-Speed Processor Execution
Host Processor Interface to 16- and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-2106x Internal
Memory
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21060C/ADSP-21060LC FEATURES . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE®
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS (5 V) . 13
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13
POWER DISSIPATION ADSP-21060C (5 V) . . . . . . . . . . 14
RECOMMENDED OPERATING CONDITIONS (3.3 V) 15
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15
POWER DISSIPATION ADSP-21060LC (3.3 V) . . . . . . . . 16
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 25
Asynchronous Read/Write—Host to ADSP-2106x . . . . . . 27
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 32
Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 33
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42
240-LEAD METRIC CQFP PIN CONFIGURATIONS . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 45
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7. JTAG Clocktree for Multiple ADSP-2106x
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20
Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21
Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23
Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24
Figure 17. Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27
Figure 18b. Asynchronous Read/Write—Host to
ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19b. Three-State Timing (Host Transition Cycle) . . 29
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31
Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37
Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38
Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40
Figure 26. Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40
Figure 28. ADSP-2106x Typical Drive Currents
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 29. Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . 41
Figure 30. Typical Output Rise Time (0.8 V–2.0 V)
vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . 41
Figure 31. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . . 41
Figure 32. ADSP-2106x Typical Drive Currents
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 33. Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . 41
Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 3.3 V) . . . . . . . . 42
FIGURES
Figure 1. ADSP-21060C/ADSP-21060LC Block Diagram . . 1
Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4. ADSP-21060C/ADSP-21060LC Memory Map . . . 7
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11
Figure 6. JTAG Scan Path Connections for Multiple
ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EZ-ICE is a registered trademark of Analog Devices, Inc.
–2–
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ADSP-21060C/ADSP-21060LC
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
S
GENERAL DESCRIPTION
The ADSP-2106x SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-2106x
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-2106x builds on the ADSP21000 DSP core to form a complete system-on-a-chip, adding a
dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-2106x.
Figure 2 shows a typical single-processor system. A multiprocessing system is shown in Figure 3.
Table I. ADSP-21060C/ADSP-21060LC Benchmarks
(@ 40 MHz)
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Divide (y/x)
Inverse Square Root (1/√x)
DMA Transfer Rate
The ADSP-2106x SHARC represents a new standard of integration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
including a 4 Mbit SRAM memory host processor interface,
DMA controller, serial ports, and link port and parallel bus
connectivity for glueless DSP multiprocessing.
Figure 1 shows a block diagram of the ADSP-21060C/
ADSP-21060LC, illustrating the following architectural features:
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–3–
0.46 ms
18,221 cycles
25 ns
100 ns
150 ns
225 ns
240 Mbytes/s
1 cycle
4 cycles
6 cycles
9 cycles
ADSP-21060C/ADSP-21060LC
ADSP-21000 FAMILY CORE ARCHITECTURE
Instruction Cache
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-21060C is codeand function-compatible with the ADSP-21061 and ADSP-21062.
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all perform single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended precision 40-bit floatingpoint, and 32-bit fixed-point data formats.
4
IRQ2-0
FLAG3-0
TIMEXP
LINK
DEVICES
(6 MAXIMUM)
(OPTIONAL)
LxCLK
LxACK
LxDAT3-0
SERIAL
DEVICE
(OPTIONAL)
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
SERIAL
DEVICE
(OPTIONAL)
TCLK1
RCLK1
TFS1
RFS1
DT1
DR1
RPBA
ID2-0
RESET
CS
BOOT
EPROM
(OPTIONAL)
DATA
ADDR
DATA
3
BMS
CONTROL
CLKIN
EBOOT
LBOOT
ADDRESS
ADSP-2106x
1x CLOCK
ADDR31-0
ADDR
DATA47-0
DATA MEMORY
AND
OE PERIPHERALS
WE (OPTIONAL)
ACK
CS
RD
WR
ACK
MS3-0
PAGE
SBTS
SW
ADRCLK
DMAR1-2
DMAG1-2
CS
HBR
HBG
REDY
BR1-6
CPA
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, and
simplifying implementation. Circular buffers can start and end
at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP2106x can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
DMA DEVICE
(OPTIONAL)
DATA
ADSP-21060C/ADSP-21060LC FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21060
adds the following architectural features:
Dual-Ported On-Chip Memory
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
The ADSP-21060C contains four megabits of on-chip SRAM,
organized as two blocks of 2 Mbits each, which can be configured for different combinations of code and data storage.
Each memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
ADDR
DATA
JTAG
7
Figure 2. ADSP-2106x System
On the ADSP-21060C, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of 16-bit
data, 80K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floatingpoint formats is done in a single instruction.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache),
all in a single cycle.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP2106x’s external port.
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ADSP-21060C/ADSP-21060LC
Off-Chip Memory and Peripherals Interface
Serial Ports
The ADSP-2106x’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
The ADSP-2106x features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold, and disable time
requirements.
Host Processor Interface
The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s external port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-2106x’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
The ADSP-2106x’s on-chip DMA controller allows zerooverhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
DMA transfers can occur between the ADSP-2106x’s internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-2106x’s internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-2106x—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-2106xs, memory or I/O transfers). Four additional link
port DMA channels are shared with serial port 1 and the external port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR1-2, DMAG1-2 ). Other DMA features include interrupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
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The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Multiprocessing
The ADSP-2106x offers powerful features tailored to multiprocessing DSP systems. The unified address space (see
Figure 4) allows direct interprocessor accesses of each ADSP2106x’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-2106xs and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port. Broadcast writes allow simultaneous transmission of data to all ADSP-2106xs and can be used
to implement reflective semaphores.
Link Ports
The ADSP-2106x features six 4-bit link ports that provide additional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits per cycle. Link port
I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems.
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Program Booting
The internal memory of the ADSP-2106x can be booted at
system power-up from either an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
–5–
ADDRESS
DATA
ADDRESS
DATA
ADSP-2106x #3
CONTROL
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
CONTROL
ADSP-21060C/ADSP-21060LC
ADDR31-0
CLKIN
DATA47-0
RESET
RPBA
011
3
ID 2-0
CONTROL
CPA
BR1-2, BR4-6
5
BR3
ADSP-2106x #2
CLKIN
RESET
ADDR31-0
DATA47-0
RPBA
3
010
ID 2-0
CONTROL
CPA
BR1, BR3-6
5
BR2
ADSP-2106x #1
1x
CLOCK
CLKIN
RESET
RESET
RPBA
001
3
ID 2-0
CONTROL
ADDR31-0
ADDR
DATA47-0
DATA
OE
WE
ACK
CS
RD
WR
ACK
MS3-0
CS
BMS
PAGE
SBTS
SW
ADRCLK
ADDR
DATA
CS
HBR
HBG
REDY
CPA
BR2-6
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
5
DATA
BR1
Figure 3. Shared Memory Multiprocessing System
–6–
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ADSP-21060C/ADSP-21060LC
0x0000 0000
0x0040 0000
IOP REGISTERS
INTERNAL
MEMORY
SPACE
0x0002 0000
BANK 0
0x0004 0000
DRAM
(OPTIONAL)
NORMAL WORD ADDRESSING
MS0
SHORT WORD ADDRESSING
0x0008 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=001
BANK 1
MS1
BANK 2
MS2
BANK 3
MS3
0x0010 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=010
0x0018 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=011
0x0020 0000
MULTIPROCESSOR
MEMORY SPACE
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=100
EXTERNAL
MEMORY
SPACE
0x0028 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0x0030 0000
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
0x0038 0000
BROADCAST WRITE
TO ALL
ADSP-2106xs
NONBANKED
0x003F FFFF
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 4. ADSP-21060C/ADSP-21060LC Memory Map
DEVELOPMENT TOOLS
The ADSP-21060C is supported with a complete set of software
and hardware development tools, including an EZ-ICE InCircuit Emulator, EZ-Kit, and development software. The
SHARC EZ-Kit is a complete low cost package for DSP evaluation and prototyping. The EZ-Kit contains a PC plug-in card
(EZ-LAB®) with an ADSP-21062 (5 V) processor. The EZ-Kit
also includes an optimizing compiler, assembler, instruction
level simulator, run-time libraries, diagnostic utilities and a
complete set of example programs.
Analog Devices ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
Assembly Library/Librarian, Linker, instruction-level Simulator,
an ANSI C optimizing Compiler, the CBug™ C Source—Level
Debugger and a C Runtime Library including DSP and mathematical functions. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x processor to monitor
and control the target board processor during emulation. The
EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware and Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21060C
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer to
the ADSP-2106x SHARC User’s Manual, Second Edition.
CBUG and SHARCPAC are trademarks of Analog Devices, Inc.
EZ-LAB is a registered trademark of Analog Devices, Inc.
REV. 0
–7–
ADSP-21060C/ADSP-21060LC
DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS
and TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.
PIN FUNCTION DESCRIPTIONS
ADSP-21060C pin definitions are listed below. All pins are
identical on the ADSP-21060C and ADSP-21060LC. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).
A = Asynchronous
G = Ground
I = Input
O = Output
P = Power Supply
S = Synchronous
(A/D) = Active Drive (O/D) = Open Drain
T = Three-State (when SBTS is asserted, or when the
ADSP-2106x is a bus slave)
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31-0 , DATA47-0 , FLAG3-0, SW, and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
Pin
Type
Function
ADDR31-0
I/O/T
External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal
memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host
processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
DATA47-0
I/O/T
External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit
single-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the
bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short
word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over
bits 23–16. Pull-up resistors on unused DATA pins are not necessary.
MS3-0
O/T
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank size must be defined in the ADSP-2106x’s system control register
(SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the MS3-0 lines are inactive; they are
active however when a conditional memory access instruction is executed, whether or not the condition
is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a
multiprocessing system the MS3-0 lines are output by the bus master.
RD
I/O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory
devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP2106xs) must assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system
RD is output by the bus master and is input by all other ADSP-2106xs.
WR
I/O/T
Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory
devices or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to
the ADSP-2106x’s internal memory. In a multiprocessing system WR is output by the bus master and
is input by all other ADSP-2106xs.
PAGE
O/T
DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control
register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can
only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
ADRCLK
O/T
Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous
memory devices (including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an
early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a
conditional write instruction). In a multiprocessing system, SW is output by the bus master and is
input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.
SW is asserted at the same time as the address output. A host processor using synchronous writes must
assert this pin when writing to the ADSP-2106x(s).
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add wait
states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.
The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was
last driven.
–8–
REV. 0
ADSP-21060C/ADSP-21060LC
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x
attempts to access external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host
processor/ADSP-2106x deadlock, or used with a DRAM controller.
IRQ2-0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG3-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master
will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address,
data, select and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus
requests (BR6-1) in a multiprocessing system.
HBG
I/O
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-2106x.
REDY (O/D) O
Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the CS and HBR inputs are asserted.
DMAR1
I/A
DMA Request 1 (DMA Channel 7).
DMAR2
I/A
DMA Request 2 (DMA Channel 8).
DMAG1
O/T
DMA Grant 1 (DMA Channel 7).
DMAG2
O/T
DMA Grant 2 (DMA Channel 8).
BR6-1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins
should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an
output.
ID2-0
I
Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP2106x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed
at reset.
RPBA
I/S
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPA (O/D)
I/O
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave
to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain
output that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 kΩ pull-up
resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
REV. 0
–9–
ADSP-21060C/ADSP-21060LC
Pin
Type
Function
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDTA3-0
I/O
Link Port Data (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxCLK
I/O
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxACK
I/O
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When
LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
BMS
I/O/T*
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP-2106x will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
CLKIN
I
Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-2106x to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after powerup or held low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor.
EMU (O/D)
O
Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.
ICSA
O
Reserved, leave unconnected.
VDD
P
Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins).
GND
G
Power Supply Return. (30 pins).
NC
Do Not Connect. Reserved pins which must be left open and unconnected.
–10–
REV. 0
ADSP-21060C/ADSP-21060LC
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI,
TDO, EMU, and GND signals be made accessible on the target
system via a 14-pin connector (a 2 row × 7 pin strip header) such
as that shown in Figure 5. The EZ-ICE probe plugs directly onto
this connector for chip-on-board emulation. You must add this
connector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZICE connector and the furthest device sharing the EZ-ICE
JTAG pins should be limited to 15 inches maximum for guaranteed operation. This length restriction must include EZ-ICE
JTAG signals that are routed to one or more ADSP-2106x
devices, or a combination of ADSP-2106x devices and other
JTAG devices on the chain.
The BTMS, BTCK, BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie BTRST to GND
and tie or pull BTCK up to VDD. The TRST pin must be
asserted after power-up (through BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
Signal
1
2
Driven through 22 Ω Resistor (16 mA Driver)
Driven at 10 MHz through 22 Ω Resistor (16 mA
Driver)
TRST* Active Low Driven through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
TDI
Driven by 22 Ω Resistor (16 mA Driver)
TDO
One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU
Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
TMS
TCK
EMU
GND
3
4
5
6
7
8
9
10
KEY (NO PIN)
CLKIN (OPTIONAL)
TMS
BTMS
TCK
BTCK
BTRST
TRST
9
11
12
BTDI
13
TDI
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
TDO
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
14
GND
Termination
TOP VIEW
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
OTHER
JTAG
CONTROLLER
ADSP-2106x
n
EMU
TMS
TRST
TDO
TDI
TCK
TRST
TDO
TDI
TMS
TMS
EMU
TRST
TDO
TDI
TCK
TDI
EZ-ICE
JTAG
CONNECTOR
JTAG
DEVICE
(OPTIONAL)
TCK
ADSP-2106x
#1
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
REV. 0
–11–
ADSP-21060C/ADSP-21060LC
TMS, CLKIN and EMU should be treated as critical signals in
terms of skew, and should be laid out as short as possible on
your board. If TCK, TMS and CLKIN are driving a large number of ADSP-21061 (more than eight) in your system, then
treat them as a clock tree using multiple drivers to minimize
skew. (See Figure 7, JTAG Clock Tree, and Clock Distribution
in the High Frequency Design Considerations section of the
ADSP-2106x User’s Manual, Second Edition.)
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping and single-stepping multiple ADSP-21061 in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP21061/ADSP-21061L processors and the CLKIN pin on the
EZ-ICE header must be minimal. If the skew is too large, synchronous operations may be off by one or more cycles between
processors. For synchronous multiprocessor operation TCK,
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP2100 Family JTAG EZ-ICE User’s Guide and Reference.
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
5kV
*
TDI
EMU
5kV
*
TCK
TMS
TRST
TDO
CLKIN
EMU
SYSTEM
CLKIN
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
–12–
REV. 0
ADSP-21060C/ADSP-21060LC
ADSP-21060C–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
Parameter
VDD
TCASE
VIH1
VIH2
VIL
Supply Voltage
Case Operating Temperature
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
4.75
–40
2.0
2.2
–0.5
K Grade
Max
5.25
+100
VDD + 0.5
VDD + 0.5
0.8
Units
V
°C
V
V
V
NOTES
1
Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQ 2-0, FLAG 3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID 2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2
Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
Test Conditions
1
High Level Output Voltage
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
Min
2
@ VDD = min, IOH = –2.0 mA
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
Max
Units
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
4.1
NOTESS
11
Applies to output and bidirectional pins: DATA 47-0, ADDR 31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG 3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR 6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12
See “Output Drive Currents” for typical drive current capabilities.
13
Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
14
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15
Applies to three-statable pins: DATA47-0 , ADDR31-0, MS 3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX , RFSX , TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-21060 is
not requesting bus mastership.)
16
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17
Applies to CPA pin.
18
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-21060 is not requesting bus mastership).
19
Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
REV. 0
–13–
ADSP-21060C/ADSP-21060LC
POWER DISSIPATION ADSP-21060C (5 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK)
High Activity (IDDINHIGH)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
Parameter
Test Conditions
Max
Units
IDDINPEAK
Supply Current (Internal)1
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
745
850
mA
mA
IDDINHIGH
Supply Current (Internal)2
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
575
670
mA
mA
IDDINLOW
Supply Current (Internal)2
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
340
390
mA
mA
IDDIDLE
Supply Current (Idle)3
VDD = max
200
mA
NOTESS
1
The test program used to measure I DDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I DDINHIGH is a composite average based on a range of high activity code. I DDINLOW is a composite average based on a range of low activity code.
3
Idle denotes ADSP-21060C state during execution of IDLE instruction.
–14–
REV. 0
ADSP-21060C/ADSP-21060LC
ADSP-21060LC–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)
Parameter
VDD
TCASE
VIH1
VIH2
VIL
Supply Voltage
Case Operating Temperature
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
3.15
–40
2.0
2.2
–0.5
K Grade
Max
3.45
+100
VDD + 0.5
VDD + 0.5
0.8
Units
V
°C
V
V
V
NOTES
1
Applies to input and bidirectional pins: DATA 47-0, ADDR 31-0, RD, WR, SW, ACK, SBTS, IRQ 2-0, FLAG 3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID 2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0,
RCLK1.
2
Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
VOH
VOL
IIH
IIL
IILP
IOZH
IOZL
IOZHP
IOZLC
IOZLA
IOZLAR
IOZLS
CIN
Test Conditions
1
High Level Output Voltage
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
Low Level Input Current4
Three-State Leakage Current5, 6, 7, 8
Three-State Leakage Current5, 9
Three-State Leakage Current9
Three-State Leakage Current7
Three-State Leakage Current10
Three-State Leakage Current8
Three-State Leakage Current6
Input Capacitance11, 12
Min
2
@ VDD = min, IOH = –2.0 mA
@ VDD = min, IOL = 4.0 mA2
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 2 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V
Max
Units
0.4
10
10
150
10
10
350
1.5
350
4.2
150
4.7
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
pF
2.4
NOTES
11
Applies to output and bidirectional pins: DATA 47-0, ADDR 31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG 3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR 6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
12
See “Output Drive Currents” for typical drive current capabilities.
13
Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
14
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15
Applies to three-statable pins: DATA47-0 , ADDR31-0, MS 3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX , RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another ADSP-21060LC
is not requesting bus mastership.)
16
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17
Applies to CPA pin.
18
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID 2-0 = 001 and another
ADSP-21060LC is not requesting bus mastership).
19
Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
REV. 0
–15–
ADSP-21060C/ADSP-21060LC
POWER DISSIPATION ADSP-21060LC (3.3 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (IDDINPEAK )
High Activity (IDDINHIGH)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
Parameter
Test Conditions
Max
Units
IDDINPEAK
1
Supply Current (Internal)
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
540
600
mA
mA
IDDINHIGH
Supply Current (Internal)2
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
425
475
mA
mA
IDDINLOW
Supply Current (Internal)2
tCK = 30 ns, VDD = max
tCK = 25 ns, VDD = max
250
275
mA
mA
IDDIDLE
Supply Current (Idle)3
VDD = max
180
mA
NOTESS
1
The test program used to measure I DDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I DDINHIGH is a composite average based on a range of high activity code. I DDINLOW is a composite average based on a range of low activity code.
3
Idle denotes ADSP-21060LC state during execution of IDLE instruction.
–16–
REV. 0
ADSP-21060C/ADSP-21060LC
ABSOLUTE MAXIMUM RATINGS (5 V)*
ABSOLUTE MAXIMUM RATINGS (3.3 V)*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21060C/ADSP-21060LC features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING SPECIFICATIONS
See Figure 28 under Test Conditions for voltage reference
levels.
Two speed grades of the ADSP-21060C are offered, 40 MHz
and 33.3 MHz. The specifications shown are based on a
CLKIN frequency of 40 MHz (tCK = 25 ns). The DT derating
allows specifications at other CLKIN frequencies (within the
min–max range of the tCK specification; see Clock Input below).
DT is the difference between the actual CLKIN period and a
CLKIN period of 25 ns:
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
DT = tCK – 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
REV. 0
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
–17–
ADSP-21060C/ADSP-21060LC
Parameter
ADSP-21060C
40 MHz
33 MHz
Min
Max
Min
Max
ADSP-21060LC
40 MHz
33 MHz
Min
Max Min
Max
25
7
5
25
9.5
5
Units
Clock Input
Timing Requirements:
tCK
CLKIN Period
CLKIN Width Low
tCKL
CLKIN Width High
tCKH
tCKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
100
30
7
5
3
100
3
100
30
9.5
5
3
100
ns
ns
ns
ns
3
tCK
CLKIN
tCKH
tCKL
Figure 8. Clock Input
Parameter
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
Units
4tCK
14 + DT/2
4tCK
14 + DT/2
ns
ns
Reset
Timing Requirements:
tWRST
RESET Pulsewidth Low1
tSRST
RESET Setup before CLKIN High2
tCK
tCK
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
tSRST
tWRST
RESET
Figure 9. Reset
Parameter
Interrupts
Timing Requirements:
tSIR
IRQ2-0 Setup before CLKIN High1
IRQ2-0 Hold before CLKIN High1
tHIR
tIPW
IRQ2-0 Pulsewidth2
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
18 + 3DT/4
18 + 3DT/4
12 + 3DT/4
2 + tCK
12 + 3DT/4
2 + tCK
Units
ns
ns
ns
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t SIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2-0
tIPW
Figure 10. Interrupts
–18–
REV. 0
ADSP-21060C/ADSP-21060LC
ADSP-21060C
Min
Max
Parameter
Timer
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
ADSP-21060LC
Min
Max
15
15
Units
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 11. Timer
Parameter
Flags
Timing Requirements:
tSFI
FLAG3-0IN Setup before CLKIN High1
FLAG3-0IN Hold after CLKIN High1
tHFI
FLAG3-0IN Delay after RD/WR Low1
tDWRFI
FLAG3-0IN Hold after RD/WR Deasserted 1
tHFIWR
Switching Characteristics:
FLAG3-0OUT Delay after CLKIN High
tDFO
FLAG3-0OUT Hold after CLKIN High
tHFO
CLKIN High to FLAG3-0OUT Enable
tDFOE
tDFOD
CLKIN High to FLAG3-0OUT Disable
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
8 + 5DT/16
0 – 5DT/16
8 + 5DT/16
0 – 5DT/16
5 + 7DT/16
0
5 + 7DT/16
0
16
4
3
16
4
3
14
14
NOTE
1
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tHFO
FLAG3-0OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG3-0I N
tDWRFI
tHFIWR
RD, WR
FLAG INPUT
Figure 12. Flags
REV. 0
–19–
tDFO
tDFOD
Units
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21060C/ADSP-21060LC
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
Parameter
Min
Timing Requirements:
tDAD
Address, Selects Delay to Data Valid 1, 2
tDRLD
RD Low to Data Valid 1
tHDA
Data Hold from Address, Selects3
tHDRH
Data Hold from RD High3
tDAAK
ACK Delay from Address, Selects 2, 4
tDSAK
ACK Delay from RD Low4
Switching Characteristics:
tDRHA
Address, Selects Hold after RD High
tDARL
Address, Selects to RD Low2
tRW
RD Pulsewidth
tRWR
RD High to WR, RD, DMAGx Low
tSADADC Address, Selects Setup before
ADRCLK High2
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
ADSP-21060C
Max
Min
ADSP-21060LC
Max
18 + DT + W
12 + 5DT/8 + W
0.5
2.0
18 + DT + W
12 + 5DT/8 + W
0.5
2.0
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W
8 + DT/2 + W
Units
ns
ns
ns
ns
ns
ns
0+H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0+H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
ns
ns
ns
ns
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t CK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
Data Delay/Setup: User must meet t DAD or t DRLD or synchronous spec t SSDATI.
The falling edge of MSx, SW, BMS is referenced.
3
Data Hold: User must meet t HDA or tHDRH or synchronous spec t HSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
4
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
1
2
ADDRESS
MSx, SW
BMS
tDARL
tRW
tDRHA
RD
tHDA
tDRLD
tDAD
tHDRH
DATA
tDSAK
tRWR
tDAAK
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 13. Memory Read—Bus Master
–20–
REV. 0
ADSP-21060C/ADSP-21060LC
Memory Write—Bus Master
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
Parameter
ADSP-21060C
Max
Min
Timing Requirements:
tDAAK
ACK Delay from Address, Selects 1, 2
tDSAK
ACK Delay from WR Low1
Min
ADSP-21060LC
Max
14 + 7DT/8 + W
8 + DT/2 + W
Switching Characteristics:
tDAWH
Address, Selects to WR Deasserted 2
tDAWL
Address, Selects to WR Low2
tWW
WR Pulsewidth
tDDWH Data Setup before WR High
tDWHA
Address Hold after WR Deasserted
tDATRWH Data Disable after WR Deasserted 3
tWWR
WR High to WR, RD, DMAGx Low
tDDWR
Data Disable before WR or RD Low
tWDE
WR Low to Data Enabled
tSADADC Address, Selects to ADRCLK High2
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
6 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
14 + 7DT/8 + W
8 + DT/2 + W
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
6 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2
The falling edge of MSx, SW, BMS is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
ADDRESS
MSx , SW
BMS
tDWHA
tDAWH
tWW
tDAWL
WR
tWWR
tDDWH
tWDE
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD , DMAG
tSADADC
ADRCLK
(OUT)
Figure 14. Memory Write—Bus Master
REV. 0
–21–
tDDWR
ADSP-21060C/ADSP-21060LC
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asynchronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
Parameter
Timing Requirements:
tSSDATI Data Setup before CLKIN
tHSDATI Data Hold after CLKIN
tDAAK
ACK Delay after Address, MSx,
SW, BMS1, 2
tSACKC ACK Setup before CLKIN2
tHACK
ACK Hold after CLKIN
Switching Characteristics:
tDADRO Address, MSx, BMS, SW Delay
after CLKIN1
tHADRO Address, MSx, BMS, SW Hold
after CLKIN
tDPGC
PAGE Delay after CLKIN
tDRDO
RD High Delay after CLKIN
tDWRO
WR High Delay after CLKIN
tDRWL
RD/WR Low Delay after CLKIN
tSDDATO Data Delay after CLKIN
tDATTR Data Disable after CLKIN3
tDADCCK ADRCLK Delay after CLKIN
tADRCK ADRCLK Period
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
Min
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
ADSP-21060C
Max
3 + DT/8
3.5 – DT/8
Min
ADSP-21060LC
Max
3 + DT/8
3.5 – DT/8
14 + 7 DT/8 + W
6.5 + DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
ns
ns
14 + 7 DT/8 + W
ns
ns
ns
7 – DT/8
ns
6.5 + DT/4
–1 – DT/4
7 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
–1 – DT/8
9 + DT/8
–2 – DT/8
–3 – 3DT/16
8 + DT/4
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
Units
16 + DT/8
4 – DT/8
4 – 3DT/16
12.5 + DT/4
19.25 + 5DT/16
7 – DT/8
10 + DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of Wait states specified in WAIT register) × tCK.
NOTES
The falling edge of MSx, SW, BMS is referenced.
2
ACK Delay/Setup: User must meet t DAAK or tDSAK or synchronous specification t SACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
–22–
REV. 0
ADSP-21060C/ADSP-21060LC
CLKIN
tADRCK
tADRCKL
tADRCKH
tDADCCK
ADRCLK
tHADRO
tDAAK
tDADRO
ADDRESS
MSx, SW
tDPGC
PAGE
tHACK
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tHSDATI
tSSDATI
DATA
(IN)
WRITE CYCLE
tDWRO
tDRWL
WR
tDATTR
tSDDATO
DATA
(OUT)
Figure 15. Synchronous Read/Write—Bus Master
REV. 0
–23–
ADSP-21060C/ADSP-21060LC
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-2106x bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
Parameter
Min
Timing Requirements:
tSADRI
Address, SW Setup before CLKIN
tHADRI Address, SW Hold before CLKIN
tSRWLI
RD/WR Low Setup before CLKIN 1
tHRWLI RD/WR Low Hold after CLKIN
tRWHPI RD/WR Pulse High
tSDATWH Data Setup before WR High
tHDATWH Data Hold after WR High
Switching Characteristics:
tSDDATO Data Delay after CLKIN
tDATTR Data Disable after CLKIN2
tDACKAD ACK Delay after Address, SW3
tACKTR ACK Disable after CLKIN3
memory space). The bus master must meet these (bus slave)
timing requirements.
ADSP-21060C
Max
ADSP-21060LC
Min
Max
15 + DT/2
15 + DT/2
5 + DT/2
9.5 + 5DT/16
–3.5 – 5DT/16
3
5
1
19 + 5DT/16
7 – DT/8
9
6 – DT/8
0 – DT/8
–1 – DT/8
8 + 7DT/16
ns
ns
ns
ns
ns
ns
ns
19.25 + 5DT/16
7 – DT/8
9
6 – DT/8
ns
ns
ns
ns
5 + DT/2
8 + 7DT/16
9.5 + 5DT/16
–3.75 – 5DT/16
3
5
1
0 – DT/8
–1 – DT/8
Units
NOTES
1
tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)
= 4 + DT/8.
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3
tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tSRWLI
tHRWLI
tRWHPI
WR
tHDATWH
tSDATWH
DATA
(IN)
Figure 16. Synchronous Read/Write—Bus Slave
–24–
REV. 0
ADSP-21060C/ADSP-21060LC
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (BRx) or a host processor
(HBR, HBG).
Parameter
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
tSHBRI HBR Setup before CLKIN2
tHHBRI HBR Hold before CLKIN2
tSHBGI HBG Setup before CLKIN
tHHBGI HBG Hold before CLKIN High
BRx, CPA Setup before CLKIN3
tSBRI
BRx, CPA Hold before CLKIN High
tHBRI
tSRPBAI RPBA Setup before CLKIN
tHRPBAI RPBA Hold before CLKIN
Switching Characteristics:
tDHBGO HBG Delay after CLKIN
tHHBGO HBG Hold after CLKIN
BRx Delay after CLKIN
tDBRO
BRx Hold after CLKIN
tHBRO
tDCPAO CPA Low Delay after CLKIN
tTRCPA CPA Disable after CLKIN
tDRDYCS REDY (O/D) or (A/D) Low from CS
and HBR Low4
tTRDYHG REDY (O/D) Disable or REDY (A/D)
High from HBG4
tARDYTR REDY (A/D) Disable from CS or
HBR High4
Min
ADSP-21060C
Max
Min
ADSP-21060LC
Max
20+ 5DT/4
20 + 3DT/4
20+ 5DT/4
20 + 3DT/4
14 + 3DT/4
13 + DT/2
14 + 3DT/4
13 + DT/2
6 + DT/2
13 + DT/2
6 + DT/2
13 + DT/2
6 + DT/2
21 + 3DT/4
6 + DT/2
21 + 3DT/4
12 + 3DT/4
12 + 3DT/4
7 – DT/8
–2 – DT/8
7 – DT/8
7 – DT/8
8.5 – DT/8
4.5 – DT/8
11.0
ns
7 – DT/8
–2 – DT/8
8 – DT/8
4.5 – DT/8
–2 – DT/8
–2 – DT/8
8.5
40 + 23DT/16
40 + 23DT/16
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2 – DT/8
–2 – DT/8
Units
ns
10
ns
NOTES
1
For first asynchronous access after HBR and CS asserted, ADDR 31-0 must be a non-MMS value 1/2 t CK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the
ADSP-2106x SHARC User’s Manual, Second Edition.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
REV. 0
–25–
ADSP-21060C/ADSP-21060LC
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG
(OUT)
tHBRO
tDBRO
BRx
(OUT)
tTRCPA
tDCPAO
CPA (OUT)
(O/D)
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
tSRPBAI
tHRPBAI
RPBA
HBR AND CS
tTRDYHG
tDRDYCS
REDY (O/D)
tARDYTR
REDY (A/D)
tHBGRCSV
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 17. Multiprocessor Bus Request and Host Bus Request
–26–
REV. 0
ADSP-21060C/ADSP-21060LC
drive the RD and WR pins to access the ADSP-2106x’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Asynchronous Read/Write—Host to ADSP-2106x
Use these specifications for asynchronous host processor accesses
of an ADSP-2106x, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-2106x, the host can
Parameter
Min
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low before RD Low1
Address Hold/CS Hold Low after RD
tHADRDH
RD/WR High Width
tWRWH
RD High Delay after REDY (O/D) Disable
tDRDHRDY
RD High Delay after REDY (A/D) Disable
tDRDHRDY
0
0
6
0
0
Switching Characteristics:
Data Valid before REDY Disable from Low
tSDATRDY
REDY (O/D) or (A/D) Low Delay after RD Low
tDRDYRDL
REDY (O/D) or (A/D) Low Pulsewidth
tRDYPRD
for Read
Data Disable after RD High
tHDARWH
Write Cycle
Timing Requirements:
CS Low Setup before WR Low
tSCSWRL
CS Low Hold after WR High
tHCSWRH
Address Setup before WR High
tSADWRH
Address Hold after WR High
tHADWRH
WR Low Width
tWWRL
RD/WR High Width
tWRWH
WR High Delay after REDY
tDWRHRDY
(O/D) or (A/D) Disable
Data Setup before WR High
tSDATWH
Data Hold after WR High
tHDATWH
Switching Characteristics:
REDY (O/D) or (A/D) Low Delay
tDRDYWRL
after WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth
tRDYPWR
for Write
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
ADSP-21060C
Max
Min
ADSP-21060LC
Max
0
0
6
0
0
2
ns
ns
ns
ns
ns
2
10
Units
12.5
ns
ns
45 + 21DT/16
2
8
45 + 21DT/16
2
8.5
ns
ns
0
0
5
2
7
6
0
0
5
2
7
6
ns
ns
ns
ns
ns
ns
0
5
1
0
5
1
ns
ns
ns
10
15 + 7DT/16
1 + 7DT/16 8 + 7DT/16
12.5
ns
15 + 7DT/16
ns
1 + 7DT/16 8 + 7DT/16 ns
NOTE
1
Not required if RD and address are valid t HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
REV. 0
–27–
ADSP-21060C/ADSP-21060LC
READ CYCLE
ADDRESS/CS
tHADRDH
tSADRDL
tWRWH
RD
tHDARWH
DATA (OUT)
tSDATRDY
tDRDYRDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tSADWRH
tSCSWRL
tHADWRH
tHCSWRH
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tDWRHRDY
tDRDYWRL
tRDYPWR
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x
–28–
REV. 0
ADSP-21060C/ADSP-21060LC
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21060C
Max
Parameter
Min
Timing Requirements:
tSTSCK
SBTS Setup before CLKIN
tHTSCK
SBTS Hold before CLKIN
12 + DT/2
Min
ADSP-21060LC
Max
12 + DT/2
6 + DT/2
Switching Characteristics:
tMIENA
Address/Select Enable after CLKIN
tMIENS
Strobes Enable after CLKIN1
tMIENHG HBG Enable after CLKIN
tMITRA
Address/Select Disable after CLKIN
tMITRS
Strobes Disable after CLKIN 1
tMITRHG HBG Disable after CLKIN
tDATEN
Data Enable after CLKIN 2
tDATTR
Data Disable after CLKIN2
tACKEN
ACK Enable after CLKIN 2
tACKTR
ACK Disable after CLKIN2
tADCEN
ADRCLK Enable after CLKIN
tADCTR
ADRCLK Disable after CLKIN
tMTRHBG Memory Interface Disable before
HBG Low3
tMENHBG Memory Interface Enable after
HBG High3
6 + DT/2
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
0 – DT/4
1.5 – DT/4
2.0 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0.25 – DT/4
1.5 – DT/4
2.0 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
7 – DT/8
6 – DT/8
8 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0 + DT/8
0 + DT/8
ns
19 + DT
19 + DT
ns
NOTES
1
Strobes = RD, WR, SW, PAGE, DMAG.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tADCEN
tADCTR
ADRCLK
Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 19b. Three-State Timing (Host Transition Cycle)
REV. 0
Units
–29–
ADSP-21060C/ADSP-21060LC
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,
ACK, and DMAG signals. For Paced Master mode, the data
Parameter
Timing Requirements:
tSDRLC
DMARx Low Setup before CLKIN1
DMARx High Setup before CLKIN1
tSDRHC
DMARx Width Low
tWDR
(Nonsynchronous)
tSDATDGL Data Setup after DMAGx Low2
tHDATIDG Data Hold after DMAGx High
tDATDRH Data Valid after DMARx High2
tDMARLL DMARx Low Edge to Low Edge
tDMARH DMARx Width High
Switching Characteristics:
DMAGx Low Delay after CLKIN
tDDGL
DMAGx High Width
tWDGH
DMAGx Low Width
tWDGL
DMAGx High Delay after CLKIN
tHDGC
tVDATDGH Data Valid before DMAGx High 3
tDATRDGH Data Disable after DMAGx High4
WR Low before DMAGx Low
tDGWRL
tDGWRH DMAGx Low before WR High
WR High before DMAGx High
tDGWRR
RD Low before DMAGx Low
tDGRDL
RD Low before DMAGx High
tDRDGH
RD High before DMAGx High
tDGRDR
DMAGx High to WR, RD, DMAGx
tDGWR
Low
Address/Select Valid to DMAGx High
tDADGH
Address/Select Hold after DMAGx
tDDGHA
High
Min
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR31-0, RD, WR,
MS3-0, SW, PAGE, DATA47-0 , and ACK also apply.
ADSP-21060C
Max
5
5
Min
ADSP-21060LC
Max
5
5
6
ns
ns
6
10 + 5DT/8
2
10 + 5DT/8
2
16 + 7DT/8
23 + 7DT/8
6
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
16 + 7DT/8
23 + 7DT/8
6
15 + DT/4
6 – DT/8
7
2
3 + DT/16
2
3
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
Units
15 + DT/4
6 – DT/8
7
2
3 + DT/16
2
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 + 3DT/8 + HI
17 + DT
5 + 3DT/8 + HI
17 + DT
ns
ns
–0.5
–0.5
ns
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
Only required for recognition in the current cycle.
2
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven t DATDRH after DMARx is brought high.
3
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t VDATDGH = 8 + 9DT/16 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
1
–30–
REV. 0
ADSP-21060C/ADSP-21060LC
CLKIN
tSDRLC
tDMARLL
tSDRHC
tWDR
tDMARH
DMARx
tHDGC
tDDGL
tWDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tVDATDGH
tDATRDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
WR
tDGWRL
tDGWRH
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
RD
tDGRDR
tDGRDL
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
tDRDGH
tDADGH
ADDRESS
MSx, SW
* MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER
TIMING SPECIFICATIONS FOR ADDR31-0, RD, WR, SW, MS3-0 AND ACK ALSO APPLY HERE.
Figure 20. DMA Handshake Timing
REV. 0
–31–
tDGWRR
tDDGHA
ADSP-21060C/ADSP-21060LC
Link Ports: 1 ⴛ CLK Speed Operation
Parameter
Min
Receive
Timing Requirements:
tSLDCL
Data Setup before LCLK Low
tHLDCL
Data Hold after LCLK Low
tLCLKIW
LCLK Period (1 × Operation)
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
3.5
3
tCK
6
5
Switching Characteristics:
tDLAHC
LACK High Delay after CLKIN High
tDLALC
LACK Low Delay after LCLK High1
tENDLK
LACK Enable from CLKIN
tTDLK
LACK Disable from CLKIN
Transmit
Timing Requirements:
tSLACH
LACK Setup before LCLK High
tHLACH
LACK Hold after LCLK High
Switching Characteristics:
tDLCLK
LCLK Delay after CLKIN (1 × Operation)
tDLDCH
Data Delay after LCLK High
tHLDCH
Data Hold after LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay after LACK High
tENDLK
LDAT, LCLK Enable after CLKIN
tTDLK
LDAT, LCLK Disable after CLKIN
Link Port Service Request Interrupts: 1 × and
2 × Speed Operations
Timing Requirements:
tSLCK
LACK/LCLK Setup before CLKIN Low 2
tHLCK
LACK/LCLK Hold after CLKIN Low 2
ADSP-21060C
Max
Min
ADSP-21060LC
Max
3
3
tCK
6
5
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
18 + DT/2
–3
5 + DT/2
20 + DT/2
18
–7
ns
ns
ns
ns
ns
29.0 + DT/2
13
20 + DT/2
20
–7
15.5
3
–3
(tCK/2) – 2
(tCK/2) – 2
(tCK/2) + 8.5
5 + DT/2
10
2
Units
ns
ns
ns
ns
ns
ns
16.75
2.5
–3
(tCK/2) + 2
(tCK/2) – 1
(tCK/2) + 2
(tCK/2) – 2.25
(3 × tCK/2) + 17 (tCK/2) + 8.0
5 + DT/2
20 + DT/2
10
2
ns
ns
ns
(tCK/2) + 2.25
ns
(tCK/2) + 1.0
ns
(3 × tCK/2) + 18.5 ns
ns
20 + DT/2
ns
ns
ns
NOTES
1
LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2
Only required for interrupt recognition in the current cycle.
–32–
REV. 0
ADSP-21060C/ADSP-21060LC
Link Ports: 2 ⴛ CLK Speed Operation
Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can
be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in
LDATA relative to LCLK, (setup skew = tLCLKTWH min – t DLDCH – tSLDCL). Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA, (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly from 2 × speed
specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew
times shown below are calculated to include only one tester guardband.
ADSP-21060C Setup Skew
ADSP-21060C Hold Skew
= 0.62 ns max (If port 2 is transmitter, setup skew is 0.39)
= 2.40 ns max
ADSP-21060LC Setup Skew = 1.23 ns max
ADSP-21060LC Hold Skew = 2.76 ns max
ADSP-21060C
Max
Parameter
Min
Receive
Timing Requirements:
tSLDCL
Data Setup before LCLK Low
tHLDCL
Data Hold after LCLK Low
tLCLKIW
LCLK Period (2 × Operation)
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
2.5
2.25
tCK/2
4.5
4.25
Switching Characteristics:
tDLAHC
LACK High Delay after CLKIN High
tDLALC
LACK Low Delay after LCLK High1
18 + DT/2
6
Transmit
Timing Requirements:
tSLACH
LACK Setup before LCLK High
tHLACH
LACK Hold after LCLK High
19
–6.75
Switching Characteristics:
tDLCLK
LCLK Delay after CLKIN
tDLDCH
Data Delay after LCLK High
tHLDCH
Data Hold after LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay after LACK High
28.5 + DT/2
16.5
ADSP-21060LC
Min
Max
Units
2.25
2.25
tCK/2
5.25
4.5
ns
ns
ns
ns
ns
18 + DT/2
6
29.5 + DT/2
18.5
19
–6.5
8
2.5
–2.0
(tCK/4) – 1
(tCK/4) + 1.5
(tCK/4) – 1.5 (tCK/4) + 1
(tCK/4) + 9
(3 * tCK/4) + 16.5
ns
ns
ns
ns
8
2.25
–2.0
(tCK/4) – 0.75 (tCK/4) + 1.5
(tCK/4) – 1.5 (tCK/4) + 1
(tCK/4) + 9
(3 * tCK/4) + 16.5
ns
ns
ns
ns
ns
ns
NOTE
1
LACK will go low with t DLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
REV. 0
–33–
ADSP-21060C/ADSP-21060LC
TRANSMIT
CLKIN
tDLCLK
tLCLKTWH
tLCLKTWL
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK 1x
OR
LCLK 2x
LCLK INACTIVE
(HIGH)
tDLDCH
tHLDCH
LDAT(3:0)
OUT
tDLACLK
tSLACH
tHLACH
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK 1x
OR
LCLK 2x
tHLDCL
tSLDCL
LDAT(3:0)
IN
tDLALC
tDLAHC
LACK (OUT)
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
t TDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tSLCK
t HLCK
LCLK
LACK
Figure 21. Link Ports
–34–
REV. 0
ADSP-21060C/ADSP-21060LC
Serial Ports
Parameter
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup before TCLK/RCLK 1
TFS/RFS Hold after TCLK/RCLK 1, 2
tHFSE
Receive Data Setup before RCLK 1
tSDRE
tHDRE
Receive Data Hold after RCLK 1
TCLK/RCLK Width
tSCLKW
tSCLK
TCLK/RCLK Period
Internal Clock
Timing Requirements:
TFS Setup before TCLK1; RFS Setup
tSFSI
before RCLK1
tHFSI
TFS/RFS Hold after TCLK/RCLK 1, 2
Receive Data Setup before RCLK 1
tSDRI
Receive Data Hold after RCLK 1
tHDRI
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay after RCLK (Internally
Generated RFS) 3
RFS Hold after RCLK (Internally
tHOFSE
Generated RFS) 3
External Clock
Switching Characteristics:
TFS Delay after TCLK (Internally
tDFSE
Generated TFS)3
tHOFSE
TFS Hold after TCLK (Internally
Generated TFS)3
Transmit Data Delay after TCLK 3
tDDTE
tHODTE
Transmit Data Hold after TCLK3
Internal Clock
Switching Characteristics:
TFS Delay after TCLK (Internally
tDFSI
Generated TFS)3
tHOFSI
TFS Hold after TCLK (Internally
Generated TFS)3
tDDTI
Transmit Data Delay after TCLK 3
Transmit Data Hold after TCLK3
tHDTI
TCLK/RCLK Width
tSCLKIW
Enable and Three-State
Switching Characteristics:
tDDTEN
Data Enable from External TCLK 3
Data Disable from External TCLK 3
tDDTTE
Data Enable from Internal TCLK 3
tDDTIN
tDDTTI
Data Disable from Internal TCLK3
TCLK/RCLK Delay from CLKIN
tDCLK
tDPTR
SPORT Disable after CLKIN
Gated SCLK with External TFS
(Mesh Multiprocessing)4
Timing Requirements:
TFS Setup before CLKIN
tSTFSCK
tHTFSCK
TFS Hold after CLKIN
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 05
tDDTENFS Data Enable from late FS or MCE = 1,
MFD = 05
Min
ADSP-21060C
Max
Min
ADSP-21060LC
Max
Units
3.5
4
1.5
4
9.5
tCK
3.5
4
1.5
4
9.5
tCK
ns
ns
ns
ns
ns
ns
8
1
3
3
8
1
3
3
ns
ns
ns
ns
13
3
13
3
13
3
ns
13
ns
16
ns
ns
ns
4.5
ns
3
16
5
5
4.5
–1.5
–1.5
7.5
0
(tSCLK/2) – 2
(tSCLK /2) + 2
3.5
7.5
0
(tSCLK /2) – 2.5
(tSCLK /2) + 2.5
4.0
10.5
0
10.5
0
3
22 + 3DT/8
17
5
tCK/2
3
22 + 3DT/8
17
5
tCK/2
12
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.8
3.5
ns
ns
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync setup
and hold, 2) data delay & data setup and hold, and 3) SCLK width.
REV. 0
–35–
ADSP-21060C/ADSP-21060LC
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3
Referenced to drive edge.
4
Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
5
MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tSFSI
tDFSE
tHOFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tSFSI
tDFSE
tHOFSE
tHFSI
TFS
tSFSE
tHFSE
TFS
tHDTI
tDDTI
tHDTE
tDDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
TCLK / RCLK
TCLK (EXT)
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tDPTR
TCLK, RCLK
TFS, RFS, DT
SPORT DISABLE DELAY
FROM INSTRUCTION
tSTFSCK
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
tHTFSCK
TFS (EXT)
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 22. Serial Ports
–36–
REV. 0
ADSP-21060C/ADSP-21060LC
EXTERNAL RFS with MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
tHOFSE/I (SEE NOTE 2)
tSFSE/I
RFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
tHOFSE/I (SEE NOTE 2)
tSFSE/I
TFS
tDDTE/I
tDDTENFS
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 23. External Late Frame Sync
REV. 0
–37–
ADSP-21060C/ADSP-21060LC
JTAG Test Access Port and Emulation
Parameter
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
Units
Timing Requirements:
tTCK
TCK Period
TDI, TMS Setup before TCK High
tSTAP
TDI, TMS Hold after TCK High
tHTAP
System Inputs Setup before TCK Low1
tSSYS
System Inputs Hold after TCK Low1
tHSYS
TRST Pulsewidth
tTRSTW
tCK
5
6
7
18
4tCK
tCK
5
6
7
18.5
4tCK
ns
ns
ns
ns
ns
ns
Switching Characteristics:
TDO Delay from TCK Low
tDTDO
tDSYS
System Outputs Delay after TCK Low2
13
18.5
13
18.5
ns
ns
NOTES
1
System Inputs = DATA 47-0, ADDR 31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, ID 2-0, RPBA, IRQ 2-0, FLAG 3-0, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA 47-0, ADDR 31-0, MS 3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR 6-1, CPA, FLAG3-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. IEEE 11499.1 JTAG Test Access Port
–38–
REV. 0
ADSP-21060C/ADSP-21060LC
Table III. External Power Calculations (3.3 V Device)
OUTPUT DRIVE CURRENTS
Figure 28 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
POWER DISSIPATION
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way:
PINT = IDDIN × VDD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (VDD)
and is calculated by:
Pin
Type
# of
Pins
%
Switching ⴛ C
Address
MS0
WR
Data
ADDRCLK
15
1
1
32
1
50
0
–
50
–
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
of 1/(4tCK), with 50% of the pins switching
–The instruction cycle rate is 40 MHz (tCK = 25 ns).
The PEXT equation is calculated for each class of pins that can
drive:
Table II. External Power Calculations (5 V Device)
Address
MS0
WR
Data
ADDRCLK
15
1
1
32
1
50
0
–
50
–
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
= 0.037 W
= 0.000 W
= 0.010 W
= 0.026 W
= 0.001 W
PTOTAL = PEXT + (IDDIN2 × 5.0 V )
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by
the following equation:
Estimate PEXT with the following assumptions:
%
Switching ⴛ C
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
t DECAY =
# of
Pins
× 10 MHz
× 10 MHz
× 20 MHz
× 10 MHz
× 20 MHz
PEXT = 0.074 W
Example:
Pin
Type
ⴛ VDD2 = PEXT
TEST CONDITIONS
Output Disable Time
PEXT = O × C × VDD2 × f
ⴛf
ⴛ VDD2 = PEXT
× 10 MHz
× 10 MHz
× 20 MHz
× 10 MHz
× 20 MHz
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
= 0.084 W
= 0.000 W
= 0.022 W
= 0.059 W
= 0.002 W
C L ∆V
IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 25. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 25). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
PEXT = 0.167 W
REV. 0
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
ⴛf
–39–
ADSP-21060C/ADSP-21060LC
IOL
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
TO
OUTPUT
PIN
+1.5V
50pF
IOH
REFERENCE
SIGNAL
Figure 26. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
tMEASURED
tDIS
tENA
1.5V
VOH (MEASURED)
VOL (MEASURED)
VOH (MEASURED) – DV
2.0V
VOL (MEASURED) + DV
1.0V
tDECAY
OUTPUT STOPS
DRIVING
VOH (MEASURED)
1.5V
Figure 27. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
VOL (MEASURED)
Capacitive Loading
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 25. Output Enable/Disable
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 26). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 29–30,
33–34 show how output rise time varies with capacitance. Figures 31, 35 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 29, 30 and 31 may not be linear outside the ranges
shown.
–40–
REV. 0
ADSP-21060C/ADSP-21060LC
5
75
50
5.25V, –408C
5.0V, +258C
0
4.75V, +1008C
–25
4.75V, +1008C
–50
5.0V, +258C
–75
4
OUTPUT DELAY OR HOLD – ns
SOURCE CURRENT – mA
25
5.25V, –408C
–100
3
Y = 0.03X –1.45
2
1
NOMINAL
–125
–15
00
–1
0.75
1.50
2.25
3.00
3.75
SOURCE VOLTAGE – V
4.50
25
5.25
Figure 28. ADSP-2106x Typical Drive Currents (VDD = 5 V)
50
175
200
Figure 31. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (V DD = 5 V)
16.0
120
100
14.0
VOH
80
12.0
SOURCE CURRENT – mA
RISE AND FALL TIMES – ns
(0.5V – 4.5V, 10% – 90%)
75
100
125
150
LOAD CAPACITANCE – pF
RISE TIME
10.0
Y = 0.005X + 3.7
8.0
FALL TIME
6.0
4.0
3.6V, –40°C
60
40
20
3.0V, +100°C
0
3.0V, +100°C
3.3V, +25°C
–20
3.6V, –40°C
–40
–60
VOL
–80
2.0
3.3V, +25°C
Y = 0.0031X + 1.1
–100
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
–120
200
Figure 29. Typical Output Rise Time (10%–90% V DD) vs.
Load Capacitance (VDD = 5 V)
RISE AND FALL TIMES – ns (10% – 90%)
RISE AND FALL TIMES – ns (0.8V – 2.0V)
1
1.5
2
2.5
SOURCE VOLTAGE – V
3.5
3
18
3.0
2.5
RISE TIME
2.0
Y = 0.009X + 1.1
1.5
FALL TIME
1.0
Y = 0.005X + 0.6
0.5
16
14
Y = 0.0796X + 1.17
12
10
RISE TIME
8
6
Y = 0.0467X + 0.55
4
FALL TIME
2
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
0
200
20
40
60
80
100
120
140
160
180
200
LOAD CAPACITANCE – pF
Figure 33. Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V)
Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 5 V)
REV. 0
0.5
Figure 32. ADSP-2106x Typical Drive Currents (VDD = 3.3 V)
3.5
0
0
–41–
ADSP-21060C/ADSP-21060LC
5
8
OUTPUT DELAY OR HOLD – ns
RISE AND FALL TIMES – ns (0.8V – 2.0V)
9
7
Y = 0.0391X + 0.36
6
5
RISE TIME
4
Y = 0.0305X + 0.24
3
FALL TIME
2
4
Y = 0.0329X –1.65
3
2
1
NOMINAL
1
0
0
20
40
60
80
100
120
140
160
180
–1
200
25
50
LOAD CAPACITANCE – pF
175
200
Figure 35. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (V DD = 3.3 V)
Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs.
Load Capacitance (VDD = 3.3 V)
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-2106x is packaged in a 240-lead thermally enhanced
ceramic QFP (CQFP). There are two package versions, one
with a copper/tungsten heat slug on top of the package (CZ) for
air cooling, and one with the heat slug on the bottom (CW) for
cooling through the board. The ADSP-2106x is specified for a
case temperature (TCASE). To ensure that the T CASE data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. A heatsink should be attached with a thermal adhesive.
TCASE = TAMB + (PD × θCA )
TCASE = Case temperature (measured on the heat slug surface)
PD =
Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is
shown under Power Dissipation).
θCA =
Value from the following table.
Airflow
(Linear Ft./Min.)
θCA (°C/W)
75
100
125
150
LOAD CAPACITANCE – pF
0
100
200
400
600
21060CW/LCW
19.5
16
14
12
10
21060CZ/LCZ
20
16
14
11.5
9.5
NOTES
This represents thermal resistance at total power of 5 W. With air flow, no variance is seen in θ CA of 5 W.
θCA at 0 LFM varies with power
21060CW/LCW: at 2 W, θCA = 23°C/W; at 3 W, θCA = 21.5°C/W.
21060CZ/LCZ: at 2 W, θCA = 24°C/W; at 3 W, θCA = 21.5°C/W.
θJC= 0.24°C/ W.
–42–
REV. 0
ADSP-21060C/ADSP-21060LC
240-LEAD METRIC CQFP PIN CONFIGURATIONS
HEAT SLUG UP VERSION (CZ)
240
181
1
180
TOP VIEW
PINS DOWN
HEAT SLUG
60
121
61
120
THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN
HEAT SLUG ON ITS TOP SURFACE. HEAT SLUG AND
PACKAGE LID ARE ELECTRICALLY ISOLATED.
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TDI
TRST
VDD
TDO
TIMEXP
EMU
ICSA
FLAG3
FLAG2
FLAG1
FLAG0
GND
ADDR0
ADDR1
VDD
ADDR2
ADDR3
ADDR4
GND
ADDR5
ADDR6
ADDR7
VDD
ADDR8
ADDR9
ADDR10
GND
ADDR11
ADDR12
ADDR13
VDD
ADDR14
ADDR15
GND
ADDR16
ADDR17
ADDR18
VDD
VDD
ADDR19
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ADDR20
ADDR21
GND
ADDR22
ADDR23
ADDR24
VDD
GND
VDD
ADDR25
ADDR26
ADDR27
GND
MS3
MS2
MS1
MS0
SW
BMS
ADDR28
GND
VDD
VDD
ADDR29
ADDR30
ADDR31
GND
SBTS
DMAR2
DMAR1
HBR
DT1
TCLK1
TFS1
DR1
RCLK1
RFS1
GND
CPA
DT0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
TCLK0
TFS0
DR0
RCLK0
RFS0
VDD
VDD
GND
ADRCLK
REDY
HBG
CS
RD
WR
GND
VDD
GND
CLKIN
ACK
DMAG2
DMAG1
PAGE
VDD
BR6
BR5
BR4
BR3
BR2
BR1
GND
VDD
GND
DATA47
DATA46
DATA45
VDD
DATA44
DATA43
DATA42
GND
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
DATA41
DATA40
DATA39
VDD
DATA38
DATA37
DATA36
GND
NC
DATA35
DATA34
DATA33
VDD
VDD
GND
DATA32
DATA31
DATA30
GND
DATA29
DATA28
DATA27
VDD
VDD
DATA26
DATA25
DATA24
GND
DATA23
DATA22
DATA21
VDD
DATA20
DATA19
DATA18
GND
DATA17
DATA16
DATA15
VDD
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DATA14
DATA13
DATA12
GND
DATA11
DATA10
DATA9
VDD
DATA8
DATA7
DATA6
GND
DATA5
DATA4
DATA3
VDD
DATA2
DATA1
DATA0
GND
GND
L0DAT3
L0DAT2
L0DAT1
L0DAT0
L0CLK
L0ACK
VDD
L1DAT3
L1DAT2
L1DAT1
L1DAT0
L1CLK
L1ACK
GND
GND
VDD
L2DAT3
L2DAT2
L2DAT1
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
REV. 0
–43–
L2DAT0
L2CLK
L2ACK
NC
VDD
L3DAT3
L3DAT2
L3DAT1
L3DAT0
L3CLK
L3ACK
GND
L4DAT3
L4DAT2
L4DAT1
L4DAT0
L4CLK
L4ACK
VDD
GND
VDD
L5DAT3
L5DAT2
L5DAT1
L5DAT0
L5CLK
L5ACK
GND
ID2
ID1
ID0
LBOOT
RPBA
RESET
EBOOT
IRQ2
IRQ1
IRQ0
TCK
TMS
ADSP-21060C/ADSP-21060LC
240-LEAD METRIC CQFP PIN CONFIGURATIONS
HEAT SLUG DOWN VERSION (CW)
240
181
1
180
TOP VIEW
PINS DOWN
HEAT SLUG
60
121
61
120
THE 240–LEAD PACKAGE CONTAINS A COPPER/TUNGSTEN
HEAT SLUG ON ITS BOTTOM SURFACE. HEAT SLUG AND
PACKAGE LID ARE ELECTRICALLY ISOLATED.
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
DATA0
DATA1
DATA2
VDD
DATA3
DATA4
DATA5
GND
DATA6
DATA7
DATA8
VDD
DATA9
DATA10
DATA11
GND
DATA12
DATA13
DATA14
VDD
DATA15
DATA16
DATA17
GND
DATA18
DATA19
DATA20
VDD
DATA21
DATA22
DATA23
GND
DATA24
DATA25
DATA26
VDD
VDD
DATA27
DATA28
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DATA29
GND
DATA30
DATA31
DATA32
GND
VDD
VDD
DATA33
DATA34
DATA35
NC
GND
DATA36
DATA37
DATA38
VDD
DATA39
DATA40
DATA41
GND
DATA42
DATA43
DATA44
VDD
DATA45
DATA46
DATA47
GND
VDD
GND
BR1
BR2
BR3
BR4
BR5
BR6
VDD
PAGE
DMAG1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DMAG2
ACK
CLKIN
GND
VDD
GND
WR
RD
CS
HBG
REDY
ADRCLK
GND
VDD
VDD
RFS0
RCLK0
DR0
TFS0
TCLK0
DT0
CPA
GND
RFS1
RCLK1
DR1
TFS1
TCLK1
DT1
HBR
DMAR1
DMAR2
SBTS
GND
ADDR31
ADDR30
ADDR29
VDD
VDD
GND
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
ADDR28
BMS
SW
MS0
MS1
MS2
MS3
GND
ADDR27
ADDR26
ADDR25
VDD
GND
VDD
ADDR24
ADDR23
ADDR22
GND
ADDR21
ADDR20
ADDR19
VDD
VDD
ADDR18
ADDR17
ADDR16
GND
ADDR15
ADDR14
VDD
ADDR13
ADDR12
ADDR11
GND
ADDR10
ADDR9
ADDR8
VDD
ADDR7
ADDR6
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
ADDR5
GND
ADDR4
ADDR3
ADDR2
VDD
ADDR1
ADDR0
GND
FLAG0
FLAG1
FLAG2
FLAG3
ICSA
EMU
TIMEXP
TDO
VDD
TRST
TDI
TMS
TCK
IRQ0
IRQ1
IRQ2
EBOOT
RESET
RPBA
LBOOT
ID0
ID1
ID2
GND
L5ACK
L5CLK
L5DAT0
L5DAT1
L5DAT2
L5DAT3
VDD
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
–44–
GND
VDD
L4ACK
L4CLK
L4DAT0
L4DAT1
L4DAT2
L4DAT3
GND
L3ACK
L3CLK
L3DAT0
L3DAT1
L3DAT2
L3DAT3
VDD
NC
L2ACK
L2CLK
L2DAT0
L2DAT1
L2DAT2
L2DAT3
VDD
GND
GND
L1ACK
L1CLK
L1DAT0
L1DAT1
L1DAT2
L1DAT3
VDD
L0ACK
L0CLK
L0DAT0
L0DAT1
L0DAT2
L0DAT3
GND
REV. 0
ADSP-21060C/ADSP-21060LC
OUTLINE DIMENSIONS
Dimensions shown in inches and (millimeters).
240-Lead CQFP with Heat Slug Up and Formed Leads (QS-240)
1.433 (36.40)
1.418 (36.025) SQ
1.404 (35.65)
PIN 1
ID
1.270 (32.25)
1.260 (32.00) SQ
1.250 (31.75)
240
1.104 (28.05)
1.094 (27.80) SQ
1.085 (27.55)
181
180
1
181
240
180
1
SEAL RING
TOP VIEW
PINS DOWN
LID
BOTTOM VIEW
HEAT SLUG
60
121
61
121
120
0.758 (19.25)
0.748 (19.00) SQ
0.738 (18.75)
0.837 (21.25)
0.827 (21.00) SQ
0.817 (20.75)
REV. 0
0.146 (3.70)
0.132 (3.35)
0.118 (3.00)
0.009 (0.23)
0.008 (0.20)
0.007 (0.17)
0.020 (0.50)
BSC
0.024 (0.60)
0.008 (0.20)
–45–
-C- SEATING PLANE
0.004 (0.10) C
D
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
61
NOTES:
1. CONTROLLING DIMENSIONS ARE IN INCHES
2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)
3. LEAD SWEEP = 0.005 (0.13) MAX
0.154 (3.90) MAX
78
–38
60
120
ADSP-21060C/ADSP-21060LC
OUTLINE DIMENSIONS
Dimensions shown in inches and (millimeters).
240-Lead Metric CQFP with Heat Slug Up and Unformed Leads (QS-240)
2.953 (75.00) SQ
0.665 (16.88)
8 3 0.650 (16.50)
0.635 (16.12)
1.161 (29.50) BSC
61
120
121
60
61
120
60
121
SEAL RING
23
2.594
(65.90)
TOP VIEW
LID
BOTTOM VIEW
HEAT SLUG
180
1
181
240
1
INDEX 1
GOLD
PLATED
INDEX 2 240
2.00 (0.079)
NO GOLD
180
181
NONCONDUCTIVE
CERAMIC TIE BAR
2.972 (75.50) SQ
–46–
REV. 0
ADSP-21060C/ADSP-21060LC
OUTLINE DIMENSIONS
Dimensions shown in inches and (millimeters).
240-Lead Metric CQFP with Heat Slug Down and Formed Leads (QS-240A)
PIN 1
ID
1.433 (36.40)
1.418 (36.025) SQ
1.404 (35.65)
0.837 (21.25)
0.827 (21.00) SQ
0.817 (20.75)
1.270 (32.25)
1.260 (32.00) SQ
1.250 (31.75)
0.758 (19.25)
0.748 (19.00) SQ
0.738 (18.75)
240
181
180
1
SEAL RING
181
240
180
1
LID
TOP VIEW
PINS DOWN
BOTTOM VIEW
HEAT SLUG
60
121
61
121
120
60
120
61
1.104 (28.05)
1.094 (27.80) SQ
1.085 (27.55)
0.144 (3.65)
0.130 (3.30)
0.116 (2.95)
78
–38
REV. 0
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
0.009 (0.23)
0.008 (0.20)
0.007 (0.17)
0.020 (0.50)
BSC
0.020 (0.50)
0.004 (0.10)
–47–
-C- SEATING PLANE
0.004 (0.10) C
D
0.154 (3.92) MAX
NOTES:
1. CONTROLLING DIMENSIONS ARE IN INCHES
2. LEAD FINISH = GOLD PLATE (60 MICROINCHES)
3. LEAD SWEEP = 0.005 (0.13) MAX
ADSP-21060C/ADSP-21060LC
OUTLINE DIMENSIONS
Dimensions shown in inches and (millimeters).
240-Lead Metric CQFP with Heat Slug Down and Unformed Leads (QS-240A)
0.665 (16.88)
8 3 0.650 (16.50)
0.635 (16.12)
1.161 (29.50) BSC
120
120
60
60
SEAL RING
23
2.594
(65.90)
61
61
121
C3350–2–3/99
2.953 (75.00) SQ
121
LID
TOP VIEW
BOTTOM VIEW
HEAT SLUG
1
180
181
240
1
INDEX 2
2.00 (0.079) 240
NO GOLD
INDEX 1
GOLD
PLATED
180
181
NONCONDUCTIVE
CERAMIC TIE BAR
2.972 (75.50) SQ
ORDERING GUIDE
Case Temperature Range
Heat Slug Orientation
Instruction Rate
Operating Voltage
ADSP-21060CZ-133
ADSP-21060CZ-160
ADSP-21060CW-133
ADSP-21060CW-160
ADSP-21060LCW-133
ADSP-21060LCW-160
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
–40°C to +100°C
Heat Slug Up
Heat Slug Up
Heat Slug Down
Heat Slug Down
Heat Slug Down
Heat Slug Down
33 MHz
40 MHz
33 MHz
40 MHz
33 MHz
40 MHz
5V
5V
5V
5V
3.3 V
3.3 V
–48–
PRINTED IN U.S.A.
Part Number
REV. 0
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