advertisement
Intel® PXA26x Processor Family
Electrical, Mechanical, and Thermal Specification
Data Sheet
Product Features
■
■
■
■
■
■
■
■
High-Performance Processor
—Intel® XScale™ Microarchitecture
—7 stage pipeline
—32 KB instruction cache
—32 KB data cache
—2 KB mini-data cache
—Extensive data buffering
Intel StrataFlash® Memory in some versions
Rich Serial Peripheral Set
—AC97 audio port
—I
2
S audio port
—USB client controller
—Four high speed UARTs (one with hardware flow control)
—FIR and SIR infrared comm ports
Hardware Debug Features
—IEEE JTAG interface with boundary scan
Hardware Performance Monitoring features with on-chip trace buffer
Real-Time Clock
Operating System Timers
USB Client Controller with differential or single-ended interface support
■
■
■
■
Low Power
—Low voltage core supply
—Low power sleep mode
High Performance Memory Controller
—Four banks of SDRAM - up to 100 MHz
( 2.5 V, and 3.3 V I/O interface)
—Six static chip selects
—Support for PCMCIA and compact
Flash
—Companion chip interface
Flexible Clocking
—CPU clock rated to 300 MHz (PXA262) or 400 MHz (PXA260, PXA261 and
PXA263)
—Flexible memory clock ratios
—Frequency change modes
—Functional clock gating
Additional peripherals for system connectivity
—SD card / MMC controller (with SPI mode support)
—Three SSP controllers
—I
2
C controller
—Pulse width modulators (PWMs)
—Most peripheral pins double as GPIOs.
April 2003
Reference Number: 278640-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® PXA26x Processor Family EMTS may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2003
*Other names and brands may be claimed as the property of others.
ii
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Contents
Contents
3.1
Package Load Specification .......................................................................3-3
3.3
Package Mass Specifications.....................................................................3-4
Absolute Maximum Ratings........................................................................5-1
Power Consumption Specifications............................................................5-2
5.4
DC Specifications .......................................................................................5-4
32.768-KHz Oscillator Specifications ............................................5-5
3.6864-MHz Oscillator Specifications............................................5-6
Reset and Power Manager AC Timing Specifications................................6-2
Power On Timing...........................................................................6-2
Hardware Reset Timing.................................................................6-3
Watchdog Reset Timing ................................................................6-4
GPIO Reset Timing .......................................................................6-4
Sleep Mode Timing .......................................................................6-5
Memory Bus and PCMCIA AC Specifications ............................................6-6
JTAG Boundary Scan AC Timing Specifications........................................6-8
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
iii
Contents
Figures
3-1 PXA26x Processor Family Package (top view)..................................................3-1
3-2 PXA26x Processor Family Package (bottom view) ............................................3-2
3-3 PXA26x Processor Family Package (side view) ................................................3-3
4-1 PXA26x Processor Family TF-BGA Ball Map: Top View ...................................4-1
Tables
3-1 Package Dynamic and Static Load Specifications .............................................3-3
3-2 Package Mass....................................................................................................3-4
4-1 Signal Descriptions for the PXA26x Processor Family ......................................4-2
4-2 PXA26x Processor Family Pin Out - Ballpad Number Order ...........................4-10
4-4 Power Supply Pin Summary ............................................................................4-19
5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2
5-3 Power Consumption Specifications....................................................................5-3
5-4 Standard Input, Output, and I/O Pin DC Operating Conditions..........................5-4
5-6 32.768-KHz Oscillator Specifications .................................................................5-5
5-8 3.6864-MHz Oscillator Specifications ................................................................5-6
6-1 Standard Input, Output, and I/O Pin AC Operating Conditions ..........................6-1
6-6 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications...................6-6
6-7 Variable Latency I/O Interface AC Specifications ..............................................6-7
6-8 Card Interface (PCMCIA or Compact Flash) AC Specifications ........................6-7
6-9 Synchronous Memory Interface AC Specifications ............................................6-8
iv
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Revision History
Date
10/25/02
04/04/03
Revision
1.0
2.0
First Release
Various minor revs to EMTS
Description
Contents
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
v
Contents
vi
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Introduction
1
1.1
This document is the electrical, mechanical, and thermal specification data sheet for the Intel®
PXA26x processor family. This datasheet contains a functional overview, mechanical data, package signal locations, targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance are published in the Intel® PXA26x Processor Family Developer's Manual, 278638.
The PXA26x processor family consists of four devices. Three of these devices integrate the Intel®
XScale™ Microarchitecture, peripherals, and Intel StrataFlash® memory. The processor is available in a single 13x13 mm, 294-pin TF-BGA package. The PXA26x processor family ordering options are as follows:
•
PXA260 processor with no Intel StrataFlash® memory
•
PXA261 processor with 128 megabits of Intel StrataFlash® memory
•
PXA262 processor with 256 megabits of Intel StrataFlash® memory in a 16-bit configuration
•
PXA263 processor with 256 megabits of Intel StrataFlash® memory in a 32-bit configuration
Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in hexadecimal and 0b1101011 in binary.
1.2
References
Material and concepts available in the documents listed in
Table 1-1 may be beneficial when
reading this document:
Table 1-1. Supplemental Documentation
Document Title
1
Intel® PXA26x Processor Family Developer's Manual
Intel
®
XScale™ Microarchitecture for the Intel
®
PXA250 and
PXA210 Application Processors User’s Manual
Intel® DBPXA26x Development Platform for Intel® PCA User's
Guide
Intel® PXA26x Processor Family Design Guide
ARM
®
Architecture Version 5T Specification
ARM
®
Architecture Reference Manual
NOTE: 1. Contact your Intel representative for the latest revision of these documents.
NOTE:
Order Number
278638
278525
278623
278639
ARM DDI 0100D-10
ARM DDI 0100B
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
1-1
Introduction
1-2
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Functional Overview
2
The Intel® PXA26x Processor family consists of four products integrating the Intel® XScale™
Microarchitecture, peripherals, and Intel® StrataFlash® memory:
•
PXA260 processor with no Intel StrataFlash® memory
•
PXA261 processor with 128 megabits of Intel StrataFlash® memory
•
PXA262 processor with 256 megabits of Intel StrataFlash® memory in a 16-bit configuration
•
PXA263 processor with 256 megabits of Intel StrataFlash® memory in a 32-bit configuration
Both the processor and the flash memory are packaged in a single 13x13 mm 294-pin TF-BGA package. The internal flash provides a 16-bit data bus interface connected to the processor inside the package for the PXA261 processor and PXA262 processor. The PXA263 processor internal flash is connected with a 32-bit data bus interface. The processor also supports external 32-bit memory devices.
The PXA26x processor family integrates either one or two Intel StrataFlash® K3 family flash memory die. Intel StrataFlash® memory supports synchronous and asynchronous operation and provides high density non-volatile storage using Intel’s reliable and proven two-bit-per-cell technology. Support for fast synchronous burst accesses make the flash ideal for use in execute-in- place (XIP) applications running code directly from flash. An XIP system architecture eliminates the need to copy program code and data from flash into dynamic memory, and thereby decreases the size and number of dynamic-memory components required in a cellular handset.
The PXA26x processor family features an integrated system-on-a-chip microprocessor for high performance, low power, portable handheld, and handset devices. It incorporates the Intel®
XScale™ Microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry-leading MIPs/mW performance. The PXA26x processor family is
ARM* Version 5TE instruction set compliant (excluding floating-point instructions) and follows the ARM programmer’s model.
The processor integrates a rich set of peripherals including a real-time clock, timers, LCD controller, USB client controller, four UARTs, three synchronous serial ports, and stereo audio
CODEC interfaces. For details on the programming model and theory of operation of each of these units, refer to the Intel® PXA26x Processor family Developer's Manual. The processor’s flexible memory interface also supports a variety of external memory devices, removable storage cards, and bus-interfaced companion chips. The memory controller also supports low-power mobile
SDRAMs.
Figure 2-1 on page 2-2 shows the PXA26x processor family block diagram.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
2-1
Functional Overview
Figure 2-1. PXA26x Processor Family Block Diagram
RTC
OS Timer
PWM(2)
Int.
Controller
Clocks &
Power Man.
I
2
S
I
2
C
AC97
UART1
UART2
Slow IrDA
Fast IrDA
SSP
USB
Client
MMC
NSSP
ASSP
HWUART
Color or
Grayscale
LCD
Controller
Memory
Controller
System Bus
Variable
Latency I/O
Control
PCMCIA
& CF
Control
Dynamic
Memory
Control
Static
Memory
Control
Intel
(R)
XScale
TM
Microarchitecure
Synchronous
Intel
StrataFlash
(R)
Memory
3.6864
MHz
Osc
32.768
KHz
Osc
ASIC
XCVR
Socket 0
Socket 1
SDRAM/
SMROM
4 banks
ROM/
Flash/
SRAM
4 banks
2-2
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Package Information
The Intel® PXA26x Processor family is available in a single 13x13 mm, 294-pin TF-BGA package.
Figure 3-3 on page 3-3 provide mechanical
specifications of the processor.
Figure 3-1. PXA26x Processor Family Package (top view)
A1 CORNER
1
2 3 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18
P
R
T
L
M
N
J
K
G
H
A
B
C
D
E
F
U
V
3
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 3-1
Package Information
Figure 3-2. PXA26x Processor Family Package (bottom view)
A1 CORNER
Ø0.05 M C
Ø0.15 M C A B
18 17 16 15 14 13
Ø0.40±0.05 (294X)
12 11 10 9 8 7
6 5 4 3
2 1
P
R
L
M
N
F
G
H
J
K
A
B
C
D
E
T
U
V
0.65
A
B
0.12(4X)
11.05
13.00±0.1
3-2 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Figure 3-3. PXA26x Processor Family Package (side view)
Package Information
SEATING PLANE
3.1
Insertion Specifications
The PXA26x processor family devices can be inserted and removed 15 times from its socket.
3.2
Processor Materials
The processor is assembled from several components.
Table 3-1 describes the basic material
properties.
Table 3-1. Processor Material Properties
Component Material
substrate mold compound solder balls
BT resin (CCL-HL832HS)
Sumitomo EMEG-770L
63 Sn/37 Pb
1
NOTE: 1.
Subsequent
PXA26x processor family
steppings may use
Pb-Free (94.5 Sn/5.0 Ag/
0.5 Cu)
. The package can withstand the 260° C reflow temp for Pb-Free.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 3-3
Package Information
3.3
Package Markings
Figure 3-4 details the package top-side markings and is an aid in the identification of the PXA26x
processor family devices.
Figure 3-4. Package Markings
Laser Mark at assembly site on top side of Package
13 x 13 mm
Mark Diagram for TPBGA 294L
Mfg. Name
– N/A
Mktg. Name – PCGAPDH326A0
i
PXA262
MECH SAMPLES
INTEL M C ‘01
QDF # / ES
Intel Legal
COO
KOREA
PIN 1 ORIENTATION
3.4
Package Power Ratings
Table 3-2.
θ
JA
and Maximum Power Ratings
Processor
PXA260
PXA261
PXA262
PXA263
θ
JA
TBD C
°
/w
TBD C
°
/w
TBD C
°
/w
TBD C
°
/w
Max Power
TBD W
TBD W
TBD W
TBD W
3-4 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
4
This section provides information on the Intel® PXA26x Processor family signals and how those
signals are connected to the pins of the package. Table 4-1 on page 4-2 contain a description of all
processor signals. Note that many signals are multiplexed so that they may be used either for a peripheral unit or for a general-purpose I/O (GPIO).
lists the mapping of these signals to specific package pins. The signal types are defined in
4.1
Signals Reference
Refer to Figure 4-1 for a diagram of the PXA26x processor family TF-BGA ball map. Refer to
Table 4-1 on page 4-2 for a list of signal names and descriptions.
Figure 4-1. PXA26x Processor Family TF-BGA Ball Map: Top View
1 2 3 4 5 6 7 8
A VSSN VSSN GPIO[69] GPIO[13] VCC GPIO[63] GPIO[11] GPIO[76]
B VSSN VSSN GPIO[71] GPIO[66] VSSQ GPIO[64] GPIO[59] GPIO[77]
C DQM[2] GPIO[73] GPIO[70] GPIO[67] VSSQ GPIO[65] GPIO[61] GPIO[75]
D SDCKE[0]
RDY/
GPIO[18]
GPIO[72] GPIO[68] VCCQ GPIO[12] GPIO[60] GPIO[41]
E SDCLK[2]
RDnWR/
GPIO[88]
VCCN DQM[1] GPIO[14] GPIO[62] GPIO[58] GPIO[10]
F nSDCS[3]/
GPIO[87]
VCC SDCLK[1] SDCKE[1] SDCLK[0] VSS_F VSS_F nRST_F
G nSDCS[1] nSDRAS VCCN nSDCS[0] nSDCAS VSSN
H VSSQ VCCN MA[0] VSSN nSDCS[2]/
GPIO[86]
MA[1]
11 12 13 14 15 16 17 18
GPIO[30] GPIO[38] SDA VCCQ USB_P GPIO[42] VSSQ VSSQ A
GPIO[29] GPIO[16] GPIO[37] VSSQ USB_N GPIO[47] VSSQ VSSQ B
GPIO[31] GPIO[17] GPIO[36] GPIO[35] GPIO[34] GPIO[45] GPIO[46] VCC nACRESET
/GPIO[89]
VCC GPIO[39] GPIO[43] GPIO[44] GPIO[9] VCCQ VSS
C
D
SCL VSSQ MMDAT GPIO[32] MMCMD GPIO[84] GPIO[81] GPIO[85] E
VCC_F VSSQ_F GPIO[8] GPIO[82] GPIO[83] GPIO[7] VCCQ VSSQ F
VCC_F
BOOT_SEL[
2]
BOOT_SEL[
1]
BOOT_SEL[
0]
TEST TESTCLK nTRST GPIO[6] G
TMS TCK GPIO[5] PLL_VCC PLL_VSS TDO TDI H
L VCCN MA[7] VSSN MA[9] MA[8] MA[10] MA[14]
M MA[11] MD[19] VCCN VSSN MA[15] VSSQ_F VCCQ_F VCC_F
N MD[20] MA[13] MA[12] MD[22] MA[17] VSSQ_F VCCQ_F VCC_F
P VSSQ MD[21] MA[16] VCCQ_F MA[18] MD[0] MD[25] VCCN
R VCCN VCC MA[20] MA[23] MA[25] VCCN VSSQ MD[6]
T MA[19] VCCN VSSQ MD[23] MA[24] MD[24] VSSN MD[5]
U VSSN VSSN VSS VCCN MA[22] MD[3] MD[2] MD[4]
V VSSN VSSN VCCN MA[21] VSSN MD[1] VCCN VCC
1 2 3 4 5 6 7 8
VSS_F
VCCQ_F nOE nWE GPIO[55] BATT_VCC VSSQ GPIO[2] PXTAL L
VCCQ_F WAIT_F1 GPIO[56] GPIO[22] GPIO[1] GPIO[0] M
VSSQ_F WAIT_F2 GPIO[49] VCCN GPIO[54] GPIO[57] N
VCCQ_F MD[14] MD[15] GPIO[48] VSSQ VCC GPIO[21] P
MD[11] VCCQ_F VSSQ_F VCC VCCN GPIO[50] GPIO[53] GPIO[19] R
VCCN MD[28] VCCN VSSN MD[13] GPIO[20] GPIO[51] GPIO[52] T nCS[3]/
GPIO[79]
MD[10] VSSQ MD[31] MD[12] nCS[5]/
GPIO[33]
VSSN VSSN nCS[2]/
GPIO[78]
MD[9] MD[29] MD[30] VSSN nCS[4]/
GPIO[80]
VSSN VSSN
U
V
11 12 13 14 15 16 17 18
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-1
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 1 of 8)
Signal Name
Memory Controller Signals
Type Descriptions
MA[25:0]
MD[31:16]
MD[15:0] nOE nWE
DQM[3:0] nSDRAS nSDCAS
SDCKE0
SDCKE1
SDCLK0
SDCLK1
SDCLK2
Output
Bi-directional
Bi-directional
Output
Output
Output
Output
Output
Output
Output
Output
MEMORY ADDRESS BUS:
Drives the requested address for memory accesses.
UPPER HALF OF MEMORY DATA BUS:
Carries data to and from 32-bit memory devices.
LOWER HALF OF MEMORY DATA BUS:
Carries data to and from memory devices.
MEMORY OUTPUT ENABLE:
Connect to the output enables of static memory devices to control data bus drivers.
MEMORY WRITE ENABLE:
Connect to the write enables of SD-RAM and static memory devices.
SDRAM DQM DATA BYTE MASK CONTROL FOR DATA BYTES 3 THROUGH 0:
Connect to the data output mask enables (DQM) for SDRAM. (DQM0 corresponds to
MD[7:0], DQM1 corresponds to MD[15:8], etc. DQMx is High to mask the byte)
SDRAM RAS:
Connect to the row address strobe (RAS) pins for all banks of SDRAM.
SDRAM CAS:
Connect to the column address strobe (CAS) pins for all banks of SDRAM.
SDRAM AND/OR SYNCHRONOUS STATIC MEMORY CLOCK ENABLE:
Connect to the clock enable pins of SDRAM. The memory controller provides control register bits for de-assertion.
SDRAM AND/OR SYNCHRONOUS STATIC MEMORY CLOCK ENABLE:
Connect to the clock enable pins of SDRAM. It is de-asserted (held low) during sleep.
SDCKE1 is always deasserted upon reset. The memory controller provides control register bits for de-assertion.
SDRAM AND/OR SYNCHRONOUS STATIC MEMORY CLOCKS:
Connect SDCLK0 to the clock pins of SMROM and SDRAM. SDCLK1 and SDCLK2 should be connected to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively.
They are driven by either the internal memory-controller clock, or the internal memory- controller clock divided by 2. At reset, all clock pins are free running at the divide-by-2 clock speed and may be turned off via free-running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK0 control-register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM. SDCLK2 and SDCLK1 control-register assertion bits are always de-asserted upon reset.
SDCLK0 and SDCLK2 are not three-stateable, SDCLK1 is three-stateable nSDCS3 nSDCS2 nSDCS1 nSDCS0
Output
SDRAM CHIP SELECTS:
Chip selects for SDRAM memory devices. Individually programmable in the memory configuration registers. nSDCS0 is three-stateable, but nSDCS1, nSDCS2 and nSDCS3 are not.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-2
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 2 of 8)
Type Descriptions Signal Name
nCS5 nCS4 nCS3 nCS2 nCS1 nCS0
Output
STATIC CHIP SELECTS
†
:
Chip selects to static memory devices such as ROM and flash. Individually programmable in the memory-configuration registers.
nCS5 to nCS0 can be used with variable latency I/O devices. nCS0 is the boot memory chip select and is a dedicated pin.
RDnWR
RDY
BOOTSEL[2:0]
MBREQ
MBGNT
Output
Input
Input
Input
Output
READ/WRITE FOR STATIC INTERFACE:
Intended for use as a steering signal for buffering logic. Indicates that the current transaction is a read (when high) or a write (when low).
VARIABLE LATENCY I/O READY PIN
†
:
An external VLIO device asserts RDY when it is ready to transfer data.
BOOT SELECT. BOOT SOURCE PROGRAMMING SELECT PINS:
These pins are sampled to indicate the type of boot device present.
MEMORY CONTROLLER ALTERNATE BUS MASTER REQUEST:
Allows an external device to request control of the memory bus from the memory controller.
MEMORY CONTROLLER ALTERNATE BUS MASTER GRANT:
The memory controller asserts MBGNT to allow an external device to control the memory bus.
PCMCIA/CF Control Signals nPOE nPWE nPIOW nPIOR nPCE2 nPCE1 nIOIS16 nPWAIT nPSKTSEL
Output
Output
Output
Output
Output
Output
Input
Input
Output
PCMCIA OUTPUT ENABLE
†
:
Output enable for reads from PCMCIA memory and PCMCIA attribute space.
PCMCIA WRITE ENABLE
†
:
Enables writes to PCMCIA memory and PCMCIA attribute space. Also used as the write enable signal for variable latency I/O.
PCMCIA I/O WRITE
†
:
Asserted for writes to PCMCIA I/O space.
PCMCIA I/O READ
†
:
Asserted for reads from PCMCIA I/O space.
PCMCIA CARD ENABLE 2
†
:
Selects a PCMCIA card. nPCE2 enables the high byte lane.
PCMCIA CARD ENABLE 1
†
:
Selects a PCMCIA card. nPCE1 enables the low byte lane.
IO SELECT 16
†
:
Input from the PCMCIA card that indicates the data bus is 16-bits wide when high. When low, this input indicates the data bus is 8-bits wide.
PCMCIA WAIT
†
:
Driven low by the PCMCIA card to insert wait states that extend transfers to and from the
PXA26x processor family device.
PCMCIA SOCKET SELECT
†
:
Used by external steering logic to route control, address, and data signals to one of the two PCMCIA sockets. When nPSKTSEL is low, socket zero is selected. When nPSKTSEL is high, socket one is selected. Has the same timing as the address bus.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-3
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 3 of 8)
Signal Name
nPREG
Type
Output
Descriptions
PCMCIA REGISTER SELECT
†
:
Functions as address bit 26 to select register space (I/O or attribute) or memory space.
Has the same timing as the address bus.
LCD Controller Signals
L_DD[15:0]
L_FCLK
L_LCLK
L_PCLK
L_BIAS
Output
Output
Output
Output
Output
LCD DISPLAY DATA
†
:
Transfers pixel information from the LCD controller to the external LCD panel.
LCD FRAME CLOCK
†
:
Frame clock that resets the LCD display module line pointers to the top of the screen.
Also, this pin is the vertical synchronization signal for active (TFT) displays.
LCD LINE CLOCK
†
:
Indicates the start of a new line. Also referred to as H sync
for active panels.
LCD PIXEL CLOCK
†
:
Pixel clock used by the LCD display module to clock the pixel data into the line-shift register. In passive mode, pixel clock transitions only when valid data is available on the data pins. In active mode, pixel clock transitions continuously and the AC bias pin is used as an output to signal when data is valid on the LCD data pins.
LCD BIAS DRIVE
†
:
AC bias used to signal the LCD display module to switch the polarity of the power supplies to the row and column axis of the screen to counteract DC offset. In active
(TFT) mode, it is used as the output-enable to signal when data should be latched from the data pins using the pixel clock.
Full Function UART Signals
FFRXD
FFTXD
FFCTS
FFDCD
FFDSR
FFRI
FFDTR
FFRTS
Input
Output
Input
Input
Input
Input
Output
Output
FULL FUNCTION UART RECEIVE DATA
†
FULL FUNCTION UART TRANSMIT DATA
†
FULL FUNCTION UART CLEAR-TO-SEND
†
FULL FUNCTION UART DATA-CARRIER-DETECT
†
FULL FUNCTION UART DATA-SET-READY
†
FULL FUNCTION UART RING INDICATOR
†
FULL FUNCTION UART DATA-TERMINAL-READY
†
FULL FUNCTION UART REQUEST-TO-SEND
†
Bluetooth UART Signals
BTRXD
BTTXD
BTCTS
Input
Output
Input
BLUETOOTH UART RECEIVE DATA
†
BLUETOOTH UART TRANSMIT DATA
†
BLUETOOTH UART CLEAR-TO-SEND
†
BLUETOOTH UART REQUEST-TO-SEND
†
BTRTS Output
Hardware UART Signals
HWRXD
HWTXD
HWCTS
HWRTS
Input
Output
Input
Output
HARDWARE UART RECEIVE DATA
†
HARDWARE UART TRANSMIT DATA
†
HARDWARE UART CLEAR-TO-SEND
†
HARDWARE UART REQUEST-TO-SEND
†
Standard UART and infrared Communication Port (ICP) Signals
IRRXD Input STANDARD UART AND IRDA RECEIVE DATA
†
4-4 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 4 of 8)
Signal Name Type
IRTXD Output
Descriptions
STANDARD UART AND IRDA TRANSMIT DATA
†
:
Transmit data pin for the standard UART, SIR and FIR functions.
MMC Controller Signals
MMCLK Output
MMCCMD
MMCDAT
MMCCS0
MMCCS1
Bi-directional
Bi-directional
Output
Output
MULTIMEDIA CARD BUS CLOCK
MULTIMEDIA CARD COMMAND:
MMC and SD – Bi-directional line for command and response tokens.
SPI – Output for command and write data.
MULTIMEDIA CARD DATA:
MMC and SD – Bi-directional line for read and write data.
SPI – Input for response token and read data.
MMC CHIP SELECT 0:
Chip select 0 for the MMC controller.
MMC CHIP SELECT 1:
Chip select 1 for the MMC controller.
Standard SSP Signals
SSPSCLK
SSPSFRM
Output
Output
SSPTXD
SSPRXD
SSPEXTCLK
Output
Input
Input
SYNCHRONOUS SERIAL PORT CLOCK
†
SYNCHRONOUS SERIAL PORT FRAME
†
SYNCHRONOUS SERIAL PORT TRANSMIT DATA
†
:
Serial data driven out synchronous with the bit clock.
SYNCHRONOUS SERIAL PORT RECEIVE DATA
†
:
Serial data latched using the bit clock.
SYNCHRONOUS SERIAL PORT EXTERNAL CLOCK
†
:
This input may be used to supply an external bit clock.
Network SSP Signals
NSSPSCLK
NSSPSFRM
NSSPTXD
NSSPRXD
Bi-directional
Bi-directional
Output
Input
NETWORK SYNCHRONOUS SERIAL PORT CLOCK
†
:
The serial bit clock may be configured as an output in master-mode operation or an input in slave-mode operation.
NETWORK SYNCHRONOUS SERIAL PORT FRAME
†
:
The serial frame sync may be configured as an output in master-mode operation or an input in slave-mode operation.
NETWORK SYNCHRONOUS SERIAL PORT TRANSMIT DATA
†
:
Serial data driven out synchronous with the bit clock.
NETWORK SYNCHRONOUS SERIAL PORT RECEIVE DATA
†
:
Serial data latched using the bit clock.
Audio SSP Signals
ASSPSCLK
ASSPSFRM
ASSPTXD
Bi-directional
Bi-directional
Output
AUDIO SYNCHRONOUS SERIAL PORT CLOCK
†
:
The serial bit clock may be configured as an output in master-mode operation or an input in slave-mode operation.
AUDIO SYNCHRONOUS SERIAL PORT FRAME
†
:
The serial frame sync may be configured as an output in master-mode operation or an input in slave-mode operation.
AUDIO SYNCHRONOUS SERIAL PORT TRANSMIT DATA
†
:
Serial data driven out synchronous with the bit clock.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-5
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 5 of 8)
Signal Name Type
ASSPRXD Input
Descriptions
AUDIO SYNCHRONOUS SERIAL PORT RECEIVE DATA
†
:
Serial data latched using the bit clock.
USB Client Signals
USBC_P
USBC_N
Bi-directional
Bi-directional
USB CLIENT POSITIVE LINE:
This differential signal connects to the USB client interface.
USB CLIENT NEGATIVE LINE:
This differential signal connects to the USB client interface.
Single-Ended USB Client Signals
USB_RCV
USB_VP
USB_VM
USB_VPO
USB_VMO
USB_nOE
Input
Input
Input
Output
Output
Output
USB CLIENT SINGLE-ENDED INTERFACE RCV:
Input from external transceiver to USB device controller.
USB CLIENT SINGLE-ENDED INTERFACE VP:
Input from external transceiver to USB device controller.
USB CLIENT SINGLE-ENDED INTERFACE VM:
Input from external transceiver to USB device controller.
USB CLIENT SINGLE-ENDED INTERFACE VPO:
Output to external transceiver differential driver.
USB CLIENT SINGLE-ENDED INTERFACE VMO:
Output to external transceiver differential driver.
USB CLIENT SINGLE-ENDED INTERFACE NOE:
Output enable to external transceiver.
AC97 Controller Signals nACRESET
BITCLK
SYNC
SDATA_OUT
SDATA_IN0
SDATA_IN1
SYSCLK
Output
Output
Output
Output
Input
Input
Output
AC97 RESET:
Active-low CODEC reset.
AC97 BIT CLOCK
†
:
Bit-rate clock.
AC97 SYNC
†
:
Frame indicator and synchronizer.
AC97 SERIAL DATA OUT
†
:
Serial audio data output to the CODEC for digital-to-analog conversion.
AC97 SERIAL DATA IN 0
†
:
Serial audio data from the primary CODEC analog-to-digital converter.
AC97 SERIAL DATA IN 1
†
:
Serial audio data from the secondary CODEC analog-to-digital converter.
AC97 SYSTEM CLOCK
†
:
AC97 system clock output.
I
2
S Interface Signals
SYSCLK
BITCLK
Output
Bi-directional
I
2
S SYSTEM CLOCK:
System clock running four times the bit clock which is used by the CODEC only.
I
2
S BIT-RATE CLOCK:
I
2
S bit-rate clock.
4-6 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 6 of 8)
Signal Name Type
SYNC
SDATA_OUT
SDATA_IN
Output
Output
Input
Descriptions
I
2
S SYNC:
Sync signal to identify left/right channel data.
I
2
S SERIAL DATA OUT:
Serial data output to the CODEC digital-to-analog converter.
I
2
S SERIAL DATA IN:
Serial data input from the CODEC analog-to-digital converter.
I
2
C Interface Signals
SCL
SDA
Bi-directional
Bi-directional
I
2
C CLOCK:
Bi-directional signal. When it is driving, it functions as an open drain device and requires a pull-up resistor. As an input, it expects standard CMOS levels.
I
2
C DATA:
Bi-directional signal. When it is driving, it functions as an open drain device and requires a pull-up resistor. As an input, it expects standard CMOS levels.
PWM Signals
PWM1
PWM0
Output
Output
PULSE WIDTH MODULATION CHANNEL 1:
Pulse width modulator channel 1 output.
PULSE WIDTH MODULATION CHANNEL 0:
Pulse width modulator channel 0 output.
DMA Signals
DREQ0
DREQ1
Input
Input
DMA REQUEST 0:
DMA request from an external companion chip.
DMA REQUEST 1:
DMA request from an external companion chip.
GPIO Signals
GPIO[1:0] Bi-directional
GPIO[14:2]
GPIO[22:21]
Bi-directional
Bi-directional
GPIO[85] Bi-directional
Crystal and Clock Signals
GENERAL PURPOSE I/O:
These signals are preconfigured at hardware reset as dedicated wakeup sources for both rising and falling edge detection. These GPIOs do not have alternate functions and are intended to be used as the main external sleep wakeup stimulus.
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
PXTAL
PEXTAL
TXTAL
TEXTAL
Output
Input
Output
Input
PROCESSOR CRYSTAL OUTPUT:
Connect the PXTAL signal to either an external 3.6864-MHz crystal or to an external clock source. No external caps are required
PROCESSOR CRYSTAL INPUT:
Connect the PEXTAL signal to either an external 3.6864-MHz crystal or left unconnected. No external caps are required
TIMEKEEPING CRYSTAL OUTPUT:
The TXTAL signal is a clock input that is distributed to the timekeeping control system
(32.768-KHz crystal or external clock source). No external caps are required
TIMEKEEPING CRYSTAL INPUT:
Connect the TEXTAL signal to either an external 32.768-KHz crystal or leave unconnected. No external caps are required
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-7
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 7 of 8)
Signal Name Type
RTCCLK
3.6MHz
32KHz
48_MHz
Output
Output
Output
Output
Descriptions
RTC CLOCK:
Real time clock, 1 Hz clock derived from the 32-KHz or 3.6864-MHz output.
3.6864-MHz CLOCK:
Output from 3.6864-MHz oscillator.
32-KHZ CLOCK:
Output from the 32-KHz oscillator.
48-MHz OUTPUT CLOCK:
This clock is only generated when the USB unit clock enable is set.
Miscellaneous Signals
PWR_EN nBATT_FAULT nVDD_FAULT nRESET nRESET_OUT
Output
Input
Input
Input
Output
POWER ENABLE FOR THE CORE POWER SUPPLY:
When low, it signals the power supply to remove power from VCC because the system is entering sleep mode. When high, the power supply must enable VCC.
BATTERY FAULT:
Active low input – Signals that main battery is low or removed. Assertion causes PXA26x processor family processor to enter sleep mode or force an imprecise data exception, which cannot be masked. PXA26x processor family processor does not recognize a wakeup event while this signal is asserted. Minimum assertion time for nBATT_FAULT is
1 ms.
VDD FAULT:
Active low input – Signals that the main power source is going out of regulation. nVDD_FAULT causes the PXA26x processor family processor to enter sleep mode or force an imprecise data exception, which cannot be masked. nVDD_FAULT is ignored after a wakeup event until the power supply timer completes (approximately 10 ms).
Minimum assertion time for nVDD_FAULT is 1 ms.
HARD RESET:
Active low input – Level-sensitive input used to start the processor from a known address. Assertion terminates the current instruction abnormally and causes a reset.
When nRESET is driven high, the processor starts execution from address 0. nRESET must remain low until the power supply is stable and the internal 3.6864 MHz oscillator has stabilized.
RESET OUT:
Active low output – This signal is asserted when nRESET is asserted and de-asserts after nRESET is negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft” reset events (sleep, watchdog reset, GPIO reset)
JTAG and Test Signals nTRST
TDI
TDO
TMS
Input
Input
Output
Input
JTAG TEST RESET. IEEE 1194.1 TEST RESET:
Resets the JTAG/debug port – If JTAG/debug is used, drive nTRST from low to high either before or at the same time as nRESET. If JTAG is not used, nTRST must be either tied to nRESET or tied low. A JTAG/debug port should be added to all systems for debug and download.
JTAG TEST DATA INPUT:
Data from the JTAG controller is sent to the PXA26x processor family using this signal.
This pin has an internal pull-up resistor.
JTAG TEST DATA OUTPUT:
Data from the PXA26x processor family is returned to the JTAG controller using this signal. This pin does not have an internal pullup resistor.
JTAG TEST MODE SELECT:
Selects the test mode required from the JTAG controller. This signal has an internal pullup resistor.
4-8 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Table 4-1. Signal Descriptions for the PXA26x Processor Family (Sheet 8 of 8)
Signal Name Type Descriptions
TCK
TEST
TESTCLK
Input
Input
Input
JTAG TEST CLOCK:
Clock for all transfers on the JTAG test interface.
NOTE: This pin needs an external pulldown resistor.
TEST MODE:
Reserved for manufacturing test. Must be grounded for normal operation.
TEST CLOCK:
Reserved for manufacturing test. Must be grounded for normal operation.
Processor Power and Ground Signals
VCC
VSS
PLL_VCC
Supply
Supply
Supply
POSITIVE SUPPLY FOR THE INTERNAL LOGIC:
Connect these pins to the low voltage supply on the PCB.
GROUND SUPPLY FOR THE INTERNAL LOGIC:
Connect these pins to the common ground plane on the PCB.
POSITIVE SUPPLY FOR PLLS AND OSCILLATORS:
Must be shorted to VCC.
PLL_VSS
VCCQ
VSSQ
VCCN
VSSN
Supply
Supply
Supply
Supply
Supply
GROUND SUPPLY FOR THE PLL:
Must be connected to common ground plane on the PCB.
POSITIVE SUPPLY FOR ALL CMOS I/O:
Except memory bus and PCMCIA pins. Connect these pins to the common 2.775 V or
3.3 V supply on the PCB.
GROUND SUPPLY FOR ALL CMOS I/O:
Except memory bus and PCMCIA pins. Connect these pins to the common ground plane on the PCB.
POSITIVE SUPPLY FOR MEMORY BUS AND PCMCIA PINS:
Connect these pins to the common 3.3 V, 2.775 V, or 2.5 V supply on the PCB.
GROUND SUPPLY FOR MEMORY BUS AND PCMCIA PINS:
Connect these pins to the common ground plane on the PCB.
Flash Signals nRST_F nWP
VPEN
WAIT_F1/WAIT_F2
VCC_F
Input
Input
Input
Output
Supply
RESET FOR FLASH ONLY
WRITE PROTECT
ERASE/PROGRAM/BLOCK LOCK ENABLE
WAIT:
Indicates invalid data in synchronous-read (burst) modes. Not used by the PXA26x, can be used by external programmers.
FLASH CORE LOGIC SUPPLY
Must be at the same voltage as VCCN.
VSS_F
VCCQ_F
Supply
Supply
FLASH CORE GROUND
FLASH I/O POWER SUPPLY:
Must be the same voltage as VCCN.
VSSQ_F Supply FLASH I/O GROUND
† GPIO reset operation: After any reset, these pins are configured as GPIO inputs by default, except for GPIO[89:86].
GPIO[89:86] are configured as their alternate function after any reset.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-9
Pin Listing and Signal Definitions
4.2
Pin Listing
The package pin listing is shown in
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 1 of 9)
Ball#
B11
B12
B13
B14
B15
B7
B8
B9
B10
B3
B4
B5
B6
A17
A18
B1
B2
A13
A14
A15
A16
A9
A10
A11
A12
A5
A6
A7
A8
A1
A2
A3
A4
Name
GPIO[59]
GPIO[77]
VCCQ
GPIO[25]
GPIO[29]
GPIO[16]
GPIO[37]
VSSQ
USB_N
VSSQ
VSSQ
VSSN
VSSN
GPIO[71]
GPIO[66]
VSSQ
GPIO[64]
VSSQ
GPIO[24]
GPIO[30]
GPIO[38]
SDA
VCCQ
USB_P
GPIO[42]
VSSN
VSSN
GPIO[69]
GPIO[13]
VCC
GPIO[63]
GPIO[11]
GPIO[76]
Type
ICOCZ
ICOCZ
IA
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
IAOA
ICOCZ
ICOCZ
IA
ICOCZ
IA
IA
IA
IA
IA
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
IAOA
ICOCZ
IA
IA
ICOCZ
ICOCZ
IA
ICOCZ
ICOCZ
ICOCZ
Primary
Function
—
—
—
—
3.6MHZ
MBREQ
—
—
—
—
—
—
SDATA_IN0
—
FFDSR
—
—
—
—
MMCCLK
—
—
—
3.6MHZ
—
—
—
SDATA_OUT
FFRI
—
—
—
BTRXD
GPIO[59]
GPIO[77]
VCCQ
GPIO[25]
GPIO[29]
GPIO[16]
GPIO[37]
VSSQ
USB_N
VSSQ
VSSQ
VSSN
VSSN
GPIO[71]
GPIO[66]
VSSQ
GPIO[64]
VSSQ
GPIO[24]
GPIO[30]
GPIO[38]
SDA
VCCQ
USB_P
GPIO[42]
VSSN
VSSN
GPIO[69]
GPIO[13]
VCC
GPIO[63]
GPIO[11]
GPIO[76]
Function
After
Reset
GPIO[59]
GPIO[77]
VCCQ
GPIO[25]
GPIO[29]
GPIO[16]
GPIO[37]
VSSQ
USB_N
VSSQ
VSSQ
VSSN
VSSN
GPIO[71]
GPIO[66]
VSSQ
GPIO[64]
VSSQ
GPIO[24]
GPIO[30]
GPIO[38]
SDA
VCCQ
USB_P
GPIO[42]
VSSN
VSSN
GPIO[69]
GPIO[13]
VCC
GPIO[63]
GPIO[11]
GPIO[76]
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
—
—
—
—
L_DD[13]
L_DD[8]
—
L_DD[6]
L_DD[1]
L_BIAS
—
TXD
SDATA_IN
PWM0
—
—
—
—
—
L_DD[11]
MBGNT
—
L_DD[5]
—
L_PCLK
—
SFRM
SDATA_OUT
—
—
—
—
—
—
—
—
—
ASSPRXD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ASSPTXD
—
—
—
—
HWRXD
—
—
—
—
—
—
—
—
4-10 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
C10
C11
C12
C13
C14
C6
C7
C8
C9
C2
C3
C4
C5
B16
B17
B18
C1
C15
D10
D11
D12
D13
D6
D7
D8
D9
D14
D15
D2
D3
D4
D5
C16
C17
C18
D1
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 2 of 9)
Ball# Name
GPIO[65]
GPIO[61]
GPIO[75]
GPIO[74]
GPIO[26]
GPIO[31]
GPIO[17]
GPIO[36]
GPIO[35]
GPIO[47]
VSSQ
VSSQ
DQM[2]
GPIO[73]
GPIO[70]
GPIO[67]
VSSQ
GPIO[34]
Type
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
IA
OCZ
ICOCZ
ICOCZ
ICOCZ
IA
ICOCZ
Function
After
Reset
GPIO[65]
GPIO[61]
GPIO[75]
GPIO[74]
GPIO[26]
GPIO[31]
GPIO[17]
GPIO[36]
GPIO[35]
GPIO[47]
VSSQ
VSSQ
DQM[2]
GPIO[73]
GPIO[70]
GPIO[67]
VSSQ
GPIO[34]
GPIO[45]
GPIO[46]
VCC
SDCKE[0]
GPIO[18]
GPIO[72]
GPIO[68]
VCCQ
ICOCZ
ICOCZ
IA
OC
ICOCZ
ICOCZ
ICOCZ
IA
GPIO[45]
GPIO[46]
VCC
SDCKE[0]
GPIO[18]
GPIO[72]
GPIO[68]
VCCQ
GPIO[12]
GPIO[60]
GPIO[41]
GPIO[23]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
GPIO[12]
GPIO[60]
GPIO[41]
GPIO[23]
GPIO[28] ICOCZ GPIO[28] nACRESET ICOCZ nACRESET
VCC
GPIO[39]
IA
ICOCZ
VCC
GPIO[39]
GPIO[43]
GPIO[44]
ICOCZ
ICOCZ
GPIO[43]
GPIO[44]
Primary
Function
GPIO[34]
GPIO[45]
GPIO[46]
VCC
SDCKE[0]
GPIO[18]
GPIO[72]
GPIO[68]
VCCQ
GPIO[12]
GPIO[60]
GPIO[41]
GPIO[23]
GPIO[28] nACRESET
VCC
GPIO[39]
GPIO[43]
GPIO[44]
GPIO[65]
GPIO[61]
GPIO[75]
GPIO[74]
GPIO[26]
GPIO[31]
GPIO[17]
GPIO[36]
GPIO[35]
GPIO[47]
VSSQ
VSSQ
DQM[2]
GPIO[73]
GPIO[70]
GPIO[67]
VSSQ
Alternate
Function 1
—
IRRXD
—
—
RDY
32KHZ
MMCCS1
—
32KHZ
—
—
—
BITCLK
GPIO[89]
—
MMCCS1
—
BTCTS
—
—
—
—
RXD
SYNC
—
FFDCD
FFCTS
STTXD
—
—
—
MBGNT
RTCCLK
MMCCS0
—
FFRXD
Alternate
Function 2
—
L_DD[2]
FFRTS
SCLK
BITCLK
—
—
FFTXD
BTTXD
—
BTRTS
STRXD
—
—
—
L_DD[14]
L_DD[10]
—
L_DD[7]
L_DD[3]
L_LCLK
L_FCLK
—
SYNC
PWM1
—
—
MMCCS0
USB_VM
IRTXD
—
—
—
L_DD[15]
L_DD[12]
L_DD[9]
—
Alternate
Function 3
—
—
—
—
—
ASSPSFRM
—
—
—
—
—
—
—
—
—
—
—
—
HWRTS
—
—
—
—
—
—
—
—
—
—
—
ASSPSCLK
—
—
USB_VPO
HWTXD
HWCTS
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-11
Pin Listing and Signal Definitions
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 3 of 9)
Ball# Name Type
Function
After
Reset
Primary
Function
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
D16
E10
E11
E12
E13
E6
E7
E8
E9
E2
E3
E4
E5
D17
D18
E1
E14
F8
F9
F10
F11
F4
F5
F6
F7
E15
E16
E17
E18
F1
F2
F3
F12
F13
F14
GPIO[9]
VCCQ
VSS
SDCLK[2]
RDnWR
VCCN
DQM[1]
GPIO[14]
GPIO[62]
GPIO[58]
GPIO[10]
GPIO[27]
GPIO[40]
SCL
VSSQ
MMCDAT
GPIO[32]
MMCCMD
GPIO[84]
GPIO[81]
GPIO[85] nSDCS[3]
VCC
SDCLK[1]
SDCKE[1]
SDCLK[0]
VSS_F
VSS_F nRST_F nWP_F
VPEN_F
VCC_F
VSSQ_F
GPIO[8]
GPIO[82]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
ICOCZ
IA
IA
OC
ICOCZ
IA
OCZ
ICOCZ
ICOCZ
IC
IC
IC
IA
OC
OCZ
IA
IA
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
OCZ
IA
ICOCZ
ICOCZ
GPIO[9]
VCCQ
VSS
SDCLK[2]
RDnWR
VCCN
DQM[1]
GPIO[14]
GPIO[62]
GPIO[58]
GPIO[10]
GPIO[27]
GPIO[40]
SCL
VSSQ
MMCDAT
GPIO[32]
MMDAT
GPIO[84]
GPIO[81]
GPIO[85] nSDCS[3]
VCC
SDCLK[1]
SDCKE[1]
SDCLK[0]
VSS_F
VSS_F nRST_F nWP_F
VPEN_F
VCC_F
VSSQ_F
GPIO[8]
GPIO[82]
GPIO[9]
GPIO[32]
MMDAT
GPIO[84]
GPIO[81]
GPIO[85] nSDCS[3]
VCC
SDCLK[1]
SDCKE[1]
SDCLK[0]
VSS_F
VSS_F nRST_F nWP_F
VPEN_F
VCC_F
VSSQ_F
GPIO[8]
GPIO[82]
VCCQ
VSS
SDCLK[2]
RDnWR
VCCN
DQM[1]
GPIO[14]
GPIO[62]
GPIO[58]
GPIO[10]
GPIO[27]
GPIO[40]
SCL
VSSQ
MMCDAT
NSSPTXD
NSSPSCLK
—
GPIO[87]
—
—
—
—
—
—
—
—
—
—
—
MMCCS0
NSSPSFRM
MMCCS1
USB_RCV
—
—
—
GPIO[88]
—
—
MBREQ
—
—
RTCCLK
EXTCLK
—
—
—
—
SDATA_IN1
SYSCLK
—
—
—
—
—
—
—
—
—
—
—
NSSPRXD
—
—
—
—
—
—
—
—
L_DD[4]
L_DD[0]
—
—
FFDTR
—
—
—
—
—
—
—
—
—
—
USB_VP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4-12 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 4 of 9)
Ball#
H16
H17
H18
J1
H12
H13
H14
H15
J2
J3
J4
J5
H3
H4
H5
H6
G17
G18
H1
H2
G13
G14
G15
G16
G5
G6
G11
G12
G1
G2
G3
G4
F15
F16
F17
F18
Name Type
IC
IC
ICOCZ
IA
IA
OCZ
IC
IA
IC
ICOCZ
IA
IA
OCZ
IA
ICOCZ
OCZ
IA
IA
ICOCZ
IA
IC
IC
IC
IC
OCZ
IA
IA
IC
ICOCZ
ICOCZ
IA
IA
ICOCZ
OCZ
IA
OCZ nTRST
GPIO[6]
VSSQ
VCCN
MA[0]
VSSN nSDCS[2]
MA[1]
TMS
TCK
GPIO[5]
PLL_VCC
PLL_VSS
TDO
TDI
VSSQ
VCC
VSSN
MD[16]
VCCN
GPIO[83]
GPIO[7]
VCCQ
VSSQ nSDCS[1] nSDRAS
VCCN nSDCS[0] nSDCAS
VSSN
VCC_F
BOOTSEL[2]
BOOTSEL[1]
BOOTSEL[0]
TEST
TESTCLK
Function
After
Reset
nTRST
GPIO[6]
VSSQ
VCCN
MA[0]
VSSN nSDCS[2]
MA[1]
TMS
TCK
GPIO[5]
PLL_VCC
PLL_VSS
TDO
TDI
VSSQ
VCC
VSSN
MD[16]
VCCN
GPIO[83]
GPIO[7]
VCCQ
VSSQ nSDCS[1] nSDRAS
VCCN nSDCS[0] nSDCAS
VSSN
VCC_F
BOOTSEL[2]
BOOTSEL[1]
BOOTSEL[0]
TEST
TESTCLK
Primary
Function
—
—
—
—
—
—
—
—
—
MMCCLK
—
—
—
—
GPIO[86]
—
—
—
—
—
—
—
—
—
—
—
—
—
NSSPTXD
48_MHz
—
—
GPIO[85]
—
—
— nTRST
GPIO[6]
VSSQ
VCCN
MA[0]
VSSN nSDCS[2]
MA[1]
TMS
TCK
GPIO[5]
PLL_VCC
PLL_VSS
TDO
TDI
VSSQ
VCC
VSSN
MD[16]
VCCN
GPIO[83]
GPIO[7]
VCCQ
VSSQ nSDCS[1] nSDRAS
VCCN nSDCS[0] nSDCAS
VSSN
VCC_F
BOOTSEL[2]
BOOTSEL[1]
BOOTSEL[0]
TEST
TESTCLK
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NSSPRXD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-13
Pin Listing and Signal Definitions
Ball#
L14
L15
L16
L17
L6
L7
L12
L13
L18
M1
M2
M3
L2
L3
L4
L5
K16
K17
K18
L1
K6
K13
K14
K15
K2
K3
K4
K5
J16
J17
J18
K1
J6
J13
J14
J15
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 5 of 9)
Name Type
Function
After
Reset
TXTAL
PWR_EN nVDD_FAULT
VCCN
MA[7]
VSSN
MA[9]
MA[8]
MA[10]
MA[14] nOE nWE
GPIO[55]
VCCQ
VSSQ
GPIO[2]
PXTAL
MA[11]
MD[19]
VCCN
MA[2]
GPIO[4]
ICOCZ
ICOCZ
MA[2]
GPIO[4] nRESET IC nRESET nRESET_OUT OC nRESET_OUT nBATT_FAULT
VCC
VSSQ
MD[17]
IC
IA
IA
ICOCZ nBATT_FAULT
VCC
VSSQ
MD[17]
MA[3]
MA[4]
MA[5]
MA[6]
MD[18]
GPIO[3]
PEXTAL
TEXTAL
OCZ
OCZ
OCZ
OCZ
ICOCZ
ICOCZ
OA
OA
MA[3]
MA[4]
MA[5]
MA[6]
MD[18]
GPIO[3]
PEXTAL
TEXTAL
OCZ
OCZ
OCZ
OCZ
ICOCZ
IA
IA
ICOCZ
OCZ
IA
OCZ
OCZ
IA
OC
IC
IA
IA
OCZ
ICOCZ
IA
TXTAL
PWR_EN nVDD_FAULT
VCCN
MA[7]
VSSN
MA[9]
MA[8]
MA[10]
MA[14] nOE nWE
GPIO[55]
VCCQ
VSSQ
GPIO[2]
PXTAL
MA[11]
MD[19]
VCCN
Primary
Function
TXTAL
PWR_EN nVDD_FAULT
VCCN
MA[7]
VSSN
MA[9]
MA[8]
MA[10]
MA[14] nOE nWE
GPIO[55]
VCCQ
VSSQ
GPIO[2]
PXTAL
MA[11]
MD[19]
VCCN
MA[2]
GPIO[4] nRESET nRESET_OUT nBATT_FAULT
VCC
VSSQ
MD[17]
MA[3]
MA[4]
MA[5]
MA[6]
MD[18]
GPIO[3]
PEXTAL
TEXTAL
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— nPREG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4-14 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Ball#
M8
M11
M13
M14
M4
M5
M6
M7
M15
N9
N10
N11
N13
N5
N6
N7
N8
N14
N15
N16
N17
N1
N2
N3
N4
M16
M17
M18
N18
P4
P5
P6
P1
P2
P3
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 6 of 9)
Name
VSSN
MA[15]
VSSQ_F
VCCQ_F
VCC_F
VSS_F
VCCQ_F
WAIT_F1
GPIO[56]
GPIO[22]
GPIO[1]
GPIO[0]
MD[20]
MA[13]
MA[12]
MD[22]
MA[17]
VSSQ_F
VCCQ_F
VCC_F
MD[27]
NC
VCCQ_F
VSSQ_F
WAIT_F2
GPIO[49]
VCCN
GPIO[54]
GPIO[57]
VSSQ
MD[21]
MA[16]
VCCQ_F
MA[18]
MD[0]
Type
IA
OCZ
IA
IA
IA
IA
IA
OCZ
ICOCZ
OCZ
IA
IA
IA
ICOCZ
—
IA
IA
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OCZ
OCZ
ICOCZ
OCZ
ICOCZ
IA
ICOCZ
ICOCZ
IA
ICOCZ
OCZ
IA
OCZ
ICOCZ
Function
After
Reset
VSSN
MA[15]
VSSQ_F
VCCQ_F
VCC_F
VSS_F
VCCQ_F
WAIT_F1
GPIO[56]
GPIO[22]
GPIO[1]
GPIO[0]
MD[20]
MA[13]
MA[12]
MD[22]
MA[17]
VSSQ_F
VCCQ_F
VCC_F
MD[27]
—
VCCQ_F
VSSQ_F
WAIT_F2
GPIO[49]
VCCN
GPIO[54]
GPIO[57]
VSSQ
MD[21]
MA[16]
VCCQ_F
MA[18]
MD[0]
Primary
Function
GPIO[56]
GPIO[22]
GPIO[1]
GPIO[0]
MD[20]
MA[13]
MA[12]
MD[22]
MA[17]
VSSQ_F
VCCQ_F
VCC_F
MD[27]
—
VCCQ_F
VSSQ_F
WAIT_F2
GPIO[49]
VCCN
GPIO[54]
VSSN
MA[15]
VSSQ_F
VCCQ_F
VCC_F
VSS_F
VCCQ_F
WAIT_F1
GPIO[57]
VSSQ
MD[21]
MA[16]
VCCQ_F
MA[18]
MD[0]
Alternate
Function 1
—
MMCCLK nIOIS16
USB_nOE
—
—
—
—
—
—
—
—
—
—
—
—
—
HWRXD
—
—
—
—
—
—
—
— nPWAIT
USB_VMO
— nGP_RST
—
—
—
—
—
—
—
Alternate
Function 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— nPWE
— nPSKTSEL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Alternate
Function 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-15
Pin Listing and Signal Definitions
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 7 of 9)
Ball#
R18
T1
T2
T3
R14
R15
R16
R17
T4
T5
T6
T7
R10
R11
R12
R13
R6
R7
R8
R9
R2
R3
R4
R5
P16
P17
P18
R1
P12
P13
P14
P15
P7
P8
P9
P10
Name
VCC
VCCN
GPIO[50]
GPIO[53]
GPIO[19]
MA[19]
VCCN
VSSQ
VCCN
VSSQ
MD[6] nCS[0]
VSSN
MD[11]
VCCQ_F
VSSQ_F
MD[23]
MA[24]
MD[24]
VSSN
VSSQ
VCC
GPIO[21]
VCCN
VCC
MA[20]
MA[23]
MA[25]
MD[25]
VCCN
MD[8]
VSS_F
VCCQ_F
MD[14]
MD[15]
GPIO[48]
Type
IA
IA
ICOCZ
ICOCZ
ICOCZ
OCZ
IA
IA
IA
IA
ICOCZ
ICOCZ
IA
ICOCZ
IA
IA
ICOCZ
OCZ
ICOCZ
IA
IA
IA
ICOCZ
IA
IA
OCZ
OCZ
OCZ
ICOCZ
IA
ICOCZ
IA
IA
ICOCZ
ICOCZ
ICOCZ
Primary
Function
—
—
HWCTS
MMCCLK
DREQ[1]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HWTXD
VCC
VCCN
GPIO[50]
GPIO[53]
GPIO[19]
MA[19]
VCCN
VSSQ
VCCN
VSSQ
MD[6] nCS[0]
VSSN
MD[11]
VCCQ_F
VSSQ_F
MD[23]
MA[24]
MD[24]
VSSN
VSSQ
VCC
GPIO[21]
VCCN
VCC
MA[20]
MA[23]
MA[25]
MD[25]
VCCN
MD[8]
VSS_F
VCCQ_F
MD[14]
MD[15]
GPIO[48]
Function
After
Reset
VCC
VCCN
GPIO[50]
GPIO[53]
GPIO[19]
MA[19]
VCCN
VSSQ
VCCN
VSSQ
MD[6] nCS[0]
VSSN
MD[11]
VCCQ_F
VSSQ_F
MD[23]
MA[24]
MD[24]
VSSN
VSSQ
VCC
GPIO[21]
VCCN
VCC
MA[20]
MA[23]
MA[25]
MD[25]
VCCN
MD[8]
VSS_F
VCCQ_F
MD[14]
MD[15]
GPIO[48]
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
—
— nPIOR nPCE[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— nPOE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4-16 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Pin Listing and Signal Definitions
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 8 of 9)
Ball#
U18
V1
V2
V3
U14
U15
U16
U17
V4
V5
V6
V7
U10
U11
U12
U13
U6
U7
U8
U9
U2
U3
U4
U5
T16
T17
T18
U1
T12
T13
T14
T15
T8
T9
T10
T11
Name
MD[31]
MD[12]
GPIO[33]
VSSN
VSSN
VSSN
VSSN
VCCN
MD[3]
MD[2]
MD[4]
VSSN
GPIO[15]
GPIO[79]
MD[10]
VSSQ
MA[21]
VSSN
MD[1]
VCCN
GPIO[20]
GPIO[51]
GPIO[52]
VSSN
VSSN
VSS
VCCN
MA[22]
MD[5]
MD[26]
DQM[0]
VCCN
MD[28]
VCCN
VSSN
MD[13]
Type
IA
IA
IA
IA
ICOCZ
ICOCZ
ICOCZ
IA
ICOCZ
ICOCZ
ICOCZ
IA
ICOCZ
ICOCZ
ICOCZ
IA
OCZ
IA
ICOCZ
IA
ICOCZ
ICOCZ
ICOCZ
IA
IA
IA
IA
OCZ
ICOCZ
ICOCZ
OCZ
IA
ICOCZ
IA
IA
ICOCZ
Primary
Function
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DREQ[0]
HWRTS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MD[31]
MD[12]
GPIO[33]
VSSN
VSSN
VSSN
VSSN
VCCN
MD[3]
MD[2]
MD[4]
VSSN
GPIO[15]
GPIO[79]
MD[10]
VSSQ
MA[21]
VSSN
MD[1]
VCCN
GPIO[20]
GPIO[51]
GPIO[52]
VSSN
VSSN
VSS
VCCN
MA[22]
MD[5]
MD[26]
DQM[0]
VCCN
MD[28]
VCCN
VSSN
MD[13]
Function
After
Reset
MD[31]
MD[12]
GPIO[33]
VSSN
VSSN
VSSN
VSSN
VCCN
MD[3]
MD[2]
MD[4]
VSSN
GPIO[15]
GPIO[79]
MD[10]
VSSQ
MA[21]
VSSN
MD[1]
VCCN
GPIO[20]
GPIO[51]
GPIO[52]
VSSN
VSSN
VSS
VCCN
MA[22]
MD[5]
MD[26]
DQM[0]
VCCN
MD[28]
VCCN
VSSN
MD[13]
Alternate
Function 1
Alternate
Function 2
Alternate
Function 3
—
—
—
—
—
—
—
—
—
— nCS[5]
—
—
—
—
— nCS[1] nCS[3]
—
—
— nPIOW nPCE[1]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
4-17
Pin Listing and Signal Definitions
Table 4-2. PXA26x Processor Family Pin Out - Ballpad Number Order (Sheet 9 of 9)
Ball#
V12
V13
V14
V15
V8
V9
V10
V11
V16
V17
V18
Name
VCC
MD[7]
DQM[3]
GPIO[78]
MD[9]
MD[29]
MD[30]
VSSN
GPIO[80]
VSSN
VSSN
Type
IA
ICOCZ
OCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
IA
ICOCZ
IA
IA
Function
After
Reset
VCC
MD[7]
DQM[3]
GPIO[78]
MD[9]
MD[29]
MD[30]
VSSN
GPIO[80]
VSSN
VSSN
Primary
Function
VCC
MD[7]
DQM[3]
GPIO[78]
MD[9]
MD[29]
MD[30]
VSSN
GPIO[80]
VSSN
VSSN
Alternate
Function 1
—
—
—
—
—
—
—
—
—
—
—
Alternate
Function 2
—
—
—
—
—
—
— nCS[2] nCS[4]
—
—
Alternate
Function 3
—
—
—
—
—
—
—
—
—
—
—
Table 4-3. Signal Types
Type
IC
OC
OCZ
ICOCZ
IA
OA
IAOA
IAOAZ
CMOS Input
CMOS output
CMOS output, three-stateable
CMOS bidirectional, three-stateable
Analog Input
Analog output
Analog bidirectional
Analog bidirectional - three-stateable
Description
4-18 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Electrical Specifications
5
5.1
Absolute Maximum Ratings
The absolute maximum ratings (shown in
Table 5-1 ) define limitations for electrical and thermal
stresses that prevent permanent damage to the PXA26x processor family device. Operating outside of these absolute maximum ratings may result in permanent damage to the device.
Table 5-1. Absolute Maximum Ratings
Symbol
T
S
VSS_O
VCC_O
VCC_HV
VCC_LV
VIP
VIP_X
V
ESD
I
EOS
Description
STORAGE TEMPERATURE
VSS OFFSET VOLTAGE:
Between any two VSS pins: VSS, VSSQ, VSSN or VSS_F,
VSSQ_F
VCC OFFSET VOLTAGE:
Between these pins: VCCN and VCCQ_F
VCC VOLTAGE APPLIED TO HIGH VOLTAGE SUPPLIES:
VCCQ, VCCN, VCCQ_F, VCC_F
VCC VOLTAGE APPLIED TO LOW VOLTAGE SUPPLIES:
VCC, PLL_VCC)
VOLTAGE APPLIED TO NON-SUPPLY PINS:
Except XTAL pins
VOLTAGE APPLIED TO XTAL PINS:
PXTAL, PEXTAL, TXTAL, TEXTAL
MAXIMUM ESD STRESS VOLTAGE:
Any pin to any supply pin, either polarity, or
Any pin to all non-supply pins together, either polarity.
Three stresses maximum.
MAXIMUM DC INPUT CURRENT:
Electrical overstress for any non-supply pin
Minimum
-40
-0.3
-0.3
VSS - 0.3
VSS - 0.3
VSS - 0.3
VSS - 0.3
Maximum
125
0.3
0.3
VSS + 4.0
VSS + 1.65
VCCQ +0.3,
VSS + 4.0
VCC + 0.3,
VSS + 1.65
2000
5
Units
°C
V
V
V
V
V
V
V mA
5.2
Operating Conditions
This section shows operating voltage, frequency, and temperature specifications for the PXA26x processor family.
, shows the supported memory and core frequency operating ranges for specific ranges of the core and memory supply voltages. The operating temperature specification is a function of memory voltage or frequency.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 5-1
Electrical Specifications
Table 5-2. Voltage, Temperature, and Frequency Electrical Specifications
Symbol Description Minimum Typical Maximum Units
f
Operating Temperature
T case
Package Operating Temperature (Note 1)
Fixed Supply Voltages
V
VSS
Voltage applied on VSS, VSSN, VSSQ,
VSSQ_F and VSS_F
V
VCCQ_H
V
VCCQ_L
V
VCCN_H
V
VCCN_M
V
VCCN_L
VCCQ @ 3.3V
VCCQ @ 2.775V (Note 2)
VCCN and VCCQ_F @ 3.3V
VCCN and VCCQ_F @ 2.775V (Note 2)
VCCN and VCCQ_F @ 2.5V (Note 2)
V
VCC_F
VCC_F
Voltage and Frequency Range 1
V
VCC_1 f
TURBO_1
SDRAM_1
Voltage applied on VCC, PLL_VCC
Turbo Mode Frequency
External Synchronous Memory
Frequency
-25
-0.3
2.97 V
2.636 V
2.97 V
2.636 V
2.375 V
2.7 V
0.95
99.5
50
—
0
3.3 V
2.775 V
3.3 V
2.775 V
2.5 V
3.3 V
1.00
—
—
+85
0.3
3.6 V
2.97 V
3.6 V
2.97 V
2.636 V
3.6 V
1.1
118
99.5
°C
V
V
MHz
MHz f f
Voltage and Frequency Range 2
V
VCC_2 f
TURBO_2
Voltage applied on VCC, PLL_VCC
Turbo Mode Frequency
SDRAM_2
External Synchronous Memory
Frequency
Voltage and Frequency Range 3
V
VCC_3 f
TURBO_3
SDRAM_3
Voltage applied on VCC, PLL_VCC
Turbo Mode Frequency
External Synchronous Memory
Frequency
0.95
99.5
50
1.045
99.5
50
1.0
—
—
1.1
—
—
1.1
199.1
99.5
1.21
298.7
99.5
V
MHz
MHz
V
MHz
MHz f
Voltage and Frequency Range 4 (PXA260, PXA261 and PXA263 Only)
V
VCC_3 f
TURBO_3
Voltage applied on VCC, PLL_VCC
Turbo Mode Frequency
1.235
99.5
SDRAM_3
External Synchronous Memory
Frequency
50
1.3
—
—
1.43
398.2
99.5
V
MHz
MHz
NOTES:
1. System design must ensure that the device case temperature is maintained within the specified limits. In some system applications it may be necessary to use external thermal management measures (e.g., a package-mounted heat spreader) or to configure the device appropriately to limit device power consumption and maintain acceptable case temperatures.
2. When VCCQ = 2.775 or VCCN = 2.5 V/2.775 V, the I/O signals that are supplied by VCCQ/VCCN are 2.5 V or 2.775 V tolerant only. Do not apply 3.3 V to any pin supplied by VCCQ or VCCN in this case.
V
V
V
V
V
V
5-2 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Electrical Specifications
5.3
Power Consumption Specifications
Power consumption depends on the operating voltage, peripherals enabled, external switching activity, and external loading.
Specifying maximum power consumption requires all units be run at their maximum performance, and at maximum voltage and loading conditions. The maximum power consumption of the
PXA26x processor family is calculated using these conditions:
•
All peripheral units operating at maximum frequency and size configuration
•
All I/O loads maximum (50 pF)
•
Core operating at worst-case power scenario (hit rates adjusted for worst power)
•
All voltages at maximum of range
•
Maximum case temperature
Do not exceed the maximum package power rating or T case
temperature.
Since few systems operate at maximum loading, performance, and voltage, a more optimal system design requires more typical power consumption figures. These figures are important when considering battery size and optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load. The typical power consumption for the PXA26x processor family is calculated using these conditions:
•
SSP, STUART, USB, PWM, timer, I2S peripherals operating
•
LCD enabled with 320x240x16-bit color
•
MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled
•
I/O loads at nominal (35 pf for all pins)
•
Core operating at 98% instruction hit rate, 95% data hit rate, run mode
•
All voltages at nominal values
•
Nominal case temperature
Table 5-3 contains power consumption numbers for the PXA260.
contains power consumption numbers for the PXA261.
Table 5-5 contains power consumption numbers for the
PXA262.
Table 5-6 contains power consumption numbers for the PXA263.
Table 5-3. Power Consumption Specifications for PXA260 (Sheet 1 of 2)
Symbol Description Typical Maximum
400 MHz active mode, Maximum: V
Typical: V cc
=1.3V, V ccq
/V cc
=1.43V, V ccq
/V ccn
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
I ccp
V
V cc
Current ccq
and V ccn
Current
245
28
693
355
P
TOTAL
Total Power 411 2270
300 MHz active mode, Maximum: V
Typical: V cc
=1.1V, V ccq
/V cc
=1.21V, V ccq
/V ccn
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
V cc
Current 185 482
I ccp
V ccq
and V ccn
Current 24 345
Units
mA mA mW mA mA
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 5-3
Electrical Specifications
5-4
Table 5-3. Power Consumption Specifications for PXA260 (Sheet 2 of 2)
Symbol Description Typical Maximum
P
TOTAL
Total Power 283
200 MHz active mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
115 I ccc
I ccp
P
TOTAL
V cc
Current
V ccq
and V ccn
Current
Total Power
19
178
1826
283
330
1500
400 MHz idle mode, Maximum: V cc
Typical: V cc
=1.3V, V ccq
/V ccn
=1.43V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
70
9
P
TOTAL
Total Power 121
300 MHz idle mode, Maximum: V cc
Typical: V cc
=1.1V, V ccq
/V ccn
=1.21V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I ccc
V cc
Current 43
P
I ccp
TOTAL
V ccq
and V ccn
Current
Total Power
9
77
200 MHz idle mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
33
9
399
50
751
283
50
522
171
50
P
TOTAL
Total Power 63
33 MHz idle mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
V cc
Current 15
I ccp
P
TOTAL
V ccq
and V ccn
Total Power
Current 9
45
Sleep mode, Maximum: V cc
=0V, V ccq
/V ccn
=3.3V, Temp=Room
I ccp
V ccq
and V ccn
Current 45
368
58
50
244
75
Fast sleep wakeup mode, Maximum: V cc
=1.0/1.1/1.3V, V ccq
/V ccn
=3.3V, Temp=Room
I ccc
V cc
Current TBD TBD
I ccp
V ccq
and V ccn
Current TBD TBD
Table 5-4. Power Consumption Specifications for PXA261 (Sheet 1 of 2)
Symbol Description Typical Maximum
400 MHz active mode, Maximum: V cc
Typical: V cc
=1.3V, V ccq
/V ccn
=1.43V, V
=3.3V, Temp=Room ccq
/V ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
245
44
693
425
P
TOTAL
Total Power 464 2521
300 MHz active mode, Maximum: V cc
Typical: V cc
=1.1V, V ccq
/V ccn
=1.21V, V
=3.3V, Temp=Room ccq
/V ccn
=3.6V, Temp=100C
Units
mW mA mA mW mA mA mW mA mA mW mA mA mW mA mA mW
µA
µA
µA
Units
mA mA mW
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Electrical Specifications
Table 5-4. Power Consumption Specifications for PXA261 (Sheet 2 of 2)
Symbol Description Typical Maximum
I ccc
I ccp
I ccp
P
TOTAL
V cc
Current
V ccq
and V ccn
Current
V ccq
and V ccn
Current
Total Power
185
40
P
TOTAL
Total Power 336
200 MHz active mode, Maximum: V
Typical: V cc
=1.0V, V ccq
/V cc
=1.1V, V ccq
/V ccn
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
V cc
Current 115
2077
283
35
230
482
415
400
1751
400 MHz idle mode, Maximum: V
Typical: V cc
=1.3V, V ccq
/V ccn cc
=1.43V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I ccc
I ccp
V
V cc
Current ccq
and V ccn
Current
70
9
399
50
P
TOTAL
Total Power 121
300 MHz idle mode, Maximum: V
Typical: V cc
=1.1V, V ccq
/V ccn cc
=1.21V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I ccc
V cc
Current 43
I ccp
P
TOTAL
V ccq
and V ccn
Total Power
Current 9
77
200 MHz idle mode, Maximum: V
Typical: V cc
=1.0V, V ccq
/V ccn cc
=1.1V, V ccq
/V ccn
=3.6V, Temp=100C
=3.3V, Temp=Room
751
283
50
522
I
I ccc ccp
P
TOTAL
P
TOTAL
63
33 MHz idle mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
I ccp
V cc
Current
V ccq
and V ccn
Current
Total Power
V
V cc
Current ccq
and V ccn
Total Power
Current
33
9
15
9
45
Sleep mode, Maximum: V cc
=0V, V ccq
/V ccn
=3.3V, Temp=Room
I ccp
V ccq
and V ccn
Current 75
171
50
368
58
50
244
130
Fast sleep wakeup mode, Maximum: V cc
=1.0/1.1/1.3V, V ccq
/V ccn
=3.3V, Temp=Room
I ccc
I ccp
V
V cc
Current ccq
and V ccn
Current
TBD
TBD
TBD
TBD
Table 5-5. Power Consumption Specifications for PXA262 (Sheet 1 of 2)
Symbol Description Typical Maximum
300 MHz active mode, Maximum: V
Typical: V cc
=1.1V, V ccq
/V cc
=1.21V, V ccq
/V ccn
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
I ccp
V
V cc
Current ccq
and V ccn
Current
185
40
482
415
Units
mA mA mW mA mA mW mA mA mW mA mA mW mA mA mW mA mA mW
µA
µA
µA
Units
mA mA
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 5-5
Electrical Specifications
5-6
Table 5-5. Power Consumption Specifications for PXA262 (Sheet 2 of 2)
Symbol Description Typical Maximum
P
TOTAL
Total Power 336
200 MHz active mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
115 I ccc
I ccp
P
TOTAL
V cc
Current
V ccq
and V ccn
Current
Total Power
35
230
2077
283
400
1751
300 MHz idle mode, Maximum: V cc
Typical: V cc
=1.1V, V ccq
/V ccn
=1.21V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
43
9
P
TOTAL
Total Power 77
200 MHz idle mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
V cc
Current 33
P
I ccp
TOTAL
V ccq
and V ccn
Current
Total Power
9
63
33 MHz idle mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
15
9
283
50
523
171
50
368
58
50
P
TOTAL
Total Power 45
Sleep mode, Maximum: V cc
=0V, V ccq
/V ccn
=3.3V, Temp=Room
244
I ccp
V ccq
and V ccn
Current 105 185
Fast sleep wakeup mode, Maximum: V cc
=1.0/1.1, V ccq
/V ccn
=3.3V, Temp=Room
I ccc
I ccp
V cc
Current
V ccq
and V ccn
Current
TBD
TBD
TBD
TBD
Table 5-6. Power Consumption Specifications for PXA263 (Sheet 1 of 2)
Symbol Description Typical Maximum
400 MHz active mode, Maximum: V cc
Typical: V cc
=1.3V, V ccq
/V ccn
=1.43V, V
=3.3V, Temp=Room ccq
/V ccn
=3.6V, Temp=100C
I ccc
V cc
Current 245 693
P
I ccp
TOTAL
V ccq
and V ccn
Current
Total Power
60
516
495
2773
300 MHz active mode, Maximum: V cc
Typical: V cc
=1.1V, V ccq
/V ccn
=1.21V, V
=3.3V, Temp=Room ccq
/V ccn
=3.6V, Temp=100C
I
I ccc ccp
V cc
Current
V ccq
and V ccn
Current
185
56
482
485
P
TOTAL
Total Power 388
200 MHz active mode, Maximum: V cc
Typical: V cc
=1.0V, V ccq
/V ccn
=1.1V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
2329
Units
mW mA mA mW mA mA mW mA mA mW mA mA mW
µA
µA
µA
Units
mA mA mW mA mA mW
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Electrical Specifications
5.4
Table 5-6. Power Consumption Specifications for PXA263 (Sheet 2 of 2)
Symbol Description Typical Maximum
I ccc
I ccp
I ccp
P
TOTAL
V cc
Current
V ccq
and V ccn
Current
V ccq
and V ccn
Current
Total Power
115
51
P
TOTAL
Total Power 283
400 MHz idle mode, Maximum: V
Typical: V cc
=1.3V, V ccq
/V ccn cc
=1.43V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I ccc
V cc
Current 70
9
121
300 MHz idle mode, Maximum: V
Typical: V cc
=1.1V, V ccq
/V ccn cc
=1.21V, V ccq
=3.3V, Temp=Room
/V ccn
=3.6V, Temp=100C
I ccc
I ccp
V
V cc
Current ccq
and V ccn
Current
43
9
283
470
2003
399
50
751
283
50
P
TOTAL
Total Power 77
200 MHz idle mode, Maximum: V
Typical: V cc
=1.0V, V ccq
/V ccn cc
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I ccc
V cc
Current 33
I ccp
P
TOTAL
V ccq
and V ccn
Total Power
Current 9
63
33 MHz idle mode, Maximum: V
Typical: V cc
=1.0V, V ccq
/V ccn cc
=1.1V, V ccq
/V
=3.3V, Temp=Room ccn
=3.6V, Temp=100C
I
I ccc ccp
P
TOTAL
V cc
Current
V ccq
and V ccn
Current
Total Power
15
9
45
Sleep mode, Maximum: V cc
=0V, V ccq
/V ccn
=3.3V, Temp=Room
522
171
50
368
58
50
244
I ccp
V ccq
and V ccn
Current 105 185
Fast sleep wakeup mode, Maximum: V cc
=1.0/1.1/1.3V, V ccq
/V ccn
=3.3V, Temp=Room
I ccc
I ccp
V cc
Current
V ccq
and V ccn
Current
TBD
TBD
TBD
TBD mA mA mW
µA
µA
µA
Units
mA mA mW mA mA mW mA mA mW mA mA mW
DC Specifications
The DC specifications for each pin include input sense levels, output drive levels, and currents.
These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. The DC operating conditions for the high- and low-strength input, output, and I/O pins are shown in
Table 5-7 . All DC specification values are valid for the entire
temperature range of the device.
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 5-7
Electrical Specifications
5.5
Table 5-7. Standard Input, Output, and I/O Pin DC Operating Conditions
Symbol Description
Input DC Operating Conditions
V
IH
INPUT HIGH VOLTAGE:
Standard input and I/O pins, relative to applicable VCC (VCCQ, VCCN, or
VCCQ_F)
V
IL
INPUT LOW VOLTAGE:
Standard input and I/O pins, relative to applicable VSS (VSSQ, VSSN, or
VSSQ_F) and VCC (VCCQ, VCCN, or
VCCQ_F)
I
IN
INPUT LEAKAGE:
Standard input and IO pins
Output DC Operating Conditions
I
I
I
I
V
V
OH
OL
OH_H
OH_L
OL_H
OL_L
OUTPUT HIGH VOLTAGE:
Standard output and I/O pins, relative to applicable VCC (VCCQ, VCCN, or
VCCQ_F)
OUTPUT LOW VOLTAGE:
Standard output and I/O pins, relative to applicable VSS (VSSQ, VSSN, or
VSSQ_F)
OUTPUT HIGH CURRENT:
Standard, high-strength output and I/O pins (VO=VOH)
OUTPUT HIGH CURRENT:
Standard, low-strength output and I/O pins (VO=VOH)
OUTPUT LOW CURRENT:
Standard, high-strength output and I/O pins (VO=VOH)
OUTPUT LOW CURRENT:
Standard, low-strength output and I/O pins (VO=VOH)
Minimum
0.8*VCC
VSS
VCC-0.1
VSS
-10
-3
10
3
Typical Maximum Units
VCC
0.2*VCC
10
VCC
VSS+0.4
V
V
µA
V
V mA mA mA mA
5.5.1
Oscillator Electrical Specifications
The processor contains two oscillators, each for a specific crystal: a 32.768-kHz oscillator and a
3.6864-MHz oscillator. When choosing a crystal, match the crystal parameters as closely as possible.
32.768-KHz Oscillator Specifications
The 32.768-kHz oscillator is connected between the TXTAL (amplifier input) and TEXTAL
(amplified output).
Table 5-8 shows the 32.768-kHz specifications.
5-8 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
Electrical Specifications
Table 5-8. 32.768-kHz Crystal Specifications
Symbol Description
Crystal Specifications - Typical is FOX NC38
F
XT
ESR
Crystal Frequency, TXTAL/TEXTAL
Equivalent series resistance, TXTAL/TEXTAL
P Drive Level
Amplifier Specifications
VIH_X Input High Voltage, TXTAL
VIL_X Input Low Voltage, TXTAL
IIN_XT Input Leakage, TXTAL
CIN_XT Input Capacitance, TXTAL/TEXTAL tS_XT Stabilization Time
Board Specifications
RP_XT Parasitic Resistance, TXTAL/TEXTAL to any node
CP_XT Parasitic Capacitance, TXTAL/TEXTAL, total
COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL
Min Typical Max Units
—
6
—
0.8*VCC
VSS
2
18
-
VCC
0.2*VCC
1
25
10
V
V
µA pF s
20
32.768
—
—
—
65
1
5
0.4
kHz k
Ω uW
M Ω pF pF
To drive the 32.768-kHz crystal pins from an external source
•
Drive the TEXTAL pin with a digital signal that has a low level near 0 volts and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 volt per 1 µs. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA.
•
Float the TXTAL pin or drive it complementary to the TXETAL pin, with the same voltage level, slew rate, and input current restrictions.
5.5.2
3.6864-MHz Oscillator Specifications
The 3.6864-MHz oscillator is connected between the PXTAL (amplifier input) and PEXTAL
(amplified output).
Table 5-9 shows the 3.6864-MHz specifications.
Table 5-9. 3.6864-MHz Crystal Specifications (Sheet 1 of 2)
Symbol Description
Crystal Specifications - Typical is FOX HC49S
F
XP
ESR
Crystal Frequency, PXTAL/PEXTAL
Equivalent series resistance, TXTAL/TEXTAL
P Drive Level
Amplifier Specifications
VIH_X Input High Voltage, PXTAL
Min
—
50
—
0.8*VCC
Typical
3.6864
-
—
Max
—
300
100
VCC
Units
MHz
Ω uW
V
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 5-9
Electrical Specifications
Table 5-9. 3.6864-MHz Crystal Specifications (Sheet 2 of 2)
Symbol Description
VIL_X Input Low Voltage, PXTAL
IIN_XP Input Leakage, PXTAL
CIN_XP Input Capacitance, PXTAL/PEXTAL
Min
VSS
Typical
40
Max
0.2*VCC
10
50
Units
V
µA pF
To drive the 3.6864-MHz crystal pins from an external source
•
Drive the PEXTAL pin with a digital signal with a low level near 0 volts and a high level near
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is
1 volt per 100 ns. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA.
•
Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system; therefore, it is not recommended.
5-10 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
AC Timing Specifications
6
A pin’s AC characteristics include input and output capacitance that determine loading for external drivers or other load analysis. The AC characteristics also include a derating factor, which indicates
how much faster or slower the AC timings perform under different loads. Table 6-1
shows the AC operating conditions for the high- and low-strength input, output, and I/O pins. All AC specification values are valid for the entire temperature range of the device.
Table 6-1. Standard Input, Output, and I/O Pin AC Operating Conditions
Symbol Description Minimum Typical Maximum Units
C
C
IN
OUT_H
INPUT CAPACITANCE:
Standard input and IO pins
OUTPUT CAPACITANCE:
Standard high-strength output and IO pins
—
20
1
—
— td td
F_H
R_H
OUTPUT DERATING:
Falling edge on all standard, highstrength output and I/O pins, from 50 pF load.
OUTPUT DERATING:
Rising edge on all standard, highstrength output and I/O pins, from 50 pF load.
—
—
—
—
NOTE: 1. AC Specifications guaranteed for loads in this range. All testing is done at 50 pF
10
50
1
—
— pF pF ns/pF ns/pF
6.1
AC Test Conditions
The AC specifications in
Section 6 are tested with a 50 pF load indicated in Figure 6-1
.
Figure 6-1. AC Test Load
Output Ball
C
L
= 50pF
C
L
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-1
AC Timing Specifications
6.2
Reset and Power Manager AC Timing Specifications
The PXA26x processor family asserts the nRESET_OUT pin in one of these modes:
•
Power on
•
Hardware reset
•
Watchdog reset
•
GPIO reset
•
Sleep mode
The following subsections provide the timing and specifications for entering and exiting these modes.
6.2.1
Power On Timing
The external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operation. This sequence is shown in
Figure 6-2, “Power-On Reset Timing” on page 6-3 and detailed in Table 6-2, “Power-On Timing
On the processor, it is important that the power supplies be powered up in a certain order to avoid high current situations. The required order is as follows:
1. VCCQ
2. VCCN
3. VCC and PLL_VCC
On the processor, it is important that the VCCQ power supply be powered up before or at the same time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up anytime within the specification shown in
.
Note: If a hardware reset is entered during sleep mode, the proper power-supply stabilization times and nRESET timing requirements must be observed as indicated in
6-2 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
AC Timing Specifications
Figure 6-2. Power-On Reset Timing t
R_VCCQ
VCCQ, PWR_EN
VCCN t
R_VCCN t
D_VCCN t
D_VCC t
R_VCC
VCC nTRST t
D_NTRST
JTAG PINS t
D_JTAG nRESET t
D_NRESET nRESET_OUT t
D_OUT
NOTE: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is de-asserted or the processor enters sleep mode.
NOTE: The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ.
The use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system’s power management requirements. VCCN and VCC do not depend on the PWR_EN signal being asserted.
Table 6-2. Power-On Timing Specifications
Symbol
t
R_VCCQ t
R_VCCN t
R_VCC t
D_VCCN t
D_VCC t
D_NTRST t
D_JTAG t
D_NRESET t
D_OUT t
D_NCS0
Description
VCCQ rise / Stabilization time
VCCN rise / Stabilization time
VCC, PLL_VCC rise / Stabilization time
Delay between VCCQ stable and VCCN applied
Delay from VCCN stable and VCC, PLL_VCC applied
Delay between VCC, PLL_VCC stable and nTRST deasserted
Delay between nTRST deasserted and JTAG pins active, with nRESET asserted
Delay between VCC, PLL_VCC stable and nRESET deasserted
Delay between nRESET deasserted and nRESET_OUT deasserted
Delay between nReset_Out and nCS0
6.2.2
Minimum
0.01 ms
0.01 ms
0.01 ms
0 ms
-10 ms
10 ms
0.03 ms
10 ms
18.1 ms
400 ns
Typical
—
—
—
—
—
—
—
—
—
—
Maximum
100 ms
100 ms
10 ms
—
—
—
—
—
18.2 ms
420 ns
Hardware Reset Timing
The timing sequences shown in
assume the power supplies are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings indicated in
Section 6.2.1, “Power On Timing” on page 6-2 .
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-3
AC Timing Specifications
Figure 6-3. Hardware Reset Timing nRESET nRESET_OUT t
DHW_NRESET t
DHW_OUT t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or the processor enters sleep mode
Table 6-3. Hardware Reset Timing Specifications
Symbol
t
DHW_NRESET t
DHW_OUT_A t
DHW_OUT t
DHW_NCS0
Description
Minimum assertion time of nRESET
Delay between nRESET asserted and nRESET_OUT asserted
Delay between nRESET de-asserted and nRESET_OUT deasserted
Delay between nRESET_OUT de-asserted and nCS0 asserted
6.2.3
Minimum
0.001 ms
0 ms
18.1 ms
400 ns
Typical
—
—
—
—
Maximum
—
0.001 ms
18.2 ms
420 ns
Watchdog Reset Timing
Watchdog reset is generated internally and therefore has no external pin dependencies. The nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for t
DHW_OUT
.
Refer to
Figure 6-3, “Hardware Reset Timing” for more information.
6.2.4
GPIO Reset Timing
GPIO reset is generated externally. The pin used as the GPIO reset is reconfigured as a standard
GPIO after the reset propagates internally. Because a GPIO reset does not reset the clock module, timing varies based on the frequency of the selected clock. Timing also varies in the frequency change sequence.
Figure 6-4 shows the possible GPIO reset timing.
Figure 6-4. GPIO Reset Timing
t
A_GP[1]
GP[1] nRESET_OUT
t
DHW_OUT
t
DHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or the application processor will enter Sleep Mode
6-4 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
AC Timing Specifications
Table 6-4. GPIO Reset Timing Specifications
Symbol Description Minimum Typical Maximum
t t
A_GP[1]
DGP_OUT_A
Minimum assert time of GP[1]
1
in 3.6864-MHz input clock cycles
Delay between GP[1] asserted and nRESET_OUT asserted in
3.6864-MHz input clock cycles
4 cycles
3 cycles
—
—
—
8 cycles t t
DGP_OUT
DGP_OUT_F
Delay between nRESET_OUT asserted and nRESET_OUT deasserted, run or turbo mode
2
Delay between nRESET_OUT asserted and nRESET_OUT deasserted, during frequency change sequence
3
1.28
1.28
µs
µs
—
—
6.5
360
µs
µs t
DGP_NCS0
Delay between nRESET_OUT and nCS0 150.69 ns — 390 ns
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of
GP[1] before configuring it as a reset to ensure no spurious reset is generated.
2. Time is 512*N processor clock cycles plus as many as 4 cycles of the 3.6864-MHz input clock.
3. Time during the frequency change sequence depends on the state of the PLL lock detector at the assertion of GPIO reset.
The lock detector has a maximum time of 350 us plus synchronization.
6.2.5
Sleep Mode Timing
Sleep mode is asserted internally, and asserts the nRESET_OUT and PWR_EN signals. The
sequence indicated in Figure 6-5
and detailed in
Table 6-5 are the required timing parameters for
sleep mode.
Figure 6-5. Sleep Mode Timing t
A_GP[x]
GP[x]
PWR_EN
VCC nVDD_FAULT nRESET_OUT
t
D_PWR_F t
D_PWR_R t
D_FAULT t
DSM_VCC t
DSM_OUT
Note: nBATT_FAULT must be high or the processor will not exit sleep mode
Table 6-5. Sleep Mode Timing Specifications (Sheet 1 of 2)
Symbol
t
A_GP[x} t
D_PWR_F t
D_PWR_R t
DSM_VCC
Description
Assert time of GPIO wake up source (x=[15:0])
Delay from nRESET_OUT asserted to PWR_EN deasserted
Delay between GP[x] asserted to PWR_EN asserted
Delay between PWR_EN asserted and VCC stable
Minimum
91.6
µs
61 µs
30.5
µs
—
Typical
—
—
—
—
Maximum
—
91.6
µs
122.1
µs
10 ms
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-5
AC Timing Specifications
Table 6-5. Sleep Mode Timing Specifications (Sheet 2 of 2)
Symbol
t
D_FAULT t
DSM_OUT_F t
DSM_OUT_O t
DSM_NCS0
Description
Delay between PWR_EN asserted and nVDD_FAULT deasserted
Delay between PWR_EN asserted and nRESET_OUT deasserted, FWAKE Set
Delay between PWR_EN asserted and nRESET_OUT deasserted, OPDE clear
Delay between nRESET_OUT and nCS0
Minimum
—
—
10.35 ms
180.84 ns
Typical
—
—
—
—
Maximum
10 ms
650 µs
10.5 ms
332 ns
Note:
For the parameter t
DSM_VCC
, VCC refers to the VCC supply internal to the processor. The internal VCC regulator must be stable within the stated maximum for the processor to function correctly. Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of the internal regulator and must be taken into account when designing the system.
6.3
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
•
SRAM / ROM / flash / synchronous fast flash asynchronous writes ( Table 6-6
)
•
Variable latency I/O (
Table 6-7 on page 6-7 )
•
Card interface (PCMCIA or compact flash) ( Table 6-8 on page 6-7 )
•
Synchronous memories (
Table 6-9 on page 6-7
)
Table 6-6. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
Symbol Description
tromAS tromAH
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) deasserted tromASW MA(25:0) setup to nWE asserted tromAHW MA(25:0) hold after nWE de-asserted tromCES nCS setup to nWE asserted tromCEH nCS hold after nWE de-asserted tromDS MD(31:0), DQM(3:0) write data setup to nWE asserted tromDSWH MD(31:0), DQM(3:0) write data setup to nWE de-asserted tromDH MD(31:0), DQM(3:0) write data hold after nWE deasserted tromNWE nWE high time between beats of write data
MEMCLKs
1
1
1
2
1
2
2
1
3
1
6-6 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
AC Timing Specifications
Table 6-7. Variable Latency I/O Interface AC Specifications
Symbol Description
tvlioAS MA(25:0) setubp to nCS asserted tvlioASRW MA(25:0) setup to nOE or nPWE asserted tvlioAH MA(25:0) hold after nOE or nPWE de-asserted tvlioCES nCS setup to nOE or nPWE asserted tvlioCEH nCS hold after nOE or nPWE de-asserted tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted tvlioDSWH
MD(31:0), DQM(3:0) write data setup to nPWE deasserted tvlioDHW MD(31:0), DQM(3:0) hold after nPWE de-asserted tvlioDHR MD(31:0) read data hold after nOE de-asserted tvlioRDYH RDY hold after nOE, nPWE de-asserted tvlioNPWE nPWE, nOE high time between beats of write or read data
MEMCLKs
1
2
1
1
1
1
2
0
2
1
0
Table 6-8. Card Interface (PCMCIA or Compact Flash) AC Specifications
Symbol Description MEMCLKs
tcardAS tcardAH
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or nPIOR asserted
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted
2
2 tcardDS tcardDH tcardCMD
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted nPWE, nPOE, nPIOW, or nPIOR command assertion
2
NOTE: These numbers are minimums. They can be much longer based on the programmable card interface timing registers.
2
2
Table 6-9. Synchronous Memory Interface AC Specifications (Sheet 1 of 2)
Symbol Description Minimum Maximum Notes
1
tsynCLK tsynCMD tsynRCD tsynCAS tsynSDOS tsynSDOH tsynSDIS tsynDIH
SDRAM / SMROM
SDCLK period nSDCAS, nSDRAS, nWE, nSDCS assert time nSDRAS to nSDCAS assert time nSDCAS to nSDCAS assert time
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise
MD(31:0) read data input setup time from SDCLK(2:0) rise
MD(31:0) read data input hold time from SDCLK(2:0) rise
10 ns
1 sdclk
1 sdclk
2 sdclk
5 ns
5 ns
0.5 ns
1.5 ns
20 ns
—
—
—
—
—
—
—
2
—
—
—
3
3
—
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-7
AC Timing Specifications
Table 6-9. Synchronous Memory Interface AC Specifications (Sheet 2 of 2)
Symbol Description Minimum Maximum Notes
1
tffCLK tffAS tffCES
Fast Flash (Synchronous READS only)
SDCLK period
MA(25:0) setup to nSDCAS (as nADV) asserted nCS setup to nSDCAS (as nADV) asserted
15 ns
0.5 sdclk
0.5 sdclk
20 ns
—
— tffADV tffOS nSDCAS (as nADV) pulse width nSDCAS (as nADV) de-assertion to nOE assertion
1 sdclk
3 sdclk
—
—
—
— tffCEH nOE deassertion to nCS de-assertion 4 sdclk — —
NOTES:
1. These numbers are for a maximum 99.5-MHz MEMCLK and 99.5-MHz output SDCLK.
2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5-MHz MEMCLK. It can be 99.5 MHz at the fastest.
3. This number represents 1/2 SDCLK period.
4. SDCLK for fast flash can be at the slowest, divide-by-2 of the 99.5-MHz MEMCLK. It can be divide-by-2 of the 132.7-MHz
MEMCLK at its fastest.
4
—
—
6.4
Peripheral Module AC Timing Specifications
This section describes the AC specifications for the LCD and the SSP peripheral units:
6.4.1
LCD Module AC Timing
Figure 6-6 describes the LCD timing parameters. The LCD pin timing specifications are referenced
to the pixel clock (L_PCLK). Values for the parameters are given in
Table 6-10 .
Figure 6-6. LCD AC Timing Definitions
L_PCLK
L_LDD[7:0]
(rise)
L_LDD[7:0]
(fall)
L_LCLK
L_BIAS
L_FCLK
Tpclkdv
Tpclklv
Tpclkbv
Tpclkfv
Tpclkdv
A4775-01
6-8 Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification
AC Timing Specifications
Table 6-10. LCD AC Timing Specifications
Symbol Description Min Max Units Notes
Tpclkdv
Tpclklv
Tpclkfv
Tpclkdv L_PCLK rise/fall to L_LDD<7:0> driven valid
L_PCLK fall to L_LCLK driven valid
L_PCLK fall to L_FCLK driven valid
0
-0.5
-0.5
3.5
2.0
2.0
ns ns ns
1
2
2
Tpclkbv L_PCLK rise to L_BIAS driven valid 5.524
12 ns 2
NOTES:
1. You can program the LCD data pins to be driven on either the rising or falling edge of the pixel clock
(L_PCLK).
2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.
6.4.2
SSP Module AC Timing
Figure 6-7, “SSP AC Timing Definitions” on page 6-9 describes the SSP timing parameters. The
SSP pin timing specifications are referenced to SCLK_C. Values for the parameters are given in
Table 6-11, “SSP AC Timing Specifications” on page 6-9 .
Figure 6-7. SSP AC Timing Definitions
SCLK_C
SFRM_C
TXD_C
RXD_C
Tsfmv
Tsfmv
Trxds Trxdh
A4774-01
Table 6-11. SSP AC Timing Specifications
Symbol
Tsfmv
Trxds
Trxdh
Tsfmv
Description
SCLK_C rise to SFRM_C driven valid
RXD_C valid to SCLK_C fall (input setup)
SCLK_C fall to RXD_C invalid (input hold)
SCLK_C rise to TXD_C valid
Min
11
0
Max
21
22
Units
ns ns ns ns
Notes
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-9
6.5
JTAG Boundary Scan AC Timing Specifications
Table 6-12 shows the boundary scan test signal timing.
Table 6-12. Boundary Scan Timing Specifications
Symbol Parameter
TBSF TCK Frequency
TBSCH TCK High Time
TBSCL TCK Low Time
TBSCR TCK Rise Time
TBSCF TCK Fall Time
TBSIS1 Input Setup to TCK TDI, TMS
TBSIH1 Input Hold from TCK TDI, TMS
TBSIS2 Input Setup to TCK nTRST
TBSIH2 Input Hold from TCK nTRST
TBSOV1 TDO Valid Delay
TOF1
TOV12
TOF2
TIS10
TIH8
TDO Float Delay
All Outputs (Non-Test) Valid
Delay
All Outputs (Non-Test) Float
Delay
Input Setup to TCK All Inputs
(Non-Test)
Input Hold from TCK All Inputs
(Non-Test)
1.5
1.1
4.0
6.0
4.0
6.0
25.0
3.0
1.5
1.1
Minimum Maximum Units
0.0
15.0
15.0
33.33
5.0
5.0
6.9
5.4
ns ns ns ns ns ns ns
MHz ns ns ns
Notes
Measured at 1.5 V
Measured at 1.5 V
0.8 V to 2.0 V
2.0 V to 0.8 V
Relative to falling edge of TCK
Relative to falling edge of TCK
6.9
5.4
ns ns ns ns
Relative to falling edge of TCK
Relative to falling edge of TCK
AC Timing Specifications
Intel® PXA26x Processor Family Electrical, Mechanical, and Thermal Specification 6-11
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Related manuals
advertisement