MCS® 51 Microcontroller Family User`s Manual

MCS® 51 Microcontroller Family User`s Manual
[email protected] MICROCONTROLLER
FAMILY USER’S MANUAL
ORDER
NO.: 272383-002
FEBRUARY
1994
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[email protected] 51 Family of
Microcontrollers
Architectural Overview
1
[email protected] FAMILY OF
MICROCONTROLLERS
ARCHITECTURAL
OVERVIEW
CONTENTS
INTRODUCTION
PAGE
.........................................1-3
CHMOS
Devices .....”.....’.......”.....-...-..........I-5
M;~$&:RGA-~oN INMc- 51
.................................................1-6
Lo ical Separation of Program and Data
h emoy ....................................................l+
Program Memo~ .........................................l-7
Data Memory ...............................................1 -8
THE MC951
INSTRUCTION
SET .............1 -9
Program Status Word ..................................1 -9
Addressing Modes .....................................l-l O
Arithmetic Instructions ...............................1-10
Logical lnstrudions
Data Tran#ers
....................................l.l2
...........................................l.l2
Boolean Instructions ..................................1-14
Jump Instructions ......................................1-16
CPU TIMING .............................................l-l7
Machine Cycles .........................................1-18
Interrupt Structure ......................................l.2O
ADDITIONAL
1-1
REFERENCES
...................1 -22
ir&L
[email protected]
ARCHITECTURAL
OVERVIEW
INTRODUCTION
The8051
is the original member of the MCW-51
family, and is the core for allMCS-51 devices. The features of the
8051 core are
● 8-bit CPU optimized for control applications
● Extensive Boolean processing (Single-blt logic) capabtilties
●
●
●
●
●
●
●
●
●
64K Program Memory address space
64K Data Memory address space
4K bytes of on-chip Program Memory
128 bytesof on-chip Data RAM
32 bidirectional and individually addressable 1/0 lines
Two 16-bit timer/counters
Full duplex UART
6-source/5-vector interrupt structure with two priority levels
On-chip clock oscillator
The basic architectural structure of this 8051 core is shown in Figure L
EXTERNAL
INTERRUPTS
,,
I
I
COUNTER
INPUTS
w
H
H
II
BUS
CONTROL
Q
SERIAL
PORT
4 1/0 PORTS
11
TXO
Po
P2
PI
RXD
P3
AODRESS/DATA
270251-1
Figure 1. Block Diagram of the 8051 Core
1-3
intd.
[email protected] ARCHITECTURAL
1-4
OVERVIEW
i~.
[email protected]’-5l ARCHITECTURAL
1-5
OVERVIEW
[email protected]
i~.
* -----------
8
1
1
1
1
1
1
1
I
1
ARCHITECTURAL
PROORAMMrhtosv
(REM ONLY)
-------------$
s
FFFFw
T
I
1
1
1
1
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1
1
1
-
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o
8
0
0
0
8
0
1
1
1
1
1
I
1
1
1
I
,
B
I
I
EXTERNAL
0
9
I
I
I
,
1
I
:
#
G=o
o
2STERNAL
0
1
0
@
*
I
:
● - ----------
m.1
IN7ERNAL
0000
--------
:
:
0
9
*
I
I
I
-.!
OVERVIEW
-----------------------t
8
I
1
I
8
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I
I
:
o
#
8
9
8
8
0
0
9
t
#
I
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1
: FfH:
OATAMEMORY
(RW/WRlT2)
. . . . .
8
8
I
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0
I
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0
I
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#
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I
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I
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1
EXIERNALm
-
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0
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------
0:
9,
e,
9
0
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1
I 00
,1+
1
● --------
0000
---------
..-
J:
-.
1%
-.-:
tiR
270251-2
Figure 2. MCW’-51 Memory Structure
CHMOS Devices
MEMORY ORGANIZATION
[email protected] DEVICES
Functionally, the CHMOS devices (designated with
“C” in the middle of the device name) me all fiuy
compatible with the 8051, but being CMOS, draw less
current than an HMOS counterpart. To further exploit
the power savings available in CMOS circuitry, two reduced power modes are added
●
Software-invoked Idle Mode, during which the CPU
is turned off while the RAM and other on-chip
peripherals continue operating. In this mode, current draw is reduced to about 15% of the current
drawn when the device is fully active.
●
Software-invoked Power Down Mode, during which
all on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
device typically draws less than 10 pA.
Logical Separation
Data Memory
IN
of Program and
AU MCS-51 devices have separate address spacea for
Program and Data Memory, as shown in Figure 2. The
logical separation of Program and Data Memory allows
the Data Memory to be acceased by 8-bit addressea,
which can be more quickly stored and manipulated by
an 8-bit CPU. Nevertheless, ld-bh Data Memory addresses can also be generated through the DPTR register.
Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory. In
the ROM and EPROM versions of these devices the
loweat 4K, 8K or 16K bytes of Program Memory are
provided on-chip. Refer to Table 1 for the amount of
on-chip ROM (or EPROM) on each device. In the
ROMleas versions all Program Memory is external.
The read strobe for external Program Memory is the
signal PSEN @rogram Store Enable).
Although the 80C51BH is functionally compatible with
its HMOS counterpart, s~lc
differeneea between the
two types of devices must be considered in the design of
an application circuit if one wiahea to ensure complete
interchangeability between the HMOS and CHMOS
devices. These considerations are discussed in the Ap
plieation Note AP-252, “Designing with the
80C5lBH.
For more information on the individual devices and
features listed in Table 1, refer to the Hardware De
scriptions and Data Sheets of the specific device.
1-6
intel.
[email protected] ARCHITECTURAL
OVERVIEW
The lowest 4K (or SK or 16K) bytes of Program Memory can be either in the on-chip ROM or in an external
ROM. This selection is made by strapping the ~ (External Access) pin to either VCC or Vss.
Data Memory occupies a separate addrexs space from
%OgrCt122 hkznory.
Up to 64K bytes of exterttd RAM
can be addreased in the externrd Data Memo~.
The CPU generatea read and write signals RD and
~,
as needed during external Data Memory accesses.
In the 4K byte ROM devices, if the=
pin is strapped
to VcC, then program fetches to addresses 0000H
through OFFFH are directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are
directed to external ROM.
External Program Memory and external Data Memory
~~
combined if-desired by applying the ~
~d
PSEN signals to the inputs of an AND gate and using
the output of the gate as the read strobe to the external
Program/Data memory.
ProgramMemory
In the SK byte ROM devices, = = Vcc selects addresses (XtOOHthrough lFFFH to be internal, and addresses 2000H through F’FFFH to be external.
Figure 3 shows a map of the lower part of the Program
Memory. After reset, the CPU begins execution from
location OWOH.
In the 16K byte ROM devices, = = VCC selects addresses 0000H through 3FFFH to be internal, and addresses 4000H through FFFFH to be external.
AS shown in [email protected] 3, each interrupt is assigned a tixed
location in Program Memory. The interrupt causes the
CPU to jump to that location, where it commences execution of the serviee routine. External Interrupt O, for
example, is assigned to location 0003H. If External Interrupt O is going to & used, its service routine must
begin at location 0003H. If the interrupt is not going to
be used, its service location is available as general purpose Program Memory.
If the ~ pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMleas
parts must have this pin externally strapped to VSS to
enable them to execute properly.
The read strobe to externally:
PSEN, is used for all
external oro.cram fetches. PSEN LSnot activated for in-
‘s
&
..-.
(O033H)
m%
1
l== 1
EPROM
INSTR.
Po
m
002EH
=
ALE
002SH
INTSRRUPT
LOCATIONS
LArcn
Ssvrm
0013H II
270251-4
000SH
0003H
R2S~
i
AOOR
a’s ‘z~
00IBH
Figure 4. Executing from External
Program Memory
0000H
270251-3
Figure 3. MCW’-51
The hardware configuration for external program execution is shown in Figure 4. Note that 16 I/O lines
(Ports O and 2) are dedicated to bus fictions during
external Program Memory f~hes. Port O(PO in Figure
4) servex as a multiplexed address/data bus. It emits
the low byte of the Program Counter (PCL) as an address, snd then goes into a float state awaiting the arrival of the code byte from the Program Memory. During
the time that the low byte of the Program Counter is
valid on PO, the signal ALE (Address Latch Enable)
clocks this byte into an address latch. Meanwhile, Port
2 (P2 in Figure 4) emits the high byte of the Program
Countex (WI-I). Then ~
strobex the EPROM and
the code byte is read into the microcontroller.
Program Memory
The interrupt aeMce locations are spaced at 8-byte intervak 0U03H for External Interrupt O, 000BH for
Tmer O, 0013H for External Interrupt 1, 00IBH for
Timer 1, etc. If an interrupt service routine is short
enough (as is often the case in control applications), it
can reside entirely within that 8-byte interval. Longer
service routinea can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
1-7
[email protected]
ARCHITECTURAL
Program Memory addresses are always 16 bits wide,
even though the aotual amount of Program Memory
used ntSy be kSS than 64K bytes. External prOq
exeoutiorssacrifices two of the 8-bit ports, PO and P2, to
the fisnction of addressing the Program Memory.
OVERVIEW
Internal Data Memory is mapped in Figure 6. The
memory space is shown divided into three bloeka,
which are generally referred to as the Lower 128, the
Upper 128, and SFR space.
Internal Data Memory addresses are always one byte
Wid%which implies an address space of only 256 bytes.
However, the addressing modes for intemssl RAM ean
in fact seeommodate 384 bytes, using a simple trick.
Direct addresses higher than 7FH awes one memory
space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Upper 128 and SFR spaceoccupyingthe ssmeblockof
addrq 80H throu~ FFH, slthoud they are physically separateentities;
Data Memory
Theright
half of Figure 2 shows the internal and external Dats Memory spaces available to the MCS-51 user.
[email protected] 5 shows a hardware configuration for accessing
up to 2K bytes of external RAM. The CPU in this ease
is executing from internal ROM. Port O serves as a
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are bein~d
to page the RAM. The CPU
generates = and WR signals as needed during exterial WM ameases.
-
n
BANK
SELECT
BRS IN
7FH
2FH
SN-ACORESSASLSSPACE
(S~ A~ESSES O-7F)
‘1
20H
1
1FH
“{
lSH
17H
‘0{
10H
OFH
0’{
OBH
07H
eo{o Ill
4 SANKSOF
8 REGIS7SRS
RO-R7
RESETVALUEOF
S7ACKPOIN7ER
270251-7
I
1’
I
270251-5
Figure 7. The Lower 128 Bytes of internal RAM
Figure 5. Accessing External Data Memory.
If the Program Memory is Internal, the Other
Bits of P2 are Available as 1/0.
The Imwer
128 bytes of W
are present in all
MCS-51 devices as mapped in [email protected] 7. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program
instructions call out these registers as RO through R7.
Two bits in the Program Status Word (PSW) seleet
which register bank is in use. This allows more effieient
use of code space, since register instructions are shorter
than instructions that use direet addreasiig.
There ean be up to 64K bytea of external Data Memory. External Data Memory addresses can be either 1 or
2 bytes wide. One-byte addresses are often used in cxmjunction with one or more other 1/0 lines to page the
R4M, as shown in Figure 5. Two-byte addresws ears
atso be used, irz which case the high address byte is
emitted at Port 2.
~:..
.-... -
, AC=IELE
, SV INDIREC7
: AtORESSING
ONLY
SDH9
UPP~
FFH
I
FFH
ACCESSIBLE
BV OIRECT
AODRSSSING
EP
‘m
ACCESSIBLE
LOWER
SY 01REC7
128
ANO INC+REC7
o AGGRESSING
80H
W 1
SPWAL
NC710N &oAmm~o
‘E~m
CONTROLems
TIMER
RE—
STACKiolN7ER
ACCUMULATOR
(’nC.)
NO SIT-AOORSSSABLE
SPACES
AVAIUBLE AS S7ACK
SPACEIN DEVICESWMI
256 BWES RAM
NOT IMPLE14EN7ED
IN 8051
80H
270251-6
270251-8
Figure 6. The Upper 128 Bytes of Internal RAM
Figure 6. Internal Data Memory
I-6
in~.
[email protected]
ARCHITECTURAL
CTIAC]
FOIRSIIRBO[
A
a
a
b
OVI
*
OVERVIEW
A
I
P
I
KWO
1
PARllY
OFACCLWUIATORSS7
~ NARoWARCTO 1 IF IT CONTAINS
AN 000 NUMBEROF 1S, OTHERWISE
171SRESE7TO0
CARRYFLAGRECEIVESCMi/fmw;
FROU BIT 1 Of ALU OPERANOS
Psw6—
AUXILIARYCARRYFLAG RECEIVES
CARRYOUT FROM B171 OF
AOOMON OPERANOS
—
Psw 1
USER OEFINABLEFUG
nw5
GENERALPURPOSES7ATUS FLAG
Psw 2
OVERFLOWFIAO SET BY
ARITIMCWOPERAl!ONS
REGtS7ER
BANKSW’%
Psw3
REOSJER
BANKSELECT
Bll O
t
270251-10
-.
.-
. . . . . .-
. .
.
...
.. .
.
.
------
----
Figure 1u. Psw (Progrsm ssssus worn) Register m mc5w-51
The next 16 bytea above the register bankBform a block
of bit-addressable memory apace. The MCS-51 instruction set includes a wide seleetion of single-blt instructions, and the 128 bits in this area can be directly addressed by these irsstmctions. The bit addreascs in this
area are W)H through 7FH.
t2evtces
!%teers addresses in SFR mace are both byte. and bit.
addressable. The blt-addre&able SFRS are ‘those whose
address ends in 000B. The bit addresses in this ares are
80H throUgh FFH.
THE [email protected] INSTRUCTION
All of the bytes in the LQwer 128 can be accessed by
either direct or indirect addressing. The Upper 128
(Figure 8) can only be accessed by indirect addressing.
The Upper 128 bytes of RAM are not implemented in
the 8051, but me in the devices with 256 bytea of RAM.
(Se Table 1).
All members of the MCS-51 family execute the same
instruction set. The MCS-51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal
MM to facilitate byte operations on small data structures. The instruction sd provides extensive support for
one-bit variables as a separate data t% allowing direct
blt manipulation in control and logic systems that require Boolean prmessirsg.
Figure 9 gives a brief look at the Special Funotion Register (SFR) space. SFRS include the Port latchea, timers, pe2iphA controls, etc. l%ese registers can only&
-seal
by dmect addressing. In general, all MCS-51
microcontrollers have the same SFRB as the 8051, and
at the same addresses in SFR space. However, enhancements to the 8051 have additional SFRB that are not
present in the 8051, nor perhaps in other proliferations
of the family.
“u
RE~MAPPSO
An overview of the MCS-51 instruction set is prrsented
below, with a brief description of how certain instructions might be used. References to “the assembler” in
this discussion are to Intel’sMCS-51 Macro Assembler,
ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler User’s Guide (Grder No. 9W3937 for 1S1SSystems, Grder
No. 122752 for DOS Systems).
POR7S
EOH
Program Status Word
AOORESSES7NAT END IN
OH OR EN ARCALSO
B~-AOORESSABLE
m
The Program Status Word (PSW) contains several
status bits that reflect the current state of the CPU. The
PSW, shown in Figure 10, resides in SFR space. It contains the Csrry bi~ the Auxdiary Carry (for BCD operations), the two register bank select bits, the Gvesflow
flag, a Parity bit, and two userdefinable status tlags.
PORT .3
80H
AOH
Porn 2
90H
POR7 1
SET
-POR7 PINS
-ACCUMULATOR
-Psw
(E7c.)
B
The Carry bit, other than serving the functions of a
Carry bit in arithmetic operations, also sesws as the
“Accumulator” for a number of Boolean operations.
J-A--I
270251-9
Figure 9. SFR Spsce
1-9
[email protected]
ARCHITECTURAL
The bits RSOand RSl are wed to select one of the four
register banks shown in Figure 7. A number of instructions refer to these RAM locations as RO through R7.
The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS1
at execution time.
The Parity bit reflects the number of 1s in the Accumulator P = 1 if the Accumulator contains an odd number of 1s, and P = O if the Accumulator contains an
even number of 1s. Thus the number of 1s in the Accumulator plus P is always even.
Two bits in the PSW are uncommitted and maybe used
as general purpose status flags.
Addressing
Modes
The addressing modes in the MCS-51 instruction set
are as follows
OVERVIEW
IMMEDIATE
CONSTANTS
The value of a constant can follow the opcode in Program Memory. For example,
MOV A, # 100
loads the Accumulator with the decimal number 100.
The same number could be specified in hex digitz as
64H.
INDEXED
ADDRESSING
only Program Memory can be amessed with indexed
addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A Id-bit base register (either DPTR or the
Program Counter) points to the base of the table, and
the Accumulator is setup with the table entry number.
The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.
DIRECT ADDRESSING
In direct addressing the operand is specitied by an 8-bit
addreas field in the instruction. Only internal Data
RAM and SFRS can be directly addressed.
INDIRECT
ADDRESSING
In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be RO or
RI of the selected register bank, or the Stack Pointer.
The addreas register for id-bit addresses can only be the
id-bit “data pointer” register, DPTR.
REGISTER
Another type of indexed addreaaing is used in the “case
jump” instruction. In this case the destination address
of a jump instruction is computed as the sum of the
base pointer and the Accumulator &ta.
Arithmetic
Themenu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be
used with each instruction to access the <byte> operand. For example, the ADD A, <byte> instruction can
be written as
ADD
ADD
ADD
ADD
INSTRUCTIONS
The register banks, containing registers RO through R7,
can be accemed by certain instructions which carry a
3-bit register specification within the opcode of the instruction. Instructions that access the registers this way
are code efficient, since this mode elirninatez an addreas
byte. When the instruction is executedj one of the eight
registers in the selected bank is amessed. One of four
banks is selected at execution time by the two bank
select bits in the PSW.
REGISTER-SPECIFIC
INSTRUCTIONS
Some instructions are specific to a certain register. For
example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is
Inneeded to point to it. The opcode itself does that.
structions that refer to the Accurrdator as A assemble
as accumulator-specific opcmdes.
Instructions
A,7FH
A,@RO
A,R7
A, # 127
(direct
addressing)
(indirect addressing)
(register addressing)
(iediate
constant)
The execution times listed in Table 2 assume a 12 MHz
clock frequency. All of the arithmetic instructions execute in 1 ps except the INC DPTR instruction, which
takes 2 W, snd the Multiply and Divide instructions,
which take 4 ps.
Note that any byte in the internal Data Memory space
can be incremented or decremented without going
through the Accumulator.
One of the INC instructions operates on the Id-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, w being able to
increment it in one 16-bit operation is a usefirl feature.
The MUL AB instruction multiplies the Accumulator
by the data in the B register and puts the Id-bit product
into the concatenated B and Accumulator registers.
1-1o
inl#
[email protected]
ARCHITECTURAL
OVERVIEW
Table 2 A Ust of the [email protected] Arithmetic
Mnemonic
Addressing
Operation
Dk
ADD
I
I
A, <byte>
ADDOA,
<byte>
SUBB
A, <byte>
INC
A
INC . <byte>
A = A +
I
A=
A+<
A–<byte>-C
I
A=A+l
I
<byte>
I
Ind
byte>+C
I
X
I
X
x
lmm
x
I
1
x
X
x
I
=<byte>+l
Execution
Time (@
Modes
Rq
x
x
<byte>
A=
Instructions
I
X
]
X
I
X
I
X
I
1
11-1
I
I
lhJC
DPTR
I
DPTR = DpTR + 1
I
Data Pointer only
121
I
DEC
A
I
A= A-l
I
Accumulator only
Ill
DEC
<byte>
<byte>
MUL
AB
B.A=Bx
DIV
AB
I
IDAA
=
<byte>
x
– 1
x
I
A
I
A = Int [A/B]
B = MOd [A/Bl
I
Decimal Adjust
I
The DIV AB instruction divides the Accumulator by
the data in the B register and leevea the 8-bit quotient
in the Accumulator, and the 8-bit remainder in the B
register.
x
1
I
ACC and B
only
ACC and B
only
I
1
Accumulator onlv
I
1
x
x
4
I
I
4
Ill
Accumulatoronly
eompletcs the shift in 4 p.s and leaves the B register
holding the bits that were shifted out.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation,
is also in BCD. Note that DA
to ensure that the red
A will not convert a binary number to BCD. The DA
A operation produces a meaningfid result only as the
second step in the addition of two BCD bytes.
Oddly enough, DIV AB finds lees use in arithmetic
“divide” routines than in radix eonversions and pro~ble
shift operstioILs. k example of the use of
DIV AB in a radix conversion will be given later. In
s~ operations, dividing a number by 2n shifts its n
bits to the right. Using DIV AS to perform the division
Table 3. A Uet of the [email protected] Instructions
I
I
Mnemonic
ANL
A,< byte>
ANL
<byte>,A
ANL
<bvte>,
A = A
ORL
A,< byte>
ORL
<bvte>,A
#data
ORL
<byte>, #data
XRL
A,< byte>
XRL
<byte>,A
XRL
<byte>,
.AND. <byte>
<byte>
=
<byte>
.AND. A
<byte>
=
<byte>
.AND. #data
I A=
A.OR.
<byte>
<byte>
= <byte> .OR. A
I <byte> = <byte> .OR. #data
A = A .XOR. <byte>
I
#data
Addressing
Operation
<byte>
=
<byte>
.XOR. A
<byte>
=
<byte>
.XOR.
#data
Dir
Ind
x
x
x
Execution
Modes
I Reg
I
Time
Imm
x
x
1
1
2
x
I X1X1X1X
x
x
X1X1X
x I
I
(ps)
X
1
1
2
x
1
I
1
2
I
CRL
A
A=OOH
Accumulator only
1
CPL
A
A =
Accumulator
only
1
IRL
RLC
.NOT. A
A
I Rotate ACC Left 1 bit
A
I Rotate Left through Csrry
Rotate ACC Right 1 bit
RR
A
RRC
A
Rotate
SWAP
A
Swap Nibbles in A
Right through Carry
1-11
I
I
Accumulator onlv
Ill
I
Accumulator only
I
1
Accumulator only
1
Accumulator
only
1
Accumulator
onlv
1
I
irrtel.
[email protected]
ARCHITECTURAL
The SWAP A instruction interchanges the high and
low nibbles within the Accumulator. This is a useful
operation in BCD manipulations. For exampie+ if the
Accumulator contains a binary number which is known
to be leas thsn IQ it can be qnickly converted to BCD
by the following code:
Logical Instructions
Table 3 shows the list ofMCS-51 logical instructions.
The instructions that perform Boolean operations
(AND, OIL Exclusive OIL NOT) on bytes perform the
operation on a bit-by-bit bssis. That is, if the AecumuIator contains 001101OIB and <byte> contains
O1OIOOIIB,then
ANL
OVERVIEW
MOV
DIV
SWAP
ADD
A, <byte>
B,# 10
AB
A
A,B
will leave the Accumulator holding OOO1OOOIB.
Dividing the number by 10 leaves the tens digit in the
low nibble of the Accumulator, and the ones digit in the
B register. The SWAP and ADD instructions move the
tens digit to the high nibble of the Accumulator, and
the onea digit to the low nibble.
The addrcasing modes that can be used to access the
<byte> operand are listedin Table 3. Thus, the ANL
A, <byte> instruction may take any of the forms
ANL
ANL
ANL
ANL
A,7FH
A,@Rl
A,R6
A, # 53H
(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)
Data Transfers
INTERNAL
AU of the logical instructions that are Accumulatorspecflc execute in lps (using a 12 MHz clock). The
othem take 2 ps.
Note that Boolean operations can be performed on any
byte in the lower 128 internal Data Memory space or
the SFR space using direct addressing, without having
to use the Accumulator. The XRL <byte >, #data instruction, for example offets a quick and easy way to
invert port bits, as in
XRL
Pl,#oFFH
If the operation is in response to an interrupt, not using
the Accumulator saves the time and effort to stack it in
the service routine.
The Rotate instructions (3U & RLC A, etc.) shift the
Aeeurtmlator 1 bit to the MI or right. For a left rotation, the MSB rolls into the LSB position. For a right
rotation, the LSB rolls into the MSB position.
Table 4. A List of the [email protected] Data Tranafer
Mnemonic
RAM
Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used
with each one. Wkh a 12 MHz clock, all of these instructions execute in either 1 or 2 ps.
The MOV < dest >, < src > instruction allows dats to
be transferred between any two internal RAM or SFR
lwations without going through the Accumulator. Remember the Upper 128 byes of data RAM can be acwased only by indirect addressing, and SFR space only
by direct addressing.
Note that in all MCS-51 devices, the stack resides in
on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies
the byte into the stack. PUSH and POP use only dkcct
addressing to identify the byte being saved or restored,
Instructions
that Access Internal Data Memory Space
Addressing
Operation
Modes
Ind
Reg
Imm
x
1
x
2
x
2
MOV
A, <src>
A = <src>
x
x
x
MOV
<cleat> ,A
<dest> = A
x
x
x
<dest> = <src>
x
x
x
MOV
<dest>,
MOV
DPTR,#data16
<src>
DPTR = 16-bit immediate constant.
PUSH
<WC>
INC SP: MOV “@’SP’, <src>
x
POP
<dest>
MOV <dest>, “@SP”: DEC SP
x
XCH
A, <byte>
ACC and <byte> exchange data
x
XCHD A,@Ri
ACC and @Riexchange low nibbles
1-12
Execution
Time (ps)
Dir
1
2
2
x
x
x
1
1
i~o
[email protected]
OVERVIEW
ARCHITECTURAL
but the stack itself is accessed by indirect addressing
using the SP register. This means the stack can go into
the Upper 128, if they are implemented, but not into
SFR space.
Atler the routine has been executed, the Accumulator
contains the two digits that were shitled out on the
right. Doing the routine with direct MOVS uses 14 code
bytes and 9 ps of execution time (assuming a 12 MHs
clock). The same operation with XCHS uses less code
and executes almost twice as fast.
In devices that do not implement the Upper 128, if the
SP points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate.
To right-shift by an odd number of digits, a one-digit
shift must be executed. Figure 12 shows a sample of
code that will right-shii a BCD number one digi~ using the XCHD instruction. Again, the contents of the
registers holding the number and of the Accumulator
are shownalongsideeachinstruction.
The Data Transfer instructions include a id-bit MOV
that can be used to initialise the Data Pointer (DPTR)
for look-up tables in Program Memory, or for Id-bit
external Data Memory accesw.
The XCH A, <byte> instruction causes the Amulator snd addressed byte to exchsnge data. The XCHD
A, @Ri instruction is similar, but only the low nibbles
are involved in the exchange.
MOV
MOV
Rl, #2EH
RO,#2DH
m
loop for R1 = 2EH
To see how XCH and XCHD can be used to fatitate
data manipulations, consider first the problem of shit%ing an 8digit BCD number two digits to the right. Figure 11 shows how this can be done using direct MOVS,
and for comparison how it can be done using XCH
instructions. To aid in understanding how the code
works, the contents of the registers that are holding the
BCD number and the content of the Accumulator are
shown alongside each instruction to indicate their
status after the instruction has been executed.
.00P
MOV
XCHD
SWAP
MOV
DEC
DEC
CJNE
Imp for RI = 2DH
loop for R1 = 2CH:
ioop for RI = 2BH:
CLR
XCH
n3JMm
MOV
A,2EH
MOV 2EH2DH
%
;;
MOV
00
12
2CH:2BH
:
%
~
A
A,2AH
00 12 34 56 78
00 12 34 56 78
00 12 34 58 78
00 12 34 58 67
00 12 34 58 67
00 12 34 56 67
76
76
67
67
67
67
00 12 36 45 67
00 18 23 45 67
0s 01 22 45 67
45
23
01
06 01 23 45 67
00 01 23 45 67
00
06
Figure 12. Shifting a SCD Number
One Digit to the Right
First, pointers RI and RO are setup to point to the two
bytea containing the last four BCD digits. Then a loop
is executed which leaves the last byte, location 2EIL
holding the last two digits of the shifted number. The
pointers are decrernented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and
Jump if Not Equal) is a loop control that will be described later.
gm
(a) Using direct MOVS 14 bytes, 9 ps
~
A,@Rl
A,@RO
A
@Rl,A
RI
RO
Rl,#2AH,LOOP
The loop is executed from LOOP to CJNE for R1 =
2EH, 2DH, 2CH and 2BH. At that point the digit that
was originally shii
out on the right has propagated
to location 2AH. Siice that location should be left with
0s, the lost digit is moved to the Accumulator.
(b) Using XCHS 9 bytes, 5 ps
..
Figure 11. Shifting a BCD Number
Two Dlgite to the Right
1-13
[email protected]
EXTERNAL
ARCHITECTURAL
Alf of these instructions execute in 2 pa, with a
12 MHz clock.
Tabfe 5. A List of the [email protected] Data
Mnemonic
Operation
PC)
-
1
The first MOVC instruction in Table 6 can accommodate a table of up to 256 entries, numbered O through
255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is setup to point to
beginning of the table. Then
A,@A+DPTR
copies the desired table entry into the Accumulator.
Execution
Time (*)
8 b~
MOVX A,@’Ri
Read external
RAM @Ri
8 bb
MOVX @Ri,A
Write external
RAM @Ri
2
16 bfia
at (A +
I
MOVC
Trsnafer Instructions that Accees
Extarnsl Data Memory Spaoe
‘6 bns
Table 6. Tha MCS3’-51 Lookup
Table Read Inetmctions
RAM
Table 5 shows a list of the Data Transfer inatmctions
that acceas external Data Memory. Only indirect ad&easing can be used. The choice is whether to use a
one-byte address, @M where Ri can be either RO or
RI of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if
only a few K bytesof externalRAMare involvedis
that 16-bit addresses use alf 8 bits of Port 2 as addreas
bus. On the other hand, S-bit addresses allow one to
address a few K bytes of RAM, as shown in Figure 5,
without having to sacrifice all of Port 2.
Address
Width
OVERVIEW
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table
base, and the table is accewed through a subroutine.
First the number of the desired entry is loaded into the
Accumulator, and the subroutine is cslled:
~
‘ovx
“@DpTR
Read external
RAM @DPTR
2
‘ovx
‘DmR’A
Writa exlemal
RAM @DPTR
2
MOV
CALL
&ENTRY_NUMBER
TABLE
The subroutine “TABLE” would look like this:
TABLE:
Note that in all external Data RAM acaases, the Accumulator is always either the destination or source of
the data.
MOVC
A,@A + PC
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255. Number O can not be used, because at the time the MOVC
instruction is executed, the PC contains the address of
the RET instruction. An entry numbered O would be
the RET opcode itseff.
The read and write strobes to external RAM are activated only during the execution of a MOVX instruction. Normally these signals are inactive and in fact if
they’re not going to be used at u their pins are available as extra 1/0 lines. More about that later.
LOOKUP TABLES
Boolean Instructions
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since
these instructions access only Program Memory, the
lookup tablea can only be read, not updated. The nmemonic is MOVC for “move constant”.
MCS-51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable blta. Afl of the port lines are bWaddressabl% and each one csn be treated as a separate singleblt port. The instructions that access these bits are not
just conditional branches, but a complete menu of
move, aeL clear, complement, OR and AND instmctions. These kinds of bit operations are not essily obtained in other architectures with any amount of byteOriented Sottware.
If the table access is to external Program Memory, then
the read strobe is PSEN.
1-14
intd.
[email protected]
ARCHITECTURAL
Note that the Boolean instruction set includes ANL
and ORL operations, but not the XRL (_ExclusiveOR)
operation. An XRL operation is simple to implement in
sof?.ware.Suppose, for example, it is Wuired @ form
the Exclusive OR of two bits
Table 7. A List of the MCS’@-51
Boolean Instrutilons
Mnemonic
Operation
Execution
Time (us)
ANL
C,bit
I
2
ANL
C./bit !IC = C .AND. .NOT. bit I1
2
n
2
nnl
F
MO\
MO\
G.
IC = C .AND. bit
16=
C.OR. bit
OVERVIEW
C = bitl .XRL. bit2
The sot%vare to do that could be as follows:
MOV
UIL,U I UIL
–
w
1=
I
ICLR
c
Ic=o
1
CLR
bit
]bit=o
1
Ic=l
SETB bn
Ibit=
1
1
CPL
C
I C = .NOT. C
1
CPL
bit
I bit = .NOT. bit
1
JC
rel
lJumpif C=
1
2
JNC
rel
Jump if C = O
2
2
JB
bit,rel
Jump if bti = 1
JNB
bit,rel
Jump if bit = O
JBC
bit,rel IJump if bti = 1; CLR bit I
1
This code uses the JNB instruction, one of a series of
bk-teat instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is
not set (JNG JNB). In the above case, blt2 is being
tested, and if bitZ = Othe CPL C instruction is jumped
over.
2
2
JBC executes the jump if the addressed bit is set, and
also clears the bit. Thus a fig can be teated and cleared
in one operation.
The instruction set for the Boolean processor is shown
in Table 7. Alt bit ameaaca are by direct addressing. Blt
addreases OOHthrough 7PH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space.
All the PSW bits are directly addressable so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.
Note how easily an internal ilag can be moved to a port
pin:
MOV
MOV
CPL
(continue)
Fkst, bit 1 is moved to the Carry. If bit2 = O, then C
now contains the correct reauh. That is, bit 1 .XRL. bit2
= bitl ifbiti = O. On the other hand, ifbit2 = 1 C
now contains the complement of the correct result. It
need only be inverted (CPL C) to complete the opcrstion.
1
SETB C
I
OVER
C,bit 1
bit2,0VER
C
RELATIVE
C,PLAG
P1.o,c
OFFSET
The destination address for these jumps is specitied to
In this example, FLAG is the name of any addressable
bit in the Lower 128 or SFR space. An 1/0 line (the
LSB of Port 1, in this case) is set or cleared depending
on whether the flag blt is 1 or O.
in the PsW isused as the single-bit ACCU.
The bTy bit
mulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carry-specflc
instructions (CLR C, etc). The Carry bit also has a
direct addreas, since it resides in the PSW register,
which is bit-addressable.
the assembler by a label or by an actual address in
Program Memory. However, the destination address
assembles to a relative offset byte. This is a signed
(two’s complement) oftket byte which is added to the
PC in two’s complement arithmetic if the jump is executed.
1-15
The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following
the instruction.
i~.
[email protected] ARCHITECTURAL
the Accumulator. Typically, DPTR is set up with the
addms of a jump table, and the Accumulator is given
an index to the table. In a 5-way branch, for examplq
an integer Othrough 4 is loaded into the Accumulator.
The code to be executed might be ax follows
Jump lnstruMlons
Table 8 shows the list of unconditional jumps.
Table 8. Unconditional Jumps
in MCW’-51 Oavices
I
Mnarnonic
I JMP
JMP
CALL
addr
I
I Jumo to addr
@A+ DPTR I Jump to A+ DPTR
addr
I Return
fromsubroutine
I RETI
I
NOP
121
I
DPTR, #JUMP_TABLE
A,INDEX_NUMBER
@A+DPTR
2
The RL A instruction converts the index number (O
through 4) to an even number on the range Othrough 8,
because each entry in the jump table is 2 bytee long:
2
I Call subroutine at addr
1RET
MOV
MOV
RLA
JMP
Exeeution
Tilna (us)
Operation
OVERVIEW
I
z
I
Returnfrominterrupt I
2
I
No oparation
1
~P_TABLE
MMP
AJMP
AJMP
AJMP
The Table lists a single “JMP addr” instruction, but in
fact there are three-SJMP, LJMP and AMP-which
differ in the format of the destination address. JMP is a
generic mnemonic which can be used if the programmer does not care which way the jump is eneoded.
CASE_O
CASE_l
CASE_2
CASE_3
CASE_4
Table 8 shows a single “CALL addr” instruction, but
there are two of them-LCALL and ACALL-which
differ in the format in which the subroutine address is
given to the CPU. CALL is a generic mnemonic which
ean be used if the programmer does not care which way
the address is encoded.
The SJMP instruction eneodes the destination address
as a relative offset, as deaeribed above. The instruction
is 2 bytes long, eonsiating of the opeode and the relative
offset byte. The jump distance is limited to a range of
-128 to + 127 bytes reIative to the instruction following the SJMP.
The LCALL instruction uses the Id-bit address format,
and the subroutine ean be anywhere in the 64K Program Memory space. The ACALL instruction uses the
1l-bit format, and the subroutine most be in the same
2K bkxk as the instruction following the ACALL.
The LJMP instruction eneodea the destination address
as a Id-bit constant. The instruction is 3 bytes long,
consisting of the opeode and two address bytes. The
destination address ean be anywhere in the 64K Program Memory SPSW.
The AJMP instruction encodes the destination address
as an 1l-bit constant. The instruction is 2 bytee long,
eonaisting of the opode, which itself contains 3 of the
11 address bits, followed by another byte containing the
low 8 bits of the destination address. When the instruction is executed, these 11 bits are simply substituted for
the low 11 bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K
block as the instruction following the AJMP.
In all eases the programmer specifies the de&nation
address to the assembler in the same way as a label or
as a id-bit constant. The assembler will put the destination address into the eormct format for the given instruction. If the format required by the instruction will
not support the distance to the specified destination rtddresa, a “Destination out of range” message is written
into the Lkt fde.
The JMP @A+ DPTR instruction supports ease
jumps. The destination address is computed at exeeution time as the sum of the lti-bit DPTR register and
1-16
In any case the programmer specifies the subroutine
address to the assembler in the same way as a label or
as a 16-bit constant. The assembler will put the address
into the correct format for the given instructions.
Subroutines should end with a RET instruction, which
returns execution to the instruction following the
CALL.
RETI is used to return from an interrupt service routine. The only difference between RET and RETI is
that RETI tells the interrupt control system that the
interrupt in progress is done. If there is no interrupt in
progress at the time RETI is executed, then the RETI
is functionally identical to RBT.
Table 9 shows the list of conditional jumps available to
the MCS-51 user. All of these jumps specify the destination address by the relative ot%et meth~ and so are
lindted to a jump distance of – 128 to + 127 bytes from
the instruction following the conditional jump instruction. Important to note, however, the user speeifies to
the assembler the actual destination address the same
way as the other jump as a label or a id-bit constant.
i~.
[email protected]
ARCHITECTURAL
Table 9. Conditions
Mnemonic
OVERVIEW
Jumps in [email protected] Devioes
Addressing
Operation
Dir
ind
Modes
Rag
imm
Execution
Time (ps)
JZ
rei
Jump if A = O
Accumulator
oniy
2
JNZ
rel
Jumpif
Accumulator
oniy
2
,rel
A+O
CJNE A, <byte> ,rei
Deorement and jump if not zero
Jumpif A # <byte>
CJNE <byte> ,#data,rei
Jump if <byte> # #data
DJNZ
<byte>
There is no Zero bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for thst ccmdition.
The DJNZ instruction (Dezrement and Jump if Not
Zero) is for loop control. To execute a loop N times,
load a counter byte with N and tersninate the loop with
a DJNZ to the beginning of the loop, as shown below
for N = 10:
x
x
x
2
2
2
x
x
x
@
Mes-51
HIAOS
ORCHMOS
‘4-J
-4-I
-i-l
OUART&&~WA; >
STAL7.
Cl
RrsONAmR
57.
S-TAL1
Vss
=
LOOP:
270251-11
MOV
com~#lo
(begin loop)
Figure 13. Using the On-Chip Oeciilator
●
*
w’%
(;d Imp)
DJNZ
COUNTER,LOOP
(continue)
HMOS
ORCnuos
SmLS
The CJNE instruction (Compare and Jump if Not
Equal) can also be used for loop control as in Figure 12.
Two bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes
are not equal. In the example of Figure 12, the two
bytes were the data in R1 and the constant 2AH. The
initial data in R1 was 2EH. Every time the loop was
executed, R 1 was decresnertted, and the looping was to
continue until the R1 &ta reached 2AH.
Another application of this instruction is in “great=
than, less than” comparisons. The two bytes in the op
erand field are taken as unsigned integers. If the first is
less than the second, then the Carry bit is set (l). If the
first is greater than or equal to the second, then the
Carry bit is cleared.
CLOCK
SIGNAL
STAL1
=
270251-12
A. HMOS or CHMOS
Mcs”-51
EilSRNAL
CLOCK
HMOS
ONLY
STAL2
STAL1
Vss
=
270251-13
B. HMOS Only
CPU TIMING
u
Mm%!
CHMOS
ONLY
All MCS-51 microcontrollers have an on-chip oscillator
which can be used if desired as the clock source for the
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTAL1 and XTAL2
pins of the microcontroller, and capacitors to ground as
shown in Figure 13.
(w)
WRNAL
STU.2
nut
L=
Vss
s
270251-14
C. CHMOS only
Figure 14. Using an Externai Ciock
1-17
i~.
MCS’5’-51 ARCHITECTURAL
Examples of how to drive the clock with an external
oscillator are shown in Figure 14. Note that in the
HMOS devices (S051, etc.) the signal at the XTAL2 pin
actually drives the internal clock generator. In the
CHMOS devices (SOC5lBH, ete.) the signsl at the
XTAL1 pin drives the internal clock generator. If only
one pin is going to be driven with the external oscillator
signal, make sure it is the right pin.
Machine Cycles
A machine cycle consists of a sequence of 6 statea,
numbered S1 through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12 Oscillator periods or 1 ps if the oscillator frequency is
12 MHz.
Each state is divided into a Phase 1 half and a Phase 2
half. Figure 15 shows the fetch/execute sequences in
The internal clock generator defmea the sequence of
states that make up the MCS-51 machine cycle.
51
52
as
se
Plm Prps PIP2 PIPS
(%L)
as
PIPs
OVERVIEW
.%
Pips
s
as
52
PIPS
Pips
L
as
S4.SE
mm
PIP2
P2 PIPS
I
51
Pips
I
ALE
1
!
I
I
I -
nw OPCODE.
J
I
READ NEXT
:,,-4ir-NEmo”oOEAGA
~
I
I
(A)t-byts, l-eydshs2mdh,
e.g., WC A.
I
I
I
I
r
I
I
READ OPCODE.
I
I
I
(B)2-byte. 1*
[email protected]
I
i
*.e.. Aoo A,mdma
I
I
I
1
READ NEXT OPCODE
OPCOOE
I
(DISCARD).
I
I
[
------S1
-------
as
es
e4ae
imhlesm
,
1
Seslases
I
[c) l-byle,2qs4C
I
AGAIN. ~
e4aEes
I
I
----------
RSAO NEXT OPCODE AGAIN.
I
, ‘1=””
I
?
1~
sla2a2s4]
-
as
AOOR
[0) MOW (l-,
I
I
— READ OPCOOE
(MWX).
READ NEXT
OPCOOE (OISCARD)
I
[email protected]@
I
-----I
I
●.s., INC DPTR.
jI-----
NO
eel
I
NO FETCH.
~NOALE
1
S11S21S2]24SSSS
I
-----
,,;
.-----
I
DATA
J
ACCESS EXTERNAL MEMORY
I
I
270251-15
Figure 15. Stete Sequences
1-18
in [email protected]’-5l Devices
in~e
[email protected]
ARCHITECTURAL
OVERVIEW
fetch/execute sequences are the same whether the
Program Memory is internal or external to the chip.
Execution times do not depend on whether the Program Memory is internal or external.
states and phases for various kinds of instructions. NormalIy two program fetches sre generated during each
machine cycle, even if the instruction being executed
doesn’t require it. If the instruction being executed
doesn’t need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incremented.
The
Figure 16 shows the signals and timing involved in program fetches when the Program Memory is external. If
Program Memo~xternsl,
then the Program Memory read strobe PSEN is normally activated twice per
machine cycle, as shown in Figure 16(A).
Execution of a one-cycle instruction (Figure 15A and
B) begins during State 1 of the machine cycle when the
opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle,
Execution is complete at the end of State 6 of this mschine cycle.
If an access to external Data Memory occurs, as shown
in Figure 16(B), two PSENS are skippe$ because the
address and data bus are being used for the Data Memory access.
instructions take two machine cycles to
execute. No program fetch is generated during the see
ond cycle of a MOVX instruction. This is the ordy time
program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in Figure
15(D).
The MOVX
r
ONE MACHINE CVCLS
sl[a21s21s41aslss
ALE
-N
~
SIIS21S21S41SE
T
I
I
I
1
I
I 1
I
I
I
I
1
1
P2 PCH
ONE MACIUNE CYCLE
I
1
ro
Note that a Data Memory bus cycle takes twice as
much time as a Program Memory bus cycle. Figure 16
shows the relative timing of the addresses being emitted
at Ports Oand 2, and of ALE and PSEN. ALE is used
to latch the low address bvte from PO into the address
latch.
r
x [
1
126
I
I
PCH OUT
I
x’
I
!
,
1
1
1 I
1
I
1
1
I
1
PCH OUT
OUTX
L
1
I
I
I
1
I
I
I
PCNOUT
1
I
t5i:F
t~::$m
WITH%)UT A
MOVX.
ty;LL&T
&T
G:v:m’lxm:m
-N
)
I
I
I
I
~
1
1
I
E
[email protected](
I
! PCHOUT
t P&m&T
1
1
I
I
OPH OUT OR P2 OUT
I
I
I
I
x!
,
I
x:
I
1
1
I
I
I
1
PCH OUT
(B)
WITH A
MOVX.
)( PWOUT
iAC:O&UT
2702!31 -16
Figure 16. Bus Cycles in [email protected] Oevices Extilng
1-19
irom External Program Memory
i~e
[email protected]
ARCHITECTURAL
When the CPU is executing from intemrd Program
Memory, ~
is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and so is available as a
clock output signal. Note, however, that one ALE is
skipprd during the execution of the MOVX instmction.
Interrupt Structure
The 8051 core provides 5 interrupt sources 2 external
interrupts, 2 timer interrupts, and the serial pat interrupt. What follows is an overview of the interrupt
structure for the t3051.Other MCS-51 devices have additional interrupt sources and vectors as shown in Table 1. Refer to the appropriate chapters on other devices for further information on their interrupts.
INTERRUPT
ENABLES
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR
(MSB)
(LSB)
EAl — I—IESIETI
Enablebk = 1 enablesb
Ensblebk =odieabksit
symbol
Pmiti9n
EA
IE.7
IEXIIETOIEXO
OVERVIEW
natned IE (Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at once. Figure 17 shows the IE register for the 8051.
INTERRUPT
PRIORITIES
Each interrupt source can also be individually prolevels by setting
or
~ed
t? one of two priority
clearing a blt m the SFR named 1P (Interrupt Priority).
Figure 18 shows the 1P register in the 8051.
A low-priority interrupt w be interrupted bya highpriority interrupt, but not by another low-priority intercan’t
beinterrupted
by
IUpt. A high-priority interrupt
any other interrupt source.
If two interrupt rquests of different priority levels are
received simultaneously, the request of Klgher priority
level is serviced. If interrupt requests of the same prioritylevel are received simultaneously, an interred polling
sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.
Figure 19 shows, for the 8051, how the IE and IP regieters and the polling sequence work to determine which
if any inttipt
Wiilbe-serviced.
interqf.
Function
d&bles all intempts. If EA = O, no
interruptW be acknowledged.If EA
= 1, each intenupt source is
itiiuslfy
enabled or disebled by
settingw clearingite eneblebit.
—
IE.6
reserved”
—
IE.5
reewed”
ES
IE.4
Ser!41Pwf Intemuptenabletin.
ETl
IE.3
TImw 1 OverflowInterrupteneblebit
Exl
IE.2
Gtsmsl Intenupf1 enable bit
ETo
IE.1
TimerOflwrffw Interruptenabfebm
Exo
IE.O
EstemslIntenuptOenablebit
“Thesereservedbiteare used in otherMCS-51devices.
(LSB)
(MSB)
——
— IPSIPTI
IPXIIPTOIPXO
Prforifybit=lsssign
shighpriwity.
Prioritytit = OassignslowprWity.
symbol
—
POeitiQn
Functfon
IP.7
resewed”
IP.6
rewed”
—
IP.5
reservedPs
IP.4
Serial Porfinterruptp+eritybii
PTl
IP.3
Timer 1 intenuptpfbrity bfi.
IP2
Pxl
ExternalIntenupt1 ptirity bit.
lP.1
PTo
limsr Ointerruptpriorftybii
Pxo
fP.o
ExternalIntellupto priorityMt.
“These resewedtits are usedin other MCB-51devices.
Figure 17. IE (Interrupt Enable)
Register in the 8051
Figure 18. 1P (Interrupt Priority)
Register in the 8051
1-20
intd.
[email protected]
ARCHITEC~RAL
IE REGISTER
OVERVIEW
HIGH PRIORllY
INTERRUPT
1P REGISTER
o
b
e
b
o
●
0
b
0
➤
1.
+h-O+io
1
I
I
INTERRUPT
‘POLUNG
SEQUENCE
/&+.
TFo
1
-&-J.
1
I
:
7FI
J&o
I
I
:
RI
n
v
J+
I
A
\
~
LyPwPNrr
270251-17
.-
Figure 19.8051 Intermpt
control
system
pleted in lms time than it takes other architectures to
commence them.
In operatiom all the interrupt tlags are latched into the
interrupt control system during State 5 of every machine cycle. The samples are polled during the following machine cycle- If the flag for an enabled interrupt is
found to be set (l), the interrupt system generates an
LCALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt.
Several conditions can block an interrupt, among them
that an interrupt of equal or higher priority level is
already in progress.
SIMULATING
SOFIWARE
A THIRD
PRIORITV
LEVEL IN
Some applications require more than the two priority
levels that are provided by on-chip hardware in
MCS-51 devices. In these cases, relatively simple software can be written to produce the same effect as a
thkd priority level.
The hardware-generated LCALL csusea the contents of
the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address of the service
routine. As previously noted (Rgare 3), the service routine for each interrupt begins at a fixed location.
Firat, interrupts that are to have higher priority than 1
are ssaigned to priority 1 in the 1P (Interrupt Priority)
register. The service routines for priority 1 interrupts
that are supposed to be interruptible by “priority 2“
interrupts are written to include the following code
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Having only the PC be automatically saved allows the programmer to decide how much time to spend saving
which other registers. This enhances the interrupt response time, albdt at the expense of increasing the pro-er’s
bu~en of responsibility. As a result, many
snterrupt functions that are typical in control applicstions-togghmg a port pim for example, or reloading a
timer, or unloading a serial but%r-can otten be mm-
PUSH
IE
IE, #MASK
MOV
LABEL
CALL
● ******
(execute service routine)
● ******
LABEL
1-21
POP
RET
RETI
IE
[email protected] ARCHITECTURAL
OVERVIEW
As soon as any priority 1 interrupt is acknowledged,
the IE (Interrupt Enable) register is m-defined so as to
disable all but “priority 2“ interrupts. Then, a CALL to
LAEEL exeoutes the RETI instruction, which clears
the priority 1 interrupt-in-program tlip-flop. At this
point SIly priority 1 interrupt that is enabled can be
seticed, but Ody “priority’ 2“ illtCSTUptSare enabled.
ADDITIONAL REFERENCES
POPping IE restores the original enable byte. Tberr a
normal RET (rather than another RETI) is used to
terminate the service routine. The additional software
adds 10 ps (at 12 MHz) to priority 1 interrupts.
2. AP-70 “Using the Intel MCW-51 Boolean Processing Capabtities”
The following application notes are found in the Embedded Chstml AppIicatwns handbook. (Order Number: 270648)
to the Intel [email protected] Sin.
gle-Chip Microcomputer Family”
1. AP-69 “An Introduction
1-22
[email protected]’s
Guide and Instruction Set
2
PAGE
MCWI51 PROGRAMMER’S CONTENTS
GUIDE AND MEMORYORGANIZATION........................2-3
INSTRUCTION SET PROGRAM MEMORY .................................2-3
Data Memory...............................................2-4
INDIRECT ADDRESS AREA,...........,.........2-6
DIRECT AND INDIRECT ADDRESS
AREA ......................................................2-6
SPECIAL FUNCTION REGISTERS............2-8
WHAT DO THE SFRS CONTAIN JUST
AFTER POWER-ON OR A RESET,......,,2-9
SFR MEMORY MAP .................................2-lo
PSW: PROGRAM STATUS WORD. BIT
ADDRESSABLE ...................................2-1 1
PCON: POWER CONTROL REGISTER.
NOT BIT ADDRESSABLE .....,..,........,..2-1 1
INTERRUPTS ............................................2-1 2
IE: INTERRUPT ENABLE REGISTER.
BIT ADDRESSABLE ............................2-12
ASSIGNING HIGHER PRIORITY TO
ONE OR MORE INTERRUPTS ..,.........,2-13
PRIORITY WITHIN LEVEL .......................2-13
1P:INTERRUPT PRIORITY REGISTER.
BIT ADDRESSABLE ..,..........,.,,...........2-13
TCON: TIMEFVCOUNTER CONTROL
REGISTER. BIT ADDRESSABLE ......,.2-14
TMOD: TIMEWCOUNTER MODE
CONTROL REGISTER. NOT BIT
ADDRESSABLE ...................................2-14
TIMER SET-UP .........................................2-1
5
TIMEFVCOUNTER
O ,..............,..,........,.,..2-15
TIMER/COUNTER 1..................................2-16
T2CON: TIMEWCOUNTER 2 CONTROL
REGISTER. BIT ADDRESSABLE ........2-17
TIMEWCOUNTER 2 SET-UP ...................2-18
SCON: SERIAL PORT CONTROL
REGISTER. BIT ADDRESSABLE ....,...2-19
2-1
CONTENTS
PAGE CONTENTS
SERIAL PORT SET-UP............................ 2-19
GENERATING BAUD RATES ..................2-1 9
Serial Port in Mode O................................ 2-19
Serial Port in Mode 1 ................................ 2-19
USING TIMER/COUNTER 1 TO
GENERATE BAUD RATES ..................2-20
PAGE
USING TIMEFUCOUNTER2 TO
GENERATE BAUD RATES ..................2-20
‘ER’AL ‘ORT ‘N ‘ODE 2 .“.”””-””-””””.
”..”;-”
2-20
SERIAL PORT IN MODE 3 ...................O. 2-20
M=&51
INSTRUCTION SET .................2-21
INSTRUCTION DEFINITIONS ................. 2-28
2-2
[email protected]
PROGRAMMER’S
GUIDEAND INSTRUCTION SET
i~.
The informationpreaentedin this chapter is collectedfrom the MCW-51 ArchitecturalOverviewand the Hardware
Descriptionof the 8051,8052and 80C51chapters of this book. The material has been selected and rearrangedto
form a quick and convenientreferencefor the programmersof the MCS-51.This guidepertains specificallyto the
8051,8052and 80C51.
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separateaddressspacesfor Program Memoryand Data Memory.The Program Memorycan be up to
64K bytes long.The lower4K (8K for the 8052)may resideon-chip.
Figure 1 showsa map of the 8051program memory,and Figure 2 showsa map of the 8052program memory.
FFFF
m.
WK
BwEe
exrmful.
64K
—
evree
OR
EXTERNAL
10M
Omo
270249-1
Figure1. The 8051 Program Memory
2-3
[email protected]’SGUIDE AND INSTRUCTION SET
S4K
BWEB
270249-2
Data Memory:
The 8051can address up to 64K bytes of Data Memoryexternal to the chip. The “MOW? instmetion is used to
access the external data memory.(Refer to the MCS-51Instmction Set, in this chapter, for detailed deaeriptionof
instructions).
The 8051has 128bytesof on-chipRAM (256bytesin the 8052)plus a numberof SpecialFunctionRegisters(SFRS).
The lower 128byteaof 3Uh4 can be accessedeither by direct addressing(MOVdata addr) or by indirect addressing
(MOV @Ri).Figure 3 showsthe 8051and the 8052Data Memoryorganization.
2-4
in~e
MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET
OFFF
“F
9—————I
64K
Bwea
DIRECT
&
INomECT
Aoon~
270249-3
Figure 3a. The 8051 Data Memory
I
FFFl
m’rEmAL
6
IWIRECT
ADORESSING
ONLY
em To FFn
w’
64K
m-me
ExnmNAL
ema
OmE(n
om.Y
m
n=
Olmcl &
INOIRECT
AwnEaslNG
00.
270249-4
Figure 3b. The 8052 Date Memory
2-5
i~.
[email protected]’S GUIDE AND INSTRUCTION SET
INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRSand the indirect address RAM have the same addreasea(80H-OFFH).Nevertheless, they are two separate areas and are amesaed in two diiferentways.
For examplethe instruction
MOV
8oH,#o&lH
writesOAAHto Port Owhichis one of the SFRSand the instruction
MOV
Rr),#80H
MOV
@RO,#OBBH
writesOBBHin location 80H of the data RAM. Thus, after executionof both of the aboveinstructionsPort Owill
contain OAAHand location 80 of the MM will contain OBBH.
Note that the stack operationsare examplesof indirect addressing,so the upper 128bytesof data MM are available
as stack space in those deviceswhich implement 256 bytesof internal RAM.
DIRECT AND INDIRECT ADDRESS AREA:
The 128bytesof W
whichcan be ameasedby both direct and indirect addressingcan be dividedinto 3 segments
as listedbelow and shownin Figure 4.
1. Registar Banks O-3:LocationsOthrough lFH (32 bytes).ASM-51and the deviceafter reset defaultto register
bank O. To use the other register banks the user must select them in the software (refer to the MCS-51Micro
AssemblerUser’s Guide). Each register bank contains 8 one-byteregisters, Othrough 7.
Resetinitiahzesthe StackPointerto location 07H and it is incrementedonceto start from location08Hwhichis the
first register(RO) of the secondregister bank. Thus, in order to use more than one register bank, the SP shouldbe
intiaked to a different locationof the RAM where it is not used for data storage (ie, higher part of the WNW).
2. Bit AddressableArex 16bytes have been assignedfor this segment,20H-2FH.Each one of the 128bits of this
wgmmt can be directly addressed(0-7FH).
The bits can be referred to in two ways both of which are acaptable by the ASM-51.One way is to refer to their
address ie. Oto 7FH. The other way is with referenceto bytes20H to 2FH. Thus,bits O-7 can alsobe referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
Each of the 16bytes in this segmentcan also be addressedas a byte.
3. Scratch Pad Arex Bytes30H through 7FH are availableto the user as &ta MM. However,if the stack pointex
has been initializedto this arm enoughnumber of bytes shouldbe left aside to prevent 5P data destruction.
2-6
in~.
[email protected]’SGUIDE AND INSTRUCTION SET
Figure4 shows the difYerentsegmentsof the on-chipRAM.
sol
SCRATCH
Pm
ARSA
14P
4SI
1.7
I 3F
301
. . . 7F 2P
AaaRLLs
2s
27 SSGMENT
20 0...
18
3
IF
10
2
1? RSGISIER
0s
1
OF
00
0
07
BANKS
270249-5
Figure 4.128 Bytes of RAM Direct and Indirect Addreeesble
2-7
in~.
[email protected]’S GUIDE AND INSTRIJCTlON SET
SPECIAL FUNCTION REGISTERS:
Table 1 containsa list of all the SFRs end their addressee.
ComparingTable 1and Figure 5 showsthat all of the SFRs that are byteand bit addressableare locatedon the first
col~n of-the diagram in Figure 5.
Table 1
Symbol
*ACC
*B
“Psw
SP
DPTR
DPL
DPH
*PO
*P1
●P2
*P3
*IP
*IE
TMOD
“TCON
*+ T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+ RCAP2H
+ RCAP2L
●SCON
SBUF
PCON
= Bitaddreaaable
+ = 8052 only
Name
Accumulator
B Register
ProgramStatusWord
Stack Pointer
Data Pointer2 Bytes
LowByte
HighByte
Porto
Port1
Port2
Port3
InterruptPriorityControl
InterruptEnable Control
Timer/Counter Mode Control
Timer/Counter Control
Timer/Counter 2 Control
Timer/Counter O HighByte
Timer/Counter O LowByte
Timer/Counter 1 HighByte
Timer/Counter 1 LowByte
Timer/Counter 2 HighByte
Timer/Counter 2 LowByte
T/C 2 Capture Reg. HighByte
T/C 2 Capture Reg. LowByte
SerialControl
Serial Data Buffer
PowerControl
2-8
Address
OEOH
OFOH
ODOH
81H
82H
83H
80H
90H
OAOH
OBOH
OB8H
OA8H
89H
88H
OC8H
8CH
8AH
8DH
8BH
OCDH
OCCH
OCBH
OCAH
98H
99H
87H
int&
[email protected] PROGRAMMERS GUIDE AND INSTRUCTION SET
WHAT DO THE SFRS CONTAIN JUST A~ER
POWER-ON OR A RESET?
Table 2 lists the contents of each SFR after power-onor a hardware reset.
Table 2. Conte
) of the SFRS after reset
Register
Value in Binary
“ACC
“B
*PSW
SP
DPTR
DPH
DPL
*PO
*P1
*P2
*P3
*IP
00000000
00000000
00000000
00000111
00000000
00000000
11111111
11111111
11111111
11111111
8051 XXXOOOOO,
8052 XXOOOOOO
8051 OXXOOOOO,
8052 OXOOOOOO
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Indeterminate
HMOS OXXXXXXX
CHMOS OXXXOOOO
*IE
TMOD
●TCON
●
+T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+RCAP2H
+RCAP2L
●SCON
SBUF
PCON
= Undefined
= BitAddreassble
+ = 8052only
2-9
intd.
M(3%51 PROGRAMMERS GUIDE AND INSTRUCTION SET
SFR MEMORY MAP
8 Bytes
F8
FO
FF
B
F7
E8
EO
EF
ACC
E7
D8
DF
DO
Psw
C8
T2CON
D7
RCAP2L
RCAP2H
TL2
CF
TH2
C7
co
B8
1P
BF
BO
P3
B7
A8
IE
AF
AO
P2
98
SCON
90
PI
88
TCON
TMOD
TLO
TL1
80
Po
SP
DPL
DPH
-r
A7
SBUF
9F
97
Figure 5
Bit
Addressable
2-1o
THO
8F
TH1
PCON
87
i~.
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
Those SFRsthat havetheir bits assignedfor variousfunctionsare listedin this section.A briefdescriptionof each bit
is providedfor quick reference.For more detailed informationrefer to the Architecture Chapter of this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
AC
CY
CY
PSW.7
AC
FO
Rsl
Rso
PSW.6
PSW.5
PSW.4
Ov
—
PSW.3
PSW.2
Psw.1
P
Psw.o
FO
RS1
RSO
Ov
I
—
I
P
Carry Flag.
AuxiliaryCarry Flag,
Flag Oavailableto the user for generalpurpose.
RegisterBank selector bit 1 (SEE NOTE 1).
RegisterBank selector bit O(SEE NOTE 1).
OverflowFlag.
User definableflag.
Parity flag. Set/cleared by herdwareeach instructioncycleto indicateerrodd/werr number of
‘1’bita in the accumulator.
NOTE:
1. Thevaluepresented
byRSOandRS1selectsthecorresponding
registerbank.
RS1
RSO
Register Bank
Address
o
o
1
1
0
1
0
1
0
1
2
3
OOH-07H
08H-OFH
10H-17H
18H-l FH
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOD
I
—
I
—
I
—
GF1
GFO
PD
IDL
SMOD Double baud rate bit. If Timer 1 is used to generatebaud rate end SMOD = 1, the baud rate is doubled
when the SeriatPort is used in modes 1, 2, or 3.
—
Not implemented,reservedfor future w.*
—
Not implemented,reservedfor future w.*
—
Not implemented,reservedfor future use.”
GF1 General purposeflag bit.
GFO General purposeflag bit.
Power Down bit. Setting this bit activates Power Down operation in the 80C51BH.(Availableonly in
PD
CHMOS).
IDL
Idle Modebit. %.ttittgthis bit activatesIdle Modeoperationin the 80C51BH.(Availableonlyin CHMOS).
If 1sare writtento PD andIDL at thesametimejPD tske$precedence,
●Usersoftwareshouldnotwrite1s to reservedbita.Thaeebitsmaybe usedin futureMCS-51productsto invokenew
featurea.In thatcase,theresetor inactivevalueofthe newbitwillbeO,anditsectivevaluewillbe 1.
2-11
irltele
[email protected]’SGUIDE AND INSTRUCTION SET
INTERRUPTS:
In
1.
2.
3.
order to use any of the interrupts in the MCS-51,the followingthree steps must be taken.
3et the EA (enableall) bit in the IE register to 1.
Set the correspondingindividualinterrupt enablebit in the IE register to 1.
Beginthe interruptserviceroutineat the em-respondingVector Addressof that interrupt. SeeTablebelow.
I
Interrupt
Souroe
I
IEO
TFO
IE1
TF1
RI &Tl
TF2 & EXF2
I
Vector
Address
OO03H
OOOBH
O013H
OOIBH
O023H
O02BH
In addition,for extemaf interrupts,pins~
and INT1 (P3.2and P3.3)must be set to 1,and dependingon whether
the intermpt is to be level or transitionactivated, bits ITOor IT1 in the TCON register may needto be set to 1.
ITx = Olevel activated
ITx = 1 transitionactivated
IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is O,the correspondinginterrupt is disabled.If the bit is 1,the correspondinginterruptis enabled.
EA
—
EA
IE.7
—
ET2
Es
ET1
EX1
ETO
EXO
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.O
ET2
ES
ETl
EX1
ETo
EXO
Disablesall interrupts.IfEA = O,no interrupt willbe acknowledged.IfEA = 1,each interrupt
source is individuallyenabledor disabledby setting or elearing its enablebit.
Not implemented,reservedfor future use.*
Enable or disablethe Timer 2 overflowor capture interrupt (8052only).
Enable or disablethe serial port interrupt.
Enable or disablethe Timer 1 overtlowinterrupt.
Enable or disableExternal Interrupt 1.
Enable or disablethe Timer Ooverflowinterrupt.
Enable or disableExternal Interrupt O.
*Usersoftwareshould not write 1sto reserved bits. These bits may be used in futore MCS-51preducts to invoke
new features. In that case, the reset or inactivevalue of the new bit wilt be O,and its active valuewillbe 1.
2-12
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the correspondingbit in the 1Pregister must be set to 1.
Rememberthat whilean interrupt servieeis in progress,it cannot be interrupted by a lower or same levelinterrupt.
PRIORITV WITHIN LEVEL:
Priority within level is only to resolvesimultaneousrequestsof the same priority level.
From high to low, interrupt sourcesare listed below:
IEO
TFo
IE1
TF1
RI or TI
TF2 or EXF2
1P:INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is O,the correspondinginterrupt has a lowerpriority and if the bit is 1 the correspondinginterrupt has a
higher priority.
I
—
—
—
PT2
Ps
Pm
Pxl
PTo
Pxo
—
PT2
Ps
PTl
Pxl
PTO
Pxo
1P.7 Not irnplementi reservedfor future use.*
1P.6 Not implemented,reservedfor future use.*
1P. 5 Detines the Timer 2 interrupt priority level(8052only).
1P.4 Definesthe SerialPort interrupt priority level.
1P. 3 Definesthe Timer 1 interrupt priority level.
1P.2 Defines External Interrupt 1 priority lexwl.
1P. 1 Defines the Timer Ointerrupt priority level.
1P.O Definesthe External Interrupt Opriority level.
*Usersoftware should not write 1s to reserved bits. Theaebits may be used in fiture MCS-51products to invoke
new features. In that case, the reset or inactive valueof the new bit will be O,and its active value willbe 1.
2-13
intel.
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TFl
TFl
TR1
TFO
TRO
IEI
IT1
IEO
ITO
TR1
TFO
TRO
IE1
IT1
IEO
ITO
TCON. 7 Timer 1 overflowflag. Setby hardware when the Timer/Counter 1 overtlows.Clearedby hsrdware as processorvectorsto the interrupt service routine.
TCON.6 Timer 1 run control bit. Set/ckared by softwareto turn Timer/Counter 1 ON/OFF.
TCON. 5 Timer Ooverflowflag. Setby hardware when the Timer/Counter Ooverflows.Clearedby hsrdware as proceasorvectorsto the seMce routine.
TCON.4 TixnerOrun control bit. Set/cleared by software to turn Timer/Counter OON/OFF.
TCON. 3 External Interrupt 1 edge flag. Set by hardware when Extemsf Interrupt edge is detected.
Clearedby hardware wheninterrupt is proeesaed.
TCON.2 Interrupt 1 type control bit. Set/cleared by sotlwsre to specifyfalling edgeflowleveltriggered
External Interrupt.
TCON. 1 External Interrupt Oedgeflag.Set by hardware when ExternalInterrupt edgedeteeted.Cleared
by hardware when interrupt is proeeased.
TCGN.O Interrupt Otype control bit. Set/cleared by sotlwsre to specifyfsfling edge/low leveltriggered
External Interrupt.
TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.
GATE
CiT’
Ml
MO
TIMER 1
TIMER O
WhenTRx (in TCON) is set rmdGATE = 1,TIMEIUCOUNTERxwillrun only whileINTx pinis high
(hardware ecmtrol).When GATE = O,TWIER./C0UNTERx will run only while TRx = 1 (software
control).
Timer or Counter seleetor. Ckred for Timer operation(input from internal system clock).Set for Counter operation(input from Tx input pin).
Mode selectorbit. (NOTE 1)
Mode selectorbit. (NOTE 1)
NOTE1:
Ml
o
o
1
1
MO
00
1
02
1
1
1
Operating Mode
13-bit Timer (MCSA8 compatible)
16-bit Timer/Counter
1
8-bit Auto-ReloadTimer/Counter
3
mimer o).TLois an a-bitTimer/Counter controlledby the standard Timer o
controlbite,THOisan 8-bitTimer and is controlledby Timer 1 controlbits.
(Timer 1) Timer/Counter 1 stopped.
3
2-14
intel.
[email protected]’SGUIDE AND INSTRUCTION SET
TIMER SET-UP
Tables 3 through 6 give some valuesfor TMOD whicheen be used to setup Timer Oin differentmodes.
It is assumedthat only one timer is beingused at a time. If it is desiredto run TimersOend 1simukaneoudy,in snY
the valuein TMOD for Timer Omust be ORed with the value shownfor Timer 1 (Tables5 and 6).
mod%
For example,ifit is desired to run Timer Oin mode1GATE (externalcontrol),and Timer 1in mode2 COUNTER,
then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover.it is assumedthat the user, at this mint, is not ready to turn the timers on and will do that at a different
point in he programby setting bit T-Rx(in TCON)to 1.
-
TIMER/COUNTER O
As a Timer:
MODE
o
1
2
3
m
Table 3
““N
13-bit Timer
16-bit Timer
8-bit Auto-Reload
two 6-bit Timera
As a Counter:
OOH
OIH
02H
03H
08H
09H
OAH
OBH
Table 4
TMOD
MODE
o
1
2
3
COUNTER 0
FUNCTION
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
13-bitTimer
16-bitTimer
8-bit Auto-Reload
04H
05H
06H
OCH
ODH
OEH
one8-bitCounter
07H
OFH
NOTES
bitTROinthesotlwere.
1. TheTimeristurnedON/OFF by eettinglclearing
on ~
(P3.2)whenTRO= 1
2. The Timeria turnedON/OFF by the 1 to Otransition
(herdwarecontrol).
2-15
intd.
[email protected]@.51 PROGRAMMERS GUIDE AND INSTRUCTION SET
TIMER/COUNTER 1
As a Time~
Table 5
TMOD
MODE
TIMER 1
FUNCTION
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
o
1
2
3
13-bitTimer
16-bitTimer
8-bit Auto-Reload
does notrun
OOH
10H
20H
30H
80H
90H
AOH
BOH
40H
50H
60H
—
WH
DOH
EOH
—
As a Counter:
o
1
2
3
Table 6
13-bitTimer
16-bitTimer
8-bitAuto-Reload
not available
NOTES
1.TheTimeristurnedON/OFFbysetting/claaring
bitTR1 inthesoftware.
2. The Timeris turnedON/OFF by the 1 to O transition
on ~
(P3.3)whenTR1 = 1
(hardwere
control).
2-16
[email protected]
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
Cln
cP/m
T2CON.7 Timer 2 overfiowtlag set by hardware and cleared by software. TP2 cannotbe set when
either RCLK = 1 or CLK = 1
EXP2
T2CON.6 Timer 2 external fig set wheneithera c.mtureor reload is causedbv a nemtive transition on
T2EX,and EXEN2-= 1.WhenTimer2 ktermpt is enabl~ EXF2-= 1‘%11causethe CPU
to vector to the Timer 2 interrupt routine.EXF2 must be cleared by software
RCLK T2C0N. 5 Receiveclock tlag. When set, causesthe Serial Port to use Timer 2 overtlowpulses for its
receiveclockin modes 1& 3. RCLK = OcausesTimer 1 overflowto be used for the receive
clock.
TLCK
T2C0N. 4 Transmit clock flag. When set, causesthe Serial Port to use Timer 2 overtlowpulses for its
transmit clock in modes 1 & 3. TCLK = O causes Timer 1 overflowsto be used for the
transmit clcck.
EXEN2 T2C0N. 3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = OcauaeaTimer 2 to ignoreeventsat T2EX.
T2CON.2 SoftwareSTART/STOP control for Timer 2. A logic 1 starts the Timer.
TR2
CRT
T2CON. 1 Timer or Counter select.
O = Internal Timer. 1 = ExternalEventCounter (fallingedgetriggered).
cP/Rm T2CON.o Capture/Reload flag. Whereset, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, AuteReloads will occur either with Timer 2 overflowsor
negativetransitions at TZEXwhenEXEN2 = 1. When either RCLK = 1 or TCLK = 1,
this bit is ignoredand the Timer is forcedto Auto-Reloadon Timer 2 overflow.
TP2
2-17
in~.
M~Q.51 PROGRAMMERS GUIDE AND INSTRUCTION SET
TIMER/COUNTER
2 SET-UP
Ex~t for the baud rate mnerstor mode. the values aiven for T2CONdo not include the settine of the TR2 bit.
ller~fore, bit TR2 must ~ set, separately,to turn th~Timer on.
As a Timer:
Table 7
T2CON
MODE
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
OOH
OIH
08H
34H
24H
14H
36H
26H
16H
16-bitAuto-Reload
16-bitCapture
BAUD rate generatorreceive&
transmitsame baudrate
receive only
transmitonlv
09H
4s a Counter:
Table 8
I
TMOD
I
MODE
INTERNAL
CONTROL
(NOTE 1)
EXTERNAL
CONTROL
(NOTE 2)
16-bitAuto-Reload
16-bitCapture
02H
03H
OAH
OBH
NOTES
1. Capture/Reload
occursonlyonTimer/Counter
overflow.
2. Capture/Reload
occurson Timer/Counter
overflowand a 1 to O transition
on T2EX
(P1.1)pinexceptwhenTimer2 isusedinthebaudrategenerating
mode.
2-18
i~e
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.
I SMO
SM1
SMO
SM1
SM2
SM2
TB8
REN
RB8
TI
RI
SCON.7 Serial Port modespecifier.(NOTE 1).
SCON.6 Serial Port modespecifier.(NOTE 1).
SCON.5 Enablesthe multiproceasor eomrnunieationfeaturein modes2 & 3. In mode2 or 3, if SM2is set
to 1 then RI will not be activated if the -veal 9th data bit (RB8)is O.In mode 1,ifSM2 = 1
then RI will not be activated if a valid stop bit was not received.In modeO,SM2 shouldbe O.
(SeeTable 9).
SCON.4 Set/Cleared by softwareto Enable/Disable reeeption.
SCON.3 The 9th bit that will be transmitted in modes2 & 3. Set/Cleared by software,
SCON.2 In modes2 & 3, is the 9th data bit that was received.In mode 1,ifSM2 = O,RB8is the stop bit
that was received.In mode O,RB8 is not used.
SCON.1 Transmit interrupt tlag. Set by hardware at the end of the 8th bit time in mode O,or at the
beginningof the stop bit in the other modes.Must be cleared by software.
SCON.O Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode O,or halfway
through the stop bit time in the other modes(exceptsee SM2).Must be cleared by software.
REN
TB8
RB8
TI
RI
NOTE1:
SMO
SM1
Mode
Deaoription
Saud Rate
o
o
1
0
1
0
0
1
2
SHl~ REGISTER
8-Bit UART
9-Bit UART
1
1
3
9-Bit UART
FOSC.112
Variable
Fo.sc./64OR
Fosc./32
Variable
SERIAL PORT SET-UP:
Table 9
MODE
SCON
SM2 VARIATION
o
1
2
3
10H
50H
90H
DOH
SingleProcessor
Environment
(SM2 = O)
o
1
2
3
:0;
BOH
FOH
Multiprocessor
Environment
(SM2 = 1)
GENERATING BAUD RATES
Serial Port in Mode O:
ModeOhas a freedbaud rate whichis 1/12 of the oscillatorfrequency.To run the serial port in this mode none of
the Timer/Countersneed to be set
up. Only the SCON register needsto be defined.
Baud Rate = Y
Serial Port in Mode 1:
Mode 1 hss a variablebaud rate. The baud rate can be generatedby either Timer 1 or Timer 2 (8052only).
2-19
i~.
[email protected]’SGUIDE AND INSTRUCTION SET
USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose,Timer 1 is used in mode 2 ([email protected]).Refer to Timer Setupsectionof this chapter.
BaudRate=
Kx Oscillator
Freq.
32X 12x [256 – (THI)]
If SMOD = O,then K = 1.
If SMOD = 1, then K = 2. (SMODis the PCON register).
Most of the time the user knowsthe baud rate and needsto know the reload valuefor TH1.
Therefore,the equation to calculate IT-Hcan be written as:
TH1 must be an integer value.Roundingoff THl to the neareat integer may not producethe desired baud rate. In
this casejthe user may have to chooseenother crystal frequency.
Sincethe PCON register is not bit addressable,one wayto set the bit is logicalORingthe PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.
USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose,Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is beingclockedthrough pin T2 (P1.0)the baud rate is:
BaudRate = Timer2 OverflowRate
16
And if it is beingclockedinternallythe baud rate is:
BaudRate=
OscFraq
32X [65536- (RCAP2H,RCAP2L)]
To obtain the reload value for RCAP2Hand RCAP2Lthe aboveequationcan be rewritten as:
RCAP2H,RCAP2L= 65536 – 32 ;:a::ate
SERIAL PORT IN MODE 2:
Thebaud rate is fixedin this modeand is 7,, or%. of the oscillatorfrequencydpding
on the v~ue of the SMOD
bit in the PCON register.
In this modenone of the Timers are used and the clock comesfrom the internal phase 2 clock.
SMOD = 1, Baud Rate = YWOsc Frcq.
SMOD = O,Baud Rate = yWw FrMI.
To set the SMODbit: ORL
pcON, #80H. The address of PCON is 87H.
SERIAL PORT IN MODE 3:
Thebaud rate in mode 3 is variableand sets up exactlythe same as in mode 1.
2-20
I
i~.
M=”-51
PROGRAMMER’SGUIDE AND INSTRUCTION SET
[email protected] INSTRUCTION SET
Table 10.8051 Inatruotion Set Summary
Interrupt ResponseTime: Refer to Hardware Description Chapter.
Dsseription
Mnemonic
---
Instructions that Affect Flag Settings(l)
Ffsg
Inetmetion
Flsg
C OV AC
C OV AC
ADD
xx
X CLRC
o
ADDC
xx
X CPLC
x
xx
X ANLC,bit X
SUBB
MUL
ox
ANLC,/bit X
DIV
ox
ORLC,bit X
x
DA
ORLC,bit X
RRC
x
MOVC,bit X
RLC
x
x
CJNE
SETBC
1
(l)FJotethat operationson SFR byte address 208or
ADD
.-
A,Rn
Instruetkm
INC
A
INC
INC
Rn
Accumulator
Adddirectbyteto
Accumulator
Addindirect
RAM
toAccumulator
Addimmediate
dateto
Accumulator
Addregister
to
Accumulator
withCarry
Adddirectbyteto
Accumulator
withCarry
Addindirect
RAMto
Accumulator
withCarry
Addimmediate
datetoAcc
withCeny
Subtract
Register
fromAcewith
borrow
Subtrectdirect
bytefromAcc
withborrow
Subfrectindiract
RAMfromACC
withborrow
Subtract
immediate
date
fromAccwith
borrw
Increment
Accumulator
Incrsmsnt
register
direct
Increment direct
ADD
A,direct
ADD
A,@Ri
ADD
A,#date
ADDC A,Rn
ADDC A,dirsct
bit addresses 209-215(i.e., the PSW or bits in the
PSW) will also afect flag settings.
ADDC [email protected]
Nota on inetruetionsat and ad&aesingmodes:
— Register R7-RO of the currently seRn
lectedRegister Bank.
direct
— 8-bit internal data location’s address.
This could been Internal Dsta RAM
locetion (0-127) or a SFR [i.e., I/O
pofi control register, status register,
etc. (128-255)].
@Ri
— 8-bit internal data RAM location (O255)addreasedindirectly through register R1 or RO.
#data — 8-bitco~~t includedin instruction.
#data 16— 16-bitconstant includedin instmction.
addr 16 — 16-bit destination address. Used by
LCALL & LJMP. A branch can be
anywhere within the 64K-byte Program Memory SddR$S SpCCe.
addr 1 — n-bit destination sddrrss. Used by
ACALL& AJMP. The branch willbe
within the same 2K-byte page of program memo~ as the first byte of the
foil-g
instruction.
rel
— Signed(two’scomplement)S-bitoffset
byte.Usedby SJMP end all conditional jumps. Range is -128 to + 127
bytes relative to first byte of the followinginstruction.
— Direct Addressedbit in Internal Data
bit
W
or SpecialFunction Register.
.
Ma registerto
ADDC A,#date
SUBB A,Rn
SUBB A,direct
SUBB [email protected]
A.#date
‘m
Oaeilfstor
Period
1
12
2
12
1
12
2
12
1
12
2
12
1
12
2
12
1
12
2
12
1
12
2
12
1
12
1
12
12
2
byte
1
12
Increment
direct
RAM
1
12
Decrement
DEC A
Accumulator
1
12
Decrement
DEC Rn
Regieter
2
12
Decrement
direct
DEC direct
byte
1
12
Decrement
DEC @Ri
indirect
RAM
WImnemonics
copyrighted
@lntelCor’pxetion
1980
INC
.
2-21
@Ri
i~e
[email protected]’SGUIDE AND INSTRUCTION SET
Table 10.8051 Inetruotion Sat Summary (Continued)
Mnemonic
Deaoription
~we o:acw~r
tRITNWTIC OPERATIONS
(Continued)
Increment
Date
1
NC DPTR
Pointer
1
dUL AB
MultiPiy
A& B
1
)IV AB
Ditie A byB
)A A
DecimelAdjuet
1
Accumulator
.OGICALOPERATtONS
ANDRegieterto
1
\NL A,Rn
Accumulator
ANDdiractbyte
2
tNL A,direct
toAccumulator
1
4NL A,@Ri
ANDindirect
RAMto
Accumulator
4NL A,#date
ANDimmediate
2
datato
Accumulator
4NL direct,A
ANDAccumulator 2
todirectbyte
4NL diract,#data ANDimmediate
3
datatodirectbyte
1
ORregister
to
)RL A,Rn
Accumulator
2RL A,direct
ORdirectbyteto
2
Accumulator
ORindiractRAM
1
2RL A,@Ri
toAccumulator
2
ORimmediate
3RL A,#date
datato
Accumulator
3RL dirac4,A
ORAccumulator 2
todirectbyte
3
3RL dirsct,~date ORimmediate
detetodiractbyte
1
KRL A,Rn
Excluaiva-OR
regieterto
Armmulator
2
I(RL A,diraot
ExclusMe-OR
directbyteto
Accumulator
1
KRL A,@Ri
Exclush/e-OR
indirect
RAMto
Accumulator
2
KRL A,#data
Exclusiva-OR
immediate
datato
Accumulator
2
Excluaive-OR
KRL direct,A
Accumulator
to
directbyte
3
KRL direct,gdata Exclueive-OR
immediate
date
todirectbyte
1
Clear
CLR A
Accumulate
1
Complement
CPL A
Accumulator
.LUUIGAL
------ urtm
---------IIUNS {wmunuao)
,A
RL
24
48
48
12
A
RLC
A
RR
A
12
RRC A
12
12
SWAP A
12
. .
,.
1
Accumulator
Left
1
Rotate
Accumulator
Left
through
theCarry
1
Rotate
Accumulator
Right
1
Rotate
Accumulator
Rightthrough
mecerry
1
Swapnibbles
withinthe
Accumulator
12
12
12
12
12
DATATRANSFER
12
1
Move
MOV A,Rn
register
to
Accumulator
12
2
Movediract
MOV A,direct
byteto
Accumulator
12
1
Moveindirect
MOV A,@Ri
RAMto
Accumulator
12
2
Move
MOV A,#date
immediate
dateto
Accumulator
12
1
Move
MOV Rn.A
Accumulator
toregister
24
2
MOV Rn,direot Movedirect
byteto
register
12
2
Move
MOV Rn,#date
immediate
date
toregister
12
2
Mova
MOV direct,A
Accumulator
todirectbyte
24
2
MOV direct,Rn Moveregister
todirectbyte
24
3
MOV diract,directMovedirect
bytatodiract
24
2
MOV direct,@Ri Moveindirect
RAMto
directbyte
24
3
MOV direct,#date Move
immediate
data
todireotbyte
12
1
Move
MOV @Ri,A
Accumulator
to
indirect
RAM
Allmnemonics
copyrighted
@lnteiCorporation
19S0
12
24
12
12
12
12
12
24
12
12
12
12
12
24
12
I
12
.2-22
in~.
M=”-51
PROGRAMMER’S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set Summary(Continued)
I
Mnemonic
OeecriptfonByte ~~k~o’
IDATATRANSFER
(continued)
MOV @Ri,direct
Movedirect
byteto
indirect
RAM
Move
MOV @Ri,#date
immediate
dateto
indirect
RAM
MOV DPTR,#data16LoedDets
Pointer
witha
16-bitconstant
MOVC A,@A+DPTR MoveMe
byterelativeto
DPTRtoAcc
MOVC A,@A+PC
MoveCode
byterelativeto
PCtoAcc
MOVX A,@Ri
Move
External
RAM(8-bit
eddr)toAcc
Move
MOVX A,@DPTR
External
RAM(l&bit
addr)toAcc
MoveAccto
MOVX @Ri,A
External
RAM
(8-bitaddr)
MoveAccto
MOVX @DPTR,A
External
RAM
(lS-bitaddr)
Pushdirect
PUSH direct
byteonto
stack
Popdirect
POP direct
bytefrom
stack
Exchange
XCH A,Rn
register
with
24
2
12
3
24
1
24
1
24
1
24
1
24
1
24
1
24
2
24
2
24
1
12
XCH
A,direct
Exchange
directbyte
with
2
12
XCH
A,@Ri
Exchange
indirect
RAM
with
1
12
Exchange
loworderDigif
indirect
RAM
1
12
XCHD A,@Ri
I
2
Mnemonic
Description
Byte
Oeciltetor
Period
BOOLEAN
VARIABLEMANIPULATION
12
1
wearwny
L
12
Clesrdirectbit
2
CLR
bit
1
12
SetCarry
SETB c
Setdirectbit
2
12
bit
1
12
Complement
c
CPL
carry
12
Complement
2
bit
CPL
directbit
ANDdirectbit
24
2
C,bit
ANL
toCARRY
24
C,/bit ANDcomplement 2
ANL
ofdirectbit
tocarry
ORdirectbit
2
24
C,bit
ORL
tocarry
24
C,/bit ORcomplement 2
ORL
ofdirectbit
tocarry
12
2
Movedirectbit
MOV C,bit
tocarry
MoveCsrryto
24
2
MOV bit,C
directbit
JumpifCsny
rel
24
2
JC
isset
JumpifCarry
24
2
rel
JNC
notset
24
3
bit,rel Jumpifdirecf
JB
Bitisset
24
3
bi$rel Jumpifdirect
JNB
BitisNotset
24
3
bit.rel Jumoifdirect
JBC
Bitisset&
clearbit
PROGRAMBRANCHING
2
ACALL addrl1 Absolute
24
Subroutine
call
LCALL addr16 Long
24
3
Subroutine
call
Returnfrom
24
1
RET
Subroutine
Retumfrom
1
RETI
24
intempt
24
2
AJMP addrll Absolute
Jump
24
3
WMP addr16 LongJump
ShortJumo
24
2
SJMP rel
(relativeaddr)
VImnemonics
copyrigMed
@lntelCorporation
1980
GLH
with Acc
2-23
int#
[email protected]’S GUIDE AND INSTRUCTION SET
Table 10.8051 Instruction Set SummarY (Continued)
Mnemonic
.FmWrIANI
. . . . . .. BmANGmNQ
-m
. ..-,,,..-
Description Byte ‘~or
,--
—.,....
(wnunueq
.’,
@A+DPTR Jumpindirecf
relativetothe
DPTR
JZ
rel
Jumpif
Accumulator
isZero
Jumpif
JNZ rel
Accumulator
isNotZero
CJNE A,direct,rei Compare
directbyteto
AccandJump
ifNotEquai
CJNE A,#date,rel Compare
immediate
to
AccandJumo
ifNotEqual
JMP
Mnemonic
1
24
2
24
2
24
3
24
3
24
Description Syte ~~or
PROGRAM
BRANCHING
(Continued)
3
24
CJNE Rn,#date,rei Compare
immediate
to
register
and
JumpifNot
Equal
24
3
CJNE @Ri,#data,rel Compare
immediate
to
indirect
and
JumpifNot
Equal
DJNZ Rn,rei
24
Decrement
2
registerand
JumpifNot
Zero
3
24
DJNZ direct,rel
Decrement
directbyte
andJumpif
NotZero
NOP
12
NoOperation 1
dlmnemonics
copyrighted
@intelCorporation
1980
2-24
i~.
[email protected] PROGRAMMERS GUIDE AND INSTRUCTION SET
i in Haxadecirnal Order
Table 11. Instruction Q
Hex
Code
00
01
02
03
04
05
06
07
06
Oe
OA
OB
Oc
OD
OE
OF
10
11
12
13
14
15
16
17
16
19
1A
lB
lC
ID
lE
IF
20
21
22
23
24
25
26
27
28
23
2A
2B
2C
2D
2E
2F
30
31
32
Number
of Bytes
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
;
:
2
1
Mnemonic
NOP
AJMP
WMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
Operands
Hex
Number
code
of Bytes
33
34
35
36
37
36
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
46
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
5e
59
5A
5B
5C
5D
5E
5F
eo
61
62
63
64
65
codesddr
codesddr
A
A
dstsaddr
@RO
@Rl
RO
RI
R2
R3
R4
R5
R6
R7
bitaddr,codeaddr
codeaddr
codeaddr
A
A
dataaddr
@RO
@Rl
RO
RI
R2
R3
R4
R5
R6
R7
bifaddr,codeaddr
codeaddr
A
A,#dats
A,datsaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bitaddr,codeaddl
codeaddr
2-25
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
Mnemonic
RLC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADD(2
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
operands
A
A,#data
A,datsaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
datsaddr,A
dateaddr,#data
A,#data
A,dataaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,Re
A,R7
codeaddr
codeaddr
dataaddr,A
dataaddr,#data
A,#data
A,datsaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
datesddr,A
datesddr,#data
A,#data
A,dataaddr
int#
[email protected]
PROGRAMMER’S
GUIDE AND INSTRUCTION
s
Hex
Code
5s
57
56
59
3A
5B
5C
6D
SE
SF
70
71
72
73
74
75
76
77
76
79
7A
70
7C
7D
7E
7F
80
81
82
83
84
85
86
87
66
89
8A
8B
SC
8D
8E
8F
90
91
92
93
94
95
M
97
98
Number
of Bytaa
1
1
1
1
1
1
1
1
1
1
2
2
2
1
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
3
2
2
2
2
2
2
2
2
2
2
3
2
2
1
2
2
1
1
1
Mnemonic
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
XRL
JNZ
ACALL
ORL
JMP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
hAov
Mov
MOV
MOV
SJMP
AJMP
ANL
MOVC
DIV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ACALL
MOV
MOVC
SUBB
SUBB
SUBB
SUBB
SUBB
.. .
. .-—--------
-----
,--.
SET
.....---,
Hex Number
Mnemonic
Coda of Bytaa
Oparanda
A,@RO
A,@Rl
~RO
A,RI
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
codeaddr
codeaddr
C,bitaddr
@A+DPTR
A,#data
datsaddr,#data
@RO,
#data
@Rl,#data
RO,#data
Rl, #data
R2,#data
R3,#data
R4,#data
R5,#data
R6,#data
R7,#data
codeaddr
codeaddr
C,bitaddr
A,@A+PC
AB
dataaddr,dataaddr
dataaddr,@RO
dataaddr,@Rl
dataaddr,RO
dataaddr,Rl
dataaddr,R2
dataaddr,R3
dataaddr,R4
dataaddr,R5
dataaddr,R6
dataaddr,R7
DPTR,#data
codeaddr
bitsddr,C
A,@A+DPTR
A,#data
A,dataaddr
A,@RO
A,@Rl
A,RO
99
9A
9B
9C
9D
9E
9F
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
02
B3
24
B5
B6
B7
08
B9
BA
BB
BC
BD
BE
BF
co
c1
C2
C3
C4
C5
C8
C7
C8
C9
CA
CB
2-26
1
1
1
1
1
1
1
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
2
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
ORL
AJMP
MOV
INC
MUL
reaervad
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ANL
ACALL
CPL
CPL
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
CJNE
PUSH
AJMP
CLR
CLR
SWAP
XCH
1
XCH
1
XCH
XCH
XCH
XCH
XCH
1
1
1
1
operands
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
C,/bitaddr
codeaddr
C,bitaddr
DPTR
AB
@RO,dataaddr
@Rl,dataaddr
RO,data
addr
Rl,dataaddr
R2,dataaddr
R3,dstaaddr
R4,dataaddr
R5,dataaddr
R6,dataaddr
R7,dataaddr
C,/bitaddr
codeaddr
bitaddr
c
A,#data,codeaddr
A,dataaddr,code
addr
@RO,
#dats,codaaddr
@Rl,#data,codeaddr
RO,#data,codeaddr
Rl,#datasodeaddr
R2,#data$odeaddr
R3,#daQcodeaddr
R4,#[email protected] addr
R5,#data,codeaddr
R8,#data,codeaddr
R7,#data,codeaddr
dataaddr
codeaddr
bitaddr
c
A
A,dataaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
ir&
Hex
Code
cc
CD
CE
CF
Do
D1
D2
D3
D4
D5
D6
D7
CM
D9
DA
DB
DC
DD
DE
DF
EO
El
E2
E3
E4
E5
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
Table 11. Instruction Opoode In1 xadecimal Order (Continued)
Number
Number
Hex
Mnemonic
Operende
Code
of Bytee ‘nemonic
of Bytee
1
1
1
1
2
2
2
1
1
3
1
1
2
2
2
2
2
2
2
2
1
2
1
1
1
2
XCH
XCH
XCH
XCH
POP
ACALL
SETB
SETB
DA
DJNZ
XCHD
XCHD
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
DJNZ
MOVX
AJMP
MOVX
MOVX
CLR
MOV
A,R4
A,R5
A,R6
A,R7
dateaddr
codaaddr
biladdr
c
A
dateaddr,codeaddr
A,@RO
A,@Rl
RO,code
addr
Rl,codeaddr
R2,codeaddr
R3,cadeaddr
R4,codeaddr
R5,codaaddr
R6,c0deaddr
R7,codeaddr
A,@DPTR
codeaddr
A,@RO
A,@Rl
A
A,dateaddr
2-27
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
FI
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
i
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVX
ACALL
MOVX
MOVX
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Operande
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
@DPTR,A
codeaddr
@RO,A
@Rl,A
A
dataaddr,A
@RO,A
@Rl~
RO,A
RI,A
R2,A
R3,A
R4,A
R5,A
R6,A
R7,A
[email protected] PROGRAMMER’S
GUIDEAND INSTRUCTION
SET
INSTRUCTION DEFINITIONS
ACALL
addrll
Function:
AbsoluteCall
Deaoription:
ACALL unconditionallycalls a subroutinelocated at the indicated address.The instruction
incrementsthe PC twim to obtain the address of the followinginstruction, then Duaheathe
Id-bit result onto the stack (low-orderbyte fret) and incremen~ the Stack Pointer&vice.The
“velyconcatenatingthe five high-orderbits of the
destinationaddress is obtainedby suceesm
incrementedPC opcodebits 7-5,and the secondbyte of the instruction.The subroutinecalled
must therefore start within the same2K block of the programmemoryas the fsrstbyte of the
instrueticmfollowingACALL. No flagsare affected.
Example:
InitiallySP equals 07H. The label “SUBRTN”is at programmemorylocation0345H. After
executingthe instruction,
ACALL SUBRTN
at location0123H, SP will contain 09H, internal IL4M locations08H and 09H will contain
25H and OIH, respectively,and the PC will contain 0345H.
Bytw
2
Cyclw
2
Encoding:
I
alO a9 a8 1
0001
a7 a6 a5 a4
ACALL
(PC)- (PC)+ 2
(SP) + 1
((sP)) + (PC74)
(SP) + (SP) + 1
((SP))- (PC15.8)
(PClo.o)+ page address
(SP) +
2-26
a3 a2 al aO
in~o
ADD
M~’@.51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
A,<src-byte>
Function:
Description:
Add
ADD adds the bytevariableindicatedto the Acewmdator,leavingthe result in the Accumulator. The carry and awdliary-carrytlags ~e set, respectively,if there is a carry-outfrom bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overtlowoeared.
OVis set if there is a carry-out of bit 6 but not out of bit 7, or a carry-outof bit 7 but not bit 6;
otherwiseOV is cleared. When addingsigmd integera,OV indicates a negativenumber produced as the sum of two positiveoperandsjor a paitive sum from two negativeoperands.
Foursouree operandaddressingmodesare allowed:register,direcLregister-indirect,or immediate.
Example:
The Accumulatorholds OC3H(11OOOO11B)
and register O holds OAAH(10101O1OB).The
instruction,
ADD A,RO
willleave6DH (O11O1IO1B)
in the Accumulatorwith the AC flag clearedand both the carry
flag and OV SWto L
ADD
A,Rn
Bytes:
1
Cycles:
1
0010
Encoding:
Operation:
ADD
Irrr
ADD
(A) + (A) + @O
A,direct
Bytatx
2
cycles:
1
Encoding:
Operation:
0010
0101
I
directaddress
ADD
(A) + (A) + (direct)
2-29
MCS”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
ADD A,@Ri
Bytes:
1
Cycles:
1
Encoding:
IO O1OI
Operation:
ADD
(A) - (A) + ((%))
Ollil
ADD &#dats
Bytes
2
Cycles:
1
0010
Encoding:
Operation:
0100
[
immediatedata
ADD
(A) -
(A) + #data
ADDC A,<src-byte>
Function:
Description:
Add with Carry
ADDC simultaneouslyadds the byte variableindicated, the carry tlag and the Accumulator
contents, leavingthe result in the Accumulator.The carry and auxiliary-carryfiags are set,
respectively,if there is a carry-out from bit 7 or bit 3, and cleared otherwise.When adding
unsignedintegers,the carry tlag indicatesan overtlowOccured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-outof bit 7 but not out of
bit 6; otherwiseOV is cleared. When addingsignedintegers, OV indicatssa negativenumber
producedas the sum of two positiveoperandsor a positivesum from two negativeoperands.
Four souroeoperandaddressingmodesare allowed:register, direct, register-indirect,or immediate.
Example:
‘l%eAccumulatorholds OC3H(11OOOO11B)
and register OholdsOAAH(10101O1OB)with the
~
fig set. The instruction,
ADDC A,RO
will leave6EH (0110111OB)
in the Accumulatorwith AC clearedand both the Carry flag and
Ov set to 1.
2-30
intd.
[email protected]
PROGRAMMER’S
GUIDE AND INSTRUCTION SET
ADDC A,Rn
Bytes:
Cyclm
1
1
Encoding:
Operation:
0011
Irrr
ADDC
(A) - (A) + (0 +(%)
ADDC A,direct
Bytes:
2
Cycles:
1
0011
Encoding:
Operation:
0101 1
directaddress
ADDC
(A) + (A) + (C) + (direct)
ADDC A,@Ri
Bytes:
1
Cycles:
1
0011
Encoding:
Operation:
Olli
ADDC
(A) + (A) + (C) + ((IQ)
ADOC A,+dats
Bytes:
2
Cyclesx
1
Enooding:
Operation:
0011
0100
I
immediatedata
ADDC
(A) +- (A) + (C) + #data
2-31
i~.
[email protected]’SGUIDE AND INSTRUCTION SET
AJMP addrll
AbsoluteJultlp
AJMP transfers program executionto the indicated address,which ia formedat run-time by
concatenatingthe high-orderfivebits of the PC (afier incrementingthe PC twice),opcodebits
7-5,and the secondbyte of the instruction. The destinationmust thereforebe withinthe same
2K block of program memoryas the first byte of the instructionfollowingAJMP.
Example
The label “JMPADR” is at program memory location0123H.The instruction,
AJMP JMPADR
is at location 0345Hand will load the PC with O123H.
Bytas
.L
Cycles
2
Encoding:
Operation:
alO a9 a8 O
0001
a7 a6 a5 a4
a3 S2 al aO
AJMP
@’cl+ (m + 2
(PClo.o)+ page address
ANL
<dest-byte>, <src-byte>
Funotion:
[email protected] for byte variables
ANL performsthe bitwiselogical-ANDoperation betweenthe variablesindicatedand storea
the results in the destinationvariable. No flags are affected.
The two operandsallowsix addressingmode combinations.When the destinationis the Accumulator, the source can w register, direct, regiater-indirec~or immediateaddressing;when
the destinationis a direct address, the source can be the Accumulatoror immediatedata.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch not the input pins.
Example:
If the Accumulatorholds OC3H(11OOUHIB)and registerOholds 55H (O1OIO1O1B)
then the
instruction,
ANL A,RO
will leave 41H (OIOWOOIB)
in the Accumulator.
When the destinationis a directly addressed byte, this instruction will clear combinationsof
bits in SOYRAM locationor hardware register. The maskbyte determiningthe pattern of bits
to beclearedwouldeitherbe a constantcontainedintheinstructionor a valuecomputedin
the Accumulatorat run-time.The instruction,
ANL Pl, #Ol110011B
will clear bits 7, 3, and 2 of output port 1.
2-32
in~.
[email protected]’SGUIDE AND INSTRUCTION SET
ANL A,Rn
Bytes:
1
Cycles:
1
Encoding:
0101
Irrr
0101
0101
Operation:
ANL
A,direct
Bytee:
Cycles:
Encoding:
Operation:
directaddress
ANL
(A) ~ (A) A (direct)
ANL
&@Ri
Bytes:
1
Cyclee:
1
0101
Encoding:
Operation:
Olli
ANL
(A) + (A) A (w))
ANL
A,#data
Bytes:
2
Cycles:
1
0101
Encoding:
Operation:
ANL
0100
immediate
date
ANL
(A) + (A) A #data
[email protected]
Bytas:
cycles
2
1
00101
Encoding:
10101
Operation:
ANL
(direct) + (direct) A (A)
directaddress
2-33
i~.
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
ANL [email protected] #dats
Bytes:
3
Cycles:
2
0101
Encoding:
Operation:
ANL
0011
directaddress
immediatedata
ANL
(direct) + (direct) A #data
C,<src-bit>
Function:
Description:
Logioal-ANDfor bit variables
If the Booleanvalueof the sourcebit is a logicalOthen clear the carry flag;otherwiseleavethe
carry flag in its current stste. A slash (“/”) precedingthe operandin the assemblylanguage
indicatesthat the logicalcomplementof the addressedbit is used as the sourcevaluq but the
source bit itself & not affwed. No other flsgs are affected.
Onlydirect addressingis allowedfor the source -d.
Set the carry flag if, and only if, P1.O= 1, ACC. 7 = 1, and OV = O:
MOV C,P1.O
;LOAD CARRY WITH INPUT PIN STATE
ANL ~ACC.7
;AND CARRY WITH ACCUM. BIT 7
ANL C,/OV
;AND WITH INVERSEOF OVERFLOWFLAG
ANL C,bit
Bytes:
2
Cycles:
2
1000
Encoding:
Operation:
ANL
100101
H
ANL
(C) ~ (C) A (bit)
C,/bit
Bytes:
2
Cycles:
.
Encoding:
Operation:
1o11
0000
ANL
(C) + (C)A 1
=
(bit)
2-34
[email protected]
MCS’@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET
CJNE <dest-byte>,<src-byte>, rel
Function:
Description:
Compareand Jump if Not Equal.
CJNE comparesthe magnitudesof the fmt two operands,and branches if their valuesare not
equal. The branch destinationis computedby addingthe signedrelative-displacementin the
last instructionbyte to the PC, after incrementingthe PC to the start of the next instruction.
The carry flag is set if the unsignedinteger value of <dest-byte> is less than the unsigned
integer valueof <src-byte>; otherwise,the carry is cleared. Neither operand is tided.
The first two operands allow four addressingmode combinations:the Accumulatormay be
comparedwith any directlyaddressedbyte or immediateda~ and any indirectRAM location
or worldngregister can be comparedwith an immediateconstant.
The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence
CJNE R7,#60H, NOT-EQ
.....
JC
“‘“
REoLLOw
...
.....
NOT—EQ:
; R7 = 60H.
; IF R7 < &3H.
; R7 > 60H.
sets the carry flag and branchesto the instructionat labelNOT-EQ. Bytestingthe carry flag,
this instructiondetermines whether R7 is greater or less than 60H.
If the data being presentedto Port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT
clears the carry tlag and continueswith the next instructionin sequence,sincethe Accumulator doesequal the data read from P1. (If someother valuewas beinginput on Pl, the program
will loopat this point until the PI data changesto 34H.)
CJNE
A,direct,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
1o11
0101
I ‘ire”addressI
(PC) - (PC) + 3
IF (A) <> (direct)
THEN
(PC) + (PC) + relativeoffket
IF (A) < (direct)
THEN
~L~E (c) -1
(c)+ o
2-35
EiEl
intel.
M&0h51 PROGRAMMERS GUIDE AND INSTRUCTION SET
CJNE A,4$data,rei
Bytee:
3
Cycles:
2
1o11
0100
(-PC)+
(PC) + 3
Encoding:
Operation:
IF (A) <> data
THEN
(PC) -
] immediatedats I
(PC)+
! rel. address I
relative offiet
IF (A) < data
THEN
EME (c) -1
(c) + o
CJNE Rn,#dats,rel
Bytea:
3
Cyclea:
2
Encoding:
1o11
Operation:
(PC) +
Irrr
I
immediate data
EEl
(Pc) + 3
IF (Rn) <> data
THEN
(PC) +
m)
+ relative ofiet
IF ([email protected] < data
THEN
(c) + 1
ELSE
(c)+ o
CJNE
@Ri,#data,rel
Bytea:
3
Cyclea:
2
Olli
I immediatedate I
Encoding:
I 1o11
Operation:
(P(2)+ (PC) + 3
IF ((Ri)) <> data
THEN
(PC) t (PC!)
+ rehztive oflset
IF (@i)) < data
THEN
ELSE (c) -1
(c) + r)
2-36
I rel.addressI
intd.
[email protected]’SGUIDE AND INSTRUCTION SET
CLR A
Function:
Description:
Example:
Clear Aecunlulator
The Aecunmlatoris cleared (all bits set on zero). No flags are affeeted.
The Accumulatorcontsins 5CH (010111OOB).
The instruction,
CLR A
will leave the Accumulatorset to OOH(~
CLR
Bytee:
1
Cyclea:
1
Encoding:
1110
Operation:
CLR
(A) + O
B).
0100
bit
Function:
Description:
Example:
Clear bit
The indicated
bit is cleared(reset to zero).No other flagsare atkted. CLR ean operateon the
CSITY
tig or any directlyaddressablebit.
Port 1 has previouslybeen written with 5DH (O1O111O1B).
The instruction,
CLR P1.2
will leave the port set to 59H (O1O11CK)1B).
CLR C
Bytea:
1
cycle=
1
Encoding:
I
Operation:
CLR
1100
0011
I
(c)+ o
CLR bit
Bytea:
2
Cyclea:
1
Encoding:
1 100
Operation:
CLR
(bit) + O
0010
I bitaddress I
2-37
intelo
[email protected]’SGUIDE AND INSTRUCTION SET
CPL A
Function:
Description:
Example:
ComplementAccumulator
Each bit of the Accumulatoris logicallycomplemented(one’scomplement).Bits whichpreviouslycontaineda one are changedto a zero and vice-versa.No tlags are affected.
The Accumulatorcontains 5CH (O1O111CX3B).
The instruction,
CPL A
will leave the Accumulatorset to OA3H(101OOO11B).
Bytes:
1
Cycles:
1
Enooding:
Operation:
CPL
1111
CPL
(A) -1
0100
(A)
bit
Function:
Deeoription:
Complementbit
The bit variablespecifiedis complemented.A bit which had beena one is changedto zero and
vice-versa.No other flagsare affected.CLR can operate on the carry or any directly addressable bit.
Note:Whenthis instructionis usedto modifyan output pin,the valueused as the originaldata
will be read from the output data latch, not the input pin.
Example:
Port 1 has previouslybeen written with 5BH (O1O1I1O1B).
The instruction sequence,
CPL P1.1
CPL P1.2
will leavethe port set to 5BH(O1O11O11B).
CPL C
Bytes:
1
Cycletx
1
Encoding:
I 1o11
Operation:
CPL
0011
(c)+ 1 (c)
2-38
i~.
CPL
[email protected]’SGUIDE AND INSTRUCTION SET
bit
Bytes:
2
Cycles:
1
Encoding:
Operstion:
DA
1o11
100’01
EEiEl
CPL
(bit) ~l(bit)
A
Funotion:
Description:
Decimrd-adjust Accumulatorfor Addition
DA A adjusts the eight-bitvaluein the Accumulatorresultingfrom the earlieradditionof two
variables(each in packed-BCDformat), producingtwo four-bitdigits. Any ADD or ADDC
instruction may have been usedto perform the addition.
IfA ccurmdatorbits 3-Oare greater than nine (xxxxlOIO-XXXX1
I1I), or if the AC tlag is onq
six is added to the Accunndatorproducingthe proper J3CDdigit in the low-ordernibble.This
internal additionwouldset the carryflag ifa carry-outof the low-orderfour-bitfieldpropagated through all high-orderbits, but it would not clear the carry tlag otherwise.
If the carry tlag is now seLor if the four high-orderbits nowexceednine (101OXXXX-1I1XXXX),
thesehigh-orderbits are incrementedby six, producingthe properBCDdigitin the high-order
nibble.Again, this wouldset the carry flag if there was a carry-out of the high-orderbits, but
wouldn’tclear the carry. The carry flag thus indicates if the sum of the original two BCD
variablesis greater than 1120,
allowingmultipleprecisiondecimaladdition.OVis not affected.
All of this occurs during the one instruction cycle. Essentially,this instructionperforms the
decimal conversionby addingOOH,06H, 60H, or 66H to the Accurnulator, depending on
initial Accurmdatorand P3W conditions.
Note:DA A cannot simplyconverta hexadecimalnumber in the Accrumdatorto BCD notation, nor does DA A apply to decimalsubtraction.
2-39
intd.
[email protected]’SGUIDE AND INSTRUCTION SET
The Accumulatorholdsthe value56H(OIO1OI1OB)
representingthe packedBCDdigits of the
decimal number 56. Register 3 containsthe value 67H (0110011lB)representingthe packed
BCD digits of the decimal number 67. The carry flag is set. The instructionsequence.
ADDC A,R3
DA
A
wdl first perform a standard twos-complementbinary addition, resultingin the value OBEH
(10111110)in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OO1OO1OOB),
indicatingthe packedBCDdigitsof the decimal number 24, the low-ordertwo
digitsof the decimalsum of 56,67, and the carry-in.The carry tlag willbe set by the Decimal
Adjust instruction,indicatingthat a ddnal overflowoccurred. The true sum 56,67, and 1 is
124.
BCDvariablescan be incrementedor decrementedby addingOIHor 99H.If the Accumulator
initially holds 30H (representingthe digitsof 30 decimal),then the instructionsequence,
ADD
A#99H
DA
A
will leave the carry set and 29H in the Accumulator,since 30 + 99 = 129.The low-order
byte of the sum can be interpreted to mean 30 – 1 = 29.
Bytes
1
Cycles:
1
Encoding:
Operstion:
1101
0100
DA
-contents of Accumulatorare BCD
IF
[[(A3-13)>91 V [(AC) = 111
THEN(A34)- (A343)+ 6
AND
IF
[[(A7-4)> 9] V [(C) = 111
THEN (A74) - (A74) + 6
2-40
in~.
MCS”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET
DEC byte
Function:
Description:
Decrement
The variableindicatedis decrementedby 1.An originalvalueof OOHwill underilowto OFFH.
No flags are affected. Four operand addressingmodes are allowed:accumulator, register,
&[email protected] or register-indirect.
Note: When this instruction is used to modifyan output port, the value used as the original
port data willbe read from the output data latch, not the input pins.
Exampte:
Register Ocontains 7FH (0111111IB). Internal RAM locations7EH and 7FH contain OOH
and 40H, respectively.The instructionsequence
DEC @RO
DEC RO
DEC @RO
will leave registerOset to 7EH and internal RAM locations7EH and 7FH set to OFFHand
3FI-I.
DEC A
Bytes:
Cyclx
1
1
Encoding:
Operation:
0001
DEC
(A) -
0100
(A) – 1
DEC Rn
Bytes:
1
cycles:
1
Encoding:
Operation:
0001
lrrr
DEC
(Rn) + @l) – 1
241
i~.
[email protected]’SGUIDE AND INSTRUCTION SET
DEC direct
Bytes:
2
Cycles:
1
Encoding:
0001
Operation:
DEC
(direct) -
0101
I
directaddress
(direct) – 1
DEC @Ri
Bytes:
1
Cycles:
1
Encoding:
10001
Operation:
DEC
(w)) -((N))
I Ollil
– I
DIV AB
Function:
Description:
Divide
DIV AB divideathe unsignedeight-bitinteger in the Accumulatorby the unsignedeight-bit
integer in register B. The Accumulator receivesthe integer part of the quotient; register B
receivesthe integer remainder.The carry snd OV tlags will be cleared.
Exception: ifB had originallycontainedOOH,the valuesreturned in the Accumulatorand B-
register will be undefinedand the overflowflag will be set. The carry tlag is cleared in any
case.
Example:
The Accumulatorcontains251(OFBHor 11111011B)
and B contains 18(12Hor OOO1OO1OB).
The instruction,
DIV AB
will leave 13in the Accumulator(ODHor OOOO11O1B)
and the value 17(lIH or OOO1OOO1B)
in B, since 251 = (13 X 18) + 17.Carry and OV willboth be cleared.
Bytes:
1
Cycles:
4
Enooding:
Operation:
I
1000
DIV
(A)15.8
~)74 -
0100
(A)/@t)
2-42
in~.
DJNZ
[email protected]’SGUIDE AND INSTRUCTION SET
<byte>, <rel-addr>
Function:
Description:
DecrementandJumpif Not =0
DJNZ decrementsthe location indicated by 1, and branchesto the address indicatedby the
second operandif the resulting value is not zero. An originalvalue of OOHwill underflowto
OFFH.No tlags are at%cted.The branch destinationwouldbe computedby addingthe signed
relative-displacementvaluein the last instructionbyteto the PC, after incrementingthe PC to
the first byte of the followinginstruction.
The location decreznentedmaybe a register or directlyaddressedbyte.
Note: When this instruction is used to modfi an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:
Internal RAM locations40H, 50~ and 60H containthe values OIH, 70H, and 15H,respec-
tively. The instructionsequence,
DJNZ 40H,LABEL-1
DJNZ 50H,LABEL-2
DJNZ 60H,LABEL-3
will cause a jump to the instructionat label LABEL-2 withthe valuesOOH,6FH, and 15Hin
the three W
locations The first jump was not taken becausethe result was zero.
This instruction provideaa simpleway of executinga programloop a givennumberof times,
or for addinga moderatetime delay (from 2 to 512machinecycles)with a singleinstruction.
The instruction sequence,
TOOOLE:
MOV
CPL
DJNZ
R2,#8
P1.7
R2,TOOGLE
will toggle P1.7 eight times, causing four output pukes to appear at bit 7 of output Port 1.
Each pulse will last three machinecycles;two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytee:
cycles:
2
2
Encoding:
I 1101
Operation:
DJNZ
(PC!)- (PC) + 2
m) -(w
– 1
w ~~~
0 or ([email protected] < t)
11’”1
EEl
(PC)+ (PC)+ rd
2-43
int&
MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET
DJNZ [email protected]
Byte=
3
Cycles
2
1101
Encoding:
Operation:
INC
0101
I ‘irw’addressI
EiEl
DJNZ
(PC) + (PC) + 2
(direct) + (direct) – 1
IF (direot) >0 or (direct) <0
THEN
(PC) -(PC)
+ ml
<byte>
Function:
Description:
Incmsnent
INC incrementsthe indicatedvariableby 1. An originalvalueof OFFHwill overflowto OOH.
No figs are affected.Three addressingmodesare allowed:register,direct, or register-indirect.
Note.”When this instruction is used to modifyan output port, the value used ss the original
port data will be read from the output data latch, not the input pins.
Exsmple:
RegisterOcontains7EH (01111111OB).
Internal RAM locations7EHand 7FH mntain OFFH
and 40H, respectively.The instructionsequence,
INC @RO
INC RO
INC @RO
will leaveregisterOset to 7FH and internal RAM locations7EHand 7FH holding(respectively) (XIHand 41H.
INC
A
Bytes:
1
cycles:
1
Encoding:
Operstion:
0000
0100
INC
(A) + (A) + 1
2-44
i~e
INC
M=”-51
Rn
Bytes:
cycles
1
1
0000
Encoding:
Operation:
INC
INC
m)+
Bytee:
2
Cycles:
1
Operation:
w)
+ 1
0000
0101
1
directaddress
INC
(direct) ~ (direct) + 1
@Ri
Bytes:
1
Cycles:
1
0000
Encoding:
Operation:
INC
Irrr
direct
Encoding:
INC
PROGRAMMER’S GUIDE AND INSTRUCTION SET
Olli
INC
(m)) + (m)) + 1
DPTR
Function:
Description:
Increment Dsta Pointer
Increment the id-bit data pointer by 1. A id-bit increment (modulo216)is performed;an
overflowof the low-orderbyte of the data pointer (DPL) from OFFHto COHwill increment
the high-orderbyte (DPH). No tlsgs are sfkted.
This is the only id-bit register whichcan be incremented.
Example:
RegistersDPH and DPL contsin 12Hsnd OFEH,respectively.The instruction sequence,
INC DPTR
INC DFTR
INC DPTR
will chsnge DPH and DPL to 13Hsnd OIH.
Bytes:
Cycle=
1
2
Encoding:
1o1o
Operation:
INC
(DPTR) -
0011
(DFITl) + 1
245
i~.
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
JB bityrei
Function:
Description:
Jump if Bit set
If the indicated bit is a one,jump to the [email protected] otherwiseproceedwith the next
instruction.The branch destinationis computedby addingthe signedreistive-displscement in
the third instruction byte to the PC, after incrementingthe PC to the fnt byte of the next
instruction. The bit tested k nor modified. No tlags are affected.
The Accumulatorhoids 56(O1O1O11OB).
The
The data present at input port 1 is 11OO1O1OB.
instructionsequence,
JB P1.2,LABEL1
JB ACC.2,LABEL2
will causeprogram executionto branch to the instruction at label LABEL2.
Bytes:
3
Cycierx
2
Encoding:
Operstion:
0010
1004
JB
(PC)+ (PC)+ 3
EEzEEl
EizEl
IF (bit) = 1
THEN
(PC) +- (PC) + rel
JBC
bitrei
Function:
Description:
lump if Bit is setand Clearbit
If the indicated bit is one, branch to the address indicated; otherwiseproceedwith the next
instruction. 17rebit wili not be cleared ~~itis already a zero. The branch destinationis computed by adding the signedrelative-displacementin the third instruction byte to the PC, after
incrementingthe PC to the tlrst byte of the next instruction. No flags are affected.
Note:When this instructionis used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Exempie:
The Accumulatorholds 56H (01010110B).The instruction sequence,
JBC ACC.3,LABELI
3BC ACC.2,LABEL2
will cause program executionto continueat the instruction identifiedby the label LABEL2,
with the Accumulator modifiedto 52H (OIO1OO1OB).
2-46
M=”-51
Bytes:
3
Cycles:
2
Encoding:
Operation:
programmers
I“” ”’l”
JBc
(PC) -
”””1
GUIDE AND INSTRUCTION SET
DEEl
EiEiEl
(PC) + 3
IF (bit) = 1
THEN
(bit) * O
(PC) ~ (PC) + rel
JC rel
Function:
Daacription:
Exsmple:
Jump if Carry is set
If the carry flag is set, branch to the addreas indicated; otherwise proceed with the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the secondinstructionbyte to the PC, after incrementingthe PC twice. No flagsare afkted.
The carry flagis clesred. The instruction sequence,
JC
LABEL1
CPL C
JC
LABEL2
will set the carry and cause program executionto continueat the instructionidentifiedby the
label LABEL2.
Bytes
2
cycles:
2
Encoding:
Operation:
0100
0000
=
JC
(PC)+ (PC)+ 2
IF (C) = 1
THEN
(PC) ~ (PC) + rel
2-47
[email protected]
JMP
[email protected]’SGUIDE AND INSTRUCTION SET
@A+DPIR
Function:
]umpindirect
Add the eight-bitunsignedcontentsof the Accurnulator with the sixteen-bitdata pointer, and
load the resultingsum to the programcounter.This willbe the addressfor subsequentinstruction fetches.Sixteen-bitaddition is performed(modrdo216):a camy-outfrom the low-order
eight bits propagatesthrough the higher-orderbits. Neither the Accumulator nor the Data
Pointer is altered.No tlags are affected.
An evennumberfromOto 6 is in the Accumulator.The followingsequenceof instructionswill
branch to one of four AJMP instructionsin a jump table starting at JMP-TBL:
MOV
JMP
AJMP
AJMP
AJMP
AJMP
JMP-TBL:
DPTRj#JMP-TBL
@A+DPTR
LABEL.O
LABEL1
LABEL2
LABEL3
If the Accumulatorequals 04H when starting this sequence,execution will jump to label
LABEL2.Rememberthat AJMP is a two-byteinstruction,so the jump instructions start at
every other address.
Bytex
1
Oycies:
2
Encoding:
10111
Opersliorx
JMP
W)+
00111
(A) +
WW
2-48
[email protected]’SGUIDE AND INSTRUCTION SH
JNB
bi~rel
Function:
Jump if Bit Not set
If the indicatedbit is a zero, branch to the indicatedaddress;otherwiseproceedwith the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the third instruction byte to the PC, after incrementingthe PC to the first byte of the next
instruction. The bit tested is not modt~ed. No flags are affected.
Example:
The data present at input port 1is 11W101OB.
The Accumulatorholds 56H(01010110B).The
instruction sequence,
JNB P1.3,LABEL1
JNB ACC.3,LABEL2
will cause program executionto continueat the instructionat label LABEL2.
Bytes:
3
Cycles:
2
Encoding:
0011
100001
Operation:
JNB
$W:)y;
+3
THEN (PC) t
JNC
LGzEl
EEl
(PC) + rel.
rel
Function:
Description:
Example:
Jump if Carry not set
If the carry tlag is a zero, branch to the addreas indicated;otherwiseproceed with the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the second instruction byte to the PC, after incrementingthe PC twice to point to the next
inatruetion.The carry tlag is not moditled.
The carrytlag is set. The instructionsequence,
JNC LABEL1
CPL C
JNc LABEL2
will clear the carry and cause program executionto continueat the instruction identitkd by
the label LABEL2.
Bytes
2
Cycles:
2
Encoding:
Operation:
0101
JNC
(PC) -
100001
-
(PC) + 2
IF (C) = O
THEN (PC) t
(PC) + rel
2-49
i~.
[email protected]’SGUIDE AND INSTRUCTION SET
JNZ rel
Function:
Jump if AccumulatorNot Zero
If any bit of the Accumulator is a one, branch to the indicatedaddress;otherwiseproceedwith
the next instruction. The branch destination is computedby adding the signed relativedisplacement in the second instruction byte to the PC, after incrementingthe PC twice. The
Accumulator is not modified.No tlags are affected.
Example:
The Accumulator originallyholdsOOH.The instructionsequence,
JNZ LABEL1
INC A
JNZ LAEEL2
will set the Accumulatorto OIH and continueat label LABEL2.
Bytea:
2
Cyclea:
2
0111
Encoding:
Operation:
10’001
EiEl
JNz
(PC)+ (PC) + 2
IF
(A) # O
THEN (PC) ~ (PC) + rel
JZ
rel
Function:
Daaoription:
Jump if AccumulatorZero
If all bits of the Accumulatorare zero, branch to the [email protected] otherwiseproceedwith
the next instruction. The branch destination is computedby adding the signed relative-displacement in the second instruction byte to the PC, after incrementingthe PC twice. The
Accumulator is not modified.No flags are affected.
The Accumulator originallycontainsOIH. The instruction sequen~
JZ LABELI
DEC A
JZ LABEL2
will change the Aec.umulator to OOHand cause programexeeutionto continueat the instruction identifiedby the label LABEL2.
Bytea:
Cycles:
“
.4
2
E“ncodirrg: I 0110
Operation:
0000
[
rel. addreee
Jz
(PCJ)
+ (w)+ 2
IF
(A) = O
THEN (PC) t
@C) + rel
2-50
in~.
M=”-51
programmers
GUIDE AND INSTRUCTION SET
LCALL addr16
Function:
Longcall
Description:
LCALLcalls a subroutineIooatedat the indicatedaddress. The instructionadds three to the
program counter to generate the address of the next instruction and then pushes the Id-bit
result onto the stack (low byte first), incrementingthe Stack Pointer by two. The high-order
and low-orderbytesof the PC are then loaded,respectively,with the secondand third bytes of
the LCALLinstruction.Programexeoutionrxmtinueswith the instructionat this address.The
subroutinemaythereforebeginanywherein the full 64K-byteprogrammemoryaddress space.
No ilags are affeeted.
Example:
Initiallythe Stack Pointer equals07H.The label “SUBRTN”is assignedto programmemory
location 1234H.After exeoutingthe instruction,
LCALL SUBRTN
at location0123H,the Stack Pointer will contain09H, internal IL4M Iccations08H and 09H
will contain26H and OIH, and the PC will contain 1234H.
Bytes:
3
Cycles:
2
Encoding:
0001
Operation:
LCALL
0010
I addr’’-add’ I
EEEiEl
(PC) + 3
(SP) + (SP) + 1
((sP)) - (PC74)
(SP) - (SP) + 1
((sP)) - (PC15.8)
(PC) ~ addr15~
(PC) +
UMP
addr16
Function:
Long
Jump
Description:
LJMP causesan unconditionalbranch to the indiested address,by loadingthe high-orderand
low-orderbytes of the PC (respectively)with the second and third instruction bytes. The
destinationmay therefore be anywherein the full 64K program memoryaddress sparx. No
flags are affected.
Example:
The label“JMPADR” is assignedto the instructionat programmemorylocation 1234H.The
instruction
LJMP JMPADR
at location0123Hwill load the programcounter with 1234H.
Cycles:
Enooding:
operation:
2-51
i~.
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
MOV <dest-byte>, <erc-byte>
Function:
Oeacription:
Movebyte vmiable
The byte variableindicatedby the secondoperandis copiedinto the locationspecifiedby the
first operand.The source byte is not affeeted.No other register or flag is at%eted.
This is by far the mmt flexible operation. Fifteen combinationsof source and destination
addressingmodes are allowed.
Example:
Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H.The data
prcaentat input port 1 is 11OO1O1OB
(OCAH).
MOV
MOV
MOV
MOV
MOV
MOV
RO,#30H
A,@RO
R1,A
B,@Rl
@Rl,Pl
P2,PI
;RO < = 30H
;A < = 40H
;Rl < = 40H
;B < = 10H
;RAM (4X-I)< = OCAH
;P2 #OCAH
leavesthe value30Hin register O,40Hin both the Aecumulator and register 1, 10Hitsregister
B, and OCAH(11OO1O1OB)
both in RAM Ioeation40H and output on port 2.
MOV A,Rn
Bytes:
1
Cycles:
1
1110
Encoding:
Operation:
*MOV
lrrr
MOV
(A) + (RIO
A,direct
Bytes:
2
Cycles:
1
Encoding:
Operation:
1110
0101
direct address
MOV
(A) + (direct)
MOV~ACC ie not a valid instruction.
2-52
intd.
[email protected]’SGUIDE AND INSTRUCTION SH
MOV A,@Ri
Bytes:
1.
Cycles:
1
1110
Encoding:
Operation:
Olli
MOV
(A) - (~))
MOV A,#data
Bytes:
2
Cycles:
1
0111
Encoding:
Operation:
0100
I
immediatedata
MOV
(A) + #data
MOV Ftn,A
Bytes:
1
Cycles:
1
Encoding:
I 1111
Operation:
MOV
~) t
I Irrrl
(A)
MOV Rn,direot
Bytee:
.L
Cyclea:
2
Encoding:
I
Operation:
1010
Ilr’rl
-
MOV
([email protected] + (direct)
MOV Rn, #data
Bytes:
cycles:
.
1
Encoding:
0111
Operation:
MOV
([email protected] -
lrrr
immediatedata
#dsts
2-53
irrtd.
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
MOV directJl
Bytetx
2
Cycle$x
1
1111
Encoding:
Operation:
0101
directaddress
MOV
(direct)
- (A)
MOV [email protected]
Bytes:
2
Cyciee:
2
1000
Encoding:
Operation:
Irrr
directaddress
MOV
(direct)
+ (lb)
MOV directjdirect
Bytw
3
Cycie=
2
Encoding:
Operation:
I
1000
0101
I
dir.addr. (src)
dir.addr. (dest)
directaddress
immediatedata I
MOV
(direct) +- (direct)
MOV [email protected]
Bytes:
2
Cycles:
2
1000
Olli
Encoding:
I
Operation:
MOV
(MM) + (w))
MOV direc$xdats
%yte=
3
Cycle=
2
Encoding:
0111
Operation:
MOV
(direct) +
0101
#date
2-54
intd.
MOV
[email protected] AND INSTRUCTION SET
@Ri&
Bcycles:
.1
1
1111
Encoding:
Operation:
MOV
MOV
MOV
Olli
MOV
(@i)) + (A)
@Ri,direct
Bytes:
2
Cycles:
2
I directaddr. I
Encoding:
llOIOIOllil
Operation:
MOV
(@i)) + (direct)
@Ri,#data
Bytes:
2
Cycles:
.1
Encoding:
0111
Operation:
MOV
((RI)) +
Olli
I
immediate data
#data
<cleat-bit>, <erc-bit>
Function:
data
Move bit
Description:
The Booleanvariableindicatedby the second operand is copiedinto the locationspecitkd by
the first operand. One of the operandsmust be the carry flag; the other may be any directly
addressablebit. No other registeror flag is affected.
Example:
The carry tlag is originallyset. The data present at input Port 3 is 11OOO1OIB.
The data
previouslywritten to output Port 1 is 35H (03110101
B).
MOV P1.3,C
MOV C,P3.3
MOV P1.2,C
will leavethecarrycleared and changePort 1 to 39H (OO111OO1B).
2-55
I
I
int&
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
MOV C,blt
Bytes:
2
Cycles:
1
Enooding:
1o1o
Operstion:
MOV
(~+(bit)
1“0’01
EiEl
1“0’01
E
MOV bi&C
Bytes:
.L
Cycles:
2
1001
Enooding:
Operstion:
MOV
MOV
(bit) + (C)
DPTR,#dsts16
Function:
Description:
Load Data Pointer with a Id-bit constant
The Data Pointer is loaded with the Id-bit constant indicated.The id-bit constant is loaded
into the second and third bytes of the instruction. The secondbyte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-orderbyte. No tlags are atTeeted.
This is the only instruction whichmovea 16bits of tits at once.
Example:
The instruction,
MOV DPTR, # 1234H
willload the value 1234Hinto the Data Pointer: DPH willhold 12Hand DPL will hold 34H.
Bytesx
3
Cycles:
.L
Encoding:
Operation:
1001
0000
I immed. dsts15-6
MOV
(DPTR) ~ #data154
DPH ❑ DPL + #&ltS15.8❑ #data73
2-56
I
immed.data7-O
intd.
[email protected]’SGUIDE AND INSTRUCTION SET
MOVC A,@A+<baas-reg>
Function:
Description:
Example:
MoveCode byte
The MOVCinatmctionsload the Accumulatorwith a oode byte, or constant from program
memory.The addressof the byte fetchedis the sum of the originalunsignedeight-bitAccumulator contents and the contents of a sixteen-bitbase register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incrementedto the addressof the following
instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bitaddition is performed so a carry-out from the low-ordereight bits may
propagatethrough higha-order bits. No flags are affected.
A valuebetweenOand 3 is in the Accumulator.The followinginstructionswill translate the
valuein the Accumulatorto one of four valuesdefimedby the DB (definebyte) directive.
REL-PC:
INC
A
MOVC A,@A+PC
RET
DB
66H
DB
77H
DB
88H
DB
99H
If the subroutineis called with the Accumulatorequal to OIH, it will return with 77H in the
Auxmmlator. The INCA beforethe MOVCinstruction is neededto “get around” the RET
instructionabovethe table. If severalbytes of code separated the MOVCfrom the table, the
correspondingnumber wouldbe added to the Accumulator instead.
MOVC [email protected]+ DPTR
Bytes:
1
Cycles:
2
Encoding:
11001
Operation:
MOVC
(A) + ((A) + (D~))
MOVC
10011
I
A,@A + Pc
Bytes:
1
Cycles:
2
Encoding:
Operation:
1000
0011
MOVC
(PC) + (PC) + 1
(A) - ((A) + (PC))
2-57
int&
MOVX
[email protected]’SGUIDE AND INSTRUCTION SET
<dest-byte>, <sin-byte>
Function:
Deaoription:
Move External
data
The MOVX instructions transfer data betweenthe Accumulator and a byte of exa
memory,hence the “X” appendedto MOV.There are two types of instructions,differingin
whetherthey providean eight-bitor sixteen-bitindirect address to the externrddata RAM.
In the first typq the contents of ROor R] in the current register bank providean eight-bit
address multiplexedwith data on PO.Eight bits are sufficient for external 1/0 expansion
decodingor for a relativelysmall RAM array. For somewhatlarger arrays, any output port
pins can be used to output higher-orderaddress bits. These pins wouldbe controlled by an
output instructionprecedingthe MOVX.
In the secondtype of MOVXinstruction,the Data Pointer generatesa sixteen-bitaddress. P2
outputsthe high-ordereight addressbits (the contents of DPH) whilePOmultiplexesthe loworder eightbits (DPL) with data. The P2 SpecialFunction Register retains its previouscontents whilethe P2 ouQut buffers are emitting the contents of DPH. This form is faster and
more efticientwhen accessingvery large data arrays (up to 64K bytes), since no additional
instructionsare neededto set up the output ports.
It is possiblein some situations to mix the two MOVX types. A large R4M array with its
high~rder address lines driven by P2 can be addressed via the Data Pointer,or with code to
output high-orderaddress bits to P2 followedby a MOVX instructionusingROor RI.
Example:
An external256 byte RAM usingmultiplexed
address/&talines(e.g.,an Mel 8155UM/
I/Oflimer) is connected to the 8051Port O. Port 3 provides control lines for the external
W.
Ports 1 and 2 are used for normal 1/0. Registers O and 1 contain 12H and 34H.
Location34Hof the extemsJ RAM holdsthe value 56H. The instructionsequence,
MOVX [email protected]
MOVX
@RO,A
copiesthe value 56H into both the Accumulatorand external RAM location 12H.
2-58
i~o
[email protected] PROGRAMMER’SGUIDE AND INSTRUCTION SET
MOVX &@Ri
Bytes:
1
Cycles:
2
Encoding:
Operation:
1110
OOli
MOVX
(A) - (~))
MOVX [email protected]
Bytes:
1
Cycles:
2
1110
0000
Encoding:
1111
OOli
Operation:
MOVX
Encoding:
Operation:
MOVX
MOVX
@Ri,A
Bytes:
1
Cycles:
2
@DPIR#l
Bytes:
1
cycles:
2
Encoding:
1111
Operation:
MOVX
(DPTR) -
0000
(A)
2-59
i~e
MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET
MUL AB
Multiply
Deeoriptiors:
Example
MUL AB multipliesthe unsignedeight-bit integers itsthe Accumulator and register B. The
Iow-orderbyteof the sixteen-bitproduct is left in the Accumulator,and the high-orderbyte in
B. If the product is greater than 255 (OPPH)the ovcrtlowflag is set; otherwiseit is cleared.
The carry fiag is alwayscleared.
Originallythe Accumulatorholds the value 80 (50H).RegisterB holds the value 160(OAOH).
The instruction,
MuLAB
will givethe product 12,S00(3200H),so B is changedto 32H(OO11OO1OB)
and the Accumulator is cleared. The overflowflag is set, carry is cleared.
Bytes:
1
Cycles:
4
Encoding:
I 101
OIO1OOI
Operation:
MUL
(A)74 + (A) X (B)
(B)15-8
NOP
Function:
No Operation
Description:
Executioncontinuesat the followinginstruction. Other than the PC, no registersor flagsare
affected.
Example:
It is desired to producea low-goingouQut pulse on bit 7 of Port 2 lasting exactly5 cycles.A
simple SETB/CLRsequencewouldgeneratea one-cyclepulse,so four additionalcyclesmust
be inserted. This may be done (ssauming no interrupts are enabled) with the instruction
SeqUenee,
CLR
NOP
NOP
NOP
NOP
SETB
Bytes
P2.7
P2.7
1
Cycles: 1
Encoding:
000010000
Operation: NOP
(PC)+ (-PC)
+1
2-00
in~.
[email protected]’SGUIDE AND INSTRUCTION SET
ORL <dest-btie> <src-byte>
Funotion:
Logicsl-ORfor byte variables
ORL performs the bitwiselogical-ORoperationbetweenthe indicated variables,storing the
results in the destinationbyte. No flags are affected.
The two operandsallowsixaddressingmodecombinations.Whenthe destinationis the Accumulator, the source can use register, direct, register-indirect,or immediateaddressing;when
the destinationis a direct addreas,the source can be the Accumulatoror immediatedata.
Note.-When this instructionis used to modifyan output port, the value used as the original
port dats will be resd from the output data latch, not the input pins.
Example:
If the Accumulator holds OC3H(I1OOOO1IB)
and ROholds 55H (O1O1O1O1B)
then the instruction,
ORL A,RO
will leave the Accumulatorholdingthe value OD7H(110101llB).
When the destinationis a directlyaddreasedbyte, the instructioncan set combinationsof bits
in any RAM location or hardware register. The pattern of bits to be set is determinedby a
mask byte, whichmaybe eithera constantdata valuein the instructionor a variablecomputed
in the Aecunndator at rim-time.The instruction,
ORL P1,#OOllOOIOB
will set bits 5,4, and 1 of output Port 1.
ORL &Rn
Bytes:
1
Cycles:
1
Encoding:
Operstion:
0100
lrrr
ORL
(A) +- (A) V K)
2-61
i~e
M=a-sl
PROGRAMMER’S
GUIDEAND INSTRUCTION SET
ORL &direct
Bytes:
2
Cycles:
1
Encoding:
1010010101
Operation:
ORL
I
directaddress
(A) + (A) V (direct)
ORL &@Ri
Bytes:
1
Cycles:
1
Olli
0100
Encoding:
Operation:
ORL A,#dets
Bytes:
2
Cycles:
1
Encoding:
Iolool
Operation:
ORL
(A) -
immediatedata
O1oo1
(A) V #dsts
ORL direct,A
Bytes:
Cyclea:
1
0100
Encoding:
Operation:
0010
directaddress
ORL
(direct) ~(direct)
V (A)
ORL direcQ*data
Bytes:
3
Cycles:
2
Encoding:
Orwstion:
0100
ORL
(direct)+
0011
I
EEEl
(direct) V #data
2-62
immediate date
I
in~.
[email protected]’S GUIDE AND INSTRUCTION SET
ORL C,<src-bit>
Function:
Description:
Example:
Logical-ORfor bit variables
*t
the carry flagif the Booleanvalue is a logical 1; leave the carry in its current state
otherwise. A slash (“/”) precedingthe operand in the assemblylanguageindicatesthat the
logicalcomplementof the addressedbit is used as the source value,but the sourcebit itselfis
not at%cted.No other tlags are afkcted.
Set the carry flag if and only ifP1.O = 1, ACC. 7 = 1, or OV = O:
MOV CPI.O
;LOAD CARRY WITH INPUT PIN P1O
ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7
ORL Wov
;OR CARRY WITH THE INVERSEOF OV.
ORL C,bit
Bytes:
2
Cycles:
2
0111
Encoding:
IOO1OI
EEl
Operation:
ORL C,/bit
Bytes:
2
Cycles:
.
Encoding:
Operation:
I 1010
100001
ORL
(c)+ (c) v @=)
EEEl
2-63
i~.
M~eI-51 programmers
GUIDE AND INSTRUCTION SET
POP direot
mrsctiom Pop from stack.
The contents of the internal RAM location addressedby the Stack Pointer is read, and the
Stack Pointer is decrementedby one. The value read is then transferred to the directly addressedbyte indicated.No flags are affected.
Example:
The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OIH, respectively.The instructionsequen~
POP DPH
POP DPL
willleavethe Stsck Pointer equal to the value30Hand the Data Pointer set to 0123H.At this
point the instruction,
POP SP
will leave the Stick Pointer set to 20H. Note that in this special case the Stack Pointer was
*remented to 2FH beforebeing loaded with the value popped (20H).
Bytea:
2
Cycla$s
2
Encoding:
I 1101
0000
Operation:
POP
(direct) + ((sP))
(SP) 4-(SP) – 1
directaddress
PUSH direct
Function:
Description:
push onto stack
The StackPointeris incrementedby one. The contentsof the indicatedvariableis then copied
into the internal RAM locationaddressedby the Stack Pointer. Otherwiseno flagsare affected.
On entaing an interrupt routine the Stack Pointercontains09H. The Data Pointer holds the
value O123H.The instruction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBHand store 23H and OIH in internal FL4Mlocations
OAHand OBH,respectively.
Bytes: 2
Cycletx 2
Enooding:
Operation:
1100
0000
I directaddreaa
PUSH
(SP) + (SP) + 1
((SP))- (direct)
2-04
int&
M~tV-51 PROGRAMMER’SGUIDEANDINSTRUCTIONSET
RET
Function:
Return tlom subroutine
Description:
RET pops the high-and low-orderbytes of the PC successivelyfrom the staclGdecrementing
the Stack Pointer by two. Program executioncontinuesat the resultingaddress,generallythe
instruction immediatelyfollowingan ACALLor LCALL. No tlags are affected.
Example:
The Stack Pointer originallycontains the valueOBH.Internal RAM locationsOAHand OBH
contain the value-a23H and OIH, respectively.The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program executionwill continue at
Ioeation0123H.
Bytm
1
cycles:
2
Encoding:
10010100101
Operation:
RET
(Pc~~-s)
+- ((sP))
(SP) +(SP)
– 1
(PC74) + ((sP))
(SP) + (SP) -1
RETI
Function:
Return from interrupt
Description:
RETI pops the high- and low-orderbytes of the PC successivelyfrom the stack, and reatores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed.The Stack Pointer is left decrementrdby two. No other registersare aik%sd; the
PSW is not automaticallyrestored to its pre-interruptstatus. Program executioncontinuesat
the resultingaddress, which is generallythe instructionimmediatelyafter the point at which
the interrupt requestwas detected. Ifa lower-or same-levelinterrupt had beenpendingwhen
the RETI instruction is executed, that one instruction will be executedbefore the pending
interrupt is processed.
Exemple:
The Stack Pointer originally contains the value OBH.An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAHand OBHcontain the
values 23H and OIH, reapeotively.The instruction,
RETI
wilt leave the Stack Pointer equat to O$IHand return program executionto locationO123H.
Bytes: 1
Cyclee: 2
Encoding:
Operation:
10011
I 00101
(PCls.s)
+ ((sP))
(sP)+
(SP) -1
(PC74) + ((sP))
(SP) -(SP)
-1
2-65
intd.
M=”-51
PROGRAMMER’SGUIDE AND INSTRUCTION SET
RL A
Function:
Description:
Example:
Rotate Aecurnulator Left
The eight bits in the Aeeurmdatorare rotated one bit to the left. Bit 7 is rotated into the bit O
position.No flagsare akted.
The Aeeumulatorholds the value OC5H(11OQO1O1B).
The instruction,
RLA
leavesthe Accumulatorholdingthe value 8BH (1OOO1O11B)
with the carry unaffected.
Bytes:
Cycle=
1
L
0010
Encoding:
Operation:
0011
I
RL
(~ + 1) - (An) n = O – 6
(AO)+ (A7)
RLC A
Function:
Rotate Accumulator L-et?through the Carry flag
Description:
The eightbits in the Aeeumulator and the carry tlag are togetherrotated onebit to the left. Bit
7 movesinto the carry flag;the originalstate of the carry tlag movesinto the bit Oposition.No
other flags are affeeted.
Example:
The Accumulatorholds the valueOC5H(110CHI101B),
and the carry is zero. The instruction,
RLC A
leavesthe Accumulatorholdingthe value 8BH (1OOO1O1OB)
with the carry set.
Bytes:
Cycle=
Encoding:
Operation:
1
1
0011
0011
RLc
(An+ 1)~ (An) n = O –
6
(AO)+ (C)
(C) +- (A7)
2-66
intd.
[email protected] PROGRAMMER’S GUIDE AND INSTRUCTION SET
RR A
Functiorx
Description:
Example:
Rotate AccumulatorRight
The eight bits in the Aeoumulatorare rotated onebit to the right. Bit Ois rotated into the bit 7
position.No flags are affected.
The Accumulator holds the value OC5H(11COO1O1B).
The instruction,
RRA
leavesthe Aecmmdatorholdingthe value OE2H(111OOOIOB)
with the carry unattested.
RRC
Bytes:
1
cycles:
1
Encoding:
0000
Operation:
RR
(An) +
(A7) -
0011
(An + 1) n = O – 6
(AO)
A
Rotate Aeeumulator Right through Carry flag
Description:
Example:
The eightbits in the Accumulatorand the carry flag are togetherrotated one bit to the right.
Bit O moves into the carry tlag; the originrd value of the carry flag moves into the bit 7
position.No other figs are affected.
The Accumulator holds the value OC5H(11OOO1O1B),
the carry is zero. The instruction,
RRC A
leavesthe Accumulatorholdingthe value 62 (O11OOO1OB)
with the carry set.
Bytes:
1
cycles:
1
Encoding:
0001
Operation:
RRc
(An) +
0011
(h
(A7) - (C)
(C) + (AO)
+ 1) n = O – 6
2-67
i~e
SETB
M([email protected] PROGRAMMER~SGUIDE AND INSTRUCTION SET
<bit>
Function:
Set Bit
SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressablebit. No other flags are affected.
Example:
The carry flagis clesred.Output Port 1has beenwritten with the value34H(OO11O1OOB).
The
instructions,
SETE C
SETB PI.O
will leave the carry tlag set to 1 and changethe data output on Port 1 to 35H (OO11O1O1B).
SETB
C
Bytes:
1
cycles:
1
Encoding:
11101
Operation:
SETB
(c) + 1
10011
I
SETB bit
Bytes:
2
cycles:
1
Encoding:
Operation:
1101
100101
EiEEl
SETB
(bit)+ 1
2-68
i~.
[email protected]’S GUIDE AND INSTRUCTION SET
SJMP rel
Function:
Short JurnP
Deaoription:
Programcontrol branchss unconditionallyto the address indicated.The branch destinationis
computedby adding the signed displacementin the second instructionbyte to the PC, after
incrementingthe PC twice. Therefore, the range of destinationsallowedis from 128bytes
precedingthis instruction to 127bytes followingit.
Example:
The label“RELADR” is assignedto an instruction at program memorylocation0123H.The
instruction,
SJMP RELADR
will assembleinto location O1OOH.
After the instruction is executed,the PC will ccmti the
value0123H.
(Norc Under the aboveconditionsthe instruction followingSJMPwillbeat 102H.Therefore,
the displacementbyte of the instructionwillbe the relativeoffset(O123H-O1O2H)
= 21H. Put
another way,an SJMP with a displacementof OFEHwouldbe a one-instructioninfiniteloop.)
Bytes:
2
Cycles:
2
Encoding:
Operation:
1000
100”01
EEl
SJMP
(PC) + (PC) + 2
(PC) -
(PC) + rel
2-69
[email protected]
MCS”-51PROGRAMMER’S
GUIDEANDINSTRUCTIONSET
SUBB A<sro-byte>
Function:
Deeoription:
Subtract with bOrrOW
SUBBsubtracts the indicated variable and the carry tlag together from the Accumulator,
lesvingthe result in the Accumulator.SUBBsets the carry (borrow)tlag if a borrowis needed
for bit 7, and cleam C otherwise. (H c was set bqfors executing a SUBBinstruction, this
indicates
that
a borrow was neededfor the previousstepin a multipleprecisionsubtraction,so
the csrry is subtracted from the Accumulatoralong with the source operand.)AC is set if a
borrowis neededfor bit 3, and clearedotherwise.OVis set ifa borrowis neededinto bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtraetm
“ g signedintegersOV indicatesa negativenumber produwd whena negative
value is subtracted from a positive value, or a positive result when a positive number is
subtractedfrom a negativenumber.
The sourceoperandallowsfour addressingmodes:register,direct, register-indirecLor immediate.
The AccumulatorholdsOC9H(11OO1OO1B),
register2 holds 54H (O1O1O1OOB),
and the carry
flag is set. The instruction,
SUBB A,R2
will leavethe value 74H (O1I1O1OOB)
in the accumulator,with the cany flag and AC cleared
but OVset.
Notice that OC9Hminus 54H is 75H.The differencebetweemthis and the aboveresult is due
to the carry (borrow)flag beingset beforethe operation.If the state of the carry is not known
before starting a singleor multiple-precisionsubtraction, it should be explicitlycleared by a
CLR C instruction.
SUBB A,Rn
Bytes:
1
Cycles:
1
Irrr
Encoding:
I 1001
Operation:
SUBB
(A) - (A) - (C) - (IQ
2-70
intel.
MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET
SUBB ~direct
Bytes:
2
cycles:
1
1001
0101
Encoding:
I
Operation:
SUBB
(A) - (A) – (C) – (direct)
I
directaddress
SUBB [email protected]
Bytes:
1
cycles:
1
Encoding:
I1OO1
Operation:
SUBB
(A) - (A) - (C) - ((M))
IOllil
SUBB A,4$dats
Bytes:
.f
Cycles:
1
1001
Encoding:
Operation:
SWAP
0100
I immediate data
SUBB
(A) - (A) - (C) – #data
A
Function:
Description:
Example:
Swapnibbleswithinthe Accumulator
SWAP A interchange the low- and high-ordernibblea(four-bit fields) of the Accumulator
(bits 3-0md bits 7-4).The operationcan ako be thoughtof as a four-bitrotate instruction.No
flags are affected.
The Accumulatorholdsthe value OC5H(11OO31O1B).
The instruction,
SWAP A
leavesthe Accumulatorholdingthe value 5CH (O1O111OOB).
Bytes:
1
Cycles:
1
Encoding:
Operation:
1100
0100
SWAP
(A3-0)~ (A7-4)
2-71
intd.
MC=’-5l PROGRAMMER’SGUIDEANDINSTRUCTIONSET
XCH Aj<byte>
Function:
BxchangeAccumulatorwith byte variable
Description:
XCH leads the Accumulatorwith the contents of the indicated variable, at the same time
writing the originalAccumulator contents
to the indicated variable. The source/destination
operand ean w register,direet, or register-indirectaddressing.
Example:
ROcontains the address20H. The Accumulatorholds the value 3FH (OO1lllllB). Internal
RAM location20H holds the value 75H (01110101B).The instruction,
X3-I
A,@RO
will leaveRAM location20H holdingthe values3FH (0011111IB) and 75H (O111O1O1B)
in
the accumulator.
XCH
A,Rn
Bytee:
1
Cycles:
1
1100
Encoding:
Operation:
XCH
XCH
(A) z ([email protected]
A,direct
Bytes:
2
Cycles:
1
1100
Encoding:
Operation:
XCH
Irrr
0101
I
directaddress
XCH
(A) z (direet)
A,@Ri
Bytes:
1
cycles:
1
Encoding:
Operation:
1100
Olli
XCH
(A) ~ (@))
2-72
i~.
MCS”-51 programmers
GUIDE AND INSTRUCTION SET
XCHD A,@Ri
Funotion:
ExchangeDigit
XCHD exchangesthe low-ordernibbleof the Accumulator(bits 3-O),generallyrepresentinga
hexadecimalor BCD digit,withthat of the internal IGUkilocationindirectlyaddressedby the
sapp~ti=gister. me high-ordernibbles(bits 7-4) of each register are not af%cted.No tlsgs
Example:
Internal
ROcontains the address 20H. The Accunndator holds the value 36H (OO11O1IOB).
W
location 20H holdsthe value 75H (O111O1O1B).
The instruction,
XCHD A,@RO
willleaveRAM location20Hholdingthe value76H(O111O11OB)
and 35H(OIM1O1O1B)
in the
Accumulator.
Bytes:
1
cycles:
1
Encoding:
1101
Operation:
XCHD
Olli
(A~~) Z ((lti~~))
XRL
<cleat-byte>, <src-byte>
Function:
Description:
LogicalExclusive-ORfor byte vsriablea
XRL performs the bitwiselogicalExcIusive-ORoperation between the indicated variables,
storing the results in the destination.No flags are affected.
The two operandsallowsixaddressingmode combinations.Whenthe destinationis the Accumulator, the source can use register,direcL register-indirect,or immediateaddressing;when
the destinationis a direct address,the source can be the Accumulatoror immediate data.
(Note When this instructionis used to modifyan output port, the value used as the original
port dats will be read from the output data latch, not the input pins.)
Example:
If the Accumulator holdsOC3H(11000011B)and register Oholds OAAH(101OIO1OB)
then
the instruction,
XRL A,RO
will leavethe Accumulator holdingthe vatue 69H (O11OIOOIB).
When the destinationis a directlyaddressedbyte this instructioncan complementcombina-
tionsofbitsinanyMM locationor hardwareregister.Thepatternofbitstobecomplemented by a maskbyte eithera constsntcontainedin the instructionor a
ed is then determin
variable computedin theAccumulator
at run-time.Theinstruction,
XRL Pl,#OOllOOOIB
will complementbits 5, 4, and Oof output Port 1.
2-73
intJ
I(RL
MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET
A,ml
Bytes:
1
Cycles;
1
Encoding:
Operation:
Irrr
0110
XRL
(4+-
(4
~ (W
XRL A,direct
Bytes
2
Cycles:
1
Encoding:
10110101011
Operation:
XRL
] directaddress I
(A) + (A) V (direct)
XRL
A,@Ri
Bytes:
1
Cycles:
1
Enwding:
0110
Olli
0110
01001
Operation:
XRL
A,#data
Bytes:
2
Cycles:
1
Encoding:
Operation:
I immediatedats I
XRL
(A) + (A) V #data
XRL
[email protected]
Bytes:
cycles
Encoding:
Operation:
2
1
0110
0010
direct address
XRL
(dinzt) + (direct) V (A)
2-74
[email protected]’SGUIDE AND INSTRUCTION SET
XRL
[email protected] #date
Bytea:
3
Cydea: 2
Encoding:
0110
Operation:
XRL
(direct)+
0011
I
direct address
(direct) Y #data
2-75
immediate date
8
and 80C51
0
Hardware Description
53
8051,8052 and 80C51 Hardware Description
CONTENTS
CONTENTS
PAGE
INTRODUCTION ........................................ 3-3
Special Function Registers ......................... 3-3
PORT STRUCTURES AND
OPERATION........................................... 3-6
[/0 Configurations....................................... 3-7
Writing to a Port .......................................... 3-7
Port Loading and Interfacing ...................... 3-8
Read-Modify-Write Feature ........................ 3-9
PAGE
INTERRUPTS ........................................... 3-23
Priority Level Structure ............................. 3-24
How Interrupts Are Handled ..................... 3-24
External Interrupts .................................... 3-25
Response Time. ........................................ 3-25
SINGLE-STEP OPERATION.................... 3-26
RESET...................................................... 3-26
ACCESSING EXTERNAL MEMORY.........3-9
POWER-ON RESET................................. 3-27
TIMEWCOUNTERS ................................... 3-9
Timer Oand Timer 1.................................. 3-10
Timer 2...................................................... 3-12
POWER-SAVING MODES OF
OPERATfON ......................................... 3-27
CHMOS Power Reduction Modes ............ 3-27
SERIAL INTERFACE ............................... 3-13
Multiprocessor Communications .............. 3-14
Serial Port Control Register ...................... 3-14
Baud Rates...............................................3-15
More About Mode O.................................. 3-17
More About Mode 1 .................................. 3-17
More About Modes 2 and 3 ...................... 3-20
EPROM VERSIONS .................................3-29
Exposure to Light...................................... 3-29
Program Memory Locks ........................... 3-29
ONCE Mode ............................................. 3-30
THE ON-CHIP OSCILLATORS ................3-30
HMOS Versions ........................................ 3-30
CHMOS Versions ..................................... 3-32
INTERNAL TIMING .................................. 3-33
3-1
8051, 8052 AND 80C51
HARDWARE DESCRIPTION
INTRODUCTION
Thischapter preaents a comprehensivedescription of
●
The EPROMversionsof the 8051AH, 8052AHand
80C51BH
The devicesunder considerationare listed in Table 1.
As it becomesunwieldyto be constantly referring to
each of these devicesby their individualnam~ we will
adopt a convcmtionof referring to them genericallyas
8051sand 8052s,unlessa specificmemberof the group
is beingreferred to, in which case it willbe specifically
named. The “8051s” include the 8051AH, 80C51BH,
and their ROMlessand EPROM versions.The “8052s”
are the 8052AH,8032AHand 8752BH.
the on-chip hardware featuresof the [email protected] Includedin this descriptionare
● The port drivers and how they function both as
ports and, for Ports Oand 2, in bus operations
● The Timer/Counters
● The Serial Interface
● The Interrupt System
● Reset
. The ReducedPower Modesin the CHMOSdevices
Figure 1showsa functionalblockdiagramof the 8051s
and 8052s.
Table 1.The MCS-51 Family of Mien ontroiiera
[
1
Devioe
Name
8051AH
8052AH
80C51BH
I
ROMleaa
Version
EPROM
Veraion
ROM
Bytes
8031AH
8032AH
80C31BH
8751H, 8751BH
8752BH
87C51
4K
8K
4K
m
SpecialFunctionRegisters
A map of the on-chipmemoryarea called SFR (SpecialFunctionRegister)spaceis shownin Figure2. SFRSmarked
by parentheses are residentin the 8052sbut not in the 8051s.
3-3
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
i~.
PO.O-PQ.7
P2.O-P2.7
I
/
I
I
B
mAo~:AAt
v
REGISTER
mm?
REG%TER
BUFFER
I
r
I
I
I
I [
INCRE%[email protected]
I
I
PORTANDTIMER
BLOCKS
WA
Ee
ALE
TIMING :K’
>~
C2#%OL ~:
=g
RST
I
I
/
[
I
li~
P
POUT1
PORT3
LATCH
LATCH
‘=
mmi
–-–––
XTAL1
Pom3
ORWERS
DRIVERS
——————
X7AL2
4&JJ
w
P3,0-P1.7
..
——
———
—,
‘Rddenli. 805s/s0320mJy.
P3,0-P3.7
=
270252-1
Figure 1. MCS-51 Architectural Block Diagram
3-4
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
8Bytes
F8
FO
FF
B
F7
E8
EO
EF
ACC
E7
lx
Do
C8
DF
Psw
,
,
(T2CON) I
(RCAP2L)
I
(-m)
I
1.
m
(RCAP2H)
D7
1
CF
(TH2)
[
1
[
c?
S8
,,
BO
Ps
B7
AS
AF
AO
IE
m
98
S&N
90
PI
88
T&N
80
Po
BF
I
I
1
1
I
i
1
I,
II
I1
II
I,
I1
A7
SBUF
I
9F
TMOD
TLO
TL1
SP
DPL
DPH
THO
THI
97
8F
I
I
PCON
87
Figure 2. SFR Map. (... ) Indicates Resident in 8052s, not in 8051s
Note that not all of the addressesare occupied.Unoccupied addreaaea are not implementedon the chip.
Read accemesto theae addresseawill in general return
random [email protected] and write accesseswillhave no effect.
to hold a 16-bitaddress. It may be manimdatedas a
id-bit register or as two ind~-dent 8-bit-registers.
User software should not write 1s to these unimplemented locations, since they may be used in future
MCS-51producta to invokenew features. In that case
the reset or inactive values of the newbits will always
be O,and their active values willbe 1.
PO,Pl, P2 and P3 are the SFR latches of Ports O,1,2
PORTS O TO 3
and 3, respectively.
SERiAL DATA BUFFER
ACC is the Accumulator register.The mnemonicsfor
Accmnulator-Speciticinstructions, however, refer to
the Accumulatorsimply as A.
The Serial Data ButTeris actually two separate registers, a transmit butTerand a receive butTerregister.
When &ta is movedto SBUF, it goes to the transmit
buffer where it is held for aerial transmission.(Moving
a byte to SBUF is what initiatea the transmission.)
When data is moved from SBUF, it comes from the
receivebuffer.
B REGISTER
TIMER REGiSTERS
The B register is used during multiplyand divideoper-
ations.For other instructionsit can be treated as another scratch pad register.
Register pairs (THO,TLO), (TH1, TL1), and (TI-D,
TL2) are the id-bit Countingregistersfor Timer/Counters O, 1, and 2, reqectively.
PROGRAM STATUS WORD
CAPTURE REGiSTERS
The fi.mctionsof the SFRSare outlinedbelow.
ACCUMULATOR
The PSWregister contains program status
as detailedin Figure 3.
information
The register pair (RCAP2H RCAP2L) are the Capture registetxfor the Timer 2 “Capture Mcde.” In this
mode, in responseto a transition at the 8052’sT2EX
pin, TH2 and TL2 are copied into RCAP2H and
RCAP2L. Timer 2 alsohas a 16-bitauto-reloadmode,
and RCAP2H and RCAP2Lhold the reload valuefor
this mode. More about Timer 2’s festures in a later
section.
STACKPOINTER
StackPointer Register is 8 bitswide.It is incrementedbefore data is stored duringPUSH and CALL
executions.Whilethe stack mayresideanywherein onchip RAM, the Stack Pointer is initializedto 07H after
a reset. This causes the stack to beginat location08H.
The
CONTROL REGiSTERS
DATA POiNTER
Special Function Registers 1P, IE, TMOD, TCON,
T2CON,SCON,and PC(3Ncontain control and status
bits for the interrupt system,the Timer/Count~ and
the serial port. They are describedin later sections.
The Data Pointer (IXTR) consists of a high byte
(DPH) and a low byte (DPL). Its intendedftmction is
3-5
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
(MSB)
I
symbol
CY
(LSB)
I
AC
Rsl
I
f&nseand
Slgniflemee
PoeJtlOn
CY
PSW.7
Calwflaa.
AC
PSW.6
Ausii~-&yfleg.
(For SCD~rafiLWs.)
PSW.5
FO
FO
RSO
Symbol
Ov
—
P
PoaStlon
Ov
—
PSW.2
Psw.1
P
Psw.o
Name and Slgnifiaanee
Overflow
fiag.
Uaerd&fneMe flag.
Parifyfleg.
Saflclesred by hardwsm eaeh
insfmfion cycle to indicatean odd/
swannumber of “one” bits in the
Aecumulatw, i.e., even parity.
FlagO
(Availabletofhe uaerforgenersl
PSW.4
PSW.3
RSI
RSO
Pm-.)
lWaterbsnk edectsontrol
O.Set/cleared tyadhssreto
1
b~ I &
NOTE:
The contents of (RS1, RSO) enable the working register banks as
follows:
(0.0)-Bank O
(OOH-07H)
(08 H-OFH)
(0.1)-Senk 1
(1.0)-Bank 2
(1OH-17H)
(1.1)-sank 3
(18H-lFH)
dstermineworking mgisterbank (see
Note).
Figure 3. PSW: Program Status Word Register
AODR/OATA
READ
LATCH
INT.BuS
WRITE
TO
LATCH
REAO
PIN
270252-3
2702S2-2
B. Port 1 Bit
A. Porf OBit
P.oon
READ
LATCH
CONTROL
ALTERNATE
OUTPUT
FUNCTION
Vcc
INT.BuS
WRITE
d
TO
LATCH
REAO
PIN
-.
FUNCTION
270252-4
270252-5
C. Port 2 Bit
D. Port 3 Bit
Figure 4.8051 Port Bit Latches and 1/0 Buffers
*SeeFigure5 for detailsof the internal pultup.
external memory addres3, time-multiplexedwith the
byte beingwritten or read. Port 2 outputs the highbyte
of the external memoryaddress when the address is 16
bits wide. Otherwisethe Port 2 pine continue to emit
the P2 SFR content.
PORT STRUCTURESAND
OPERATION
AUfour ports in the 8051are bidirectional.Each consists of a latch (SpecialFunction Regietera PO through
P3), en output driver, and an input buflkr.
All the Port 3 pina,and (in the 8052)two Port 1 pins
are multifunctional.They are not onfy port pins, but
afao serve the functionsof various special featurea as
listed on the followingpage.
The output driversof Ports Oand 2, and the input butFera of Port O,are used in ameaaesto external memory.
In this application,Port Ooutputs the low byte of the
3-6
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Port Pin
“P1.o
Alternate Function
T2 (Timer/Counter2
*P1.1
externalinput)
T2EX(Timer/Counter2
Capture/Reloadtrigger)
P3.O
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ADDIVDATA BUS).To be usedas an input, the port
bit latch must contain a 1, which turns off the output
driver FBT. Then, for Ports 1, 2, and 3, the pin is
pulled high by the internal puflup,but can be pulfed
low by an external source.
RXD (serialinputport)
TXD (serialoutputport)
INTO(externalinterrupt)
~
(externalinterrupt)
TO (Timer/CounterOexternal
input)
T1 (Timer/Counter I external
input)
~ (externalData Memory
write strobe)
~ (external DataMemory
Port Odiffersin not havinginternsdpullups.The ptiup
FBT in the POoutput driver (seeFigure4) is used onfy
when the Port is ernitdng 1s during external memory
accasea otherwise the pullupFET is off. ConaequentIy POlima that are being used as output port lines are
open drain. Writing a 1 to the bit latch leaves both
output FETs off, so the pin floats. In that conditionit
can be used a high-impedanceinput.
BecausePorts 1, 2, and 3 have fixed internaf pullups
they are sometimescalled “qussi-bidirectional”porta.
Whets eontigured as inputs they pull high and will
sourcecurrent (IIL, in the data sheets)whenextemafly
pulled low. Port O, on the other hand, is considered
“true” bidirectional,[email protected] as an input it floats.
readstrobe)
●P1.Oand P1.1 serve these aftemate fuctions onlyon
the 8052.
The alternate functionscan onlybe activatedif the correspondingbit latch in the pm-tSFR containsa 1.0therwise the port pin is stuck at O.
Affthe port latches itsthe 8051have 1swritten to them
by the reset function.If a Ois subsequentlywritten to a
port latch, it can be reconfiguredas an input by writing
a 1 to it.
1/0 Configurations
Writingto a Port
Figure 4 shows a fictional diagram of a typical bit
latch and 1/0 buffer in each of the four ports. The bit
latch (one bit its the port’s SFR) is represented as a
Type D tlipflop, which will clock in a value from the
internal bus in response to a “write to latch” signal
from the CPU. The Q output of the tlipflop is placed
on the intersttdbus itsresponseto a “read latch” signal
from the CPU. The levelof the port pin itselfis placed
on the internal bus in response to a “read pin” signal
from the CPU. Someinstructionsthat read a port activate the “read latch” signal, and others activate the
“read pin” signal.More about that later.
In the executionof an instructionthat changesthe value in a port latch, the new value arrives at the latch
during S6P2of the final cycleof the instruction. However, port latches are in fact sampledby their output
buffers O~Y during Phase 1 of SSlyclock period. @IKittg Phase 2 the output buffer holds the value it saw
during the previous Phase 1). Consequently,the new
value in the port latch won’t actually appear at the
output pin until the next Phase 1,whichwillbe at SIP1
of the next machinecycle.SeeFigure39in the Internal
Timingsection.
As shownin Figure4, the output drivers of Ports Oand
2 are switchableto an istternrdADDR and ADDR/
DATA bus by an internal CONTROLsignalfor w its
external memoryaccesam.During external memoryaccesses,the P2 SFR rcsrm“nsunchanged,but the POSFR
gets 1s written to it.
If the changerequiresa O-to-1transitionin Port 1,2, or
3, art additional pullup is turned on during SIP1 and
S1P2of the cyclein whichthe transitionocmu-s..This is
done to increasethe transition speed.The extra pullup
can sourceabout 100timesthe current that the normal
pullup can. It shouldbe noted that the internal pttllups
are field-effecttransistors, not linear resistors.Tlseptdlup -CInCntS
are shownin Figure 5.
Nso shownin Figure4, is that ifa P3 bit latch contains
a 1, then the output level is controlled by the signal
labeled “alternate output function.” The actual P3.X
pin levelis afwaysavailableto the pin’salternate input
function, if any.
In HMOS veraionsof the 8051,the fixed part of the
pullup is a depletion-modetransistor with the gate
wiredto the source.This transistorwillallowthe pin to
source about 0.25 mA when shorted to ground. In
parallel with the fixed pullupis assenhancement-mode
transistor, which is activated during S1 wheneverthe
port bit doesa O-to-1transition.Duringthis intervaf,if
the port pin is shorted to ground,this extra transistor
will allowthe pin to sourcean additional30 sttA.
Ports 1,2, and 3 have internal puUups.Port Ohas open
drain outputs.Each I/O line ean be independentlyused
as an input or an output. (Ports O and 2 may not be
used as general purpose I/O whetsbeing used as the
3-7
intd.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Vcc
Vv,,
270252-6
HMOS Configuration. The enhancement mode transistor
is turned on for 2 OSC.periods after~ makes a O-to-1 transition.
A.
‘JCc
WC
%c
2 OSC.PERIODS
PI
b
n
6 D
FROMPORT
LATCH
1’-
‘
=-’@-’@
D-J
“AD
PORTPIN
270262-7
B. CHMOS Configuration. pFET 1 is turned on for 2 OSC.periods after~
makes a O-to-1transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch whioh holds the 1. pFET 2 is also on.
Figure 5. Porta 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Exoept That It Holds The Strong Pullup On While Emitting
1s That Are Address Bits. (See Text, “Acceaaing External Memory”.)
In the CHMOSversions,the pullup consists of three
DFETs. It shordd be noted that an n-channel FET
@ET) is turned on wherea logical 1 is applied to its
gate, and is turned off whena logicalOis appliedto its
gate. A p-channelFET (pFET) is the opposite:it is on
when its gate seesa O,and off when its gate sees a 1.
Port Loadingand Interfacing
The output buffersof Porta 1,2, and 3 ean each drive4
LS TTL inputs. These porta on HMOSversionscan be
drivenin a normal manner by any ITL or NMOS cirenit. Both HMOS and CHMOS @lS can be dliVell by
open-collectorand open-drainoutputs, but note that Oto-1transitions will not be fast. In the HMOSdevi~ if
the pin is driven by an open-cdleetor output, a O-to-1
transition will have to be drivenby the relativelyweak
depletionmode FET in Figure 5(A). In the CHMOS
device,sssinput OtllmSOffpldklppFET3, kwislg Only
the very weak pullup pFET2 to drive the transition.
pFETl in Figure5 is the transistor that is turned on for
2 oscillatorperiodsafter a O-to-1transition in the port
latch. While it’s on, it turns on PFET3 (a weak pullUP),throughthe inverter.This inverterand pFET form
a latch whichhold the 1.
Note that if the pin is emittinga 1, a negativeglitch on
the pin from someexternal sourceean turn off PFET3,
causingthe pin to go into a float state. pFET2 is a very
weak pullup whichis on wheneverthe nFET is off, in
traditional CMOSstyle.It’s onlyabout ‘/10the strength
of pFET3.Its functionis to restorea 1 to the pin in the
event the pin had a 1 and lost it to a glitch.
In external bus mode, Port Ooutput buffers can each
drive8 L3 ITL inputs. As port pins,they require external pultups to drive any inputs.
3-8
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Whenevera id-bit addressis used, the highbyte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle.Note that the Port 2
drivers use the strong pullups during the entire time
that they are emittingaddress bits that are 1s. This is
duringthe executionof a [email protected]
Duringthis time the Port 2 latch (the SpecialFunction
Register)does not haveto contain 1s,and the contents
of the Port 2 SFR are not modified,If the external
memory cycle is not immediatelyfoflowedby another
external memorycycle,the undisturbedcontentsof the
Port 2 SFR will reappearin the next cycle.
Read-Modify-WriteFeature
Someinstructions that read a port read the latch and
others read the pin. Whichonesdo which?The instructionsthat read the latch rather than the pin are the ones
that read a value possiblychangeit, and then rewrite it
to the latch. These are called “read-modify-write”instructions.The instructionslisted beloware read-modify-writeinstructions. When the destinationoperand is
a wrt, or a PII bit, these instructions read the latch
rather than the pin:
ANL
(logicalAND, e.g., ANL PI, A)
ORL
(logicalOR, e.g., ORL P2, A)
(logicalEXIOR,e.g., XRL P3, A)
XRL
JBC
(jump if bit = 1 and clear bit, e.g.,
JBC P1.1, LABEL)
CPL
(complementbit, e.g., CPL P3.0)
INC
(increment,e.g., INC P2)
(decrement,e.g., DEC P2)
DEC
DJNZ
(decrernent and jump if not zero, e.g.,
DJNZ P3, LABEL)
MOV,PX.Y, C (movecarry bit to bit Y of Port X)
(clear bit Y of Port X)
CLR PX.Y
SETBPX.Y (set bit Y of Port X)
If an 8-bit address is being used (MOVX @Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughoutthe externafmemorycycle.This will facilitate paging.
In any case, the low byte of the address is time-mukiplexed with the data byte on Port O. The ADDR/
DATA signal drives both FETs in the Port O output
buffers.Thus, in this applicationthe Port Opins me not
open-drainoutputs, and do not require external pullups. Signal ALE (Address Latch Enable) shoufd be
usedto capture the addressbyte into an external latch.
The address byte is valid at the negativetransition of
ALE. Then, in a write cycle,the data byte to be written
appears on Port Ojustbrrm ~ is activated,and remains there until after WR is deactivated. In a read
cycle, the incomingbyte is accepted at Port Ojust before the read strobe is deactivated.
It is not obviousthat the fast three instructions in this
list are read-modify-writeinstructions, but they are.
Theyread the port byt%all 8bits, modifythe addressed
bit, then write the new byte back to the latch.
Duringany accessto externalmemory,the CPU writes
OFFHto the Port Olatch (the SpecialFunction Register), thus obliteratingwhateverinformationthe Port O
SFRmay havebeenholding.If the user writeato Port O
during an external memory fetch, the incomingcode
byte is corrupted. Therefore,do not write to Port O if
external program memoryis used.
The reason that read-modify-writeinstructions are directed to the latch rather than the pin is to avoid a
possiblemisinterpretation of the voltage level at the
pin. For example,a port bit mightbe used to drive the
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct vafue of 1.
ACCESSING
EXTERNAL
External Program Memoryis amessedunder two conditions:
1) Wheneversignal= is active; or
2) Whenever the program counter (PC) contains a
number that is larger than OFFFH(WFFH for the
8052).
MEMORY
This requiresthat the ROMleasversionshave~
wired
lowto enablethelower4K (8Kforthe 8032)program
Accessesto external memoryare of two types: accewes
bytes to be fetched from extemafmemory.
to external Program Memoryand amesaes to external
Data Memory. Accessesto external program Memory
use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use ~ or
~ (alternate functionsof P3.7and P3.6) to strobe the
memory.Refer to Figures36through38 in the Internal
Tintingsection.
When the CPU is executingout of external Program
Memory,all 8 bits of Port 2 are dedicatedto an output
fimctionand may not be used for generalpurposeI/O.
During external program fetches they output the high
byte of the PC. Duringthis time the Port 2 drivers use
the strong pullups to emit PC bits that are 1s.
Fetches from externrdProgram Memory always use a
16bit address. Accessesto external Data Memory can
use either a l~bit address (MOVX @DPTR) or an
8-bitaddress (MOVX @w).
TIMER/COUNTERS
The 8051has two 16-bitTimer/Counterregisters:Timer O and Timer 1. The 8052has these two plus one
3-9
int&
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
four operatingmod- which are selectedby bit-pairs
(M1. MO)in TMOD. Modes O, 1, and 2 are the same
for both Timer/Counters.Mode 3 is different.The four
operatingmodesare describeditsthe followingtext.
more:Timer 2. AUthree can be ccmflgurecito operate
either as timers or event counters.
In the “Timer” function, the register is incremented
everymachinecycle.Thw onecan think of it as countingmachinecycles.Sincea machinecycleconsistsof 12
oscillatorperiods,the count rate is 1/,, of the oscillator
frequency.
MODEO
EitherTimerin ModeO is an 8-bit Counter with a
divide-by-32preacaler. This 13-bit timer is MCS-48
compatible.Figure 7 showsthe Mode Ooperationas it
appliesto Timer 1.
In the “Counter” timction, the register is incremented
in responseto a l-to-Otransition at its corresponding
externrdinput pin, TO,T1 or (in the 8052)T2. In this
timction,the externalinputis sampledduring S5P2of
everymachine cycle.When the samplesshowa high in
onecycleand a lowin the nextcycle,the countis incremented. The new count value appeara in the register
duringS3P1of the cyclefollowingthe one in whichthe
transitionwas detected.Sinceit takes 2 machinecycles
(24 oscillator periods)to recognizea l-to-Otransition,
the maxiMuMcount rate is 2/24of the oaciliator frequency.There are no restrictions on the duty cycle of
the external input signaf, but to ensure that a given
level is sampled at least once before it changes, it
shouldbe held for at least one full machinecycle.
In this mode, the Timer regiater is configured as a
13-Bitregister.As the count rolls over fromail 1sto ail
0s, it sets the Timer interrupt flag TF1. The cmnted
input is enabledto the Timer whenTR1 = 1and either
GATE = Oor ~
= 1. (SettingGATE = 1 aflows
the Timer to be controlledby externafinput INT1, to
facilitate pulse width measurements.)TRl is a control
bit in the SpeciafFunction Register TCON (Figure 8).
GATE is in TMOD.
The 13-Bitregister consistsof ail 8 bits of THl and the
lower 5 bits of TL1. The upper 3 bits of TLl are ittdeterminate and shouIdbe ignored. Settingthe run flag
(’TR1)doesnot clear the registers.
In addition to the “Timer” or “Counter” selection,
Timer Oand Timer 1 have four operatingmodesfrom
whichto select. Timer 2, in the 8052,has three modes
of operation: “Capture,“ “Auto-Relrxid”and “baud
rate generator.”
ModeOoperationis the same for Timer Oas for Timer
1. SubstituteTRO,TFOand ~
for the corresponding Timer 1sigmdsin Figure 7. There are two dif%rent
GATE bia one for Timer 1 (TMOD.7) and one for
Timer O(TMOD.3).
TimerOand Timer 1
TheaeTimer/Counteraarepreaent in both the 8051and
the 8052.The “Timerr’or “Counter” functionis aelected by control bits Cfl in the SpeciaiFunctionRegister
TMOD (Figure 6). These two Timer/Countem have
MODE 1
Mode 1 is the same as Mode O,except that the Tima
registeris beingrun with all 16bits. (LSB)
(MSB)
GATE
C/T
I
Ml
I
MO
I
GATE
C/7
I
Ml
MO
A
Timer 1
whensaLTirnar/Countar
Gadng
conrrol
“x” is anablad
cmlywhilempin
is hiohand “TRx’”mntrol pinis
set When
cberedTimaf “x” is anabledwharfaver
“7Rx”
Timer O
Opamtfng Mode
S-bitlimar/@ntar’’THX”
with.<TIJ,, as ~it
WI
o
MO
0
o
1
IS-bil T!mar/Ccunter 4“THx’,and 4.TIX am
cascadad; there is no ~r.
1
0
S-bitauto-reloadTimSr/~ntar
“THx” holdsa
value whichis toba reloadad info“TLx” asch
time it OYWIIOWS.
1
1
(i_knwO)TLOisanS-bitTimer/Counter
mntrolled by the [email protected] Timar Ocontrolbti.
prese%r.
eontrolbitkeat.
Timaror CounterSalaetor daaradfor Timer opwstiOn
(inwtfromifttmelwetafn
ebek). sattorcountar
Won
(inputfrom “Tx” inputpin).
THO
isanB-bit
[email protected] bytimarI
Centml
Ms.
1
1
flimerl)
7imer/Ccunter 1 stcopad.
Figure 6. TMOD: Timer/Counter Mode Control Register
3-1o
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Osc
‘ ICOJTROL’(5%
’J:L’H
‘F’
k
[A
I
INTERRUPT
270252-9
Figure 7. Timer/Counter 1 Mode O:13-Bit Counter
(MSB]
[
symbol
TFl
(LSB)
TRl
TFo
IE1
TRO
-1
IEO
ITO
Posltlon
Neme mdslgnlffcenm
TF1
TCON.7
llner 1 overflowFlag. Set by
hardware on Tw/Counter
overflow.
Cleared byherdwerewtten procveetorsto intemuptroutine.
IE1
Tc%+J.3
Interrupt1 Edgs flsg. Sstbyhardwsre
when external intenupt~ge
deteeted. Cfesmdwhen interrupt
prmeesed.
TR1
TmN.6
l%ner 1 Run eontml biLSet/cleared
by sottwsreto tum Tkn6f/Counte?WI
off.
IT1
TCON.2
TFo
TCON.5
Timer Oovsrfiow Flag.Set by
herdwsreon Timef/Camter overflow.
Cleared byhsrdware whan pmmee.or
veetorsto intemuptmutine.
Intenupt 1 Type mntrd bk Set/
elearadbyaofttnr etoapecifyfsiiing
sdgdbw level biggwadesternel
interrupts.
IEO
TU)N.1
lntenuptOEdgsfleg. Set byhsrdwsre
when external intsfruptedge
detected. Cleared *
interrupt
~.
ITO
TCON.O
InterruptOTyPSmntrol biLSet/
cleared by sdtwereto speeifyfslling
[email protected] [email protected]
interrupt
TRO
POaltlon
TCON.4
[email protected]
IT1
Timer ORuncontml ML SatJcleared
byeoftwareto tum Timer/Counter on/
off,
Figure 8.TCON: Timer/Counter Control Register
Timer O in Mode 3 establieheaTLOand THOas two
separate counters.The logicfor Mode 3 on Timer Ois
MODE 2
Mode2 configures
theTimerregisterasan 8-bitCounter (’TLl)with automatic reload, as shownin Figure 9.
OverfiowfromTL1 not only sets TFl, but also reloads
TL1 with the contentsof THl, which is preset by aoftware. The reload leav~ THI unchanged.
Mode 2 operationis the same for Timer/Counter O.
MODE 3
Timer 1in Mode3 simplyholds its count.The effeetis
the ssrne as setting TRl = O.
sh_own
inFigure10.TLO&estheTimerOcontrolbits:
Cfi, GATE,TRO,INTO,and TFO.THOis lockedinto
a timer function (counting machine cycles)and takes
over the useof TR1 and TFl fromTimer 1.Thus THO
now controlsthe “Timer 1“ interrupt.
Mode 3 is providedfor applicationsrequiringan extra
8-bit timer or counter. With Timer o in Mode 3, gIL
8051ean looklike it has three Timer/Counte~ and an
8052, like it has four. When Timer O is in Mode 3.
Tim~ 1 een be tinned on and off by switchingit out of
and into its own Mode 3, or esn still be used by the
serial DOrtae s baud rate mnerstor, or in fact, in any
appli~tion not requiring& iaterru~t.
3-11
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
‘ROL~
[M
CIT. o
.,
PINJ*”
INTERRUPT
270252-10
Figure9. Timer/Counter1 Mode 2: 8-Bit Auto-Reload
EI--EI-’’”SC”SC
11121~’~
I
/t
1 ‘
.PIN~fi=l
—
INTERRUPT
CONTROL
Id’
1/12 1“’~
_
~
TR1
~
INTERRUPT
I CONTROL
270252-11
Figure 10. Timer/Counter OMode 3: Two 6-Bit Countere
Timer2
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052.Like Timers Oand 1, it can operate
either as a timer or as an eventcounter. Thisis selected
by bit Cm in the SpecialFunction Register T2C0N
(Figure 11).It haa three operating modes: “capture,”
“autdoad” and “baud rate generator,” which are se-
Table 2. Timer 2 Operating Modea
IRCLK + TCLKlCPI~lTR21
lectedbybitsin T2CONas shownin Table2.
3-12
Mode
o
0
1 16-bitAuto-Reload
o
1
1
1 16-bitCapture
x
1
Baud
Rate
Generator
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
(MSB)
(Lss)
TF2
EXF2
I
RCLK
TCLK
EXEN2
symbol
POaRion
Named
I
cm
TR2
cPlm
1
Signllkenw
TF2
T2CX3N.7
Timer 20vedlowflag ~bya Tiir2
ovarflowand mustbe cleeredbyaoffwara.
TF2will not be astwtsen [email protected] = 1 orTCLK = 1.
EXF2
T2CON.6
limer2exfemal flag eetwheneifhar a eapfura orraload iseaumd bya negative
t~SifiOn on T2EX and EXEN2 = 1. When Tirrwr2 interruptiaenablad, EXF2 = 1
will eauaafha CPU toveeforte tha T}mer2 intarruptrwtine. EXF2 must be
cfeared trysoftware.
RCLK
T2CON.5
Raeeivecloek ffsg.When eat, eausesthe aerfal porttouee Tirnw2 overflow
pulseaforits raceiva clookin Modaa 1 and 3. RCLK = Oeauaaa Timer 1 ovarlfow
to be @ ferfha raeeive Clock.
TCLK
T2CON.4
Transmitclock flag.Whenaat, eaueeethe aafisl port to uee Timw2 overflow
puleeafwitat ranemit deck in modes 1 and 3. TCLK = OcaueeaTmer 1
overflcws to ba uaad for fhefranamif deck.
EXEN2
T2CON.3
Tirnar2 external enebleffag. When set, allows aeapfure o+raleedtoooeures a
result ofa negativatranaifiemon T2EX ifllnar2 is not beinguaadto eiockthe
til
PM. EXEN2 = Ocausea Timar2 to ignoreevenfset T2EX.
TR2
T2mN.2
Start/atop cmItrolfor Timar2. A logic 1 afarta Usatimer.
CII’2
T2CZ)N.1
Timarorcountaraalect flimer2)
O = Internaltimar (OSC/12)
1 = ~1
event muntar (fallingedgetrfggered).
T2c0N.o
Captwe/RaloadflW. Wheneet ~tureawillr rccuronnagstivet renaifions et
T2EX if EXEN2 = I.When eiaarad, aufo.ralosdswill occuraifherwithTimer2
overflowsor nSgatiVetranaifiorreatT2EX wlwn EXEN2 = 1. When eifher RCLK
= 1 or TCLK = 1, this bfiis ignciad and the timer is foreed foeute-rafoedem
Timar20verflew.
cP/m
-.
. . ———-..
—.
.-
Figure 11. TZCON: Timer/Counter 2 Control
In the Capture Mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = O,
then Timer 2 is a Id-bit timer or counter which upon
overtlowingeeta bit TF2, the Timer 2 overflowbit,
which can be used to generatean interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the
added feature that a l-to-Otransition at external input
T2EX causesthe current valuein the Timer 2 registers,
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively.(RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In
addition, the transition at T2EX causes bit EXF2 in
T2CONto be set, and EXF2,like TF2, an generateen
interrupt.
The Capture Modeis illustrated in Figure 12.
In the auto-reloadmcdethereare againtwo options,
which are selected by bit EXEN2 in T2CON. If
EXEN2 = O,then whenTimer 2 rolla over it not only
sets TF2 but also causes the Timer 2 registers to be
reloaded with the l~bit va2uein registera RCAP2L
and RCAP2H,whichare presetby software.If EXEN2
= 1, then Timer 2 still does the above, but with the
Register
added feature that a l-to-o transition at external irmfrt
T2EX will alaotrigger the id-bit reload and set E&2.
The auto-reloadmede is ilfuetratedin Figure 13.
The baud rate generatormodeis selectedby RCLK =
bedescribedin ecmjunc1 and/or TCLK = 1. Itwill
tion with the aerial port.
SERIAL INTERFACE
The seriaf port is full duplex,meaningit can transmit
and receive eimultarseously.It is aleo receivebutTered,
meaning it can commencereception of a second byte
before a previouslyreceivedbyte has beersresd from
the reeeive register. (However,if the tirat byte still
hasn’tbeenreadby the timereceptionof the second
byte is completq one of the bytes wilf be lost). The
serial port receive end transmit registers are both acceeaedat SpeeialFunctionRegister SBUF.Writing to
SBUF loada the transmit register, and reading SBUF
aeceeeeaa physieaflyseparatereceiveregister.
3-13
irrtd.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Sxlins
270252-12
Figure
12. Timer 2 in CaptureMode
The serial port can operatein 4 modes:
MultiprocessorCommunications
Mode O: Serial date enters end exits through RXD.
TXD outputs the shift clock.8 bits are tranamittext/received:8 date bits (LSBftrat).The baud rate is tixed at
1/12 the oscillator frequency.
Modes 2 end 3 have a special provisionfor muMproceasorcommunications.In these mod- 9 data bita are
received.The 9th one goea into RB8. Then comes a
stop bit. The port can be programmedsuch that when
the stop bit is received,the aerialPrt interrupt will be
activated only if RB8 = 1. This feature is enabled by
setting bit
SM2in SCON. A wayto use this fmture in
multiprocessorsystems is 22folfows.
- Mode 1: 10bits are transmitted (through TXD) or received(through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (l). On receive+the stop bit goes
into RB8 in Special Function Register SCON. The
baud rate is variable.
Mode 2: 11bits are transmitted (through TXD) or received(through RXD): a start bit (0), 8 data bits (LSB
fret), a programmeble 9th data bit, and a stop bit (l).
On Transmit, the 9th data bit (TB8 in SCON)can be
eaaignedthe valueof Oor 1.Or, for example,the parity
bit (P, in the PSW) coufdbe moved into TB8. On receive,the 9th data bit goesinto RB8 in SpecialFuncton
RegisterSCON,whilethe stop bit is ignored.The baud
rate is programmableto either ‘/”2or ‘\e4the oscillator
frequency.
Mode 3: 11bits are transmitted (through TXD) or received(through IUD): a start bit (0), 8 data bits (LSB
first), a programmable9th data bit and a stop bit (l). In
fac~ Mode 3 is thesameesMode 2 in all reapeeta
except the baud rate. The baud rate in Mode 3 is veriable.
In all four modes, transmissionis initiated by any instruction that uses SBUFes a destinationregister.Reception is initiated in ModeOby the conditionRI = O
and REN = 1. Reception is initiated in the other
modesby the incomingstart bit if RBN = 1.
3-14
Whenthe master proceaaor wantsto trananu“ta blockof
data to one of several slaves, it firat sends out an address byte which identifiesthe target slave.An address
byte differsfroma data byte in that the 9tb bit is 1in en
eddress byte and Oin a data byte.With SM2 = 1, no
slave will be interrupted by a date byte. An eddreas
byte, however, will interrupt elf slav= so that each
alevecan exsmine the receivedbyteend seeifit is being
eddreaaed.The addressed slave will clear ita SM2 bit
end prepare to remive the data bytesthat will be coming. The slaves that
weren’tbeingaddressedleave their
SM2Sset and go on about their business,ignoringthe
comingdata bytes.
SM2 has no effect in Mode O,and in Mode 1 can be
used to check the validityof the stop bit. In a Mode 1
reception,ifSM2 = 1, [email protected] interruptwillnotbe
activated unlessa vatid atop bit is received.
SerialPortControlRegister
The serialport control end status registeris the Speciaf
Function Register SCON, shown in Figure 14. This
register mntains not only the mode selectionbits, but
also the 9th data bit for transmit and receive(TB8and
RB8), and the aerial port interrupt bits (TTand RI).
intd.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
l++
+12
TR2
nEmAO
-R
2
llslEmnlWr
Max PfN
axaNa
270252-13
Figure 13. Timer 2 in Auto-Reload Mode
(MSB)
SMO
(LSB)
SM1
REN I TB8 I RSS ] n
SM2
Where SMO, SM1 epeeify the aefial pommode, as follows:
SMO
o
o
1
1
1
s SM2
●
aMl
0
1
o
REN
mode
0
1
2
3
●
TSS
Scud Rate
f=flz
vadable
f-/s4
or
f=,/32
9-btuARTvenable
ie the Sthdate bifthetwill be
RSS
in Modes 2and 3, iatha Sthdata bit
thatwes received. In Mode 1, ifSM2
= O,RSS iethe atopbitthet wea
received. In MOdeO,RS3 is rrotuaed.
●
TI
iewenemif irstarruptflag.Set by
hardsrareatthe end ofttw8th bittime
in M*O,
oratthe beginningof the
*P bit in the offwrrnodes,in any
aerieffmnamieaion.Muetbecleared
byaoftware.
●
RI
is receive irsferruptflag.Sat by
herdware atthe end of thesth bit time
in Mode O,or helfweythrcrughthe atop
b4ttirrwin the other modes,inany
serial recefdkm (exoepta8a SM2).
Muaf be Cia
byeoftwere.
●
enebleethe muftipromaeor
communieatfonfeature in Modes 2
and 3.InM*20r3,
if SM2isaetto
1 than RI willnotbaactf.mtad if the
received 3th date bit(R*) iaO. In
Mode 1, if SM2 = 1 then RI willnot
baatited
ifavalid stop bhwea not
recefvad. In Mode O,SM2 ahouldbe
o.
enableeaeriel reqstion. %by
eoftwareto enable raoaption.Clear
byeoftwaretodieeble raee+stkm
. -----
RI
bansin Modaa2 end3. % or
dear byaoftwareaa rtaairad.
Deeerfpnorl
Shiftragiatar
S-bifUART
9-bit UART
—.
I
-
. . —
—
—
Figure 14. SCON: Serial Port Control Register
2SMOD
Mode 2 BaudRate= ~X(Oscillator
The baud rate in Mode Ois tlxed:
ModeOBaud Rate =
Frequency)
OscillatorFrequency
12
The baud rate in Mode 2 dependeon the value of bit
SMODin SpecialFunction RegisterPCON. If SMOD
= O(whichis the valueon reset),the baud rate % the
oaeillatorfrequency.If SMOD = 1, the baud rate ie
%2 the oscillatorfrequency.
In the 8051.the baud ratea in Modes1and 3 are determinedby the Timer 1 overflowrate. In the 8052,these
baud ratea earsbe determinedby Timer 1, or by Timer
2, or by both (one for transmit end the other for reeeive).
3-15
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
UsingTimer 1 to Generate Baud Rates
mode (high nibbleof TMOD = OO1OB),
In that ease,
the baud rate is givenby the formula
When Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflowrate and the valueof SMOD as follows:
Modes 1, 3 2SMOD~ OscillatorFrequency
BaudRate = —
32
L% [256- (THI)I
ModesL 3 2SMOD
BaudRate = —
32
X (Timer 1OverflowRate)
The Timer 1 interrupt shouldbe disabledin this application. The Timer itself can be configuredfor either
“timer” or “cormter” operation, and in any of its 3
running modes. In the most typioaiaprdication~ it is
contl~ed for “timer” operati6n, in ‘the auto-reload
I
I
Saud Rate
Mode OMax:1 MHZ
Mode2 Msx:375K
Modes 1,3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
with
Timer 1 by
One ean achievevery low baud rates
leavingthe Timer 1 interrupt enabl~ and mntlguring
the Timer to run as a 16-bit timer (hish nibble of
TMOD = OOOIB),
and using the TiM~ I_interruptto
do a lti-bit softwarereload.
Figure 15lists variouseommordyused baud rates and
how they can be obtsined from Timer 1.
1
Timer
f~c
SMOD
12 MHZ
12 MHZ
12 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6 MHZ
12 MHZ
x
1
1
1
o
o
o
o
o
o
o
Cfl
Reload
Value
x
x
FFH
FDH
FDH
FAH
F4H
E8H
lDH
72H
FEEBH
Mode
T
x
x
x
o
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
Figure 15.Timer 1 Ganerated Commonly Ueed Baud Rates
Using Timer 2 to Generate SaudRates
In the 8052,Timer 2 is selectedas the baud rate generator by setting TCLK rind/or RCLKin T2CON (Figure
piol?:lxcmm
ls-
11).Note then the baud rates for transmit and reoeive
can be simultaneouslydifferent.SettingRCLK and/or
TCLK puts Timer 2 into its baud rate generatormode,
as shownin Figure 16.
r+l
Svam’rlz
+2
2!3?’
k.
““-=’
“ ---amo
i
.,”
Inm
.W,
Mm
--
.1,,
r=
---
-—
L.z.———
Figure 16. Timer 2 in Saud RateGeneratorMode
3-16
.,’
mx-
+,’
‘1’ XCLOCK
“o------
270252-14
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
The baud rate generatormode is similar to the auto-reloadmcde, in that a rolloverin TH2 causesthe Timer 2
registerstObe reloadedwith the Id-bit vahsein registers
RCAP2Hand RCAP2L,which are preset by software.
Now, the baud rates in Modes 1 and 3 are determined
by Timer 2’soverflowrate as follows:
Modes 1,3 BaudRate =
Timer 2 @clfiow
16
SEND enables the output of the shift register to the
alternate output functionline of P3.0, and sdsoenables
SHIFf CLOCKto the alternate output functionline of
P3.1. SHIPT CLOCK is low during S3, S4, and S5 of
everymachinecycle,and high during S6,S1and S2.At
S6P2of everymachinecycle in which SEND is active,
the contents of the transmit shift register are shiftedto
the right one position.
Rate
The Tim= can be configured for either “timer” or
“counter” operation.In the most typicalapplications,it
is configuredfor “timer” operation(C/T2 = O).“Timer” operationis a fittle different for Timer 2 when it’s
being used as a baud rate generator. Normally, as a
timer it wouldincrement every machine cycle(thus at
Y,, the mdlator frequency).
Asa baud rate generator,
however,it incrementsevery state time (thus at ~, the
oscillatorfrequency).In that case the baud rate is given
by the formula
Mcdes 1,3
‘aud ‘te
As data bits shift out to the right, zeroescomein from
the left. Whenthe MSBof the data byte is at the output
positionof the shift register, then the 1that was initialIy loaded into the 9th position,is just to the left of the
MSB,and all positionsto the left of that containzeroes
This condition flags the TX Control block to do one
last shitl and then deactivateSEND and set TL Bothof
these actions occur at SIP1 of the loth machinecycle
after “write to SBUF.”
OscillatorFrequency
= 32x [65536– (RCAP2H,RCAP2L)1
where (RCAP2H, RCAF2L) is the content of
RCAP2Hand RCAP2Ltaken as a Id-bit unsignedinteger.
Timer 2 as a baud rate generatoris shownin Figure 16.
This Figure is valid only if RCLK + TCLK = 1 in
T2CON.Note that a rolloverin TH2 doesnot set TP2,
and willnot generatean interrupt. Therefore,the Timer
2 interrupt doesnot have to be disabledwhenTimer 2
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a l-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L)to (TH2,TL2). Thus whenTimer 2 is in use
as a baud rate generator,T2EX can be usedas an extra
external interrupt, if desired.
It shouldbe noted that when Timer 2 is running(TR2
= 1) in “timer” function in the baud rate generator
mod~ one shouldnot try to read or write TH2or TL2.
Under these conditionsthe Timer is beingincremented
everystate time, and the results of a read or write may
not be accurate.The RCAP rcgistm may be read, but
shouldn’tbe written to, becausea write mightoverlapa
reload and cause write and/or reload errors. Turn the
Timer off (clear TR2) before ruessing the Timer 2 or
RCAP registers,in this case.
MoreAboutModeO
Serial
dataenters and exits through RXD. TXD outputs the shifl clock. 8 bits are tranarnitted/received:8
data bits (LSBfwst).The baud rate is fixedat !/,2 the
oscillatorfrequency.
Trsnamissionis initiated by any instruction that uses
SBUF as a destinationregister. The “write to SBUF’
signalat S6P2also loadsa 1into the 9th positionof the
transmit shift registerand tells the TX Controlblockto
commencea transmission.The internal timing is such
that one till machine cycle will elapse between“write
to SBUF,” and activationof SEND.
Receptionis initiated by the condition REN = 1 and
R1 = O.At S6P2of the next machine cyclq the RX
Control unit writes the bits 11111110to the receive
shift register,and in the next clock phaseactivatesRECEIVE.
RECEIVE enables SHIFT CLOCK to the alterstate
output function line of P3.1. SHIIW CLOCK makes
transitions
at S3P1and S6P1 of every machine cycle.
At S6P2of everymachinecycle in which RECEIVEis
active,the contentsof the receiveshift registerare shifted to the left one position. The value that comes in
from the right is the vrduethat was sampledat the P3.O
pin at S5P2of the same machine cycle.
As &ta bits comein from the righL 1sshift out to the
left. When the Othat was initiallyloadedinto the rightmost positionarrivesat the leftmostpositionin the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SIP1 of the Klth machine
cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.
MoreAboutMode 1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSBtirst),
and a stop bit (l). on receive, the stop bit gces into
RBg in SCON.In the 8051the baud rate is determined
by the Timer 1 overflowrate. In the 8052it is determinedeither by the Timer 1overtlowratej or the Timer
2 overtlowrate or both (one for transmit and the other
for receive).
Figure 18showsa simplitlsdfunctionaldiagramof the
serial port in Mode 1, and associatedtimingsfor trsnsmit receive.
Figure 17showsa simplifiedfunctioneddiagramof the
serial port in ModeO,and associatedtiming.
3-17
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Sosl
MTERNALws
WRITE
TO
SBUF
RXD
PS.OALT
OUTPUT
FUNCTION
SHIFT
Tx CONTROL
26
SERIAL
PORT
INTERRUPT
l-m
P3.1 ALT
OUTPUT
FUNCTION
REN
R
RX(I
P!?OALT
INPUT
FUNCTION
. . ...
~T”
u
I
1
SeuF
REAO
SBUF
nwRrTEToseuF
SEND SNIFT
n
II
1
01
n WRITE T08CON(CUAR
Ill)
MD {DATAOUTI \
W
x
n
lx?
,
n
w
1
n
M
x
n
m
I
n
06
1
n
07
\
TRANSMIT
Tli6i6\
n
I
am
RECEIVE
SNm
I
I
RXD(DATAIN)
n
M
L
n
“m
n
.Ds
I-I
.0s
n
“m
n
.0s
RECEIVE
n
.06
n
D?
mmwmaocm
270252-15
Figure 17. 8erial Port Mode O
3-18
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
20s1INTERNALBUS
TIMER2
OVERFLOW
TIMER 1
OVERFLOW
TSS
!?
WRITS
TO —
SBUF
+2
SMOD
=1
SMOD
=0
TXD
RCLK----
IFFH
RXD
LOAD
SBUF
SSUF
READ
SSUF
*
lx
@oclq
I
I
IWWTSTOSSUF
sEND
OATA SIPF r
sNln
1
I 00 z m
~L
STARTSIT
1!
I
I
I
1
1 m
0
r 03
I
1 0s
rRANsMrT
1 D5 r 0s
1 n7 1
STOPBtl
+1’1
-lsnEsm
.S
RXO
RECEIVE
MT”
STOPOIT
● TM=-—=
Blwf
RI
l-++++++:
270262-16
Figure 18. Serial Port Mode 1. TCLK, RCLK and TTmer2 are Preaent in the 8052/8032 Only.
Trammission is initiated by any instruction that oses
SBUF as a destinationregister. The “write to SBUF”
sid * IOSdSa 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmissionis requested.Tmnsmission aotually
commencesat SIP1 of the machinecycle followingthe
next rolloverin the divide-by-16counter. (Thus,the bit
timesare synchronisedto the divide-by-16counter, not
to the “write to SBUF” signal).
The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, whichenablesthe output bit of the
transmit shift register to TXD. The first shift pulse cccurs one bit time after that.
3-19
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
As data bita shift out to the right, zeroesare clockedin
from the left. When the MSBof the data byte is at the
output positionof the shift register,then the 1 that was
initiallyloadedinto the 9th positionisjust to the left of
the MSB, and all positionsto the left of that contain
zeroes. This conditiontlags the TX Control unit to do
one last shift and then deactivate SEND and set TI.
This occurs at the loth divide-by-16rollover after
“write to SBUF.”
mit, the 9th data bit (TB8)can be assignedthe value of
Oor 1. On receivejthe 9th data bit goes into RB8 in
SCON.The baud rate is programmableto either Y&or
%.
the oscillatorfrequency
in Mcde2. Mode3 may
havea variablebaud rate generatedfromeither Timer 1
or 2 dependingon the state of TCLK and RCLK.
Receptionis initiated by a detected l-to-Otransition at
RXD. For this purposeRXD is sampledat a rate of 16
times whateverbaud rate has been established.When a
transitionis detected,the divide-by-16counter is immediately reaet, and IFFH is written into the input shift
register. Reaetting the divide-by-16counter aligns its
rolloverswith the boundariesof the incomingbit titnea.
The 16 states of the counter divide each bit time into
16ths.At the 7th, 8th, and 9th counterstates of each bit
time, the bit detector sampleathe value of RXD. The
value acceptedis the valuethat was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not O, the
receivecircuits are reset and the unit goeaback to looking for another l-to-Otransition. This is to providerejection of false start bita. If the start bit proves valid, it
is shifted into the input shift register, and reception of
the rest of the thrne will proceed.
As data bits come in from the right, 1s shift out to the
left. When the start bit arrives at the leftmost position
in the shift register, (which in mode 1 is a 9-bit register), it figs the RX Controlblock to do one last shift,
load SBUF and RB8, and set RL The signal to led
SBUFand RB8, and to set RI, will be generatedif, and
onlyif, the followingconditionsare met at the time the
final shifl pulse is generat.d
1) RI
and
2) EitherSM2 = O,orthereceivedstopbit = 1
= O,
If either of these two conditionsis not met, the received
frame is irretrievably lost. If both conditionsare met,
the stop bit goes into RB8, the 8 data bits go into
SBUF, and RI is activated. At this time, whether the
aboveconditionsare met or not, the unit goes bsek to
lookingfor a l-to-Otransition in RXD.
MoreAbout Modes2 and 3
Elevenbita are transmitted (throughTXD), or received
(throughRXD): a start bit (0),8 data bits (LSBfit), a
programmable9th data bit, and a stop bit (l). On trans-
Figurca 19 and 20 show a fictional diagram of the
serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion
differsfrom Mode 1 only in the 9th bit of the transmit
shift register.
Transmissionis initiated by any instruction that uses
SBUF as a destinationregister. The “write to SBUF”
signal also bads TB8 into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmiasion is requested. Transmissioncommencesat SIP1 of the machinecyclefollowingthe next
rollover in the divide-by-16counter. (Thus, the bit
timesare synchronizedto the divide-by-16counter,not
to the “write to SBUF”signal.)
The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated,whichenablesthe outputbit of the
transmit shift registerto TXD. The first shitl pulse occurs one bit time after that. The first shift clocks a 1
(the stop bit) into the 9th bit positionof the W register. Thereafter, ordy seroes are clocked in. Thus, as
data bits shift out to the right, zeroes are clocked in
fromthe left. WhenTB8is at the output positionof the
shitl register, then the stop bit isjust to the left of TB8,
and all positionsto the left of that containzeroes.This
conditionflagsthe TX Controlunit to do one last shift
and then deactivate SEND and set TL This occurs at
the llth divide-by-16rolloverafter “write to SBUF.”
Receptionis initiated by a detected 1-W3transition at
RXD. For this purposeRXD is sampledat a rate of 16
timeswhateverbaud rate has been established.When a
transitionis detect~ the divide-by-16counteris immediately reaet, and lFFH is written to the input shift
register.
At the 7th, 8tb and 9th counter ststes of each bit time
the bit detector samplesthe vrdueof RXD. The value
acceptedis the valuethat was seen in at least 2 of the 3
samplea.If the value acceptedduring the first bit time
is notO,the receivecircuitsareresetandtheunitgoes
back to looking for another l-to-O transition. If the
start bit provea valid, it is shifted into the input shift
register,and receptionof the rest of the frame will proeecd.
3-20
i~.
HARDWARE DESCRIPTlON OF THE 8051,8052 AND 80C51
S0S1INTERNAL BUS
TSS
WRITE
S~tF
TXD
PHASE 2 CLOCK
(% fosc)
STOP 91T
GEN,
‘H’mDATA
TX CONTROL
Sm
TX CLOCK
TI
START
MOOE 2
LOAO +
IFFH
RxD
LOAD
SBUF
~LOC~
1
I WRITE TO SBUF
OATA
sNIPr
n
t
n
n
n
n
n
a
n
11
R
1
n
n
n
I
n
I
o
TRANSMIT
n
TI
STOPRl~
lSRESET
ICLOCK 1
1
Rxo
B17DETEcToR15’m’~/
SAMPLE TIMES
m
RECEIVE
SHIT
1
I
r
m
!4!4
n
n
I
D1
m
n
8
1
02
W
n
n
I
D3
Im
n
1
I
M
m
n
n
r
06
Es
n
o
I
m
u
n
n
1
07
m
n
m
1 ma
M
n
1
k.4.pP
270252-17
Figure 19. Serial Port Mode 2
3-21
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
TIME
OVEI
TIMER 1
OVERFLOW
S051INTSRNALBUS
II
.Ow
Qr-
WRITE
TO —
SSUF
:2
SMOD
=1
SMOD
:0
rw
,“..%
TCLK -
TSB
,...
1
/
--
,.,..
“o”’
RCLK ----
r
—--7--A
+1$L
I+%’E
;“’”l
I
RX CLOCK RI
LOAD+
-lE&ElI
I
IFFH
!’
,
v
RXD
LOAD
SBUF
*
READ
SBUF
*
Tx
&LOCl$
n
I WRITE TO S8UF
‘1
DATA
SHIFT
TRANSMIT
STOP SIT
-r,
Figure20.5enalPortMode3. TCLK,RCLK,andTimer2 arePresentinthe6052/8032Only.
3-22
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
was transition-activated.If the interrupt was [email protected] then the externalrequestingsource is what controls the requestflag,rather than the on-chiphardware.
As data bits come in from the right, 1sshift out to the
left. Whenthe start bit arrives at the leftmost position
in the shift register (whichin Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last
shit%load SBUF and RIM, and set RI. The signal to
load SBUFand RB8, and to set RI, willbe generatedif,
and onlyif, the followingconditionsare met at the time
the final shift pulse is generated:
The Timer Oand Timer 1 Interrupts are generatedby
TFOand TFl, which are set by a rollover in their respectiveTimer/Counterregkters (exceptseeTimerOin
Mode 3). Whena tinter interrupt is generated,the flag
that generated it is cleared by the on-chip hardware
when the serviceroutine is vectoredto.
1)RI= O,artd
2) EitherSM2= Oor the received9thdata bit = I
The SerialPort Interrupt is generatedby the logicalOR
of RI and TI. Neither of these flags is cleared by hardware when the cervix routine ia vectored to. In fact,
the service routine will normally have to determine
whether it was RI or TI that generated the interrupt,
and the bit will have to be cleared in software.
If either of these conditions is not met, the received
three is irretrievably lost, and RI is not set. If both
conditionsare met, the received9th data bit goes into
RB8, and the tiret 8 &ta bits go into SBUF. One bit
time later, whether the aboveconditionswere met or
not, the unit goesback to lookingfor a l-tQ-Otransition
at the RXD input.
In the 8052,the Timer 2 Interrupt is generatedby the
logicalOR of TF2 and EXF2. Neither of these flags is
cleared by hardware when the service routine is vectored to. In fact, the serviceroutine may have to determine whether it wee TF2 or EXF2 that generatedthe
interrupL and the bit will have to be cleared in software.
Note that the value of the receivedstop bit is irrelevant
to SBUF,RB8, or RI.
INTERRUPTS
8051 provides 5 interrupt sources. The 8052provides6. These are shown in Figure 21.
The
The External Interrupts ~
and INT1 carseach be
either level-activatedor transition-activate&depending
on bita ~ and ITl in RegisterTCON. The tlags that
actuallygenerate these interrupts are bits IEQand IE1
in TCON.Whetsen externalinterrupt is generated,the
tlag that generated it is cleared by the hardware when
the serviceroutine is vectoredto only if the interrupt
All of the bite that generate interrupt can be set
or
cleared by software,with the same result as though it
had beenset or clearedby hardware.That is, interrupts
can be generatedor pendinginterrupts can be canceled
insoftware.
D
m
I
P
— I E72 I ES I ~1
I EXl I ETO ] EXO
Enable S4 = 1 enaMss the infwrupt
Ensble Sit = O dieebles it
EA
[email protected]+=
m
m]
symbol
.J?--#GJ,
(LSB)
(MSS)
Position
IE.7
Function
&eek4es sII interrupts.If EA = 0, no
intemuptwillbeeeknowledged. If EA
= I,eeehinterrupt solneeie
indbiduskyenebled wdissbled by
settingorclearing meaaeble bit.
IE.6
resewed.
ET2
IE.5
litnw2 intenupf enable bit
ES
IE.4
Serial P&t infamuptenebletit.
El-l
IE.3
ITmer 1 imenupl ensbfe bit.
Exl
IE2
Extarrsalinterrupt1 ertablebt
ETo
IE.t
Timw Oikttanuptenablsbit.
Exo
IE.O
ExterrKaintenuptO eneblebit
Usersotiwaraslwuld navarwrits Istourtimplamwfad
~MSYbausad
infutureMCS-51 @ueta
bits,since
Figure22.IE:InterruptEnableRsgister
exn
(mssOMLo
-J
270252-19
Figurs 21. [email protected] Sources
3-23
infd.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Each of these interrupt sourcescan be itldividdy enabled or disabledby settingor clearing a bit in Special
Function Register IE (Figure 22). IE contains also a
global disablebit, EA, which disables all interrupts at
once.
ceivedsimultaneously,an internal pollingsequencedetermines which request is serviced. Thus within each
priority levelthere is a second priority structure determined by the pollingsequence,as follows:
Source
1.
2.
3.
4.
5.
6.
Note in Figure 22 that bit position IE.6 is unimplemented. In the 8051s bit positionIE.5 is also tmimplemented. User softwareshouldnot write 1s to these bit
positions, since they may be used in future MCS-51
products.
PriorityLevelStructure
Eachinterrupt source can also be individually pro-
—
Priority Within Level
(highest)
(lowest)
Note that the “prioritywithin level” structureis only
usedto resolvem“muitaneousrequests of thesomeprionty level.
grammed to one of two priority levels by setting or
clearing a bit in SpecialFunction Register 1P (Figure
23). A low-priorityinterrupt can itself be interrupted
by a high-priorityinterrup~but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by ~y other-int&rupt-aource. (MSB)
IEO
TFO
IE1
TF1
RI +Tl
TF2 + EXF2
The 1P register contains a numbes of unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s,and in the
8051sthese and IP.5 are vacant. User softwareshould
not write 1s to these bit positions,since they may be
used in future MCS-51products.
(LSB)
—
PT2
PS
PTl
Pxl
How InterruptsAre HandIed
PTo Pxo
Figure 23. 1P:Interrupt Priority Register
interrupt flags are sampled at S5P2 of every machine cycle. The samplesare polled during the following machine cycle.The 8052’sTimer 2 interrupt cycle
is ditkrent as describedin the ResponseTime Section.
Hone of the ilagswasin a set conditionat S5P2of the
P~ “ g cycle the polling cycle will find it and the
interrupt systemwillgeneratean L-CALLto the appropriate serviceroutine,providedthis hardwere-generated LCALL is not blockedby any of the followingconditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling)cycle is not the final cycle in
the executionof the instruction in progress.
3. The instructionin progressis RETI or any write to
the IE or 1Pregisters.
If two requests of dikent
priority levelsare received
simultaneously,the request of higher priority level is
serviced. If requests of the same priority level are re-
Any of these three conditionswill blockthe generation
of the LCALL to the interrupt serviceroutine. tXmdition 2 cn3urcethat the instruction in progress wilt be
Riwity bit = 1 assigns high priortty.
Priorftybit = Osssigns low priority.
Symbol
—
Poeitforl
IP.7
The
Funefion
reserved
IP.6
resewed
PT2
IP.5
Tmer2 intemuptprie+ftybit.
Ps
IP.4
Swisl Port intenupt prioritybl
PTl
IP.3
Timer 1 intenupt primityMt.
Pxl
IP.2
Externalintenupt 1 pttofitybit
MO
IP.1
lim6r0 interruptpttoiitybit.
Pxo
IP.O
Extemsl intenupt Oprioritybit
User soffwareshould neverwite 1$ to unimplementedbits,since
theYmbe
used ifIfufurs [email protected] P+oducts.
ISEP21
m
%
INTERRUPT INTERRUPT
GOES
LATCHEO
ACTWE
I
‘:
A
A
INTERRU~
AREPOLLSO
LONGCALLTO
IM’ERRUPT
VECTORAOOQESS
. . .. .
INIERRUPTHOUllNE
270252-20
Ttisisthefeetestpossible reeponee vhn C2isthefinel cydeofaninettuctien ottwrthert RETI oranaeaesto
Ftgure24. Interrupt ResponseTimingDisgrem
3-24
IEorlP.
intdo
HARDWARE DESCRIPllON OF THE 8051,8052 AND 80C51
completedbeforevectoringto any serviceroutine.Condition 3 ensures that if the instruction in progress is
RETI or any accessto IE or 1P, then at least one more
instruction wiffbe executedbefore any interrupt is vectored to.
The polfing cycleis repeated with each machinecycl~
and the valuespolledare the valuesthat werepresentat
S5P2 of the previousmachine cycle. Note then that if
an interrupt flagis activebut not beingrespondedto for
one of the aboveconditions,and is not still active when
the blockingconditionis removed,the deniedinterrupt
will not be serviced.In other wor& the fact that the
interrupt tlag was once active but not servicedis not
remembemd.Everypoflingcycle is new.
The pofling cycle/LCALL sequence is illustrated in
Figure 24.
Note that if an interrupt of higher priority Ievefgoes
active prior to S5P2of the machine cyclelabeledC3 in
Figure 24, then in accordance with the aboverules it
@ be Vectored to during C5 and cd, without Stlyinstruction of the lowerpriority routine havingbeenexecuted.
Thus the procesaor acknowledgesan interrupt request
by executinga hardware-generatedLCALL to the ap
propriate servicingroutine. In some casesit also clears
the flag that generatedthe interrupt, and in other cases
it doesn’t. It never clears the Serial Port or Timer 2
flags. This has to be done in the user’s software. It
clears an external interrupt flag (IEOor IEl) only if it
was transition-activated. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it
does not save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectoredto, as ahownbelow.
IEO
TFO
IE1
TF1
Vector
Address
OO03H
OOOBH
O013H
OOIBH
RI + TI
O023H
8ource
TF2 + EXF2
O02BH
Executionproceedsfromthat locationuntilthe RETI
instructionis encountered.The RETI instructioninformsthe processo
r that this interruptroutineis no
longerin progr~ then popsthe top twobyteafromthe
stack and reloads the program Counter. Executionof
the interrupted program continues from where it left
off.
Note that a simple RET instruction would also have
returned executionto the interrupted progmrn,but it
would have left the interrupt control system thinking
an interrupt was stiIl in progress.
3-25
ExternalInterrupts
The externalsourcescan be programmedto be level-activated or transition-activatedby setting or clearing bit
ITI or ITOin Register TCON. If ITx = O, extemaf
interrupt x is triggered by a detectedlow at the INTx
pin. If ITx = 1, external interrupt x is edge-tiered.
In this mode if successive samples of the INTx pin
show a high in one cycle and a low in the next CYCIG
interrupt requeatflag IEx in TCONis set. Flag bit IEx
then requeststhe interrupt.
Sincethe extemaf interrupt pinsare sampledonce each
machinecycle, an input high or lowshould hold for at
least 12 oscillator periods to ensure sampfing. If the
external interrupt is transition-activated,the external
sourcehas to hold the requeatpin high for at least one
machine cycle, and then hold it low for at least one
machine cycle to ensure that the transition is seen so
that interrupt request flag IEx will be set. IEx will be
automatically cleared by the CPU when the service
routine is called.
If the external interrupt is level-activated,the external
sourcehas to hold the requestactiveuntil the requested
interrupt is actually generated.Then it has to deactivate the request before the interrupt service routine is
complet~ or else another interrupt will be generated.
ResponseTime
The ~
and INT1 levels are inverted and latched
into the interrupt tlags IEOand IEl at S5P2 of every
machine Cycle.Similarly,the Timer 2 flag EXF2 and
the Serial Port flags RI and TI are set at S5P2. The
valuesare not actually polledby the circuitry until the
next machinecycle.
The TimerOand Timer 1flags,TFOand TFl, are set at
S5P2 of the cycle in which the timers overflow.The
vafuesare then polledby the circuitryin the next cycle.
However,the Timer 2 flag TF2 is set at S2P2 and is
polledin the same cycle in whichthe timer overtlows.
If a requeatis active and conditionsare right for it to be
acknowledged,a hardware subroutinecd to the requestedserviceroutine wittbe the nextinstructionto be
executed.The call itself takes two cycles.Thus, a minimum ofthreecompletemachinecycleselapsebetween
activation of an external interrupt request and the beginningof executionof the first instructionof the aerviceroutine.Figure 24showsinterruptresponsetimings.
A longer response time woufdresult if the request is
blockedby one of the 3 previouslyfisted conditions.If
an interrupt of equal or higherpriority level is already
in progress,the additionalwait time obviouslydepends
on the nature of the other interrupt’sserviceroutine. If
the instruction in progressis not in its final cycl~ the
additionalwait time cannotbe morethan 3 cycles,since
the longest instructions (MUL and DIV) are only 4
intel.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
cycles long, and if the instructionin progress is RET2
or an accessto IE or 1P, the additionalwait time cannot be more than 5 cycles (a maximumof one more
cycle to complete the instruction in progress, plus 4
cyclesto completethe next instructionif the instruction
is MUL or DIV).
RESET
The reset input is the RST pin, whichis the input to a
SchmittTrigger.
A reset is accomplishedby holdingthe RST pin high
for at least two machine cycles(24 oscillator periods),
while the asciIlator h rwnning. The CPU responds by
generatingan internal [email protected] with the timing shown in
Figure 25.
Thus, in a single-interruptsystenLthe responsetime is
rdwaysmore than 3 cyclesand less than 9 cycles.
SINGLE-STEPOPERATION
The 8051interrupt structure allowssingle-stepexecution with very little software overhead.As previously
noted, an interrupt request will not be responded to
whilean interrupt of equal prioritylevelis still in progress, nor will it be respondedto after RETI until at
least one other instruction has been executed. Thus,
once an interrupt routine has beenentered,it cannot be
reentered until at least one instructionof the interrupted programis executed.One wayto use this feature for
single-stopoperationis to programone of the external
interrupts (say, INTO)to be level-activated.The service
routine for the interrupt willterminatewith the following cude:
JNB P3.2,$ ;Wait Here Till~Goes
High
P3.2,$ ;NowWait HereTill it Goes Low
JB
RETI
:Go Back and ExecuteOne Instruction
Now if the ~
pin, whichis alsothe P3.2 pin, is held
normallylow, the CPU will go right into the External
Interrupt Oroutine and stay there until ~
is pulsed
(from low to high to low). Then it will execute RETI,
go back to the task program, executeone instruction,
and immediatelyre-enter the Extend Interrupt Oroutine to await the next pulsingof P3.2. One step of the
task program is executedeach time P3.2 is puked.
~t2
RST:
The externalreset signalis asynchronousto the internal
clock. The RST pin is sampledduring State 5 Phase 2
of every machine cycle. The port pins will maintain
their current [email protected] 19 oscillatorperiods after a
logic 1 has been sampledat the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal
has been applied to the RST pin.
Whilethe RST pin is high, ALE and PSEN are weakly
pulledhigh. Mer RSTis pulledlow,it will take 1 to 2
machine cycles for ALE and PSEN to start clocking.
For this reason, other devicescan not be synchronized
to the internal timingsof the 8051.
Driving the ALE and PSEN pins to O while reset is
active could cause the deviceto go into an indeterminate state.
The internal reset algorithm writes 0s to all the SFRS
except the port latch= the Stack Pointer, and SBUF.
The port latches are initialized to FFH, the Stack
Pointer to 07H, and SBUF is indeterminate. Table 3
lists the SFRSand their reset values.
The internal R4M is not affectedby reset. On power
up the ILkM content is indeterminate
OSC. PERIODS ~
I//l/l/l///w
IN7ERNAL RESETSIGNAL
SAMPLE RST
SAMPti, RST
I
,
1 I I ~1 I I [ I I t,,
~:
1
Po:
!(
INST
—11
I
,
—19
Osc. PERIOOS
OSC. PERIODS —
270252-33
Figure 25. Reset Timing
3-26
i~o
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Table 3. Reset Values of the SFRS
I
ACC
07H
DPTR
I
PO-P3
I
OOOOH
FFH
1P(8051)
1
IE [8051)
IE (8052)
TMOD
TCON
I
THO
TLO
TH1
TL1
I
I
Whenpoweris turned on, the circuit holdsthe RSTpin
highfor an amount of time that dependson the capacitor value and the rate at whichit charges.To ensure a
valid reset the RST pin must be held high long enough
to allow the oscillator to stsrt up plus two machine
cycles.
XXXOOOOOB
XXOOOOOOB
1P(8052)
[
For HMOSdeviceswhenVCCis turned on an automatic reset can be obtainedby connectingthe RST pin to
V~ througha 10pF capacitor and to Vss throughan
8.2 Kf2 reeistor (Figure 26). The CHMOSdeviceado
not require this resistor although its presencedoea no
harm. In fact, for CHMOSdevicesthe externalresistor
can be removedbecausethey havean internalpulldown
on the RST pin. The capacitor valuecould then be rduced to 1 pF.
OOH
OOH
OOH
B
Psw
SP
I
I
POWER-ONRESET
Reset Value
OOOOH
SFR Name
Pc
OXXOOOOOB
OXOOOOOOB
OOH
OOH
OOH
TH2 (8052)
TL2 (8052)
On power up, VCCshould rise within approximately
ten milliseconds.The oscillator start-up time will dependon the oscillatorfrequency.Fora 10MHz crystal,
the start-up timeis typically 1rns.For a 1MHz crystal,
the start-up time is typically 10ms.
I
OOH
OOH
OOH
I
I
OOH
J
With the givencircui~ reducingVW quicklyto Ocauses the RST pin voltageto momentarilyfall below OV.
However,this voltageis internzdlylimitedand will not
harm the device.
OOH
OOH
OOH
OOH
RCAP2H(8052)
RCAP2L(8052)
SCON
NOTE:
The port pins will be in a random state until
the oscillatorhas started and the internal reset
algorithmhas written 1s to them.
Indeterminate
SBUF
PCON (HMOS)
PCON (CHMOS)
OXXXXXXXB
OXXXOOOOB
,.”,l
Powering up the device without a valid reset could
cause the CPU to start executinginstructionsfrom an
indeterrninatelocation. This is becausethe SFRs, apecitically the Program Counter, may not get properly
initialized.
k3
‘cc
Sml
ST
POWER-SAVINGMODESOF
OPERATION
For applicationswhere power consumptionis critical
the CHMOSversionprovideapowerreducedmodesof
operationas a standard feature. The powerdownmode
in HMOS devicesis nolongera standardfeatureandis
beingphased OUt.
UKIL
Isa
=
270252-21
Figure25. PoweronResetCircuit
CHMOSPowerReductionModes
CHMOS versions have two power-reducingmodes,
Idle and PowerDown.The input throughwhichbackup power is suppliedduring these operationsis VCC.
Figure 27 shows the internal circuitry which implements these features. In the Idle mode(IDL = 1), the
oscillator continuea to run and the Interrupt, Serial
Port, and Timer blockscontinueto be clocked,but the
3-27
intel.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
clock signal is gated off to the CPU. In Power Down
(PD = 1), the oscillator is frozen.The Idle and Power
Down modes are activated by setting bits in Special
Function RegisterPCON. The address of this regiete.r
is 87H. Figure 26 details ita contents.
An instructionthat sets PCON.Ocausesthat to be the
last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions.The CPU statue is preserved
in its entirety: the Stack Pointer, Program Counter,
Program StatueWord, Accumulator,and all other registers maintain their data during Idle. The port pins
hold the logical statea they had at the time Idle was
activated. ALE and PSEN hold at logichigh levels.
IOL
Natrteattd Furtotic+t
PoSnIOrt
PCON.7
OoubleSaud rats bit.When aattoa 1
and Timer 1 is used togenerrda baud
rate, andfhs SsrW .%rl is used in
modes 1,2, 0r3.
PCON.6
(Reserved)
FCON.5
(Reserved)
—
PCON.4
(Reaswsd)
GF1
PCON.3
General-purpose flag bit
GFO
PCX2N.2
Gemaraf-pu~
PD
FCX2N.I
Powsr Down M. Satfingthisbit
activates powsrdewmoperation.
IDL
PCON.O
Idle mode bit.Setfingthk btiactivataa
idle mode opsratiort
flqlrit.
If 1s arewrfrren to PD and IDL at the aametime, PDfskes
precedence.l%areeetvaluaof PCONia(OXXXOCOO).
In tfw HMOSd* ~N
@2taroII~contains SMOD.
Ttwofherfcurtit
eareimpkmer!tsd onfyintlw CHMOSdsvioea.
User mftwsre sfwuld rwverwite Istourimplememtsd bita,ainm
tfwymaybeuasdin future MCS-51 pmduote.
28.
PCON: PowerControlRegister
The signal at the RST pin clears the IDL bit directly
and asynchronously.At this time the CPU resumes
programexecutionfrom where it left off;that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cyclesof programexecutionmay take pleee beforethe
internal reset algorithm takes control. On-chip hardware inhibita access to the internal RAM during this
time, but aeccas to the port pins is not inhibited. To
eliminate the possibilityof unexpectedoutputs at the
port pine,the instructionfollowingthe onethat invokes
Idle should not be one that writes to a port pin or to
external Data RAM.
b-27.
PD
“ ting the Idle mode is with a
The other way of termma
hardware reset. Since the clock oscillator is still running the hardwarereset needsto be heldactivefor only
two machinecycles (24 oscillator periods)to complete
the reset.
2rAL2
Figure
GFO
The tlag bite GPO end GFI can be used to give an
indiesti;n if en interrupt occurred duringnorm~ operation or during an Idle. For example, an instruction
that activates Idle can also set one or both flag bita.
“ ted by an interrupt, the interrupt
When Idle is terrmna
serviceroutine can examine the fig bita.
riOh
‘L...
GF1
SMOD
Figure
There are two waysto t-ate
the Idle. Activationof
any enabledinterropt will cause PCON.Oto be ckared
“ ting the Idle mode.The interrupt
by hardware termma
will be [email protected] and followingRETI the next instruction to be executed will be the one followingthe instruction that put the deviceinto Idle.
I-I-I-
symbol
In the HMOSdeviceathe PCON registeronlycontains
SMOD. The other four bits are implementedonly in
the CHMOSdevices.User softwareshouldneverwrite
1s to unimplementedbita, since they may be used in
t%tureMCS-51products.
IDLE MODE
(Lss)
(MSB)
SMOO
Idle and Power Down Hardware
POWER DOWN MODE
An instructionthat seta PCON.1 cauaeathat to be the
last instruction executed before going into the Power
Down mode. In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all func-
3-28
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Table4. EPROMVersionsof the 8051and8052
Device
1
Name
EPROM
Version
EPROM
Bytes
Type
8051AH
8751H/8751BH
4K
Ckt
Time Required to
VPP
ProgramEntireArray
HMOS
21.0V112.75V
4 minutes
13 seconds
26 seconds
80C51BH
87C51
4K
CHMOS
12.75V
8052AH
8752BH
8K
HMOS
12.75V
tions are stopped, but the on-chip RAM and Special
Function Registeraare held. The port pins output the
valuesheld by their reapecdveSFRS.ALE and P8EN
output lows.
The only exit from Power Down for the 80C51is a
hardware reset. Reset redefinesall the SPRS,but does
not changethe on-chip W.
In the Power Down mode of operation, VCC can be
reducedto as low as 2V. Care must be taken, however,
to ensure that VCC is not reduced before the Power
Downmodeis invoked,and that VCCis restoredto its
normaloperatinglevel,beforethe PowerDownmodeis
terminated.The reset that terminatesPowerDownalso
frees the oaeillator. The reset should not be activated
before VCC is restored to its normal operating level,
and must be held active longenoughto allowthe oscillator to restart and stabilise (normally less than 10
maec).
EPROMVERSIONS
The EPROM versionsof these devieesare listedin Table 4. The 8751Hprograms at VPP = 21Vusing one
50 msec PROO pulse per byte programmed.This results in a total programmingtime (4K bytes)of approximately4 minutes.
The 8751BH, 8752BH and 87C51 use the faster
‘@i~k-p~>> pro~gm
~gorithm. ~=
de12.75Vusing a series of
twenty-fiveIMlps PROO pulsesper byteprogrammed.
This results in a total programmingtime of approximately 26 seconds for the 8752BH (8 Kbytes) and
13seeondsfor the 87C51(4 Kbytes).
Detailedprocedures for programming and verifying
each deviceare givenin the data sheets.
Exposureto Light
It is good practice to cover the EPROM windowwith
an opaquelabel when the deviceis in operation.This is
not so much to protect the EPROM array from inadvertent erssure but to protect the RAM and other onchip logic.Allowinglight to impingeon the silicondie
whilethe deviceis operatingcan csuae logicalmalfhnetion.
3-29
ProgramMemoryLocks
In somemicrocontrollerapplicationsit is desirablethat
the Program Memorybe secure from software piracy.
Intel has responded to this need by implementinga
Program Memorylockingschemein someof the MCS51devices.Whileit is impossiblefor anyoneto guarantee absolutesecurity againatall levelsof technological
sophistication,the ProgramMemorylocksin the MCS51deviceswillpresenta substantialbarrier againatillegal readout of proteetedsoftware.
One Lock Bit Scheme on 8751H
The 8751H contains a lock bit which, once pro-
grammed, denies electrical access by any external
means to the on-chipProgram Memory. The etht of
this lock bit is that whileit is programmedthe internal
Program Memorycan not be read out, the devicecan
not be further programmed,and it can not execute external ?%ognamMemory. Erasing the EPROM array
deactivates the lock bit and restores the device’sfull
functionality.It can then be re-progratnmed.
The procedurefor programmingthe lock bit is detailed
in the 8751Hdata sheet.
Two ProgramMemoryLockSshemes
The 8751BH,8752BHand 87C51contain two Program
Memory lockingschemes:Encryptedverify and Lock
Bits.
EncryptionArraw Within the EPROM is an array of
encryptionbytes that are initially unprogrammCd(au
l’s). The user ean program the array to encrypt the
code bytes during EPROM veriftcstion. The verification procedure sequentiallyXNORS each code byte
with oneof the keybytes.Whenthe last keybyte in the
-Y k reached,the verifyroutine starts over with the
first byte of the array for the next code byte. If the key
byteaare unprogrammed,the XNOR processleavesthe
code byte unchanged.With the keybytes programmed,
the code bytes are encryptedand can be read correctly
only if the key bytes are knownin their proper order.
Table 6 lists the number of encryptionbytrs available
on the variousproducts.
Whenusingthe encryptionarray, one important factor
should be considered. If a code byte has the value
[email protected]
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
OFFH,ven~g the byte will prqduce the encryption
byte value. If a large block of code is letl unprogrammed,a verificationroutinewilldisplaythe encryption array contents. For this reason all unused code
bytea should be progrsmmed with some value other
than OFFH, and not all of them the same value. This
will ensure maximumprogramprotection.
Prosram Lack Bita: Also included in the Program
Lack scheme are Lock Bits which csn be enabled to
providevaryingdegreesof protection,Table 5 lists the
L.cckBits and their correspondingeffecton the microcontroller.Refer to Table 6 for the Lock Bits available
on the variousproducts.
Erasing the EPROM also erases the EncryptionArray
and the Lack Bits,returningthe part to full functionality.
When Lock Bit 1 is programm~ the logiclevelat the
~ pin is sampledand latched during react. If the device is poweredup withouta reset, the latch inidalizes
to a random value, and holds that value until reset is
activated. It is ncassary that the latched value of ~
be in agreement with the current logic levelat that pin
in order for the deviceto function properly.
ROM PROTECTION
The 8051AHP and 30C51BHP are ROM Protectrd
versionsof the 3051AHand 30C51BH,respectively.To
incorporate this Protection Feature, program verification has been disabled and extcrnaf memory amessca
have been limited to 4K. Refer to the data sheets on
these parts for more information.
ONCETMMode
Table 5. Program Lo k Bits and their Features
Program Loci 3ita
——
LB1 LB2 LB3
Y-
u
No programlock features
enabled.(Code verifywill
stillbe encryptedbythe
encryptionarray if
programmed.)
T
u
MOVC instructions
executedfromexternal
programmemoryare
disabledfromfetching
code bytesfrom internal
memory,EA is sampled
and latchedon reset,and
furtherprogrammingof
the EPROM is disabled.
P
P
u
Same
P
P
P
Same as 3, also external
executionis disabled.
—
—
gremmed
—
ONCE (“on-circuit emulation”) mode facilitates
testing and debuggingof systemsusingthe devicewithout the &vice havingto be removed from the circuit.
ONCE mode is invokedby:
The
1. Pull ALE low whilethe deviceis in reactand PSEN
is high;
2. Hold ALE low as RST is deactivated.
The
Protection Type
While the deviceis in ONCE modq the Port Opins go
into a float state, and the other port pins and ALE and
~
are weakly pulled high. The oscillator circuit
remains active. While the device is in this modq an
emulator or teat CPU can be used to drive the circuit.
Normal operation is restored after a normal reset is
applied.
THE ON-CHIPOSCILLATORS
2, also verifyis
disabled.
as
HMOSVersions
cm-chip oscillator circuitry for the HMOS
(HMOS-Iand HMOS-11)membersof the MCS-51fsmily is a singlestage tinearinverter (Figure 29), intended
for usc as a crystal-controlled,positivereactance oscillator (Figure 30). In this appficstionthe crystal is operated in ita fundsmentafresponsemode as an inductive
reactarw in psralfel resonancewith capacitance-external to the crystal.
The
mogrammed
Any other combinationof the LockBits is not defied.
Table6. ProgramProtection
Device
LocfrBite
8751BH
8752BH
87C51
LB1, LB2
LB1, LB2
LB1, LB2, LB3
Enorypt Any
32 Bytes
32 Bytes
84 Bfles
3-30
in~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND80C51
b
J&
loamm4AL
Oa
rnllo
ImLz
ar
xrALl
CUTS
a4
T
Suesl.
01
%s
-
270252-23
Figure29.On-ChipOsciiiatorCircuitryinthe HMOS Versions of the [email protected]
V=*”=
--------
msl
In general, crystals used with these devices typically
have the followingspecifications:
!-+=9
‘a%’
.
xrALl ----
0
xraLr -----
ESR (EquivalentSeriesResistance)
c20(ShuntCapacitance)
CL(bid ~pr$ei~ee)
Drive Level
seeFigure 31
7.opFmax.
30pF *3 pF
1 mW
ouAnr2cRvalAL
ORC6RANICRESOWIOR
270252-24
Figure 30. Using the HMOS On-Chip Oeciiiator
crvstal meeifkationa and cauacitanee values (Cl
and C2-inFi&re 30)are not criti&l. 30 pF can be u&i
irr these positionsat any frequencywith good quality
crystals. A ceramic resonator can be used in place of
the crystal in cost-sensitiveapplications. When a ceramic resonatoris used,Cl and C2arenormally
seleetedto beof somewhat
highervaluea,
typically,47 pF.
The manufacturer of the ceramic resonator should be
consulted for recmnmcndationson the vaiucs of thCSC
capacitors.
The
3-31
4
a
12
16
CRYS7ALFSEQUEHCV
in MHz
270252-34
—.
- -—— -
Figure 31. ESR VSFr6!qUenOy
[email protected]
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
Frequency,toleranceand temperaturerange are determined by the systemrequirements.
CHMOSVersions
A more in-depthdiscussionof crystalspeciticstions,ceramic reaonstors,and the selectionof valuesfor Cl and
C2 can be foundin ApplicationNoteAP-155,“Oscillators for Microcontrollers,” which is included in the
Embedded Appticatwnz Handbook.
The on-chip oscillator circuitry for the 80C51BH,
shown in Figure 33, consists of a single stage linear
inverter intended for use as a crystal-controlled,positive reactance oscillator in the same manner as the
HMOSparta. However, there are some important differences.
To drive the HMOS parts with an external clock
source, apply the external clock signalto XTAL2, rmd
ground XTAL1,as shownin Figure32.A pullup reaistor may be used (to increase noisemargin), but is optional ifVOH of the drivinggate exceedsthe VIH MIN
specificationof XTAL2. --
One differenceis that the 80C51BHis able to turn off
its oscillatorunder software control (by writing a 1 to
the PD bit in PCON). Another differenceis that in the
80C51BHthe internal clockingcircuitry is driven by
the signalat XTAL1, whereasin the HMOSversionsit
is by the signalat XTAL2.
The feedbackresistor Rfin Figure 33 consistsof paralleledn- and p- channel FETs controlledby the PD bit,
such that Rf is opened when PD = 1. The diodeaD1
and D2, which act as clamps to VCC and VSS, are
parasitic to the Rf FETs.
+-!4
V&
msl
EXTSRNAL
XTAU
oeenLAloR
SIGNAL
The oscillatorcan be used with the same external componentsas the HMOS versio~ as shownin Figure 34.
Typically,Cl = C2 = 30 pF when the feedbackelementis a quartz crystal, and Cl = C2 = 47 pF whena
ceramicreaonator is used.
XTAL1
t
v=
GATE
mTsu.PoLe
‘
OUTPUT
To drive the CHMOS parts with ass external clock
sourcq apply the external clocksignalto XTAL1, and
leaveXT-=2 float, as shownin F&ssre35.
270252-25
Figure32.Drivingthe [email protected]
Partewithan ExtemsdClockSource
m
xrALl
c1
L
Mon
s
r?“
02
al
I
Q%e
270252-26
Figure
33. On-Chip
Osoillsstor
Circuitry
In the
3-32
CHMOS
Versions
of the
[email protected]
Family
i~e
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
w
he
70 m?lsmu
nsaNo curs
F5
m
----
%s
—---
xrMl
-----
I
w
v
c1
Q
=
xrAL2------
1
270252-27
Figure 34. Usingthe CHMOS On-ChipOscillator
I
MC+
Soeal
INTERNALTIMING
Figures 36 through 39 show when the various strobe
and port signals are clockedinternally.The figuresdo
not showrise and fall times of the signals,nor do they
showpropagationdelaysbetweenthe XTALsignaland
eventsat other pins.
X-rAu
*
270252-28
Figura 35. Driving the CHMOS [email protected]’-5l
Parts with an External Clock Source
The reason for this change from the way the HMOS
part is drivencan be seenby comparingFigures29 and
33. In the HMOS devices the internal timing oircuits
are driven by the signal at XTAL2. In the CHMOS
devicesthe internal timing circuits are driven by the
signalat XTAL1.
Rise and fall times are dependenton the external loadingthat each pin must drive.They are oftentaken to be
somethingin the neighborhoodof 10 ~
measured
bemveen0.8V and 2.OV.
Propagationdelays are differentfor differentpins. For
a given pin they vary with pin loading temperature,
VCC,and manufacturinglot. If the XTALwaveformis
taken as the timing referenee, prop delays may vary
from 25 to 125nsec.
The AC Timingssectionof the data sheetsdo not reference any timing to the XTAL waveform.Rather, they
relate the criticsdedges of control and input signalsto
eaoh other. The timings published in the data sheets
include the effects of propagation delays under the
specitledtest conditions.
3-33
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
SYATS1 STATS2 STAY53 STATS4 SYATS5 STATS6 STATS1 ~AlS2
Imlmlmlmlnlmlmlmlm
lmlmlmlmlnlm,nl
XIAk
ALS: ~
~:
DATA
w:
OATA
+aANPLsD
4
1
8
P2:
I
OATA
-SAMPLSO
1
Pet’loul
E
Pctlour
Pcnoul
270252-29
Figure 36. External Program Memory Fetches
STATS 4 STATE 5 SYATS6
ln,mlPllmlnlml
SYATE1 SYAYE2 STATS3 STA= 4 SIATE5
Mlml MlwlPllmlPl IAIF+I
XTAL
‘“:
~
~&
1
OPLOR
RI
OUT If
PO:
P2:
PCHOR
P2am
OAIA2AMPLS0
FLOAT
0% ORP2SFRour
PCLOUYF
PRoGw NSNORY
s axrER?4AL
PCHOR
P2am
270252-20
Figure37.ExtemelDateMemoryRead~cle
3-34
intdo
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
STATE 5 2TATE 6 STATE 1
STATE4
STATE
2
STATE 3 STATE4 STATE 5
I‘11’2 IPllP2IPI1’2I‘11’2I‘11’2 I PI1’2I PllP2I ‘1 I ‘2 I
XTAIJ
“’~
~:
DPLORRI
OuT
PO:
‘2
P2em
PcHOn
PCLOUTF
PROGRAM MEMORV
16exramu
1
1
OATAOUT
On
P2eFu
I Pctl
oPHoRP2amour
270252-31
Figure38. External Data Memory WriteCycle
STATE4
STATE 6 STATE6
2TATE 1 STATE 2 STATES STAlE4
PllP21PllP21Pl lmlnlmlmlnlmlnl
STATES
nlmlPllml
Irrk
“–’HpD”
x:”
NovPowr,eRc:
N2WOATA
OLOOATA
s!~
+
+nxo
RxoeAuPLeo+
---
+
270252-32
Figure 39. Port Operation
3-35
i~.
HARDWARE DESCRIPTION OF THE 8051,8052 AND80C51
ADDITIONALREFERENCES
The following application notes and articles are found in the Embedded Applications handbook.
(Order Number:270648)
1. AP-125“DesigningMicrocontrollerSystemsfor ElectricallyNoisy Environments”.
2. AP-155“Oscillatorsfor Microcontrollers”.
3. AP-252“Designingwith the 80C51BH”.
4. AR-517“Usingthe 8051Microcontrollerwith ResonantTransducers”.
3-36
8XC5U54/58Hardware
Description
4
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