NXP 8xC51MA2, 8xC51MB2, 8xC51MB2/02, 8xC51MC2

NXP 8xC51MA2, 8xC51MB2, 8xC51MB2/02, 8xC51MC2

INTEGRATED CIRCUITS

USER’S MANUAL

P87C51MB2/P87C51MC2

80C51 8-bit microcontroller family with extended memory

64KB/96KB OTP with 2KB/3KB RAM

Preliminary 2002 June 28

Version 0.95

Philips

Semiconductors

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

1 INTRODUCTION ............................................................................................................................1

1.1

The 51MX CPU CORE ..........................................................................................................1

1.2

P87C51Mx2 microcontrollers.................................................................................................1

1.3

P87C51Mx2 Logic Symbol ....................................................................................................3

1.4

P87C51Mx2 Block Diagram ..................................................................................................4

2 Memory Organization ......................................................................................................................5

2.1

Programmer’s Models and Memory Maps .............................................................................5

2.2

Data Memory (DATA, IDATA, and EDATA).......................................................................6

2.2.1

Registers R0 - R7 .....................................................................................................6

2.2.2

Bit Addressable RAM..............................................................................................7

2.2.3

Extended Data Memory (EDATA)..........................................................................7

2.2.4

Stack.........................................................................................................................7

2.2.5

General Purpose RAM...........................................................................................10

2.3

Special Function Registers (SFRs) .......................................................................................11

2.4

External Data Memory (XDATA) ........................................................................................12

2.5

High Data Memory (HDATA) .............................................................................................12

2.6

Program Memory (CODE) ...................................................................................................14

2.7

Universal Pointers.................................................................................................................15

3 51MX Instructions ..........................................................................................................................20

3.1

Instruction Set Summary ......................................................................................................22

3.2

51MX Operation Code Charts ..............................................................................................23

4 External Bus ....................................................................................................................................28

4.1

Multiplexed External Bus .....................................................................................................28

5 Interrupt Processing .......................................................................................................................30

6 P87C51Mx2 Ports, Power Control and Peripherals....................................................................34

6.1

Special Function Registers....................................................................................................34

6.2

P87C51Mx2 Ports.................................................................................................................37

6.2.1

Ports 0, 1, 2, 3 ........................................................................................................37

6.2.2

Port 4......................................................................................................................37

6.3

P87C51Mx2 Low Power Modes...........................................................................................38

6.3.1

Stop Clock Mode ...................................................................................................38

6.3.2

Idle Mode ...............................................................................................................38

6.3.3

Power-Down Mode................................................................................................38

6.3.4

Power-On Flag .......................................................................................................40

6.3.5

Design Consideration.............................................................................................40

6.3.6

ONCE™ Mode ......................................................................................................40

6.3.7

Low Power Eprom Operation (LPEP) ..................................................................40

6.4

Timers/Counters 0 and 1.......................................................................................................40

6.4.1

Mode 0 ...................................................................................................................41

6.4.2

Mode 1 ...................................................................................................................41

1 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.4.3

Mode 2 ...................................................................................................................41

6.4.4

Mode 3 ...................................................................................................................42

6.5

Timer 2..................................................................................................................................44

6.5.1

Capture Mode ........................................................................................................44

6.5.2

Auto-Reload Mode (Up or Down Counter) ...........................................................44

6.5.3

Programmable Clock-Out ......................................................................................45

6.5.4

Baud Rate Generator Mode For UART 0 (Serial Port 0) ......................................47

6.5.5

Summary Of Baud Rate Equations ........................................................................48

6.5.6

Timer/Counter 2 Set-up .........................................................................................48

6.6

UARTs ..................................................................................................................................51

6.6.1

Mode 0 ...................................................................................................................51

6.6.2

Mode 1 ...................................................................................................................51

6.6.3

Mode 2 ...................................................................................................................51

6.6.4

Mode 3 ...................................................................................................................51

6.6.5

SFR and Extended SFR Spaces .............................................................................51

6.6.6

Baud Rate Generator and Selection .......................................................................52

6.6.7

Framing Error ........................................................................................................55

6.6.8

Status Register .......................................................................................................56

6.6.9

More About UART Mode 1...................................................................................57

6.6.10

More About UART Modes 2 and 3 .......................................................................58

6.6.11

Double Buffering ...................................................................................................60

6.6.12

Multiprocessor Communications ...........................................................................62

6.6.13

Automatic Address Recognition ............................................................................62

6.7

Watchdog Timer ...................................................................................................................63

6.7.1

Watchdog Function................................................................................................63

6.7.2

Feed Sequence .......................................................................................................63

6.7.3

WDT Control .........................................................................................................66

6.7.4

WatchDog Reset Width .........................................................................................66

6.7.5

Reading from the WDCON SFR ...........................................................................66

6.7.6

Software Reset Via WatchDog Timer Feed Sequence ..........................................66

6.8

Additional Features...............................................................................................................67

6.8.1

Expanded Data RAM Addressing..........................................................................67

6.8.2

Dual Data Pointers .................................................................................................68

6.9

Programmable Counter Array (PCA) ...................................................................................68

6.9.1

PCA Capture Mode................................................................................................72

6.9.2

16-bit Software Timer Mode .................................................................................73

6.9.3

High Speed Output Mode ......................................................................................73

6.9.4

Pulse Width Modulator Mode................................................................................73

6.9.5

PCA Watchdog Timer ...........................................................................................73

2 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

1 INTRODUCTION

P87C51Mx2 User Manual

P87C51Mx2

1.1

THE 51MX CPU CORE

Philips Semiconductor’s 51MX (Memory eXtension) core is based on an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear, unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes (KB) limit to support up to 8 megabytes (MB) of program memory and 8 MB of data memory. It retains full program code compatibility to enable design engineers to reuse 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core retains 80C51 bus compatibility to allow for the continued use of

80C51-interfaced peripherals and Application-Specific Integrated Circuits (ASICs). However, by entering the Extended

Addressing Mode in order to access either data or code beyond 64 KB, the bus interface changes.

The 51MX core is completely backward compatible with the 80C51: code written for the 80C51 may be run on 51MX-based derivatives with no changes.

Summary of differences between the classic 80C51 architecture and the 51MX core:

• Program Counter: The Program Counter is extended to 23 bits.

• Extended Data Pointer: A 23-bit Extended Data Pointer called the EPTR has been added in order to allow simple adjustment to existing assembly language programs that must be expanded to address more than 64 KB of data memory.

• Stack: Two independent alternate Stack modes are added. The first causes addresses pushed onto the Stack by interrupts to be expanded to 23 bits. The second allows Stack extension into a larger memory space.

• Instruction set: A small number of instructions have extended addressing modes to allow full use of extended code and data addressing.

• Addressing Modes: A new addressing mode, Universal Pointer mode, is added that allows accessing all of the data and code areas except for SFRs using a single instruction. This mode produces major improvements in size and performance of compiled programs.

• Six clock cycles per machine cycle.

The 51MX core is described in more details in the 51MX Architecture Reference.

1.2

P87C51MX2 MICROCONTROLLERS

The P87C51Mx2 represents the first microcontroller based on the 51MX core. The P87C51MC2 features 96 KB of OTP program memory and 3 KB of data SRAM, while the P87C51MB2 has 64 KB of OTP and 2 KB of RAM. In addition, both devices are equipped with a Programmable Counter Array, a watchdog timer that can be configured to different time ranges, as well as two enhanced UARTs.

The P87C51Mx2 provides greater functionality, increased performance, and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for software workarounds. The increased program memory enables design engineers to develop more complex programs in a highlevel language like C, for example, without struggling to contain the program within the traditional 64 KB of program memory.

These enhancements also greatly improve C language efficiency for code sizes below 64 KB.

KEY FEATURES

• 23-bit program memory space and 23-bit data memory space

• 96 KB or 64 KB of on-chip OTP

• 3 KB or 2 KB of on-chip RAM

• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

1 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

• Programmable Counter Array (PCA)

• Two full-duplex enhanced UARTs

P87C51Mx2 User Manual

P87C51Mx2

KEY BENEFITS

• Increases program/data address range to 8 MB each

• Enhances performance and efficiency for C programs

• Fully 80C51-compatible microcontroller

• Provides seamless and compelling upgrade path from classic 80C51

• Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs

• Supported by 80C51 development and programming tools

• The P87C51Mx2 makes it possible to develop applications at a lower cost and with a reduced time-to-market

COMPLETE FEATURES

• Fully static

• Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

• 96 KB or 64 KB of on-chip OTP

• 3 KB or 2 KB of on-chip RAM

• 23-bit program memory space and 23-bit data memory space

• Four interrupt priority levels

• 32 I/O lines (4 ports)

• Three Timers: Timer0, Timer1 and Timer2

• Two full-duplex enhanced UARTs with baud rate generator

• Framing error detection

• Automatic address recognition

• Power control modes

• Clock can be stopped and resumed

• Idle mode

• Power down mode

• Second DPTR register

• Asynchronous port reset

• Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules

• Low EMI (inhibit ALE)

• Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)

80C51 COMPATIBILITY FEATURES OF THE 51MX CORE

• 100% binary compatibility with the classic 80C51 so that existing code is completely reusable

• Linear program and data address range expanded to support up to 8 MB each

• Program counter and data pointers expanded to 23 bits

• Stack pointer extended to 16 bits

2 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

1.3

P87C51MX2 LOGIC SYMBOL

V

DD

V

SS

RXD0

TXD0

INT0

INT1

T0

T1

WR

RD

RXD1

TXD1

RST

EA/Vpp

PSEN

ALE/PROG

P87C51Mx2

XTAL2

XTAL1

Figure 1: P87C51Mx2 Logic Symbol

T2

T2EX

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

P87C51Mx2 User Manual

P87C51Mx2

3 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

1.4

P87C51MX2 BLOCK DIAGRAM

Crystal or

Resonator

96KB / 64KB

Code OTP

High Performance

80C51 CPU

(51MX Core)

Internal Bus

UART 0

3KB / 2KB

Data RAM

Baud Rate

Generator

UART 1

Port 3

Port 2

Port 1

Port 0

Oscillator

Timer0

Timer1

Watchdog Timer

PCA

(Programmable

Counter Array)

Timer2

P87C51Mx2 User Manual

P87C51Mx2

Figure 2: P87C51Mx2 Block Diagram

4 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

2 MEMORY ORGANIZATION

P87C51Mx2 User Manual

P87C51Mx2

2.1

PROGRAMMER’S MODELS AND MEMORY MAPS

The P87C51Mx2 retains all of the 80C51 memory spaces. Additional memory space has been added transparently as part of the means for allowing extended addressing. The basic memory spaces include code memory (which may be on-chip, off-chip, or both); external data memory; Special Function Registers; and internal data memory, which includes on-chip RAM, registers, and stack. Provision is made for internal data memory to be extended, allowing a larger processor stack.

The P87C51Mx2 programmer’s model and memory map is shown in Figure 3.

CODE

7F:FFFFh

Two 24-bit Universal Pointers

R7 R6 R5

R3 R2 R1

23-bit Program Counter

23-bit Extended Data Pointer

Two 16-bit DPTRs

16-bit Stack Pointer

HDATA

(includes XDATA)

7E:FFFFh

On-Chip and/or

Off-Chip

Code Memory

8 MB Code

Memory Space

PSW B A

EDATA

(includes DATA & IDATA)

Extended Data

Memory

(stack and indirect addressing)

4FFh

00:0000h

Extended SFRs

Special Function

Registers

(directly addressable)

IDATA

(includes DATA)

256 Byte On-Chip

Data Memory

(stack and indirect addressing)

100h

FFh

DATA

128 Byte On-Chip

Data Memory

(stack, direct and indirect addressing)

Four Register Banks

R0 - R7

Data Memory Space

(DATA, IDATA, EDATA)

80h

7Fh

00h

Off-Chip

Data Memory

XDATA

00:07FFh

00:06FFh

1792 Bytes On-Chip

Data Memory

(P87C51MC2)

XDATA

00:0300h

00:02FFh

768 Bytes On-Chip

Data Memory

(P87C51MB2)

00:0000h

8 MB - 64 KB External

Data Memory Space

(XDATA, HDATA)

Figure 3: P87C51MB2/C2 Programmer’s Model and Memory Map

5 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary.

DATA

IDATA

EDATA

SFR

128 bytes of internal data memory space (00h...7Fh) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.

Indirect Data. 256 bytes of internal data memory space (00h...FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

Extended Data. This is a superset of DATA and IDATA areas. Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory. The added area may be accessed only as Stack and via indirect addressing using

Universal Pointers. The Stack may reside in the extended area if enabled to do so.

Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing (addresses in range 80h...FFh). This includes the new 51MX extended SFRs.

XDATA "External" Data. Duplicates the classic 80C51 64 KB memory space addressed via the MOVX instruction using the

DPTR, R0, or R1. On-chip XDATA can be disabled under program control. Also, XDATA may be placed in external devices. P87C51MB2 has 768 bytes of on-chip XDATA memory space and P87C51MC2 has 1792 bytes of on-chip

XDATA memory space.

HDATA "High" Data. This is a superset of XDATA and may include up to 8,323,072 bytes (8 MB - 64 KB) of memory space addressed via the MOVX instruction using the EPTR, DPTR, R0, or R1. Non XDATA portion of HDATA is placed in external devices.

CODE Up to 8 MB of Code memory, accessed as part of program execution and via the MOVC instruction.

All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV instruction. This feature is detailed in a subsequent section.

2.2

DATA MEMORY (DATA, IDATA, AND EDATA)

The standard 80C51 internal data memory consists of 256 bytes of DATA/IDATA RAM, and is always entirely on-chip. In this space are the data registers R0 through R7, the default stack, a bit addressable RAM area, and general purpose data RAM. On the top of the DATA/IDATA memory space is a 1 KB block of RAM that can be accessed as stack or via indirect addressing.

Alltogether this forms EDATA RAM of 1280 bytes. The different portions of the data memory are accessed in different manners as described in the following sections.

2.2.1

REGISTERS R0 - R7

General purpose registers R0 through R7 allow quick, efficient access to a small number of internal data memory locations. For example, the instruction:

MOV A,R0 uses one byte of code and executes in one machine cycle. Using direct addressing to accomplish the same result as in:

MOV A,10h requires two bytes of code memory and executes in two machine cycles. Indirect addressing further requires setup of the pointer register, etc.

These registers are “banked”. There are four groups of registers, any one of which may be selected to represent R0 through R7 at any particular time. This feature may be used to minimize the time required for context switching during an interrupt service or a subroutine, or to provide more register space for complicated algorithms.

The registers are no different from other internal data memory locations except that they can be addressed in "shorthand" notation as "R0", "R1", etc. Instructions addressing the internal data memory by other means, such as direct or indirect addressing, are quite capable of accessing the same physical locations as the registers in any of the four banks.

6 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

2.2.2

BIT ADDRESSABLE RAM

Internal data memory locations 20 hex through 2F hex may be accessed as both bytes and bits. This allows a convenient and efficient way to manipulate individual flag bits without using much memory space. The bottom bit of the byte at address 20h is bit number 00h, the next bit in the same byte is bit number 01h, etc. The final bit, bit 7 of the byte at address 2Fh, is bit number

7Fh (127 decimal). Bit numbers above this refer to bits in Special Function Registers.

This code:

SETB

CPL

JNB

20h.1

20h.2

20h.2, LABEL1 sets bit 1 at address 20 hex, complements bit 2 in the same byte, then branches if the second bit is not equal to 1. In an actual program, these bits would normally be given names and referred to by those names in the bit manipulation instructions.

2.2.3

EXTENDED DATA MEMORY (EDATA)

The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic

80C51s. This space can be used as an extended or alternative processor stack space, or can be used as general purpose storage under program control. Other than Stack Pointer based access to this space, which is automatic if Extended Stack

Memory Mode is enabled (see the following Stack section), this memory is addressed only using the new Universal Pointer feature. Universal Pointers are described in a later section.

Both P87C51MB2 and P87C51MC2 have 1280 bytes of SRAM in EDATA memory.

2.2.4

STACK

The processor stack provides a means to store interrupt and subroutine return addresses, as well as temporary data. The stack grows upwards, from lower addresses towards higher addresses. The current Stack Pointer always points to the last item pushed on the stack, unless the stack is empty. Prior to a push operation, the Stack Pointer is incremented, then data is written to memory. When the stack is popped, the reverse procedure is used. First, data is read from memory, then the Stack Pointer is decremented.

The default configuration of the 51MX stack is identical to the classic 80C51 stack implementation. When interrupt or subroutine addresses are pushed onto the stack, only the lower 16 bits of the Program Counter are stored. This default 80C51 mode stack

operation is shown in Figure 4.

7 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

This figure applies to the ACALL and

LCALL instructions in all modes. In

80C51 stack mode, it also applies to interrupt processing.

PCH (PC.15-8)

PCL (PC.7-0)

0083h

0082h

0081h

0080h

007Fh

Final SP Value (after ACALL,

LCALL or Interrupt)

Initial SP Value (before

ACALL, LCALL, or interrupt)

Figure 4: Return Address Storage on the Stack (80C51 Mode)

There are two configuration options for the stack. For purposes of backward compatibility with the classic 80C51, both alternate modes are disabled by a chip reset. The first option, Extended Interrupt Frame Mode, causes interrupts to push the entire 23-bit

Program Counter onto the stack (as three bytes), and the RETI instruction to pop all 23-bits as a return address, as shown in

Figure 5. The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a "1" to be

consistent with Universal Pointer addressing.

Storing the full 23-bit Program Counter value is a requirement for systems that include more than 64 KB of program, since an interrupt could occur at any point in the program. The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruction only, while other calls and returns are not affected. Special extended call and return instructions allow large programs to traverse the entire code space with full 23-bit return addresses. The Extended Interrupt Frame Mode is enabled by setting the EIFM bit in the MXCON register.

This figure applies to interrupt services in Extended Interrupt Frame

Mode, as well as the ECALL instruction in all modes.

The upper bit of the byte containing

PCE is forced to a "1" in order to be consistent with Universal Pointers.

PCE (PC.22-16)

PCH (PC.15-8)

PCL (PC.7-0)

0083h

0082h

0081h

0080h

007Fh

Figure 5: Extended Return Address Storage on the Stack

Final SP Value (after

ECALL or interrupt)

Initial SP Value (before

ECALL or interrupt)

8 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

The second stack option, Extended Stack Memory Mode, allows for stack extension beyond the 256 byte limit of the classic

80C51 family. Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory. Stack extension has no effect on the data

that is stored on the stack, it will continue to be stored as shown on in figures 4 and 5. The Extended Stack Memory Mode is

enabled by setting the ESMM bit in the MXCON register.

If the Stack Pointer is not initialized by software, the stack will begin at on-chip RAM address 8, just as for the 80C51. Also note that in Extended Stack Memory Mode, both MB2 and MC2 parts have 1KB of RAM on the top of DATA/IDATA space available for the stack.

The stack mode bits ESMM and EIFM are shown in Figure 6. Note that the stack mode bits are intended to be set once during

program initialization and not altered after that point. Changing stack modes dynamically may cause stack synchronization problems.

MXCON

Address: FFh (51MX Extended SFR Space)

Not bit addressable

7 6

Reset Value: 00h -

BIT

MXCON.7 - 3

MXCON.2

MXCON.1

MXCON.0

SYMBOL

-

EAM

ESMM

EIFM

5

-

4

-

3

-

2

EAM

1

ESMM

0

EIFM

FUNCTION

Reserved. Programs should not write a 1 to these bits.

Enables Extended Addressing Mode, in connection with a non-volatile user configuration bit. The logical OR of the SFR bit and the non-volatile configuration bit determines whether code and data addressing beyond 64 KB is allowed. The same logical OR value will be read from this bit by software. When 0, all addressing (on-chip and off-chip) is limited to

64 KB each of code and data. When 1, 51MX addressing capabilities are extended beyond boundary of 64 KB to 8 MB each of code and data, and upper address bits are

multiplexed on Port 2 for external code and/or data accesses. Refer to the External Bus

section for additional details.

EAM must be set to EAM=1 if at least one of the next two statements is true:

- there is executable code or constants in CODE space are above 64 KB

- address of data byte that has to be accessed in HDATA is above 64 KB

Enables the Extended Stack Memory Mode. When ESMM = 0, the Stack Pointer is 8 bits in width and the stack is located in the IDATA memory space. When ESMM = 1, the Stack

Pointer is increased to 16-bits in width and the stack may be located anywhere in the

EDATA space. ESMM is independent of EAM and EIFM bits.

Enables the Extended Interrupt Frame Mode. When EIFM = 0, an interrupt service will cause only the lower 16 bits of the PC to be pushed onto the stack, and an RETI instruction will restore only the lower 16 bits of the PC. When EIFM = 1, an interrupt service will cause all 23 bits of the PC to be pushed onto the stack, while an RETI instruction will restore all 23 bits of the PC. EIFM must be set to one if the application allows execution beyond the first 64 KB of code memory.

Figure 6: MX Configuration Register (MXCON)

9 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

2.2.5

GENERAL PURPOSE RAM

Portions of the internal data memory that are not used in a particular application as registers, stack, or bit addressable locations may be considered general purpose RAM and used in any desired manner.

The lower 128 bytes of the internal data memory (DATA) may be accessed using either direct or indirect addressing. Direct addressing incorporates the entire address within the instruction. For example, the instruction:

MOV 31h,#10 will store the value 10 (decimal) in location 31 hex. Direct addresses above 128 will access the Special Function Registers rather than the internal data memory.

Indirect addressing takes an address from either R0 or R1 of the current register bank and uses it to identify a location in the internal data memory. The entire 256 byte internal data memory space (IDATA) may be accessed using indirect addressing. For example, the instruction sequence:

MOV

MOV

R0,#90h

A,@R0 will cause the contents of location 90 hex to be loaded into the accumulator. It is typical with the classic 80C51 to cause the stack to be located in the upper area, leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect addressing. With the 51MX, the stack may be extended and moved completely out of the lower 256 bytes of memory.

8 Bytes

1F

17

0F

07

3F

37

2F

27

5F

57

4F

47

7F

77

6F

67 bit 7F … bank 3 bank 2 bank 1 bank 0

… bit 0

18

10

08

00

38

30

28

20

58

50

48

40

78

70

68

60

Undedicated

Area

Bit Addressable

Segment

Register

Banks

Figure 7: Internal Data Memory, Lower 128 Bytes

10 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

2.3

SPECIAL FUNCTION REGISTERS (SFRS)

Special Function Registers (SFRs) provide a means for the processor to access internal control registers, peripheral devices, and I/O ports. An SFR address is always contained entirely within an instruction.

The standard SFR space is 128 bytes in size. SFRs are implemented in each 51MX device as needed in order to provide control for peripherals or access to CPU features and functions. Undefined SFRs are considered "reserved" and should not be accessed by user programs.

Sixteen addresses in the SFR space are both byte- and bit-addressable. The bit-addressable SFRs are those whose address ends in 0h or 8h (i.e. 80h, 88h, ..., F8h). Bit addressing allows direct control and testing of bits in those SFRs.

All 51MX devices also have additional 128 bytes of extended SFRs as discussed in the "51MX Architecture Reference". Figures

8 and 9 show the SFR and the Extended SFR maps for P87C51MB2/C2 parts.

D8

D0

C8

C0

F8

F0

E8

E0

0 / 8

IP1

B

IEN1

ACC

CCON

PSW

T2CON

1 / 9

CH

CL

CMOD

T2MOD

B8

B0

A8

A0

IP0

P3

IEN0

P2

S0ADEN

S0ADDR

98

90

S0CON

P1

S0BUF

88 TCON TMOD

80 P0

Bit Addressable SFRs

SP

2 / A

CCAP0H

CCAP0L

CCAPM0

R2CAPL

AUXR1

TL0

DPL

3 / B

CCAP1H

CCAP1L

CCAPM1

R2CAPH

TL1

DPH

4 / C

CCAP2H

CCAP2L

CCAPM2

TL2

TH0

5 / D

CCAP3H

CCAP3L

CCAPM3

TH2

TH1

6 / E

CCAP4H

CCAP4L

CCAPM4

WDRST

AUXR

7 / F

IP1H

IP0H

PCON

Figure 8: Standard SFR Map for the P87C51Mx2

Figure 9 shows the extended SFR map for the P87C51Mx2.

9F

97

8F

87

BF

B7

AF

A7

DF

D7

CF

C7

FF

F7

EF

E7

11 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

D8

D0

C8

C0

F8

F0

E8

E0

0 / 8 1 / 9 2 / A 3 / B

SPE

4 / C

EPL

5 / D

EPM

6 / E

EPH

B8

B0

A8

A0

98

90

88 S0STAT

80 S1CON S1BUF S1ADDR S1ADEN S1STAT BRGCON BRGR0

Bit Addressable SFRs

7 / F

MXCON

WDCON

BRGR1

Figure 9: Extended SFRs Map for the P87C51Mx2

9F

97

8F

87

BF

B7

AF

A7

DF

D7

CF

C7

FF

F7

EF

E7

2.4

EXTERNAL DATA MEMORY (XDATA)

The XDATA space on the 51MX is the same as the 64 KB external data memory space on the classic 80C51.

On-chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register. Accesses above implemented on-chip XDATA will be routed to the external bus. If on-chip XDATA memory is disabled, all XDATA accesses will be routed to the external bus. P87C51MB2 has 768 bytes of on-chip XDATA, while P87C51MC2 has 1792 bytes of on-chip

XDATA memory.

2.5

HIGH DATA MEMORY (HDATA)

The 51MX architecture supports up to an 8 MB data memory space, using 23-bit addressing. The entire 8 megabyte space except for the 64 KB EDATA space is called HDATA. The XDATA space comprises the lower 64 KB of HDATA.

Data Pointers

The 51MX adds an additional 23-bit Extended Data Pointer (EPTR) in order to allow a simple method of extending existing 80C51 programs to use more than 64 KB of data memory. If we want to access a single data byte from HDATA RAM located above the first 64 KB, EAM bit in MXCON sfr must be set to EAM=1.

All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR. The 23-bit EPTR is comprised of (in order)

EPH, EPM, and EPL. Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR

respectively. Since the EPTR is a 23-bit value, the 8th bit of EPH is not used. If read, it will return a 1, like other unimplemented bits in SFRs. Use of the EPTR allows access to the entire HDATA space, including XDATA.

12 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

At any point in time, one specific Data Pointer is active and is used by instructions that reference the DPTR. The active DPTR may be changed by altering the Data Pointer Select (DPS) bit. The DPS bit occupies the bottom bit of the AUXR1 register. The

DPS bit applies only to the two DPTRs, not to the EPTR.

In the indirect addressing mode, the currently active DPTR or the EPTR provides a data memory address for accessing the

XDATA and HDATA space respectively. When the DPTR is used for addressing, only the XDATA space is available. When the

EPTR is used for addressing, the entire HDATA space (which includes the XDATA space) may be accessed. If the EPTR value exceeds 7E:FFFF (the limit of HDATA), data accesses using EPTR will yield undefined results. The reason for limiting HDATA addresses is to keep the addressing uniform for EPTR addressing and Universal Pointer addressing (which is explained in a later section of this document).

Example Instruction:

MOVX @DPTR,A

External Data

Memory

DPS

0

Data Pointers

(00:A17Ch)

0 = A17Ch

1 = 2962h

Location

00:A17Ch:

33h

Accumulator

33h

Figure 10: External Data Memory Access using Indirect Addressing with DPTR

Example Instruction:

MOVX A,@EPTR

EPTR

0 = 01:1034h

External Data

Memory

Location

01:1034h:

3Bh

Accumulator

3Bh

Figure 11: External Data Memory Access using Indirect Addressing with EPTR

13 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

2.6

PROGRAM MEMORY (CODE)

The 80C51, and thus the 51MX, are "Harvard" architectures, meaning that the code and data spaces are separated. If there is a single byte of executable code above 64 KB, EAM bit in MXCON sfr must be set to EAM=1. Also, if there is constant in CODE space above 64 KB boundary that is read by the application, EAM must be set to EAM=1, too.

The 51MX expands the 80C51 Program Counter to 23 bits, providing a contiguous, unsegmented linear code space that may be as large as 8 MB. On-chip space begins at code address 0 and extends to the limit of the on-chip code memory. Above that, code will be fetched from off-chip. The 51MX architecture allows for an external bus which supports:

• Mixed mode (some code and/or data memory off-chip).

• Single-chip operation (no external bus connection).

• ROMless operation (no use of on-chip code memory).

In some cases, code memory may be addressed as data. Extended instruction address modes provide access to the entire code space of 8 MB through the use of indexed indirect addressing. The currently active DPTR, the EPTR, a Universal Pointer, or the

Program Counter may be used as the base address. Examples of the various code memory addressing modes are shown in

figures 12 through 14.

Following a reset, the 51MX begins code execution like a classic 80C51, at address 00:0000h. Similarly, the interrupt vectors are placed just above the reset address, starting at address 00:0003h. It is important to note that first instruction (located at address

0) should not be an EJMP instruction. EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt 0 vector address.

Example Instruction:

MOVC A,@A+PC

PC

3E:97FFh

Accumulator

D3h

+

(3E:98D2h)

Code

Memory

Location

3E:98D2h:

70h

Accumulator

70h

Figure 12: Code Memory Access using Indexed Indirect Addressing with the Program Counter

14 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Example Instruction:

MOVC A,@A+DPTR executed at address 01:59B3

DPS

1

Data Pointers

0 = C340h

1 = FF0Ch

Accumulator

A2h

Upper 7 bits of

Program Counter

(01h)

+

(FFAEh)

01:FFAEh

Code

Memory

Location

01:FFAEh:

C1h

Accumulator

C1h

Figure 13: Code Memory Access using Indexed Indirect Addressing with DPTR

Example Instruction:

MOVC A,@A+EPTR

Code

Memory

EPTR

12:B109h

Accumulator

CDh

+

(12:B1D6h)

Location

12:B1D6h:

55h

Accumulator

55h

Figure 14: Code Memory Access using Indexed Indirect Addressing with EPTR

2.7

UNIVERSAL POINTERS

A new addressing mode called Universal Pointer mode has been added to the 51MX, specifically for the purpose of greatly enhancing C language code density and performance. This addressing mode allows access to any of the on-chip or off-chip code and data spaces using one instruction, without the need to know in advance which of the different spaces the data will reside in.

This includes the DATA, IDATA, EDATA, XDATA, HDATA, and CODE spaces. The SFR space is the only space that may not be accessed using the Universal Pointer mode.

15 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

The Universal Pointer addressing mode uses a new set of pointer registers for two reasons. The first is that 24-bit pointers are needed in order to allow addressing both the 8 MB code space and the 8 MB data space. The other reason is that it is much more efficient to manipulate multi-byte pointer values in registers than it is in SFRs. C compilers typically already perform pointer manipulation in registers, then move the result to a Data Pointer for use.

Two Universal Pointers are supported: PR0 and PR1. The pointer PR0 is composed of registers R1, R2, and R3 of the current

register bank, while PR1 is composed of registers R5, R6, and R7 of the current register bank, as shown in Figure 15.

MSB

R3

PR0

R2

LSB

R1

MSB

R7

PR1

R6

LSB

R5

Figure 15: Universal Pointer Registers

In order to access all of the various memory spaces in a single unified manner, they must all be mapped into a new "view" that allows 16 MB of total memory space. This new view is called the Universal Memory Map.

The XDATA space is placed at the bottom of this new address map. The HDATA space continues above XDATA. The standard internal data memory spaces (DATA and IDATA) are above HDATA, followed by the remainder of the EDATA space. Finally, the code memory occupies the top of the map.

Thus, the most significant bit of the Universal Pointer determines whether code or data memory is accessed. By placing the

XDATA space at the bottom of the Universal Memory Map, Universal Pointer addresses 00:0000 through 00:FFFF can correspond to the classic 80C51 external data memory space. This allows for full backward compatibility for code that does not

need more than 64 KB of external data space. The Universal Memory Map is shown in Figure 16, while the standard view of the

memory spaces and how they relate to Universal Pointer values are shown in Figure 17.

The Universal Pointers are used only by a new 51MX instruction called EMOV. The EMOV instruction allows moving data via one of the Universal Pointers into or out of the accumulator. In either case, a displacement of 0, 1, 2, or 3 may also be specified, which is added to the pointer prior to its use. The displacement allows C compiler access of variables of up to 4 bytes in size (e.g.

Long Integers) without the need to alter the pointer value. An example of Universal Pointer usage is shown in Figure 18. Note

that it is not possible to store a value to the CODE area of the Universal Memory Map.

Another new instruction is added to allow incrementing one of the Universal Pointers by a value from 1 to 4. This allows the pointer to be advanced past the last data element accessed, to the next data element.

16 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Memory Space

CODE

Up to 8 MB on-Chip and/or off-Chip program memory

FF:FFFFh

Addressing Modes

PC, PC relative addressing

DPTR (lower 64 KB of Code)

EPTR

Universal Pointers: PR0, PR1

EDATA

IDATA

DATA

80:0000h

7F:FFFFh

Up to 64 KB - 256 bytes on-chip and/or off-chip data accessed as Stack and via

Universal Pointer only

Upper 128 bytes on-chip indirectly addressed

RAM

7F:0100h

7F:00FFh

7F:0080h

7F:007Fh

Lower 128 bytes on-chip directly & indirectly addressed RAM

7F:0000h

7E:FFFFh

Stack (SPE / SP)

Universal Pointers: PR0, PR1

R0, R1

Stack (SPE / SP)

Universal Pointers: PR0, PR1

Direct addressing

R0, R1 indirect

Stack (SPE / SP)

Universal Pointers: PR0, PR1

HDATA

XDATA

Up to 8 MB - 128 KB data accessed via MOVX

(generally off-chip data)

01:0000h

00:FFFFh

Up to 64 KB on-chip and/or off-chip data accessed via MOVX

00:0000h

Figure 16: Universal Memory Map

R0, R1 (lower 256 bytes on-chip, lower 64 KB

off-chip via use of P2)

DPTR (XDATA access only)

EPTR (HDATA access)

Universal Pointers: PR0, PR1

17 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

16MB

P87C51Mx2 User Manual

P87C51Mx2

CODE

DATA,

IDATA,

EDATA

8MB

HDATA

CODE

HDATA,

XDATA

EDATA

IDATA

DATA

Standard Memory Map

XDATA

0

24-bit Addressing using PR1 and PR2

Figure 17: Mapping of other Addressing Modes to Universal Pointer Addressing

18 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

Example Instruction:

EMOV @PR0+1,A

PR0

12:C340h

Universal

Memory Map

1

+

(12:C341h)

Location

12:C341h:

39h

P87C51Mx2 User Manual

P87C51Mx2

Accumulator

39h

Figure 18: Memory Access using Universal Pointer Addressing

Universal Pointers are designed primarily to facilitate addressing in Extended Addressing Mode, with the EAM bit in MXCON set to one. However, Universal Pointers may still be used when EAM = 0. In this case, Universal Pointer addressing can access only the bottom 64 KB of the Code space, the 64 KB XDATA space, and the 64 KB EDATA space. The Universal Pointer values that point to these areas do not change. When EAM = 0, Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex.

19 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

3 51MX INSTRUCTIONS

The 51MX instruction set is a a true binary-level superset of the classic 80C51, designed to be fully compatible with previously written 80C51 code. The changes to the instruction set are all related to the expanded address space. Some details of existing instructions have been altered, and some instructions have had an extended mode added. In the latter case, the alternate mode of the instruction is activated by preceding the instruction with a special one-byte prefix code, A5h.

An important goal in the implementation of the 51MX was to keep the same timing relationship of existing 80C51 instructions to existing devices. Any 80C51 instruction executed on the 51MX will take the same number of machine cycles to execute.

80C51 Instruction

All relative branches

ACALL addr11

AJMP

JMP @A+DPTR

MOVC A,@A+DPTR

MOVC addr11

A,@A+PC

MOVX @DPTR,A

MOVX A,@DPTR

RET

RETI

LCALL

LJMP addr16 addr16

Effect of Extended Addressing

Includes SJMP and all conditional branches. These instructions may cross a 64 KB boundary if they are located within branch range of the boundary.

This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

The lower 16-bits of the Program Counter are replaced with the value formed by the sum of the

Accumulator and the active DPTR. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

The address formed by replacing the lower 16-bits of the Program Counter with the value formed by the sum of the Accumulator and the active DPTR is used to access code memory. The PC value used is that of the instruction following MOVC.

The sum of the Accumulator and the 23-bit Program Counter forms the 23-bit address used to read the code memory. The PC value used is that of the instruction following MOVC.

The active DPTR points to an address in the 64 KB XDATA memory.

The active DPTR points to an address in the 64 KB XDATA memory.

Replaces the lower 16 bits of the Program Counter with a 16-bit address from the Stack. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

When the extended interrupt frame mode is not enabled, this instruction replaces the lower 16 bits of the Program Counter with a 16-bit address from the Stack. This will cause a 64 KB boundary to be crossed if the instruction is located such that the next instruction in sequence is across the boundary. If the extended interrupt frame mode is enabled, a 23-bit address is loaded into the PC from the stack.

Replaces the lower 16 bits of the Program Counter with the 16-bit address. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

Replaces the lower 16 bits of the Program Counter with the 16-bit address. This instruction will cross a 64 KB boundary if it is located such that the next instruction in sequence is across the boundary.

Table 1: Instructions Affected by Extended Address Space

20 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

80C51 Instruction

LCALL addr16

LJMP

JMP addr16

@A+DPTR

MOVC A,@A+DPTR

MOVX @DPTR,A

MOVX A,@DPTR

INC

MOV DPTR,#data16

RET

ORL

ANL

XRL

DPTR

A,Rn

A,Rn

A,Rn

51MX Effect

Without Prefix

51MX Enhancement

(these instructions use the prefix byte)

51MX Effect with Prefix

Load a 16-bit address into the

Program Counter.

ECALL addr23

Load a 16-bit address into the

Program Counter.

EJMP addr23

The lower 16-bits of the

Program Counter are replaced with the sum of the

Accumulator and the active

DPTR.

JMP @A+EPTR

Logically OR Register n to the

Accumulator.

Logically AND Register n to the

Accumulator.

Exclusive OR Register n to the

Accumulator.

EMOV A,@PRi+disp

EMOV @PRi+disp,A

ADD PRi,#data2

Load a 23-bit address into the Program

Counter.

Load a 23-bit address into the Program

Counter.

The Program Counter is loaded with the value formed by the sum of the Accumulator and the EPTR.

Code memory is accessed using the address formed by replacing the lower 16-bits of the Program Counter with the sum of the Accumulator and the active DPTR.

MOVC A,@A+EPTR

The active DPTR points to an address in the 64 KB XDATA memory.

MOVX @EPTR,A

The active DPTR points to an address in the 64 KB XDATA memory.

MOVX A,@EPTR

Increment the active Data

Pointer.

INC EPTR

Code memory is accessed using the address formed by the sum of the

Accumulator and the EPTR.

The EPTR points to an address anywhere in

HDATA memory (not DATA, IDATA, or

EDATA).

The EPTR points to an address anywhere in

HDATA memory (not DATA, IDATA, or

EDATA).

Increment the 23 bit EPTR.

Load a 16-bit value into the active Data Pointer.

MOV

Load a 16-bit address into the

Program Counter from the

Stack.

ERET

EPTR,#data23 Load a 23-bit value into the EPTR.

Load a 23-bit address into the Program

Counter from the Stack.

Load the Accumulator with the value from the Universal Memory Map at the address formed by PR0 or PR1plus the displacement (a value from 0 to 3).

Load the Universal Memory Map address formed by PR0 or PR1 plus the displacement (a value from 0 to 3) with the contents of the Accumulator.

Add an immediate data value from 1 to 4 to the specified Universal Pointer. This is a 24bit addition.

Table 2: Enhancements to the 80C51 Instruction Set Enabled by the Prefix Byte

21 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

3.1

INSTRUCTION SET SUMMARY

The following table summarizes the entire 51MX instruction set. The instructions are grouped by type, and instructions that share operand formats are combined. 51MX extended instructions and operand combinations are designated by bold text.

Data Movement

MOV

XCH

MOV

A,Rn

A,direct

A,@Ri

A,#data

Rn,A

Rn,direct

Rn,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data

@Ri,A

@Ri,direct

@Ri,#data

DPTR,#data16

EPTR,#data23

MOVC A,@A+DPTR

A,@A+PC

A,@A+EPTR

MOVX A,@Ri

A,@DPTR

@Ri,A

@DPTR,A

A,@EPTR

@EPTR,A

EMOV A,@PRi+disp

@PRi+disp,A

PUSH direct

POP

XCHD A,@Ri

Arithmetic & Logic

DA

CLR

CPL

RL

RLC

RR

RRC

SWAP

ANL

ORL

XRL

ADD A,Rn

ADDC A,direct

SUBB A,@Ri

A,#data

INC

DEC

A

Rn direct

@Ri

INC

ADD

MUL

DIV

DPTR

EPTR

PRi,#data2

AB

A

A,Rn

A,direct

A,@Ri

A,#data direct,A direct,#data

Table 3: 51MX Instruction Set Summary

Program Control

JC

JNC

JZ

JNZ

SJMP

JB

JNB

JBC

JMP rel bit,rel

@A+DPTR

@A+EPTR

CJNE A,direct,rel

A,#data,rel

Rn,#data,rel

@Ri,#data,rel

DJNZ Rn,rel direct,rel

ACALL addr11

AJMP

LCALL addr16

LJMP

EJMP addr23

ECALL

RET

RETI

ERET

NOP

Bit Operations

SETB C

CLR Bit

CPL

ANL

ORL

MOV

C,bit

C,/bit

C,bit bit,C

22 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

3.2

51MX OPERATION CODE CHARTS

This 51MX opcode chart consists of four pages. The first two pages are identical to a classic 80C51 opcode chart except that the

A5h opcode is marked as the MX extended instruction prefix value. The third and fourth pages show instruction encoding that follows the A5h prefix. These instructions are unique to the 51MX, and are divided into several types as shown below.

Contents of Each Table Entry:

opcode bytes/cycles instruction mnemonic operand(s)

51MX Extended Instruction Types:

Unmodified

80C51

Instruction

These instructions are identical to classic 80C51 instructions and thus appear only on the first two pages of the opcode chart.

New MX

Instructions

These instructions are new to the 51MX. All are related to the Universal

Pointers.

Extended

Addressing

Instructions

These instructions incorporate extended addressing, and are modified versions of classic 80C51 instructions.

Extended SFR

Addressing

These instructions allow access to the expanded SFR space. These are not actually new instructions, but are classic 80C51 instructions whose function are altered by the A5h opcode.

Operand Definitions Used in the Tables:

addr11 : 11-bit address addr16 : 16-bit address addr23 : 23-bit address bit : addressable bit dir : direct address rel8 : 8-bit relative address

#d8 : 8-bit immediate data

#d16 : 16-bit immediate data

#d23 : 23-bit immediate data

23 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

00 1/1

NOP

18 1/1

DEC

R0

19 1/1

DEC

R1

1A 1/1

DEC

R2

1B 1/1

DEC

R3

1C 1/1

DEC

R4

1D 1/1

DEC

R5

1E 1/1

DEC

R6

1F 1/1

DEC

R7

10 3/2

JBC bit,rel8

11 2/2

ACALL addr11

12 3/2

LCALL addr16

13 1/1

RRC

A

14 1/1

DEC

A

15 2/1

DEC dir

16 1/1

DEC

@R0

17 1/1

DEC

@R1

09 1/1

INC

R1

0A 1/1

INC

R2

0B 1/1

INC

R3

0C 1/1

INC

R4

0D 1/1

INC

R5

0E 1/1

INC

R6

0F 1/1

INC

R7

01 2/2

AJMP addr11

02 3/2

LJMP addr16

03 1/1

RR

A

04 1/1

INC

A

05 2/1

INC dir

06 1/1

INC

@R0

07 1/1

INC

@R1

08 1/1

INC

R0

20 3/2

JB bit,rel8

21 2/2

AJMP addr11

22 1/2

RET

30 3/2

JNB bit,rel8

31 2/2

ACALL addr11

32 1/2

RETI

23 1/1

RL

A

24 2/1

ADD

A,#d8

25 2/1

ADD

A,dir

26 1/1

ADD

A,@R0

27 1/1

ADD

A,@R1

28 1/1

ADD

A,R0

29 1/1

ADD

A,R1

2A 1/1

ADD

A,R2

2B 1/1

ADD

A,R3

2C 1/1

ADD

A,R4

2D 1/1

ADD

A,R5

2E 1/1

ADD

A,R6

2F 1/1

ADD

A,R7

33 1/1

RLC

A

34 2/1

ADDC

A,#d8

35 2/1

ADDC

A,dir

36 1/1

ADDC

A,@R0

37 1/1

ADDC

A,@R1

38 1/1

ADDC

A,R0

39 1/1

ADDC

A,R1

3A 1/1

ADDC

A,R2

3B 1/1

ADDC

A,R3

3C 1/1

ADDC

A,R4

3D 1/1

ADDC

A,R5

3E 1/1

ADDC

A,R6

3F 1/1

ADDC

A,R7

58 1/1

ANL

A,R0

59 1/1

ANL

A,R1

5A 1/1

ANL

A,R2

5B 1/1

ANL

A,R3

5C 1/1

ANL

A,R4

5D 1/1

ANL

A,R5

5E 1/1

ANL

A,R6

5F 1/1

ANL

A,R7

50 2/2

JNC rel8

51 2/2

ACALL addr11

52 2/1

ANL dir,A

53 3/2

ANL dir,#d8

54 2/1

ANL

A,#d8

55 2/1

ANL

A,dir

56 1/1

ANL

A,@R0

57 1/1

ANL

A,@R1

48 1/1

ORL

A,R0

49 1/1

ORL

A,R1

4A 1/1

ORL

A,R2

4B 1/1

ORL

A,R3

4C 1/1

ORL

A,R4

4D 1/1

ORL

A,R5

4E 1/1

ORL

A,R6

4F 1/1

ORL

A,R7

40 2/2

JC rel8

41 2/2

AJMP addr11

42 2/1

ORL dir,A

43 3/2

ORL dir,#d8

44 2/1

ORL

A,#d8

45 2/1

ORL

A,dir

46 1/1

ORL

A,@R0

47 1/1

ORL

A,@R1

78 2/1

MOV

R0,#d8

79 2/1

MOV

R1,#d8

7A 2/1

MOV

R2,#d8

7B 2/1

MOV

R3,#d8

7C 2/1

MOV

R4,#d8

7D 2/1

MOV

R5,#d8

7E 2/1

MOV

R6,#d8

7F 2/1

MOV

R7,#d8

70 2/2

JNZ rel8

71 2/2

ACALL addr11

72 2/2

ORL

C,bit

73 1/2

JMP

@A+DPTR

74 2/1

MOV

A,#d8

75 3/2

MOV dir,#d8

76 2/1

MOV

@R0,#d8

77 2/1

MOV

@R1,#d8

68 1/1

XRL

A,R0

69 1/1

XRL

A,R1

6A 1/1

XRL

A,R2

6B 1/1

XRL

A,R3

6C 1/1

XRL

A,R4

6D 1/1

XRL

A,R5

6E 1/1

XRL

A,R6

6F 1/1

XRL

A,R7

60 2/2

JZ rel8

61 2/2

AJMP addr11

62 2/1

XRL dir,A

63 3/2

XRL dir,#d8

64 2/1

XRL

A,#d8

65 2/1

XRL

A,dir

66 1/1

XRL

A,@R0

67 1/1

XRL

A,@R1

Table 4: 51MX Operation Code Chart: Part 1

24 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

98 1/1

SUBB

A,R0

99 1/1

SUBB

A,R1

9A 1/1

SUBB

A,R2

9B 1/1

SUBB

A,R3

9C 1/1

SUBB

A,R4

9D 1/1

SUBB

A,R5

9E 1/1

SUBB

A,R6

9F 1/1

SUBB

A,R7

90 3/2

MOV

DPTR,#d16

91 2/2

ACALL addr11

92 2/2

MOV bit,C

93 1/2

MOVC

A,@A+DPTR

94 2/1

SUBB

A,#d8

95 2/1

SUBB

A,dir

96 1/1

SUBB

A,@R0

97 1/1

SUBB

A,@R1

88 2/2

MOV dir,R0

89 2/2

MOV dir,R1

8A 2/2

MOV dir,R2

8B 2/2

MOV dir,R3

8C 2/2

MOV dir,R4

8D 2/2

MOV dir,R5

8E 2/2

MOV dir,R6

8F 2/2

MOV dir,R7

80 2/2

SJMP rel8

81 2/2

AJMP addr11

82 2/2

ANL

C,bit

83 1/2

MOVC

A,@A+PC

84 1/4

DIV

AB

85 3/2

MOV dir,dir

86 2/2

MOV dir,@R0

87 2/2

MOV dir,@R1

A8 2/2

MOV

R0,dir

A9 2/2

MOV

R1,dir

AA 2/2

MOV

R2,dir

AB 2/2

MOV

R3,dir

AC 2/2

MOV

R4,dir

AD 2/2

MOV

R5,dir

AE 2/2

MOV

R6,dir

AF 2/2

MOV

R7,dir

A0 2/2

ORL

C,/bit

A1 2/2

AJMP addr11

A2 2/1

MOV

C,bit

A3 1/2

INC

DPTR

A4 1/4

MUL

AB

A5 -/-

(MX extension prefix)

A6 2/2

MOV

@R0,dir

A7 2/2

MOV

@R1,dir

B0 2/2

ANL

C,/bit

B1 2/2

ACALL addr11

B2 2/1

CPL bit

B3 1/1

CPL

C

B4 3/2

CJNE

A,#d8,rel8

B5 3/2

CJNE

A,dir,rel8

B6 3/2

CJNE

@R0,#d8,rel8

B7 3/2

CJNE

@R1,#d8,rel8

C0 2/2

PUSH dir

C1 2/2

AJMP addr11

C2 2/1

CLR bit

C3 1/1

CLR

C

C4 1/1

SWAP

A

C5 2/1

XCH

A,dir

C6 1/1

XCH

A,@R0

C7 1/1

XCH

A,@R1

B8 3/2

CJNE

R0,#d8,rel8

B9 3/2

CJNE

R1,#d8,rel8

BA 3/2

CJNE

R2,#d8,rel8

BB 3/2

CJNE

R3,#d8,rel8

C8 1/1

XCH

A,R0

C9 1/1

XCH

A,R1

CA 1/1

XCH

A,R2

CB 1/1

XCH

A,R3

D8 2/2

DJNZ

R0,rel8

D9 2/2

DJNZ

R1,rel8

DA 2/2

DJNZ

R2,rel8

DB 2/2

DJNZ

R3,rel8

BC 3/2

CJNE

R4,#d8,rel8

BD 3/2

CJNE

R5,#d8,rel8

CC 1/1

XCH

A,R4

CD 1/1

XCH

A,R5

DC 2/2

DJNZ

R4,rel8

DD 2/2

DJNZ

R5,rel8

BE 3/2

CJNE

R6,#d8,rel8

BF 3/2

CJNE

R7,#d8,rel8

CE 1/1

XCH

A,R6

CF 1/1

XCH

A,R7

DE 2/2

DJNZ

R6,rel8

DF 2/2

DJNZ

R7,rel8

D0 2/2

POP dir

D1 2/2

ACALL addr11

D2 2/1

SETB bit

D3 1/1

SETB

C

D4 1/1

DA

A

D5 3/2

DJNZ dir,rel8

D6 1/1

XCHD

A,@R0

D7 1/1

XCHD

A,@R1

E8 1/1

MOV

A,R0

E9 1/1

MOV

A,R1

EA 1/1

MOV

A,R2

EB 1/1

MOV

A,R3

EC 1/1

MOV

A,R4

ED 1/1

MOV

A,R5

EE 1/1

MOV

A,R6

EF 1/1

MOV

A,R7

E0 1/2

MOVX

A,@DPTR

E1 2/2

AJMP addr11

E2 1/2

MOVX

A,@R0

E3 1/2

MOVX

A,@R1

E4 1/1

CLR

A

E5 2/1

MOV

A,dir

E6 1/1

MOV

A,@R0

E7 1/1

MOV

A,@R1

F8 1/1

MOV

R0,A

F9 1/1

MOV

R1,A

FA 1/1

MOV

R2,A

FB 1/1

MOV

R3,A

FC 1/1

MOV

R4,A

FD 1/1

MOV

R5,A

FE 1/1

MOV

R6,A

FF 1/1

MOV

R7,A

F0 1/2

MOVX

@DPTR,A

F1 2/2

ACALL addr11

F2 1/2

MOVX

@R0,A

F3 1/2

MOVX

@R1,A

F4 1/1

CPL

A

F5 2/1

MOV dir,A

F6 1/1

MOV

@R0,A

F7 1/1

MOV

@R1,A

Table 5: 51MX Operation Code Chart: Part 2

25 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

10 4/3

JBC bit,rel8

20 4/3

JB bit,rel8

30 4/3

JNB bit,rel8

P87C51Mx2 User Manual

P87C51Mx2

02 5/4

EJMP addr23

12 5/4

ECALL addr23

22 2/4

ERET

42 3/2

ORL dir,A

43 4/3

ORL dir,#d8

52 3/2

ANL dir,A

53 4/3

ANL dir,#d8

62 3/2

XRL dir,A

63 4/3

XRL dir,#d8

72 3/3

ORL

C,bit

73 2/2

JMP

@A+EPTR

05 3/2

INC dir

15 3/2

DEC dir

25 3/2

ADD

A,dir

35 3/2

ADDC

A,dir

45 3/2

ORL

A,dir

55 3/2

ANL

A,dir

65 3/2

XRL

A,dir

75 4/3

MOV dir,#d8

48 2/4

EMOV

A,@PR0+0

49 2/4

EMOV

A,@PR0+1

4A 2/4

EMOV

A,@PR0+2

4B 2/4

EMOV

A,@PR0+3

4C 2/4

EMOV

A,@PR1+0

4D 2/4

EMOV

A,@PR1+1

4E 2/4

EMOV

A,@PR1+2

4F 2/4

EMOV

A,@PR1+3

58 2/4

EMOV

@PR0+0,A

59 2/4

EMOV

@PR0+1,A

5A 2/4

EMOV

@PR0+2,A

5B 2/4

EMOV

@PR0+3,A

5C 2/4

EMOV

@PR1+0,A

5D 2/4

EMOV

@PR1+1,A

5E 2/4

EMOV

@PR1+2,A

5F 2/4

EMOV

@PR1+3,A

68 2/4

ADD

PR0,#4

69 2/4

ADD

PR0,#1

6A 2/4

ADD

PR0,#2

6B 2/4

ADD

PR0,#3

6C 2/4

ADD

PR1,#4

6D 2/4

ADD

PR1,#1

6E 2/4

ADD

PR1,#2

6F 2/4

ADD

PR1,#3

Table 6: 51MX Operation Code Chart: Part 3

26 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

90 5/4

MOV

EPTR,#d23

A0 3/3

ORL

C,/bit

B0 3/3

ANL

C,/bit

C0 3/3

PUSH dir

D0 3/3

POP dir

E0 2/4

MOVX

A,@EPTR

F0 2/4

MOVX

@EPTR,A

82 3/3

ANL

C,bit

92 3/3

MOV bit,C

93 2/4

MOVC

A,@A+EPTR

A2 3/2

MOV

C,bit

A3 2/2

INC

EPTR

B2 3/2

CPL bit

C2 3/2

CLR bit

D2 3/2

SETB bit

85 4/3

MOV dir,dir

86 3/3

MOV dir,@R0

87 3/3

MOV dir,@R1

88 3/3

MOV dir,R0

89 3/3

MOV dir,R1

8A 3/3

MOV dir,R2

8B 3/3

MOV dir,R3

8C 3/3

MOV dir,R4

8D 3/3

MOV dir,R5

8E 3/3

MOV dir,R6

8F 3/3

MOV dir,R7

95 3/2

SUBB

A,dir

A6 3/3

MOV

@R0,dir

A7 3/3

MOV

@R1,dir

A8 3/3

MOV

R0,dir

A9 3/3

MOV

R1,dir

AA 3/3

MOV

R2,dir

AB 3/3

MOV

R3,dir

AC 3/3

MOV

R4,dir

AD 3/3

MOV

R5,dir

AE 3/3

MOV

R6,dir

AF 3/3

MOV

R7,dir

B5 4/3

CJNE

A,dir,rel8

C5 3/2

XCH

A,dir

D5 4/3

DJNZ dir,rel8

E5 3/2

MOV

A,dir

F5 3/2

MOV dir,A

Table 7: 51MX Operation Code Chart: Part 4

27 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

4 EXTERNAL BUS

The external bus provides address information to external devices, and initiates code read, data read, or data write operations.

In 51MX devices, the external bus duplicates the classic 80C51 multiplexed external bus, but allows increasing the address output to 23 bits.

4.1

MULTIPLEXED EXTERNAL BUS

The 51MX external bus supports 8-bit data transfers and up to 23 address lines. The number of address lines available is configurable, and depends on the setting of the EAM bit in the MXCON register.

The default for an unprogrammed part following reset is 16 address bits. This provides drop-in compatibility in existing 80C51 sockets. A non-volatile configuration bit allows pre-selecting a 23-bit address size at the time that the part is programmed.

Software may later enable the extended addressing mode even if the pre-programmed configuration does not.

The non-volatile address configuration is implemented using EPROM technology. The configuration is comprised of a single bit that enables multiplexing of the 7 extended address bits on Port 2. If the non-volatile configuration bit is not programmed, extended addressing may be enabled at run time via the EAM bit in the MXCON SFR. Software may write a 1 to MXCON, changing the default configuration. Typically, this would be done a single time. If software reads the EAM bit in MXCON, the value will be the logical OR of the non-volatile configuration bit and the MXCON.EAM bit value. It is not recommended to change the address configuration dynamically during program execution (for example: changing EAM=1 to EAM=0 changes external memory bus interface and prevents core from executing code above the 64 KB boundary). The encoding of the configuration bit is such that an unprogrammed device is configured for 16 address lines.

When the full 23-bit address is multiplexed on Port 2 (when the EAM bit in MXCON = 1), the high order address information (bits

A22 through A16) must be latched externally in the same manner as the low order bits (A7 through A0) on Port 0. The middle address bits (A15 through A8) appear on Port 2 after ALE goes low. If extended addressing is not enabled, Port 2 behaves just

as on a classic 80C51. An example of Port 2 address multiplexing is shown in Figure 19.

There are two special cases for Port 2 multiplexing when extended addressing is enabled: MOVX @Ri and MOVX @DPTR.

These instructions do not supply a source for a full 23-bit external address. Where program memory is involved (jumps and

MOVC), any "missing" address bits are supplied by the Program Counter (see Table 1). For MOVX, the additional bits are forced

to zeroes to complete the address. So, MOVX @Ri will output a 23-bit address composed of seven zeroes for the upper address,

Port 2 SFR contents for the middle byte of the address, and Ri contents for the bottom byte. Similarly, MOVX @DPTR will output a 23-bit address composed of seven zeroes for the upper address and the current DPTR contents for the middle and bottom bytes of the address.

If we have a single-chip application with code exceeding 64 KB (and thus having EAM=1) and if an old 51 bus interface has to be preserved, instead of using MOVX @Ri,A the instruction EMOV @PRi,A should be used. If we load the content of P2 sfr to

R3 and R2, execution of instruction EMOV @PR0,A will have exactly the same output in a system with EAM=1 as it is in case of

MOVX @R0,A in a design with standard 51bus interface.

Some 51MX applications may use extended addressing and rely on software setting the EAM bit in MXCON (i.e. the non-volatile address configuration bit is not programmed). If such an application is set up such that the first code executed upon reset is offchip, then the instruction that sets the EAM bit in MXCON must be located at or below address 00FBh. This is to prevent the external bus from supplying a 16-bit address when a 23-bit address is required. If the Program Counter were to reach address

0100h while EAM = 0, the apparent address (to external hardware that is expecting a 23-bit address) would become 01:0100.

28 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

S1 S2 S3 S4 S5 S6 S1 S2

ALE

P2

P0

PSEN high address low address middle address instruction data in high address low address middle address instruction data in low address

Figure 19: Example of External Code Memory Read Cycles using 23 Address Bits

The standard control signals and their functions for the external bus are as follows:

Signal name

ALE

PSEN

RD

WR

Function

Address Latch Enable. This signal directs an external address latch to store the multiplexed portion of the address for the next bus operation. This may be either a data address or a code address.

Program Store Enable. Indicates that the processor is reading code from the bus. Typically connected to the

Output Enable pin of external EPROMs or other memory devices. External bus addresses for code memory may range from 00:0000 through 7F:FFFF. In the Universal Memory Map, these correspond to addresses

80:0000 through FF:FFFF

Read. The external data read strobe. Typically connected to the RD pin of external peripheral devices.

Write. The write strobe for external data. Typically connected to the WR pin of external peripheral devices.

External bus addresses for data memory may range from 00:0000 through 7E:FFFF, which matches Universal Memory Map addresses. If on-chip XDATA is enabled, it will cause an addressing discontinuity in the external data address space. The DATA and IDATA spaces are always on-chip, and therefore always create such an addressing discontinuity.

29 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

5 INTERRUPT PROCESSING

The P87C51Mx2 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P87C51Mx2 has ten interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts at once.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the IP0, IP0H,

IP1, and IP1H registers. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source.

So, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level.

Table 8 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, and whether each

interrupt may wake up the CPU from Power Down mode.

Description

External Interrupt 0

Timer 0 Interrupt

External Interrupt 1

Interrupt

Flag Bit(s)

IE0

TF0

IE1

Vector

Address

0003h

000Bh

0013h

Interrupt

Enable Bit(s)

EX0 (IEN0.0)

ET0 (IEN0.1)

EX1 (IEN0.2)

Interrupt

Priority

IP0H.0, IP0.0

IP0H.1, IP0.1

IP0H.2, IP0.2

Polling

Priority

1 (highest)

2

3

Power Down

Wakeup

Yes

No

Yes

Timer 1 Interrupt

Serial Port 0 Tx and Rx

1,5

Serial Port 0 Rx

1

Timer 2 Interrupt

TF1

TI_0 & RI_0

5

001Bh

0023h

ET1 (IEN0.3)

ES0(IEN0.4)

IP0H.3, IP0.3

IP0H.4, IP0.4

4

6

No

No

RI_0

TF2, EXF2 002Bh ET2 (IEN0.5) IP0H.5, IP0.5

7 No

PCA interrupt

Serial Port 1 Tx and Rx

2,6

Serial Port 1 Rx

2

Serial Port 0 Tx

3

Serial Port 1 Tx

4

CF, CCFn*

TI_1 & RI_1

RI_1

TI_0

6

0033h

0053h

003Bh

EC (IEN0.6)

ES1 (IEN1.0)

EI10 (IEN1.1)

IP0H.6, IP0.6

IP1H.0, IP1.0

IP1H.1, IP1.1

5

10 (lowest)

8

No

No

No

TI_1 0043h EI11 (IEN1.2) IP1H.2, IP1.2

9 No

1. S0STAT.5 = 0 selects combined Serial Port 0 Tx and Rx interrupt; S0STAT.5 = 1 selects Serial Port 0 Rx interrupt only (and

TX interrupt will be different, see Note 3 below).

2. S1STAT.5 = 0 selects combined Serial Port 1 Tx and Rx interrupt; S1STAT.5 = 1 selects Serial Port 1 Rx interrupt only (and

TX interrupt will be different, see Note 4 below).

3. This interrupt is used as Serial Port 0 Tx interrupt if and only if S0STAT.5 = 1, and is disabled otherwise.

4. This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT.5 = 1, and is disabled otherwise.

5. If S0STAT.0 = 1, the following Serial Port 0 additional flag bits can cause this interrupt: FE_0, BR_0, OE_0.

6. If S1STAT.0 = 1, the following Serial Port 1 additional flag bits can cause this interrupt: FE_1, BR_1, OE_1.

Table 8: Summary of Interrupts

30 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

IEN0

Address: A8h

Bit addressable

Reset Value: 00h

BIT

IEN0.7

IEN0.6

IEN0.5

IEN0.4

IEN0.3

IEN0.2

IEN0.1

IEN0.0

SYMBOL

EA

EC

ET2

ES0/ES0R

ET1

EX1

ET0

EX0

7

EA

6

EC

5

ET2

4

ES0/ES0R

3

ET1

2

EX1

1

ET0

0

EX0

FUNCTION

Interrupt Enable Bit.

PCA Interrupt Enable bit.

Timer 2 Interrupt Enable.

Serial Port 0 Combined Interrupt Enable (S0STAT.5 = 0)/Serial Port 0 Receive Interrupt

Enable (S0STAT.5 = 1).

Timer1 Overflow Interrupt Enable.

External Interrupt 1 Enable.

Timer 0 Overflow Interrupt Enable.

External Interrupt 0 Enable.

Figure 20: Interrupt Enable Register IEN0

IEN1

Address: E8h

Bit addressable

Reset Value: 00h

BIT

IEN1.7-3

IEN1.2

IEN1.1

IEN1.0

SYMBOL

-

ES1T

ES0T

ES1/ES1R

7

-

6

-

5

-

4

-

3

-

2

ES1T

1

ES0T

0

ES1/ES1R

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

If S1STAT.5 = 1, it is Serial Port 1 Transmit Interrupt Enable. If S1STAT.5 = 0, this interrupt is disabled anyway.

If S0STAT.5 = 1, it is Serial Port 0 Transmit Interrupt Enable. If S0STAT.5 = 0, this interrupt is disabled anyway.

Serial Port 1 Combined Interrupt Enable (S1STAT.5 = 0)/Serial Port 1 Receive Interrupt

Enable (S1STAT.5 = 1).

Figure 21: Interrupt Enable Register IEN1

31 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

IP0

Address: B8h

Bit addressable

Reset Value: 00h

BIT

IP0.7

IP0.6

IP0.5

IP0.4

IP0.3

IP0.2

IP0.1

IP0.0

SYMBOL

-

PPC

PT2

PS0/PS0R

PT1

PX1

PT0

PX0

7

-

6

PPC

5

PT2

4

PS0/PS0R

3

PT1

2

PX1

1

PT0

0

PX0

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

PCA Interrupt Priority bit Low Bit.

Timer 2 Interrupt Priority Low Bit.

Serial Port 0 Combined Interrupt (S0STAT.5 = 0)/Receive Interrupt (S0STAT.5 = 1)

Priority Low Bit.

Timer 1 Interrupt Priority Low Bit.

External Interrupt 1 Priority Low Bit.

Timer 0 Interrupt Priority Low Bit.

External Interrupt 0 Priority Low Bit.

Figure 22: Interrupt Priority Register IP0

IP0H

Address: B7H

Not bit addressable

Reset Value: 00h

BIT

IP0H.7

IP0H.6

IP0H.5

IP0H.4

IP0H.3

IP0H.2

IP0H.1

IP0H.0

7

-

6

PPCH

5

PT2H

4

PS0H/PS0RH

3

PT1H

2

PX1H

1

PT0H

0

PX0H

SYMBOL

-

PPCH

PT2H

PS0H/PS0RH

PT1H

PX1H

PT0H

PX0H

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

PCA Interrupt Priority bit High Bit.

Timer 2 Interrupt Priority High Bit.

Serial Port 0 Combined Interrupt (S0STAT.5 = 0)/Receive Interrupt (S0STAT.5 = 1)

Priority High Bit.

Timer 1 Interrupt Priority High Bit.

External Interrupt 1 Priority High Bit.

Timer 0 Interrupt Priority High Bit.

External Interrupt 0 Priority High Bit.

Figure 23: Interrupt Priority High Byte IP0H

32 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

IP1

Address: F8H

Bit addressable

Reset Value: 00h

BIT

IP1.7-3

IP1.2

IP1.1

IP1.0

SYMBOL

-

PS1T

PS0T

PS1/PS1R

7

-

6

-

5

-

4

-

3

-

2

PS1T

1

PS0T

0

PS1/PS1R

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

Serial Port 1 transmit Interrupt (S1STAT.5 = 1) Priority Low Bit.

Serial Port 0 transmit Interrupt (S0STAT.5 = 1) Priority Low Bit.

Serial Port 1 combined Interrupt (S1STAT.5 = 0)/receive Interrupt (S1STAT.5 = 1) Priority

Low Bit.

Figure 24: Interrupt Priority Register 1

IP1H

Address: F7H

Not bit addressable

Reset Value: 00h

BIT

IP1H.7-3

IP1H.2

IP1H.1

IP1H.0

SYMBOL

-

PS1TH

PS0TH

PS1H/PS1RH

7

-

6

-

5

-

4

-

3

-

2

PS1TH

1

PS0TH

0

PS1H/PS1RH

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

Serial Port 1 transmit Interrupt (S1STAT.5 = 1) Priority High Bit.

Serial Port 0 transmit Interrupt (S0STAT.5 = 1) Priority High Bit.

Serial Port 1 combined Interrupt (S1STAT.5 = 0)/receive Interrupt (S1STAT.5 = 1) Priority

High Bit.

Figure 25: Interrupt Priority Register 1 High Byte

33 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

6 P87C51MX2 PORTS, POWER CONTROL AND

PERIPHERALS

P87C51Mx2 User Manual

P87C51Mx2

6.1

SPECIAL FUNCTION REGISTERS

Note: Special Function Registers (SFRs) accesses are restricted in the following ways:

1. User must NOT attempt to access any SFR locations not defined.

2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

3. SFR bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:

- ’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.

- ’0’ MUST be written with ’0’, and will return a ’0’ when read.

- ’1’ MUST be written with ’1’, and will return a ’1’ when read.

Special Function Registers

SYMBOL DESCRIPTION

DIRECT

ADDRESS

MSB

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

LSB

Reset

Value

E7 E6 E5 E4 E3 E2 E1 E0

ACC* Accumulator

AUXR# Auxiliary Function Register

AUXR1# Auxiliary Function Register 1

E0H

8EH

A2H -

-

-

-

-

-

LPEP

-

GF2

-

0

EXTRAM AO

DPS

00H

00H

%

00H

%

F7 F6 F5 F4 F3 F2 F1 F0

B* B Register F0H 00H

BRGR0#§ Baud Rate Generator Rate Low

BRGR1#§ Baud Rate Generator Rate High

BRGCON# Baud Rate Generator Control

86H

87H

BRATE11 BRATE10 BRATE9 BRATE8 BRATE7 BRATE6 BRATE5 BRATE4

BRATE3 BRATE2 BRATE1 BRATE0 -

00H

00H

85H

S0BRGS BRGEN 00H

%

CCAP0H# Module 0 Capture High

CCAP1H# Module 1 Capture High

CCAP2H# Module 2 Capture High

CCAP3H# Module 3 Capture High

CCAP4H# Module 4 Capture High

CCAP0L# Module 0 Capture Low

CCAP1L# Module 1 Capture Low

CCAP2L# Module 2 Capture Low

CCAP3L# Module 3 Capture Low

CCAP4L# Module 4 Capture Low

CCAPM0# Module 0 Mode

CCAPM1# Module 1 Mode

CCAPM2# Module 2 Mode

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

DAH

DBH

DCH

-

-

-

ECOM_0 CAPP_0 CAPN_0 MAT_0

ECOM_1 CAPP_1 CAPN_1 MAT_1

ECOM_2 CAPP_2 CAPN_2 MAT_2

TOG_0

TOG_1

TOG_2

PWM_0 ECCF_0

PWM_1 ECCF_1

PWM_2 ECCF_2

XXH

XXH

XXH

XXH

XXH

XXH

XXH

XXH

XXH

XXH

00H

%

00H

%

00H

%

34 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Special Function Registers (Continued)

SYMBOL DESCRIPTION

DIRECT

ADDRESS

MSB

CCAPM3# Module 3 Mode

CCAPM4# Module 4 Mode

DDH

DEH -

-

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

Reset

Value

LSB

ECOM_3 CAPP_3 CAPN_3 MAT_3

ECOM_4 CAPP_4 CAPN_4 MAT_4

TOG_3

TOG_4

PWM_3 ECCF_3

PWM_4 ECCF_4

00H

%

00H

%

CCON#

CH#

CL#

CMOD#

PCA Counter Control

PCA Counter High

PCA Counter Low

PCA Counter Mode

DPTR

DPH

DPL

EPL#

EPM#

EPH#

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

Extended Data Pointer Low

Extended Data Pointer Middle

Extended Data Pointer High

IEN0*

IEN1*

IP0*

IP0H

IP1*

IP1H

MXCON#

P0*

Interrupt Enable 0

Interrupt Enable 1

Interrupt Priority

Interrupt Priority 0 High

Interrupt Priority 1

Interrupt Priority 1 High

MX Control Register

Port 0

D8H

F9H

E9H

D9H

83H

82H

FCH

FDH

FEH

A8H

E8H

B8H

B7H

F8H

F7H

FFH

80H

-

87

AD7

DF

CF

CIDL

AF

EA

EF

FF

-

-

BF

-

-

-

DE

CR

WDTE

DD

-

-

DC

CCF4

DB

CCF3

-

DA

CCF2

D9

CCF1

CPS1 CPS0

D8

CCF0

ECF

00H

%

00H

00H

00H

%

00H

00H

00H

00H

00H

00H

AE

EC

EE

-

-

-

86

AD6

AD

ET2

ED

-

-

-

85

AD5

AC

ES0/

ES0R

EC

-

-

-

84

AD4

AB

ET1

EB

-

AA

EX1

A9

ET0

A8

EX0 00H

EA

ES1T

E9

ES0T

E8

ES1/

ES1R

00H

%

BE

PPC

FE

-

BD

PT2

FD

-

BC

PS0/

PS0R

FC

-

BB

PT1

FB

-

BA

PX1

FA

PS1T

B9

PT0

F9

PS0T

B8

PX0

PPCH PT2H

PS0H/

PS0RH

PT1H PX1H PT0H PX0H

F8

PS1/

PS1R

00H

00H

00H

%

-

-

83

AD3

PS1TH PS0TH

PS1H/

PS1RH

00H

%

EAM ESMM EIFM

00H

%

82

AD2

81

AD1

80

AD0 FFH

35 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Special Function Registers (Continued)

SYMBOL DESCRIPTION

DIRECT

ADDRESS

MSB

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

P1* Port 1 90H

97

CEX4

96

CEX3

95

CEX2

94

CEX1

93

CEX0

92

ECI

91

T2EX

LSB

Reset

Value

90

T2 FFH

P2*

TCON*

Port 2

Timer Control Register

A0H

P3*

P4*#

Port 3

Port 4

B0H

C0H

B7

RD

C7

-

B6

WR

C6

-

B5

T1

C5

-

B4

T0

C4

-

B3

INT1

C3

-

B2

INT0

C2

-

B1

TxD0

C1

TxD1

B0

RxD0

C0

RxD1

FFH

FFH

PCON# Power Control Register 87H SMOD1 SMOD0

D7

CY

D6

AC

-

D5

F0

POF

D4

RS1

GF1

D3

RS0 PSW* Program Status Word

RCAP2H# Timer2 Capture High

RCAP2L# Timer2 Capture Low

D0H

CBH

CAH

S0CON* Serial Port 0 Control

S0BUF

S0ADDR

Serial Port 0 Data Buffer Register

Serial Port 0 Address Register

S0ADEN Serial Port 0 Address Enable

S0STAT# Serial Port 0 Status

98H

99H

A9H

B9H

8CH

9F

SM0_0/

FE_0

9E

SM1_0

9D

SM2_0

9C

REN_0

9B

TB8_0

DBMOD_

0

INTLO_0 CIDIS_0 DBISEL_0 FE_0

GF0

D2

OV

9A

RB8_0

BR_0

PD

D1

F1

99

TI_0

OE_0

IDL

D0

P

00H/10H

00H

00H

00H

98

RI_0

STINT_0

00H xxH

00H

00H

00H

%

&

S1CON#* Serial Port 1 Control

S1BUF# Serial Port 1 Data buffer Register

S1ADDR# Serial Port 1 Address Register

S1ADEN# Serial Port 1 Address Enable

S1STAT# Serial Port 1 Status

80H

81H

82H

83H

84H

87

SM0_1/

FE_1

86

SM1_1

85

SM2_1

84

REN_1

DBMOD_

1

INTLO_1 CIDIS_1 DBISEL1

83

TB8_1

FE_1

82

RB8_1

BR_1

81

TI_1

OE_1

80

RI_1

STINT_1

00H

XXH

00H

00H

00H

%

SP

SPE#

Stack Pointer (or Stack Pointer

Low Byte When EDATA

Supported)

Stack Pointer High

81H

FBH

00H

88H

A7

AD15

A6

AD14/

AD22

A5

ADA13/

AD21

A4

AD12/AD20

A3

AD11/

AD19

A2

AD10/

AD18

A1

AD9/

AD17

A0

AD8/

AD16

8F

TF1

8E

TR1

8D

TF0

8C

TR0

8B

IE1

8A

IT1

89

IE0

88

IT0

FFH

00H

36 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Special Function Registers (Continued)

SYMBOL DESCRIPTION

DIRECT

ADDRESS

MSB

BIT ADDRESS, SYMBOL, OR ALTERNATE PORT FUNCTION

LSB

Reset

Value

T2CON#* Timer2 Control Register

T2MOD# Timer2 Mode Control

TH0

TH1

TH2

TL0

TL1

TL2

Timer 0 High

Timer 1 High

Timer 2 High

Timer 0 Low

Timer 1 Low

Timer 2 Low

TMOD Timer 0 and 1 Mode

WDTRST# Watchdog Timer Reset

WDCON# Watchdog Timer Control

C8H

C9H

A6H

8FH

CF

TF2

-

8CH

8DH

CDH

8AH

8BH

CCH

89H GATE C/T

-

CE

EXF2

-

-

CD

RCLK

-

M1

-

CC

TCLK

-

CB

EXEN2

-

M0

-

CA

TR2

-

C9

C/T2

T2OE

C8

CP/RL2

DCEN

00H

00H

%

GATE

-

C/T M1 M0

FFH

WDPRE2 WDPRE1 WDPRE0 00H

%

00H

00H

00H

00H

00H

00H

00H

Notes:

* SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

‡ Extended SFRs accessed by preceeding the instruction with MX escape (opcode A5h).

Reserved bits, must be written with 0’s.

& Power on reset is 10H. Other reset is 00H.

% The unimplemented bits (labeled ’-’) in the SFRs are ’X’s (unknown) at all times. ’1’s should NOT be written to these bits, as they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are unknown when read.

% The unimplemented bits (labeled ’-’) in the SFRs are ’X’s (unknown) at all times. ’1’s should NOT be written to these bits, as they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are unknown when read.

6.2

P87C51MX2 PORTS

6.2.1

PORTS 0, 1, 2, 3

Ports 0, 1, 2, 3 are the same as the ports in a conventional 80C51 device. They are located at the same bit-addressable locations of 80H, 90H, A0H, and B0H in the conventional SFR space.

6.2.2

PORT 4

The P87C51Mx2 has an additional port called Port 4. This port is currently not available as general purpose I/O.

The table below shows function of Port 4:

37 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P4.0

RXD1

P4.1

TXD1

Serial input port 1 (with pull-up)

Serial output port 1 (with pull-up)

P87C51Mx2 User Manual

P87C51Mx2

6.3

P87C51MX2 LOW POWER MODES

6.3.1

STOP CLOCK MODE

The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.

6.3.2

IDLE MODE

In the idle mode (see Table 9), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to

invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

Idle mode is entered by setting the IDL bit in the PCON register.

6.3.3

POWER-DOWN MODE

To save even more power, a Power Down mode (see Table 9) can be invoked by software. In this mode, the oscillator is stopped

and the instruction that invoked Power Down is the last instruction executed.

The Power Down mode stops the oscillator in order to absolutely minimize power consumption. Power Down mode is entered by setting the PD bit in the PCON register.

The processor can be made to exit Power Down mode via Reset or one of the external interrupt inputs (INT0, INT1 - configured to be level sensitive only). This will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress.

While having the MX part in Power Down Mode and driving Reset high (or external interrupt line low), the oscillator dedicated analog subsystem inside of microcontroller will be enabled. However, only when the wake-up pulse on reset/external interrupt line is ended, the rest of microcontroller will be supplied with the system clock, and continue to operate. The duration of an input pulse on reset/external interrupt pin in order to wake the part from Power Down Mode depends solely on external oscillator’s circuit components. At the end of wake-up procedure, reset/external interrupt line can be brought to non-active level as soon as input at XTAL1 pin achieves stable frequency, duty cycle and amplitude. If an external interrupt caused the part to wake up, execution of forced jump (that directs code execution to the proper interrupt service routine) will end Power Down Mode.

By exiting Power Down mode via external interrupt, the core automatically clears the PD bit and thus enables a new entry into

Power Down Mode. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down Mode.

In Power Down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V

RAM

. This retains the RAM contents at the point where Power Down mode was entered. SFR contents are not guaranteed after V

DD

has been lowered to

V

RAM

, therefore it is recommended to wake up the processor via Reset in this case (since Reset redefines all SFRs - including

PD bit, but doesn’t change on-chip RAM). V

DD

must be raised to within the operating range before the Power Down mode is exited.

38 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

MODE

Idle

Idle

Power Down

Power Down

Program Memory

Internal

External

Internal

External

ALE

1

1

0

0

PSEN

1

1

0

0

PORT 0

Data

Float

Data

Float

PORT 1

Data

Data

Data

Data

Table 9: External Pin Status During Idle and Power Down Modes

PORT 2

Data

Address

Data

Data

PORT 3

Data

Data

Data

Data

PCON

-

*

Reset Value

Power Control Register

7

SMOD1

0

6

SMOD0

0

5

-

-

4

POF

*

3

GF1

0

2

GF0

0

1

PD

0

0

IDL

0

-Reset Value: 000*0000B

(* See description below for PCON.4 reset value)

BIT SYMBOL FUNCTION

PCON.7

SMOD1 Baud Rate Control bit for serial port (UART). When 0, the baud rate for UART is the input rate (T1 timer or baud rate generator, as determined by the BRGCON extended SFR) divided by two. When 1, the baud rate for UART is the input rate (T1 timer or baud rate generator).

PCON.6

SMOD0 Framing Error Location:

When 0, bit 7 of SCON functions as SM0 for the UART.

When 1, bit 7 of SCON is the framing error status for the UART.

This bit also determines the location of the UART reception interrupt RI occurs (see

description on RI in Figure 43).

Reserved for future use. Should be set to 0 by user programs.

PCON.5

PCON.4

PCON.3

-

POF

GF1

PCON.2

PCON.1

PCON.0

GF0

PD

IDL

Power On Flag. (Reset value = 1 for power-on reset only.)

General purpose flag 1. May be read or written by user software, but has no effect on operation.

General purpose flag 0. May be read or written by user software, but has no effect on operation.

Power Down control bit. Setting this bit activates Power Down mode operation. Cleared when the Power Down mode is terminated (see text).

Idle mode control bit. Setting this bit activates Idle mode operation. Cleared when the Idle mode is terminated (see text).

Figure 26: Power Control Register (PCON)

39 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.3.4

POWER-ON FLAG

The Power On Flag (POF) is set by on-chip circuitry when the V

DD

level on the P87C51Mx2 rises from 0V. The POF bit has to be cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown.

6.3.5

DESIGN CONSIDERATION

When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

6.3.6

ONCE™ MODE

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

6.3.7

LOW POWER EPROM OPERATION (LPEP)

Microcontroller contains some analog circuits that are not required when V

CC

is less than 3.6 V, but are required for a V

CC

greater than 3.6 V. The LPEP bit (AUXR.4), when set, will powerdown these analog circuits resulting in a reduced supply current. This bit should be set ONLY for applications that operate at a V

CC

less than 3.6 V.

If LPEP=1 with V

CC

greater than 3.6 V, readings from internal RAM will be invalid and the part itself can be damaged.

6.4

TIMERS/COUNTERS 0 AND 1

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see

Figure 27).

In the "Timer" function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles.

Since a machine cycle consists of 6 oscillator periods, the count rate is 1/6 of the oscillator frequency.

In the "Counter" function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register in the machine cycle following the one in which the transition was detected. Since it takes 2 machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full cycle. In addition to the "Timer" or "Counter" selection, Timer 0 and Timer 1 have four operating modes from which to select.

The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/

Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both

Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.

40 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

TMOD

Address: 89h

Not bit addressable

Reset Source(s): Any source

Reset Value: 00000000B

T1/T0

GATE

M1

0

0

1

1

C/T

M0

0

1

0

1

7

T1GATE

6

T1C/T

5

T1M1

4

T1M0

3

T0GATE

2

T0C/T

1

T0M1

0

T0M0

Bits controling Timer1/Timer0

Gating control when set. Timer/Counter “x” is enabled only while “INTx” pin is high and

“TRx” control pin is set. when cleared Timer “x” is enabled whenever “TRx” control bit is set.

Gating Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from “Tx” input pin).

OPERATING

8048 Timer “TLx” serves as 5-bit prescaler.

16-bit Timer/Counter “THx” and “TLx” are cascaded; there is no prescaler.

8-bit auto-reload Timer/Counter “THx” holds a value which is to be reloaded into “TLx” each time it overflows.

(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

(Timer 1) Timer/Counter 1 stopped.

Figure 27: Timer/Counter Mode Control Register (TMOD)

6.4.1

MODE 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure

29 shows Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special

Function Register TCON (Figure 28). The GATE bit is in the TMOD register.

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 29). There are two different GATE bits, one for Timer 1

(TMOD.7) and one for Timer 0 (TMOD.3).

6.4.2

MODE 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 30.

6.4.3

MODE 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 31. Overflow from TLn

not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

41 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.4.4

MODE 3

When Timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure

32. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, an P87C51MB2/MC2 can look like it has an additional Timer.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

TCON

Address: 88h

Bit addressable

Reset Source(s): Any reset

Reset Value: 00000000B

BIT

TCON.7

SYMBOL

TF1

TCON.6

TCON.5

TCON.4

TCON.3

TR1

TF0

TR0

IE1

TCON.2

TCON.1

TCON.0

IT1

IE0

IT0

7

TF1

6

TR1

5

TF0

4

TR0

3

IE1

2

IT1

1

IE0

0

IT0

FUNCTION

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine, or by software.

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine, or by software.

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when the interrupt is processed, or by software.

Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when the interrupt is processed, or by software.

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Figure 28: Timer/Counter Control Register (TCON)

42 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

Osc / 6

Tn Pin

TRn

Gate

INTn Pin

C/T = 0

C/T = 1

P87C51Mx2 User Manual

P87C51Mx2

Control

TLn

(5-bits)

THn

(8-bits)

Overflow

TFn

Interrupt

Osc / 6

Tn Pin

TRn

Gate

INTn Pin

Figure 29: Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)

C/T = 0

C/T = 1

Control

TLn

(8-bits)

THn

(8-bits)

Overflow

TFn Interrupt

Osc / 6

Tn Pin

TRn

Gate

INTn Pin

Figure 30: Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter)

C/T = 0

C/T = 1

Control

TLn

(8-bits)

Reload

Overflow

TFn

THn

(8-bits)

Figure 31: Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload)

Interrupt

43 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

Osc /6

T0 Pin

TR0

Gate

INT0 Pin

C/T = 0

C/T = 1

P87C51Mx2 User Manual

P87C51Mx2

Control

TL0

(8-bits)

Overflow

TF0

Interrupt

Osc / 2

Control

TH0

(8-bits)

Overflow

TF1

Interrupt

TR1

Figure 32: Timer/Counter 0 Mode 3 (Two 8-Bit Counters)

6.5

TIMER 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud

Rate Generator, which are selected by bits in the T2CON as shown in Figure 33.

6.5.1

CAPTURE MODE

I n the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers,

TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit

EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt).

The capture mode is illustrated in Figure 35. (There is no reload value for TL2 and TH2 in this mode. Even when a capture event

occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses.)

6.5.2

AUTO-RELOAD MODE (UP OR DOWN COUNTER)

In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (via C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD

register (see Figure 34). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer

2 can count up or down depending on the value of the T2EX pin.

Figure 36 shows Timer 2 counting up automatically (DCEN = 0). In this mode, there are two options selected by bit EXEN2 in

T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means.

44 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is 1.

In Figure 37, DCEN=1. Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When

a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed.

6.5.3

PROGRAMMABLE CLOCK-OUT

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two additional functions. It can be programmed:

1. To input the external clock for Timer/Counter 2, or;

2. To output a 50% duty cycle clock ranging from 122Hz to 8MHz at a 16MHz operating frequency.

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H,

RCAP2L) as shown in this equation:

(

OscillatorFrequency

2x 65536 –

(

RCAP2H RCAP2L

) )

Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The "6" in the denominator of the above equation indicates six oscillator cycles per machine cycle.

In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note that the equations for baudrate and the Clock-Out frequency are different.

45 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

T2CON

Address: C8h

Bit addressable

Reset Value: 00h

BIT

T2CON.7

T2CON.6

SYMBOL

TF2

EXF2

T2CON.5

T2CON.4

T2CON.3

T2CON.2

T2CON.1

T2CON.0

RCLK+TCLK

0

0

1

X

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

7

TF2

6

EXF2

5

RCLK

4 3

TCLK EXEN2

2

TR2

1 0

C/T2 CP/RL2

FUNCTION

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1.

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.

Microcontroller’s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2=1: in the first machine cycle pin T2EX has to be sampled as "1"; in the second machine cycle it has to be sampled as "0", and in the third machine cycle EXF2 will be set to 1.

Receive clock flag. When set, causes the serial port 0 (UART 0) to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 (unless SBRGS - BRGCON.1 is set to ’1’).

RCLK = 0 causes Timer 1 overflow to be used for the receive clock. (See section on

"UARTs").

Transmit clock flag. When set, causes the serial port 0 (UART 0) to use Timer 2 overflow pulses for its transmit clockN in modes 1 and 3 (unless SBRGS - BRGCON.1 is set to ’1’).

TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. (See section on

"UARTs").

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2

= 0 causes Timer 2 to ignore events at T2EX

.

Start/stop control for Timer 2. A logic 1 enables the timer to run.

Timer or counter select. (Timer 2)

0 = Internal timer (f

OSC

/6)

1 = External event counter (falling edge triggered; external clock’s max. rate=f

OSC

/12)

.

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if

EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Figure 33: Timer/Counter 2 (T2CON) Control Register

CP/RL2

0

1

X

X

TR2

1

1

1

0

Table 10: Timer 2 operating mode

MODE

16-BIT auto reload

16-bit capture

Baud rate generator for UART 0 off

46 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

T2MOD

Address: C9h

Not bit addressable

Reset Value: XXXXXX00B

BIT

T2MOD.7-2

T2MOD.1

T2MOD.0

SYMBOL

-

T2OE

DCEN

7

-

6

-

5

-

4

-

3

-

2

-

1 0

T2OE DCEN

FUNCTION

Reserved for future use. Should be set to 0 by user programs.*

Timer 2 Output Enable bit.

Down Count Enable bit. When set, this allows timer2 to be configured as an up/down counter.

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate

.

Figure 34: Timer 2 Mode (T2MOD) Control Register

6.5.4

BAUD RATE GENERATOR MODE FOR UART 0 (SERIAL PORT 0)

When serial port 0 (UART 0) doesn’t use the independent baud rate generator (S0BRGS = 0, S0BRGS is BRGCON.1), bits TCLK and/or RCLK in T2CON allow the serial port 0 (UART 0) transmit and receive baud rates to be derived from either Timer 1 or

Timer 2. Refer to the section on UARTs for details. Assume that S0BRGS = 0, when TCLK= 0, Timer 1 is used as the UART 0

transmit baud rate generator. when TCLK= 1, Timer 2 is used as the UART 0 transmit baud rate generator. RCLK has the same effect for the UART 0 receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates –

Timer 1, Timer 2 or baud rate generator.

Figure 38 shows Timer 2 in baud rate generator mode. The baud rate generation mode is like the auto-reload mode,in that a

rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.

The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below:

Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate/16

The timer can be configured for either “timer” or “counter” operation. In many applications, it is configured for “timer” operation

(C/T2=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator.

Usually, as a timer it would increment every machine cycle (i.e., 1 / 6 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows:

Modes 1 and 3 Baud Rates =

Oscillator Frequency / (16 X (65536 - (RCAP2H, RCAP2L)))

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when

Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.

When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a

47 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2 write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing

the Timer 2 or RCAP2 registers. Table 11 shows commonly used baud rates and how they can be obtained from Timer 2.

6.5.5

SUMMARY OF BAUD RATE EQUATIONS

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is:

If Timer 2 is being clocked internally , the baud rate is:

Baud Rate = f

OSC

/ (16 x (65536 - (RCAP2H, RCAP2L)))

Where f

OSC

= Oscillator Frequency

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as:

RCAP2H, RCAP2L = 65536 - f

OSC

/ (16 x Baud Rate)

6.5.6

TIMER/COUNTER 2 SET-UP

Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit

TR2 must be set, separately, to turn the timer on.

RCLK+TCLK

0

0

1

X

CP/RL2

0

1

X

X

TR2

1

1

1

0

MODE

16-BIT auto reload

16-bit capture

Baud rate generator for UART 0 (if S0BRGS

(BRGCON.1) = 0) off

750K

19.2K

9.6K

4.8K

2.4K

600

220

600

220

Baud Rate Osc Freq Timer 2

12MHz

12MHz

12MHz

12MHz

12MHz

12MHz

12MHz

6MHz

6MHz

RCAP2H

FF

FF

FF

FF

FE

FB

F2

FD

F9

Table 11: Timer 2 Generated Commonly Used Baud Rates

RCAP2L

FF

D9

B2

64

C8

1E

AF

8F

57

48 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

OSC

÷

6

C/T2 = 0

T2 Pin

Transition

Detector

C/T2 = 1

TL2

(8-bit)

TH2

(8-bit)

TR2

CONTROL

CAPTURE

RCAP2L RCAP2H

T2EX Pin

CONTROL

EXEN2

Figure 35: Timer 2 in Capture Mode

TF2

EXF2

P87C51Mx2 User Manual

P87C51Mx2

Timer 2

Interrupt

OSC

÷

6

T2 Pin

Transition

Detector

C/T2 = 0

C/T2 = 1

CONTROL

TR2

RELOAD

TL2

(8-bit)

TH2

(8-bit)

RCAP2H

T2EX Pin

TF2

EXEN2

CONTROL

Figure 36: Timer 2 in Auto Reload Mode (DCEN = 0).

EXF2

49

Timer 2

Interrupt

Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

(DOWN COUNTING RELOAD VALUE)

FFH FFH

P87C51Mx2 User Manual

P87C51Mx2

TOGGLE

EXF2

OSC

÷

6

T2 Pin

C/T2 = 0

TL2

(8-bit)

TH2

(8-bit)

OVERFLOW

TF2

Timer 2

Interrupt

C/T2 = 1

CONTROL

TR2

COUNT DIRECTION

1 = UP

0 = DOWN

RCAP2L RCAP2H

(UP COUNTING RELOAD VALUE)

Figure 37: Timer 2 in Auto Reload Mode (DCEN = 1).

T2EX PIN

OSC

÷

2

T2 Pin

C/T2 = 0

C/T2 = 1

TR2

CONTROL

TL2

(8-bit)

TH2

(8-bit)

RELOAD

TX/RX Baud Rate (See section "Baud

Rate Generator and Selection")

T2EX Pin

RCAP2L RCAP2H

Transition

Detector

CONTROL

EXF2

Timer 2

Interrupt

EXEN2

Figure 38: Timer 2 in Baud Rate Generator Mode

50 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.6

UARTS

The P87C51Mx2 includes two enhanced UARTs with one independent Baud Rate Generator. They are compatible with the enhanced UART based on the 8xC51Rx+ except the baud rate generator. The first UART (UART 0) can select using Timer1 overflow, Timer2 overflow or the independent Baud Rate Generator. The second UART (UART 1) only uses the independent

Baud Rate Generator to generate its baud rate. Besides the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The two UARTs are called UARTs 0 and 1 to correspond to the serial port assignments.

Each serial port can be operated in 4 modes:

6.6.1

MODE 0

Serial data enters and exits through RxD_n. TxD_n outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 1/6 of the CPU clock frequency.

6.6.2

MODE 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical

1). When data is received, the stop bit is stored in RB8_0/RB8_1 in Special Function Register S0CON/S1CON. For UART 0, the baud rate is variable and is determined by the Timer 1/2 (see T2CON.5-4) overflow rate or the Baud Rate Generator (described

later in section on "Baud Rate Generator and Selection"). The Baud Rate Generator is the only source for baud rate for UART 1.

6.6.3

MODE 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register S0CON/S1CON, while the stop bit is ignored. For UART 0, the baud rate is programmable to either

1/16 or 1/32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. For UART 1, the baud rate is from the Baud

Rate Generator.

6.6.4

MODE 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. For UART 0, the baud rate in Mode 3 is variable and is determined by the Timer 1/2 (see T2CON.5-4) overflow rate or the Baud Rate Generator

(described later in section on "Baud Rate Generator and Selection"). Baud Rate Generator is the only source for baud rate for

UART 1.

In all four modes, transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. Reception is initiated in Mode 0 by the condition RI_0/RI_1 = 0 and REN_0/REN_1 = 1. Reception is initiated in the other modes by the incoming start bit if REN_0/REN_1 = 1.

6.6.5

SFR AND EXTENDED SFR SPACES

The regular UART 0 SFRs and control bits are in the regular SFR space. However, extended control and UART 1 registers are in the MX extended SFR space.

51 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Register Description

PCON Power Control

T2CON Timer2 Control

S0CON Serial Port 0 Control

S0BUF Serial Port 0 Data Buffer

S0ADDR Serial Port 0 Address

S0ADEN Serial Port 0 Address Enable

S0STAT Serial Port 0 Status

S1CON Serial Port 1 Control

S1BUF Serial Port 1 Data Buffer

S1ADDR Serial Port 1 Address

S1ADEN Serial Port 1 Address Enable

S1STAT Serial Port 1 Status

BRGR1 Baud Rate Generator Rate High Byte

BRGR0 Baud Rate Generator Rate Low Byte

BRGCON Baud Rate Generator Control

SFR Location

87H

C8H

98H

99H

A9H

B9H

Table 12: SFR/Extended SFR Locations for UARTs.

MX Extended SFR Location

8CH

80H

81H

82H

83H

84H

87H

86H

85H

6.6.6

BAUD RATE GENERATOR AND SELECTION

The P87C51Mx2 enhanced UARTs have one associated independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs in the extended SFR space. (BRGR1.7-0, BRGR0.7-4) together form a 12-bit baud rate divisor value (BRATE11-0) that works in a similar manner as Timer 1/2, but if the baud rate generator is used, Timer 1/2 can be used for other timing functions.

UART 0 can use either Timer 1/2 (see T2CON.5-4) or the baud rate generator output (as determined by BRGCON.2-1 in the extended SFR space), while UART 1 only uses the baud rate generator. Note that in UART 0, Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. T2 (for UART 0) and the independent Baud Rate Generator (for both UARTs) will be used

as is, without the divided by 2 option (see Figure 42).

BRGR0

Address: 86h (MX Extended SFR Space)

Not bit addressable

Reset Value: 00h

BIT

BRGR0.7-4

BRGR0.3-0

SYMBOL

BRATE3-0

-

7 6 5 4

BRATE3 BRATE2 BRATE1 BRATE0

3

-

2

-

FUNCTION

Baud rate divisor bits 3-0.

Reserved for future use. Should be set to 0 by user programs.

Figure 39: BRGR0 Register

1

-

0

-

52 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

BRGR1

Address: 87h (MX Extended SFR Space)

Not bit addressable

Reset Value: 00h

7 6 5 4 3 2 1 0

BRATE11BRATE10 BRATE9 BRATE8 BRATE7 BRATE6 BRATE5 BRATE4

BIT

BRGR1.7-0

SYMBOL

BRATE11-4

FUNCTION

Baud rate divisor bits 11-4.

Figure 40: BRGR1 Register

Updating the BRGR1 and BRGR0 SFRs.

The effective baud rate is a 16-bit value.The baud rate SFRs, BRGR1 and

BRGR0 must only be loaded when the Baud Rate Generator is disabled (the BRGEN bit in the BRGCON register is ’0’). This avoids the loading of an interim value (when only one of BRGR1 and BRGR0 is written) to the baud rate generator. (CAUTION:

If any of BRGR0 or BRGR1 is written if BRGEN = 1, result is unpredictable.)

S0CON.7

(SM0_0)

0

S0CON.6

(SM1_0)

0

T2CON.5/4

(RCLK - Receive

TCLK - Transmit)

X

0

0 1

1

X

0

1

1

1

1

0

0

1

0

1

X

0

1

* Receiver and transmit clocks can be different.

PCON.7

(SMOD1)

X

0

1

X

X

0

1

0

1

X

X

BRGCON.1

(S0BRGS)

X

X

X

0

1

X

X

X

X

0

1

Receive/Transmit Baud Rate for UART 0 f f

OSC

OSC f f f

OSC

OSC

OSC

/6

T1_rate/32

T1_rate/16

T2_rate/16

/(BRATE

×

16+16)

/32

/16

T1_rate/32

T1_rate/16

T2_rate/16

*

*

*

*

*

*

/(BRATE

×

16+16)

*

*

Table 13: Baud Rate Generation for UART 0. Use T2CON.5 (RCLK) in Receive Baud Rate Selection, T2CON.4 (TCLK) in Transmit Baud Rate Selection

53 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

S1CON.7

(SM0_1)

S1CON.6

(SM1_1)

Baud Rate for UART 1

0

0

1

1

0

1

0

1 f

OSC

/6 f

OSC

/(BRATE

×

16+16)

* f

OSC

/(BRATE

×

16+16)

* f

OSC

/(BRATE

×

16+16)

*

* UART 1 has the same receive and transmit baud rate.

Table 14: Baud Rate Generation for UART 1.

BRGCON Address: 85h (MX Extended SFR Space)

Not bit addressable 7 6

Reset Value: 00h -

BIT

BRGCON.7-2

BRGCON.1

BRGCON.0

SYMBOL

-

S0BRGS

BRGEN

5

-

4

-

3

-

2

-

1 0

S0BRGS BRGEN

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

(For UART 0 only) Used in combination with the RCLK and TCLK in deciding the receive

and transmit baud rates to UART 0 in modes 1 & 3 (see Table 13 for details).

0: Disable Baud Rate Generator; 1: Enable Baud Rate Generator. Baud rate SFRs

(BRGR1 and BRGR0) can only be written when BRGEN is ’0’.

Figure 41: BRGCON Register

SMOD1 = 1

Timer 1 Overflow

Baud Rate Generator

Timer 2 Overflow

÷2

SMOD1 = 0

S0BRGS = 1

RCLK = 0

UART 0 Receive Baud Rate Modes 1 and 3

RCLK = 1

TCLK = 0

UART 0 Transmit Baud Rate Modes 1 and 3

TCLK = 1

S0BRGS = 0

UART 1 Receive and Transmit Baud Rate Modes 1, 2, and 3

Figure 42: Baud Rate Generations for UART 0 (Modes 1, 3) and UART 1 (Modes 1, 2, 3)

54 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

SnCON

S0CON: Address: 98h (Conventional SFR Space)

S1CON: Address: 80h (MX Extended SFR Space)

Bit addressable

7 6 5

Reset Value: 00h

SM0_n/FE_n

SM1_n SM2_n

4

REN_n

3

TB8_n

2

RB8_n

1

TI_n

0

RI_n

BIT

SnCON.7

SnCON. 6

SnCON.5

SnCON.4

SnCON.3

SnCON.2

SnCON.1

SnCON.0

SYMBOL

SM0_n/FE_n

FUNCTION

The usage of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is SM0_n, which with SM1_n, defines the serial port mode. If SMOD0 = 1, this bit is FE

(Framing Error). FE is set by the receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared by valid frames but is cleared by software. (Note: It is recommended to set up UART mode bits SM0_n and SM1_n before setting SMOD0 to

’1’.)

With SM0_n, defines the serial port mode (see table below).

SM1_n

SM0_n, SM1_n UART Mode

0 0 0: shift register

UART 0 Baud Rate

CPU clock/6

UART 1 Baud Rate

CPU clock/6

0 1

1 0

1 1

SM2_n

REN_n

TB8_n

RB8_n

TI_n

RI_n

1: 8-bit UART

2: 9-bit UART

Variable (see Table 13)

Baud Rate Generator (see Table 14)

CPU clock/32 or CPU clock/16

Baud Rate Generator (see Table 14)

3: 9-bit UART

Variable (see Table 13)

Baud Rate Generator (see Table 14)

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if

SM2_n is set to 1, then Rl_n will not be activated if the received 9th data bit (RB8_n) is 0.

In Mode 1, if SM2_n=1 then RI_n will not be activated if a valid stop bit was not received.

In Mode 0, SM2_n should be 0.

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2_n=0, RB8_n is the stop bit that was received. In Mode 0, RB8_n is undefined.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the the stop bit (see description of INTLO bit in SnSTAT register) in the other modes, in any serial transmission. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3, if

SMOD0 = 0, it is set near the middle of the 9th data bit (bit 8); if SMOD0 = 1, it is set nearly the middle of the stop bit. (See SM2_n for exceptions). Must be cleared by software.

Figure 43: Serial Port Control Register (SnCON)

6.6.7

FRAMING ERROR

Framing error (FE_n) is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6) is 1, framing errors for UARTs

0 and 1 can be made available to the S0CON.7 and S1CON.7 respectively. If SMOD0 is 0, S0CON.7 and S1CON.7 are SM0 for

UARTs 0 and 1 respectively. It is recommended that SM0_n and SM1_n (SnCON.7-6) are set up before SMOD0 is set to ’1’.

It should also be noted that a break detect (setting of BR_n) also sets FE_n.

55 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.6.8

STATUS REGISTER

Each of the enhanced UARTs contains a status register. The status register also contains some control bits:

• DBMOD_n (n = 0, 1) - The enhanced UART includes double buffering. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to disable double buffering.

• INTLO_n - For modes 1, 2 and 3, the UART allows Tx interrupt to occur at the beginning or end of the STOP bit. This bit is reset to ’0’ to select Tx to be issued at the beginning of the STOP bit. Note that in the case of single buffering, if Tx interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit. For UART mode 0, this bit must be cleared to ’0’.

• CIDIS_n (n = 0, 1) - The UART can issue combined Tx/Rx interrupt (conventional 80C51 UART) or have separate Tx and Rx interrupts. This bit is reset to ’0’ to select combined interrupt.

• DBISEL_n (n = 0, 1) - This is only used when the corresponding DBMOD_n = 1. If DBMOD_n = 0, this bit must be cleared to

’0’ for future compatibility. This bit controls the number of interrupts that can occur when double buffering is enabled. If ’0’, the number of Tx interrupts must be the same as the number of characters sent. If ’1’, an additional interrupt is sent at the beginning

(INTLO_n = 0) or the end (INTLO_n = 1) of the STOP bit when there is no more data in the double buffer. This last interrupt can be used to indicate that all transmit operations are over.

• STINT_n (n = 0,1) - If ’1’, FE_n, BR_n and OE_n can cause interrupt (refer to Figure 44).

The bits DBMOD_n and DBISEL_n are discussed further in section "Double Buffering". INTLO_n behaves in the same manner regardless of single of double buffering, but the first interrupt occurs different. It is also explained in the section "Double Buffering".

CIDIS_n is not related to double buffering.

56 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

SnSTAT

S0STAT: Address: 8Ch (MX Extended SFR Space)

S1STAT: Address: 84h (MX Extended SFR Space)

Not bit addressable

7 6 5

Reset Value: 00h

4 3

DBMOD_n INTLO_n CIDIS_n DBISEL_n

FE_n

2

BR_n

1 0

OE_n STINT_n

BIT

SnSTAT.7

SnSTAT. 6

SnSTAT.5

SnSTAT.4

SnSTAT.3

SnSTAT.2

SnSTAT.1

SnSTAT.0

SYMBOL

DBMOD_n

INTLO_n

CIDIS_n

DBISEL_n

FE_n

BR_n

OE_n

STINT_n

FUNCTION

0: Double buffering disabled; 1: Double buffering enabled.

Transmit interrupt position for UART mode 1, 2 or 3. 0: Tx interrupt issued at beginning of stop bit; 1: Tx interrupt issued at end of stop bit. Must be ’0’ for mode 0

0: Combined Tx/Rx interrupt for Serial Port n; 1: Rx and Tx interrupts are separate.

Double buffering transmit interrupt select - used only if double buffering is enabled

(DBMOD_n set to ’1’), must be ’0’ when double buffering is disabled:

0: There is only one transmit interrupt generated per character written to SnBUF.

1: One transmit interrupt is generated after each character written to SnBUF, and there is also one more transmit interrupt generated at the STOP bit of the last character sent (i.e., no more data in buffer).

Note that except for the first character written (when buffer is empty), the location of the transmit interrupt is determined by INTLO_n. When the first character is written, the transmit interrupt is generated immediately after the SnBUF is written.

Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. It is also set with BR_n if a break is detected. Cleared by software.

Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ’0’. Thus it gives a "Start of Break Detect" on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect feature operates indpendently of the UARTs and provides the

START of Break Detect status bit that a user program may poll. Cleared by software.

Overrun Error flag is set if a new character is received in the receiver buffer while it is still full, i.e., when bit 8 of a new byte is received while RI in SnCON is still set. If an overrun occurs, SnBUF retains the old data and the new character received is lost. Cleared by software.

Status Interrupt Enable:

0: FE_n, BR_n, OE_n cannot cause any interrupt.

1: FE_n, BR_n, OE_n can cause interrupt. The interrupt used is shared with RI_n

(CIDIS_n = 1) or combined TI_n/RI_n (CIDIS_n = 0).

Figure 44: Serial Port Status Register (SnSTAT)

6.6.9

MORE ABOUT UART MODE 1

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

57 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

The signal to load SBUF and RB8 (RB8_0 for UART 0 or RB8_1 for UART 1), and to set RI (RI_0 for UART 0 or RI_1 for UART

1), will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and

(b) Either SM2 (SM2_0 for UART 0 or SM2_1 for UART 1) = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated.

6.6.10

MORE ABOUT UART MODES 2 AND 3

Reception is performed in the same manner as in mode 1.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1.

If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF.

S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6 S1 ... S6

Write to SBUF

Shift

D0 D1 D2 D3 D4 D5 D6 D7 RxD (Data Out)

TxD (Shift Clock)

TI

Write to SCON (Clear RI)

RI

Shift

RxD

(Data In)

TxD (Shift Clock)

D0 D1 D2 D3 D4 D5 D6 D7

Figure 45: Serial Port Mode 0 (Only Single Transmit Buffering Case Is Shown)

Transmit

Receive

58 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

TX Clock

Write to SBUF

Shift

TxD

TI

Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit

INTLO_n = 0

INTLO_n = 1

Transmit

RX Clock

RxD

Shift

RI

÷ 16 Reset Start Bit

D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit

Figure 46: Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown)

TX Clock

Write to SBUF

Shift

TxD

TI

Receive

Transmit

Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit

INTLO_n = 0

INTLO_n = 1

RX Clock

RxD

Shift

RI

÷ 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit

Receive

SMOD0 = 0

Figure 47: Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown)

SMOD0 = 1

59 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.6.11

DOUBLE BUFFERING

Each of the P87CMx2's UARTs optionally has the ability to buffer the next character to be transmitted while the current character is still being shifted out of the transmit shift register. The advantage of double buffering comes when it is desired to transmit a string of characters with only a single Stop Bit between characters. In order to accomplish this on the original 80C51 UART the next character be loaded while the Stop Bit of the previous character was being sent. Double buffering allows the next character to be loaded at any time from the beginning of the Start bit to the end of the Stop Bit of the previous character. If double buffering is disabled the UART is compatible with the conventional 80C51 UART.

Double buffering is enabled by setting the DBMOD_n (SnSTAT.7) SFR bit to ’1’. If disabled (DBMOD_n = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out.

Transmit Interrupts with Double Buffering.

Without double buffering the transmit interrupt can be selected to occur at either the beginning or the end of the Stop Bit. The purpose of the interrupt is to let the user program know when the UART can accept another character. As a result the timing of the interrupt has been changed when double buffering is enabled. An interrupt is generated each time data is transferred from the buffer register to the transmit shift register. Thus if the UART transmit is idle an interrupt will be generated as soon as the buffer register is loaded. If the UART is transmitting a character when the buffer register is loaded, an interrupt will not occur until the beginning of the Stop Bit of the current character. Note that if the buffer is loaded anytime before the end of the Stop Bit characters will be transmitted without extra Stop Bit time. Also if a character is loaded into the buffer during the stop bit the interrupt will occur when the buffer is loaded.

There is one additional feature with respect to the occurrence of interrupts when double buffering is enabled. If the DBISEL_n

SFR bit is a '0' an interrupt occurs only when data is transferred from the buffer to the transmit shift register. Thus each character generates a single interrupt. The operation is identical if DBISEL_n is a '1.' As long as the buffer register is filled before the stop bit is reached. If DBISEL_n is a '0' and the INTLO_n SFR bit is a '1' an interrupt will occur at the end of the Stop Bit of the last character if the buffer register is empty. If If DBISEL_n is a '0' and the INTLO_n SFR bit is a '0', an interrupt will be generated at the beginning of the Stop Bit if the transmit buffer register is empty. Note that in this case if the transmit buffer is loaded before the end of the stop bit another interrupt will be generated and the UART will transmit this new character without lengthening the

Stop Bit.

60 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

TxDn

Write to

SnBUF

Tx Interrupt

Single Buffering (DBMOD_n/SnSTAT.7 = 0), Early Interrupt (INTLO_n/SnSTAT.6 = 0) is Shown

TxDn

Write to

SnBUF

Tx Interrupt

Double Buffering (DBMOD_n/SnSTAT.7 = 1), Early Interrupt (INTLO_n/SnSTAT.6 = 0) is Shown,

No Ending Tx Interrupt (DBISEL_n/SnSTAT.4 = 0)

TxDn

Write to

SnBUF

Tx Interrupt

Double Buffering (DBMOD_n/SnSTAT.7 = 1), Early Interrupt (INTLO_n/SnSTAT.6 = 0) is Shown,

With Ending Tx Interrupt (DBISEL_n/SnSTAT.4 = 1)

Figure 48: Transmission with and without Double Buffering (8-Bit Case)

The 9th Bit (Bit 8) in Double Buffering.

If double buffering is disabled (DBMOD_n, i.e. SnSTAT.7 = 0), TB8 can be written before or after SnBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 MUST be updated before SnBUF is written, as TB8 will be double-buffered together with

SnBUF data. The operation described in the section "Transmit Interrupts with Double Buffering" becomes as follows:

1. The double buffer is empty initially.

2. The CPU writes to TB8.

3. The CPU writes to SnBUF.

4. The SnBUF/TB8 data is loaded to the shift register and a Tx interrupt is generated immediately.

5. If there is more data, go to 7, else continue on 6.

6. If there is no more data, then:

- If DBISEL_n is ’0’, no more interrupt will occur.

- If DBISEL_n is ’1’ and INTLO_n is ’0’, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

- If DBISEL_n is ’1’ and INTLO_n is ’1’ (UART mode 1, 2 or 3), a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data).

7. If there is more data, the CPU writes to TB8 again.

8. The CPU writes to SnBUF again. Then:

61 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

- If INTLO_n is ’0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter.

- If INTLO_n is ’1’ (UART mode 1, 2 or 3), the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter.

Go to 4.

Note that if DBISEL_n is ’1’ and when the CPU is writing to SnBUF about the same time the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

6.6.12

MULTIPROCESSOR COMMUNICATIONS

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8_n. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8_n = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.

With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes.

SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

6.6.13

AUTOMATIC ADDRESS RECOGNITION

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON.

In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special

Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the

SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1101

Given = 1100 00X0

Slave 1 SADDR = 1100 0000

SADEN = 1111 1110

Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

62 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Slave 0 SADDR = 1110 0000

SADEN = 1111 1001

Given = 1110 0XX0

Slave 1 SADDR = 1110 0000

SADEN = 1111 1010

Given = 1110 0X0X

Slave 2 SADDR = 1110 0000

SADEN = 1111 1100

Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave

2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110

0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

6.7

WATCHDOG TIMER

The watchdog timer subsystem protects the system from incorrect code execution over a longer period of time by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count.

For the P87C51Mx2, the watchdog timer is compatible with the watchdog timer in 89C51Rx2. In addition, it has a prescaler of up to 1024 times (default without prescaling) that support longer watchdog timeout.

The WDT consists of a 14-bit counter and Watchdog Timer Reset(WDTRST) SFR. The prescaler is determined by the watchdog control (WDCON) SFR in the MX extended SFR space.

6.7.1

WATCHDOG FUNCTION

The time interval of the watchdog timer can be calculated as: timeoutperiod =

16383

× prescalefactor

× f

OSC

In other words, after a feed sequence, the watchdog timer time out will occur after

16383

× prescalefactor will cause a watchdog reset, unless the next feed sequence occurs before the time out.

machine cycles and

6.7.2

FEED SEQUENCE

WDT is disabled after reset of the microcontroller. To enable the WDT, user must write 01EH and 0E1H in sequence to the

WDTRST register. Once the WDT is enabled, user must feed the watchdog in by writing 01EH and 0E1H to WDTRST before a

WDT timeout to avoid WDT overflow. When WDT overflows, it will drive an reset HIGH pulse at the RST pin. After WDT is enabled, it cannot be disabled unless reset.

The following code is recommended for a feed sequence:

CLR EA ;Disable all interrupts, avoid interrupt in between two parts of feed

;sequence.

63 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

MOV

MOV

SETB

WDTRST,#01Eh

WDTRST,#0E1h

EA

;Feed sequence first part

;Feed sequence second part

;Enable interrupts.

Note that:

• Upon a power up or any reset, including WDT reset, the watch dog timer is disabled. Executing the feed sequence once will start the WDT. Once started, it cannot be disabled until reset again.

• The watchdog is enabled by a write of 1Eh followed by a write of E1h to the WDTRST register. Before the first 1Eh is written to WDTRST, a write of any pattern (other than 1Eh) will not cause a reset. Once an 1Eh is written to the WDTRST register, any write of a pattern other than 1Eh or E1h to the WDTRST register will cause a watchdog reset.

• The triggering event to restart the WDT is the second part (writing E1h to the WDTRST SFR) of the feed sequence.

• Refer to Figure 49 for details of WDT operations, including effects of illegal feed patterns to the WDTRST SFR.

64 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

Any Reset

WDT disabled. Wait for next write to the WDTRST SFR

No Written 01Eh to the

WDTRST SFR?

Yes

WDT disabled. Wait for next write to the WDTRST SFR

=1Eh Value written to the

WDTRST SFR?

=E1h

Start WDT

Neither 1E h nor E1h

=E1h

=1Ehh

WDT enabled. Wait for next write to the WDTRST SFR

Written 0E1h to the

WDTRST SFR?

=E1h

Restart WDT

Time out

Value written to the

WDTRST SFR?

=1Eh

WDT enabled. Wait for next write to the WDTRST SFR

Neither 1Eh nor E1h

Time out

Neither 1Eh nor E1h

Figure 49: Watchdog Timer State Transitions

WDT Reset

P87C51Mx2 User Manual

P87C51Mx2

65 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

6.7.3

WDT CONTROL

The P87C51Mx2 has a control register in the MX extended SFR space. It has a 3-bit prescaler control to select the prescale factor for the watchdog timer clock. WDCON should be loaded with selected value before WDT is turned on. Writing to WDCON while WDT is enabled will result in unpredictable behavior.

6.7.4

WATCHDOG RESET WIDTH

When the WDT times out, a reset will occur, and the external reset (RST) pin will be driven high for 98 clock cycles.

WDCON

Address: 8Fh (MX Extended SFR Space)

Not bit addressable

7 6

Reset Value: 00h

-

5

-

4

-

3

-

2 1 0

WDPRE2 WDPRE1 WDPRE0

BIT

WDCON.7-3

WDCON.2-0

SYMBOL

-

WDPRE2-0

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

Select WDT presecale factor. Note that the value written to these bits will not be immediately available to be read until after a WDT feed sequence.

Figure 50: WDCON Register

WDPRE2 WDPRE1 WDPRE0

0 0 0

0

0

0

1

1

0

1

1

0

1

1

1

0

0

1

1

1

0

1

0

1

Table 15: WDT Prescale Selection

Prescale Factor

1

4

16

64

128

256

512

1024

6.7.5

READING FROM THE WDCON SFR

It should be noted that value written to the WDCON register will not be immediately available to be read until after a successful feed sequence. Any read before a feed sequence will fetch the old value.

6.7.6

SOFTWARE RESET VIA WATCHDOG TIMER FEED SEQUENCE

The following instructions will result in a software reset via the watchdog timer reset, even if one or more interrupts occur during those instructions:

MOV

MOV

WDTRST,#01Eh

WDTRST,#0AAh

;Feed sequence first part

;Any pattern other than 1Eh or E1h (not necessarily AAh) will perform a

;WDT reset

66 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

This software reset will be performing the same function as a WDT reset, where a reset pulse will also be generated to reset external circuitries.

6.8

ADDITIONAL FEATURES

AUXR

Address: 8EH

Not bit addressable

Reset Value: 00h

BIT

AUXR.7-2

AUXR.1

SYMBOL

-

EXTRAM

AUXR.0

AO

7

-

6

-

5

-

4

-

3

-

2

-

1 0

EXTRAM AO

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

Internal/External RAM access using MOVX @Ri/@DPTR. When 0, internal XRAM access is selected. When 1, external data memory is selected. (Refer to "51MX Architecture

Reference").

Disable/Enable ALE. When 0, ALE is emitted at a constant rate of 1/3 the oscillator frequency. When 1, ALE is active only during a MOVX or MOVC instruction that is targeting .

Figure 51: AUXR Register

6.8.1

EXPANDED DATA RAM ADDRESSING

The P87C51Mx2 has expanded data RAM addressing capability. Details of the data memory structure are explained in "51MX

Architecture Reference".

The device has on-chip data memory that is mapped into the following segments:

• Address 0000H-007FH are directly and indirectly addressable (DATA memory).

• Address 0080H-00FFH are indirectly addressable as RAM (IDATA memory). Note: When 000080H-0000FFH is directly addressed, SFRs will be accessed.

• Address 0100H-04FFH (for MB2/MC2) are extended indirectly addressable RAM (part of EDATA memory).

• There are also 768 bytes of XDATA memory (locations 000000H-0002FFH) for MB2, and 1,792 bytes of XDATA memory

(locations 000000H-0006FFH) for MC2. If EXTRAM = 0, this internal XDATA memory location is selected in a MOVX instruction to/from locations 000000H-0002FFH (for MB2) or 000000H-0006FFH (for MC2), and external memory will be accessed above these locations. If EXTRAM = 1, the internal XDATA RAM will not be used, all MOVX instructions will access external data memory.

67 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

AUXR1

Address: A2h

Not bit addressable

Reset Value: 00h

BIT

AUXR1.7-5

AUXR1.4

AUXR1.3

AUXR1.2

AUXR1.1

AUXR1.0

SYMBOL

-

LPEP

GF2

0

-

DPS

7

-

6

-

5

-

4

LPEP

3

GF2

2

0

1

-

0

DPS

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

LPEP can be set to one for applications where V

CC

< 4V (reduces power consumption).

General purpose user-defined flag.

This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register.

Reserved for future use. Should be set to 0 by user programs.

Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details.

Figure 52: AUXR1 Register

6.8.2

DUAL DATA POINTERS

The dual Data Pointer (DPTR) adds to the ways in which the processor can specify the address used with certain instructions.

The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled.

Specific instructions affected by the Data Pointer selection are:

• INC DPTR

• JMP @A+DPTR

Increments the Data Pointer by 1.

Jump indirect relative to DPTR value.

• MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant.

• MOVC A, @A+DPTR Move code byte relative to DPTR to the accumulator.

• MOVX A, @DPTR

• MOVX @DPTR, A

Move data byte from data memory, relative to DPTR, to the accumulator.

Move data byte from the accumulator to data memory, relative to DPTR.

Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled

(thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

6.9

PROGRAMMABLE COUNTER ARRAY (PCA)

The Programmable Counter Array available on the P87C51Mx2 is compatible with 89C51Rx2. The PCA includes a special 16bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and

CPS0 bits in the CMOD SFR (see Figure 55).

68 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

16 BITS

PCA TIMER/COUNTER

TIME BASE FOR PCA MODULES

MODULE FUNCTIONS:

16-BIT CAPTURE

16-BIT TIMER

16-BIT HIGH SPEED OUTPUT

8-BIT PWM

WATCHDOG TIMER (MODULE 4 ONLY)

16 BITS

MODULE0

MODULE1

MODULE2

MODULE3

MODULE4

Figure 53: Programmable Counter Array (PCA)

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.

The watchdog timer function is implemented in module 4.

The CCON SFR contains the run control bit for the PCA and t he flags for the PCA timer (CF) and each module. To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software. All the modules share

one interrupt vector. The PCA interrupt system is shown in Figure 54.

Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit

(CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the

CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The

CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output.

69 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

CF CR CCF4 CCF3 CCF2 CCF1 CCF0

CCON

(D8h)

PCA TIMER/COUNTER

MODULE0

MODULE1

MODULE2

MODULE3

MODULE4

CMOD.0

ECF CCAPMn.0

ECCFn

IE.6

EC

IE.7

EA

TO

INTERRUPT

PRIORITY

DECODER

Figure 54: PCA Interrupt System

CMOD

Address: D9H

Not bit addressable

Reset Value: 00h

BIT SYMBOL

CMOD.7

CIDL

CMOD.6

CMOD.5-3

CMOD.2-1

WDTE

-

CPS1,CPS0

CMOD.0

ECF

7

CIDL

6

WDTE

5

-

4

-

3

-

2

CPS1

1

CPS0

0

ECF

FUNCTION

Counter Idle Control: CIDL = 0 programs the PCA Counter to continue functioning during

Idle Mode. CIDL = 1 program it to be gated off during idle.

Watchdog Timer Enable: WDTE = 0 disables watchdog timer function on module 4.

WDTE = 1 enable it.

Reserved for future use. Should be set to 0 by user programs.

PCA Count Pulse Select:

CPS1

0

0

1

CPS0

0

1

0

Select PCA Input_______________

0 Internal Clock, f

OSC

/ 6

1 Internal Clock, f

OSC

/ 2

2 Timer 0 Overflow

1 1 3 External Clock at ECI/P1.2 pin ( max rate = f

OSC

/4)

PCA Enable Counter Overflow Interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disabled that function.

Figure 55: CMOD: PCA Counter Mode Register

70 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

CCON

Address: 0D8H

Bit addressable

Reset Value: 00h

BIT SYMBOL

CCON.7

CF

CCON.6

CCON.5

CCON.4

CCON.3

CCON.2

CCON.1

CCON.0

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

7

CF

6

CR

5

-

4

CCF4

3

CCF3

2

CCF2

1

CCF1

0

CCF0

FUNCTION

PCA Counter Overflow Flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software.

PCA Counter Run Control Bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off.

Reserved for future use. Should be set to 0 by user programs.

PCA Module 4 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 3 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 2 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 1 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 0 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software.

Figure 56: PCA Counter Control Register

71 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

CCAPMn

Address: CCAPM0 0DAH

CCAPM1 0DBH

CCAPM2 0DCH

CCAPM3 0DDH

CCAPM4 0DEH

Not bit addressable

Reset Value: 00h

BIT SYMBOL

CCAPMn.7

CCAPMn.6

-

ECOMn

CCAPMn.5

CCAPMn.4

CCAPMn.3

CAPPn

CAPNn

MATn

CCAPMn.2

CCAPMn.1

CCAPMn.0

TOGn

PWMn

ECCFn

7

-

6

ECOMn

5

CAPPn

4

CAPNn

3

MATn

2

TOGn

1

PWMn

0

ECCFn

FUNCTION

Reserved for future use. Should be set to 0 by user programs.

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1 a match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt.

T oggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle.

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.

Enable CCF Interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

Figure 57: CCAPMn: PCA Modules Compare/Capture Registers

ECOMn

0 x x x

1

1

1

1

CAPPn

0

1

0

1

0

0

0

0

CAPNn

0

0

1

1

0

0

0

0

MATn

0

0

0

0

TOGn

0

0

0

0

PWMn

0

0

0

0

ECCFn

0 x x x

Module Function

No Operation

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative-edge trigger on CEXn

16-bit capture by any transistion on

CEXn

16-bit software timer 1

1

0

1

0

1

0 x

0

0

1

0 x x

0 x

Table 16: PCA Module Modes (CCAPMn Register)

16-bit high speed output

8-bit PWM

Watchdog timer

6.9.1

PCA CAPTURE MODE

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH).

72 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

6.9.2

16-BIT SOFTWARE TIMER MODE

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register.

The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn

(CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

6.9.3

HIGH SPEED OUTPUT MODE

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set.

6.9.4

PULSE WIDTH MODULATOR MODE

All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPnL. When the value of the PCA CL SFR is less than the value in the module’s CCAPnL SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. this allows updating the PWM without glitches. The PWM and

ECOM bits in the module’s CCAPMn reg ister must be set to enable the PWM mode.

6.9.5

PCA WATCHDOG TIMER

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count.

Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog

is not needed. Figure 58 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers.

Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high.

73 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

WRITE

TO

CCAP4L

RESET

WRITE

TO

CCAP4H

1 0

CIDL WDTE -

CCAP4H (FEH) CCAP4L (EEH) MODULE 4

-

16-BIT COMPARATOR

MATCH

CPS1 CPS0 ECF

CMOD

(D9H)

INTERNAL

RESET

CH (F9H) CL (E9H)

PCA TIMER/COUNTER

ECOMn CAPPn

0

CAPNn

0

MATn

1

TOGn

X

PWMn

0

ECCFn

X

CCAPM4

(DEH)

Figure 58: PCA Watchdog Timer (Module 4 only)

In order to hold off the reset, the user has three options:

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.

The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.

The following shows the code for initializing the watchdog timer:

INIT_WATCHDOG:

MOV

MOV

MOV

ORL

MOV

SETB

RET

CCAPM4,#04Ch

CCAP4L,#0FFh

CCAP4H,#0FFh

CMOD,#040h

;Module 4 in compare mode

;Write to low byte first

;Before PCA counts up to FFFFh, these compare values must be changed

;Set the WDTE bit to enable the watchdog timer without changing the

;other bits in CMOD

;CALL the following WATCHDOG subroutine periodically.

CLR

MOV

EA

CCAP4L,#00

;Hold off interrupts

;Next compare value is within 255 counts of current PCA timer value

CCAP4H,CH

EA ;Re-enable interrupts

74 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user’s software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine shown above.

This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 2

16

count of the PCA timer.

75 Preliminary 2002 June 28

Philips Semiconductors

Extended Address Range Microcontroller

P87C51Mx2 User Manual

P87C51Mx2

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Copyright Philips Electronics North America Corporation 2002

All rights reserved. Printed in U.S.A.

Date of preliminary release: 06-02

76 Preliminary 2002 June 28

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents