IFX80471SKV Demo Board Users Manual

IFX80471SKV Demo Board Users Manual
I F X 8 047 1 S K V
Demo Board User’s Manual
Demoboard
Rev.1.0, 2012-05-15
Standard Power
Demo Board IFX80471
1
Abstract
Note: The following information is given as a guideline for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
This Application Note is intended to provide support for using the demo board of the Step-Down DC to DC
Controller IFX80471SKV. This document is written in order to help the reader understand the dimensioning
of the external components needed for the proper functioning of the DC/DC controller. It will also enable the
reader to change the external components to adapt the function of the controller to his/her application needs.
2
Introduction
Selection of appropriate external components and the layout of the PCB are key factors when designing
DC/DC applications for various industrial environments. The goal is to achieve optimum functionality with
minimum output voltage ripple and good EMC performance. This application note provides, as an example,
1) proposal for the components selection
2) recommendation for layout
Figure 1
Demoboard
Photo of the demo board assembled with the IFX80471SKV DC/DC Controller.
2
Rev.1.0, 2012-05-15
Demo Board IFX80471
Application schematic for Adjustable version
3
Figure 2 shows the minimum application circuit as proposed in the IFX80471 Datasheet which applies for the
adjustable output voltage version IFX80471SKV.
RSENSE=
VIN
L1 = 47 H
M1
47m
VOUT
to e.g. 5V rail
CIN1 =
100 F
CBDS=
220 nF
COUT =
RSO=
D1
100 F
RRO=
20k
11
13
RSI1=
CIN2 =
BDS
VS
7
RSI2=
VOUT
SO
9
FB
2
COMP
SI
6
SYNC GND
5
1
ON
RFB1=
RO
4
10
M1: Infineon BSO 613SPV
or Infineon BSP 613P
330k
3
GDRV
CS
SI_GND ENABLE
100k
Figure 2
12
IFX80471SKV
220nF
400k
14
to µC
22nF
8
RFB2=
430
47k
to µC
OFF
Minimum application circuit for IFX80471SKV.
The complete circuitry used for the demo board is shown in Figure 3. Compared to the minimum circuitry it:

covers a wider load current range

improves EMC performance

enables to use only one PCB to evaluate other voltage variants of the device
VIN
D2
L2
22 µH
R1
M1
22m
L1
33µH
VOUT
C4_1
4.7µF
C4_2
4.7µF
C1
C2
100nF 100 µF
R4
D1 220k
C8
220nF
R2
0
R5
47k
R6
0
C5
100µF
R12
5.1k
11
BDS
13 VS
C7
220nF
7
14
CS
12
GDRV
IFX80471SKV
2
FB
3
VOUT
COMP 8
SI
SI_GND SI_ENABLE SYNC GND RO
C3 R3
4
6
1
5
10
2.2nF 680
R11
R10
390k
68k
VEXT
R13
5.1k
SO 9
C6
100nF
SO
RO
SYNC
R8
0
Figure 3
Demoboard
Schematic of the demo board for IFX80471SKV.
3
Rev.1.0, 2012-05-15
Demo Board IFX80471
Table 1
Components recommendation – BOM for IFX80471SKV
Device
Supplier
Type
Value & Remark
L1
Coilcraft
DO-3340P-333
33µH, 2.0A, 80m
L2
Coilcraft
DO-3340P-223
C1
Various
Al-Electrolytic capacitor
22µH, 2.5A, 66m
100µF, 63V
Ceramic capacitor
X7R, 100nF, >60V
C2
C3
1
Ceramic capacitor
X7R, 2.2nF, 16V
C4_1, C4_2
TDK
Ceramic capacitor C4532X7R1H475M
X7R, 4.7µF, 50Vq
C5
EPCOS
Tantalum electrolytic capacitor
B45010D1076M506
Ceramic capacitor
Low ESR, ‘Speed Power’
C6
X7R, 100nF, 16V
C7
TDK
Ceramic capacitor C3216X7R2A224
X7R, 220nF, 100V
C8
Various
Ceramic capacitor
X7R, 220nF, 16V
C9
not assembled
Resistor
22m, ±1%
R1
R2,R6,R8
0
R3
Resistor
680
R4
Resistor
220k
R5
Resistor
47k
R10
Resistor
68k
R11
Resistor
390k
R12,R13
Resistor
R7,R9
not assembled
D1
ON
Schottky Diode
5.1k
MBRD 360, 3A, 60V
D2
Various
Diode, S3D
3A
P-channel MOSFET
BSP 613P
M1
3.1
2
About the IFX80471SKV demo board
The IFX80471SKV has open drain outputs at the pins RO and SO. The pull up resistors R12 and R13 on the
demo board are connected to the V_EXT pad. V_EXT should be connected to an appropriate pull up voltage
source (usually the microcontroller I/O voltage source). The pull up resistors have been assembled with a
value of R12=R13=5.1k This resistor value should be checked with respect to the actual I/O voltage and
microcontroller requirements. The driving capability of the reset output and sense output are described in the
datasheet (under “Electrical Characteristics”, item 5.1.40 and 5.1.55).
The synchronizing function is disabled by the 0 resistor R8 connecting pin 5 directly to GND. In case the
synchronizing function is needed make sure R8 is removed before connecting a TTL-Level frequency
source to the SYNC connector of the demo board.
1
2
Mounted on PCB back side
Pin 2 (GND) to be cut before assembly on demo board
Demoboard
4
Rev.1.0, 2012-05-15
Demo Board IFX80471
4
Dimensioning of the external components
The equations for the dimensioning of the external components L1, R1 are given in the datasheet in chapter
7, where the dimensioning of the feedback divider resistors R4 and R5 is discussed.
In this application note a practical approach how to apply these equations for given application requirements
is shown.
1.4
VOUT
IFX 80471 SKV
R SENSE = 50 m 
V V = 13 .5V
App .SCircuit Fig . 5
VOUT ,nom
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.25
0.5
0.75
1.0
1.25
1.5 1.75
ILOAD
A
Figure 4
Example of typ. characteristic of the output current limit (foldback).
4.1
Variable output voltage
For the IFX80471SKV variable device demo board we use the same output current target as for the fixed
voltage version: 2.0A, with permission to be in the foldback current limit range (see Fig. 4). The desired
output voltage should be typ. 7.10V.
We should now fix the feedback output voltage divider. The datasheet (chapter 7.3) allows a range from 5k
to 500k for R5 (corresponds to RFB2). We have selected a value of R5= 47k.
Using the feedback voltage value of 1.25V (item 5.1.12 of the electrical characteristics in the datasheet) we
can calculate R4 as
R4= 47k·(7.10V/1.25V -1) = 220k .
The following procedure is very similar to component dimentioning for the 5V versions. The shunt resistor is
given by the current limitation target.
From the datasheet (Chapter 7.8.2) the equation for R1 is:
R1 = VLIM / 2·IPEAK;PWM .
VLIM is specified in the electrical characteristics as item 5.1.27 ‘peak current limit threshold voltage’,
50mV…90mV. To get the worst case (lowest) current we apply the equation above, but we leave out the
factor 2 since we have accepted to enter the foldback part of the current characteristic. We get
R1_max= 50mV/2.0A= 25m.
We have to take into account that we have not yet considered the ripple current which reduces the maximum
available load current according to the equation
IPeak,PWM=ILoad+0.5 · I
Demoboard
5
Rev.1.0, 2012-05-15
Demo Board IFX80471
To continue we select R1 as
R1=22m
Using this value we can calculate the maximum allowed ripple current, assuming still a load current of 2.0A:
I _ max 
50mV / 22m  2.0A
= 545mA.
0.5
In order to keep the output voltage ripple as low as possible we choose a ripple current of 300mA in the
typical operation condition with 13.5V VBAT, corresponding to 15% of the 2.0A maximum load current. In the
datasheet, chapter 7.8.1 we find the equation,
I 
( VIN  VOUT )  VOUT
fSW  VIN  L1
which we now use to define the buck inductance L1.
L1 
(13.5V  5.0V)  5.0V
 30H .
370kHz 13.5V  300mA
We select the next norm value:
L1=33µH.
Now it remains to check if the stability conditions arising from the slope compensation are fulfilled. The
inequation from chapter 7.8.1 in the datasheet gives us
(2.0 x10 4 )  (VOUT )  ( RSENSE)  L1  (4.0 x10 4 )  (VOUT )  ( RSENSE)
(2.0 x10 4 )  (7.1V )  (22m)  L1  (4.0 x10 4 )  (7.1V )  (22m)
31H  L1  62H ,
which confirms that our selected inductance is good to maintain stability.
5
Components placement and PCB layout of the Demo Board
For EMC optimization the demo board comes with an input -Filter (C4, L2, and C1). Thus emission from
the VBAT line is largely suppressed.
For proper operation and to avoid stray inductance paths the external catch diode, the Buck inductance and
the input capacitor CIN1 have to be connected as close as possible to the PMOS device. Also the GDRV path
from the controller to the switching transistor should be as short as possible. Best suitable for the connection
of the cathode of the catch diode and one terminal of the inductance would be a small plain located next to
the drain of the PMOS.
The GND connection of the catch diode must be also as short as possible. In general the GND level should
be implemented as surface area over the whole PCB as second layer.
The most sensitive points for coupled switching noise are the feedback path to the pins FB and VOUT and
the input path. Also switching noise coupled back to the SYNC input must be avoided. These paths should
be kept away from the switching node. On the demo board also the ceramic capacitor C6 helps to suppress
potential noise on the feedback line.
Demoboard
6
Rev.1.0, 2012-05-15
Demo Board IFX80471
Figure 5
Demoboard
PCB Layout Front and Back
7
Rev.1.0, 2012-05-15
Demo Board IFX80471
6
General Layout Recommendations
It is important to follow the layout recommendations given in this section. The commutation circuit input
capacitor C1, the PMOS M1 and the free-wheeling diode D1 should be as compact as possible in order to
have low inductance. The area of the connection M1-L1-D1 should be as small as possible. This can be
seen in the Figure 7 as the green highlighted area and the blue trace respectively. The Input and Output
capacitors should have a short low inductance link.
D1
C
C6
Figure 6
Layout Recommendations (Blue Line: Short Connection, Green: Small Area)
The supply voltage should be routed via the pins of the input capacitors. The output voltage should be routed
nd
via the pins of the output capacitors. It is recommended to design the ground as a ground area in a 2 layer.
There should be a direct connection of all GND terminals of input capacitors, free-wheeling diode D1, output
capacitors, the IC, RC elements and filter capacitors. Use a star shaped ground link to avoid ground looping.
Separate the ground system; connect to external wiring ground only via a single trace. Connect the current
sensing IC terminals (pin 13 and 14) directly to the shunt R1 and design to be short.
Please also make sure the following pins are free from any switching noise:
Demoboard
8
Rev.1.0, 2012-05-15
Demo Board IFX80471

Pin 2: [FB], Feedback Input. Keep the PCB traces far from switching nodes to prevent from coupled
switching noise. Use of low-ESR ceramic capacitors recommended.

Pin 3: [VOUT], Buck Output Voltage Input. Use low-ESR ceramic capacitors.

Pin 5: [SYNC], Input for external frequency synchronization.

Pin 8: [COMP], Compesation Input.

Pin 13: [VS], Device Supply Input. Spikes at VS may influence the Bandgap reference generating
positive feedback that might cause instability. Usage of low-ESR ceramic capacitors in the range 220nF
to 1µF is recommended.
For further details about the pin definitions and functions please refer to section 3.2 of the IFX80471
datasheet.
Additional Information
7


For further information please refer to www.infineon.com/industrial-standard
For technical support please write to [email protected]
Demoboard
9
Rev.1.0, 2012-05-15
Demo Board IFX80471
AP Number
Revision History:
2012-05-15
Previous Version:
none
1.0
Demoboard
Rev. 1.0
Initial Rev.
10
Rev.1.0, 2012-05-15
Edition 2009
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
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QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION
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IN THIS APPLICATION NOTE.
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