Khepera bus and turret specifications - K
8 March 2000
Khepera bus and turret specifications
Khepera bus and turret specifications
Rev. 1.2
Edoardo Franzi LAMI-EPFL
INF-Ecublens
CH-1015 Lausanne
[email protected]
Abstract
Khepera modularity allows to realise, in a quite simple way, turrets for any
kind of extensions. Simple experimental turrets can be interfaced using the
parallel bus scheme (a classical microprocessor interface). More complicate
turrets (where a local processing is necessary) need to use a local multimicrocontroller network scheme. In this document, only the electrical and
the mechanical specifications of the Khepera busses will be discussed and
presented. See [Fra95a] to get a complete information about the multi-microcontroller network.
The architecture and the definition of the bus schemes of Khepera will be
presented first. Detailed specifications of each bus will be explained (electrical, temporal and mechanical).
All the available possibilities to build turrets will be discussed and presented
at the end of this document.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
1
8 March 2000
1
Khepera bus and turret specifications
Generalities
1.1
The bus architecture
Figure 1 shows the general topology of the busses used in the Khepera projects. The multibus architecture can be seen as a complicate way to extend the capabilities of Khepera,
but this architecture was designed to ensure the best compromise between the modularity
exigences and the place at the hand on the turrets.
Parallel turrets
Serial turrets
Turret #n
Turret #n [0..31]
Turret #0
Turret #0
Small piggy.back bus
Khepera main
CPU (68331)
8-bit main Khepera CPU bus
Khepera main
motion and power
Local network bus
Miscellaneous bus
Figure 1: General topology of the bus scheme of Khepera
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
2
Khepera bus and turret specifications
8 March 2000
2
The main bus of Khepera
In this section the main bus of Khepera will be presented. Different signals are used to
manage some basic functionnalities of Khepera (private propriety). For instance, some
“input capture” are used to manage the incremental counters of the wheels, or the “SPI”
interface is used to control the on-board A/D converter and to manage the local multimicrocontroller network; for this reason, they have to be used with care.
Figure 2 shows how the signals of main bus are distributed on the surface of the
Khepera board.
12
11
10
9
8
7
6
22
49
24
21
52
5
23
20
51
3
1
47
37
2
4
48
38
36
39
50
53
Top view
54
46
43
41
40
42
55
56
57
45
25
19
18
17
16
15
14
13
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
/Reset
VCC_Ext
GND
VCC
GND
VRef
GNA
Charger
PWM0
Dir0
PH0A
PH0B
PWM1
Dir1
PH1A
PH1B
/CSCAP
D8
D9
D10
D11
D12
D13
Delta_CAP
L_Ambiante
CH3
CH4
CH5
PAI
D14
D15
A0
A1
A2
R/W
/CSExt
F7
/IRQ6
MISO
MOSI
SCK
/CSCOM
TxD
RxD
A3
A4
A5
Figure 2: Distribution of the signals of the bus1
The signals of the bus are distributed in different groups, defined by their own
function.
1. The followed signals are available on the CPU board of Khepera; however they are not spread to
the top of the bus:
“Charger”, “Delta_CAP”, “L_Ambiante”, “/CSCAP”, “PWM0”, “PWM1”, “Dir0”, “Dir1”,
“PH0A”, “PH0B”, “PH1A”, “PH1B”.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.1
Signals of the power group
These signals are used to power both the minirobot and the extension turrets. Table 1 and
figure 3 show all the signals that are members of this group.
Signal
TP
I/O
Remarks
Comment
VCC_Ext
2
Power I
4.1 to 6V
Input main power (coming from the six pin
serial connector). It powers the robot if the
batteries switch is OFF.
VCC
4
Power O
4.1 to 6V
Main power (under the switch control). The
power is taken from either “VCC_Ext” signal
(switch off) or to the batteries (switch on).
GND
3, 5
Power O
-
General digital ground.
Table 1: Signal of “power group”
Top view
12 11 10 9 8 7 6
22
24 21
23 20
47
48
53
54
46
49
52 5
51 3 1
37 2 4
38 36
Power group
39 50 44
43 41 40 42 55 56 57 45
25 19 18 17 16 15 14 13
Figure 3: Location of the signals of the “power group”
During the design of the extension turrets, a particular attention has to be given to
the power consumption of the hardware. Khepera can be powered with the embarked
four NiCd accumulators of 110mA/h to allow autonomous works. To increase the operating time when Khepera works in this mode, it is a good idea to get under software control
the power of some parts of the design.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.2
Signals of the analog group
These signals are used to control all the analog parts of Khepera. Table 2 and figure 4
show all the signals that are members of this group.
Signal
TP
I/O
Remarks
Comment
VRef
6
Analog O
4.096V
Reference of the A/D converter. The maximum
allowable current is 1mA.
GNA
7
Analog O
-
General analog ground. All the extension turrets which use CH3..CH5 have to refer these
inputs to this potential.
Charger
8
Analog I
100kΩ
Pull-down
Reserved to detect if a charger is plugged.
Delta_CAP
24
Analog I
-
Value of the light variation of the 8 I.R..
L_Ambiante
25
Analog I
-
Value of the ambient light oh the 8 I.R..
CH3
36
Analog I
max. 4.3V
User analog input.
CH4
37
Analog I
max. 4.3V
User analog input.
CH5
38
Analog I
max. 4.3V
User analog input.
Table 2: Signal of “analog group”
Top view
12 11 10 9 8 7 6
22
24 21
23 20
47
48
53
54
46
49
52 5
51 3 1
37 2 4
38 36
Analog group
39 50 44
43 41 40 42 55 56 57 45
25 19 18 17 16 15 14 13
Figure 4: Location of the signals of the “analog group”
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.3
Signals of the motion group
These signals are used to control the motion of Khepera. Table 3 and figure 5 show all
the signals that are members of this group.
Signal
TP
I/O
Remarks
Comment
PWM0
9
Digital O
3.3kΩ
Pull-down
PWM to control the power of the right motor.
Dir0
10
Digital O
3.3kΩ
Pull-down
Control of the direction of the right motor.
PH0A
11
Digital I
4.7kΩ
Pull-up
Signal used to count the pulses coming from
the right incremental sensor.
PH0B
12
Digital I
4.7kΩ
Pull-up
Signal used to count the pulses coming from
the right incremental sensor.
PWM1
13
Digital O
3.3kΩ
Pull-down
PWM to control the power of the left motor.
Dir1
14
Digital O
3.3kΩ
Pull-down
Control of the direction of the left motor.
PH1A
15
Digital I
4.7kΩ
Pull-up
Signal used to count the pulses coming from
the left incremental sensor.
PH1B
16
Digital I
4.7kΩ
Pull-up
Signal used to count the pulses coming from
the left incremental sensor.
Table 3: Signal of “motion group”
Top view
12 11 10 9 8 7 6
22
24 21
23 20
47
48
53
54
46
49
52 5
51 3 1
37 2 4
38 36
Motion group
39 50 44
43 41 40 42 55 56 57 45
25 19 18 17 16 15 14 13
Figure 5: Location of the signals of the “motion group”
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.4
Signals of the CPU group
These signals are used by the different interfaces of Khepera (ROM, RAM, I/O, etc.).
Table 4 and figure 6 show all the signals that are members of this group.
Signal
TP
I/O
Remarks
Comment
/Reset
1
Digital I/O
-
General reset of the Khepera.
/CSCAP
17
Digital O
-
Chip select used to control the 8 I.R. interface.
D8
18
Digital I/O
3.3kΩ
Pull-down
Data 8 of the processor. The pull-down is necessary during the start-up sequence of the
CPU.
D9
19
Digital I/O
3.3kΩ
Pull-down
Data 9 of the processor. The pull-down is necessary during the start-up sequence of the
CPU.
D10
20
Digital I/O
-
Data 10 of the processor.
D11
21
Digital I/O
-
Data 11 of the processor.
D12
22
Digital I/O
-
Data 12 of the processor.
D13
23
Digital I/O
-
Data 13 of the processor.
D14
40
Digital I/O
-
Data 14 of the processor.
D15
41
Digital I/O
-
Data 15 of the processor.
A0
42
Digital O
-
Address 0 of the processor.
A1
43
Digital O
-
Address 1 of the processor.
A2
44
Digital O
-
Address 2 of the processor.
R/W
45
Digital O
-
R/W of the processor.
/CSExt
46
Digital O
-
User chip select used to control extension turrets.
/IRQ6
48
Digital I
3.3kΩ
Pull-up
User interruption. This interruption is level
sensitive.
A3
55
Digital O
-
Address 3 of the processor.
A4
56
Digital O
-
Address 4 of the processor.
A5
57
Digital O
-
Address 5 of the processor.
Table 4: Signal of “CPU group”
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
Top view
12 11 10 9 8 7 6
22
24 21
23 20
47
48
53
54
46
49
52 5
51 3 1
37 2 4
38 36
CPU group
39 50 44
43 41 40 42 55 56 57 45
25 19 18 17 16 15 14 13
Figure 6: Location of the signals of the “CPU group”
Figure 7 shows the main timings of the CPU accesses. All the bus acknowledges
are under the control of the SIM unit and cannot be modified. The timings which are
shown are available only for a bus frequency of 16.78MHz (normal frequency operations
of Khepera). If the bus frequency is decreased to 8MHz by the BIOS call-system
“var_cpu_speed(1)”, the access duration will be increased of a two factor. More information about timings is available in [Mot91].
62nS
S0 S1 S2
W1
W2
W3 S3 S4 S5
S0 S1 S2
W1
W2
W3 S3 S4 S5
Ck
A0..A5
/CSExt
R/W
D8..D15
5nS 15nS
a) Read cycle
15nS
15nS
b) Write cycle
!!! The signal Ck is not available on the bus.
It is shown only to illustrate the time relations
between the signals.
Figure 7: Main timings of the “CPU group” signals
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.5
Signals of the communication group
These signals are used to control the communications of Khepera. Table 5 and figure 8
show all the signals that are members of this group.
Signal
TP
I/O
Remarks
Comment
PAI
39
Digital I
100kΩ
Pull-down
Message acknowledge used in the local multimicrocontroller network scheme.
F7
47
Digital O
3.3kΩ
Pull-up
Message strobe used in the local multi-microcontroller network scheme.
MISO
49
Digital I
-
Data input used in the local multi-microcontroller network scheme.
MOSI
50
Digital O
-
Data output used in the local multi-microcontroller network scheme.
SCK
51
Digital O
-
Clock used in the local multi-microcontroller
network scheme.
/CSCOM
52
Digital O
-
Chip select used to control the different turrets
in the local multi-microcontroller network
scheme.
TxD
53
Digital O
-
Asynchronous transmitting data.
RxD
54
Digital I
100kΩ
Pull-down
Asynchronous receiving data.
Table 5: Signal of “communication group”
Top view
12 11 10 9 8 7 6
22
24 21
23 20
47
48
53
54
46
49
52 5
51 3 1
37 2 4
38 36
Communication group
39 50 44
43 41 40 42 55 56 57 45
25 19 18 17 16 15 14 13
Figure 8: Location of the signals of the “communication group”
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
9
Khepera bus and turret specifications
8 March 2000
Figure 9 shows the main timings and the network cycles used in the multi-microcontroller communication scheme. More information about timings is available in
[Mot91].
Data out changed
Data in captured
/CSCOM
SCK
MSB
MOSI
LSB
MISO
1µS
0.952µS
2µS
/CSCOM
SCK
#2
MOSI
1
2
11
MISO
12
13
F7
PAI
500µs
A
t
10µs
B
C
A. Khepera signals that after 500µs it starts a message
B. Each byte sent has to be acknowledged by the turret
C. The turret signals that a byte is now ready and Khepera can get it
Figure 9: Main timings and cycles used in the multi-microconroller scheme
The complete implementation of the communication layers of the network protocol
coupled with an example of an intelligent turret design is available in [Fra95a] [Fra95b].
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
10
Khepera bus and turret specifications
8 March 2000
2.6
2.6.1
2.7
Turret electrical specifications
Absolute maximum rating (for one turret)
Supply voltage (Vcc):
-0.5V to 6.5V
Load on the power:
100mA1
Load by signal (digital)
2 HC loads
Load by signal (analog)
1mA (only on VRef output)
DC output voltage (digital) -0.5V to Vcc+0.5V
DC output voltage (analog) -0.2V to VRef+0.2V
Turret mechanical specifications
2.7.1
Turrets compatibility
Figure 10 shows the main constraint to respect to ensure a good mechanical compatibility between all the turrets.
Bus connection
Highest component
PCB Board
2 mm max.
2.6 mm min.
No component over the
Khepera jumpers. Min. 3.5 mm.
lowest component
Figure 10: Mechanical bus constraint
1. When
the power consumption excede 25mA, it is a good practice to forsee a system to cut-off
the power of some fat interface part under soft control.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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Khepera bus and turret specifications
8 March 2000
2.7.2
Bus placement
Figure 11 shows the exact position of all the bus interconnections. The “Gerber” file used
by the CAO systems can be requested at K-Team S.A. company.
0.100
0.750
0.650
0.300
0.200
0.300
0.400
0.900
0.600
2.200
0.275
0.300
0.100
0.800
0.100
0.350
0.350
All the measures are in inches
Figure 11: Bus placement
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
12
Khepera bus and turret specifications
8 March 2000
3
Types of turrets
To get the best modularity with the extentions it was necessary to define three types of
turrets: the parallel, the serial and the top (parallel or serial) ones.
3.1
The parallel turrets
These turrets are intended to realise in a very fast way simple extensions for Khepera. A
basic know-how in the microprocessor interface field (hardware) is required for building
this kind of turrets.
Table 6 shows all the bus signals needed to spread these turrets to allow a multiple
turret systems. The designer has to care particularly about the analog inputs named
“CH3, CH4 and CH5”. The underlined signals are directly used by this kind of turret.
Signal
TP
I/O
Signal
TP
I/O
Group
VCC_Ext
2
Power I
GND
3
Power O
Power
VCC
4
Power O
GND
5
Power O
VRef
6
Analog O
CH4
37
Analog I
GNA
7
Analog O
CH5
38
Analog I
CH3
36
Analog I
----
----
----
/Reset
1
Digital I/O
A0
42
Digital O
D8
18
Digital I/O
A1
43
Digital O
D9
19
Digital I/O
A2
44
Digital O
D10
20
Digital I/O
R/W
45
Digital O
D11
21
Digital I/O
/CSExt
46
Digital O
D12
22
Digital I/O
/IRQ6
48
Digital I
D13
23
Digital I/O
A3
55
Digital O
D14
40
Digital I/O
A4
56
Digital O
D15
41
Digital I/O
A5
57
Digital O
PAI
39
Digital I
SCK
51
Digital O
F7
47
Digital O
/CSCOM
52
Digital O
MISO
49
Digital I
TxD
53
Digital O
MOSI
50
Digital O
RxD
54
Digital I
Analog
CPU
Communication
Table 6: Bus signals necessary for parallel turrets
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
13
Khepera bus and turret specifications
8 March 2000
All the communications between Khepera and these turrets are immediately under
the BIOS or under the “SerCom” protocol control (see [Fra93]). For this approach the
control of all the devices of these turrets is realised by the normal CPU bus accesses.
To avoid compatibility problems between K-Team and user designs, here is the
CPU address reservation space (table 7) that the user has to respect for his designs.
/CSExt
A5
A4
A3
A2
A1
A0
Comment
0
0
x
x
x
x
x
User free address space.
0
1
x
x
x
x
x
Address space reserved for K-Team extension turrets.
Table 7: Address space reservation for parallel turrets
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
14
Khepera bus and turret specifications
8 March 2000
3.2
The serial turrets
The local multi-microcontroller network is the most important way to realise performant
extension turrets on Khepera. This allows the connection of intelligent turrets equipped
with their own local microcontroller and the migration of conventional or neural preprocessing software layers closer to the sensors and actuators. A good know-how in the
microprocessor interface field (hardware and software) is required for building this kind
of turrets.
Table 8 shows all the bus signals needed to spread these turrets to allow a multiple
turret systems. The designer has to care particularly about the analog inputs named
“CH3, CH4 and CH5”. The underlined signals are directly used by this kind of turret.
Signal
TP
I/O
Signal
TP
I/O
Group
VCC_Ext
2
Power I
GND
3
Power O
Power
VCC
4
Power O
GND
5
Power O
VRef
6
Analog O
CH4
37
Analog I
GNA
7
Analog O
CH5
38
Analog I
CH3
36
Analog I
----
----
----
/Reset
1
Digital I/O
A0
42
Digital O
D8
18
Digital I/O
A1
43
Digital O
D9
19
Digital I/O
A2
44
Digital O
D10
20
Digital I/O
R/W
45
Digital O
D11
21
Digital I/O
/CSExt
46
Digital O
D12
22
Digital I/O
/IRQ6
48
Digital I
D13
23
Digital I/O
A3
55
Digital O
D14
40
Digital I/O
A4
56
Digital O
D15
41
Digital I/O
A5
57
Digital O
PAI
39
Digital I
SCK
51
Digital O
F7
47
Digital O
/CSCOM
52
Digital O
MISO
49
Digital I
TxD
53
Digital O
MOSI
50
Digital O
RxD
54
Digital I
Analog
CPU
Communication
Table 8: Bus signals necessary for serial turrets
All the communications between Khepera and these turrets are immediately under
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
15
8 March 2000
Khepera bus and turret specifications
the BIOS or under the “SerCom” protocol control (see [Fra93]). For this approach the
contol of all the devices of these turrets is realised by writing a dedicated software layer
(on the local microcontrollers) to realise the interface between Khepera and the different
devices of the turrets.
To avoid compatibility problems between K-Team and user designs, here is the turret number reservation (table 9) that the user has to respect for his designs.
Turret ID
Comment
0..23
Reserved for K-Team serial turrets. See below.
1
Gripper.
2
K213 64x1 pixel vision.
3
Laser GPS.
4
Radio link.
----
----
24..31
User free ID numbers.
Table 9: ID numbers for serial turrets
3.3
The top turrets (a special case)
It is sometimes necessary to realise turrets at the top of Khepera (ex. vision). This kind of
turrets can be either parallel or serial.
As these turrets are at the top, it is not necessary to spread all the bus signals. However, some minimum signals are necessary to ensure the electrical functionality and the
mechanical stability.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
16
8 March 2000
Khepera bus and turret specifications
References
[Fra93]
"The low level BIOS of Khepera", Edoardo Franzi, Internal report R93.28, LAMI-EPFL,
Lausanne, 1993.
[Fra95a] "The multi-microcontroller network of Khepera", Edoardo Franzi, Internal report, K-Team S.A.,
Lausanne, 1995.
[Fra95b] "Building intelligent turret for Khepera", Edoardo Franzi, Internal report, K-Team S.A.,
Lausanne, 1993.
[Mon93a] “Mobile robot miniaturization: A tool for investigation in control algorithms”, Francesco Mondada, Edoardo Franzi, and Paolo Ienne, In proceedings of the Third International Symposium on
Experimental Robotics, Kyoto, Japan, 1993, presented paper.
[Mon93b] “Biologically Inspired Mobile Robot Control Algorithm”, Francesco Mondada and Edoardo
Franzi, In proceedings of NRP23-Symposium on Artificial Intelligence and Robotics, pages 4759, Zürich, October 22 1993.
[Mot91] "MC68331 User’s Manual", Ref. MC68331UM/AD, Motorola INC., 1991.
Edoardo Franzi, K-Team, LAMI-EPFL
[email protected]
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