Stellaris Development Board User`s Manual and Schematics

Stellaris Development Board User`s Manual and Schematics
Stellaris® Family
Development Board
U S E R ’S M A N U A L
DM - LM3SF AM-0 4
C opyr ight © 2005- 2007 Lumi nary Micro , Inc.
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to
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Copyright © 2006-2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and the Luminary Micro logo is a trademark
of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a
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Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
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Stellaris® Family Development Board User’s Manual
Revision History
This table provides a summary of the document revisions.
Date
Revision
Description
March 2006
00
Initial release of doc to customers.
May 2006
01
Release of DB48 daughterboard and documentation.
May 2006
02
Added missing DB48 schematics to board manual PDF.
July 2006
03
Switched DB48 Layout 1 and Layout 2 figures so most current board is first.
Added QEI text to Headers paragraph in Chapter 1.
February 2007
February 6, 2007
04
Release of revision 3 of motherboard, which adds two headers: JP34 and JP35.
3
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Stellaris® Family Development Board User’s Manual
Table of Contents
Chapter 1: Stellaris® Family Development Board ......................................................................................... 9
Features.............................................................................................................................................................. 9
Block Diagram .................................................................................................................................................. 10
Functional Description ...................................................................................................................................... 11
Daughterboard .............................................................................................................................................. 11
UART ............................................................................................................................................................ 11
Headers ........................................................................................................................................................ 11
Potentiometer................................................................................................................................................ 11
Photocell ....................................................................................................................................................... 11
User LEDs..................................................................................................................................................... 11
User Pushbutton ........................................................................................................................................... 11
JTAG Debug Connector................................................................................................................................ 12
USB Debug ................................................................................................................................................... 12
I2C EEPROM Memory.................................................................................................................................. 12
SPI Flash Memory ........................................................................................................................................ 12
Buzzer........................................................................................................................................................... 12
Real-Time Clock ........................................................................................................................................... 12
External Reset .............................................................................................................................................. 12
Prototype Area .............................................................................................................................................. 12
Peripheral Device Controller (PDC) .............................................................................................................. 12
Power Supply................................................................................................................................................ 13
Motherboard Layout...................................................................................................................................... 13
Development Board Configuration.................................................................................................................... 14
Daughterboard Installation............................................................................................................................ 14
UART ............................................................................................................................................................ 14
SPI Port (On-Board Peripherals) .................................................................................................................. 14
I2C Port ......................................................................................................................................................... 14
Buzzer........................................................................................................................................................... 14
LCD Panel, DIP Switch, LEDs, and GPIOs .................................................................................................. 14
User Pushbutton ........................................................................................................................................... 15
User LEDs..................................................................................................................................................... 15
Photocell ....................................................................................................................................................... 15
Potentiometer................................................................................................................................................ 15
JTAG Debug Connector................................................................................................................................ 15
USB Debug ................................................................................................................................................... 15
32.768-KHz Clock Oscillator ......................................................................................................................... 15
Reset Switch ................................................................................................................................................. 16
GPIO Headers .............................................................................................................................................. 16
Power............................................................................................................................................................ 16
Peripheral Device Controller (PDC) .................................................................................................................. 16
Stellaris Microcontroller to PDC Interface ..................................................................................................... 17
PDC I/O......................................................................................................................................................... 17
PDC Registers .............................................................................................................................................. 18
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SPI Protocol .................................................................................................................................................. 19
Chapter 2: DB28 Daughterboard ................................................................................................................... 21
Features............................................................................................................................................................ 21
Block Diagram .................................................................................................................................................. 21
Daughterboard Interface................................................................................................................................... 21
Daughterboard Layout ...................................................................................................................................... 22
Shunt Jumper ................................................................................................................................................... 23
Development Board Signal Usage.................................................................................................................... 24
Chapter 3: DB48 Daughterboard ................................................................................................................... 27
Features............................................................................................................................................................ 27
Block Diagram .................................................................................................................................................. 27
Daughterboard Interface................................................................................................................................... 27
Daughterboard Layout ...................................................................................................................................... 28
Shunt Jumpers.................................................................................................................................................. 30
Development Board Signal Usage.................................................................................................................... 31
Appendix A: Contact Information ................................................................................................................. 35
Appendix B: Schematics................................................................................................................................ 37
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Stellaris® Family Development Board User’s Manual
List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 2-1.
Figure 2-2.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Stellaris® Family Development Board Block Diagram .................................................................. 10
Stellaris Family Motherboard Layout ............................................................................................ 13
PDC Timing Diagrams................................................................................................................... 20
DB28 Daughterboard Block Diagram ............................................................................................ 21
DB28 Daughterboard Layout......................................................................................................... 23
DB48 Daughterboard Block Diagram ............................................................................................ 27
DB48 Daughterboard Layout 1 (R3).............................................................................................. 29
DB48 Daughterboard Layout 2 (R2).............................................................................................. 30
February 6, 2007
7
List of Tables
Table 1-1.
Table 1-2.
Table 1-3.
Table 1-4.
Table 2-1.
Table 2-2.
Table 2-3.
Table 3-1.
Table 3-2.
Table 3-3.
8
Possible Board Power Sources..................................................................................................... 16
Stellaris Microcontroller to PDC Interface ..................................................................................... 17
Peripheral to PDC Interface .......................................................................................................... 17
PDC Registers............................................................................................................................... 18
DB28 Daughterboard Interface ..................................................................................................... 22
Jumper Settings for DB28 Daughterboard .................................................................................... 23
Development Board Signals Used by DB28 Daughterboard......................................................... 24
DB48 Daughterboard Interface ..................................................................................................... 28
Jumper Settings for DB48 Daughterboard .................................................................................... 30
Development Board Signals Used by DB48 Daughterboard......................................................... 31
February 6, 2007
C H A P T E R 1
Stellaris® Family Development Board
The Stellaris® Family Development Board provides a platform for product development. Hardware
and software engineers use this board for evaluation of Stellaris™ family microcontroller features
and functionality, and for software development.
The development board includes the Stellaris motherboard and a daughterboard with a Stellaris
family microcontroller. The DB28 daughterboard is available for 28-pin SOIC devices, and the
DB48 daughterboard is available for 48-pin LQFP devices. These daughterboards are described
in Chapter 2, “DB28 Daughterboard” on page 21 and Chapter 3, “DB48 Daughterboard” on page
27.
Features
The Stellaris® Family Development Board includes the following features. Note that not all
features are implemented on all Stellaris microcontrollers.
„
Daughterboards enable support for multiple package/pin-out options
„
Two UART transceivers and DB9 male connectors
„
All I/O available on headers
„
One potentiometer and one photocell for driving the Analog-to-Digital Converter (ADC) and
comparator inputs
„
Eight user LEDs and one pushbutton for use with the Stellaris GPIOs
„
Standard ARM® 20-pin JTAG debug connector
„
USB 2.0 full speed interface allows JTAG/SWD debug without in-circuit emulator (ICE)
„
8-Kbit I2C EEPROM memory
„
1-Mbit SPI-based flash memory
„
One buzzer for PWM use
„
32.768-KHz oscillator for real-time clock
„
External reset switch and power-on reset supervisor
„
5-V and 3.3-V LED power indicators
„
User-prototype area
„
Peripheral Device Controller (PDC) CPLD for interface with the following:
– 16 character by 2-line LCD display
– 8 status LEDs
– 8-position dual-inline package (DIP) switch
– 24 GPIOs
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Stellaris® Family Development Board
Block Diagram
Figure 1-1.
Stellaris® Family Development Board Block Diagram
Stellaris
Daughterboard
Connectors
RESET
UART0
JTAG
UART1
Photocell
ADC[0/2/4/6]
C0+/C1+/C2+
ADC[1/3/5/7]
Port Headers
PA
PB
PC
PD
PE
I2C Bus
C0-/C1-/C2USB
EEPROM
Flash
Potentiometer
3.3 V
Regulator
Expansion
Headers
SPI Bus
User LEDs
PDC
User
Pushbutton
GPIOX
GPIOY
GPIOZ
GPIOs
DIP Switch
Buzzer
LCD Panel
LEDs
Motherboard
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Stellaris® Family Development Board User’s Manual
Functional Description
Daughterboard
The daughterboard contains the Stellaris microcontroller and connects to the motherboard with
four 21-pin connectors. The Stellaris PLL clock is generated from a 6-MHz crystal provided on pin
sockets for easy crystal changes. An optional SMA connector can be used to drive an external
clock source.
UART
Two UART transceivers and DB9 connectors are provided to connect with the Stellaris
microcontroller UART peripherals. The UART0 peripheral (TX, RX) is included in all Stellaris
microcontrollers; UART1 is available in all 48-pin microcontrollers except the LM3S301. On the
LM3S101, LM3S102 and LM3S301, UART1 is available for external use.
Headers
All Stellaris I/O signals are available on five 8-pin GPIO headers labeled Port A through Port E to
match the Stellaris microcontroller GPIO ports. For each port header, pin 1 is bit 0 and pin 8 is bit 7
of the corresponding Stellaris GPIO. For example, Port B pin 1 is PB0 and Port B pin 8 is PB7 of
the Stellaris microcontroller. Note that ports A and E have only six I/O signals, with the remaining
two header pins connected to ground. Jumper shunts are used to connect Stellaris signals to onboard devices to allow connect/disconnect. Stellaris signals can be rewired with the included flywires.
There are also two 20-pin expansion headers (J9 and J22). Header J9 is intended primarily as an
interface for a motor driver board, and includes all the Stellaris PWM outputs, QEI inputs, analog
comparator inputs, and three ADC inputs. Header J22 has the remaining Stellaris signals, and
includes UART, SSI, I2C, JTAG, and timer CCP input signals.
NOTE: PWM, QEI, ADC, I2C, and analog comparators are available on select Stellaris
microcontrollers.
Potentiometer
One potentiometer is included to drive selected Analog-to-Digital Converter (ADC) inputs and/or
analog comparator inputs. The voltage range is 0 to 3.0. Shunt headers are used for signal
selection.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
Photocell
One photocell is included to drive selected ADC inputs and/or analog comparator inputs. The
voltage range is 0 to 3.0. Shunt headers are used for signal selection.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
User LEDs
Eight user LEDs (ULED0-ULED7) are provided for general use. Headers are provided for
connectivity.
User Pushbutton
One user pushbutton (SW3) is provided for general use. A header is provided for connectivity.
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Stellaris® Family Development Board
JTAG Debug Connector
A standard 20-pin connector for JTAG debug is provided. This port is also used to access the
Serial-Wire Debug (SWD) interface of the Stellaris microcontroller. When using this connector, the
USB interface cannot be used for JTAG/SWD debug (USB can still be used for providing board
power). A shunt jumper at location JP31 may be required when using this port.
USB Debug
A USB 2.0 full-speed interface provides debug capability via JTAG or SWD without the need for an
ICE. Note that use of this interface requires installation of the corresponding USB drivers. When
using this interface, the 20-pin JTAG connector cannot be used for JTAG/SWD debug. Ensure that
no shunt jumper is present at location JP31.
I2C EEPROM Memory
An 8-Kbit I2C memory is included for use with the Inter-Integrated Circuit (I2C) bus interface. A
jumper block is provided for connecting this memory.
NOTE: The I2C interface is available on select Stellaris microcontrollers.
SPI Flash Memory
A 1-Mbit SPI flash memory is included for use with the Serial Port Interface (SPI) port. A jumper
block is provided for connecting this memory.
Buzzer
A buzzer is provided for use with one of the PWM outputs.
Real-Time Clock
A 32.768-KHz crystal oscillator generates a clock signal that can be used to drive the Stellaris realtime clock. Shunt jumpers on the daughterboard can be used to connect this clock source.
External Reset
The external reset is implemented with a reset switch SW2 connected to a reset supervisor circuit,
and provides a system reset signal.
Prototype Area
A prototype area is provided for implementing user circuits. To supply power, there are power and
ground rows. The prototype area is indicated on the board with a Luminary Micro logo (see
Figure 1-2 on page 13).
Peripheral Device Controller (PDC)
A Peripheral Device Controller (PDC) implemented with a CPLD is accessible via the SPI interface
and provides access to several devices including a 16-character by 2-line LCD display, an 8-bit
DIP switch, 8 general-purpose user LEDs, and 24 GPIOs.
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Stellaris® Family Development Board User’s Manual
Power Supply
The Stellaris® Family Development Board requires 5 volts at 500 mA for operation, and three
options are provided for supply connection.
1. A USB connector can be used when connected to a high-power (500-mA) USB hub port.
2. A 5-V jack can be used with an external power supply.
3. A terminal block can be wired to a 5-V external bench supply.
A slide switch selects between USB power and the other two options (see Figure 1-2 on page 13).
Table 1-1 on page 16 describes how to select the power supply.
Motherboard Layout
The Stellaris™ family motherboard layout is shown in Figure 1-2. The gray squares show the
location of pin 1 for all connectors and headers. (On the board silk-screen, white arrows indicate
pin 1.) There are four ground test loops: TL1-TL4. TL5 is 5.0 V, and TL6 is 3.3 V.
NOTE: Two motherboard revisions are in production, Rev 2 and Rev 3. The revision is marked in
the lower left corner of the board, as indicated in the figure. The only functional difference
between these revisions is the addition in Rev 3 of headers JP34 and JP35 next to the
GPIOZ headers to allow source selection for signals IDX (PD7 or PB2) and FAULT (PD6
or PB3). JP34 and JP35 are highlighted in the figure with a red box.
Stellaris Family Motherboard Layout
P1
P2
J9
J21
J19
JP6
JP7
JP8
JP9
J18
J22
J17
S1
J1
3.3V
J4
J2
J3
J20
TL4
JP20
J15
JP31
J14
R25
3. 3V
JP34
PortA PortB PortC GPIOZ
5.0V
JP35
JP18
JP10
JP16
JP15
JP17
Figure 1-2.
PortD PortE Spare GPIOX GPIOY
JP11 JP12
JP14
JP21
WP
SCL
JP13
SDA
LED 7 JP30 ULED7
GND
JP1
J11
JP26
SW1
SW2
BZ1
JP19
SW3
JP3
JP2
JP5
JP4
POT1
R3
R5
REV 3
LED 0 JP22 ULED 0
NOTE: The gray squares indicate the location of pin 1 for all connectors and headers.
February 6, 2007
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Stellaris® Family Development Board
Development Board Configuration
NOTE: In the descriptions that follow, reference designators are used to indicate locations on the
board layout (as shown in Figure 1-2). In addition, reference designators in parenthesis
refer to parts in the schematics in Appendix B, “Schematics.
Daughterboard Installation
The daughterboard connects to the motherboard header connectors J1-J4. With no power applied
to the motherboard, place the daughterboard and align each connector of the motherboard with
the corresponding daughterboard connector. Press the daughterboard down until the
daughterboard is firmly seated, and visually inspect all four connectors to ensure proper
connection before proceeding.
UART
To connect the UART0 transceiver, connect shunt jumpers on headers JP6 and JP7. To connect
UART1, connect shunt jumpers on headers JP8 and JP9.
SPI Port (On-Board Peripherals)
To connect the Serial Peripheral Interface port, which is used to communicate with the PDC and
the on-board flash memory, connect shunt jumpers to pins 1-2 of headers JP15, JP16, JP17, and
JP18. To write-protect the SPI flash memory, place a shunt jumper on JP10.
NOTE: The Stellaris microcontroller’s SSI port can be programmed for one of three serial modes:
Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments
synchronous serial. (The mode is set with the FRF bit in the SSI Control0 (SSICR0)
register.) The Stellaris Family Development Board is designed for use with SPI mode
although MICROWIRE and TI synchronous serial modes can be used when implementing
user circuits in the prototype area. SPI mode must be set to use the board’s LCD, DIP
switch, LEDs, and GPIOX, GPIOY, and GPIOZ ports.
I2C Port
To connect the I2C port for access to the on-board EEPROM, place shunt jumpers on JP13 and
JP14. To write-protect the EEPROM memory, place a shunt jumper on JP12. Address line A2 for
the EEPROM memory can be set to 0 by placing a shunt jumper on JP11. Removing the jumper
sets A2 to 1.
NOTE: The I2C interface is available on select Stellaris microcontrollers.
Buzzer
To enable the buzzer BZ1, connect a shunt jumper to JP21. To connect the buzzer power driver to
the Stellaris microcontroller PB0 port, place a shunt jumper on JP26. To use a different port to
drive the buzzer, remove the shunt at JP26 and connect a fly-wire from the desired port to JP26-2.
LCD Panel, DIP Switch, LEDs, and GPIOs
To use the LCD panel, DIP switch, LEDs LED0-LED7 (D1-D8), and the GPIOs, the SPI port must
be connected as described above. The SPI port connects to the PDC to control these devices.
The potentiometer R25 is used to adjust the contrast of the LCD panel. The LCD panel, DIP
switch, LEDs, and GPIOs are controlled with the PDC registers (see Table 1-4 on page 18).
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Stellaris® Family Development Board User’s Manual
User Pushbutton
Pushbutton SW3 is available for general use. To connect this switch to PB4, place a shunt jumper
on JP19. To use a different port, remove shunt at JP19 and connect a fly-wire from the desired port
to JP19-2.
User LEDs
User LEDs ULED0-ULED7 (D9, D10, D12, D13-D17) are available for general use. Each user
LED has an associated header for connection to a Stellaris GPIO, PDC GPIO, or external circuitry.
To connect a user LED to its associated Stellaris GPIO, place a shunt jumper on the corresponding
header (ULED0-ULED3 => PB0-PB3, ULED4-ULED7 => PD0-PD3). To use a different port,
remove the shunt jumper from the header and connect a fly-wire from the desired port to pin 2 of
the header.
Photocell
Photocell R3 can be used to provide an analog signal to drive the ADC (analog-to-digital
converter) and the analog comparator using headers JP2 (ADC0,ADC2,ADC4,ADC6) =>
(PE5,PE3,PD7,PD5), and JP3 (C0+,C1+,C2+) => (PB6,PC5,PC6). To connect the photocell to an
ADC channel, place a shunt jumper on the corresponding JP2 header. To connect the photocell to
a comparator channel, place a shunt jumper on the corresponding JP3 header.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
Potentiometer
Potentiometer R5 can be used to provide an analog signal to drive the ADC (analog-to-digital
converter) and the analog comparator using headers JP4 (ADC1,ADC3,ADC5,ADC7) =>
(PE4,PE2,PD6,PD4), and JP5 (C0-,C1-,C2-) => (PB4,PB5,PC7). To connect the potentiometer to
an ADC channel, place a shunt jumper on the corresponding JP4 header. To connect the
potentiometer to a comparator channel, place a shunt jumper on the corresponding JP5 header.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
JTAG Debug Connector
For JTAG debug with an external ICE, connect the ICE to connector J14 with a standard 20-pin
JTAG debug cable. To link the motherboard reset to the JTAG emulator reset, place a shunt
jumper on JP20. Depending on the ICE, a shunt jumper at location JP31 may be required if a USB
driver conflict occurs.
USB Debug
For debug with USB, connect the USB cable to the USB device connector. Ensure that no shunt
jumper is present at location JP31. Note that a corresponding USB driver must be installed on the
host computer. The USB driver selects the mode of operation by controlling the USB_MOD signal
from the FTDI part (ADBUS7). If USB_MOD is 1, JTAG mode is selected. If USB_MOD is 0, SWD
mode is selected. JTAG/SWD signals are driven to the Stellaris microcontroller when the USB
driver sets USB_DEN (ADBUS6) to 0.
32.768-KHz Clock Oscillator
An on-board 32.768-KHz oscillator can be used to drive the Stellaris real-time clock. To enable this
oscillator, remove the shunt jumper on JP1. To disable the oscillator output, place a shunt jumper
on JP1.
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Stellaris® Family Development Board
Reset Switch
Reset switch SW2 generates a 140-ms (minimum) system reset signal. Powering up the board
also generates a 140-ms system reset signal. A shunt jumper can be placed on JP20 to link the
JTAG emulator reset with the system reset.
GPIO Headers
All Stellaris GPIO ports are available on 8-pin headers labeled PortA (J5), PortB (J6), PortC (J7),
PortD (J10), and PortE (J12). The 20-pin headers J9 and J22 include all the GPIOs and provide a
convenient connection for expansion to another board. The 8-pin headers labeled GPIOX (J26),
GPIOY (J27), and GPIOZ (J16) provide a connection to the GPIOs implemented in the PDC.
Power
Three options are available for board power, and only one should be connected to the board.
These are described in Table 1-1. The two power indicators light once there is power to the board.
Table 1-1. Possible Board Power Sources
Power Source
Configuration
USB high-power hub (500 mA)
Slide switch S1 towards the board edge. Connect a USB cable
from the USB hub to the USB-B receptacle J18. Slide switch S1
towards the board center to turn on power.
5-V (500-mA) supply with 2.5-mm plug
Slide switch S1 towards the center of the board. Connect a 5-V
supply with a 2.5-mm plug to jack J19. Slide switch S1 towards
the board edge to turn on power.
5-V (500-mA) bench supply
Slide switch S1 towards the center of the board. Connect a 5-V
supply with two wires to terminal block J21. Connect the 5-V
wire to J21-1 (5V) and the ground wire to J21-2 (GND). Slide
switch S1 towards the board edge to turn on power.
J21
5V GND
Peripheral Device Controller (PDC)
The PDC provides access to a common set of peripherals across all Stellaris microcontrollers,
since they all include an SSI port. The Stellaris SSI port is used in SPI mode for communications
with the PDC. The PDC operates at 1 MHz.
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Stellaris® Family Development Board User’s Manual
Stellaris Microcontroller to PDC Interface
The Stellaris microcontroller connects to the PDC with a SPI port using the signals shown in
Table 1-2.
Table 1-2. Stellaris Microcontroller to PDC Interface
Board Signal
Direction
Description
SPI_CLK
Input
SPI clock signal, 1 MHz.
SPI_SEL
Input
SPI select signal, set high to enable SPI transfers. Set to low for
reset of the PDC (minimum 200 nanoseconds). Note that with
SPI_SEL low the SPI flash at location U3 is selected.
SPI_MOSI
Input
Master output, slave input data transfer signal.
SPI_MISO
Output
Master input, slave output data transfer signal.
PDC I/O
The PDC connects to supported peripherals with the following signals:
Table 1-3. Peripheral to PDC Interface
Board Signal
Direction
Description
L_RS
Out
LCD register select
L_RW
Out
LCD read/write
L_CEN
Out
LCD chip enable
L_BLIGHT
Out
LCD backlight
InOut
LCD data bus
LD[7:0]
LED[7:0]
Out
DSW[7:0]
In
DIP switch inputs
GPIOX_[7:0]
InOut
GPIOX I/O ports
GPIOY_[7:0]
InOut
GPIOY I/O ports
GPIOZ_[7:0]
InOut
GPIOZ I/O ports
February 6, 2007
LED select outputs
17
Stellaris® Family Development Board
PDC Registers
PDC registers are 8 bits, and there are three types: Read-Only (RO), Read/Write (R/W), and
Read/Write delayed (RWD). A RWD transaction requires an additional dummy transfer due to
peripheral device latency.
Table 1-4. PDC Registers
Register
Address
Type
VERSION
0x0
R0
CSR
0x1
R/W
Description
The VERSION register contains the version of the PDC design
programmed in the CPLD.
The Command/Status (CSR) register is used to set special
configuration options and read device status. Unused bits are reserved
and should be written to 0. The following bits are defined:
Bit0 - LCBL: The LCD backlight bit controls the LCD panel backlight.
Setting this bit to 1 turns on the LCD backlight. Setting this bit to 0 turns
off the LCD backlight.
Bit7 - LCBSY: The LCD busy bit reflects the value of the LCD panel
busy flag. When this bit is 1, the LCD panel is busy processing a
command. When this bit is 0, a new command can be written to the LCD
panel.
DIPSW
0x4
R0
The DIP Switch (DIPSW) register contains the value of the debug DIP
switch at location SW1. Bit i corresponds to switch i+1. A switch in the
OFF position is read as 0. A switch in the ON position is read as 1.
LED
0x5
R/W
The LED Output (LED) register controls LED0-LED7. Bit i controls
LEDi. Writing a bit to 1 turns on the corresponding LED. Writing a bit to 0
turns off the corresponding LED.
LCDCSR
0x6
RWD
The LCD Command/Status (LCDCSR) register is used to write
configuration and control commands and to read status information from
the LCD panel. For more information, refer to the CFAH1602B LCD
panel data sheet (available from www.crystalfontz.com).
LCDRAM
0x7
RWD
The LCD RAM (LCDRAM) register is used to write and read the LCD
display data RAM (DDRAM) and the character generator RAM
(CGRAM). For more information, refer to the CFAH1602B LCD panel
data sheet (available from www.crystalfontz.com).
GPXDAT
0x8
R/W
The GPIOX Data (GPXDAT) register is used to access the generalpurpose I/O port GPIOX at location J26. Bit i corresponds with the
GPIOX_i port signal. Each bit can be configured for input or output in
the GPXDIR register.
Writing a bit to 1 sets the corresponding GPIOX port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOX port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOX port signal. If
the GPIOX port is 0, the bit will read as 0. If the GPIOX port signal is 1,
the bit will read as 1. Note that a read of the GPXDAT register always
reads the GPIOX port signals, not the internal register.
18
February 6, 2007
Stellaris® Family Development Board User’s Manual
Table 1-4. PDC Registers
Register
Address
Type
Description
GPXDIR
0x9
R/W
The GPIOX Direction (GPXDIR) register is used to select the data
transfer direction for the GPXDAT register. Bit i corresponds to GPXDAT
bit i. Writing a bit to 1 sets the corresponding GPXDAT bit as an output
port. Writing a bit to 0 sets the corresponding GPXDAT bit as an input
port.
GPYDAT
0xA
R/W
The GPIOY Data (GPYDAT) register is used to access the generalpurpose I/O port GPIOY at location J27. Bit i corresponds with the
GPIOY_i port signal. Each bit can be configured for input or output in
the GPYDIR register.
Writing a bit to 1 sets the corresponding GPIOY port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOY port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOY port signal. If
the GPIOY port is 0, the bit will read as 0. If the GPIOY port signal is 1,
the bit will read as 1. Note that a read of the GPYDAT register always
reads the GPIOY port signals, not the internal register.
GPYDIR
0xB
R/W
The GPIOY Direction (GPYDIR) register is used to select the data
transfer direction for the GPYDAT register. Bit i corresponds with
GPYDAT bit i. Writing a bit to 1 sets the corresponding GPYDAT bit as
an output port. Writing a bit to 0 sets the corresponding GPYDAT bit as
an input port.
GPZDAT
0xC
R/W
The GPIOZ Data (GPZDAT) register is used to access the generalpurpose I/O port GPIOZ at location J16. Bit i corresponds with the
GPIOZ_i port signal. Each bit can be configured for input or output in the
GPZDIR register.
Writing a bit to 1 sets the corresponding GPIOZ port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOZ port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOZ port signal. If
the GPIOZ port is 0, the bit will read as 0. If the GPIOZ port signal is 1,
the bit will read as 1. Note that a read of the GPZDAT register always
reads the GPIOZ port signals, not the internal register.
GPZDIR
0xD
R/W
The GPIOZ Direction (GPZDIR) register is used to select the data
transfer direction for the GPZDAT register. Bit i corresponds with
GPZDAT bit i. Writing a bit to 1 sets the corresponding GPZDAT bit as
an output port. Writing a bit to 0 sets the corresponding GPZDAT bit as
an input port.
SPI Protocol
The SPI slave interface is enabled when SPI_SEL goes High. All SPI commands and data are
received via the SPI_MOSI input signal, with data sampled on the rising edge of the SPI clock. All
SPI output data is transmitted on the SPI_MISO output signal, with data shifted out on the falling
edge of the SPI clock. Set SPI_SEL Low for 200 nanoseconds to reset the PDC.
February 6, 2007
19
Stellaris® Family Development Board
Every transaction is composed of at least two 8-bit SPI transfers. The first byte contains a 4-bit
address on the lower bits (bits 3:0) and a read/write (R/W) bit to indicate transfer direction on the
most significant bit (bit 7). The remaining bits (bits 6:4) are reserved and must be 0. The next byte
is driven by the Stellaris microcontroller for write transfers (R/W bit=0), and by the PDC for read
transfers (R/W bit=1). For read transfers to LCD registers, a dummy byte follows the first byte, with
a valid data byte afterwards. Timing diagrams are shown in Figure 1-3.
Figure 1-3.
PDC Timing Diagrams
PDC Read Transfer
SPI_SEL
SPI_CLK
SPI_MOSI
RW
0
0
0
A3
A2
A1
A0
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
D1
D0
LCD Read Transfer
SPI_SEL
SPI_CLK
SPI_MOSI
RW
0
0
0
A3
A2
A1
A0
SPI_MISO
D7
D6
D5
D4
D3
D2
D1
D0
Dummy Byte
PDC/LCD Write Transfer
SPI_SEL
SPI_CLK
SPI_MOSI
RW
0
0
0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
SPI_MISO
20
February 6, 2007
C H A P T E R 2
DB28 Daughterboard
The DB28 daughterboard contains a 28-pin SOIC Stellaris microcontroller and connects to the
motherboard with four 21-pin connectors.
NOTE: In the descriptions that follow, reference designators are used to indicate locations on the
board layout (as shown in Figure 2-2 on page 23). In addition, reference designators in
parenthesis refer to parts in the schematics in Appendix B, “Schematics.
Features
„
Designed for 28-pin SOIC Stellaris microcontroller
„
6-MHz crystal mounted on pin sockets for easy crystal changes
„
SMA connector for external clock
„
Power and ground test loops
„
Jumper-selectable 32.768-KHz clock
„
All daughterboard connector signals accessible via headers on the daughterboard
Block Diagram
Figure 2-1.
DB28 Daughterboard Block Diagram
Stellaris
JP1
Connectors
Daughterboard Interface
The DB28 daughterboard connects to the motherboard with four connectors: J1-J4 (see
Figure 1-2 on page 13). Table 2-1 on page 22 lists the connections.
February 6, 2007
21
DB28 Daughterboard
Table 2-1. DB28 Daughterboard Interface
Pin
J1
J2
1
GND
3.3V
J3
J4
3.3V
GND
2
3
4
5
XPB1
6
PB0
7
CLK32K
8
GND
9
PB2
10
PB3
11
5V
12
RSTn
13
PA2
14
PA5
15
PA4
16
PA3
PC3/TDO
17
18
PC0/TCK
PB6
19
PC1/TMS
PB5
PA0
20
PC2/TDI
PB4
PA1
21
PB7/TRST
GND
GND
Daughterboard Layout
The DB28 daughterboard layout is shown in Figure 2-2 on page 23. A single Stellaris
microcontroller is soldered at location U1. There are four ground test loops: TL1, TL4, TL5, and
TL7. TL2 is connected to the LDO pin and TL3 is connected to VDD. The gray squares show the
location of pin 1 for each connector. Note that TL6 and pin 1 of J2 and J4 are 3.3 V. A clock signal
can be applied to SMA connector J6 after removing crystal Y1.
22
February 6, 2007
Stellaris® Family Development Board User’s Manual
Figure 2-2.
DB28 Daughterboard Layout
J1
3.3V
3.3V
TL1
TL2
TL3
TL4
GND
LDO
VDD
GND
U2
U1
J4
J2
J6
Y1
TL5
TL6
TL7
GND
J3
3.3V
GND
JP1
NOTE: The gray squares indicate the location of pin 1.
Shunt Jumper
There is a single shunt jumper JP1 (see Figure 2-2) used for selecting the connection of port B1
(PB1) as shown in Table 2-2.
Table 2-2. Jumper Settings for DB28 Daughterboard
Shunt
Description
No shunt
PB1 is unconnected
Shunt 1-2
PB1 is connected to 32.768-KHz clock
Shunt 2-3
PB1 is connected to daughterboard connector J4-5
(XPB1)
February 6, 2007
23
DB28 Daughterboard
Development Board Signal Usage
Table 2-3 shows the signal connectivity and usage between the DB28 daughterboard and the
motherboard. For the jumpers column, the numbers in brackets show the jumper position.
Table 2-3. Development Board Signals Used by DB28 Daughterboard
Stellaris
Signal
DB28
Daughterboard
Connection
Motherboard
Jumpers
Motherboard
Signal
Description
PA0
J4-19
JP7-[1][2]
U0_RX
Serial port 0 receive
PA1
J4-20
JP6-[1][2]
U0_TX
Serial port 0 transmit
PA2
J4-13
JP15-[2][1]
SPI_CLK
Serial peripheral interface clock
PA3
J4-16
JP18-[2][1]
SPI_SEL
Serial peripheral interface select
PA4
J4-15
JP17-[2][1]
SPI_MISO
Serial peripheral interface master-in/slave-out
PA5
J4-14
JP16-[2][1]
SPI_MOSI
Serial peripheral interface master-out/slave-in
PB0
J4-6
JP26[1][2]
PWM
Buzzer signal
JP22[1][2]
ULED0
User LED
CLK32K
32.768-KHz clock
JP23-[1][2]
ULED1
User LED
J4-9
I2C_SCL
I2C clock signal to EEPROM
JP24[1][2]
ULED2
User LED
J4-10
I2C_SDA
I2C data signal to EEPROM
JP25[1][2]
ULED3
User LED
PB1
JP1-[2][1]Ö(J3-7)
JP1-[2][3]Ö(J4-5)
PB2
J4-9
PB3
J4-10
PB4
J3-20
JP5-[2][1]
C0-
Connects to 10k potentiometer
PB5
J3-19
JP5-[4][3]
C1-
Connects to 10k potentiometer
PB6
J3-18
JP3-[2][1]
C0+
Connects to photocell
PB7
J1-21
J14-3
TRST
JTAG signal, used by emulator
PC0
J1-18
J14-9
TCK
JTAG signal, used by emulator
PC1
J1-19
J14-7
TMS
JTAG signal, used by emulator
PC2
J1-20
J14-5
TDI
JTAG signal, used by emulator
PC3
J1-16
J14-13
TDO
JTAG signal, used by emulator
RST
J1-12
SYSRST_B
Connects to reset supervisor
OSC0
J7, C4
Connects to pin socket and capacitor for crystal
OSC1
J8, C5
Connects to pin socket and capacitor for crystal
VDD(U1)
TL6, J2-1, J4-1
24
3.3V
Connects to 3.3-V plane
February 6, 2007
Stellaris® Family Development Board User’s Manual
Table 2-3. Development Board Signals Used by DB28 Daughterboard
Stellaris
Signal
DB28
Daughterboard
Connection
GND
J1-1, J2-21
Motherboard
Jumpers
Motherboard
Signal
Description
GND
Connects to ground plane
J3-8, J4-21
LDO
February 6, 2007
Connects to 1.3 microfarad capacitor and to test
loop 2
25
DB28 Daughterboard
26
February 6, 2007
C H A P T E R 3
DB48 Daughterboard
The DB48 daughterboard contains a 48-pin LQFP Stellaris microcontroller and connects to the
motherboard with four 21-pin connectors.
NOTE: In the descriptions that follow, reference designators are used to indicate locations on the
board layout (as shown in Figure 3-2 on page 29 and Figure 3-3 on page 30). In addition,
reference designators in parenthesis refer to parts in the schematics in Appendix B,
“Schematics.
Features
„
Designed for 48-pin LQFP Stellaris microcontroller
„
6-MHz crystal mounted on pin sockets for easy crystal changes
„
SMA connector for external clock
„
Power and ground test loops
„
Jumper-selectable 32.768-KHz clock
„
All daughterboard connector signals accessible via headers on the daughterboard
Block Diagram
Figure 3-1.
DB48 Daughterboard Block Diagram
Stellaris
JP3
JP2
JP1
Connectors
Daughterboard Interface
The DB48 daughterboard connects to the motherboard with four connectors: J1-J4 (see
Figure 1-2 on page 13). Table 3-1 on page 28 lists the connections.
February 6, 2007
27
DB48 Daughterboard
Table 3-1. DB48 Daughterboard Interface
Pin
J1
J2
1
GND
3.3V
2
PD7V
3
PC4
PE5
4
PC6
PE4
J3
J4
3.3V
GND
5
XPB1
6
PB0
7
CLK32K
8
GND
9
XPE2
PB2
PD5
10
11
5V
PE3
12
RSTn
PD4
PB3
13
PA2
14
PA5
PE1
15
16
PC3/TDO
PE0
17
PA4
XPC7
PA3
PD6
PD2
PB6
PD3
18
PC0/TCK
19
PC1/TMS
PD1
PB5
PA0
20
PC2/TDI
PD0
PB4
PA1
21
PB7/TRST
GND
PC5
GND
Daughterboard Layout
There are two different layouts of the DB48 daughterboard. Layout 1 shown on Figure 3-2 on page
29 has the Stellaris microcontroller soldered at U1 on the center of the board. Layout 2 shown on
Figure 3-3 on page 30 has the Stellaris microcontroller soldered at location U1 on the left side of
the board.
Both layouts include four ground test loops: TL1-TL4 in Layout 1 and TL1, TL4, TL5, and TL7 in
Layout 2. TL6 in Layout 1 and TL2 in Layout 2 are connected to the LDO pin. The gray squares
show the location of pin 1 for each connector. Note that TL5 in Layout 1 and TL6 in Layout 2 as
well as pin 1 of J2 and J4 are 3.3 V. A clock signal can be applied to SMA connector J6 after
removing crystal Y1.
28
February 6, 2007
Stellaris® Family Development Board User’s Manual
Figure 3-2.
DB48 Daughterboard Layout 1 (R3)
J1
3.3V
3.3V
TL1
TL6
TL2
GND
LDO
GND
JP2
JP3
JP1
U1
J4
J2
TL5
J6
3.3V
Y1
TL4
TL3
GND
GND
J3
NOTE: The gray squares indicate the location of pin 1.
February 6, 2007
29
DB48 Daughterboard
Figure 3-3.
DB48 Daughterboard Layout 2 (R2)
J1
3.3V
3.3V
TL1
TL2
TL3
TL4
GND
LDO
VDD
GND
J4
U1
J2
U1
U2
J6
Y1
TL5
TL6
TL7
GND
J3
3.3V
GND
JP3
JP2
JP1
NOTE: The gray squares indicate the location of pin 1.
Shunt Jumpers
There are three shunt jumpers for connection of a 32.768-KHz clock as shown in Table 3-2.
Table 3-2. Jumper Settings for DB48 Daughterboard
Jumper
Shunt
Description
JP1
No shunt
PB1 is unconnected
Shunt 1-2
PB1 is connected to 32.768-KHz clock.
Shunt 2-3
PB1 is connected to daughterboard connector J4-5 (XPB1)
No shunt
PC7 is unconnected
Shunt 1-2
PC7 is connected to 32.768-KHz clock.
Shunt 2-3
PC7 is connected to daughterboard connector J4-5 (XPC7)
No shunt
PE2 is unconnected
Shunt 1-2
PE2 is connected to 32.768-KHz clock.
Shunt 2-3
PE2 is connected to daughterboard connector J4-5 (XPE2)
JP2
JP3
30
February 6, 2007
Stellaris® Family Development Board User’s Manual
Development Board Signal Usage
Table 3-3 shows the signal connectivity and usage between the DB48 daughterboard and the
motherboard. For the jumpers column, the numbers in brackets show the jumper position.
Table 3-3. Development Board Signals Used by DB48 Daughterboard
Stellaris
Signal
DB48
Daughterboard
Connection
Motherboard
Jumpers
Motherboard
Signal
Description
PA0
J4-19
JP7-[1][2]
U0_RX
Serial port 0 receive
PA1
J4-20
JP6-[1][2]
U0_TX
Serial port 0 transmit
PA2
J4-13
JP15-[2][1]
SPI_CLK
Serial peripheral interface clock
PA3
J4-16
JP18-[2][1]
SPI_SEL
Serial peripheral interface select
PA4
J4-15
JP17-[2][1]
SPI_MISO
Serial peripheral interface master-in/slave-out
PA5
J4-14
JP16-[2][1]
SPI_MOSI
Serial peripheral interface master-out/slave-in
PB0
J4-6
JP26-[1][2]
PWM
Buzzer signal
JP22-[1][2]
ULED0
User LED
CLK32K
32.768-KHz clock
JP23-[1][2]
ULED1
User LED
JP14-[1][2]
I2C_SCL
I2C clock signal to EEPROM
JP24-[1][2]
ULED2
User LED
JP34-[2][3]a
IDX
Motor index signal
JP13-[1][2]
I2C_SDA
I2C data signal to EEPROM
JP25-[1][2]
ULED3
User LED
JP35-[2][3]a
FAULT
Motor fault signal
PB1
PB2
PB3
JP1-[2][1]Ö(J3-7)
JP1-[2][3]Ö(J4-5)
J4-9
J4-10
PB4
J3-20
JP5-[2][1]
C0-
Connects to 10k potentiometer
PB5
J3-19
JP5-[4][3]
C1-
Connects to 10k potentiometer
PB6
J3-18
JP3-[2][1]
C0+
Connects to photocell
PB7
J1-21
J14-3
TRST
JTAG signal, used by emulator
PC0
J1-18
J14-9
TCK
JTAG signal, used by emulator
PC1
J1-19
J14-7
TMS
JTAG signal, used by emulator
PC2
J1-20
J14-5
TDI
JTAG signal, used by emulator
PC3
J1-16
J14-13
TDO
JTAG signal, used by emulator
PC4
J1-3
PC4
Not used
PC5
J3-21
JP3-[4][3]
C1+
Connects to photocell
PC6
J1-4
JP3-[6][5]
C2+
Connects to photocell
February 6, 2007
31
DB48 Daughterboard
Table 3-3. Development Board Signals Used by DB48 Daughterboard
Stellaris
Signal
DB48
Daughterboard
Connection
Motherboard
Jumpers
Motherboard
Signal
Description
JP2-[2][1]Ö(J3-7)
JP5-[6][5]
C2-
32.768-KHz clock
PC7
JP2-[2][3]Ö(J316)
JP5-[6][5]
C2-
Connects to 10k potentiometer
PD0
J2-20
JP27-[1][2]
ULED4
User LED
PD1
J2-19
JP28-[1][2]
ULED5
User LED
PD2
J4-17
JP9-[1][2]
U1_RX
Serial port 1 receive
JP29-[1][2]
ULED6
User LED
PD3
J4-18
JP8-[1][2]
U1_TX
Serial port 1 transmit
JP30-[1][2]
ULED7
User LED
PD4
J2-12
JP4-[8][7]
ADC7
Connects to 10k potentiometer
PD5
J2-10
JP2-[8][7]
ADC6
Connects to photocell
PD6
J3-17
JP4-[6][5]
ADC5
Connects to 10k potentiometer
JP35-[1][2]a
FAULT
Motor fault signal
JP2-[6][5]
ADC4
Connects to photocell
JP34-[1][2]a
IDX
Motor index signal
PD7
J1-2
PE0
J2-16
PE0
Not used
PE1
J2-15
PE1
Not used
JP3-[2][1]Ö(J3-7)
CLK32K
32.768-KHz clock
PE2
JP3-[2][3]Ö(J4-7)
JP4-[4][3]
ADC3
Connects to 10k potentiometer
PE3
J2-11
JP2-[4][3]
ADC2
Connects to photocell
PE4
J2-4
JP4-[2][1]
ADC1
Connects to 10k potentiometer
PE5
J2-3
JP2-[2][1]
ADC0
Connects to photocell
RST
J1-12
SYSRST_B
Connects to reset supervisor
OSC0
J7,C4
Connects to pin socket and capacitor for crystal
OSC1
J8,C5
Connects to pin socket and capacitor for crystal
VDD(U1)
TL5 (Layout 1),
TL6 (Layout 2),
J2-1, J4-1
3.3V
Connects to 3.3-V plane
GND
J1-1,J2-21
GND
Connects to ground plane
J3-8,J4-21
32
February 6, 2007
Stellaris® Family Development Board User’s Manual
Table 3-3. Development Board Signals Used by DB48 Daughterboard
Stellaris
Signal
DB48
Daughterboard
Connection
Motherboard
Jumpers
Motherboard
Signal
LDO
Description
Connects to 1.3 microfarad capacitor and to test
loop 2
a. Jumpers 34 and 35 are only available on Rev3 or later boards.
February 6, 2007
33
DB48 Daughterboard
34
February 6, 2007
A P P E N D I X A
Contact Information
Company Information
Founded in 2004, Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based
microcontrollers (MCUs). Austin, Texas-based Luminary Micro is the lead partner for the CortexM3 processor, delivering the world's first silicon implementation of the Cortex-M3 processor.
Luminary Micro's introduction of the Stellaris® family of products provides 32-bit performance for
the same price as current 8- and 16-bit microcontroller designs. With entry-level pricing at $1.00
for an ARM technology-based MCU, Luminary Micro's Stellaris product line allows for
standardization that eliminates future architectural upgrades or software tool changes.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com
+1-512-279-8800, ext. 3
February 6, 2007
35
36
February 6, 2007
A P P E N D I X B
Schematics
Schematics for the development board follow:
„
Stellaris Motherboard on page 39
„
DB28 Daughterboard on page 46
„
DB48 Daughterboard Layout 1 (board revision R3) on page 48
„
DB48 Daughterboard Layout 2 (board revision R2) on page 50
February 6, 2007
37
38
February 6, 2007
1
6
2
A
A
Table of Contents
Page
Description
1
Table of Contents / Revision Control
2
Block Diagram
3
Board Connectors, GPIO, JTAG
4
UART, SPI, I2C
5
PDC, LCD Display, LEDs, DIP Switch
6
Reset, Power
7
USB to JTAG / SWD
B
B
C
C
Luminary Micro, Inc.
D
108 Wild Basin Rd.
Two Wild Basin Suite 350
Austin, TX 78746
This document contains information proprietary to Luminary Micro, Inc. and shall not be used for
engineering design, procurement of manufacture in whole or in part without the express written
permission of Luminary Micro, Inc. Copyright © 2007 Luminary Micro, Inc. All rights reserved.
Designer:
Arnaldo Cruz
Drawn by:
Arnaldo Cruz
Approved:
*
Drawing Title:
Stellaris Development Board
Page Title:
Table of Contents
Size
Date:
1
2
Document Number:
C
Rev
0001
2/5/2007
6
R3
Sheet 1
of
7
D
1
2
3
4
5
6
A
A
Board Connectors
J1, J2, J3, J4
SYSTEM
Reset
JTAG
USB
JTAG / SWD
JUMPER
BLOCK
32kHz
Oscillator
UART
XVER
PORT0
SMA
B
B
Jumper block
ADC[0/2/4/6]
C0+/C1+/C2+
Photocell
Jumper block
ADC[1/3/5/7]
C0-/C1-/C2-
Potentiometer
Port Headers
PA[5:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[5:0]
I2C BUS
JUMPER
BLOCK
UART
XVER
JUMPER
BLOCK
I2C
EEPROM
8kbit
PORT1
JUMPER
BLOCK
3.3V Regulator
SPI BUS
Expansion Headers
FLASH
1Mbit
JUMPER
BLOCK
User LEDS
C
C
JUMPER
BLOCK
User Pushbutton
PDC (Peripheral Device Controller)
JUMPER
BLOCK
GPIO Port Headers
GPIOX[7:0]
GPIOY[7:0]
GPIOZ[7:0]
Buzzer
DIP Switch [7:0]
LCD panel 16 char x 2 rows
LEDS [7:0]
D
D
Drawing Title:
Stellaris Development Board
Page Title:
Block Diagram
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 2
2/5/2007
6
of
7
1
2
3
4
5
6
RSTn
SYSRST_B
DBGACK
DBGRQ
SRST_B
PC3
RTCK
PC0
PC1
PC2
PB7
M_INDEX
M_CH_A
M_CH_B
TDO
TCK
TMS
TDI
TRST
PD7
PC4
PC6
5v
A
A
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Board Connectors
J1
1X21HDR
J4
3.3v
PB1
PB0
PE2
PB2
PB3
PA0
PA1
PA2
PA3
PA4
PA5
U0_RX
U0_TX
SSI_CLK
SSI_FSS
SSI_RX
SSI_TX
1
2
3
4
5
6
7
8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PWM2
PWM3
I2CSCL
I2CSDA
C0C1C0+
TRST
1
2
3
4
5
6
7
8
PA2
PA5
PA4
PA3
PD2
PD3
PA0
PA1
J5
1X8HDR
PortA
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
3.3v
+
3.3v
C1
10uF
TANT
16V
+
3.3v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5v
C2
10uF
TANT
16V
+
C3
10uF
TANT
16V
1X21HDR
PE5
PE4
PD5
PE3
PD4
PE1
PE0
PD1
PD0
1X21HDR
3.3v
B
B
J9
J3
J6
1X8HDR
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1X21HDR
PortB
FB1
1
3.3vA
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
TCK
TMS
TDI
TDO
ChA
C0o/C1+
ChB
C2-
1
2
3
4
5
6
7
8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PWM0
PWM1
U1_RX
U1_TX
CCP0
CCP2
Fault
IDX
1
2
3
4
5
6
7
8
PE0
PE1
PE2
PE3
PE4
PE5
PWM4
PWM5
CCP4
CCP1
CCP3
CCP5
1
2
3
4
5
6
7
8
PWM0
PD0
PWM1
PD1
PWM2
PB0
PWM3
PB1
PWM4
PE0
PWM5
PE1
SYSRST_B
ADC7
PD4
39ohm @ 100 MHz
C66
0.1uF
PC5
PB4
PB5
PB6
PD6
PC7
J7
1X8HDR
PortC
3.3v
2
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
ChA
ChB
IDX
C1+
C2ADC6
ADC5
C0C1C0+
PC4
PC6
PD7X
PC5
PC7
PD5
PD6X
PB4
PB5
PB6
2X10 HDR
C65
0.1uF
JP34
PWM/QEI/ADC/CMP
1
2
3
PD7
1
2
3
PD6
PB2
1X3HDR
IDX
JP35
C
2
J10
1X8HDR
J11
PortD
3
1
SMA_32k
R1
22.1
CLK32K
3.3v
PA0
PA1
PA2
PA3
PA4
PA5
PB2
PB3
PB7
U1
JP1
PortE
1
1
2
1x2 HDR
2
32kEN
E/D
OUT
GND
Vcc
FAULT
J22
SMA
DNP
R77
10K
J12
1X8HDR
3
3.3v
4
TILE_48
C6
0.1uF
32.768KHz
PB3
1X3HDR
U0_RX
U0_TX
SSI_CLK
SSI_FSS
SSI_RX
SSI_TX
I2CSCL
I2CSDA
TRST
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
TCK
TMS
TDI
TDO
U1_RX
U1_TX
CCP4
CCP1
CCP3
CCP5
Note: JP34 and JP35 are present only
on the REV 3 board. Previous board
versions have signal PD7 directly
connected to J9-6 and signal PD6
directly connected to J9-14.
PC0
PC1
PC2
PC3
PD2
PD3
PE2
PE3
PE4
PE5
C
2X10 HDR
SERIAL/CCP
3.3v
R3
PHOTOCELL-P8102
JP2 ADC
1
3
5
7
PHOTOCELL
PCELL
2
4
6
8
0
2
4
6
PE5
PE3
PD7
PD5
2
4
6
C0+
C1+
C2+
PB6
PC5
PC6
2
4
6
8
1
3
5
7
PE4
PE2
PD6
PD4
2
4
6
C0C1C2-
PB4
PB5
PC7
2x4 HDR
JP3
1
3
5
R2
12.7K
3.3v
2x3 HDR
R66
10K
R6
10K
R7
10K
R8
10K
R9
10K
R10
10K
R11
10K
R12
10K
JTAG
3.3v
J14
D
SRST_B
PB7
PC2
PC1
PC0
RTCK
PC3
SRST_B
DBGRQ
DBGACK
1
3
5
7
9
11
13
15
17
19
TRST
TDI
TMS
TCK
TDO
R4
511
2
4
6
8
10
12
14
16
18
20
JP4 ADC
1
3
5
7
POT
R5
10K
POT1
2X10 HDR-SHRD
D
2x4 HDR
JP5
1
3
5
Drawing Title:
2x3 HDR
Stellaris Development Board
Page Title:
Board Connectors, GPIO, JTAG
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 3
2/5/2007
6
of
7
1
2
3
4
5
6
JP6 U0_TX
PA1
1
2
U0_TX
1x2 HDR
JP7
U0_RX
1
2
U0_RX
A
1
13
2
U1_TX
12
1x2 HDR
JP9
PD2
15
U1_RX
1
2
1x2 HDR
C7
R1IN
R2OUT
2
4
C10
R67
10K
T2OUT
R2IN
C1+
V+
C1-
V-
17
8
16
C_TXD0
9
C_RXD0
3
R13
10K
R14
10K
5
C8
5
9
4
8
3
7
2
6
1
P1
DB9_M
SER0
0.47uF
0.47uF
3.3v
R68
10K
T1OUT
T2IN
R1OUT
10
U1_RX
T1IN
7
C9
11
JP8 U1_TX
PD3
10
U2
1x2 HDR
0.47uF
C2+
0.47uF
6
INVALID
READY
C2-
14
20
11
1
TP1
TP2
FORCEON
FORCEOFF
18
10
PA0
A
3.3v
GND
VCC
19
0.47uF
C11
C_TXD1
C_RXD1
P2
DB9_M
SER1
11
MAX3224
5
9
4
8
3
7
2
6
1
3.3v
R15
10K
B
B
JP10
1
2
SPIM_WP
3.3v
R16
10K
1x2 HDR
1
2
3
4
SPI_SEL
3.3v
1Mbit
U3
8
7
6
5
CS
VCC
SO HOLD
WP
SCK
GND
SI
C12
0.1uF
AT25F1024AN
SPI_MISO
SPI_MOSI
SPI_CLK
3.3v
R17
10K
C
C
JP11
1
2
I2CM_A2
3.3v
R18
330
1x2 HDR
3.3v
JP12
U4
1
2
3
4
A0
VCC
A1
WP
A2
SCL
GND SDA
AT24C08A
8Kbits
8
7
6
5
1
2
C13
0.1uF
R19
10K
I2CM_WP
1x2 HDR
3.3v
R20
2.80K
JP13
PB3
1
I2C_SDA
2
R21
2.80K
I2C_SDA
1x2 HDR
JP14
PB2
1
I2C_SCL
2
I2C_SCL
1x2 HDR
D
D
Drawing Title:
Stellaris Development Board
Page Title:
UART/SPI/I2C
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 4
2/5/2007
6
of
7
1
2
3
4
5
6
3.3v
R69
10K
PA2
JP15
1
2
3
SPI_CLK
A
SPI_CLK
A
CPLD_TCK
1X3HDR
PA5
JP16
1
2
3
SPI_MOSI
5v
SPI_MOSI
5v
CPLD_TDI
J15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1X3HDR
PA4
JP17
SPI_MISO
1
2
3
CPLD_TDO
1
2
3
CPLD_TMS
SPI_MISO
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
1X3HDR
PA3
JP18
SPI_SEL
SPI_SEL
R22
R70
10K
1X3HDR
40.2
R71
10K
C31
0.1uF
3
R73
B
3
4
5
6
J23
8
7
6
5
4
3
2
1
SPARE
SPARE_7
SPARE_6
SPARE_5
SPARE_4
SPARE_3
SPARE_2
SPARE_1
SPARE_0
7
8
9
11
13
14
1X8HDR
SYSRST_B
15
16
TILE_48
J16
3.3v
8
7
6
5
4
3
2
1
GPIOZ
R75
330
J25
3.3v
100
99
98
97
96
95
GPIOX_0
GPIOX_1
GPIOX_2
GPIOX_3
GPIOX_4
GPIOX_5
GPIOX_6
GPIOX_7
94
91
89
87
1X8HDR
R65
10K
86
85
83
82
81
80
CLK_20M
U7
2
1x2 HDR
OE
OUT
GND VDD
3
J27
3.3v
4
C14
0.1uF
20.000MHZ 3.3V
GPIOY
1
2
3
4
5
6
7
8
GPIOY_0
GPIOY_1
GPIOY_2
GPIOY_3
GPIOY_4
GPIOY_5
GPIOY_6
GPIOY_7
79
78
77
1X8HDR
48
USB_MOD
R76
10K
28
26
33
31
J24
1
2
40
84
3.3v
1x2 HDR
R33
10K
R34
10K
62
75
93
R35
10K
12
25
42
J17
1
2
3
4
5
6
7
8
CPLD_JTAG
D
1X8HDR
PR5A
PR5B
PR5C
PR5D
PL6A
PL6B/TSALL
PR6A
PR6B
PL7A
PL7B
PL7C
PL7D
PR7A
PR7B
PR7C
PR7D
PL8A
PL8B
PR8A
PR8B
PL9A
PL9B
PR9A
PR9B
PT2A
PT2B
PT2C
PT2D
PT2E
PT2F
PB2A
PB2B
PB2C
PB2D
PT3A
PT3B
PT3C
PT3D
PB3A/CLK1_1
PB3B
PB3C/CLK1_0
PB3D
68
67
LD0
LD1
66
65
64
63
LD2
LD3
LD4
LD5
61
59
LD6
LD7
58
57
56
55
LED0
LED1
LED2
LED3
R28
54
53
LED4
LED5
R23
D1
330
2
1
GREEN LED
LED0
D2
330
2
1
GREEN LED
52
51
LED1
LED6
LED7
D3
R24
330
29
30
32
34
2
1
GREEN LED
USB_DEN
FT_DI
FT_DO
FT_CS
PC3
R29
TP8
R30
LED2
D4
330
CPLD_TDO
CPLD_TDI
2
1
GREEN LED
LED3
PT4A/CLK0_0
PT4B/CLK0_1
PT4C
PT4D
PT4E
PT4F
PB4A
PB4B
PB4C
PB4D
PT5A
PT5B
PT5C
PB5A
PB5C
PB5D
36
37
38
39
D5
TP10
330
2
43
44
45
46
DSW1
DSW2
DSW3
DSW4
47
49
50
DSW5
DSW6
DSW7
1
GREEN LED
DSW0
C
LED4
D6
R31
330
2
1
GREEN LED
LED5
D7
R32
330
2
1
GREEN LED
LED6
D8
R37
3.3v
CPLD_SLEEP
PL5A
PL5B
PL5C
PL5D/GSRN
B
L_RS
L_RW
L_CEn
L_BLIGHT
330
2
SLEEPN
1
GREEN LED
TCK
TMS
TDI
TDO
LED7
3.3v
GND
GND
VCC
VCC
VAUX
GND_0
GND_0
GND_0
VIO_0
VIO_0
VIO_0
GND_1
GND_1
GND_1
VIO_1
VIO_1
VIO_1
LCMXO256-T100C
35
90
88
60
74
92
10
24
41
DEBUG
3.3v
SW1
C15
0.1uF
C16
0.1uF
C17
0.1uF
C18
0.1uF
C19
0.1uF
C28
0.1uF
C20
0.1uF
C21
0.1uF
C29
0.1uF
1
2
3
4
5
6
7
8
DSW0
DSW1
DSW2
DSW3
DSW4
DSW5
DSW6
DSW7
ON
16
15
14
13
12
11
10
9
8
1
1
2
PR4A
PR4B
72
71
70
69
SW DIP-8 Rocker
10K
10K
10K
10K
10K
10K
10K
10K
J20
20MHz_OE
PL4A
PL4B
R27
6.8K
PC1
PC2
1
1
2
3
4
5
6
7
8
GPIOX
C
PR3A
PR3B
PR3C
PR3D
76
73
J26
R74
10K
1x2 HDR
23
27
1X8HDR
TEST
PL3A
PL3B
PL3C
PL3D
L_CONTRAST
CPLD_TMS
D
CPLD_TCK
C30
0.1uF
R36
4.75K
R38
R39
R40
R41
R42
R43
R44
R45
DNP
21
22
PR2A
PR2B
1X16HDR
CONTRAST
DSW[7..0]
1
2
TEST
17
18
19
20
GPIOZ_7
GPIOZ_6
GPIOZ_5
GPIOZ_4
GPIOZ_3
GPIOZ_2
GPIOZ_1
GPIOZ_0
PL2A
PL2B
R25
10K
LCD Display 16x2
330
R26
3.18K
Q2
MMBT3904
2
PDC
U10
1
2
2.80K 1
LD[7..0]
R72
U5
Drawing Title:
Stellaris Development Board
Page Title:
PDC, LCD Display, LEDs, DIP Switch
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 5
2/5/2007
6
of
7
1
2
3
4
5
6
3.3v
SW2
3.3v
4
1
A
SYSRST
SW3
USER_PB
1
2
4
1
R47
10K
4
VCC
PB4
GND
GND
GND
GND
TL1
TL2
TL3
TL4
100 Mil Mask
FID3
40 Mil Pad
FID4
40 Mil Pad
100 Mil Mask
A
100 Mil Mask
1x2 HDR
GND
2
RESET
SYSRST_B
C23
0.1uF
MAX6386
USER
FID5
40 Mil Pad
3
1
2
3
2
MR
FID2
40 Mil Pad
100 Mil Mask
JP19
U8
3
C22
0.1uF
FID1
40 Mil Pad
R46
10K
FID6
40 Mil Pad
100 Mil Mask
100 Mil Mask
FID7
40 Mil Pad
FID8
40 Mil Pad
100 Mil Mask
100 Mil Mask
JP20
1
SRST_B
Fiducials
2
1x2 HDR
LINK_SRST
JP21
PWM_Buzzer
1
2
5v 1x2 HDR
R49
511
R50
33.2
JP22
2
BZ1
D11
GREEN LED
B
1
1
PB0
JP23
-
PWM_LED
1
PB1
BUZZER CEM-1206S
1
3
1
R56
2
2.80K
Q1
MMBT3904
1
R55
82.5K
1x2 HDR
PWM
1
PB2
2
ULED1
2
ULED2
2
JP25
1
PB3
ULED3
2
D10
R51
330
2
JP27
1
ULED4
2
JP28
1
ULED5
2
D12
330
2
JP29
1
ULED6
2
D13
R53
330
2
JP30
1
ULED7
2
1
GREEN LED
ULED3
D14
R54
330
2
1
GREEN LED
ULED4
D15
R57
330
2
1
GREEN LED
ULED5
D16
R58
330
2
1
GREEN LED
1x2 HDR
PD3
1
GREEN LED
ULED2
1x2 HDR
PD2
B
ULED1
R52
1x2 HDR
PD1
1
GREEN LED
1x2 HDR
PD0
1
GREEN LED
ULED0
1x2 HDR
2
PB0
330
1x2 HDR
JP24
JP26
D9
R48
1x2 HDR
+
2
ULED0
2
ULED6
D17
R59
330
2
1
GREEN LED
1x2 HDR
ULED7
C
C
Notes:
1. Power provided by external 5v DC supply or USB port, as selected by switch
2. Use of USB power requires a high power port (500mA).
USB_5v
5.0V
3.3V
TL5
TL6
3
2
R60
511
1101M2S3CQE2
R61
10K
1
+
1N5819
D18
GREEN LED
RAPC722
C24
22uF
C25
0.1uF
1
EN
TANT
16V
TAB
1
2
2
5.0V
D20
VOUT
3
3
J19
VIN
GND
2
2
3.3v
MIC5209
U9
ADJ
4
R62
5
C26
470 pF
R63
330
82.5K
R64
137K
+
C27
22uF
2
5v
S1
TAB
1
D19
GREEN LED
TANT
16V
J21
5.0V
1
3.3V
1
5.0V
D21
1
2
GND
2
1
1N5819
Term_Block_V_2pos
D
D
Drawing Title:
Stellaris Development Board
Page Title:
Power, Reset
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 6
2/5/2007
6
of
7
1
2
3
4
5
6
A
A
J18
USB_B
D-
V
D+
G
SGND
SGND
USB
5
6
1
4
2
3
3.3v
USB_5v
FB2
1
2
R94
10K
39ohm @ 100 MHz
C34
0.1uF
B
R79
27
8
R80
27
7
3V3OUT
USBDM
USBDP
R84
10K
U12
VCC
DC
NC
GND
CS
SK
DI
DO
1
2
3
4
R83
B
48
1
2
47
2.21K
43
44
AT93C46A-10SI-2.7
1K 64X16
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
SI/WUA
R81
1.50K
8
7
6
5
R86
10K
U11
6
5v
R95
10K
4
5
EECS
EESK
EEDATA
TEST
XTIN
XTOUT
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
SI/WUB
RESET#
RSTOUT#
PWREN#
GND
GND
GND
GND
VCC
VCC
VCCIOA
VCCIOB
24
23
22
21
20
19
17
16
TCK/SK
TDI/DO
TDO/DI
TMS/CS
TP11
TP12
15
13
12
11
10
R87
0
R92
R88
0
0
PC0
FT_DO
FT_DI
FT_CS
USB_DEN
USB_MOD
TP13
TP15
TP14
TP16
40
39
38
37
36
35
33
32
SWO
PC3
TP18
TP20
TP19
TP21
TP22
TP23
30
29
28
27
26
TP24
TP25
TP26
TP27
41
TP29
3.3v
5v
USB_5v
R91
10K
C
JP31
USB_OFF
1
2
R85
10K
Y1
1
2
C33 6.000MHz
18pF
9
18
25
34
C32
18pF
45
R93
20K
1x2 HDR
AGND
FT2232C
AVCC
3
42
14
31
46
C
FB3
R82
C39
0.1uF
475
1
2
C37
0.1uF
C38
0.1uF
C35
0.1uF
C36
0.1uF
39ohm @ 100 MHz
D
D
Drawing Title:
Stellaris Development Board
Page Title:
USB to JTAG / SWD
Size
Document Number:
C
Date:
1
2
3
4
5
Rev
R3
0001
Sheet 7
2/5/2007
6
of
7
5
D
4
3
2
1
D
Table of Contents
Page
Description
1
Table of Contents / Revision Control
2
LM3S1XX, Socket, Connectors
C
C
B
B
A
Luminary Micro, Inc.
2499 S. Capital of Texas Hwy
Austin, TX 78746
This document contains information proprietary to Luminary Micro Inc. and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written
permission of Luminary Micro, Inc. Copyright © 2005 Luminary Micro, Inc. All rights reserved.
5
4
3
2
Designer:
Arnaldo Cruz
Drawing Title:
Drawn by:
Arnaldo Cruz
Page Title:
Approved:
<Approver>
Size
C
Document Number
Date:
Saturday, March 18, 2006
Stellaris DB28 Daughterboard
Table of Contents
Rev
R2
0001
Sheet
1
1
of
2
A
5
4
3
2
1
5v
RSTn
PC3
TDO
PC0
PC1
PC2
PB7
TCK
TMS
TDI
TRST
D
J1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
21x1 SKT
3.3v
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
XPB1
PB0
PB2
PB3
PA2
PA5
PA4
PA3
PA0
PA1
C
J4
3.3v
3.3v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
3.3v
+ C1
10uF
TANT
16V
+ C2
10uF
TANT
16V
21x1 SKT
C
21x1 SKT
J3
GND
TL1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21x1 SKT
GND
TL4
GND
TL5
GND
TL7
PB4
PB5
PB6
CLK32K
1
2
3
JP1
1X3HDR
PB1_MUX
3.3v
R1
0.1 Ohm
0.5%
U2
PB7
PB6
PB5
PB4
RSTn
LDO
B
FID1
40 Mil Pad
100 Mil Mask
FID2
40 Mil Pad
100 Mil Mask
FID3
40 Mil Pad
100 Mil Mask
FID4
40 Mil Pad
100 Mil Mask
VDD
TL3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OSC0
OSC1
PA0
PA1
PA2
PA3
C4
0.1uF
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
SOP28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC0
PC1
PC2
PC3
PB3
PB2
B
Fiducials
PB1
PB0
PA5
PA4
C5
0.1uF
C6
0.1uF
SOCKET_SOP28
DNP
2
U1
J6
1
3
A
R2
22.1
1%
PA0
PA1
PA2
PA3
PA4
PA5
11
12
13
14
15
16
PA0/U0Rx
PA1/U0Tx
PA2/SSIClk
PA3/SSIFss
PA4/SSIRx
PA5/SSITx
PC0
PC1
PC2
PC3
28
27
26
25
PC0/TCK/SWCLK
PC1/TMS/SWDIO
PC2/TDI
PC3/TDO/SWO
9
10
OSC0
OSC1
OSC0
OSC1
SMA
J7
1
C7
18pF
50V
10%
1
9548
RSTn
J8
Y1
2
6.000MHz
1
9548
C8
18pF
50V
10%
PB0/CCP0
PB1/32KHz
PB2/I2CSCL
PB3/I2CSDA
PB4/C0PB5/C1-/C0o
PB6/C0+/CCP1
PB7/TRST
19
20
23
24
4
3
2
1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
3.3v
TL6
LDO
TL2
A
5
RST
LDO
6
8
18
21
GND
GND
GND
VDD
VDD
VDD
7
17
22
LDO
3.3v
C12
1uF
C9
0.1uF
LM3S1XX_SOP28
C10
0.1uF
C11
0.1uF
C13
0.33uF
16V
10%
Drawing Title:
Stellaris DB28 Daughterboard
Page Title:
LM3S1XX, Socket, Connectors
5
4
3
2
Size
C
Document Number
Date:
Saturday, March 18, 2006
Rev
R2
0001
Sheet
1
2
of
2
5
D
4
3
2
1
D
Table of Contents
Page
Description
1
Table of Contents / Revision Control
2
LM3SXXX, Connectors
C
C
B
B
A
Luminary Micro, Inc.
2499 S. Capital of Texas Hwy
Austin, TX 78746
This document contains information proprietary to Luminary Micro Inc. and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written
permission of Luminary Micro, Inc. Copyright © 2005 Luminary Micro, Inc. All rights reserved.
5
4
3
2
Designer:
Arnaldo Cruz
Drawing Title:
Drawn by:
Arnaldo Cruz
Page Title:
Approved:
<Approver>
Size
C
Document Number
Date:
Thursday, May 18, 2006
Stellaris DB48 Daughterboard
Table of Contents
Rev
R3
0001
Sheet
1
1
of
2
A
5
4
3
2
1
RSTn
RSTn
PC3
TDO
PC0
PC1
PC2
PB7
TCK
TMS
TDI
TRST
PD7
PC4
PC6
5v
D
J1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
21x1 SKT
3.3v
J4
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
XPB1
PB0
XPE2
PB2
PB3
PA2
PA5
PA4
PA3
PD2
PD3
PA0
PA1
3.3v
3.3v
+ C1
10uF
TANT
16V
+ C2
10uF
TANT
16V
3.3v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5v
+ C3
10uF
TANT
16V
21x1 SKT
PE5
PE4
PD5
PE3
PD4
PE1
PE0
PD1
PD0
21x1 SKT
J3
C
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21x1 SKT
C
CLK32K
PC5
PB4
PB5
PB6
PD6
XPC7
JP1
1X3HDR
PB1
1
2
3
PB1
XPB1
JP2
1X3HDR
PC7
1
2
3
PC7
XPC7
JP3
1X3HDR
PE2
1
2
3
PE2
XPE2
GND
TL1
U1
3
2
B
J6
1
PA0
PA1
PA2
PA3
PA4
PA5
17
18
19
20
21
22
PA0/U0Rx
PA1/U0Tx
PA2/SSIClk
PA3/SSIFss
PA4/SSIRx
PA5/SSITx
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
40
39
38
37
14
13
12
11
PC0/TCK/SWCLK
PC1/TMS/SWDIO
PC2/TDI
PC3/TDO/SWO
PC4/CCP5/PhA
PC5/C1+/C1o/C0o/CCP1
PC6/C2+/C2o/CCP3/PhB
PC7/C2-/CCP4
PE0
PE1
PE2
PE3
PE4
PE5
35
36
4
3
2
1
PE0/PWM4
PE1/PWM5
PE2/ADC3/CCP4
PE3/ADC2/CCP1
PE4/ADC1/CCP3
PE5/ADC0/CCP5
9
10
OSC0
OSC1
PB0/PWM2/CCP0
PB1/PWM3/CCP2
PB2/I2CSCL
PB3/I2CSDA
PB4/C0PB5/C1-/CCP5
PB6/C0+
PB7/TRST
29
30
33
34
44
43
42
41
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PD0/PWM0
PD1/PWM1
PD2/U1Rx
PD3/U1Tx
PD4/ADC7/CCP0
PD5/ADC6/CCP2
PD6/ADC5/Fault
PD7/ADC4/C0o/IDX
25
26
27
28
45
46
47
48
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
22.1
1%
OSC0
OSC1
SMA
J7
1
C4
18pF
50V
10%
9548
RSTn
J8
Y1
1
2
6.000MHz
1
9548
C5
18pF
50V
10%
GND
TL3
GND
TL4
FID1
40 Mil Pad
100 Mil Mask
FID2
40 Mil Pad
100 Mil Mask
FID3
40 Mil Pad
100 Mil Mask
FID4
40 Mil Pad
100 Mil Mask
B
Fiducials
3.3v
TL5
R1
GND
TL2
LDO
TL6
3.3v
5
RST
LDO
6
8
16
24
31
GND
GND
GND
GND
VDD
VDD
VDD
VDD
7
15
23
32
LDO
C8
0.1 uF
C9
0.1 uF
C10
0.1 uF
C11
0.1 uF
+ C16
10uF
TANT
16V
C12
0.01 uF
C13
0.01 uF
C14
0.01 uF
C15
0.01 uF
+ C17
10uF
TANT
16V
C18
0.1 uF
C19
0.1 uF
C20
0.1 uF
C21
0.1 uF
DNP
DNP
DNP
DNP
+ C22
10uF
TANT
16V
DNP
C26
0.01 uF
DNP
C27
0.01 uF
DNP
C28
0.01 uF
DNP
C29
0.01 uF
DNP
C6
1uF
C7
0.33uF
16V
10%
LM3SXXX_QFP48
A
A
+ C23
10uF
TANT
16V
DNP
C24
1uF
DNP
C25
0.33uF
16V
10%
DNP
Drawing Title:
Stellaris DB48 Daughterboard
Page Title:
LM3SXXX, Connectors
Located on bottom layer
5
4
3
2
Size
C
Document Number
Date:
Thursday, May 18, 2006
Rev
R3
0001
Sheet
1
2
of
2
5
D
4
3
2
1
D
Table of Contents
Page
Description
1
Table of Contents / Revision Control
2
LM3SXXX, Socket, Connectors
C
C
B
B
A
Luminary Micro, Inc.
2499 S. Capital of Texas Hwy
Austin, TX 78746
This document contains information proprietary to Luminary Micro Inc. and shall not be used for
engineering design, procurement or manufacture in whole or in part without the express written
permission of Luminary Micro, Inc. Copyright © 2005 Luminary Micro, Inc. All rights reserved.
5
4
3
2
Designer:
Arnaldo Cruz
Drawing Title:
Drawn by:
Arnaldo Cruz
Page Title:
Approved:
<Approver>
Size
C
Document Number
Date:
Saturday, March 18, 2006
Stellaris DB48 Daughterboard
Table of Contents
Rev
R2
0001
Sheet
1
1
of
2
A
5
4
3
2
1
RSTn
RSTn
PC3
TDO
PC0
PC1
PC2
PB7
TCK
TMS
TDI
TRST
PD7
PC4
PC6
5v
D
J1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
21x1 SKT
3.3v
J4
J2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
XPB1
PB0
XPE2
PB2
PB3
PA2
PA5
PA4
PA3
PD2
PD3
PA0
PA1
3.3v
3.3v
+ C1
10uF
TANT
16V
+ C2
10uF
TANT
16V
5v
+ C3
10uF
TANT
16V
21x1 SKT
3.3v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PE5
PE4
PD5
PE3
PD4
PE1
PE0
PD1
PD0
21x1 SKT
J3
C
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21x1 SKT
C
CLK32K
PC5
PB4
PB5
PB6
PD6
XPC7
JP1
1X3HDR
PB1
1
2
3
PB1
XPB1
JP2
1X3HDR
PC7
1
2
3
PC7
XPC7
JP3
1X3HDR
PE2
1
2
3
PE2
XPE2
GND
TL1
GND
TL4
GND
TL5
GND
TL7
FID1
40 Mil Pad
100 Mil Mask
FID2
40 Mil Pad
100 Mil Mask
FID3
40 Mil Pad
100 Mil Mask
FID4
40 Mil Pad
100 Mil Mask
3.3v
PD7
PD6
PD5
PD4
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
VDD
TL3
P48
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
48
47
46
45
44
43
42
41
40
39
38
37
R1
0.1 Ohm
0.5%
U2
B
PE5
PE4
PE3
PE2
RSTn
LDO
1
2
3
4
5
6
7
8
9
10
11
12
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
QFP48
Fiducials
U1
PB1
PB0
PD3
PD2
PD1
PD0
PA0
PA1
PA2
PA3
PA4
PA5
17
18
19
20
21
22
PA0/U0Rx
PA1/U0Tx
PA2/SSIClk
PA3/SSIFss
PA4/SSIRx
PA5/SSITx
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
40
39
38
37
14
13
12
11
PC0/TCK/SWCLK
PC1/TMS/SWDIO
PC2/TDI
PC3/TDO/SWO
PC4/CCP5/PhA
PC5/C1+/C1o/C0o/CCP1
PC6/C2+/C2o/CCP3/PhB
PC7/C2-/CCP4
PE0
PE1
PE2
PE3
PE4
PE5
35
36
4
3
2
1
PE0/PWM4
PE1/PWM5
PE2/ADC3/CCP4
PE3/ADC2/CCP1
PE4/ADC1/CCP3
PE5/ADC0/CCP5
9
10
OSC0
OSC1
SOCKET_QFP48
DNP
C14
0.1uF
2
J6
1
3
A
C15
0.1uF
PA0
PA1
PA2
PA3
PA4
PA5
C13
0.1uF
PC5
PC4
C12
0.1uF
13
14
15
16
17
18
19
20
21
22
23
24
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
OSC0
OSC1
PC7
PC6
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
B
PE1
PE0
PB3
PB2
36
35
34
33
32
31
30
29
28
27
26
25
PB0/PWM2/CCP0
PB1/PWM3/CCP2
PB2/I2CSCL
PB3/I2CSDA
PB4/C0PB5/C1-/CCP5
PB6/C0+
PB7/TRST
29
30
33
34
44
43
42
41
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PD0/PWM0
PD1/PWM1
PD2/U1Rx
PD3/U1Tx
PD4/ADC7/CCP0
PD5/ADC6/CCP2
PD6/ADC5/Fault
PD7/ADC4/C0o/IDX
25
26
27
28
45
46
47
48
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
3.3v
TL6
R2
22.1
1%
OSC0
OSC1
SMA
J7
1
C4
18pF
50V
10%
1
9548
RSTn
J8
Y1
2
6.000MHz
1
9548
C5
18pF
50V
10%
LDO
TL2
A
5
RST
LDO
6
8
16
24
31
GND
GND
GND
GND
VDD
VDD
VDD
VDD
7
15
23
32
LDO
3.3v
C6
1uF
C8
0.1uF
LM3SXXX_QFP48
C9
0.1uF
C10
0.1uF
C11
0.1uF
C7
0.33uF
16V
10%
Drawing Title:
Stellaris DB48 Daughterboard
Page Title:
LM3SXXX, Socket, Connectors
5
4
3
2
Size
C
Document Number
Date:
Saturday, March 18, 2006
Rev
R2
0001
Sheet
1
2
of
2
IMPORTANT NOTICE
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such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
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