III - Renesas Electronics

III - Renesas Electronics

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

Application Note

78K/0 Series

8-bit Single-chip Microcontroller

Basic (III)

µ

PD78054 subseries

µ

PD78064 subseries

µ

PD78078 subseries

µ

PD78083 subseries

µ

PD780018 subseries

µ

PD780058 subseries

µ

PD780308 subseries

µ

PD78058F subseries

µ

PD78064B subseries

µ

PD78075B subseries

µ

PD78098B subseries

µ

PD78054Y subseries

µ

PD78064Y subseries

µ

PD78078Y subseries

µ

PD78098 subseries

µ

PD780018Y subseries

µ

PD780058Y subseries

µ

PD780308Y subseries

µ

PD78058FY subseries

µ

PD78070A, 78070AY

µ

PD78075BY subseries

Document No. U10182EJ2V0AN00 (2nd edition)

Date Published October 1997 N

©

Printed in Japan

1995

[MEMO]

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

FIP, EEPROM, and IEBus are trademarks of NEC Corporation.

Purchase of NEC I

2

C components conveys a license under the Philips I

2

C Patent Rights to use these components in an I

2

C system, provided that the system conforms to the I

2

C Standard Specification as defined by Philips.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M7 96.5

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 800-366-9782

Fax: 800-729-9288

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 01-504-2787

Fax: 01-504-2860

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

J96. 8

Page

Throughout p.100

p.113

p.196

p.197

p.204, p206 p.218, p.224

p.239

p.240

p.250

p.286

p.347

p.216, p.217

p.229-p.232

p.352, p.353

p.387

Major Revisions in This Edition

Description

Addition of following products as target products:

µ

PD780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY,

78098B subseries,

µ

PD78070A, 78070AY

µ

PD78052(A), 78053(A), 78054(A)

µ

PD78062(A), 78063(A), 78064(A)

µ

PD78081(A), 78082(A), 78P083(A), 78081(A2)

µ

PD78058F(A), 78058FY(A)

µ

PD78064B(A)

Deletion of following products as target products:

µ

PD78P054Y, 78P064Y, 78074, 78075, 78075, 78074Y, 78075Y

Addition of Note 2 and Caution 2 to Figure 4-5 Format of Watchdog Timer Mode Register

Addition of Caution to Figure 5-8 Format of External Interrupt Mode Register 0

Addition of Table 8-2 Items Supported by Each Subseries

Addition of Table 8-3 Registers of Serial Interface

Addition of note on using wake-up function and note on changing operation mode to Figures 8-7 and 8-8

Format of Serial Operating Mode Register 0

Addition of Caution to Figures 8-16 and 8-17 Format of Automatic Data Transfer/Reception Interval

Specification Register

Addition of Figures 8-23 and 8-24 Format of Serial Interface Pin Select Register

µ

PD6252 as maintenance product in 8.1 Interface with EEPROM

TM

(

µ

PD6252)

Addition of (5) Limitations when using I

2

C bus mode to 8.1.2 Communication in I

2

C bus mode

Addition of (f) Limitations when using UART mode to 8.5 Interface in Asynchronous Serial Interface

(UART) Mode

Addition of Figure 11-3 Format of Port Mode Register 12

Description of following register formats and tables for each subseries:

Figures 8-14 and 8-15 Format of Automatic Data Transmission/Reception Control Register

Tables 8-4, 8-5, and 8-6 Setting of Operation Modes of Serial Interface Channel 2

Figures 12-1 and 12-2 Format of LCD Display Mode Register

Addition of APPENDIX B REVISION HISTORY

The mark shows major revised points.

Readers

INTRODUCTION

This Application Note is intended for use by engineers who understand the functions of the 78K/0 series and wish to design application programs with the following subseries products:

• Subseries

µ

PD78054 subseries :

µ

PD78052, 78053, 78054, 78P054, 78055, 78056,

78058, 78P058, 78052(A), 78053(A), 78054(A)

µ

PD78054Y subseries :

µ

PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y,

78058Y, 78P058Y

µ

PD78064 subseries :

µ

PD78062, 78063, 78064, 78P064, 78062(A), 78063(A),

78064(A)

µ

PD78064Y subseries :

µ

PD78062Y, 78063Y, 78064Y

µ

PD78078 subseries :

µ

PD78076, 78078, 78P078

µ

PD78078Y subseries :

µ

PD78076Y, 78078Y, 78P078Y

µ

PD78083 subseries :

µ

PD78081, 78082, 78P083, 78081(A), 78082(A),

78P83(A), 78081(A2)

µ

PD78098 subseries :

µ

PD78094, 78095, 78096, 78098A

Note 1

, 78P098A

Note 1

µ

PD780018 subseries :

µ

PD780016

Note 2

, 780018

Note 2

, 78P0018

Note 2

µ

PD780018Y subseries :

µ

PD780016Y

Note 2

, 780018Y

Note 2

, 78P0018Y

Note 2

µ

PD780058 subseries :

µ

PD780053

Note 1

, 780054

Note 1

, 780055

Note 1

,

780056

Note 1

, 780058

Note 1

, 78F0058

Note 1

µ

PD780058Y subseries :

µ

PD780053Y

Note 2

, 780054Y

Note 2

,

780055Y

Note 2

, 780056Y

Note 2

, 780058Y

Note 2

,

78F0058Y

Note 2

µ

PD780308 subseries :

µ

PD780306

Note 1

, 780308

Note 1

, 78P0308

Note 1

µ

PD780308Y subseries :

µ

PD780306Y

Note 1

, 780308Y

Note 1

, 78P0308Y

Note 1

µ

PD78058F subseries :

µ

PD78056F, 78058F, 78P058F, 78058F(A)

µ

PD78058FY subseries :

µ

PD78056FY, 78058FY, 78P058FY, 78P058FY(A)

µ

PD78064B subseries :

µ

PD78064B, 78P064B, 78064B(A)

µ

PD78070A, 78070AY

µ

PD78075B subseries :

µ

PD78074B, 78075B

µ

PD78075BY subseries:

µ

PD78074BY

Note 1

, 78075BY

Note 1

µ

PD78098B subseries :

µ

PD78095B

Note 2

, 78096B

Note 2

, 78098B

Note 2

,

78P098B

Note 2

Notes 1. Under development

2. Planned

Remarks 1. The

µ

PD78052(A), 78053(A), and 78054(A) have higher reliability than the

µ

PD78052, 78053, and 78054.

2. The

µ

PD78062(A), 78063(A), and 78064(A) have higher reliability than the

µ

PD78062, 78063, and 78064.

3. The

µ

PD78081(A), 78082(A), 78P083(A), and 78081(A2) have higher reliability than the

µ

PD78081, 78082, and 78P083.

4. The

µ

PD78058F(A) and 78058FY(A) have higher reliability than the

µ

PD78058F and 78058FY.

5. The

µ

PD78064B(A) has higher reliability than the

µ

PD78064B.

Purpose

Organization

This Application Note is to deepen your understanding of the basic functions of the

78K/0 series by using program examples.

Note that the programs and hardware configuration shown in this document are only examples and not subject to mass production.

This Application Note consists of the following contents:

• General

• Software

• Hardware

In addition to this Application Note, the following Application Notes are also available:

Document Name

78K/0 Series

Application Note

Basic (I)

78K/0 Series

Application Note

Basic (II)

78K/0 Series

Application Note

Basic (III)

78K/0 Series

Application Note

Floating-Point

Operation Program

µ

PD78014 Series

Application Note

Electronic Pocketbook

Document Number

Targeted Subseries

Japanese English

IEA-715 IEA-1288

µ

PD78002, 78002Y

µ

PD78014, 78014Y

µ

PD78018F, 78018FY

U10121J U10121E

µ

PD78044

µ

PD78044H

µ

PD780208

µ

PD780228

U10182J This

µ

PD78054, 78054Y document

µ

PD78064, 78064Y

µ

PD78078, 78078Y

µ

PD78083

µ

PD78098

µ

PD780018, 780018Y

µ

PD780058, 780058Y

µ

PD780308, 780308Y

µ

PD78058F, 78058FY

µ

PD78064B

µ

PD78070A, 78070AY

µ

PD78075B, 78075BY

µ

PD78098B

IEA-718 IEA-1289 All subseries in 78K/0 series except

µ

PD78002 and

78002Y subseries

IEA-744 IEA-1301

µ

PD78014 only

µ

PD78014 and

78P014

Explains floating-point operation programs of products in 78K/0 series

Contents

Explains basic functions of products in 78K/0 series by using program examples

Explains how to organize electronic pocketbook by using

µ

PD78014 subseries

Caution The application examples and program lists shown in this Application Note assume that the main system clock operates at 4.19 MHz, not at 5.0 MHz.

How to Read This Manual

Although this Application Note explains the functions of the 78K/0 series products, the functions of some products in each subseries differ from those of the others.

(1/2)

Chapter

Subseries

µ

PD78054

µ

PD78064

µ

PD78078

µ

PD78083

µ

PD78098

µ

PD780018

µ

PD780058

µ

PD78054Y

µ

PD78064Y

µ

PD78078Y

µ

PD780018Y

µ

PD780058Y

CHAPTER 1 GENERAL

CHAPTER 2 FUNDAMENTALS

OF SOFTWARE

CHAPTER 3 APPLICATIONS

OF SYSTEM CLOCK SELECTION

CHAPTER 4 APPLICATIONS OF

WATCHDOG TIMER

CHAPTER 5 APPLICATIONS OF

16-BIT TIMER/EVENT COUNTER

CHAPTER 6 APPLICATIONS OF

8-BIT TIMER/EVENT COUNTER

CHAPTER 7 APPLICATIONS OF

WATCH TIMER

CHAPTER 8 APPLICATIONS OF

SERIAL INTERFACE

CHAPTER 9 APPLICATIONS OF

A/D CONVERTER

CHAPTER 10 APPLICATIONS

OF D/A CONVERTER

CHAPTER 11 APPLICATION OF

REAL-TIME OUTPUT PORT

CHAPTER 12 APPLICATIONS

OF LCD CONTROLLER/DRIVER

CHAPTER 13 APPLICATIONS

OF KEY INPUT

– –

Chapter

Subseries

µ

PD780308

µ

PD78058F

µ

PD780308Y

µ

PD78058FY

CHAPTER 1 GENERAL

CHAPTER 2 FUNDAMENTALS

OF SOFTWARE

CHAPTER 3 APPLICATIONS

OF SYSTEM CLOCK SELECTION

CHAPTER 4 APPLICATIONS OF

WATCHDOG TIMER

CHAPTER 5 APPLICATIONS OF

16-BIT TIMER/EVENT COUNTER

CHAPTER 6 APPLICATIONS OF

8-BIT TIMER/EVENT COUNTER

CHAPTER 7 APPLICATIONS OF

WATCH TIMER

CHAPTER 8 APPLICATIONS OF

SERIAL INTERFACE

CHAPTER 9 APPLICATIONS OF

A/D CONVERTER

CHAPTER 10 APPLICATIONS

OF D/A CONVERTER

CHAPTER 11 APPLICATION OF

REAL-TIME OUTPUT PORT

CHAPTER 12 APPLICATIONS

OF LCD CONTROLLER/DRIVER

CHAPTER 13 APPLICATIONS

OF KEY INPUT

(2/2)

µ

PD78064B

µ

PD78070A

µ

PD78075B

µ

PD78098B

µ

PD78070AY

µ

PD78075BY

– –

Legend

Quality Grade

The (A)-model and standard models differ only in quality grade.

The

µ

PD78081(A2) differs from standard models and (A)-models in terms of supply voltage and operating temperature range. For details, refer to the individual Data

Sheet.

In this document, read (A)-models and (A2)-model as follows:

µ

PD78052

→ µ

PD78052(A)

µ

PD78054

→ µ

PD78054(A)

µ

PD78063

→ µ

PD78063(A)

µ

PD78081

→ µ

PD78081(A)

µ

PD78P083

→ µ

PD78P083(A)

µ

PD78058F

→ µ

PD78058F(A)

µ

PD78064B

→ µ

PD78064B(A)

µ

PD78053

→ µ

PD78053(A)

µ

PD78062

→ µ

PD78062(A)

µ

PD78064

→ µ

PD78064(A)

µ

PD78082

→ µ

PD78082(A)

µ

PD78081

→ µ

PD78081(A2)

µ

PD78058FY

→ µ

PD78058FY(A)

Data significance

Low active

: Left: higher digit, right: lower digit

:

×××

(top bar over pin or signal name)

: Description of Note in the text

Note

Caution

: Important information

Remark

: Supplement

Numeric representation : Binary ...

××××

or

××××

B

Decimal ...

××××

Hexadecimal ...

××××

H

Standard

µ

PD78052, 78053, 78054, 78055, 78056, 78058, 78P058

µ

PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y, 78P058Y

µ

PD78062, 78063, 78064, 78P064

µ

PD78062Y, 78063Y, 78064Y

µ

PD78076, 78078, 78P078

µ

PD78076Y, 78078Y, 78P078Y

µ

PD78081, 78082, 78P083

µ

PD78094, 78095, 78096, 78098A, 78P098A

µ

PD780016, 780018, 78P0018

µ

PD780016Y, 780018Y, 78P0018Y

µ

PD780053, 780054, 780055, 780056, 780058, 78F0058

µ

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y, 78F0058Y

µ

PD780306, 780308, 78P0308

µ

PD780306Y, 780308Y, 78P0308Y

µ

PD78056F, 78058F, 78P058F

µ

PD78056FY, 78058FY, 78P058FY

µ

PD78064B, 78P064B

µ

PD78070A, 78070AY

µ

PD78074B, 78075B

µ

PD78074BY, 78075BY

µ

PD78095B, 78096B, 78098B, 78P098B

Special

µ

PD78052(A), 78053(A), 78054(A)

µ

PD78062(A), 78063(A), 78064(A)

µ

PD78082(A), 78083(A), 78P083(A), 78081(A2)

µ

PD78058F(A), 78058FY(A)

µ

PD78064B(A)

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Application Field

Consumer appliances

Related documents

Some of the related documents listed below are preliminary versions but not so specified here.

• Common related documents

Document Name

78K/0 Series Application Note - Basic (III)

78K/0 Series Application Note - Floating-Point Operation Program

78K/0 Series User’s Manual - Instruction

78K/0 Series Instruction Set

78K/0 Series Instruction Table

Document Number

Japanese English

U10182J

IEA-718

This document

IEA-1289

U12326J

U10904J

U10903J

U12326E

• Documents dedicated to product

(1)

µ

PD78054 subseries

Document Name

µ

PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet

µ

PD78P054 Data Sheet

µ

PD78P058 Data Sheet

µ

PD78054,

µ

PD78054Y Subseries User’s Manual

µ

PD78054 Subseries Special Function Register Table

µ

PD78052(A), 78053(A), 78054(A) Data Sheet

(2)

µ

PD78054Y subseries

Document Name

µ

PD78052Y, 78053Y, 78054Y, 78056Y, 78058Y Data Sheet

µ

PD78P058Y Data Sheet

µ

PD78054, 78054Y Subseries User’s Manual

µ

PD78054Y Subseries Special Function Register Table

(3)

µ

PD78064 subseries

Document Name

µ

PD78062, 78063, 78064 Data Sheet

µ

PD78P064 Data Sheet

µ

PD78062(A), 78063(A), 78064(A) Data Sheet

µ

PD78064, 78064Y Subseries User’s Manual

µ

PD78064 Subseries Special Function Register Table

(4)

µ

PD78064Y subseries

Document Name

µ

PD78062Y, 78063Y, 78064Y Data Sheet

µ

PD78064, 78064Y Subseries User’s Manual

µ

PD78064Y Subseries Special Function Register Table

Document Number

Japanese English

U12327J

U12346J

IC-3403

U12346E

IC-8884

U11747J

U10102J

U12171J

U10417E

U11747E

U12171E

Document Number

Japanese English

U10906J

U10907J

U11747J

U10087J

U10906E

U10907E

U11747E

Document Number

Japanese English

U12238J

U12589J

U12338E

U12589E

U10335J

U10105J

IEM-5568

U10335E

U10105E

Document Number

Japanese English

U10330J

U10105J

IEM-5583

U10330E

U10105E

(5)

µ

PD78078 subseries

Document Name

µ

PD78076, 78078 Data Sheet

µ

PD78P078 Data Sheet

µ

PD78078 Subseries User’s Manual

µ

PD78078 Subseries Special Function Register Table

(6)

µ

PD78078Y subseries

Document Name

µ

PD78076Y, 78078Y Data Sheet

µ

PD78P078Y Data Sheet

µ

PD78078, 78078Y Subseries User’s Manual

µ

PD78078Y Subseries Special Function Register Table

(7)

µ

PD78083 subseries

Document Name

µ

PD78081, 78082 Data Sheet

µ

PD78P083 Data Sheet uPD78081(A), 78082(A) Data Sheet uPD78P083(A) Data Sheet

µ

PD78083 Subseries User’s Manual

µ

PD78083 Subseries Special Function Register Table

(8)

µ

PD78098 subseries

Document Name

µ

PD78094, 78095, 78096, 78098A Data Sheet

µ

PD78P098A Data Sheet

µ

PD78098 Subseries User’s Manual

µ

PD78098 Subseries Special Function Register List

Document Number

Japanese English

U10167J

U10168J

U10167E

U10168E

U10641J

IEM-5607

U10641E

Document Number

Japanese English

U10605J

U10606J

U10605E

U10606E

U10641J

U10257J

U10641E

Document Number

Japanese English

U11415J

U11006J

U11415E

U11006E

U12436J

U12175J

U12176J

IEM-5599

To be released soon

U12175E

U12176E

Document Number

Japanese English

U10146J

U10203J

U10146E

U10203E

IEU-854

IEM-5591

IEU-1381

(9)

µ

PD780018 subseries

Document Name

µ

PD780016, 780018 Preliminary Product Information

µ

PD78P0018 Preliminary Product Information

µ

PD780018, 780018Y Subseries User’s Manual

(10)

µ

PD780018Y subseries

Document Name

µ

PD780016Y, 780018Y Preliminary Product Information

µ

PD78P0018Y Preliminary Product Information

µ

PD780018, 780018Y Subseries User’s Manual

(11)

µ

PD780058 subseries

Document Name

µ

PD780053, 780054, 780055, 780056, 780058

Preliminary Product Information

µ

PD78F0058 Preliminary Product Information

µ

PD780058, 780058Y Subseries User’s Manual

(12)

µ

PD780058, 780058Y subseries

Document Name

µ

PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y

Preliminary Product Information

µ

PD78F0058Y Preliminary Product Information

µ

PD780058, 780058Y Subseries User’s Manual

(13)

µ

PD780308 subseries

Document Name

µ

PD780306, 780308 Data Sheet

µ

PD78P0308 Preliminary Product Information

µ

PD780308, 780308Y Subseries User’s Manual

Document Number

Japanese English

Plan to prepare

Plan to prepare

Plan to prepare

Plan to prepare

Plan to prepare

Plan to prepare

Document Number

Japanese English

U11810J

Plan to prepare

Plan to prepare

U11810E

Plan to prepare

Plan to prepare

Document Number

Japanese English

U12182J U12182E

U12092J

U12013J

U12092E

U12013E

Document Number

Japanese English

Plan to prepare Plan to prepare

U12324J

U12013J

U12324E

U12013E

Document Number

Japanese English

U11105J

U11776J

U11377J

U11105E

U11776E

U11377E

(14)

µ

PD780308Y subseries

Document Name

µ

PD780306Y, 780308Y Data Sheet

µ

PD78P0308Y Preliminary Product Information

µ

PD780308, 780308Y Subseries User’s Manual

(15)

µ

PD78058F subseries

Document Name

µ

PD78056F, 78058F Data Sheet

µ

PD78P058F Data Sheet

µ

PD78058F(A) Data Sheet

µ

PD78058F, 78058FY Subseries User’s Manual

(16)

µ

PD78058FY subseries

Document Name

µ

PD78056FY, 78058FY Data Sheet

µ

PD78P058FY Data Sheet

µ

PD78058F, 78058FY Subseries User’s Manual

(17)

µ

PD78064B subseries

Document Name

µ

PD78064B Data Sheet

µ

PD78064B(A) Data Sheet

µ

PD78P064B Data Sheet

µ

PD780308, 780308Y User’s Manual

Document Number

Japanese English

U12251J

U11832J

U11377J

U12251E

U11832E

U11377E

Document Number

Japanese English

U11795J

U11796J

U11795E

U11796E

To be released soon Plan to prepare

U12068J U12068E

Document Number

Japanese English

U12142J

U12076J

U12068J

U12142E

U12076E

To be released soon

Document Number

Japanese English

U11590J

U11597J

U11590E

U11597E

U11598J

U10785J

U11598E

U10785E

(18)

µ

PD78070A, 78070AY subseries

Document Name

µ

PD78070A Data Sheet

µ

PD78070AY Data Sheet

µ

PD78070A, 78070AY User’s Manual

µ

PD78070A

µ

PD78070AY

(19)

µ

PD78075B subseries

Document Name

µ

PD78074B, 78075B Data Sheet

µ

PD78075B, 78075BY Subseries User’s Manual

(20)

µ

PD78075BY subseries

Document Name

µ

PD78074BY, 78075BY Data Sheet

µ

PD78075B, 78075BY Subseries User’s Manual

(21)

µ

PD78098B subseries

Document Name

µ

PD78095B, 78096B, 78098B Data Sheet

µ

PD78P098B Data Sheet

µ

PD78098B Subseries User’s Manual

Document Number

Japanese English

U10326J

U10542J

IEU-907

U10133J

U10134J

Japanese

U12017J

U12560J

Japanese

Plan to prepare

U12560J

U10326E

U10542E

U10200E

Document Number

English

U12017E

To be released soon

Document Number

English

Plan to prepare

To be released soon

Document Number

Japanese

Plan to prepare

Plan to prepare

English

Plan to prepare

Plan to prepare

To be released soon Plan to prepare

The contents of the above related documents are subject to change without notice. Be sure to use the latest edition when you design your system.

CONTENTS

CHAPTER 1 GENERAL ................................................................................................................... 1

1.1 Product Development of 78K/0 Series ....................................................................... 1

1.2 Features of 78K/0 Series .............................................................................................. 3

CHAPTER 2 FUNDAMENTALS OF SOFTWARE .......................................................................... 57

2.1 Data Transfer .................................................................................................................. 57

2.2 Data Comparison ........................................................................................................... 58

2.3 Decimal Addition ........................................................................................................... 59

2.4 Decimal Subtraction ...................................................................................................... 66

2.5 Binary-to-Decimal Conversion ..................................................................................... 68

2.6 Bit Manipulation Instruction ......................................................................................... 70

2.7 Binary Multiplication (16 bits

×

16 bits) ..................................................................... 71

2.8 Binary Division (32 bits

÷

16 bits) ............................................................................... 75

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION ................................................. 79

3.1 Changing PCC Immediately after RESET ................................................................... 89

3.2 Selecting Power ON/OFF .............................................................................................. 91

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER ............................................................... 95

4.1 Setting Watchdog Timer Mode .................................................................................... 101

4.2 Setting Interval Timer Mode ......................................................................................... 103

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ......................................... 105

5.1 Setting of Interval Timer ............................................................................................... 116

5.2 PWM Output .................................................................................................................... 118

5.3 Remote Controller Signal Reception .......................................................................... 121

5.3.1 Remote controller signal reception by counter clearing ................................................ 123

5.3.2 Remote controller signal reception by PWM output and free running mode ................ 137

5.4 One-Shot Pulse Output ................................................................................................. 152

5.5 PPG Output ..................................................................................................................... 156

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER ........................................... 163

6.1 Setting of Interval Timer ............................................................................................... 171

6.1.1 Setting of 8-bit timers ...................................................................................................... 172

6.1.2 Setting of 16-bit timer ...................................................................................................... 173

6.2 Musical Scale Generation ............................................................................................. 174

CHAPTER 7 APPLICATIONS OF WATCH TIMER ........................................................................ 181

7.1 Watch and LED Display Program ................................................................................ 187

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE .............................................................. 195

8.1 Interface with EEPROM

TM

(

µ

PD6252) .........................................................................

240

8.1.1 Communication in 2-wire serial I/O mode ...................................................................... 242

8.1.2 Communication in I

2

C bus mode .................................................................................... 250

– i –

8.2

Interface with OSD LSI (

µ

PD6451A) ............................................................................

260

8.3

Interface in SBI Mode ....................................................................................................

265

8.3.1

Application as master CPU .............................................................................................

267

8.3.2

Application as slave CPU ................................................................................................

276

8.4

Interface in 3-Wire Serial I/O Mode .............................................................................

279

8.4.1

Application as master CPU .............................................................................................

280

8.4.2

Application as slave CPU ................................................................................................

283

8.5

Interface in Asynchronous Serial Interface (UART) Mode ......................................

286

CHAPTER 9 APPLICATIONS OF A/D CONVERTER ...................................................................

299

9.1

Level Meter .....................................................................................................................

307

9.2

Thermometer ..................................................................................................................

316

9.3

Analog Key Input ...........................................................................................................

326

9.4

4-Channel Input A/D Conversion .................................................................................

332

CHAPTER 10 APPLICATIONS OF D/A CONVERTER .................................................................

337

10.1

SIN Wave Output ............................................................................................................

338

CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT ...................................................

345

11.1

Stepping Motor ...............................................................................................................

348

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER ...............................................

351

12.1

Static Display .................................................................................................................

360

12.2

4-Time Division Display ................................................................................................

366

CHAPTER 13 APPLICATIONS OF KEY INPUT ............................................................................

373

APPENDIX A DESCRIPTION OF SPD CHART .............................................................................

379

APPENDIX B REVISION HISTORY ...............................................................................................

387

– ii –

LIST OF FIGURES (1/6)

Fig. No.

1-9.

1-10.

1-11.

1-12.

1-13.

1-14.

1-15.

1-16.

1-1.

1-2.

1-3.

1-4.

1-5.

1-6.

1-7.

1-8.

1-17.

1-18.

1-19.

1-20.

1-21.

1-22.

2-1.

2-2.

2-3.

2-4.

2-5.

2-6.

2-7.

2-8.

3-1.

3-2.

3-3.

3-4.

3-5.

3-6.

Title

Block Diagram of

µ

PD78054 Subseries .......................................................................................

Block Diagram of

µ

PD78054Y Subseries ....................................................................................

Block Diagram of

µ

PD78064 Subseries .......................................................................................

Block Diagram of

µ

PD78064Y Subseries ....................................................................................

Block Diagram of

µ

PD78078 Subseries .......................................................................................

Block Diagram of

µ

PD78078Y Subseries ....................................................................................

Block Diagram of

µ

PD78083 Subseries .......................................................................................

Block Diagram of

µ

PD78098 Subseries .......................................................................................

Block Diagram of

µ

PD780018 Subseries .....................................................................................

Block Diagram of

µ

PD780018Y Subseries ..................................................................................

Block Diagram of

µ

PD780058 Subseries .....................................................................................

Block Diagram of

µ

PD780058Y Subseries ..................................................................................

Block Diagram of

µ

PD780308 Subseries .....................................................................................

Block Diagram of

µ

PD780308Y Subseries ..................................................................................

Block Diagram of

µ

PD78058F Subseries ....................................................................................

Block Diagram of

µ

PD78058FY Subseries ..................................................................................

Block Diagram of

µ

PD78064B Subseries ....................................................................................

Block Diagram of

µ

PD78070A .....................................................................................................

Block Diagram of

µ

PD78070AY ...................................................................................................

Block Diagram of

µ

PD78075B Subseries ....................................................................................

Block Diagram of

µ

PD78075BY Subseries ..................................................................................

Block Diagram of

µ

PD78098B Subseries ....................................................................................

Page

35

37

39

42

23

26

29

32

14

16

18

20

10

12

4

7

45

47

49

51

53

55

Data Exchange ............................................................................................................................

Data Comparison .........................................................................................................................

Decimal Addition ..........................................................................................................................

Decimal Subtraction .....................................................................................................................

Binary-to-Decimal Conversion .....................................................................................................

Bit Operation ................................................................................................................................

Binary Multiplication .....................................................................................................................

Binary Division .............................................................................................................................

68

70

71

75

57

58

59

66

Format of Processor Clock Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,78070AY) ....................

Format of Processor Clock Control Register (

µ

PD78083 subseries) ...........................................

Format of Processor Clock Control Register (

µ

PD78098, 78098B subseries) ............................

Format of Processor Clock Control Register (

µ

PD780018, 780018Y subseries) ........................

Format of Oscillation Mode Select Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) .....................................................................................................................................

Format of Oscillation Mode Select Register (

µ

PD78098, 78098B subseries) .............................

85

85

81

82

83

84

– iii –

LIST OF FIGURES (2/6)

5-2.

5-3.

5-4.

5-5.

5-6.

5-7.

5-8.

5-9.

5-10.

5-11.

5-12.

5-13.

5-14.

5-15.

5-16.

5-17.

6-1.

Fig. No.

3-7.

3-8.

3-9.

3-10.

3-11.

3-12.

4-1.

4-2.

4-3.

4-4.

4-5.

4-6.

Title Page

Format of Oscillation Mode Select Register

(

µ

PD780018, 780018Y subseries) ...............................................................................................

Format of Clock Select Register 1 (

µ

PD78098, 78098B subseries) ............................................

Format of Clock Select Register 2 (

µ

PD78098, 78098B subseries) ............................................

Example of Selecting CPU Clock after RESET (with

µ

PD78054 subseries) ...............................

Example of System Clock Changing Circuit ................................................................................

Example of Changing System Clock on Power Failure (

µ

PD78054 subseries) ...........................

Format of Timer Clock Select Register 2

(

µ

PD78054 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) ...................

Format of Timer Clock Select Register 2 (

µ

PD78083 subseries) ................................................

Format of Timer Clock Select Register 2 (

µ

PD78098, 78098B subseries) ..................................

Format of Timer Clock Select Register 2 (

µ

PD780018, 780018Y subseries) ..............................

96

97

98

99

Format of Watchdog Timer Mode Register ..................................................................................

100

Count Timing of Watchdog Timer ................................................................................................

103

86

86

86

89

90

90

5-1.

6-2.

Format of Timer Clock Select Register 0

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F,

78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) .................................

106

Format of Timer Clock Select Register 0 (

µ

PD78098, 78098B subseries) ..................................

108

Format of Timer Clock Select Register 0 (

µ

PD780018, 780018Y subseries) ..............................

109

Format of 16-Bit Timer Mode Control Register ............................................................................

110

Format of Capture/Compare Control Register .............................................................................

111

Format of 16-Bit Timer Output Control Register ..........................................................................

112

Format of Port Mode Register 3 ...................................................................................................

113

Format of External Interrupt Mode Register 0 ..............................................................................

113

Format of Sampling Clock Select Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) ...................

114

Format of Sampling Clock Select Register (

µ

PD78098, 78098B subseries) ...............................

115

Format of Sampling Clock Select Register (

µ

PD780018, 780018Y subseries) ...........................

115

Example of Remote Controller Signal Receiver Circuit ...............................................................

121

Remote Controller Signal Transmitter IC Output Signal ..............................................................

122

Output Signal of Receiver Preamplifier ........................................................................................

122

Sampling of Remote Controller Signal .........................................................................................

123

Timing of One-Shot Pulse Output Operation by Software Trigger ...............................................

153

PPG Output Waveform Changing Timing ....................................................................................

156

Format of Timer Clock Select Register 1

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) ...................

164

Format of Timer Clock Select Register 1 (

µ

PD78098, 78098B subseries) ..................................

166

– iv –

LIST OF FIGURES (3/6)

Fig. No.

6-3.

6-4.

6-5.

6-6.

6-7.

6-8.

6-9.

7-1.

7-2.

7-3.

7-4.

7-5.

7-6.

7-7.

7-8.

8-1.

8-2.

8-3.

8-4.

8-5.

8-6.

8-7.

8-8.

8-9.

8-10.

Title Page

Format of Timer Clock Select Register 1 (

µ

PD780018, 780018Y subseries) ..............................

167

Format of 8-Bit Timer Mode Control Register ..............................................................................

168

Format of 8-Bit Timer Output Control Register ............................................................................

169

Format of Port Mode Register 3 ...................................................................................................

170

Count timing of 8-Bit Timers ........................................................................................................

171

Musical Scale Generation Circuit .................................................................................................

174

Timer Output and Interval ............................................................................................................

174

Format of Timer Clock Select Register 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) ...................

182

Format of Timer Clock Select Register 2 (

µ

PD78098, 78098B subseries) ..................................

183

Format of Timer Clock Select Register 2 (

µ

PD780018, 780018Y subseries) ..............................

184

Format of Watch Timer Mode Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) .....................................................................................................................................

185

Format of Watch Timer Mode Control Register (

µ

PD78098, 78098B subseries) ........................

186

Concept of Watch Data ................................................................................................................

187

LED Display Timing ......................................................................................................................

188

Circuit Example of Watch Timer ..................................................................................................

188

Format of Timer Clock Select Register 3

(

µ

PD78054, 78078, 780058, 78058F, 78075B subseries,

µ

PD78070A) .....................................

198

Format of Timer Clock Select Register 3

(

µ

PD78054Y, 78078Y, 780058Y, 78058FY, 78075BY subseries,

µ

PD78070AY) .......................

199

Format of Timer Clock Select Register 3 (

µ

PD78064, 780308, 78064B subseries) ....................

200

Format of Timer Clock Select Register 3 (

µ

PD78064Y, 780308Y subseries) .............................

201

Format of Timer Clock Select Register 3 (

µ

PD78098, 78098B subseries) ..................................

202

Format of Timer Clock Select Register 3 (

µ

PD780018, 780018Y subseries) ..............................

203

Format of Serial Operating Mode Register 0

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,

78098B subseries,

µ

PD78070A) ..................................................................................................

204

Format of Serial Operating Mode Register 0

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308, 78058FY, 78075BY subseries,

µ

PD78070AY) ..............................................................................................................................

206

Format of Serial Bus Interface Control Register

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries,

µ

PD78070A) ...............................................................................................................

208

Format of Serial Bus Interface Control Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) ..............................................................................................................................

210

– v –

LIST OF FIGURES (4/6)

Fig. No.

8-11.

8-12.

8-13.

8-14.

8-15.

8-16.

8-17.

8-18.

8-19.

8-20.

8-21.

8-22.

8-23.

8-24.

8-25.

8-26.

8-27.

8-28.

Title Page

Format of Interrupt Timing Specification Register

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,

78098B subseries,

µ

PD78070A) ..................................................................................................

212

Format of Interrupt Timing Specification Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 78008Y, 78058FY, 78075BY subseries,

µ

PD78070AY) ..............................................................................................................................

213

Format of Serial Operating Mode Register 1

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY) .................................

215

Format of Automatic Data Transfer/Reception Control Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B,

78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ................................................................

216

Format of Automatic Data Transfer/Reception Control Register

(

µ

PD780058, 780058Y subseries) ...............................................................................................

217

Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) ...............................................

218

Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78098, 78098B subseries) ...................................................................................................

224

Format of Serial Operating Mode Register 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ................................................................................................................

227

Format of Asynchronous Serial Interface Mode Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ................................................................................................................

228

Format of Asynchronous Serial Interface Status Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ................................................................................................................

234

Format of Baud Rate Generator Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) .....................................................................................................................................

235

Format of Baud Rate Generator Control Register (

µ

PD78098, 78098B subseries) ....................

237

Format of Serial Interface Pin Select Register (

µ

PD780058 and 780058Y Subseries) ...............

239

Format of Serial Interface Pin Select Register

(

µ

PD780308 and 780308Y Subseries) ........................................................................................

239

Pin Configuration of

µ

PD6252 .....................................................................................................

240

Example of Connection of

µ

PD6252 ............................................................................................

242

Communication Format of

µ

PD6252 ............................................................................................

243

Example of Connection between

µ

PD6252 and I

2

C Bus Mode ...................................................

250

– vi –

LIST OF FIGURES (5/6)

9-6.

9-7.

9-8.

9-9.

9-10.

9-11.

9-12.

9-13.

9-14.

9-15.

10-1.

10-2.

10-3.

10-4.

Fig. No.

8-37.

8-38.

8-39.

8-40.

8-41.

8-42.

8-43.

8-29.

8-30.

8-31.

8-32.

8-33.

8-34.

8-35.

8-36.

9-1.

9-2.

9-3.

9-4.

9-5.

Title Page

µ

PD6252 Operation Timing ........................................................................................................

251

Example of Connecting

µ

PD6451A .............................................................................................

260

Communication Format of

µ

PD6451A .........................................................................................

260

Example of Connection in SBI Mode ...........................................................................................

265

Communication Format in SBI Mode ...........................................................................................

266

ACK Signal in Case of Time out ..................................................................................................

267

Testing Bus Line ..........................................................................................................................

267

Example of Connection in 3-Wire Serial I/O Mode ......................................................................

279

Communication Format in 3-Wire Serial I/O Mode ......................................................................

279

Output of Busy Signal ..................................................................................................................

283

Communication Block Diagram ....................................................................................................

288

Communication Format ................................................................................................................

289

Reception Format ........................................................................................................................

289

Timing of Reception Completion Interrupt (when ISRM = 1) .......................................................

295

Receive Buffer Register Reading Disabled Period ......................................................................

296

Format of A/D Converter Mode Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) .....................................................................................................................................

300

Format of A/D Converter Mode Register (

µ

PD78098, 78098B subseries) ..................................

301

Format of A/D Converter Mode Register (

µ

PD780018, 780018Y subseries) ..............................

302

Format of A/D Converter Input Select Register ...........................................................................

303

Format of External Interrupt Mode Register 1 ..............................................................................

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B,

78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ................................................................

304

Format of External Interrupt Mode Register 1

(

µ

PD78064, 78064Y, 780058, 780058Y, 780308, 780308Y, 78064B subseries) ........................

305

Format of External Interrupt Mode Register 1 (

µ

PD78083 subseries) .........................................

306

Format of A/D Current Cut Select Register (

µ

PD78098, 78098B subseries) ..............................

306

Example of Level Meter Circuit ....................................................................................................

307

A/D Conversion Result and Display .............................................................................................

307

Concept of Peak Hold ..................................................................................................................

308

Circuit Example of Thermometer .................................................................................................

316

Temperature vs. Output Characteristic ........................................................................................

317

Example of Analog Key Input Circuit ...........................................................................................

327

Timing Chart in 4-Channel Scan Mode ........................................................................................

332

Format of D/A Converter Mode Register .....................................................................................

337

Analog Output and Output Data Storage Timing .........................................................................

338

D/A Output Waveform ..................................................................................................................

338

SIN Wave Conversion Circuit ......................................................................................................

340

– vii –

LIST OF FIGURES (6/6)

Fig. No.

Title Page

11-1.

11-2.

11-3.

11-4.

Format of Real-Time Output Port Mode Register ........................................................................

346

Format of Real-Time Output Port Control Register ......................................................................

346

Format of Port Mode Register 12 .................................................................................................

347

Phase Excitation Output Pattern and Output Timing ...................................................................

348

12-1.

12-2.

12-3.

12-4.

12-5.

12-6.

12-7.

12-8.

12-9.

12-10.

12-11.

12-12.

12-13.

12-14.

Format of LCD Display Mode Register (

µ

PD78064, 78064Y, 78064B subseries) .......................

352

Format of LCD Display Mode Register (

µ

PD780308, 780308Y subseries) .................................

353

Format of LCD Display Control Register ......................................................................................

354

Relations between Contents of LCD Display Data Memory and Segment/Common Output .......

356

Common Signal Waveform ..........................................................................................................

358

Phase Difference in Voltage between Command Signal and Segment Signal ............................

359

Display Pattern and Electrode Wiring of Static LCD ....................................................................

360

Connection of Static LCD .............................................................................................................

361

Example of Connecting LCD Driving Power in Static Display Mode

(with external divider resistor, V

DD

= 5 V, and V

LCD

= 5 V) ...........................................................

361

Example of Static LCD Driving Waveform ...................................................................................

362

Display Pattern of 4-Time Division LCD and Electrode Wiring ....................................................

366

Connections of 4-Time Division LCD Panel .................................................................................

367

Example of Connecting LCD Drive Power in 4-Time Division Mode

(with external divider resistor, V

DD

= 5 V, V

LCD

= 5 V) ..................................................................

367

Example of 4-Time Division LCD Driving Waveform ....................................................................

368

13-1.

Key Matrix Circuit .........................................................................................................................

373

– viii –

LIST OF TABLES (1/2)

1-9.

1-10.

1-11.

1-12.

1-13.

1-14.

1-15.

1-16.

1-1.

1-2.

1-3.

1-4.

1-5.

1-6.

1-7.

1-8.

1-17.

1-18.

1-19.

1-20.

1-21.

1-22.

Table. No.

Title

Functional Outline of

µ

PD78054 Subseries .................................................................................

Functional Outline of

µ

PD78054Y Subseries ...............................................................................

Functional Outline of

µ

PD78064 Subseries .................................................................................

Functional Outline of

µ

PD78064Y Subseries ...............................................................................

Functional Outline of

µ

PD78078 Subseries .................................................................................

Functional Outline of

µ

PD78078Y Subseries ...............................................................................

Functional Outline of

µ

PD78083 Subseries .................................................................................

Functional Outline of

µ

PD78098 Subseries .................................................................................

Functional Outline of

µ

PD780018 Subseries ...............................................................................

Functional Outline of

µ

PD780018Y Subseries .............................................................................

Functional Outline of

µ

PD780058 Subseries ...............................................................................

Functional Outline of

µ

PD780058Y Subseries .............................................................................

Functional Outline of

µ

PD780308 Subseries ...............................................................................

Functional Outline of

µ

PD780308Y Subseries .............................................................................

Functional Outline of

µ

PD78058F Subseries ...............................................................................

Functional Outline of

µ

PD78058FY Subseries ............................................................................

Functional Outline of

µ

PD78064B Subseries ...............................................................................

Functional Outline of

µ

PD78070A ................................................................................................

Functional Outline of

µ

PD78070AY .............................................................................................

Functional Outline of

µ

PD78075B8 Subseries .............................................................................

Functional Outline of

µ

PD78075BY Subseries ............................................................................

Functional Outline of

µ

PD78098B Subseries ...............................................................................

Page

36

38

40

43

24

27

30

33

15

17

19

21

11

13

5

8

46

48

50

52

54

56

3-1.

3-2.

3-3.

5-1.

5-2.

Maximum Time Required for Changing CPU Clock .....................................................................

Relation between CPU Clock and Minimum Instruction Execution Time

(other than

µ

PD78098 and 78098B subseries) ............................................................................

CPU Clock (f

CPU

) List (

µ

PD78098 and 78098B Subseries) ..........................................................

80

87

88

Valid Time of Input Signal ............................................................................................................

123

Valid Time of Input Signal ............................................................................................................

137

6-1.

8-1.

8-2.

8-3.

8-4.

8-5.

8-6.

Musical Scale and Frequency ......................................................................................................

17

Serial Interface Channel of Each Subseries ................................................................................

195

Items Supported by Each Subseries ............................................................................................

196

Registers of Serial Interface .........................................................................................................

197

Setting of Operation Modes of Serial Interface Channel 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 78058F, 78058FY,

78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY) ...................................

229

Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780058 and

780058Y Subseries) ....................................................................................................................

230

Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780308 and

780308Y Subseries) ....................................................................................................................

232

– ix –

LIST OF TABLES (2/2)

Table. No.

8-7.

8-8.

8-9.

8-10.

Title Page

Pin Function of

µ

PD6252 .............................................................................................................

241

µ

PD6252 Commands ...................................................................................................................

242

Signals in SBI Mode .....................................................................................................................

266

Relations between Main System Clock and Baud Rate (at f

X

= 4.19 MHz) .................................

287

9-1.

9-2.

9-3.

A/D Conversion Value and Temperature .....................................................................................

318

Input Voltage and Key Code ........................................................................................................

326

Resistances of R1 through R5 .....................................................................................................

327

10-1.

11-1.

12-1.

12-2.

12-3.

12-4.

A-1.

Voltage of SIN Wave Output and Preset Value ...........................................................................

Operation Mode and Output Trigger of Real-Time Output Port ...................................................

Select and Unselect Voltages (COM0, 1, 2, 3) ............................................................................

Comparison between SPD Symbols and Flowchart Symbol .......................................................

339

346

Maximum Number of Pixels for Display .......................................................................................

355

COM Signal ..................................................................................................................................

357

Select and Unselect Voltages (COM0) ........................................................................................

360

366

379

– x –

CHAPTER 1 GENERAL

1.1 Product Development of 78K/0 Series

The following shows the products organized according to usage. The names in the parallelograms are subseries names.

78K/0

Series

Products in mass production

Products under development

Y subseries products are compatible with I

2

C bus.

100-pin

100-pin

100-pin

100-pin

80-pin

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

42/44-pin

Control

µ

PD78075B

µ

PD78078

µ

PD78070A

µ

PD780058

µ

PD78058F

µ

PD78054

µ

PD780034

µ

PD780024

µ

PD78014H

µ

PD78018F

µ

PD78014

µ

PD780001

µ

PD78002

µ

PD78083

µ

PD78075BY

µ

PD78078Y

µ

PD78070AY

µ

PD780018AY

µ

PD780058Y

Note

µ

PD78058FY

µ

PD78054Y

µ

PD780034Y

µ

PD780024Y

µ

µ

µ

PD78018FY

PD78014Y

PD78002Y Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

64-pin

64-pin

Inverter control

µ

PD780964

µ

PD780924

FIP

TM

drive

On-chip inverter control circuit and UART. EMI-noise was reduced.

100-pin

100-pin

80-pin

80-pin

100-pin

100-pin

100-pin

PD780228

µ

PD78044H

µ

PD78044F

LCD drive

µ

PD780308

µ

PD78064B

µ

PD78064

µ

µ

PD780308Y

PD78064Y

Basic subseries for driving FIP, Display output total: 34

Basic subseries for driving LCDs, On-chip UART

80-pin

80-pin

IEBus

TM

supported

µ

PD78098B

µ

PD78098

80-pin

64-pin

Meter control

µ

PD780973

LV

µ

PD78P0914

On-chip automobile meter driving controller/driver

On-chip PWM output, LV digital code decoder, and Hsync counter

Note Under planning

1

CHAPTER 1 GENERAL

The following lists the main functional differences between subseries products.

Function

ROM

Capacity

Subseries Name

Control

µ

PD78075B 32K-40K

µ

PD78078 48K-60K

µ

PD78070A –

µ

PD780058 24K-60K

µ

PD78058F 48K-60K

µ

PD78054 16K-60K

µ

PD780034 8K-32K

µ

PD780024

µ

PD78014H

µ

PD78018F 8K-60K

µ

PD78014 8K-32K

µ

PD780001 8K

µ

PD78002

µ

PD78083

8K-16K

Inverter

µ

PD780964 8K-32K control

µ

PD780924

FIP drive

µ

PD780208 32K-60K

µ

PD780228 48K-60K

µ

PD78044H 32K-48K

µ

PD78044F 16K-40K

LCD drive

µ

PD780308 48K-60K

µ

PD78064B 32K

Meter control

µ

PD78064 16K-32K

IEBus

µ

PD78098 supported

µ

PD78098B

40K-60K

32K-60K

µ

PD780973 24K-32K

LV

µ

PD78P0914 32K

Timer

8-bit 10-bit 8-bit

8-bit 16-bit Watch WDT A/D

A/D D/A

Serial Interface

4ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART: 1ch)

2ch

8ch

8ch

2ch 3ch (time division UART: 1ch)

3ch (UART: 1ch)

3ch (UART: 1ch, time division 3-wire: 1ch)

2ch

– –

1ch

8ch

1ch

1ch (UART: 1ch)

3ch Note – 1ch – 8ch – 2ch (UART: 2ch)

8ch –

2ch 1ch 1ch 1ch 8ch –

3ch

2ch

2ch

3ch

6ch

2ch 1ch 1ch

1ch

1ch

1ch

1ch 1ch

1ch 1ch

1ch 1ch

– 1ch

8ch

8ch

5ch

8ch

2ch

1ch

I/O

88

61

68

69

51

53

2ch

– 3ch (time division UART: 1ch) 57

2ch (UART: 1ch)

2ch 3ch (UART: 1ch)

2ch (UART: 1ch)

2ch

39

53

33

47

74

72

68

69

56

54

V

DD

MIN.

External

Value Expansion

1.8 V

2.7 V

1.8 V

2.7 V

2.0 V

1.8 V

1.8 V

2.7 V

1.8 V

2.7 V

2.7 V

4.5 V

2.7 V

2.0 V

2.7 V

4.5 V

4.5 V

Note 10-bit timer: 1 channel

2

CHAPTER 1 GENERAL

1.2 Features of 78K/0 Series

The 78K/0 series is a collection of 8-bit single-chip microcontrollers ideal for commercial systems.

The

µ

PD78054 and 78054Y subseries are provided with peripheral hardware functions such as an A/D converter,

D/A converter, timer, serial interface, real-time output port, and interrupt function.

The

µ

PD78064 and 78064Y subseries are provided with peripheral hardware functions such as an LCD controller/ driver, A/D converter, timer, serial interface, and interrupt function.

The

µ

PD78078 and 78078Y subseries are based on the

µ

PD78054 and 78054Y subseries with a timer added and the external interface function reinforced.

The

µ

PD78083 subseries is provided with peripheral hardware functions such as an A/D converter, timer, serial interface, and interrupt function.

The

µ

PD78098 subseries is based on the

µ

PD78054 subseries with an IEBus controller added.

The

µ

PD780018 and 780018Y subseries are versions of the

µ

PD78078 and 78078Y subseries (serial interface with time division transfer function) with an improved serial interface and a limited number of functions.

The

µ

PD780058 and 780058Y subseries are low-EMI noise versions of the

µ

PD78054 and 78054Y subseries

(serial interface with time division transfer function), with an improved serial interface.

The

µ

PD780308 and 780308Y subseries are versions of the

µ

PD78064 and 78064Y subseries with increased ROM and RAM with an improved serial interface.

The

µ

PD78058F, 78058FY, 78064B, 78075B, 78075BY, and 78098B subseries are low-EMI noise versions of the

µ

PD78054, 78054Y, 78064, 78078, 78078Y, and 78098 subseries.

The

µ

PD78070A and 78070AY subseries are the ROM-less versions of the

µ

PD78078 and 78078Y subseries.

The

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries and

µ

PD78070AY are provided with I

2

C bus control function instead of the SBI function of the

µ

PD78054, 78064, 78078, 780058, 780308,

78058F, 78075B subseries and

µ

PD78070A.

In addition, one-time PROM, EPROM, or flash-memory models that can operate at the same operating voltage as the mask ROM models and that are ideal for early and small-scale production of the application system are also available.

The block diagram and function outline of each series is shown on the following pages.

3

CHAPTER 1 GENERAL

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

Figure 1-1. Block Diagram of

µ

PD78054 Subseries

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

78K/0

CPU CORE

ROM

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

SERIAL

INTERFACE 1

PORT7

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

RAM

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

PCL/P35

V

DD

V

SS

IC

(V

PP

)

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P054, 78P058

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

4

CHAPTER 1 GENERAL

Table 1-1. Functional Outline of

µ

PD78054 Subseries (1/2)

A/D converter

D/A converter

Serial interface

Timer

Item

µ

PD78052

µ

PD78053

µ

PD78054

µ

PD78P054

µ

PD78055

µ

PD78056

µ

PD78058

µ

PD78P058

Note 1 Note 2

Part Number

Internal memory

ROM

High-speed RAM

Mask ROM PROM

16K bytes 24K bytes 32K bytes

32K bytes

Note 2

Mask ROM

40K bytes 48K bytes 60K bytes

PROM

60K bytes

Note 3

512 bytes 1024 bytes

1024 bytes

Note 3

1024 bytes

1024 bytes

Note 3

Buffer RAM

32 bytes

Expansion RAM

None

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

1024 bytes

1024 bytes

Note 4

I/O port • Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The

µ

PD78P054 is a PROM model of the

µ

PD78052, 78053, and 78054.

2. The

µ

PD78P058 is a PROM model of the

µ

PD78055, 78056, and 78058.

3. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS).

4. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

5

CHAPTER 1 GENERAL

Table 1-1. Functional Outline of

µ

PD78054 Subseries (2/2)

source

Test input

Software

Item µ

PD78052

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable

µ

PD78053

µ

PD78054

µ

PD78P054

Note 1

µ

PD78055

µ

PD78056

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

1

Internal: 1, external: 1

µ

PD78058

µ

PD78P058

Note 2

Supply voltage

Package

V

DD

= 2.0 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Note 3

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm) (

µ

PD78052, 78053, 78054, 78P054, 78058 only)

• 80-pin ceramic WQFN (14

×

14 mm) (

µ

PD78P054, 78P058 only)

Notes 1. The

µ

PD78P054 is a PROM model of the

µ

PD78052, 78053, and 78054.

2. The

µ

PD78P058 is a PROM model of the

µ

PD78055, 78056, and 78058.

3. Under planning

6

CHAPTER 1 GENERAL

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

Figure 1-2. Block Diagram of

µ

PD78054Y Subseries

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

78K/0

CPU CORE

ROM

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

SERIAL

INTERFACE 1

PORT7

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

RAM

V

DD

V

SS

IC

(V

PP

)

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

Remarks 1. The capacities of the internal ROM and RAM differ depending on the model.

2. ( ):

µ

PD78P058Y

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

7

CHAPTER 1 GENERAL

Table 1-2. Functional Outline of

µ

PD78054Y Subseries (1/2)

Item

µ

PD78052Y

µ

PD78053Y

µ

PD78054Y

µ

PD78055Y

µ

PD78056Y

µ

PD78058Y

µ

PD78P058Y

Part Number

Internal memory

ROM Mask ROM

16K bytes 24K bytes 32K bytes

1024 bytes

PROM

40K bytes 48K bytes 60K bytes

60K bytes

Note 1

1024 bytes

Note 1

High-speed RAM 512 bytes

Buffer RAM 32 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Expansion RAM None

A/D converter

D/A converter

Serial interface

1024 bytes

1024 bytes

Note 2

• Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer

Timer output

Clock output

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS).

2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

8

CHAPTER 1 GENERAL

Table 1-2. Functional Outline of

µ

PD78054Y Subseries (2/2)

Item

µ

PD78052Y

µ

PD78053Y

µ

PD78054Y

µ

PD78055Y

µ

PD78056Y

µ

PD78058Y

µ

PD78P058Y

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Package

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.0 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Note

• 80-pin ceramic WQFN (14

×

14 mm)(

µ

PD78P058Y only)

Note

Under planning

9

CHAPTER 1 GENERAL

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF

Figure 1-3. Block Diagram of

µ

PD78064 Subseries

16-bit TIMER/

EVENT COUNTER

PORT0

PORT1

8-bit TIMER/EVENT

COUNTER 1

PORT2

8-bit TIMER/EVENT

COUNTER 2

PORT3

PORT7

WATCHDOG TIMER

PORT8

WATCH TIMER

78K/0

CPU CORE

ROM

PORT9

SERIAL

INTERFACE 0

PORT10

SERIAL

INTERFACE 2

A/D CONVERTER

RAM

PORT11

LCD

CONTROLLER/

DRIVER

INTP0/P00-

INTP5/P05

INTERRUPT

CONTROL

BUZ/P36

BUZZER OUTPUT

PCL/P35

CLOCK OUTPUT

CONTROL

V

DD

V

SS

IC

(V

PP

)

SYSTEM

CONTROL

P00

P01-P05

P07

P10-P17

P25-P27

P30-P37

P70-P72

P80-P87

P90-P97

P100-P103

P110-P117

S0-S23

S24/P97-

S31/P90

S32/P87-

S39/P80

COM0-COM3

V

LC0

-V

LC2

BIAS f

LCD

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P064

10

CHAPTER 1 GENERAL

Table 1-3. Functional Outline of

µ

PD78064 Subseries

Item

µ

PD78062

µ

PD78063

µ

PD78064

Part Number

Internal memory

ROM

Mask ROM

16K bytes 24K bytes 32K bytes

High-speed RAM

512 bytes

LCD display RAM

40

×

4 bits

Memory space

General-purpose register

1024 bytes

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

µ

PROM

PD78P064

32K bytes

Note 1

1024 bytes

Note 1

I/O port

(including pins multiplexed with segment signal output)

A/D converter

• Total : 57

• CMOS input : 2

• CMOS I/O : 55

8-bit resolution

×

8 channels

LCD controller/driver

• Segment signal output : 40 max.

• Common signal output : 4 max.

• Bias : 1/2 or 1/3 bias selectable

Serial interface

Timer

Timer output

Clock output

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored interrupt source

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 12, external: 6

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.0 to 6.0 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm, resin thickness 1.45 mm)

• 100-pin plastic LQFP (fine pitch) (14

×

14 mm, resin thickness 1.4 mm)

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin ceramic WQFN (14

×

20 mm)

Note 2

(

µ

PD78P064 only)

Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS).

2. Under development

11

CHAPTER 1 GENERAL

Figure 1-4. Block Diagram of

µ

PD78064Y Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

PORT0

PORT1

PORT2

TO2/P32

TI2/P34

8-bit TIMER/EVENT

COUNTER 2

PORT3

PORT7

WATCHDOG TIMER

PORT8

WATCH TIMER

78K/0

CPU CORE

ROM

PORT9

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SDL/P27

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF

SERIAL

INTERFACE 0

SERIAL

INTERFACE 2

A/D CONVERTER

RAM

PORT10

PORT11

LCD

CONTROLLER/

DRIVER

INTP0/P00-

INTP5/P05

INTERRUPT

CONTROL

BUZ/P36

PCL/P35

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL V

DD

V

SS

IC

SYSTEM

CONTROL

P00

P01-P05

P07

P10-P17

P25-P27

P30-P37

P70-P72

P80-P87

P90-P97

P100-P103

P110-P117

S0-S23

S24/P97-

S31/P90

S32/P87-

S39/P80

COM0-COM3

V

LC0

-V

LC2

BIAS f

LCD

RESET

X1

X2

XT1/P07

XT2

Remark The internal ROM and RAM capacities differ depending on the model.

12

CHAPTER 1 GENERAL

Table 1-4. Functional Outline of

µ

PD78064Y Subseries

Item

µ

PD78062Y

µ

PD78063Y

Part Number

Internal memory

ROM Mask ROM

16K bytes 24K bytes

High-speed RAM 512 bytes

LCD display RAM 40

×

4 bits

Memory space

General-purpose register

1024 bytes

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz) Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

(including pins multiplexed with segment signal output)

A/D converter

• Total : 57

• CMOS input : 2

• CMOS I/O : 55

8-bit resolution

×

8 channels

LCD controller/driver

Serial interface

• Segment signal output : 40 max.

• Common signal output : 4 max.

• Bias : 1/2 or 1/3 bias selectable

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer • 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

µ

32K bytes

PD78064Y

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 12, external: 6

Internal: 1

1

Test input

Supply voltage

Package

Internal: 1, external: 1

V

DD

= 2.0 to 6.0 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm, resin thickness 1.45 mm)

• 100-pin plastic LQFP (fine pitch) (14

×

14 mm, resin thickness 1.4 mm)

• 100-pin plastic QFP (14

×

20 mm)

13

CHAPTER 1 GENERAL

Figure 1-5. Block Diagram of

µ

PD78078 Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

TI5/TO5/P100

TI6/TO6/P101

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

78K/0

CPU CORE

ROM

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

RAM

PCL/P35

V

DD

V

SS

IC

(V

PP

)

Remarks 1. The internal ROM capacitiy differs depending on the model.

2. ( ):

µ

PD78P078

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT8

PORT9

PORT10

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P60-P67

P70-P72

P80-P87

P90-P96

P100-P103

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

14

CHAPTER 1 GENERAL

Table 1-5. Functional Outline of

µ

PD78078 Subseries

A/D converter

D/A converter

Item

µ

PD78076

µ

PD78078

Part Number

Internal memory

ROM

Mask ROM

48K bytes 60K bytes

High-speed RAM

1024 bytes

Buffer RAM

32 bytes

Expansion RAM

1024 bytes

Memory space

General-purpose register

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz) Minimum With main instruction system clock execution With subsystem timon clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Serial interface

Timer

PROM

µ

60K bytes

PD78P078

Note 1

• Total

• CMOS input

: 88

: 2

• CMOS I/O : 78

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Vectored interrupt source

Test input

Package

Maskable

Non-maskable

Software

Supply voltage

Internal: 15, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm, resin thickness 1.45 mm)

• 100-pin plastic LQFP (fine pitch) (14

×

14 mm, resin thickness 1.4 mm)

Note 2

• 100-pin plastic QFP (14

×

20 mm, resin thickness 2.7 mm)

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P078 only)

Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS).

2. Under planning

15

CHAPTER 1 GENERAL

Figure 1-6. Block Diagram of

µ

PD78078Y Subseries

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

IC

(V

PP

)

PORT4

PORT5

PORT6

PORT7

PORT8

PORT0

PORT1

PORT2

PORT3

PORT9

PORT10

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P70-P72

P80-P87

P90-P96

P100-P103

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

16

Remarks 1. The internal ROM capacity differs depending on the model.

2. ( ):

µ

PD78P078Y

CHAPTER 1 GENERAL

Table 1-6. Functional Outline of

µ

PD78078Y Subseries

Item

µ

PD78076Y

Part Number

Internal memory

ROM Mask ROM

48K bytes

High-speed RAM 1024 bytes

Buffer RAM 32 bytes

µ

60K bytes

PD78078Y

PROM

µ

60K bytes

PD78P078Y

Note 1

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Expansion RAM 1024 bytes

A/D converter

D/A converter

Serial interface

Timer

• Total

• CMOS input

: 88

: 2

• CMOS I/O : 78

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Package

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 15, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

• 100-pin plastic QFP (14

×

20 mm, resin thickness 2.7 mm)

• 100-pin plastic LQFP (fine pitch) (14

×

14 mm, resin thickness 1.4 mm)

Note 2

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P078Y only)

Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS).

2. Under development

17

CHAPTER 1 GENERAL

SI2/RxD/P70

SO2/TxD/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF1

INTP1/P01-

INTP3/P03

BUZ/P36

PCL/P35

TI5/TO5/P100

TI6/TO6/P101

Figure 1-7. Block Diagram of

µ

PD78083 Subseries

8-bit TIMER/

EVENT COUNTER 5

PORT0

5-bit TIMER/

EVENT COUNTER 6

WATCHDOG TIMER

SERIAL

INTERFACE 2

78K/0

CPU CORE

ROM

PORT1

PORT3

PORT5

A/D CONVERTER

RAM

PORT7

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

V

DD

V

SS

IC

(V

PP

)

PORT10

SYSTEM

CONTROL

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P083

P00

P01-P03

P10-P17

P30-P37

P50-P57

P70-P72

P100, P101

RESET

X1

X2

18

CHAPTER 1 GENERAL

Table 1-7. Functional Outline of

µ

PD78083 Subseries

Item

Memory space

General-purpose register

Minimum instruction execution time

Instruction set

µ

PD78081

µ

PD78082

Part Number

Internal memory

ROM Mask ROM

8K bytes

High-speed RAM 256 bytes

16K bytes

384 bytes

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s

(with main system clock of 5.0 MHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

Serial interface

Timer

Timer output

Clock output

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

• Total : 33

• CMOS input : 1

• CMOS I/O : 32

8-bit resolution

×

8 channels

3-wire serial I/O/UART mode selectable: 1 channel

• 8-bit timer/event counter : 2 channels

• Watchdog timer : 1 channel

2 (8-bit PWM output)

PROM

24K bytes

512 bytes

µ

PD78P083

Note 1

Note 1

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz

(with main system clock of 5.0 MHz)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 8, external: 3

Supply voltage

Package

Internal: 1

1

V

DD

= 1.8 to 5.5 V

Note 2

• 42-pin plastic shrink DIP (600 mil)

• 42-pin ceramic shrink DIP (with window) (600 mil) (

µ

PD78P083 only)

• 44-pin plastic QFP (10

×

10 mm)

Notes 1. The capacities of the internal PROM and internal-high-speed RAM can be changed by using a memory size select register. (IMS)

2. The supply voltage (V

DD

) of the

µ

PD78081(A2) is 4.5 to 5.5 V.

19

CHAPTER 1 GENERAL

Figure 1-8. Block Diagram of

µ

PD78098 Subseries

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF1

ANO0/P130,

ANO1/P131

AV

SS

AV

REF0

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

IC

(V

PP

)

EXTERNAL

ACCESS

SYSTEM

CONTROL

PORT4

PORT5

PORT6

PORT7

PORT0

PORT1

PORT2

PORT3

PORT12

PORT13

REAL-TIME

OUTPUT PORT

IEBus

CONTROLLER

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

TX/P124/RTP4

RX/P125/RTP5

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P098A

20

CHAPTER 1 GENERAL

Table 1-8. Functional Outline of

µ

PD78098 Subseries (1/2)

Item

µ

PD78094

µ

PD78095

µ

PD78096

µ

PD78098A

Note 1

µ

PD78P098A

Note 1, 2

Part Number

Internal memory

ROM

40K bytes 48K bytes 60K bytes

PROM

60K bytes

Note 3

High-speed RAM 1024 bytes

Buffer RAM 32 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.5

µ s/1.0

µ s/2.0

µ s/4.0

µ s/8.0

µ s/16.0 (at 6.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Expansion RAM None

IEBus controller

A/D converter

D/A converter

Serial interface

Timer

2048 bytes 2048 bytes

Note 4

• Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O: 4

Effective transfer rate: 3.9 kbps/17 kbps/26 kbps

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

Mask ROM

32K bytes

3 (14-bit PWM output: 1)

15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz, 4.0 MHz (with main system clock of 6.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. Under development

2. The

µ

PD78P098A is the PROM model of the

µ

PD78094, 78095, 78096, and 78098A.

3. The internal PROM capacity can be changed by using a memory size select register (IMS).

4. The internal expansion RAM can be changed by using an internal expansion RAM size select register

(IXS).

21

CHAPTER 1 GENERAL

Table 1-8. Functional Outline of

µ

PD78098 Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source

Test input

Software

µ

PD78094

µ

PD78095

µ

PD78096

µ

PD78098A

Note 1

977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (with main system clock of 6.0 MHz)

Internal: 14, external: 7

Internal: 1

1

µ

PD78P098A

Note 1, 2

Supply voltage

Package

Internal: 1, external: 1

V

DD

= 2.7 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm)

• 80-pin ceramic WQFN (14

×

14 mm)

Note 1

(

µ

PD78P098A only)

Notes 1. Under development

2. The

µ

PD78P098A is a PROM model of the

µ

PD78094, 78095, 78096, and 78098A.

22

CHAPTER 1 GENERAL

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI4A/P90

SO4A/P91

SCK4A/P92

SI4B/P93

SO4B/P94

SCK4B/P95

SI4C/P110

SO4C/P111

SCK4C/P112

ANI0/P10-

ANI7/P17

AV

SS

AV

REF

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

Figure 1-9. Block Diagram of

µ

PD780018 Subseries

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

PORT0

PORT1

PORT2

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

78K/0

CPU CORE

ROM

PORT3

PORT4

PORT5

PORT6

PORT8

SERIAL

INTERFACE 1

PORT9

RAM

PORT10

SERIAL

INTERFACE 4

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

(V

PP

)

PORT11

PORT15

EXTERNAL

ACCESS

SYSTEM

CONTROL

Remarks 1. The internal ROM capacity differs depending on the model.

2. ( ):

µ

PD78P0018

P80-P87

P90-P96

P100-P103

P110-P117

P150-P156

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1

XT2

P00

P01-P06

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

23

CHAPTER 1 GENERAL

Table 1-9. Functional Outline of

µ

PD780018 Subseries (1/2)

Part Number

Item

µ

PD780016

µ

PD780018

Internal memory

ROM

Mask ROM

48K bytes 60K bytes

High-speed RAM

1024 bytes

Buffer RAM

32 bytes

Expansion RAM

1024 bytes

Memory space

General-purpose register

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s (at 5.0 MHz)

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

Serial interface

Timer

Timer output

Clock output

PROM

µ

60K bytes

PD78P0018

Note

• Total

• CMOS input

• CMOS I/O

: 88

: 9

: 79

8-bit resolution

×

8 channels

• 3-wire serial I/O mode (with automatical transfer/reception function)

• 3-wire serial I/O mode selectable (with time-division transfer function)

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

: 1 channel

: 1 channel

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Note The internal ROM capacity can be changed by using a memory size select register. (IMS)

Caution The

µ

PD780018 subseries is under planning.

24

CHAPTER 1 GENERAL

Table 1-9. Functional Outline of

µ

PD780018 Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Operating temperature

Package

µ

PD780016

µ

PD780018

2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 12, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.7 to 5.5 V

T

A

= –40 to +85

°

C

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P0018 only)

Caution The

µ

PD780018 subseries is under planning.

µ

PD78P0018

25

26

CHAPTER 1 GENERAL

Figure 1-10. Block Diagram of

µ

PD780018Y Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

78K/0

CPU CORE

ROM

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI4A/P90

SO4A/P91

SCK4A/P92

SI4B/P93

SO4B/P94

SCK4B/P95

SI4C/P110

SO4C/P111

SCK4C/P112

SDA/P116

SCL/P117

ANI0/P10-

ANI7/P17

AV

SS

AV

REF

INTP0/P00-

INTP6/P06

BUZ/P36

SERIAL

INTERFACE 1

SERIAL

INTERFACE 4

SERIAL

INTERFACE 5

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

RAM

PCL/P35

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

(V

PP

)

Remarks 1. The internal ROM capacity differs depending on the model.

2. ( ):

µ

PD78P0018Y

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT8

PORT9

PORT10

PORT11

PORT15

EXTERNAL

ACCESS

SYSTEM

CONTROL

P50-P57

P60-P67

P80-P87

P90-P96

P100-P103

P110-P117

P150-P156

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1

XT2

P00

P01-P06

P10-P17

P20-P27

P30-P37

P40-P47

CHAPTER 1 GENERAL

Table 1-10. Functional Outline of

µ

PD780018Y Subseries (1/2)

Item

Part Number

Internal memory

ROM

High-speed RAM 1024 bytes

Buffer RAM 32 bytes

µ

Mask ROM

48K bytes

PD780016Y

µ

60K bytes

PD780018Y

PROM

µ

60K bytes

PD78P018Y

Note

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

Expansion RAM 1024 bytes

A/D converter

Serial interface

Timer

• Total

• CMOS input

• CMOS I/O

: 88

: 9

: 79

8-bit resolution

×

8 channels

• 3-wire serial I/O mode (with automatical transfer/reception function)

• 3-wire serial I/O mode selectable (with time-division transfer function)

• I

2

C bus mode (multi-master compatible)

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

: 1 channel

: 1 channel

: 1 channel

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Note The internal PROM capacity can be changed by using a memory size select register. (IMS)

Caution The

µ

PD780018Y subseries is under development.

27

CHAPTER 1 GENERAL

Table 1-10. Functional Outline of

µ

PD78P0018Y Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Operating temperature

Package

µ

PD780016Y

µ

PD780018Y

2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 12, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.7 to 5.5 V

T

A

= –40 to +85

°

C

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P0018Y only)

µ

PD78P018Y

Caution The

µ

PD780018Y subseries is under development.

28

CHAPTER 1 GENERAL

Figure 1-11. Block Diagram of

µ

PD780058 Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/TxD1/P23

BUSY/RxD1/P24

BUSY/RxD1/P24

STB/TxD1/P23

SI2/RxD0/P70

SO2/TxD0/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP5/P05

BUZ/P36

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

FLASH

MEMORY

RAM

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

PCL/P35

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

(V

PP

)

Remarks 1. The capacities of the internal ROM and RAM differ depending on the model.

2. ( ):

µ

PD78F0058

P00

P01-P05

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

29

CHAPTER 1 GENERAL

Table 1-11. Functional Outline of

µ

PD780058 Subseries (1/2)

Item

µ

PD780053

Part Number

Internal memory

ROM

Mask ROM

24K bytes

High-speed RAM

1024 bytes

Buffer RAM 32 bytes

Expansion RAM None

Timer output

Clock output

µ

PD780054

32K bytes

µ

PD780055

40K bytes

µ

PD780056

48K bytes

µ

PD780058

60K bytes

µ

PD78F0058

Flash memory

60K bytes

Note 1

1024 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

• Total

• CMOS input

: 68

: 2

• CMOS I/O : 62

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable (with time-division transfer function) : 1 channel

Timer

1024 bytes

Note 2

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The capacities of the flash memory can be changed by using a memory size select register (IMS).

2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

Caution The

µ

PD780058 subseries is under development.

30

CHAPTER 1 GENERAL

Table 1-11. Functional Outline of

µ

PD780058 Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Operating temperature

Package

µ

PD780053

µ

PD780054

µ

PD780055

µ

PD780056

µ

PD780058

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

T

A

= –40 to +85

°

C

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Note

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

µ

PD78F0058

Note Under planning

Caution The

µ

PD780058 subseries is under development.

31

CHAPTER 1 GENERAL

Figure 1-12. Block Diagram of

µ

PD780058Y Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/TxD1/P23

BUSY/RxD1/P24

BUSY/RxD1/P24

STB/TxD1/P23

SI2/RxD0/P70

SO2/TxD0/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP5/P05

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

FLASH

MEMORY

RAM

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

(V

PP

)

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P40-P47

P50-P57

P60-P67

P70-P72

P00

P01-P05

P07

P10-P17

P20-P27

P30-P37

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The capacities of the internal ROM and RAM differ depending on the model.

2. ( ):

µ

PD78F0058Y

32

CHAPTER 1 GENERAL

Table 1-12. Functional Outline of

µ

PD780058Y Subseries (1/2)

Item

µ

PD780053Y

µ

PD780054Y

µ

PD780055Y

µ

PD780056Y

µ

PD780058Y

µ

PD78F0058Y

Part Number

Internal memory

ROM

Mask ROM

24K bytes

High-speed RAM

1024 bytes

Buffer RAM 32 bytes

Expansion RAM None

32K bytes 40K bytes 48K bytes 60K bytes

1024 bytes

Flash memory

60K bytes

Note 1

1024 bytes

Note 2

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

• Total

• CMOS input

: 68

: 2

• CMOS I/O : 62

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable (with time-division transfer function) : 1 channel

Timer

Timer output

Clock output

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The capacities of the flash memory can be changed by using a memory size select register (IMS).

2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

Caution The

µ

PD780058Y subseries is under planning.

33

CHAPTER 1 GENERAL

Table 1-12. Functional Outline of

µ

PD780058Y Subseries (2/2)

Item

µ

PD780053Y

µ

PD780054Y

µ

PD780055Y

µ

PD780056Y

µ

PD780058Y

µ

PD78F0058Y

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable

Software

Test input

Supply voltage

Operating temperature

Package

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

T

A

= –40 to +85

°

C

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

Caution The

µ

PD780058Y subseries is under planning.

34

CHAPTER 1 GENERAL

Figure 1-13. Block Diagram of

µ

PD780308 Subseries

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI2/R

X

D/P70

SO2/T

X

D/P71

R

X

D/P114

T

X

D/P113

SCK2/ASCK/P72

SI3/P110

SO3/P111

SCK3/P112

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF

INTP0/P00-

INTP5/P05

BUZ/P36

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

PCL/P35

SERIAL

INTERFACE 2

SERIAL

INTERFACE 3

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD0

,

V

DD1

,

V

SS0

,

V

SS1

,

IC

(V

PP

)

Remarks 1. The internal ROM capacity differs depending on the model.

2. ( ):

µ

PD78P0308

LCD

CONTROLLER/

DRIVER

SYSTEM

CONTROL

PORT0

PORT1

PORT2

PORT3

PORT7

PORT8

PORT9

PORT10

PORT11

P00

P01-P05

P07

P10-P17

P25-P27

P30-P37

P70-P72

P80-P87

P90-P97

P100-P103

P110-P117

S0-S23

S24/P97-

S31/P90

S32/P87-

S39/P80

COM0-COM3

V

LC0

-V

LC2

BIAS f

LCD

RESET

X1

X2

XT1/P07

XT2

35

CHAPTER 1 GENERAL

Table 1-13. Functional Outline of

µ

PD780308 Subseries

Part Number

Internal memory

ROM

Item

Mask ROM

48K bytes

µ

PD780306

60K bytes

µ

PD780308

High-speed RAM

1024 bytes

Expansion RAM

1024 bytes

LCD display RAM

40

×

4 bits

Memory space

General-purpose register

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

(including pins multiplexed with segment signal output)

A/D converter

• Total : 57

• CMOS input : 2

• CMOS I/O : 55

8-bit resolution

×

8 channels

LCD controller/driver

• Segment signal output : 40 max.

• Common signal output : 4 max.

• Bias : 1/2 or 1/3 bias selectable

Serial interface

Timer

Timer output

Clock output

PROM

µ

60K bytes

PD78P0308

Note

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable

• 3-wire serial I/O/UART mode selectable

• 3-wire serial I/O mode

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

: 1 channel

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored interrupt

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 6

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.0 to 5.5 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm)

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P0308 only)

Note The capacity of the internal PROM can be changed by using a memory size select register (IMS).

Caution The

µ

PD780308 subseries is under development.

36

CHAPTER 1 GENERAL

Figure 1-14. Block Diagram of

µ

PD780308Y Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

RxD/P114

TxD/P113

SCK0/SDL/P27

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

SI3/P110

SO3/P111

SCK3/P112

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF

INTP0/P00-

INTP5/P05

BUZ/P36

PCL/P35

SERIAL

INTERFACE 0

SERIAL

INTERFACE 2

SERIAL

INTERFACE 3

A/D CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD0

,

V

DD1

,

V

SS0

,

V

SS1

,

IC

LCD

CONTROLLER/

DRIVER

SYSTEM

CONTROL

PORT7

PORT8

PORT9

PORT10

PORT11

PORT0

PORT1

PORT2

PORT3

P00

P01-P05

P07

P10-P17

P25-P27

P30-P37

P70-P72

P80-P87

P90-P97

P100-P103

P110-P117

S0-S23

S24/P97-

S31/P90

S32/P87-

S39/P80

COM0-COM3

V

LC0

-V

LC2

BIAS f

LCD

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The internal ROM capacity differs depending on the model.

2. ( ):

µ

PD78P0308Y

37

CHAPTER 1 GENERAL

Table 1-14. Functional Outline of

µ

PD780308Y Subseries

Item

µ

PD780306Y

µ

PD780308Y

Part Number

Internal memory

ROM

Mask ROM

48K bytes 60K bytes

High-speed RAM

1024 bytes

Expansion RAM

1024 bytes

LCD display RAM

40

×

4 bits

Memory space

General-purpose register

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

Minimum With main

Instruction system clock execution With subsystem cycle clock

122

µ s (at 32.768 kHz)

Instruction set

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

PROM

µ

PD78P0308Y

60K bytes

Note

I/O port

(including pins multiplexed with segment signal output)

A/D converter

• Total : 57

• CMOS input : 2

• CMOS I/O : 55

8-bit resolution

×

8 channels

LCD controller/driver

Serial interface

• Segment signal output : 40 max.

• Common signal output : 4 max.

• Bias : 1/2 or 1/3 bias selectable

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable

• 3-wire serial I/O/UART mode selectable

• 3-wire serial I/O mode

Timer

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

: 1 channel

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Package

Internal: 13, external: 6

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.0 to 5.5 V

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin ceramic WQFN (14

×

20 mm) (

µ

PD78P0308Y only)

Note The capacity of the internal PROM can be changed by using a memory size select register (IMS).

Caution The

µ

PD780308Y subseries is under development.

38

CHAPTER 1 GENERAL

Figure 1-15. Block Diagram of

µ

PD78058F Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

REF0

ANO0/P130,

ANO1/P131

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

AV

DD

AV

SS

IC

(V

PP

)

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P058F

39

CHAPTER 1 GENERAL

Table 1-15. Functional Outline of

µ

PD78058F Subseries (1/2)

Part Number

Item

µ

PD78056F

µ

PD78058F

Internal memory

ROM

Mask ROM

48K bytes 60K bytes

High-speed RAM

1024 bytes

Buffer RAM

32 bytes

Expansion RAM

None

Memory space

General-purpose register

1024 bytes

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

Timer

Timer output

Clock output

PROM

µ

60K bytes

PD78P058F

Note 1

1024 bytes

Note 2

• Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The capacity of the internal PROM can be changed by using a memory size select register (IMS).

2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

40

CHAPTER 1 GENERAL

Table 1-15. Functional Outline of

µ

PD78058F Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Package

µ

PD78056F

µ

PD78058F

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

Internal: 1

Internal: 1, external: 1

V

DD

= 2.7 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Note

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm) (

µ

PD78058F only)

µ

PD78P058F

Note Under planning

41

CHAPTER 1 GENERAL

Figure 1-16. Block Diagram of

µ

PD78058FY Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

REF0

ANO0/P130,

ANO1/P131

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

AV

DD

AV

SS

IC

(V

PP

)

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The capacities of the internal ROM and RAM differ depending on the model.

2. ( ):

µ

PD78P058FY

42

CHAPTER 1 GENERAL

Table 1-16. Functional Outline of

µ

PD78058FY Subseries (1/2)

Item

µ

PD78056FY

µ

PD78058FY

µ

PD78P058FY

Part Number

Internal memory

ROM Mask ROM

48K bytes 60K bytes

PROM

60K bytes

Note 1

High-speed RAM 1024 bytes

Buffer RAM 32 bytes

Expansion RAM None 1024 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

1024 bytes

Note 2

• Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O : 4

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

Timer

Timer output

Clock output

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Notes 1. The capacity of the internal PROM can be changed by using a memory size select register (IMS).

2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS).

43

CHAPTER 1 GENERAL

Table 1-16. Functional Outline of

µ

PD78058FY Subseries (2/2)

Item

Part Number

Buzzer output

Vectored Maskable interrupt Non-maskable source Software

Test input

Supply voltage

Package

µ

PD78056FY

µ

PD78058FY

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 13, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.7 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Note

• 80-pin plastic TQFP (fine pitch)(12

×

12 mm) (

µ

PD78058FY only)

µ

PD78P058FY

Note Under planning

44

CHAPTER 1 GENERAL

Figure 1-17. Block Diagram of

µ

PD78064B Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

16-bit TIMER/

EVENT COUNTER

TO1/P31

TI1/P33

8-bit TIMER/EVENT

COUNTER 1

TO2/P32

TI2/P34

8-bit TIMER/EVENT

COUNTER 2

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

REF

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 2

A/D CONVERTER

78K/0

CPU CORE

ROM

RAM

PORT8

PORT9

PORT10

PORT11

PORT0

PORT1

PORT2

PORT3

PORT7

LCD

CONTROLLER/

DRIVER

INTP0/P00-

INTP5/P05

INTERRUPT

CONTROL

BUZ/P36

BUZZER OUTPUT

PCL/P35

CLOCK OUTPUT

CONTROL

V

DD

V

SS

AV

DD

AV

SS

IC

(V

PP

)

SYSTEM

CONTROL

P00

P01-P05

P07

P10-P17

P25-P27

P30-P37

P70-P72

P80-P87

P90-P97

P100-P103

P110-P117

S0-S23

S24/P97-

S31/P90

S32/P87-

S39/P80

COM0-COM3

V

LC0

-V

LC2

BIAS f

LCD

RESET

X1

X2

XT1/P07

XT2

Remark ( ):

µ

PD78P064B

45

CHAPTER 1 GENERAL

Table 1-17. Functional Outline of

µ

PD78064B Subseries

Item

µ

PD78064B

µ

PD78P064B

Part Number

Internal memory

ROM

Timer output

Clock output

Mask ROM

32K bytes

PROM

High-speed RAM 1024 bytes

LCD display RAM 40

×

4 bits

Memory space

General-purpose register

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz) Minimum With main instruction system clock execution With subsystem time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

(including pins multiplexed with segment signal output)

A/D converter

• Total : 57

• CMOS input : 2

• CMOS I/O : 55

8-bit resolution

×

8 channels

LCD controller/driver • Segment signal output : 40 max.

• Common signal output : 4 max.

• Bias : 1/2 or 1/3 bias selectable

Serial interface

Timer

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable

• 3-wire serial I/O/UART mode selectable

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

: 1 channel

: 1 channel

3 (14-bit PWM output: 1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored interrupt source

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 12, external: 6

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.0 to 6.0 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm)

• 100-pin plastic QFP (14

×

20 mm)

46

CHAPTER 1 GENERAL

Figure 1-18. Block Diagram of

µ

PD78070A

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

RAM

V

DD

V

SS

IC

PORT0

PORT1

P00

P01-P06

P07

P10-P17

PORT2

PORT3

P20-P27

P30-P37

PORT6

P60-P63,P66

P70-P72 PORT7

PORT9

P90-P96

P100-P103 PORT10

PORT12

P120-P127

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P130, P131

RTP0/P120-

RTP7/P127

AD0-AD7

A0-A15

RD

WR

WAIT/P66

RESET

X1

X2

XT1/P07

XT2

47

CHAPTER 1 GENERAL

Table 1-18. Functional Outline of

µ

PD78070A

Internal memory

Part Number

ROM

High-speed RAM

None

1024 bytes

Functions

Buffer RAM 32 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

Timer

• Total

• CMOS input

: 61

: 2

• CMOS I/O : 51

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serail I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Vectored Maskable interrupt Non-maskable source

Test input

Software

Supply voltage

Package

Internal: 15, external: 7

Internal: 1

1

Internal: 1

V

DD

= 2.7 to 5.5 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm)

• 100-pin plastic QFP (14

×

20 mm)

48

CHAPTER 1 GENERAL

Figure 1-19. Block Diagram of

µ

PD78070AY

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

RAM

V

DD

V

SS

IC

PORT0

PORT1

PORT2

PORT3

PORT6

PORT7

PORT9

P70-P72

P90-P96

PORT10

PORT12

P100-P103

P120-P127

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P130, P131

RTP0/P120-

RTP7/P127

AD0-AD7

A0-A15

RD

WR

WAIT/P66

RESET

X1

X2

XT1/P07

XT2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P60-P63, P66

49

CHAPTER 1 GENERAL

Table 1-19. Functional Outline of

µ

PD78070AY

Internal memory

Part Number

ROM

High-speed RAM

None

1024 bytes

Buffer RAM 32 bytes

Functions

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

Timer

• Total

• CMOS input

: 61

: 2

• CMOS I/O : 51

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored interrupt source

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 15, external: 7

Internal: 1

1

Internal: 1

V

DD

= 2.7 to 5.5 V

• 100-pin plastic QFP (14

×

20 mm)

• 100-pin plastic QFP (fine pitch) (14

×

14 mm)

50

CHAPTER 1 GENERAL

Figure 1-20. Block Diagram of

µ

PD78075B Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

EXTERNAL

ACCESS

SYSTEM

CONTROL

PORT4

PORT5

PORT6

PORT7

PORT0

PORT1

PORT2

PORT3

PORT8

PORT9

PORT10

PORT12

PORT13

REAL-TIME

OUTPUT PORT

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P80-P87

P90-P96

P100-P103

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remark The internal ROM capacity differs depending on the model.

51

CHAPTER 1 GENERAL

Table 1-20. Functional Outline of

µ

PD78075B8 Subseries

Part Number

Item

µ

PD78074B

µ

PD78075B

Internal memory

ROM

High-speed RAM

Mask ROM

32K bytes 40K bytes

Buffer RAM 1024 bytes

Expansion RAM

32 bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

A/D converter

D/A converter

Serial interface

Timer

Timer output

Clock output

Vectored interrupt source

Test input

Package

Maskable

Non-maskable

Software

Supply voltage

• Total

• CMOS input

: 88

: 2

• CMOS I/O : 78

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Internal: 15, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

• 100-pin plastic QFP (fine pitch) (14

×

14 mm, resin thickness 1.45 mm)

• 100-pin plastic QFP (14

×

20 mm, resin thickness 2.7 mm)

52

CHAPTER 1 GENERAL

Figure 1-21. Block Diagram of

µ

PD78075BY Subseries

SI0/SB0/SDA0/P25

SO0/SB1/SDA1/P26

SCK0/SCL/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

8-bit TIMER/EVENT

COUNTER 5

8-bit TIMER/EVENT

COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD0

,

V

DD1

V

SS0

,

V

SS1

IC

(V

PP

)

PORT4

PORT5

PORT6

PORT7

PORT0

PORT1

PORT2

PORT3

PORT8

PORT9

PORT10

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P60-P67

P70-P72

P80-P87

P90-P96

P100-P103

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

AD0/P40-

AD7/P47

A0/P80-

A7/P87

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

Remark The internal ROM capacity differs depending on the model.

53

CHAPTER 1 GENERAL

Table 1-21. Functional Outline of

µ

PD78075BY Subseries

Item

µ

PD78074BY

µ

PD78075BY

Part Number

Internal memory

ROM

Mask ROM

32K bytes 40K bytes

Memory space

General-purpose register

Minimum With main instruction system clock execution With subsystem time clock

Instruction set

64K bytes

8 bits

×

8

×

4 banks

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0 MHz)

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

High-speed RAM

1024 bytes

Buffer RAM 32 bytes

A/D converter

D/A converter

Serial interface

Timer

• Total

• CMOS input

: 88

: 2

• CMOS I/O : 78

• N-ch open-drain I/O : 8

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/2-wire serial I/O/I

2

C bus mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

5 (14-bit PWM output: 1, 8-bit PWM output: 2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

Buzzer output

Vectored interrupt source

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)

Internal: 15, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 1.8 to 5.5 V

• 100-pin plastic QFP (14

×

20 mm, resin thickness 2.7 mm)

Caution The

µ

PD78075BY subseries is under development.

54

CHAPTER 1 GENERAL

Figure 1-22. Block Diagram of

µ

PD78098B Subseries

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/R

X

D/P70

SO2/T

X

D/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

REF1

ANO0/P130,

ANO1/P131

AV

REF0

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/EVENT

COUNTER 1

8-bit TIMER/EVENT

COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

AV

DD

AV

SS

IC

(V

PP

)

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

IEBus

CONTROLLER

EXTERNAL

ACCESS

SYSTEM

CONTROL

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P72

P120-P127

P130, P131

RTP0/P120-

RTP7/P127

TX/P124/RTP4

RX/P125/RTP5

AD0/P40-

AD7/P47

A8/P50-

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

Remarks 1. The internal ROM and RAM capacities differ depending on the model.

2. ( ):

µ

PD78P098B

55

CHAPTER 1 GENERAL

Table 1-22. Functional Outline of

µ

PD78098B Subseries

Item

µ

PD78095B

µ

PD78096B

µ

PD78098B

Part Number

Internal memory

ROM

Mask ROM

40K bytes 48K bytes 60K bytes

High-speed RAM

1024 bytes

Buffer RAM

32 bytes

Expansion RAM

None

Memory space

General-purpose register

2048 bytes

64K bytes

8 bits

×

8

×

4 banks

0.5

µ s/1.0

µ s/2.0

µ s/4.0

µ s/8.0

µ s/16.0 (at 6.0 MHz)

Minimum With main instruction system clock execution With subsystem

time clock

Instruction set

122

µ s (at 32.768 kHz)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits, 16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjustment, etc.

I/O port

IEBus controller

A/D converter

D/A converter

Serial interface

Timer

µ

PD78P098B

PROM

60K bytes

Note 1

2048 bytes

Note 2

• Total

• CMOS input

: 69

: 2

• CMOS I/O : 63

• N-ch open-drain I/O: 4

Effective transfer rate: 3.9 kbps/17 kbps/26 kbps

8-bit resolution

×

8 channels

8-bit resolution

×

2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel

• 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel

• 3-wire serial I/O/UART mode selectable : 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Timer output

Clock output

Buzzer output

Vectored interrupt source

Test input

Supply voltage

Package

Maskable

Non-maskable

Software

3 (14-bit PWM output: 1)

15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz, 4.0 MHz (with main system clock of 6.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)

977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (with main system clock of 6.0 MHz)

Internal: 14, external: 7

Internal: 1

1

Internal: 1, external: 1

V

DD

= 2.7 to 6.0 V

• 80-pin plastic QFP (14

×

14 mm)

• 80-pin ceramic WQFN (14

×

14 mm) (

µ

PD78P098B only)

Notes 1. The internal PROM capacity can be changed by using a memory size select register (IMS).

2. The internal expansion RAM can be changed by using an internal expansion RAM size select register

(IXS).

Caution The

µ

PD78098B subseries is under planning.

56

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.1 Data Transfer

Data is exchanged by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be exchanged is specified by the B register.

Figure 2-1. Data Exchange

Address

DE + B – 1

Address

HL + B – 1

Data exchange

DE

(1) Registers used

A, B, DE, HL

(2) Program list

EXCH:

MOV

XCH

XCH

INCW

INCW

DBNZ

RET

A,[DE]

A,[HL]

A,[DE]

DE

HL

B,$EXCH

HL

57

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.2 Data Comparison

Data is compared by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be compared is specified by the B register. If the result of comparison is equal, CY is cleared to 0; if not, CY is set to 1.

Figure 2-2. Data Comparison

Address

DE + B – 1

Address

HL + B – 1

Data comparison

DE

(1) Registers used

A, B, DE, HL

(2) Program list

COMP:

ERROR:

SET1

RTN:

MOV

CMP

BNZ

INCW

INCW

DBNZ

CLR1

BR

RET

A,[DE]

A,[HL]

$ERROR

DE

HL

B,$COMP

CY

RTN

CY

HL

58

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.3 Decimal Addition

The lowest address for decimal addition is specified by the DE and HL registers, and the number of digits specified by BYTNUM is added. The result of the addition is stored to an area specified by the HL register. If an overflow or underflow occurs as a result of the addition, execution branches to error processing. Define the branch address as

‘ERROR’ in the main routine. Also declare it as PUBLIC.

Address

DE + BYTNUM – 1

Figure 2-3. Decimal Addition

Address

HL + BYTNUM – 1

Address

HL + BYTNUM – 1

+ =

DE

(1) Flowchart

HL HL

BCDADD

C

number of bytes for decimal addition

B

C – 1

Number of bytes for decimal addition without sign

BCDAD2

Signs of augend and addend same?

Yes

Decimal addition processing

No

RET

Decimal subtraction processing

59

60

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

DADDS

CY

0

Sign flag SFLAG

0

DADDS1

A

[DE] + [HL] + CY

Adds augend and addend with CY

Adjusts result to decimal and stores in memory

DE

DE + 1, HL

HL + 1

Increments addend and augend addresses

B

B – 1

No

B = 0

Yes

A

[DE] + [HL] + CY

Adds addend and augend with CY

CY = 1

Yes

Sign flag SFLAG

1

CY = 0

DADDS3

Result adjusted to decimal?

No

Yes

CY = 1

No

A7 = 1

No

Yes

No

Sign flag SFLAG = 1

Yes

A7

1

DADDS6

Stores A to memory

RET

ERROR

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

DSUBS

Makes subtrahend positive

Sign flag SFLAG

0

Minuend < 0

Yes

Makes subtrahend positive

Sign flag SFLAG

1

DSUBS1

B

C, CY

0

DSUBS2

A

[DE] – [HL] – CY

Subtracts subtrahend from minuend with CY

DE

DE + 1, HL

HL + 1

Increments subtrahend and minuend addresses

No

Adjusts result to decimal and stores in memory

C

C – 1

No

C = 0

Yes

CY = 1

Yes

Inverts sign flag that takes

10's complement

DSUBS5

Result = 0

No

No

Yes

Sign flag = 1

Yes

Appends negative sign to result

No

RET

61

62

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(2) Registers used

AX, BC, DE, HL

(3) Program list

;******************************************************************

; *

; Input parameter *

;

;

;

;

;

HL register: addend first address

DE register: augend first address

Output parameter

HL register: Operation result first address

*

*

*

*

*

;******************************************************************

;

EXTBIT SFLAG

;

BYTNUM EQU 4

CSEG

BCDADD:

MOV C,#BYTNUM

BCDAD1:

PUBLIC BCDADD,BCDAD1,BCDAD2

PUBLIC DADDS

PUBLIC DSUBS

EXTRN ERROR

MOV

MOV

DEC

A,C

B,A

B

BCDAD2:

MOV

XCHW

XCHW

XCHW

XOR

XCHW

XCHW

XCHW

A,[HL+BYTNUM–1]

AX,DE

AX,HL

AX,DE

A,[HL+BYTNUM–1]

AX,HL

AX,DE

AX,HL

; Error processing branch address

; Sign flag

; Sets number of digits for operation

; Sets number of digits for operation to C register

; Loads MSB (sign data) of augend

; Loads MSB (sign data) of augend

BCDAD3:

BT

CALL

RET

CALL

RET

A.7,$BCDAD3

!DADDS

!DSUBS

; Signs coincide? ELSE subtraction processing

; THEN addition processing

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

;=============================================================

; ***** 10 Decimal addition *****

;=============================================================

DADDS:

DADDS1:

CLR1

CLR1

MOV

ADDC

ADJBA

MOV

INCW

INCW

DBNZ

CY

SFLAG

A,[DE]

A,[HL]

[HL],A

HL

DE

B,$DADDS1

MOV

ADDC

DADDS2:

DADDS3:

ADJBA

BNC

BR

DADDS4:

DADDS5:

BF

BR

BF

SET1

DADDS6:

BNC

SET1

CLR1

MOV

RET

A,[DE]

A,[HL]

$DADDS3

SFLAG

CY

$DADDS4

ERROR

A.7,$DADDS5

ERROR

SFLAG,$DADDS6

A.7

[HL],A

; Starts addition from lowest digit

; End of addition (number of digits for operation – 1)

; Negative addition

; THEN sets negative status

; Sets sign

63

64

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

;================================================================

; ***** 10 Decimal subtraction *****

;================================================================

DSUBS:

DSUBS1:

DSUBS2:

XCHW

XCHW

XCHW

MOV

MOV

CLR1

PUSH

CLR1

MOV

CLR1

MOV

XCHW

XCHW

XCHW

MOV

BF

CLR1

MOV

SET1

MOV

SUBC

ADJBS

MOV

INCW

INCW

DBNZ

HL

SFLAG

A,[HL+BYTNUM–1]

A.7

[HL+BYTNUM–1],A

AX,DE

AX,HL

AX,DE

A,[HL+BYTNUM–1]

A.7,$DSUBS1

A.7

[HL+BYTNUM–1],A

SFLAG

AX,HL

AX,DE

AX,HL

A,C

B,A

CY

A,[DE]

A,[HL]

[HL],A

HL

DE

C,$DSUBS2

DSUBS3:

BNC

POP

PUSH

MOV

MOV

MOV

SUB

ADJBS

MOV

INCW

DBNZ

$DSUBS5

HL

HL

A,B

C,A

A,#99H

A,[HL]

[HL],A

HL

C,$DSUBS3

;

; Sets subtrahend as positive value

; Minuend is negative

; THEN sets minuend as positive value

; Sets sign as negative

; End of subtraction of number of digits for operation

; THEN subtrahend > minuend

; Complement operation of result of subtraction

(result of subtraction – 99H)

POP

PUSH

SET1

HL

HL

CY

MOV

MOV

DSUBS4:

MOV

ADDC

ADJBA

A,B

C,A

A,#0

A,[HL]

; Adds 1 to result of complement operation

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

MOV

INCW

[HL],A

HL

DBNZ

MOV1

C,$DSUBS4

CY,SFLAG

NOT1

MOV1

CY

SFLAG,CY

;======================================================

; ***** 0 check of operation result *****

;======================================================

DSUBS5:

MOV

MOV

POP

PUSH

MOV

DSUBS6:

CMP

INCW

BNZ

DBNZ

POP

RET

DSUBS7:

BF

POP

PUSH

MOV

SET1

MOV

DSUBS8:

POP

RET

A,B

C,A

HL

HL

A,#0

A,[HL]

HL

$DSUBS7

C,$DSUBS6

HL

SFLAG,$DSUBS8

HL

HL

A,[HL+BYTNUM–1]

A.7

[HL+BYTNUM–1],A

HL

; 0 check from lowest digit

; 0 check of all digits completed

; THEN result of subtraction = 0

; Result of subtraction is negative

; THEN sets sign

65

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.4 Decimal Subtraction

The lowest address for decimal subtraction is specified by the DE and HL registers, and the number of digits specified by BYTNUM is subtracted. The result of the subtraction is stored to an area specified by the HL register.

If an overflow or underflow occurs as a result of the subtraction, execution branches to error processing. Define the branch address as ‘ERROR’ in the main routine. Also declare it as PUBLIC.

This program replaces minuend and subtrahend with augend and addend, and calls a program of decimal addition.

Address

DE + BYTNUM – 1

Figure 2-4. Decimal Subtraction

Address

HL + BYTNUM – 1

Address

HL + BYTNUM – 1

– =

DE

(1) Flowchart

HL HL

BCDSUB

C

number of bytes for decimal subtraction

Inverts sign bit of subtrahend

Decimal addition with subtrahend and minuend as addend and augend

RET

(2) Registers used

AX, BC, DE, HL

66

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(3) Program list

;******************************************************************

; *

; Input parameter *

;

;

;

;

;

HL register: subtrahend first address

DE register: minuend first address

Output parameter

HL register: Operation result first address

*

*

*

*

*

;******************************************************************

PUBLIC BYTNUM

PUBLIC BCDSUB

EXTRN BCDADD,BCDAD2

;

BYTNUM EQU 4

;

CSEG

BCDSUB:

MOV C,#BYTNUM

BCDSU1:

MOV

MOV

DEC

A,C

B,A

B

MOV

MOV1

NOT1

MOV1

MOV

CALL

RET

A,[HL+BYTNUM–1]

CY,A.7

CY

A.7,CY

[HL+BYTNUM–1],A

!BCDAD2

; Sets number of digits for operation

; Sets number of digits for operation to C register

; Sets MSB (sign data) of subtrahend for addition

; Inverts sign data

; Calls decimal addition processing

67

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.5 Binary-to-Decimal Conversion

Binary data of 16 bits in data memory is converted into 5-digit decimal data and stored in data memory. Binary data of 16 bits is divided by decimal 10 by the number of times equal to the number of digits (4 times), and conversion is carried out with the result of the operation and the value of the remainder at that time.

Low

× × ×

High

×

Binary 16 bits (2 bytes)

Figure 2-5. Binary-to-Decimal Conversion

Low

0

×

0

×

Decimal 5 digits (5 bytes)

0

×

0

×

0

High

×

Example

To convert FFH into decimal number

Low

F F 0

High

0

Binary 16 bits (2 bytes)

(1) Registers used

AX, BC, HL

Low

0 5 0 5

Decimal 5 digits (5 bytes)

0 2 0 0 0

High

0

68

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(2) Program list

PUBLIC B_DCONV

DATDEC EQU 10

DSEG

REGA: DS

REGB: DS

SADDRP

2

5

COLNUM EQU 4

B_DCONV:

MOVW

MOV

MOVW

B_D1:

AX,REGA

B,#COLNUM

HL,#REGB

MOV C,#DATDEC

DIVUW C

XCH A,C

MOV

INCW

XCH

DBNZ

MOV

MOV

RET

[HL],A

HL

A,C

B,$B_D1

A,X

[HL],A

; Stores binary 16-bit data

; Stores decimal 5-digit data

69

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.6 Bit Manipulation Instruction

A 1 bit of a flag in the data memory is ANDed with the bit 4 of port 6, and the result is ANDed with the bit 5 of port 6 and is output to the bit 6 of port 6.

Figure 2-6. Bit Operation

FLG

PORT6.4

PORT6.5

PORT6.6

(1) Program list

PUBLIC BIT_OP,FLG

FLG

BSEG

DBIT

BIT_OP:

MOV1 CY,FLG

AND1 CY,P6.4

OR1 CY,P6.5

MOV1 P6.6,CY

RET

70

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.7 Binary Multiplication (16 bits

×

16 bits)

Data in a multiplicand area (HIKAKE; 16 bits) and multiplier area (KAKE; 16 bits) are multiplied, and the result is stored in an operation result storage area (KOTAE).

Figure 2-7. Binary Multiplication

HIKAKE + 1 HIKAKE

Multiplicand area (2 bytes)

KAKE + 1

×

KAKE

Multiplier area (2 bytes)

Operation result storage area (4 bytes)

KOTAE + 3 KOTAE

<Processing contents>

Multiplication is performed by adding the multiplicand by the number of bits of the multiplier that are “1”.

71

72

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

<Contents used>

Set the data in the multiplicand (HIKAKE) and multiplier (KAKE) areas, and call subroutine S_KAKERU.

MAIN:

EXTRN S_KAKERU

EXTRN HIKAKE,KAKE,KOTAE

; Multiplier

·

·

HIKAKE=WORKA (A)

HIKAKE+1=WORKA+1 (A)

KAKE=WORKB (A)

KAKE+1=WORKB+1 (A)

CALL !S_KAKERU

HL=#KOTAE

·

·

·

;

;

; Stores multiplicand data to multiplicand area

; Stores multiplier data to multiplier area

; Calls multiplication routine

; HL

RAM address of operation result storage area

; Stores result by indirect address transfer

Caution Manipulate the data memory in 8-bit units.

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(1) Input/output condition

• Input parameter

HIKAKE : Store the multiplicand data in this area.

KAKE : Store the multiplier data in this area.

• Output parameter

KOTAE : Store the result of the operation in this area.

(2) SPD chart

[Multiplication subroutine]

S_KAKERU Initializes operation result storage area

WORK1

multiplier (low) for (B = #0 ; B < #16 ; B + +) if (B = #8)

THEN

WORK1

multiplier (high)

Shifts WORK1 1 bit to left if_bit (CY = #1)

THEN

Adds multiplicand to operation result storage area if (B

#15)

THEN

Shifts operation result storage area 1 bit to left

(3) Registers used

A, B

73

74

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(4) Program list

$PC(054)

;

PUBLIC HIKAKE,S_KAKERU,KAKE,KOTAE

;

;************************************************

; RAM definition

;************************************************

DSEG SADDR

HIKAKE:

KAKE:

WORK1:

DS

DS

DS

2

2

1

KOTAE:

;

DS 4

;************************************************

; Multiplicand area

; Multiplier area

; Work area

; Operation result storage area

; Multiplication

;************************************************

CSEG

;

S_KAKERU:

WORK1=KAKE+1 (A)

KOTAE=#0

KOTAE+1=#0

;

; Stores multiplier (low) in work area

;

; Initializes operation result storage area

KOTAE+2=#0

KOTAE+3=#0 for(B=#0;B<#16;B++)(A) if(B == #8)(A)

WORK1=KAKE (A) endif

A=WORK1

CLR1 CY

;

;

; Stores higher multiplier in work area

; if low multiplication is completed

;

;

;

; Shifts multiplier 1 bit to left next

RET

ROLC

WORK1=A endif

KOTAE+3+=KOTAE+3,CY (A) endif

A,1 if_bit(CY)

KOTAE+=HIKAKE (A)

(KOTAE+1)+=HIKAKE+1,CY (A)

(KOTAE+2)+=#0,CY (A)

(KOTAE+3)+=#0,CY (A) if(B != #15) (A)

KOTAE+=KOTAE (A)

KOTAE+1+=KOTAE+1,CY (A)

KOTAE+2+=KOTAE+2,CY (A)

;

;

;

;

;

;

;

; Adds multiplicand to operation result storage area if carry occurs

;

;

;

;

;

;

;

; Shifts operation result storage area 1 bit to left

END

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

2.8 Binary Division (32 bits

÷

16 bits)

Data in a dividend area (HIWARU; 32 bits) is divided by data in a divisor area (WARUM; 16 bits), and the result is stored in an operation result storage area (KOTAE). If a remainder is generated, it is stored in a calculation result reminder area (AMARI).

If division is executed with the divisor being 0, an error occurs.

Figure 2-8. Binary Division

Dividend storage area (4 bytes)

HIWARU + 3

÷

WARUM + 1 WARUM

Divisor area (2 bytes)

HIWARU

Operation result storage area (4 bytes)

KOTAE + 3 KOTAE

AMARI + 1 AMARI

Calculation result remainder area (2 bytes)

<Processing contents>

The dividend is shifted to the left to the work area starting from the highest digit. If the contents of the work area are greater than the divisor, the divisor is subtracted from the work area, and the least significant bit of the dividend is set to 1. In this way, division is carried out by executing the program by the number of bits of the dividend.

If the divisor is 0, an error flag (F_ERR) is set.

75

76

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

<Usage>

Set data in the dividend area (HIWARU) and divisor area (WARUM), and call subroutine S_WARU.

EXTRN S_WARU

EXTRN HIWARU,WARUM,KOTAE

EXBIT F_ERR

MAIN:

·

·

HIWARU=WORKA (A)

HIWARU+1=WORKA+1 (A)

WARUM=WORKB (A)

WARUM+1=WORKB+1 (A)

CALL !S_WARU

HL=#KOTAE if_bit(F_ERR)

Calculation error processing endif

·

·

·

·

·

;

;

;

; Stores dividend data to dividend area

;

;

;

;

; Stores divisor data to divisor area

;

;

; Calls division calculation routine

; HL

stores RAM address of operation result storage area

Caution Manipulate the data memory in 8-bit units.

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(1) Input/output conditions

• Input parameter

HIWARU: Store the dividend data in this area.

WARUM : Store the divisor data in this area.

• Output parameter

KOTAE : Store the result of the calculation in this area.

(2) SPD chart

[Division subroutine]

S_WARU Clears operation error flag

Initializes operation result storage area and calculation result remainder area if (divisor = #0)

THEN

Sets operation error flag if_bit (operation error flag = #0)

THEN for (B = #0 ; B < #32 ; B + +)

Shifts dividend and calculation result remainder I bit to left at same time if (calculation result remainder divisor)

THEN

Calculation result remainder

calculation result remainder - divisor

Dividend

dividend OR #1

Operation result storage area

dividend area

(3) Registers used

A, B

77

78

CHAPTER 2 FUNDAMENTALS OF SOFTWARE

(4) Program list

$PC(054)

;

PUBLIC S_WARU,HIWARU,WARUM,F_ERR

EXTRN KOTAE

;

;************************************************

; RAM definition

;************************************************

DSEG SADDR

HIWARU:

WARUM:

DS

DS

4

2

AMARI:

F_ERR

DS

BSEG

DBIT

2

;************************************************

; Dividend area

; Divisor area

; Calculation result remainder storage area

; Operation error flag

;

CSEG

Division

;************************************************

;

S_WARU:

CLR1 F_ERR

;

; Clears operation error flag

AMARI=#0

AMARI+1=#0

;

; Clears calculation result storage area to 0

KOTAE=#0

KOTAE+1=#0

;

; Clears operation result storage area to 0

KOTAE+2=#0

KOTAE+3=#0

;

; if(WARUM == #0) if(WARUM+1 == #0)

;

; Divisor = 0?

SET1 endif

F_ERR

;

; Sets operation error flag if divisor is 0 endif if_bit(!F_ERR)

;

; Operation error?

for(B=#0;B < #32;B++) (A)

HIWARU+=HIWARU (A)

; Starts 32-bit division

; Shifts dividend and remainder 1 bit to left

HIWARU+1+=HIWARU+1,CY

HIWARU+2+=HIWARU+2,CY

(A)

(A)

;

;

HIWARU+3+=HIWARU+3,CY

AMARI+=AMARI,CY (A)

(A)

;

;

AMARI+1+=AMARI+1,CY (A) if(AMARI+1 > WARUM+1) (A)

AMARI–=WARUM (A)

;

;

;

; Remainder

divisor?

Remainder = remainder – divisor

AMARI+1–=WARUM+1,CY (A)

HIWARU |= #1

;

; Stores 1 to first bit of dividend area elseif_bit(Z) if(AMARI >= WARUM) (A)

;

;

AMARI–=WARUM(A)

AMARI+1–=WARUM+1,CY (A)

;

;

HIWARU |= #1 endif

;

; next endif

;

;

KOTAE=HIWARU (A)

KOTAE+1=HIWARU+1 (A)

;

; Stores operation result

KOTAE+2=HIWARU+2 (A)

KOTAE+3=HIWARU+3 (A)

;

; endif

RET

;

;

END

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

The 78K/0 series allows you to select a CPU clock and controls the operation of the oscillator by rewriting the contents of the processor clock control register (PCC), oscillation mode select register (OSMS), and clock select registers 1 and 2 (IECL1 and IECL2).

When the CPU clock is changed, the time shown in Table 3-1 is required since the contents of the PCC have been rewritten until the CPU clock is actually changed. It is therefore not apparent for a while after the contents of the

PCC have been rewritten, whether the processor operates on the new or old clock. To stop the main system clock or execute the STOP instruction, therefore, the wait time shown in Table 3-1 is necessary.

Caution IECL1 and IECL2 are provided to the

µ

PD78098, 78098B subseries only.

79

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Table 3-1. Maximum Time Required for Changing CPU Clock

Set Value before Change Set Value after Change

MCS CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1

× × ×

×

0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction

×

0 0 0 1 16 instructions

×

0 0 1 0 16 instructions 8 instructions

4 instructions 2 instructions 1 instruction 1 instruction

2 instructions 1 instruction 1 instruction

×

0 0 1 1 16 instructions 8 instructions 4 instructions

×

0 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions

1 instruction 1 instruction

1 instruction

1 1

× × × f

X

/2f

XT

instructions f

X

/4f

XT

instructions f

X

/8f

XT

instructions f

X

/16f

XT

instructions f

X

/32f

XT

instructions

(77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions)

0 1

× × × f

X

/4

XT

instructions f

X

/8f

XT

instructions f

X

/16f

XT

instructions f

X

/32f

XT

instructions f

X

/64f

XT

instructions

(39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions)

Caution Do not select dividing the CPU clock (PCC0-PCC2) and changing from the main system clock to subsystem clock (by setting CSS to 0

1) at the same time.

However, dividing the CPU clock (PCC0-PCC2) can be selected at the same time as changing from the subsystem clock to the main system clock.

Remarks 1. One instruction is the minimum instruction execution time of the CPU clock before change.

2. ( ): f

X

= 5.0 MHz, f

XT

= 32.768 kHz

80

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Figure 3-1. Format of Processor Clock Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY)

Symbol

PCC

7

MCC

6

FRC

5

CLS

4

CSS

3

0

2 1 0

PCC2 PCC1 PCC0

Address

FFFBH

At reset

04H

R/W

R/W

Note1

R/W CSS

0

1

Others

PCC2 PCC1 PCC0

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

1

1

0

1

0

0

0

1

0

0

1

0

1 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XT

/2

Setting prohibited f

X f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4

Selects CPU clock (f

CPU

)

MCS = 1 f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5

MCS = 0

R CLS

0

1

Main system clock

Subsystem clock

Status of CPU clock

R/W FRC

0

1

Selects feedback resistor of subsystem clock

Uses internal feedback resistor

Does not use internal feedback resistor

R/W MCC

0

1

Enables oscillation

Stops oscillation

Controls oscillation of main system clock

Note 2

Notes 1. Bit 5 is a read-only bit.

2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction.

Caution Be sure to clear bit 3 to 0.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4. MCS: bit 0 of oscillation mode select register (OSMS)

81

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Symbol

PCC

7

0

Figure 3-2. Format of Processor Clock Control Register (

µ

PD78083 subseries)

6

0

5

0

4

0

3

0

2 1 0

PCC2 PCC1 PCC0

Address

FFFBH

At reset

04H

R/W

R/W

PCC2 PCC1 PCC0

0

0

0

0

1

Others

1

1

0

0

0

0

1

0

1

0 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4

Setting prohibited

Caution Be sure to clear bits 3 through 7 to 0.

f

X f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4

Selects CPU clock (f

CPU

)

MCS = 1 f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5

MCS = 0

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. MCS: bit 0 of oscillation mode select register (OSMS)

82

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Figure 3-3. Format of Processor Clock Control Register (

µ

PD78098, 78098B subseries)

Symbol

PCC

7

MCC

6

FRC

5

CLS

4

CSS

3

0

2 1 0

PCC2 PCC1 PCC0

Address

FFFBH

At reset

04H

R/W

R/W

Note 1

R/W CSS PCC2 PCC1 PCC0

0 0 0 0

0

0

0

1

1

0

1

0

1

0

0

1

0

0

0

1

0

0

1 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XT

/2

0

0

1

1

1

0

0

1

0

Others Setting prohibited

Selects CPU clock (f

Status of CPU clock

CPU

)

R CLS

0

1

Main system clock

Subsystem clock

R/W FRC

0

1

Selects feedback resistor of subsystem clock

Uses internal feedback resistor

Does not use internal feedback resistor

R/W MCC

0

1

Enables oscillation

Stops oscillation

Controls oscillation of main system clock

Note 2

Notes 1. Bit 5 is a read-only bit.

2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction.

Caution Be sure to clear bit 3 to 0.

Remarks 1. f

XX

: main system clock frequency

2. f

XT

: subsystem clock oscillation frequency

83

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Figure 3-4. Format of Processor Clock Control Register (

µ

PD780018, 780018Y subseries)

Symbol

PCC

7

MCC

6

FRC

5

CLS

4

CSS

3

0

2 1 0

PCC2 PCC1 PCC0

Address

FFFBH

At reset

04H

R/W

R/W

Note 1

R/W CSS PCC2 PCC1 PCC0

0 0 0 0

0

0

0

1

1

0

1

0

1

0

0

1

0

0

0

1

0

0

1 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XT

/2

0

0

1

1

1

0

0

1

0

Others Setting prohibited

Selects CPU clock (f

Status of CPU clock f

X f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4

CPU

)

R CLS

0

1

Main system clock

Subsystem clock

R/W FRC

0

1

Selects feedback resistor of subsystem clock

Uses internal feedback resistor

Does not use internal feedback resistor

R/W MCC

0

1

Enables oscillation

Stops oscillation

Controls oscillation of main system clock

Note 2

Notes 1. Bit 5 is a read-only bit.

2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction.

Caution Be sure to clear bit 3 to 0.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

84

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Symbol

OSMS

7

0

Figure 3-5. Format of Oscillation Mode Select Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY)

6

0

5

0

4

0

3

0

2

0

1

0

0

MCS

Address

FFF2H

At reset

00H

R/W

W

MCS Controls divider circuit of main system clock

0 Uses divider circuit

1 Does not use divider circuit

Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/f

X

only during the execution of the write instruction.

Consequently, a temporary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs.

When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well as the clock supplied to the CPU, is changed.

It is therefore recommended that you execute the instruction to write the OSMS only once after the reset signal has been deasserted, and before the peripheral hardware operates.

2. Set 1 to MCS after V

DD

has risen to 2.7 V or more.

Symbol

OSMS

7

0

Figure 3-6. Format of Oscillation Mode Select Register (

µ

PD78098, 78098B subseries)

6

0

5

0

4

0

3

0

2

0

1

0

0

MCS

Address

FFF2H

At reset

00H

R/W

W

MCS

0

1

Controls divider circuit of main system clock (divider circuit 1)

Uses 1/2 divider circuit in divider circuit 1

Does not use 1/2 divider circuit in divider circuit 1

Caution When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/f

X

only during the execution of the write instruction.

Consequently, `rary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs.

When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well as the clock supplied to the CPU, is changed.

It is therefore recommended that you execute the instruction to write the OSMS only once after the reset signal has been deasserted, and before the peripheral hardware operates.

85

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Symbol

OSMS

7

0

Figure 3-7. Format of Oscillation Mode Select Register (

µ

PD780018, 780018Y subseries)

6

0

5

0

4

0

3

0

2

0

1

0

0

MCS

Address

FFF2H

At reset

00H

R/W

W

MCS Controls divider circuit of main system clock

0 Setting prohibited

1 Does not use divider circuit

Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/f

X

only during the execution of the write instruction.

Consequently, a temporary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs.

2. Setting MCS to 0 is prohibited. On RESET input, however, OSMS is reset to 00H. Therefore, be sure to set MCS to 1 at the start of a program or after clearing reset.

Figure 3-8. Format of Clock Select Register 1 (

µ

PD78098, 78098B subseries)

Symbol

IECL1

7

0

6

0

5

0

4

0

3

0

2

0

1 0

IECL11 IECL10

Address

F8E0H

At reset

00H

R/W

R/W

IECL10

Controls divider circuit of main system clock (divider circuit 1)

0

1

Uses 2/3 divider circuit in divider circuit 1

Does not use 2/3 divider circuit in divider circuit 1

IECL11

0

Controls divider circuit of main system clock (divider circuit 2)

Uses 1/2 divider circuit in divider circuit 2

1 Does not use1/2 divider circuit in divider circuit 2

Caution Be sure to clear bits 2 through 7 to 0.

Figure 3-9. Format of Clock Select Register 2 (

µ

PD78098, 78098B subseries)

Symbol

IECL2

7

0

6

0

5

0

4

0

3

0

2

0

1

0

0

IECL20

Address

F8E1H

At reset

00H

R/W

R/W

IECL20

Controls divider circuit of main system clock (divider circuit 1)

0

1

Uses 1/3 divider circuit in divider circuit 1

Does not use 1/3 divider circuit in divider circuit 1

Caution Be sure to clear bits 1 through 7 to 0.

86

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

The fastest instruction is executed in two CPU clocks. Therefore, the relation between the CPU clock (f

CPU

) and minimum instruction execution time is as shown in Tables 3-2 and 3-3.

Table 3-2. Relation between CPU Clock and Minimum Instruction Execution Time

(other than

µ

PD78098 and 78098B subseries)

f

X f

X

/2 f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5Note 1 f

XT

Note 2

CPU Clock (f

CPU

) Minimum Instruction Execution Time: 2/f

CPU

0.4

µ s

0.8

µ s

1.6

µ s

3.2

µ s

6.4

µ s

12.8

µ s

122

µ s

Notes 1. Except

µ

PD780018 and 780018Y subseries

2. Except

µ

PD78083 subseries

Remark f

X

= 5.0 MHz, f

XT

= 32.768 kHz f

X

: Main system clock oscillation frequency f

XT

: Subsystem clock oscillation frequency

87

Table 3-3. CPU Clock (f

CPU

) List (

µ

PD78098 and 78098B Subseries)

CSS PCC2 PCC1 PCC0

Selects CPU clock (f

CPU

)

MCS 0

IECL20 0

IECL10 0

0 0 0 0 f

XX

0 0 1 f

XX

/2 f

X

/2

(0.67

µ s) f

X

/2

2

(1.33

µ s)

0 1 0 f

XX

/2

2

0 1 1 f

XX

/2

3 f

X

/2

3

(2.67

µ s) f

X

/2

4

(5.33

µ s)

1 0 0 f

XX

/2

4 f

X

/2

5

(10.7

µ s)

1

Others

0

0

0

0

1

0

0

1

1

0

0

1

0 f

XT

/2(122

µ s)

1

0

Setting prohibited

0

0

1

(2f

X

/3)/2

(1.00

µ s)

(2f

X

/3)/2

2

(2.00

µ s)

(2f

X

/3)/2

3

(4.00

µ s)

(2f

X

/3)/2

4

(8.00

µ s)

(2f

X

/3)/2

5

(16.0

µ s)

0

1

0

(f

X

/3)/2

(2.00

µ s)

(f

X

/3)/2

2

(4.00

µ s)

(f

X

/3)/2

3

(8.00

µ s)

(f

X

/3)/2

4

(16.0

µ s)

(f

X

/3)/2

5

(32.0

µ s)

0

1

1

(2f

X

/9)/2

(3.00

µ s)

(2f

X

/9)/2

2

(6.00

µ s)

(2f

X

/9)/2

3

(12.0

µ s)

(2f

X

/9)/2

4

(24.0

µ s)

(2f

X

/9)/2

5

(48.0

µ s)

1

0

0 f

X

(Setting prohibited) f

X

/2

(0.67

µ s) f

X

/2

2

(1.33

µ s) f

X

/2

3

(2.67

µ s) f

X

/2

4

(5.33

µ s)

1

0

1

2f

X

/3

(0.50

µ s)

(2f

X

/3)/2

(1.00

µ s)

(2f

X

/3)/2

2

(2.00

µ s)

(2f

X

/3)/2

3

(4.00

µ s)

(2f

X

/3)/2

4

(8.00

µ s)

Remarks 1. f

X

: Main system clock oscillation frequency

2. f

XX

: Main system clock frequency

3. f

XT

: Subsystem clock oscillation frequency

4. ( ) : Minimum instruction execution time with f

X

= 6.0 MHz or f

XT

= 32.768 kHz: 2/f

CPU

1

1

0 f

X

/3

(1.00

µ s)

(f

X

/3)/2

(2.00

µ s)

(f

X

/3)/2

2

(4.00

µ s)

(f

X

/3)/2

3

(8.00

µ s)

(f

X

/3)/2

4

(16.0

µ s)

1

1

1

2f

X

/9

(1.50

µ s)

(2f

X

/9)/2

(3.00

µ s)

(2f

X

/9)/2

2

(6.00

µ s)

(2f

X

/9)/2

3

(12.0

µ s)

(2f

X

/9)/2

4

(24.0

µ s)

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

3.1 Changing PCC Immediately after RESET

When the RESET signal is asserted, the slowest mode (processor clock control register: PCC = 04H, oscillation mode select register: OSMS = 00H) of the main system clock is selected for the CPU clock. To set the highest speed of the CPU clock, therefore, the contents of the PCC must be rewritten (PCC = 00H, OSMS = 01H). To use the fasted mode, however, the voltage on the V

DD

pin has to have risen to a sufficient level and be stable.

In the following example, the CPU waits until the V

DD

pin voltage has risen to the sufficient level by using the watch timer (the interval time is set to 3.91 ms). After that, the CPU operates on the fastest clock.

Figure 3-10. Example of Selecting CPU Clock after RESET (with

µ

PD78054 subseries)

ON

Commercial power source

V

DD

pin voltage

OFF

4.5 V

2.0 V

H

RESET signal

L

CPU clock wait time

Wait status

31.3 ms

(2

17

/f

X

: at 4.19 MHz)

3.9 ms

RESET signal is deasserted

10 s after V

DD

pin voltage has risen to 2.0 V or more.

CPU clock oscillation starts.

V

DD

pin voltage has risen to 4.5 V or more before contents of PCC are changed.

89

90

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

(1) SPD chart

Sets watch timer to 3.91 ms

WHILE: No watch timer interrupt request ( ! TMIF3)

Clears TMIF3

Sets PCC in fastest mode

(2) Program list

;**************************************

;* Sets wait time

;**************************************

TCL2=#00010000B

TMC2=#00110110B while_bit(!TMIF3)

; Sets watch timer to 3.91 ms

; 3.91 ms?

endw

CLR1 WTIF

OSMS=#00000001B

PCC=#00000000B

; Does not use divider circuit

; Sets CPU clock in fastest mode

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

3.2 Selecting Power ON/OFF

The 78K/0 series can operate in an ultra low current consumption mode by using the processor clock control register

(PCC) and selecting the subsystem clock. By providing a backup power supply such as a Ni-Cd battery or super capacitor to the system, therefore, the system can continue operating even if a power failure occurs.

In this example, a power failure is detected by using INTP1 (both the rising and falling edges are selected as the edge to be detected), and the contents of the PCC are changed depending on the port level at that time. Figure 3-

11 shows a circuit example, and Figure 3-12 shows the system clock changing timing.

Figure 3-11. Example of System Clock Changing Circuit

+ 5.6V

V

DD

V

SS

+

INTP1/TI01/P01

91

92

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

Figure 3-12. Example of Changing System Clock on Power Failure (

µ

PD78054 subseries)

V

DD

pin voltage

6.0 (V)

4.5 (V)

2.0 (V)

ON

Commercial power source

OFF

H

P01/INTP1 pin

System clock

L

Interrupt request occurs

Main system clock Subsystem clock

Interrupt request occurs

Main system clock

Waits until V

DD

rises to 4.5 V or more

CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION

(1) SPD chart

INTP1

THEN

IF: power off (P01 = low level)

Sets CPU clock in slowest mode

User processing

ELSE

Sets CPU clock in fastest mode

User processing

(2) Program list

VEP0 CSEG

DW

AT 08H

INTP1 ; Sets vector address of INTP1

; Both edge detection mode

MOV

CLR1

EI

INTM0,#00110000B

PMK1

;*****************************************

;* Sets low-/high-speed mode

;*****************************************

INTP1:

;

; if_bit(!P0.1)

Setting of internal hardware (low speed)

User processing

;

;

PCC=#10010000B

; Sets low-speed mode else

Sets internal hardware (high speed)

User processing

PCC=#00000000B

; Sets high-speed mode endif

RETI

93

[MEMO]

94

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

The watchdog timer of the 78K/0 series has two modes: watchdog timer mode in which a hang-up of the microcontroller is detected, and interval timer mode.

The watchdog timer is set by using timer clock select register 2 (TCL2) and watchdog timer mode register (WDTM).

95

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

Figure 4-1. Format of Timer Clock Select Register 2

(

µ

PD78054 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

3

0

2 1 0

TCL22 TCL21 TCL20

TCL22 TCL21 TCL20

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2 f

XX

/2 f

XX

/2 f

XX

/2 f

XX

/2 f

XX

/2 f

XX

/2

3

4

5

6

7

8

9

11

Address

FF42H

At reset

00H

R/W

R/W

Selects count clock of watchdog timer

MCS = 1 f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

12

(1.2 kHz)

TCL24 Selects count clock of watch timer

MCS = 1 f

X

/2

7

(39.1 kHz)

MCS = 0 f

X

/2

8

(19.5 kHz) 0

1 f

XX

/2

7 f

XT

(32.768 kHz)

TCL27 TCL26 TCL25

1

1

0

1

1

×

0

0

1

1

×

0

1

0

1

Selects frequency of buzzer output

MCS = 1

Disables buzzer output f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Setting prohibited f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz) f

X

/2

12

(1.2 kHz)

Caution To change the data of TCL2 except when writing the same data, once stop the timer operation.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4.

×

: don’t care

5. MCS: bit 0 of oscillation mode select register (OSMS)

6. ( ) : f

X

= 5.0 MHz or f

XT

= 32.768 kHz

96

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

Figure 4-2. Format of Timer Clock Select Register 2 (

µ

PD78083 subseries)

Symbol 7 6 5

TCL2 TCL27 TCL26 TCL25

4

0

3 2 1 0

0 TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

R/W

R/W

TCL22 TCL21 TCL20

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

0

0

1

0

1

0

1

0

1 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Selects count clock of watchdog timer

MCS = 1 f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

12

(1.2 kHz)

TCL27 TCL26 TCL25

1

1

0

1

1

×

0

0

1

1

×

0

1

0

1

Selects frequency of buzzer output

MCS = 1

Disables buzzer output f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Setting prohibited f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz) f

X

/2

12

(1.2 kHz)

Cautions 1. To change the data of TCL2 except when writing the same data, once stop the timer operation.

2. Be sure to clear bits 3 and 4 to 0.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3.

×

: don’t care

4. MCS: bit 0 of oscillation mode select register (OSMS)

5. ( ) : f

X

= 5.0 MHz

97

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

Figure 4-3. Format of Timer Clock Select Register 2 (

µ

PD78098, 78098B subseries)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

3 2 1 0

0 TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

R/W

R/W

TCL22 TCL21 TCL20

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1 f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz) f

XX

/2

9

(7.8 kHz) f

XX

/2

11

(2.0 kHz)

Selects count clock of watchdog timer

TCL24

0

1 f

XX

/2

7

(31.3 kHz) f

XT

(32.768 kHz)

Selects count clock of watch timer

TCL27 TCL26 TCL25

0

× ×

1 0 0

Disables buzzer output f

XX

/2

9

(7.8 kHz)

1

1

0

1

1

0 f

XX

/2

10

(3.9 kHz) f

XX

/2

11

(1.95 kHz)

1 1 1 Setting prohibited

Selects frequency of buzzer output

Caution To change the data of TCL2 except when writing the same data, once stop the timer operation.

Remarks 1. f

XX

: main system clock frequency

2. f

XT

: subsystem clock oscillation frequency

3.

×

: don’t care

4. ( ) : f

XX

= 4.0 MHz or f

XT

= 32.768 kHz

98

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

Figure 4-4. Format of Timer Clock Select Register 2 (

µ

PD780018, 780018Y subseries)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

3 2 1 0

0 TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

R/W

R/W

TCL22 TCL21 TCL20

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Selects count clock of watchdog timer f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

TCL24

0

1 f

XX

/2

7 f

XT

(32.768 kHz)

Selects count clock of watch timer f

X

/2

7

(39.1 kHz)

TCL27 TCL26 TCL25

0

× ×

1 0 0

Disables buzzer output f

XX

/2

9

1

1

0

1

1

0 f

XX

/2

10 f

XX

/2

11

1 1 1 Setting prohibited

Selects frequency of buzzer output f f f

X

X

X

/2

/2

/2

9

10

(9.8 kHz)

11

(4.9 kHz)

(2.4 kHz)

Caution To change the data of TCL2 except when writing the same data, once stop the timer operation.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4.

×

: don’t care

5. ( ): f

X

= 5.0 MHz or f

XT

= 32.768 kHz

99

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

Figure 4-5. Format of Watchdog Timer Mode Register

Symbol

WDTM

7

RUN

6

0

5

0

4 3

WDTM4 WDTM3

2

0

1

0

0

0

Address

FFF9H

At reset

00H

R/W

R/W

WDTM4 WDTM3

0

×

1

1

0

1

Selects operation mode of watchdog time

Note 1

Interval timer mode

Note 2

(maskable interrupt request occurs when overflow occurs)

Watchdog timer mode (non-maskable interrupt request occurs when overflow occurs)

Watchdog timer mode 2 (reset operation starts when overflow occurs)

RUN Selects watchdog timer operation

Note 3

0 Stops counting

1 Clears counter and starts counting

Notes 1. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.

2. When RUN is set to 1, the WDTM starts interval timer operation.

3. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting has been started, it cannot be stopped by any means other than the RESET signal.

Caution 1. When RUN is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the timer clock select register 2.

2. When using the watchdog timer modes 1 and 2, confirm that the interrupt request flag (TMIF4) is 0 and then set WDTM4 to 1. If WDTM4 is set to 1 while TMIF4 is 1, the non-maskable interrupt occurs regardless of the contents of WDTM3.

100

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

4.1 Setting Watchdog Timer Mode

Reset processing or non-maskable interrupt processing is performed after the watchdog timer has detected a hangup. You can select which processing is to be performed by the watchdog timer mode register (WDTM). When the watchdog timer mode is used, the timer must be cleared at intervals shorter than the set hang-up detection time. If the timer is not cleared, an overflow occurs, and reset or interrupt processing is executed.

The hang-up detection time of the watchdog timer is set by the timer clock select register 2 (TCL2).

In the following example, the hang-up detection time is set to 7.81 ms and the reset processing is performed when an overflow occurs.

(1) SPD chart

Sets hang-up detection time of watchdog timer to 7.81 ms

Sets watchdog timer in reset start mode

User processing 1

Clears watchdog timer

User processing 2

Clears watchdog timer

User processing 3

Clears watchdog timer

101

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

(2) Program list

;*************************************

;* Sets watchdog timer

;*************************************

OSMS=#00000001B

TCL2=#00000100B

WDTM=#10011000B

; Does not use divider circuit

; Sets watchdog timer to 7.81 ms

; Sets reset start mode

;

User processing 1

SET1 RUN

; Clears timer

;

User processing 2

SET1 RUN

; Clears timer

;

User processing 3

SET1 RUN

; Clears timer

102

CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER

4.2 Setting Interval Timer Mode

When the interval timer mode is used, the interval time is set by the timer clock select register 2 (TCL2) (interval time = 0.488 ms to 125 ms, at f

X

= 4.19 MHz). In this mode, an interrupt request flag (TMIF4) is set when an overflow occurs in the timer.

In the following example, three types of times, 0.977 ms, 7.82 ms, and 125 ms, are set.

Figure 4-6. Count Timing of Watchdog Timer

Timer count

INTWDT

FC FD FE FF 00 01 02 03 FD FE FF 00

(1) Program list

<1> To set 0.977 ms

TCL2=#00000001B

WDTM=#10001000B

; Sets 0.977 ms

; Selects interval timer mode

<2> To set 7.82 ms

TCL2=#00000100B

WDTM=#10001000B

; Sets 7.82 ms

; Selects interval timer mode

<3> To set 125 ms

TCL2=#00000111B

WDTM=#10001000B

; Sets 125 ms

; Selects interval timer mode

Remark

The above interval time is the value when OSMS = 01H.

103

[MEMO]

104

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

The 16-bit timer/event counter of the 78K/0 series has the following six functions:

• Interval timer

• PWM output

• Pulse width measurement

• External event counter

• Square wave output

• One-shot pulse output

The 16-bit timer/event counter is set by the following registers:

• Timer clock select register 0 (TCL0)

• 16-bit timer mode control register (TMC0)

• Capture/compare control register 0 (CRC0)

• 16-bit timer output control register (TOC0)

• Port mode register 3 (PM3)

• External interrupt mode register (INTM0)

• Sampling clock select register (SCS)

105

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-1. Format of Timer Clock Select Register 0

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY)

Symbol

TCL0

7 6 5 4 3 2 1 0

CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00

Address

FF40H

At reset

00H

R/W

R/W

TCL03 TCL02 TCL01 TCL00

1

1

1

1

0

0

0

0

1

Others

0

1

1

1

0

0

0

0

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Selects clock of PCL output

MCS = 1 f f

XT

(32.768 kHz)

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7

Setting prohibited f

X

(5.0 MHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz)

MCS = 0 f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz)

TCL06 TCL05 TCL04

0

0

0

0

1

1

Others

0

0

1

1

0

1

0

1

0

1

0

1 f

Selects count clock of 16-bit timer register

MCS = 1

TI00 (valid edge can be specified)

2f

XX

Setting prohibited

XX f

XX

/2 f

XX

/2

2 f

X

(5.0 MHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz)

MCS = 0 f

X

(5.0 MHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz)

Watch timer output (INTTM3)

Setting prohibited

CLOE

0

1

Disables output

Enables output

Controls PCL output

Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0

(INTM0). The frequency of the sampling clock is selected by the sampling clock select register

(SCS).

2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction.

3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0.

4. Before writing new data to TCL0, stop the timer operation once.

106

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4. TI00 : input pin of 16-bit timer/event counter

5. TM0 : 16-bit timer register

6. MCS: bit 0 of oscillation mode select register (OSMS)

7. ( ) : at f

X

= 5.0 MHz or f

XT

= 32.768 kHz

107

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-2. Format of Timer Clock Select Register 0 (

µ

PD78098, 78098B subseries)

Symbol 7 6 5 4 3 2 1 0

TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00

Address

FF40H

At reset

00H

R/W

R/W

TCL03 TCL02 TCL01 TCL00

0 0 0 0 f

XT

(32.768 kHz)

0

0

0

1

1

1

1

1

Others

1

1

1

0

0

0

0

1

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0 f

XX

(4.0 MHz) f

XX

/2 (2.0 MHz) f

XX

/2

2

(1.0 MHz) f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz)

Setting prohibited

Selects clock of PCL output

TCL06 TCL05 TCL04

0 0 0

0 0 1

Selects count clock of 16-bit timer register

TI00 (valid edge can be specified)

2f

XX

Note

0

0

1

1

Others

1

1

0

1

0

1

0

1 f

XX

(4.0 MHz) f

XX

/2 (2.0 MHz) f

XX

/2

2

(1.0 MHz)

Watch timer output (INTTM3)

Setting prohibited

CLOE

0

1

Disables output

Enables output

Note At f

XX

> 2.5 MHz, setting prohibited.

Controls PCL output

Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0

(INTM0). The frequency of the sampling clock is selected by the sampling clock select register

(SCS).

2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction.

3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0.

4. Before writing new data to TCL0, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency

2. f

XT

: subsystem clock oscillation frequency

3. TI00 : input pin of 16-bit timer/event counter

4. TM0 : 16-bit timer register

5. ( ) : at f

XX

= 4.0 MHz or f

XT

= 32.768 kHz

108

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-3. Format of Timer Clock Select Register 0 (

µ

PD780018, 780018Y subseries)

Symbol 7 6 5 4 3 2 1 0

TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00

Address

FF40H

At reset

00H

R/W

R/W

TCL03 TCL02 TCL01 TCL00

0 0 0 0 f

XT

(32.768 kHz)

0

0

0

1

1

1

1

1

Others

1

1

1

0

0

0

0

1

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7

Setting prohibited

Selects clock of PCL output f

X

(5.0 MHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz)

TCL06 TCL05 TCL04

0 0 0

Selects count clock of 16-bit timer register

TI00 (valid edge can be specified)

0

0

1

1

Others

1

1

0

1

0

1

0

1 f

XX f

XX

/2 f

XX

/2

2

Watch timer output (INTTM3)

Setting prohibited f

X

(5.0 MHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz)

CLOE

0

1

Disables output

Enables output

Controls PCL output

Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0

(INTM0). The frequency of the sampling clock is selected by the sampling clock select register

(SCS).

2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction.

3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0.

4. Before writing new data to TCL0, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4. TI00 : input pin of 16-bit timer/event counter

5. TM0 : 16-bit timer register

6. ( ) : at f

X

= 5.0 MHz or f

XT

= 32.768 kHz

109

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Symbol

TMC0

7

0

6

0

5

0

Figure 5-4. Format of 16-Bit Timer Mode Control Register

4

0 TMC03 TMC02 TMC01

OVF0

0

1

Overflow does not occur

Overflow occurs

3 2 1 0

OVF0

Address

FF48H

Detects overflow of 16-bit timer register

At reset

00H

R/W

R/W

TMC03 TMC02 TMC01

0 0 0

Selects operation mode and clear mode

Stops operation (clears TM0 to 0)

0

0

0

1

1

0

PWM mode (free running)

Free running mode

0

1

1

1

1

1

0

0

1

1

1

0

1

0

1

Clears and starts at valid edge of TI00

Clears and start at coincidence between TM0 and

CR00

Selects output timing of TO0

Not affected

Occurrence of interrupt request

Does not occur

PWM pulse output

Coincidence between TM0 and CR00 or between TM0 and CR01

Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of

TI00

Coincidence between TM0 and CR00 or between TM0 and CR01

Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of

TI00

Coincidence between TM0 and CR00 or between TM0 and CR01

Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of

TI00

Occurs if TM0 and CR00 coincide and if TM0 and

CR01 coincide

Cautions 1. Before setting the clear mode or changing the output timing of TO0, stop the timer operation

(by clearing TMC01 through TMC03 to 0, 0, 0).

2. The valid edge of the TI00/INTP0 pin is selected by the external interrupt mode register 0

(INTM0). The frequency of the sampling clock is selected by the sampling clock select register

(SCS).

3. When using the PWM mode, set data to CR00 after setting the PWM mode.

4. When a mode in which the timer is cleared and started on coincidence between TM0 and CR00, the OVF0 flag is set to 1 when the set value of CR00 is FFFFH and the value of TM0 changes from FFFFH to 0000H.

5. The 16-bit timer register starts operating as soon as a value other than 0, 0, 0 (operation stop mode) is set to TMC01 through TMC03. To stop the operation, clear TMC01 through TMC03 to 0, 0, 0.

110

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Remarks 1. TO0 : output pin of 16-bit timer/event counter

2. TI00 : input pin of 16-bit timer/event counter

3. TM0 : 16-bit timer register

4. CR00 : compare register 00

5. CR01 : compare register 01

Figure 5-5. Format of Capture/Compare Control Register

Symbol

CRC0

7

0

6

0

5

0

4

0

3 2 1 0

0 CRC02 CRC01 CRC00

Address

FF4CH

At reset

04H

R/W

R/W

CRC00 Selects operation mode of CR00

0 Operates as compare register

1 Operates as capture register

CRC01 Selects capture trigger of CR00

0 Captures at valid edge of TI01

1 Captures at valid edge of TI00

CRC02 Selects operation mode of CR01

0 Operates as compare register

1 Operates as capture register

Cautions 1. Be sure to stop the timer operation before setting CRC0.

2. When a mode in which the timer is cleared and started on coincidence between TM0 and CR00 is selected by the 16-bit timer mode control register, do not specify CR00 as the capture register.

111

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-6. Format of 16-Bit Timer Output Control Register

Symbol

TOC0

7

0

6 5 4 3 2 1 0

OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0

Address

FF4EH

At reset

00H

R/W

R/W

TOE0 Controls output of 16-bit timer/event counter

0 Disables output (port mode)

1 Enables output

TOC01 PWM mode

Selects active level

0

1

Active high

Active low

Other than PWM mode

Controls timer output F/F on coincidence between

CR00 and TM0

Disables reverse operation

Enables reverse operation

LVS0 LVR0

0

0

0

0

0

1

0

1

Sets status of timer output F/F of 16-bit timer/ event counter

Not affected

Resets timer output F/F (to 0)

Sets timer output F/F (to 1)

Setting prohibited

TOC04 Controls timer output F/F on coincidence between

CR01 and TM0

0

0

Disables reverse operation

Enables reverse operation

OSPE Controls one-shot pulse output operation

0 Successive pulse output

1 One-shot pulse output

OSPT Controls output trigger of one-shot pulse by software

0

1

No one-shot pulse trigger

One-shot pulse trigger

Cautions 1. Be sure to stop the timer operation before setting TOC0 (except OSPT).

2. LVS0 and LVR0 are always 0 when they are read immediately after data has been set.

3. OSPT is automatically cleared after data has been set. It is therefore always 0 when read.

112

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-7. Format of Port Mode Register 3

Symbol

PM3

7 6 5 4 3 2 1 0

PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30

Address

FF23H

At reset

FFH

R/W

R/W

PM3n Selects input/output mode of P3n pin (n = 0-7)

0 Output mode (output buffer ON)

1 Input mode (output buffer OFF)

Figure 5-8. Format of External Interrupt Mode Register 0

Symbol

INTM0

7

ES31

6

ES30

5

ES21

4

ES20

3 2

ES11 ES10

1

0

0

0

Address

FFECH

At reset

00H

R/W

R/W

ES11

0

0

1

1

ES10

0

1

0

1

Selects valid edge of INTP0

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES21

0

0

1

1

ES20

0

1

0

1

Selects valid edge of INTP1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES31

0

0

1

1

ES30

0

1

0

1

Selects valid edge of INTP2

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Caution Before setting the valid edge of the INTP0/TI00/P00 pin, clear bits 1 through 3 (TMC01 through

TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, and stop the timer.

113

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Symbol

SCS

7

0

Figure 5-9. Format of Sampling Clock Select Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY)

6

0

5

0

4

0

3

0

2

0

1 0

SCS1 SCS0

Address

FF47H

At reset

00H

R/W

R/W

SCS1 SCS0

1

1

0

0

0

1

0

1

Selects sampling clock of INTP0

MCS = 1 MCS = 0 f

XX

/2

N f

XX

/2

7 f

XX

/2

5 f

XX

/2

6 f f

X

/2 f

X

/2

X

/2

7

5

6

(39.1 kHz)

(156.3 kHz) f

X

/2

(78.1 kHz) f

X

/2 f

X

/2

8

6

7

(19.5 kHz)

(78.1 kHz)

(39.1 kHz)

Caution f

XX

/2

N

is the clock supplied to the CPU, and f

XX

/2

5

, f

XX

/2

6

, and f

XX

/2

7

are the clocks supplied to the peripheral hardware. f

XX

/2

N

is stopped in the HALT mode.

Remarks 1. N : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC)

2. f

XX

: main system clock frequency (f

X

or f

X

/2)

3. f

X

: main system clock oscillation frequency

4. MCS: bit 0 of oscillation mode select register (OSMS)

5. ( ) : at f

X

= 5.0 MHz

114

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Symbol

SCS

7

0

Figure 5-10. Format of Sampling Clock Select Register (

µ

PD78098, 78098B subseries)

6

0

5

0

4

0

3

0

2

0

1

SCS1

0

SCS0

Address

FF47H

At reset

00H

R/W

R/W

SCS1

0

0

1

1

SCS0

0

1

0

1

Selects sampling clock of INTP0 f

XX

/2

N f

XX

/2

7

(31.3 kHz) f

XX

/2

5

(125.0 kHz) f

XX

/2

6

(62.5 kHz)

Caution f

XX

/2

N

is the clock supplied to the CPU, and f

XX

/2

5

, f

XX

/2

6

, and f

XX

/2

7

are the clocks supplied to the peripheral hardware. f

XX

/2

N

is stopped in the HALT mode.

Remarks 1. N : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC)

2. f

XX

: main system clock frequency

3. ( ) : at f

XX

= 4.0 MHz

Figure 5-11. Format of Sampling Clock Select Register (

µ

PD780018, 780018Y subseries)

Symbol

SCS

7

0

6

0

5

0

4

0

3

0

2

0

1 0

SCS1 SCS0

Address

FF47H

At reset

00H

R/W

R/W

SCS1

1

1

0

0

SCS0

0

1

0

1

Selects sampling clock of INTP0 f

XX

/2

N f

XX

/2

7 f

XX

/2

5 f

XX

/2

6 f f

X

/2 f

X

/2

X

/2

7

5

6

(39.1 kHz)

(156.3 kHz)

(78.1 kHz)

Caution f

XX

/2

N

is the clock supplied to the CPU, and f

XX

/2

5

, f

XX

/2

6

, and f

XX

/2

7

are the clocks supplied to the peripheral hardware. f

XX

/2

N

is stopped in the HALT mode.

Remarks 1. N : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC)

2. f

XX

: main system clock frequency (f

X

)

3. f

X

: main system clock oscillation frequency

4. ( ) : at f

X

= 5.0 MHz

115

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.1 Setting of Interval Timer

To set the 16-bit timer/event counter as an interval timer, first set the timer clock select register 0 (TCL0) and the

16-bit timer mode control register (TMC0). The clear mode of the 16-bit timer is set by TMC0 and the interval time is set by TCL0.

After that, set the value of the compare register (CR00) from the setup time and count clock. Determine the setup time by using the following expression:

Setup time = (Compare register value + 1)

×

Count clock cycle

This section shows two examples of setup times of the interval timer: 10 ms and 50 ms.

(a) Interval of 10 ms

<1> Setting of TMC0

Selects a mode in which the timer is cleared and started on coincidence between TM0 and CR00.

<2> Setting of TCL0

Select the f

XX

mode in which an interval time of 10 ms or more can be set and the resolution is the highest (OSMS = 01H).

<3> Setting of CR00

10 ms = (N + 1)

×

1

4.19 MHz

N = 10 ms

×

4.19 MHz – 1 = 4.1899

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

CRC0 = #00000000B ; Selects CR00 as compare register

CR00 = #41899

TCL0 = #00100000B ; Selects count clock f

XX

TMC0 = #00001100B ; Clears and starts 16-bit timer/event counter when TM0 and CR00 coincide

116

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(b) Interval of 50 ms

<1> Setting of TMC0

Selects a mode in which the timer is cleared and started on coincidence between TM0 and CR00.

<2> Setting of TCL0

Select the f

XX

/2

2

mode in which an interval time of 50 ms or more can be set and the resolution is the highest (OSMS = 01H).

<3> Setting of CR00

50 ms = (N + 1)

×

1

4.19 MHz/2

2

N = 50 ms

×

4.19 MHz/2

2

– 1 = 52374

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

CRC0 = #00000000B ; Selects CR00 as compare register

CR00 = #52374

TCL0 = #01000000B ; Selects count clock f

XX

/2

2

TMC0 = #00001100B ; Clears and starts 16-bit timer/event counter when TM0 and CR00 coincide

117

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.2 PWM Output

When using the 16-bit timer/event counter in the PWM output mode, set the PWM mode by the 16-bit timer mode control register (TMC0) and enables the output of the 16-bit timer/event counter by the 16-bit timer output control register (TOC0).

The pulse width (active level) of PWM is determined by the value set to the capture/compare register 00 (CR00).

Because the PWM of the 78K/0 series has a resolution of 14 bits, however, bits 2 through 15 of CR00 are valid (clear bits 0 and 1 of CR00 to ‘0, 0’).

In the example below, the basic cycle of the PWM mode is set to 61.0

µ

1 s (

×

2

8

) and the low level is selected f

XX as the active level. The high-order 4 bits of the pulse width are rewritten depending on the value of the parameter

(00H to FFH). Therefore, in the following application example, PWM output can be performed in 16 steps (CR00 =

0FFCH to FFFCH).

(1) Description of package

<Public declaration symbol>

PWM : PWM output subroutine name

PWMOUT : input parameter of PWM active level

<Registers used>

AX

<RAM used>

Name

PWMOUT

Usage

Sets PWM active level

Attribute

SADDR

Bytes

1

<Nesting>

1 level 2 bytes

<Hardware units used>

• 16-bit timer/event counter

• P30/TO0

118

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<Initial setting>

• OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

• Setting of 16-bit timer/event counter

CRC0 = #00000000B ; Selects CR00 as compare register

TMC0 = #00000010B ; PWM output mode

TCL0 = #00100000B ; PWM basic cycle: 61.0

µ s

TOC0 = #00000011B ; Low-active output

• PM30 = 0

• P30 = 0

; P30 output mode

; P30 output latch

<Starting>

After setting data to PWMOUT in RAM, call subroutine PWM.

(2) Example of use

EXTRN PWM, PWMOUT

.

..

OSMS = #00000001B ; Does not use divider circuit

CRC0 = #00000000B

TOC0 = #00000011B

TCL0 = #00100000B

; Selects CR00 as compare register

; Sets low-active PWM output

; Selects count clock f

XX

; Sets PWM mode TMC0 = #00000010B

.

..

PWMOUT = A

CALL !PWM

; Sets input parameter of active level

(3) SPD chart

PWM Loads data of PWMOUT

Decodes data of high-order 4 bits of CR00

Sets XFFCH to CR00 (X: 0 to FH)

119

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC PWM,PWMOUT

PWM_DAT DSEG SADDR

PWMOUT: DS 1

;************************************

;* PWM output (16 steps)

;************************************

P0_SEG CSEG

PWM:

; PWM output data area (0-15)

; Loads high-order data of PWMOUT

A=PWMOUT

A<<=1

A<<=1

A<<=1

A<<=1

A|=#0FH ; Sets low-order 12 bits to 0FFCH

X=#0FCH

CR00=AX

RET

120

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.3 Remote Controller Signal Reception

This section introduces two examples of programs that receives signals from a remote controller by using the 16bit timer/event counter.

• The counter is cleared each time the valid edge of the remote controller signal has been detected, and measures a pulse width from the timer count value (capture register CR01) when the next valid edge has been detected.

• The timer operates in the free running mode to measure a pulse width from the difference of the counter between valid edges. PWM output is also performed at the same time.

The remote controller signal is received by a PIN receiver diode and is input to the P00/TI00/INTP0 pin via receive amplifier

µ

PC1490. Figure 5-12 shows an example of a remote controller signal receiver circuit, and Figure 5-13 shows the format of the remote controller signal.

Figure 5-12. Example of Remote Controller Signal Receiver Circuit

+5 V

+

160 k

V

DD

PH310

100 k

IN+ f

0

V

CC

OUT INTP0/TI00/P00

+

IN–

4.7

+

C

D

GND C

1

1000 pF

GND

Shield case

121

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-13. Remote Controller Signal Transmitter IC Output Signal

Time at oscillation frequency of 455 kHz

67.5 ms

108 ms 108 ms

First time

9 ms 4.5 ms

Custom Code

8 bits

13.5 ms

Leader Code

27 ms

Custom Code

8 bits

67.5 ms

Data Code

8 bits

27 ms

Data Code

8 bits

9 ms 4.5 ms 0.56 ms

13.5 ms 1.125 ms 2.25 ms

0

Second time and onward (signal transmitted only while key is held down)

1 1 0 0 1

9 ms

11.25 ms

2.25 ms

0.56 ms

Because the receiver preamplifier

µ

PC1490 used in the circuit example on the previous page is low-active, the level input to the

µ

PD78054 subseries is the inverted data of the remote controller transmit data.

Figure 5-14. Output Signal of Receiver Preamplifier

µ

PC1490 output

H

L

9 ms 4.5 ms

Leader code

122

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.3.1 Remote controller signal reception by counter clearing

Table 5-1 shows the valid pulse width for receiving a remote controller signal in the program example shown in this section, and <1> through <6> describes how to process each signal. The repeat signal of the remote controller signal is valid only within 250 ms after a valid signal has been input. If a signal input within 3 ms after the normal data has been loaded, the data is invalid.

Table 5-1. Valid Time of Input Signal

Signal Name

Leader code (low)

Leader code

(high)

Output Time

9 ms

Normal 4.5 ms

Repeat 2.25 ms

Valid Time

6.8 ms-11.8 ms

3 ms-5 ms

1.8 ms-3 ms

Custom/data code

0

1

1.125 ms

2.25 ms

0.5 ms-1.8 ms

1.8 ms-2.5 ms

<1> Leader code (low)

The interval time of the 16-bit timer/event counter is set to 1.5 ms, and the port level is sampled by means of interrupt processing. When five low levels have been detected in succession, these low levels are identified as a leader code, and the interval time is changed to 7.81 ms. After that, the pulse width of the low level of the leader code is measured by using rising-edge interrupt request INTP0.

Figure 5-15. Sampling of Remote Controller Signal

Noise Noise

Valid if low five times in succession

Interval time 1.5 ms 7.81 ms

123

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<2> Leader code (high)

The pulse width while the leader code is high is measured by using the falling-edge interrupt request

INTP0 and the count value of the timer.

<3> Custom/data code

The pulse width of each 1 bit (1 cycle) is measured by using the falling-edge interrupt request INTP0.

After the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide. It also checks that there is no data in the 33rd bit.

<4> Repeat code detection

When the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the INTP0 is measured.

<5> Valid period of repeat code

After the valid data has been input, sampling is performed by the interrupt processing (1.5 ms interval) of the 16-bit timer/event counter to measure the valid time of the repeat code of 250 ms.

<6> Time out during pulse width measurement

If the interrupt request of the 16-bit timer/event counter (7.81 ms) occurs during pulse width measurement, it is judged to be time out, and the data is invalid.

(1) Description of package

<Public declaration symbol>

RMDATA : Stores remote controller receive data

RPT : Repeat valid period identification flag

IPDTFG : Valid data identification flag

RMDTOK : Input signal validity identification flag

RMDTSET : Input signal identification flag

<Registers used>

Bank 0: AX, BC, HL

124

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<RAM used>

Name

RPTCT

RMENDCT

SELMOD

LD_CT

RMDATA

WORKP

<Flags used>

Name

IPDTFG

RMDTOK

RMDTSET

RPT

Usage

Repeat code valid time counter

No-input time counter after data input

Mode selection

Leader signal detection counter

Valid data storage area

Input signal storage area

Attribute

SADDR

SADDRP

Usage

Presence/absence of valid data

Validity of input signal

Presence/absence of input signal

Judgment whether repeat valid period elapsed

<Nesting>

5 levels 12 bytes

<Hardware used>

• 16-bit timer/event counter

• P00/TI00/INTP0

<Initial setting>

• OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

• Setting of 16-bit timer/event counter

CRC0 = #00000100B ; Selects operation mode of CR00, CR01

TMC0 = #00001100B ; Clears timer on coincidence between TM0 and CR00

TCL0 = #00100000B ; Count clock f

XX

CR00 = #6290 ; Compare register 00

• SCS = #00000011B ; INTP0 sampling clock f

XX

/2

6

• PPR0 = 0

• TMMK0 = 0

; INTP0 high-priority interrupt

; Enables 16-bit timer/event counter interrupt

• Defines custom code to be CSTM and declares PUBLIC

• RAM clear

<Starting>

Started by INTP0 and INTTM00 interrupt requests

Bytes

1

4

125

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(2) Example of use

PUBLIC CSTM

EXTRN RMDATA,RPTCT

EXTBIT RPT,RMDTSET,IPDTFG

EQU 9DH CSTM

OSMS=#00000001B

CRC0=#00000100B

CR00=#6290

TCL0=#00100000B

TMC0=#00001100B

SCS=#00000011B

CLR1

CLR1

CLR1

CLR1

PPR0

RPT

IPDTFG

RMDTSET

; Remote controller custom code

; Does not use divider circuit

; Selects operation mode of CR00, CR01

; Sets 1.5 ms

; f

XX

/2

6

as INTP0 sampling clock

; INTP0 with high priority

; Clears flag

CLR1

EI

TMMK0

; Enables timer interrupt

;

;

;

;

;

;

;

;

;

DT_TEST: if_bit(RMDTSET)

CLR1 RMDTSET if_bit(RPT)

Repeat processing else

Processing when there is input endif else if_bit(!RPT)

Processing when there is no input endif endif

126

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(3) SPD chart

INTTM00 Selects register bank 1

Enables master interrupt

THEN

IF: input signal exists (IPDTFG)

THEN

IF: valid data exists (RMDTOK)

IF: no input within repeat valid time (250 ms)

THEN

ELSE

Invalidates repeat code

Clears RPT, IPDTFG, and RMDTOK

Counts repeat valid time

Counts leader low time S_LOWCT

ELSE

IF: No input after end of data input (within 4.5 ms)

THEN

Valid data exists

Sets RMDTOK and RMDTSET

Sets leader low detection mode S_M0SET

Initializes leader low detection counter

ELSE

Counts leader low time S_LOWCT

S_LOWCT

THEN

IF: Leader low detection mode

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW five times in succession

Selects leader low measuring mode

Sets 16-bit timer to 7.81 ms

Sets INTP0 rising-edge detection mode

Enables INTP0

Initializes leader low detection counter

ELSE

Initializes leader detection counter

ELSE

Sets leader low detection mode S_M0SET

Initializes leader detection counter

127

128

INTP0

LEAD_L

LEAD_H

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Selects register bank 0

OF: 1

CASE: SELMOD

Leader low measuring mode LEAD_L

OF: 2

Leader high measuring mode LEAD_H

OF: 3

Custom code/data loading mode CDCODE

OF: 4

Repeat code detection mode REPCD

OF: 5

Abnormal data detection mode ENDCHK

THEN

IF: P00 = HIGH

THEN

IF: P00 = HIGH

THEN

Reads timer CR_READ

IF: 6.8 ms

Ieader low

11.8 ms

Selects leader high detection mode

Sets INTP0 falling-edge detection mode

ELSE

Sets leader low detection mode S_M0SET

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

THEN

Reads timer CR_READ

IF: 2 ms

leader high

5 ms

IF: Ieader high

3 ms

THEN

Selects custom code/data load mode

Initializes data storage area

ELSE

Selects repeat detection mode

Sets INTP0 rising-edge detection mode

ELSE

Sets leader low detection mode S_M0SET

CDCODE

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Reads timer CR_READ

IF: 0.5 ms < input data

2.5 ms

THEN

THEN

IF: input data

1.8 ms

Sets CY

ELSE

Clears CY

Stores CY to data storage area

THEN

IF: end of 32 bits of data input

THEN

IF: custom code coincides

THEN

IF: custom/data code coincides with inverted data

Stores data code

Sets status in which input data exists

Sets IPDTFG and clears RMDTSET, RPT, and RMDTOK

Sets leader low detection mode S_M0SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets leader low detection mode S_M0SET

REPCD

THEN

IF: P00 = HIGH

THEN

IF: P00 = HIGH

THEN

IF: valid data exists

THEN

Reads timer CR_READ

IF: repeat code

1 ms

Sets repeat code valid status

Sets RPT

Sets data input end status

Sets abnormal data detection mode S_M5SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets abnormal data detection mode S M5SET

129

130

ENDCHK

CR_READ

S_M0SET

S_M5SET

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Sets input signal invalid status

Clears IPDTFG and RPT

Sets leader low detection mode S_M0SET

Reads capture register

Stops 16-bit timer operation

Starts timer

Selects leader low detection mode

Disables INTP0 interrupt

Sets 16-bit timer to 1.5 ms

Selects abnormal data detection mode

Sets counter for repeat valid time

Sets 16-bit timer to 1.5 ms

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC RPT,IPDTFG,RMDTOK,RMDTSET

PUBLIC RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA

EXTRN CSTM

RM_DAT DSEG

RPTCT: DS

RMENDCT:

SELMOD: DS

LD_CT: DS

RMDATA: DS

SADDR

1

DS

1

1

1

SADDRP

4

RM_DATP DSEG

WORKP: DS

BSEG

IPDTFG DBIT

RMDTOK DBIT

RMDTSET DBIT

RPT DBIT

VEP0 CSEG

DW

VETM0 CSEG

DW

AT 06H

INTP0

AT 20H

INTTM00

; Repeat code valid time counter

; Selects mode

; Leader signal detection counter

; Valid data storage area

; Input signal storage area

; Valid data exists

; Input signal is valid

; Input signal exists

; Repeat code valid period

; Sets vector address of INTP0

; Sets vector address of 16-bit timer

;******************************************************

; Remote controller signal timer processing

;******************************************************

TM0_SEG CSEG

INTTM00:

SEL RB1

EI if_bit(IPDTFG) if_bit(RMDTOK)

RPTCT–– if(RPTCT==#0)

CLR1

CLR1

RPT

IPDTFG

RMDTOK CLR1 endif else

CALL !S_LOWCT

RMENDCT–– if(RMENDCT==#0)

SET1

SET1

RMDTOK

RMDTSET

!S_M0SET

CALL endif

LD_CT=#5 endif else

CALL endif

RETI

!s_LOWCT

; Enables interrupt (INTP0)

; Input signal exists?

; Valid data exists?

; Repeat invalid time

; Repeat code invalid status

; Sets that valid data exists

; Sets leader (low) detection mode

131

132

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

S_LOWCT: if(SELMOD==#0) if_bit(!P0.0)

LD_CT–– if(LD_CT==#0)

SELMOD=#1

TMC0=#00000000B

CR00=#32767

TMC0=#00001100B

INTM0=#00000100B

CLR1

CLR1

LD_CT=#5

PIF0

PMK0 endif else

LD_CT=#5 else endif

CALL

LD_CT=#5

!S_MOSET

; Leader (low) detection mode?

; Leader (low) measuring mode

; Timer: 7.81 ms

; Enables INTP0 interrupt

; Sets leader (low) detection mode endif

RET

$EJECT

;***********************************************************

;* Remote controller signal edge detection processing

;***********************************************************

P0_SEG CSEG

INTP0:

SEL RB0

CALL !WAIT

switch(SELMOD) case 1:

CALL break case 2:

CALL break case 3:

CALL break case 4:

CALL break case 5:

CALL ends

RET1

!LEAD_L

!LEAD_H

!CDCODE

!REPCD

!ENDCHK

; Waits for 100

µ s

; Leader low detection processing

; Leader high detection processing

; Custom/data code loading processing

; Repeat code detection processing

; Abnormal data detection processing

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;****************************************

;* Leader low detection

;****************************************

LEAD_L: if_bit(P0.0)

CALL !WAIT

if_bit(P0.0)

CALL !CR_READ

if(AX>=#3354) if(AX<#18035)

SELMOD=#2

INTM0=#00000000B else

CALL endif else

CALL endif endif

!S_MOSET

!S_MOSET

endif

RET

$EJECT

;****************************************

;* Leader high detection

;****************************************

LEAD_H: if_bit(!P0.0)

CALL !WAIT

if_bit(!P0.0)

CALL !CR_READ

if(AX>=#6710–160/2) if(AX<#20132–160/2) if(AX>#11743–160/2)

SELMOD=#3

WORKP=#0000H else

(WORKP)+2=#8000H

SELMOD=#4

INTM0=#00000100B else endif

CALL endif

!S_M0SET

else

CALL endif endif endif

RET

!S_M0SET

$EJECT

; Level check P0.0 = 0: noise

; Waits for 100

µ s

; Reads timer value

; 6.8 ms – (1.5 ms * 4)

; 11.8 ms – (1.5 ms * 5)

; Leader high detection mode

; INTP0 falling edge

; Sets leader (low) detection mode

; Sets leader (low) detection mode

; Level check P0.0 = 1: noise

; Waits for 100

µ s

; Reads timer value

; 1.8 ms – 100

µ s * 2 – 160 clocks (edge detection

timer starts)

; 5 ms – 100

µ s * 2 – 160 clocks (edge detection

timer starts)

; Custom/data code (3 ms – 100

µ s * 2)?

; Data loading mode

; Initializes work area

; Sets most significant bit to 1 (to check end of data)

; Repeat detection mode

; INTP0 rises

; Sets leader (low) detection mode

; Sets leader (low) detection mode

133

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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;******************************

;* Custom/data code loading

;******************************

CDCODE: if_bit(!P0.0)

CALL !WAIT

if_bit(!P0.0)

CALL !CR_READ

; Level check P0.0 = 1: noise

; Waits for 100

µ s if(AX>=#1257–190/2) if(AX<#9646–190/2) if(AX>=#6710–190/2)

SET1 CY else

; Reads timer value

; 0.5 ms – 100

µ s * 2 – 190 clocks (edge detection

timer starts)

; 2.5 ms – 100

µ s * 2 –190 clocks (edge detection

timer starts)

; 1.8 ms – 100

µ s * 2 – 190 clocks (edge detection

timer starts)

CLR1 endif

HL=#WORKP+3

CY

C=#4

WKSHFT:

A=[HL]

RORC A,1

A^WORKP+1 if(A==#0FFH)

; Sets work area address

; Sets number of digits of work area

; Stores 1-bit data

; Shifts 1 bit

[HL]=A

HL––

DBNZ if_bit(CY)

C,$WKSHFT

; End of shifting all bits

; End of 32-bit input?

if(WORKP+0==#CSTM) (A)

; Custom code check

; Custom code inverted data check

A=WORKP+2

A^=WORKP+3

; Data code inverted data check if(A==#0FFH)

; Stores input data

RMDATA=WORKP+2 (A)

; Sets status in which input data exists

SET1

CLR1

IPDTFG

RMDTSET

CLR1

CLR1 else

CALL

RPT

RMDTOK

!S_M5SET

CALL else endif

CALL

; Sets leader (low) detection mode

!S_M0SET

; Sets leader (low) detection mode

!S_M0SET

else endif

CALL !S_M0SET

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

endif endif else

CALL else endif

CALL

!S_M0SET

!S_M0SET

endif endif endif

RET

$EJECT

;************************************

;* Repeat code detection

;************************************

REPCD: if_bit(P0.0)

CALL !WAIT

if_bit(P0.0) if_bit(RMDTOK)

CALL !CR_READ

if(AX<=#3354–190/2)

SET1

CLR1

RPT

RMDTOK

CLR1

CALL else

CALL

RMDTSET

!S_M5SET

!S_M0SET

endif endif

RET else endif

CALL endif

!S_M0SET

$EJECT

; Sets leader (low) detection mode

; Sets leader (low) detection mode

; Level check P0.0 = 0: noise

; Waits for 100

µ s

; Valid data exists?

; Reads timer value

; 1 ms – 100

µ s * 2 – 190 clocks (edge detection

timer starts)

; Input signal check after end of data

; Sets leader (low) detection mode

; Sets leader (low) detection mode

135

136

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;****************************************

;* Abnormal data detection

;****************************************

ENDCHK: if_bit(!P0.0)

CALL !WAIT

if_bit(!P0.0)

CLR1 IPDTFG

CLR1

CALL endif endif

RET

RPT

!S_M0SET

; Level check P0.0 = 1: noise

; Waits for 100

µ s

; Abnormal data input

; Input signal invalid

; Sets leader (low) detection mode

;****************************************

;* Waits for 100

µ s

;****************************************

WAIT:

B=#(838–14–12–8)/12

WAITCT:

DBNZ

RET

B,$WAITCT

; CALL(14), RET(12), MOV(8)

; Sets 100

µ s

; 1 instruction 12 clocks

;*****************************************

;* Sets leader (low) detection mode

;*****************************************

S_M0SET:

TMC0=#00000000B

CR00=#6290

TCL0=#00100000B

; Sets timer to 1.5 ms

TMC0=#00001100B

SELMOD=#0

SET1

RET

PMK0

; Leader (low) detection mode

;*****************************************

;* Sets abnormal data detection mode

;*****************************************

S_M5SET:

RPTCT=#173

SELMOD=#5

RMENDCT=#3

TMC0=#00000000B

CR00=#6290

TMC0=#00001100B

RET

; 250 ms measuring counter

; Data input end mode

; No-input checking counter

; Stops operation

; Sets 1.5 ms

;****************************************

;* Reads timer count value

;****************************************

CR_READ:

AX=CR01

TMC0=#00000000B

TMC0=#00001100B

RET

; Stops operation

; Starts timer

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.3.2 Remote controller signal reception by PWM output and free running mode

Table 5-2 shows the valid pulse width when a remote controller signal is received by this program. <1> through

<6> below describes how each signal is processed.

Table 5-2. Valid Time of Input Signal

Signal Name

Leader code (low)

Leader code

(high)

Output Time

9 ms

Normal 4.5 ms

Repeat 2.25 ms

Custom/data code

0

1

1.125 ms

2.25 ms

Valid Time

3 ms-10 ms

3 ms-5 ms

1.8 ms-3 ms

0.5 ms-1.8 ms

1.8 ms-2.5 ms

<1> Leader code (low)

The value of the capture/compare register 01 (CR01) is stored to memory by an interrupt request that occurs when the falling edge of INTP0 is detected.

The pulse width is measured from the difference between the values of CR01 and the capture/compare register 00 (CR00) when the rising edge is generated.

<2> Leader code (high)

The pulse width between the high levels of the leader code is measured by the falling-edge interrupt request INTP0 and the count value of the timer.

<3> Custom/data code

The pulse width of each 1 bit (1 cycle) is measured by the falling-edge interrupt request INTP0. After the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide.

It also checks that there is no data of the 33rd bit.

<4> Repeat code detection

When the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the INTP0 is measured.

<5> Valid period of repeat code

After the valid data has been input, the overflow flag (OVF0) of the 16-bit timer/event counter is tested by the main program, and the repeat code valid time of 250 ms is measured.

137

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<6> Time out during pulse width measurement

The OVF0 of the 16-bit timer/event counter is tested during pulse width measurement. If it is detected two times, time out is assumed and the data is assumed to be invalid.

Because the 16-bit timer/event counter operates in the PWM mode in this example, the remote controller signal is received and, at the same time, PWM output can be performed by linking the program of 5.2

PWM Output.

(1) Description of package

<Public declaration symbol>

TIM_PRO : name of subroutine processing timer overflow

RMDATA : stores remote controller receive data

RPT : repeat valid period identification flag

IPDTFG : valid data identification flag

RMDTOK : valid input signal identification flag

RMDTSET : input signal identification flag

OVSENS : INTP0 processing timer overflow detection flag

<Registers used>

Bank 0: AX, BC, HL

<RAM used>

Name

RPTCT

RMENDCT

SELMOD

LD_CT

RMDATA

TO_CNT

CR01_NP

CR01_OP

WORKP

Mode selection

Usage

Repeat code invalid time counter

No-input time counter after data input

Leader signal detection counter

Valid data storage area

Timer overflow detection counter

Newest timer count value storage area

Previous timer count value storage area

Input signal storage area

Attribute

SADDR

SADDRP

Bytes

1

2

4

138

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<Flag used>

Name

IPDTFG

RMDTOK

RMDTSET

RPT

TO_FLG

OVSENS

Usage

Presence/absence of valid data

Presence/absence of valid input signal

Presence/absence of input signal

Judgment whether repeat valid period elapsed

Occurrence of timer overflow

Detection of timer overflow by INTP0 processing

<Nesting>

5 levels 11 bytes

<Hardware used>

• 16-bit timer/event counter

• P00/TI00/INTP0

• P30/TO0

<Initial setting>

• OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

• Setting of 16-bit timer/event counter

CRC0 = #00000100B ; Selects operation mode of CR00, CR01

TMC0 = #00000010B ; PWM output mode

TCL0 = #00100000B ; PWM basic cycle: 61.0

µ s

TOC0 = #00000011B ; Low-active output

• PM30 = 0

• SCS = #00000011B

; P30 output mode

; INTP0 sampling clock f

XX

/2

6

• PPR0 = 0

• PMK0 = 0

; INTP0 high-priority interrupt

; Enables INTP0 interrupt

• Defines custom code to CSTM and declares PUBLIC

• RAM clear

<Starting>

• Test the OVF0 of the 16-bit timer/event counter. When OVF0 is set, call subroutine TIM_PRO.

• Start by an interrupt request when the valid edge of the remote controller signal is detected.

139

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(2) Example of use

CSTM

PUBLIC CSTM

EXTRN RMDATA,RPTCT,PWM,PWMOUT,TIM_PRO

EXTBIT RPT,RMDTSET,IPDTFG,TO_FLG,OVSENS

EQU 9DH

; Custom code

OSMS=#00000001B

CRC0=#00000100B

TOC0=#00000011B

TCL0=#00100000B

TMC0=#00000010B

INTM0=#00000000B

SCS=#00000011B

CLR1

CLR1

CLR1

CLR1

PPR0

RPT

IPDTFG

RMDTSET

; Does not use divider circuit

; Selects operation mode of CR00, CR01

; PWM output, low active setting

; Selects count clock f

XX

; PWM mode, overflow occurs

; INTP0 falling edge

; INTP0 sampling clock f

XX

/2

6

; INTP0 with high priority

; Clears flag

;

;

;

;

;

;

;

;

;

CLR1

DT_TEST:

EI

PMK0 if_bit(OVSENS)

CLR1 OVSENS

CALL !TIM_PRO

elseif_bit(OVF0)

CLR1

SET1

CALL endif

OVF0

TO_FLG

!TIM_PRO

if_bit(RMDTSET)

CLR1 RMDTSET if_bit(RPT)

Repeat processing else

; Enables INTP0 interrupt

; Detects timer overflow by INTP0 processing

; Timer overflow occurs

Processing when input exists else endif if_bit(!RPT)

Processing when input does not exist endif endif

MOV

CALL

PWMOUT,A

!PWM

140

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(3) SPD chart

TIM_PRO

TO_CHK

INTP0

IF: input signal exists

THEN

THEN

IF: valid data exists

THEN

IF: repeat code invalid time

Sets repeat code invalid status

Clears RPT, IPDTFG, RMDTOK

Checks timer overflow TO_CHK

ELSE

THEN

IF: No input exists after input of data (within 61.0 s

×

2)

Sets that valid data exists

Sets RMDTOK, RMDTSET

Sets leader low detection mode S_M0SET

ELSE

Checks timer overflow TO_CHK

THEN

IF: leader low detection mode

Sets that timer overflow does not occur

ELSE

Timer overflow count

IF: Timer overflow occurs 2 times

THEN

Sets leader low detection mode S_M0SET

Selects register bank 0

OF: 0

CASE: SELMOD

Leader low detection mode RM_STA

OF: 1

Leader low measuring mode LEAD_L

OF: 2

Leader high measuring mode LEAD_H

OF: 3

Custom code/data loading mode CDCODE

OF: 4

Repeat code detection mode REPCD

OF: 5

Abnormal data detection mode ENDCHK

141

142

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

RM_STA

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Stores data of capture register to memory

Selects leader low measuring mode 1

Sets INTP0 rising-edge detection mode

LEAD_L

THEN

IF: P00 = HIGH

THEN

IF: P00 = HIGH

THEN

Reads timer PW_CT

IF: 3 ms

Ieader low

10 ms

Selects leader high detection mode

Sets INTP0 falling-edge detection mode

ELSE

Sets leader low detection mode S_M0SET

LEAD_H

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Reads timer PW_CT

IF: 2 ms

leader high

5 ms

THEN

IF: Ieader high

3 ms

THEN

Selects custom code/data loading mode

Initializes data storage area

ELSE

Selects repeat detection mode

Sets INTP0 rising-edge detection mode

ELSE

Sets leader low detection mode S_M0SET

CDCODE

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Reads timer CR_READ

IF: 0.5 ms < input data

2.5 ms

THEN

IF: input data

1.8 ms

THEN

Sets CY

ELSE

Clears CY

Stores CY to data storage area

IF: end of 32 bits of data input

THEN

THEN

IF: custom code coincidence

THEN

IF: Coincidence between custom/data code and inverted data

Stores data code

Sets input data existing status

Sets IPDTFG, and clears RMDTSET, RPT, and RMDTOK

Sets abrormal data detection mode S_M5SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets leader low detection mode S_M0SET

REPCD

THEN

IF: P00 = HIGH

THEN

IF: P00 = HIGH

THEN

IF: valid data exists

Reads timer PW_CT

IF: repeat code

1 ms

THEN

Sets repeat code valid status

Sets RPT

Sets data input end status

Sets abnormal data detection mode S_M5SET

ELSE

Sets leader low detection mode S_M0SET

ELSE

Sets abnormal data detection mode S_M5SET

143

144

ENDCHK

PW_CT

S_M0SET

S_M5SET

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

THEN

IF: P00 = LOW

THEN

IF: P00 = LOW

Sets input signal invalid status

Clears IPDTFG, RPT

Sets leader low detection mode S_M0SET

THEN

IF: OVF occurs after edge detection processing

THEN

IF: OVF occurs < interrupt acknowledgment processing time (65 clocks)

THEN

Sets that timer overflow occurs

Loads capture register value

Subtracts capture register value from previous value

IF: borrow occurs as result of subtraction (CY = 1)

IF: timer overflow occurs (TO_FLG = 1)

THEN

Clears CY flag

ELSE

THEN

IF: timer overflow occurs (TO_FLG = 1)

Sets CY flag

Stores capture register value to memory

Selects leader low detection mode

Clears TO_FLG

Sets INTP0 falling-edge detection mode

Selects abnormal data detection mode

Sets repeat valid time counter

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC TIM_PRO,RPT,IPDTFG,RMDTOK,RMDTSET

PUBLIC RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA

PUBLIC TO_FLG,OVSENS

EXTRN CSTM

RM_DAT DSEG

RPTCT: DS

RMENDCT:DS

SELMOD: DS

LD_CT: DS

RMDATA: DS

TO_CNT: DS

RM_DATP DSEG

CR01_NP:DS

CR01_OP:DS

WORKP: DS

SADDR

1

1

1

1

1

1

SADDRP

2

2

4

; Repeat code valid time counter

; No-input time counter after data input

; Mode selection

; Leader signal detection counter

; Valid data storage area

; Timer overflow counter

; Newest timer counter value storage area

; Previous timer counter value storage area

; Input signal storage area

BSEG

IPDTFG DBIT

RMDTOK DBIT

RMDTSET DBIT

RPT DBIT

TO_FLG DBIT

OVSENS DBIT

VEP0 CSEG

DW

; Valid data exists

; Input signal valid

; Input signal exists

; Repeat code valid period

; Timer overflow occurs

; Detects timer overflow by INTP0 processing

AT 06H

INTP0

; Sets vector address of INTP0

$EJECT

;******************************************************

; Remote controller signal timer processing

;******************************************************

TM0_SEG CSEG

TIM_PRO: if_bit(IPDTFG) if_bit(RMDTOK)

; Input signal exists?

; Valid data exists?

RPTCT–– if(RPTCT==#0)

CLR1

CLR1

RPT

IPDTFG

RMDTOK CLR1 endif else

RMENDCT––

; Repeat invalid time

; Repeat code valid status endif endif else

CALL !TO_CHK

endif

RET if(RMENDCT==#0)

SET1 RMDTOK

SET1

CALL

RMDTSET

!S_M0SET

; Valid data exists

; Sets leader (low) detection mode

; Checks timer overflow

145

146

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

TO_CHK: if(SELMOD==#0) else

CLR1 TO_FLG

TO_CNT++ if(TO_CNT==#2)

CALL !S_M0SET

; Sets start edge detection mode endif endif

RET

$EJECT

;***********************************************************

;* Remote controller signal edge detection processing

;***********************************************************

P0_SEG CSEG

INTP0:

SEL RB0

CALL !WAIT

; Waits for 100

µ s switch(SELMOD) case 0:

CALL break case 1:

CALL break case 2:

CALL break case 3:

CALL break case 4:

CALL break case 5: ends

CALL

RET1

!RM_STA

!LEAD_L

!LEAD_H

!CDCODE

!REPCD

!ENDCHK

; Start edge detection processing

; Leader low detection processing

; Leader high detection processing

; Custom/data code loading processing

; Repeat code detection processing

; Abnormal data detection processing

;***********************************************************

;* Start edge detection

;***********************************************************

RM_STA:

CLR1 if_bit(!P0.0)

CALL

TO_FLG

!WAIT

if_bit(!P0.0)

; Starts timer count

; Level check P0.0 = 1: noise

; Waits for 100

µ s

CR01_OP=CR01 (AX)

SELMOD=#1

INTM0=#00000100B

TO_CNT=#0

; Stores capture register

; Leader low detection mode

; INTP0 rising edge endif endif

RET

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;****************************************

;* Leader low detection

;****************************************

LEAD_L: if_bit(P0.0)

CALL !WAIT

if_bit(P0.0)

CALL !PW_CT

if_bit(!CY)

TO_CNT=#0 if(AX>=#12582) if(AX<#41942)

SELMOD=#2

INTM0=#00000000B else

CALL !S_M0SET

else endif

CALL endif

!S_M0SET

else

CALL endif endif

!S_M0SET

endif

RET

$EJECT

;****************************************

;* Leader high detection

;****************************************

LEAD_H: if_bit(!P0.0)

CALL !WAIT

if_bit(!P0.0)

CALL if_bit(!CY)

!PW_CT

TO_CNT=#0 if(AX>=#7549) if(AX<#20971) if(AX>#12582)

SELMOD=#3

WORKP=#0000H else

(WORKP)+2=#8000H

SELMOD=#4

INTM0=#00000100B else endif

CALL endif else

CALL

!S_M0SET

!S_M0SET

endif endif

RET

$EJECT else endif

CALL endif

!S_M0SET

; Level check P0.0 = 1: noise

; Waits for 100

µ s

; Reads timer value

; 3 ms

; 10 ms

; Leader high detection mode

; INTP0 falling edge

; Sets start edge detection mode

; Sets start edge detection mode

; Sets start edge detection mode

; Level check P0.0 = 0: noise

; Waits for 100

µ s

; Reads timer value

; 1.8 ms

; 5 ms

; Custom/data code (3 ms)?

; Data loading mode

; Initializes work area

; Sets most significant bit to 1 (to confirm end of data)

; Repeat detection mode

; INTP0 rises

; Sets start edge detection mode

; Sets start edge detection mode

; Sets start edge detection mode

147

148

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;******************************

;* Custom/data code loading

;******************************

CDCODE: if_bit(!P0.0)

CALL !WAIT

if_bit(!P0.0)

CALL !PW_CT

if_bit(!CY)

TO_CNT=#0 if(AX>=#2096) if(AX<#10485) if(AX>=#7549)

CY SET1 else

CLR1 endif

CY

; Level check P0.0 = 1: noise

; Waits for 100

µ s

; Reads timer value

; 0.5 ms

; 2.5 ms

; 1.8 ms

HL=#WORKP+3

C=#4

WKSHFT:

A=[HL]

A,1 RORC

[HL]=A

HL––

DBNZ C,$WKSHFT

; Sets work area address

; Sets number of work area digits

; Stores 1-bit data

; Shifts 1 bit

; End of shifting all digits if_bit(CY)

; End of input of 32 bits?

; Checks custom code if(WORKP+0==#CSTM) (A)

A^=WORKP+1 if(A==#0FFH)

A=WORKP+2

; Checks custom code inverted data

; Checks data code inverted data

A^=WORKP+3 if(A==#0FFH)

; Stores input data

RMDATA=WORKP+2 (A)

; Sets input data existing status

SET1 IPDTFG else

CLR1

CLR1

CLR1

CALL

RMDTSET

RPT

RMDTOK

!S_M5SET

!S_M0SET

; Sets start edge detection mode else

CALL endif

; Sets start edge detection mode endif endif else

CALL !S_M0SET

else endif

CALL endif else

CALL

!S_M0SET

!S_M0SET

; Sets start edge detection mode

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

$EJECT

CALL endif endif endif endif

RET else

CALL !S_M0SET

!S_M0SET

;************************************

;* Repeat code detection

;************************************

REPCD: if_bit(P0.0)

CALL !WAIT

if_bit(P0.0) if_bit(RMDTOK)

CALL !PW_CT

if_bit(!CY)

TO_CNT=#0 if(AX<=#4193)

SET1

CLR1

CLR1

CALL else

CALL else endif

RPT

RMDTOK

RMDTSET

!S_M5SET

!S_M0SET

CALL endif else

CALL

!S_M0SET

!S_M0SET

endif

RET

$EJECT endif endif

; Sets start edge detection mode

; Sets start edge detection mode

; Level check P0.0 = 1: noise

; Waits for 100

; Valid data?

; Reads timer value

; 1 ms

µ s

; Checks input signal after end of data

; Sets start edge detection mode

; Sets start edge detection mode

; Sets start edge detection mode

149

150

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;*********************************************

;* Abnormal data detection

;*********************************************

ENDCHK: if_bit(!P0.0)

CALL !WAIT

; Level check P0.0 = 1: noise

; Waits for 100

µ s if_bit(!P0.0)

CLR1

CLR1

CALL

IPDTFG

RPT

!S_M0SET

; Abnormal data input

; Input signal invalid

; Sets start edge detection mode endif endif

RET

;*********************************************

;* Calculation of capture register value

;*********************************************

PW_CT: if_bit(OVF0) if(CR01<#10000–33) (AX)

; OVF0 after edge detection?

; Interrupt acknowledgment processing time = 65 clocks (MAX)

SET1 endif endif

CLR1

SET1

OVF0

OVSENS

TO_FLG

CR01_NP=CR01 (AX)

; Loads capture register value

; AX = CR01_NP – CR01_OP

A=CR01_NP+0

A–=CR01_OP

X=A

A=CR01_NP+1

SUBC A,CR01_OP+1

BC=AX if_bit(CY) if_bit(TO_FLG)

CLR1 CY else endif if_bit(TO_FLG)

SET1 CY endif endif

; Saves operation result

; CR01_NP > CR01_OP

; Timer overflow occurs (flag test)

; Normal data

; Timer overflow

; Error occurs

CR01_OP=CR01_NP (AX)

AX=BC

CLR1

RET

TO_FLG

; Restores operation result

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

;**********************************************

;* Waits for 100

µ s

;**********************************************

WAIT:

B=#(838–14–12–8)/12

WAITCT:

DBNZ

RET

B,$WAITCT

; CALL (14), RET (12), MOV (8)

; Sets 100

µ s

; 1 instruction 12 clocks

;**********************************************

;* Sets start edge detection mode

;**********************************************

S_M0SET:

TO_CNT=#0

SELMOD=#0

INTM0=#00000000B

RET

; Start edge detection mode

; INTP0 falling edge

;**********************************************

;* Setting of abnormal data detection mode

;**********************************************

S_M5SET:

RPTCT=#16

SELMOD=#5

RMENDCT=#2

RET

; 250 ms measuring counter

; Data input end mode

; No-input checking counter

151

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

5.4 One-Shot Pulse Output

The 16-bit timer/event counter has a function which outputs a one-shot pulse in synchronization with a software trigger and external trigger (INTP0/TI00/P00 pin input).

When using the one-shot pulse output function, the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register (TOC0) must be set.

In this section, an example for setting the one-shot pulse by using the software trigger is introduced.

The OSPT flag (bit 6 of the TOC0 register) is set at arbitrary timing (such as key input).

After the software trigger has occurred, TM0 is cleared and started. When the value of TM0 coincides with the value set in advance to CR01, the TO0/P30 pin output is inverted (and becomes active). When the value of TM0 later coincides with the value set in advance to CR00, the TO0/P30 pin output is inverted again (and becomes inactive).

The TM0 counter is cleared and counting up is started again after the value of TM0 has coincided with the value of

CR00. The output of the TO0/P30 pin, however, is not inverted even if coincidence occurs next time. TM0 is cleared and started and the output of the TO0/P30 pin is inverted only when the software trigger is set. The active level of the TO0/P30 pin is determined by selecting the initial value of the TO0/P30 pin output of the TOC0 register.

Note that, when using the one-shot pulse output function with the software trigger, the OSPT flag must not be set to 1 while the one-shot pulse is output. To output the one-shot pulse again, do so after INTTM00, which is an interrupt request that occurs when TM0 coincides with CR00, has occurred.

In the example presented in this section, the software trigger is designed by using key input, and “H” active output is produced 10 ms after for 1 ms.

152

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

Figure 5-16. Timing of One-Shot Pulse Output Operation by Software Trigger

Count clock

0000 N N+1 M–2 M–1 M 0000 TM0 count value

TO0/P30 pin output

CR01 set value

CR00 set value

OSPT

INTTM01

INTTM00

N

M

F_TRG

10 ms 1 ms

Remark F_TRG: flag indicating that output of the one-shot pulse is in progress. For details, refer to (2) Example

of use.

153

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(1) Description of package

<Public declaration symbol>

SOP_INIT: One-shot pulse output initial setting subroutine

<Register used>

None

<RAM used>

None

<Nesting level>

1 level 2 bytes

<Hardware used>

• 16-bit timer/event counter

<Initial setting>

• OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

• CLR1

• CLR1

• CALL

P3.0

PM3.0

; Clears output latch of bit 0 of port 3 to 0

; Sets bit 0 of port mode register 3 in output mode

!SOP_INIT ; Sets by subroutine SOP_INIT

<Starting>

Set bit 6 (OSPT) of the 16-bit timer output control register (TOC0).

154

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(2) Example of use

Because bit 6 (OSPT) of the 16-bit timer output control register (TOC0) is not set again while the pulse is output in the example of this package, the F_TRG flag is set as soon as the OSPT flag has been set as shown in

Figure 5-16. Even if the next output request is issued while the F_TRG flag is set (i.e., while the pulse is output), the OSPT flag is not set. After the one-shot pulse has been output (INTTM00 occurs), clear the F_TRG flag.

EXTRN SOP_INT

M1PR0

RES_STA:

CSEG

OSMS=#00000001B

CLR1 P3.0

CLR1 PM3.0

CALL !SOP_INIT

·

· if(key request issued) if_bit(!F_TRG)

SET1 OSPT

F_TRG SET1 endif endif if_bit(TMIF00)

CLR1 F_TRG

CLR1 endif

TMIF00

·

·

; Does not use divider circuit

; Sets 0 to output latch if multiplexed pin is used

; Sets output mode if multiplexed pin is used

; One-shot pulse output initial setting routine

;

;

;

; Previous output ends?

Clears and starts 16-bit counter

Sets one-shot pulse trigger flag

;

;

;

;

; End of one-shot pulse output?

Clears one-shot trigger flag

Clears TMIF00 request flag

(3) SPD chart

SOP_INIT Stops timer operation

Selects count clock of 16-bit timer register

Uses CR00 and CR01 as compare registers

Sets compare register 00 (CR00)

(Time required from start of trigger to second inversion of TO0 output)

Sets compare register 01 (CR01)

(Time required from start of trigger to first inversion of TO0 output)

Selects one-shot pulse output mode

Starts on coincidence between TM0 and CR00

(enables timer operation)

155

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC SOP_INIT

OPINIT CSEG

SOP_INIT:

TMC0=#00000000B

TCL0=#01000000B

CRC0=#00000000B

CR00=#11550–1

CR01=#10500–1

TOC0=#00110111B

TMC0=#00001100B

RET

END

5.5 PPG Output

; Stops timer operation

; Count clock of 16-bit timer register: 1.05 MHz

; Uses CR00 and CR01 as compare registers

;

; Sets compare register to 11 ms

; Sets compare register to 10 ms

; Selects one-shot pulse mode

; Starts on coincidence between TM0 and CR00 (enables timer operation)

When using the 16-bit timer/event counter in the PPG (Programmable Pulse Generator) mode, the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register

(TOC0) must be set.

As the PPG output pulse, a square wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count value set in advance to the 16-bit capture/ compare register 01 (CR01) is output from the TO0/P30 pin.

In the application example shown in this section, the output waveform is changed by using the PPG output. Data indicating the one cycle and pulse width of the output waveform is stored in ROM. This data is stored in the compare register.

The cycle and pulse width of the PPG output in this program can be changed in units of 1 ms to 10 ms. Therefore, the cycle can be set in a range of 2 to 10 ms, and the pulse width can be set in a range of 1 to 9 ms. If the cycle is equal to or less than the pulse width when the output waveform is changed, the data is not changed.

The output waveform is changed after the end of one output cycle. Figure 5-17 shows the PPG output waveform changing timing.

Figure 5-17. PPG Output Waveform Changing Timing

Request for change

Data changed Request for change

Data changed

Pulse width

1 cycle

156

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(1) Description of package

<Public declaration symbol>

• Subroutine name

SPG_INIT : PPG output initial setting subroutine

• Data definition reference name of SPG_INIT routine

PDAT

SDAT

: First address of data value for pulse width stored to compare register

: First address of data value for cycle stored to compare register

• Input parameter of SPG_INIT routine

PARUSU : Pulse width time storage area

SAIKURU : 1 cycle time storage area

• Input/output parameters of SPG_INIT routine and INTTM00 interrupt

PARUSUP : Pulse width time change data storage area

SAIKURUP : 1-cycle time change data storage area

<Registers used>

SPG_INIT : Bank 0 AX, HL

INTTM00 : Bank 2 AX

<RAM used>

Name

PARUSU

SAIKURU

PARUSUP

SAIKURUP

Sets pulse width time

Sets 1-cycle time

Usage Attribute

SADDR

SADDR

Sets compare data value corresponding to pulse SADDRP width time

Sets compare data value corresponding to 1 cycle SADDRP time

<Flag used>

None

Bytes

1

1

2

2

157

158

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

<Nesting level>

1 level 3 bytes

<Hardware used>

• 16-bit timer/event counter

<Initial setting>

• OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

• CLR1

• CLR1

• CALL

P3.0

PM3.0

; Clears output latch of bit 0 of port 3 to 0

; Sets bit 0 of port mode register 3 in output mode

!PPG_INIT ; Sets by subroutine PPG_INIT

<Starting>

After the 16-bit timer/event counter has been reset and started, set pulse width time in the specified range to PARUSU in RAM and cycle time in the specified range to SAIKURU, and call subroutine PPG_INIT.

When changing the PPG output waveform, clear the INTTM00 interrupt request flag to enable the interrupt after setting a compare data value corresponding to the pulse width in the specified range to PARUSUP, and a compare data value corresponding to the cycle time in the specified range to SAIKURUP.

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(2) Example of use

EXTRN SPG_INIT

EXTRN SAIKURUP.PARUSUP

EXTRN SAIKURU,PARUSU

EXTRN PDAT,SDAT

;

SMIN

PMIN

EQU

EQU

·

·

02H

01H

;

; Minimum cycle time

; Minimum pulse width time

OSMS=#00000001B

SAIKURU=#SMIN

PARUSU=#PMIN

CLR1 P3.0

CLR1 PM3.0

CALL

EI

!SPG_INIT

·

;

;

; Does not use divider circuit

; Sets initial cycle value

; Sets initial pulse width value

; Clears output latch to 0 if multiplexed pin is used

; Sets output mode if multiplexed pin is used

· if(request for changing square wave) if(SAIKURU > PARUSU) (A)

A=PARUSU

A––

A <<= 1

X=A

A=#0

AX+=#PDAT

HL=AX

X=[HL] (A)

HL++

A=[HL]

PARUSUP=AX

;

; If SAIKURUP > PARUSU

; Data 1

address XXX0

; Data 2

address XXX2

; Data 3

address XXX4

·

; Table reference of low-order 8 bits of value stored to

;

;

; compare register

X register

low-order 8 bits

;

;

; Table reference of high-order 8 bits of value stored to compare register

A register

high-order 8 bits endif

·

A=SAIKURU

A––

A––

A <<= 1

X=A

A=#0

AX+=#SDAT

HL=AX

X=[HL] (A)

HL++

A=[HL]

SAIKURUP=AX

CLR1

CLR1 endif

TMIF00

TMMK00

;

;

;

;

;

;

;

; Cycle time storage processing

;

;

;

;

;

;

; Clears request flag

;

; Enables compare register 00 interrupt

No data change

·

159

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(3) SPD chart

PPG_INIT

INTTM00

Stops timer operation

Selects count clock of 16-bit timer register

Uses CR00 and CR01 as compare registers

Table reference of compare data corresponding to PARUSU area contents and stores it in PARUSU area

Table reference of compare data corresponding to SAIKURU area contents and stores it in SAIKURUP area

Stores contents of SAIKURUP area to compare register 00 (CR00)

Stores contents of PARUSUP area to compare register 01 (CR01)

Sets successive pulse output and sets initial value "H" of TO0 pin output

Starts on coincidence between TM0 and CR00 (enables timer operation)

Selects register bank 2

Stores contents of SAIKURUP area to compare register 00 (CR00)

Stores contents of PARUSUP area to compare register 01 (CR01)

Disables INTTM00 interrupt

160

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC SPG_INIT,PDAT,SDAT

PUBLIC SAIKURU,PARUSU

EXTRN SAIKURUP,PARUSUP

;

;************************************************

; RAM definition

;************************************************

PPGRAM DSEG SADDR

SAIKURU:

PARUSU:

;

DS

DS

1

1

;

; 1 cycle time storage area

; Pulse width storage area

;************************************************

; PPG output initial setting

;************************************************

PPGINIT CSEG

SPG_INIT:

TMC0=#00000000B

;

TCL0=#00100000B

CRC0=#00000000B

A=PARUSU

A––

A <<= 1

X=A

A=#0

AX+=#PDAT

HL=AX

X=[HL] (A)

HL++

A=[HL]

PARUSUP=AX

A=SAIKURU

A––

A––

A <<= 1

X=A

A=#0

AX+=#SDAT

HL=AX

X=[HL] (A)

HL++

A=[HL]

SAIKURUP=AX

CR00=SAIKURUP (AX)

CR01=PARUSUP (AX)

TOC0=#00011011B

TMC0=#00001100B

RET

; Stops timer operation

; Count clock of 16-bit timer register: 4.19 MHz

;

;

;

;

; Uses CR00 and CR01 as compare register

Data 1

address XXX0

Data 2

address XXX2

Data 3

address XXX4

·

; Table reference of low-order 8 bits of value stored to

;

;

; compare register

X register

low-order 8 bits

;

;

;

; Table reference of high-order 8 bits of value stored to compare register

A register

high-order 8 bits

;

;

;

;

;

;

;

; Cycle time storage processing

;

;

;

;

;

; Sets compare register to 2 ms

; Sets compare register to 1 ms

; Sets successive pulse output and initial value ‘H’

; Starts on coincidence between TM0 and CR00 (enables timer operation)

161

162

CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER

PDAT:

DW 4201

DW 8403

DW 12605

DW 16807

DW 21009

DW 25211

DW 29413

DW 33615

DW 37817

SDAT:

DW 8403

DW 12605

DW 16807

DW 21009

DW 25211

DW 29413

DW 33615

DW 37817

DW 42019

END

;

;

;

;

;

;

;

;

;

;

;

;

;

;

; Address XXX0

; Address XXX2

; Address XXX4

; Address XXX0

; Address XXX2

; Address XXX4

PUBLIC

;

VETM00

PARUSUP,SAIKURUP

CSEG

DW

AT 20H

INTTM00

;

P2RAM

PARUSUP:

DSEG

DS

SADDRP

2

; Pulse width time changing data storage area

SAIKURUP: DS 2

; 1 cycle time changing data storage area

;****************************************************************

; PPG output (cycle pulse width time changing interrupt)

;****************************************************************

TM00

INTTM00:

SEL

RETI

END

CSEG

RB2

CR01=PARUSUP (AX)

CR00=SAIKURUP (AX)

SET1 TMMK00

;

;

;

;

; Selects bank 2

; CR00, CR01

← stores pulse width and cycle time changing data

; Disables compare register 00 interrupt

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

The 8-bit timer/event counter of the 78K/0 series has three functions: interval timer, external event counter, and square wave output. Two channels of 8-bit timers/event counters are provided and these timers/event counters can be used as a 16-bit timer/event counter when connected in cascade.

The 8-bit timers/event counters are set by the following registers:

• Timer clock select register 1 (TCL1)

• 8-bit timer mode control register (TMC1)

• 8-bit timer output control register (TOC1)

• Port mode register 3 (PM3)

• Port 3 (P3)

163

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Figure 6-1. Format of Timer Clock Select Register 1

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY)

Symbol 7 6 5 4 3 2 1 0

TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10

Address

FF41H

At reset

00H

R/W

R/W

TCL13 TCL12 TCL11 TCL10

0

0

0

0

1

1

1

1

1

1

1

1

Others

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Falling edge of TI1

Rising edge of TI1

Selects count clock of 8-bit timer register 1

MCS = 1 MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

12

(1.2 kHz)

Setting prohibited f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

TCL17 TCL16 TCL15 TCL14

0

0

0

0

1

1

1

1

1

1

1

1

Others

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Falling edge of TI2

Rising edge of TI2

Selects count clock of 8-bit timer register 2

MCS = 1 MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

12

(1.2 kHz)

Setting prohibited f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

Caution Before writing new data to TCL1, stop the timer operation once.

164

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. TI1 : input pin of 8-bit timer register 1

4. TI2 : input pin of 8-bit timer register 2

5. MCS: bit 0 of oscillation mode select register (OSMS)

6. ( ) : at f

X

= 5.0 MHz

165

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Figure 6-2. Format of Timer Clock Select Register 1 (

µ

PD78098, 78098B subseries)

Symbol 7 6 5 4 3 2 1 0

TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10

Address

FF41H

At reset

00H

R/W

R/W

TCL13 TCL12 TCL11 TCL10

0 0 0 0

Selects count clock of 8-bit timer register 1

Falling edge of TI1

0

0

0

1

1

1

1

1

1

1

1

Others

0

1

1

0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

Rising edge of TI1 f

XX

/2 (2.0 MHz) f

XX

/2

2

(1.0 MHz) f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz) f

XX

/2

9

(7.8 kHz) f

XX

/2

11

(2.0 kHz)

Setting prohibited

TCL17 TCL16 TCL15 TCL14

0 0 0 0

Selects count clock of 8-bit timer register 2

Falling edge of TI2

0

0

0

1

1

1

1

1

1

1

1

Others

0

1

1

0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

Rising edge of TI2 f

XX

/2 (2.0 MHz) f

XX

/2

2

(1.0 MHz) f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz) f

XX

/2

9

(7.8 kHz) f

XX

/2

11

(2.0 kHz)

Setting prohibited

Caution Before writing new data to TCL1, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency

2. TI1: input pin of 8-bit timer register 1

3. TI2: input pin of 8-bit timer register 2

4. ( ) : at f

XX

= 4.0 MHz

166

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Figure 6-3. Format of Timer Clock Select Register 1 (

µ

PD780018, 780018Y subseries)

Symbol 7 6 5 4 3 2 1 0

TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10

Address

FF41H

At reset

00H

TCL13 TCL12 TCL11 TCL10

0 0 0 0

Selects count clock of 8-bit timer register 1

Falling edge of TI1

0

0

0

1

1

1

1

1

1

1

1

Others

0

1

1

0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

Rising edge of TI1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Setting prohibited f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

R/W

R/W

TCL17 TCL16 TCL15 TCL14

0 0 0 0

Selects count clock of 8-bit timer register 2

Falling edge of TI2

0

0

0

1

1

1

1

1

1

1

1

Others

0

1

1

0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

Rising edge of TI2 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Setting prohibited f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

Caution Before writing new data to TCL1, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. TI1 : input pin of 8-bit timer register 1

4. TI2 : input pin of 8-bit timer register 2

5. ( ) : at f

X

= 5.0 MHz

167

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Symbol

TMC1

7

0

6

0

5

0

Figure 6-4. Format of 8-Bit Timer Mode Control Register

4

0

3 2 1

0 TMC12 TCE2

0

TCE1

Address

FF49H

At reset

00H

R/W

R/W

TCE1 Controls operation of 8-bit timer register 1

0 Stops operation (clears TM1 to 0)

1 Enables operation

TCE2 Controls operation of 8-bit timer register 2

0 Stops operation (clears TM2 to 0)

1 Enables operation

TMC12 Selects operation mode

0

1

8-bit timer register

×

2 channel mode (TM1, TM2)

16-bit timer register

×

1 channel mode (TMS)

Cautions 1. Before changing the operation mode, stop the timer operation.

2. When using the two 8-bit timer registers as a one 16-bit timer register, enable or stop the operation by using TCE1.

168

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Figure 6-5. Format of 8-Bit Timer Output Control Register

Symbol

TOC1

7

LVS2

6 5 4

LVR2 TOC15 TOE2

3 2 1 0

LVS1 LVR1 TOC11 TOE1

Address

FF4FH

At reset

00H

R/W

R/W

TOE1 Controls output of 8-bit timer/event counter 1

0 Disables output (port mode)

1 Enables output

TOC11 Controls timer output F/F of 8-bit timer/event counter 1

0 Disables reverse operation

1 Enables reverse operation

1

1

0

0

LVS1 LVR1

0

1

0

1

Sets status of timer output F/F of 8-bit timer/ event counter 1

Not affected

Resets timer output F/F (to 0)

Sets timer output F/F (to 1)

Setting prohibited

TOE2 Controls output of 8-bit timer/event counter 2

0 Disables output (port mode)

1 Enables output

TOC15 Controls timer output F/F of 8-bit timer/event counter 2

0 Disables reverse operation

1 Enables reverse operation

LVS2 LVR2

1

1

0

0

0

1

0

1

Sets status of timer output F/F of 8-bit timer/ event counter 2

Not affected

Resets timer output F/F (to 0)

Sets timer output F/F (to 1)

Setting prohibited

Cautions 1. Before setting TOC1, be sure to stop the timer operation.

2. LVS1, LVS2, LVR1, and LVR2 are always 0 when they are read.

169

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

Figure 6-6. Format of Port Mode Register 3

Symbol

PM3

7 6 5 4 3 2

PM37 PM36 PM35 PM34 PM33 PM32

1 0

PM31 PM30

Address

FF23H

At reset

FFH

R/W

R/W

PM3n Selects input/output mode of P3n pin (n = 0-7)

0 Output mode (output buffer ON)

1 Input mode (output buffer OFF)

170

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

6.1 Setting of Interval Timer

When using an 8-bit timer/event counter as an interval timer, set an operation mode by the 8-bit timer mode control register (TMC1) and interval time by the timer clock select register 1 (TCL1).

After that, set the values of the compare registers (CR10 and CR20) from the setup time and count clock. The setup time is determined by using the following expression:

Setup time = (Compare register value + 1)

×

Count clock cycle

The setup time can be calculated in the same manner regardless of whether each 8-bit timer/event counter is used or two 8-bit timers/event counters are used as a 16-bit timer/event counter. The count clock when two 8-bit timers/ event counters are used as a 16-bit timer/event counter, however, is selected by the bits 0 through 3 (TCL10 through

TCL13) of TCL1.

Examples of the modes of the 8-bit timers and 16-bit timer are described next.

Figure 6-7. Count timing of 8-Bit Timers

Count clock

TM1, TM2

INTTM1, INTTM2

TO1

N–2 N–1 N 00 01 02 N–2 N–1 N

171

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

6.1.1 Setting of 8-bit timers

In this example, 8-bit timer 2 is used to set two types of interval times: 500

µ s and 100 ms.

(a) To set interval of 500

µ

s

<1> Setting of TMC1

Select the 8-bit timer register

×

2 channel mode and enables the operation of the 8-bit timer 2.

<2> Setting of TCL1

Select f

XX

/2

4

that allows setting of 500

µ s or more and has the highest resolution (OSMS = 01H).

<3> Setting of CR20

500

µ s = (N + 1)

×

1

4.19 MHz/2

4

N = 500

µ s

×

4.19 MHz/2

4

– 1 = 130

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

TCL1 = #10011001B ; Selects f

XX

/2

4

as count clock

CR20 = #130

TMC1 = #00000010B

(b) To set interval of 100 ms

<1> Setting of TMC1

Select the 8-bit timer register

×

2 channel mode and enables the operation of the 8-bit timer 2.

<2> Setting of TCL1

Select f

XX

/2

11

that allows setting of 100 ms or more and has the highest resolution (OSMS = 01H).

<3> Setting of CR20

100 ms = (N + 1)

×

1

4.19 MHz/2

11

N = 100 ms

×

4.19 MHz/2

11

– 1 = 204

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

TCL1 = #11111111B ; Selects f

XX

/2

11

as count clock

CR20 = #204

TMC1 = #00000010B

172

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

6.1.2 Setting of 16-bit timer

In this example, 8-bit timers 1 and 2 are connected in cascade as a 16-bit timer to set two types of interval times:

500 ms and 10 s.

(a) To set interval of 500 ms

<1> Setting of TMC1

Select the 16-bit timer register

×

1 channel mode and enables the operation of the 8-bit timers 1 and 2.

<2> Setting of TCL1

Select f

XX

/2

5

that allows setting of 500 ms or more and has the highest resolution (OSMS = 01H).

<3> Setting of CR10 and CR20

500 ms =

N + 1

4.19 MHz/2

5

N = 500 ms

×

4.19 MHz/2

5

– 1 = 65468 = FF6CH

CR10 = 6CH, CR20 = FFH

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

TCL1 = #00001010B

CR10 = #06CH

CR20 = #0FFH

TMC1 = #00000111B

; Sets 65468 to CR10 and CR20

; CR10 = 6CH, CR20 = FFH

(b) To set interval of 10 s

<1> Setting of TMC1

Select the 16-bit timer register

×

1 channel mode and enable the operation of the 8-bit timers 1 and

2.

<2> Setting of TCL1

Select f

XX

/2

11

that allows setting of 10 s or more and has the highest resolution (OSMS = 01H).

<3> Setting of CR10 and CR20

10 s =

N + 1

4.19 MHz/2

11

N = 10 s

×

4.19 MHz/2

11

– 1 = 20458 = 4FEAH

CR10 = EAH, CR20 = 4FH

(1) Program list

OSMS = #00000001B ; Does not use divider circuit

TCL1 = #00001111B

CR10 = #0EAH

CR20 = #4FH

TMC1 = #00000111B

; Sets 20458 to CR10 and CR20

; CR10 = EAH, CR20 = 4FH

173

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

6.2 Musical Scale Generation

This section shows an example of a program that uses the square wave output (P31/TO1) of an 8-bit timer/event counter and generates a musical scale by supplying pulses to an external buzzer.

Figure 6-8. Musical Scale Generation Circuit

V

DD

P31/TO1

The output frequency of the P31/TO1 pin is set by the count clock and a compare register. In this example, the central frequency of the musical scale is set to a range of 523 to 1046 Hz. Therefore, f

XX

/2

5

is selected as the count clock (oscillation mode select register: OSMS = 01H). Table 6-1 shows the musical scale, the set value of the compare register, and frequency of the output pulse. Because one cycle of the timer output is created when the value of the timer coincides with the value of the compare register two times, the interval time is set as half a cycle time.

Figure 6-9. Timer Output and Interval

Interval

CR10 coincidence interval

Timer output cycle

174

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

As for the time length of a sound, the output time is determined by setting an interval time with 8-bit timer/event counter 2 and by counting the number of times the interrupt generated by the timer/event counter. In this example,

8-bit timer/event counter 2 is set to 20 ms.

Table 6-1. Musical Scale and Frequency

Musical Scale Musical Scale Frequency Hz Compare Register Value Output Frequency Hz

Do 523.25

124 524.3

Re

Mi

587.33

659.25

111

98

585.1

662.0

Fa

So

La

Tee

Do

698.46

783.98

880.00

987.77

1046.5

93

83

73

65

62

697.2

780.2

885.6

993.0

1040

The format of the data table for this program is shown below.

TABLE:

DB musical scale data 1, sound length data 1

DB musical scale data 2, sound length data 2

.

..

..

.

DB musical scale data n, sound length data n

DB 0, 0

The musical scale data is set to 0 for rest, and the sound length data is set to 0 for the end of data.

Example Number of counts of 8-bit timer/event counter to output sound for 1 second

Number of counts = 1 s/20 ms = 50 (50 is set as number of counts)

This program sequentially outputs do, re, mi, and so on, for 1 second each.

175

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

(1) Description of package

<Public declaration symbol>

MLDY: Subroutine name of musical scale generation program

<Registers used>

Bank 0: A, B, HL

<RAM used>

Name

POINT

LNG

Usage

Stores pointer value of table data

Counts sound length data

<Nesting>

1 level 3 bytes

<Hardware used>

8-bit timer/event counters 1 and 2

P31/TO1

<Initial setting>

Sets by subroutine MLDY

Enables interrupt

<Starting>

Call subroutine MLDY

(2) Example of use

EXTRN MLDY

.

..

CALL !MLDY

EI

Attribute

SADDR

Bytes

1

176

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

(3) SPD chart

MLDY

INTTM2

Sets P31/TO1 in output mode

Clears pointer (POINT) of reference table to 0

Sets initial data 1 as sound length data (LNG)

Sets 8-bit timer/event counter 1 in output mode

Sets 8-bit timer/event counter 2 to 20 ms

Enables 8-bit timer 2 interrupt

Selects register bank 0

Decrements sound length data (LNG)

THEN

IF: end of output time

THEN

References sound data indicated by pointer

IF: sound data

mute data

Sets sound data to compare register of timer 1

ELSE

Disables TO1 output of timer 1

THEN

References sound length data

IF: sound length data

musical scale generation end data

Sets sound length data

ELSE

Disables timer 2 interrupt

Stops timer 2 operation

177

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

(4) Program list

PUBLIC MLDY

VETM2 CSEG

DW

ML_DAT DSEG

POINT: DS

LNG: DS

AT 26H

INTTM2

SADDR

1

1

; Sets vector address of 8-bit timer/event counter

; Pointer for table data

; Sound length data

;*************************************************

;* Musical scale generation initialize

;*************************************************

ML_SEG CSEG

MLDY:

CLR

POINT=#0

LGN=#1

PM3.1

; Sets P3.1 in output mode

; Initial setting of pointer

OSMS=#00000001B

TOC1=#00000011B

; Does not use divider circuit

; Sets TO1 output mode

TCL1=#11101010B

CR20=#163

TMC1=#00000010B

CLR1 TMMK2

RET

; Sets timer 2 to 20 ms

; Enables timer 2 operation

; Enables timer 2 interrupt

$EJECT

178

CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER

;***********************************************

; Sets musical scale generation data

;***********************************************

TM2_SEG CSEG

INTTM2:

SEL RB0

LNG–– if(LNG==#0)

B=POINT (A)

HL=#TABLE

A=[HL+B] if(A!=#0)

CLR1 TCE1

; Sets table first address

; Sets sound data

CR10=A

SET1

SET1 else

CLR1 endif

TOE1

TCE1

TOE1

B++

A=[HL+B] if(A!=#0)

LNG=A

B++

POINT=B (A) else

SET1

CLR1 endif

TMMK2

TCE2

; Increments pointer

; Loads sound length data

; Sound output in progress?

; Sets sound length data

; Disables timer 2 interrupt

; Stops timer 2 operation endif

RETI

;***********************************************

; Musical scale data table

;***********************************************

TABLE:

DB

DB

DB

DB

124,50

111,50

98,50

93,50

; Do

; Re

; Mi

; Fa

DB

DB

DB

DB

DB

83,50

73,50

65,50

62,50

00,00

; So

; La

; Tee

; Do

; End

179

[MEMO]

180

CHAPTER 7 APPLICATIONS OF WATCH TIMER

The watch timer of the 78K/0 series has a watch timer function that causes the timer to overflow every 0.5 second by using the main system clock or subsystem clock as the clock source, and an interval timer function that allows you to set six types of reference times. These two functions can be simultaneously used.

The watch timer is set by using timer clock select register 2 (TCL2) and watch timer mode control register (TMC2).

181

CHAPTER 7 APPLICATIONS OF WATCH TIMER

Figure 7-1. Format of Timer Clock Select Register 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

3

0

2 1 0

TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

R/W

R/W

TCL22 TCL21 TCL20

1

1

0

0

1

1

0

0

1

1

1

1

0

0

0

0

0

1

0

1

0

1

0

1 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

Selects count clock of watchdog timer

MCS = 1 f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

12

(1.2 kHz)

TCL24 Selects count clock of watch timer

MCS = 1 f

X

/2

7

(39.1 kHz)

MCS = 0 f

X

/2

8

(19.5 kHz) 0

1 f

XX

/2

7 f

XT

(32.768 kHz)

TCL27 TCL26 TCL25

1

1

0

1

1

×

0

0

1

1

×

0

1

0

1

Selects frequency of buzzer output

MCS = 1

Disables buzzer output f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Setting prohibited f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz)

MCS = 0 f

X

/2

10

(4.9 kHz) f

X

/2

11

(2.4 kHz) f

X

/2

12

(1.2 kHz)

Caution Before writing new data to TCL2, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4.

×

: don’t care

5. MCS: bit 0 of oscillation mode select register (OSMS)

6. ( ) : at f

X

= 5.0 MHz or f

XT

= 32.768 kHz

182

CHAPTER 7 APPLICATIONS OF WATCH TIMER

Figure 7-2. Format of Timer Clock Select Register 2 (

µ

PD78098, 78098B subseries)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

3

0

2 1 0

TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

Selects count clock of watchdog timer TCL22 TCL21 TCL20

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1 f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz) f

XX

/2

9

(7.8 kHz) f

XX

/2

11

(2.0 kHz)

R/W

R/W

TCL24

0

1 f

XX

/2

7

(31.3 kHz) f

XT

(32.768 kHz)

Selects count clock of watch timer

TCL27 TCL26 TCL25

0

× ×

1 0 0

Disables buzzer output f

XX

/2

9

(7.8 kHz)

1

1

0

1

1

0 f

XX

/2

10

(3.9 kHz) f

XX

/2

11

(1.95 kHz)

1 1 1 Setting prohibited

Selects frequency of buzzer output

Caution Before writing new data to TCL2, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency

2. f

XT

: subsystem clock oscillation frequency

3.

×

: don’t care

4. ( ): at f

XX

= 4.0 MHz or f

XT

= 32.768 kHz

183

CHAPTER 7 APPLICATIONS OF WATCH TIMER

Figure 7-3. Format of Timer Clock Select Register 2 (

µ

PD780018, 780018Y subseries)

Symbol 7 6 5 4

TCL2 TCL27 TCL26 TCL25 TCL24

TCL22 TCL21 TCL20

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

11

3 2

1 0

0 TCL22 TCL21 TCL20

Address

FF42H

At reset

00H

Selects count clock of watchdog timer f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

11

(2.4 kHz)

R/W

R/W

TCL24

0 f

XX

/2

7

1 f

XT

Selects count clock of watch timer f

X

/2

7

(39.1 kHz)

TCL27 TCL26 TCL25

0

× ×

1 0 0

Disables buzzer output f

XX

/2

9

1

1

0

1

1

0 f

XX

/2

10 f

XX

/2

11

1 1 1 Setting prohibited

Selects frequency of buzzer output f f

X

/2 f

X

/2

X

/2

9

10

(9.8 kHz)

11

(4.9 kHz)

(2.4 kHz)

Caution Before writing new data to TCL2, stop the timer operation once.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. f

XT

: subsystem clock oscillation frequency

4.

×

: don’t care

5. ( ): at f

X

= 5.0 MHz or f

XT

= 32.768 kHz

184

CHAPTER 7 APPLICATIONS OF WATCH TIMER

Figure 7-4. Format of Watch Timer Mode Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780018, 780018Y, 780058,

780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY)

Symbol

TMC2

7

0

6 5 4 3 2 1 0

TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20

Address

FF4AH

At reset

00H

R/W

R/W

TMC20

0

Selects watch operation mode

Normal operation mode (sets flag at f

W

/2

14

)

1 Fast-forward mode (sets flag at f

W

/2

5

)

TMC21

0 Clears after operation stopped

1 Enables operation

Controls operation of prescaler

TMC22

0 Clears after operation stopped

1 Enables operation

Controls operation of 5-bit counter

TMC23

0

1

At f

XX

= 5.0 MHz

2

14

/f

W

(0.4 sec)

2

13

/f

W

(0.2 sec)

Selects set time of watch timer

At f

XX

= 4.19 MHz

2

14

/f

W

(0.5 sec)

2

13

/f

W

(0.25 sec)

At f

XT

= 32.768 kHz

2

14

/f

W

(0.5 sec)

2

13

/f

W

(0.25 sec)

TMC26 TMC25 TMC24

0

0

0

0

1

1

Others

0

0

1

1

0

0

0

1

0

1

0

1

At f

XX

= 5.0 MHz

2

4

/f

W

(410

µ s)

2

5

/f

W

(819

µ s)

2

6

/f

W

(1.64 ms)

2

7

/f

W

(3.28 ms)

2

8

/f

W

(6.55 ms)

2

9

/f

W

(13.1 ms)

Setting prohibited

Selects interval time of prescaler

At f

XX

= 4.19 MHz

2

4

/f

W

(488

µ s)

2

5

/f

W

(977

µ s)

2

6

/f

W

(1.95 ms)

2

7

/f

W

(3.91 ms)

2

8

/f

W

(7.81 ms)

2

9

/f

W

(15.6 ms)

At f

XT

= 32.768 kHz

2

4

/f

W

(488

µ s)

2

5

/f

W

(977

µ s)

2

6

/f

W

(1.95 ms)

2

7

/f

W

(3.91 ms)

2

8

/f

W

(7.81 ms)

2

9

/f

W

(15.6 ms)

Caution Do not often clear the prescaler when the watch timer is used.

Remarks 1. f

W

: watch timer clock frequency (f

XX

/2

7

or f

XT

)

2. f

XX

: main system clock frequency (f

X

or f

X

/2)

3. f

X

: main system clock oscillation frequency

4. f

XT

: subsystem clock oscillation frequency

185

CHAPTER 7 APPLICATIONS OF WATCH TIMER

Figure 7-5. Format of Watch Timer Mode Control Register (

µ

PD78098, 78098B subseries)

Symbol

TMC2

7

0

6 5 4 3 2 1 0

TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20

Address

FF4AH

At reset

00H

R/W

R/W

TMC23 TMC20

0

1

0

0

1

1

Selects set time of watch flag

2

14

/f

W

(0.5s)

2

13

/f

W

(0.25s)

2

5

/f

W

µ

2

4

/f

W

µ

TMC21 Controls operation of prescaler

0 Clears after operation stopped

1 Enables operation

TMC22 Controls operation of 5-bit counter

0 Clears after operation stopped

1 Enables operation

TMC26 TMC25 TMC24

0

0

0

0

1

1

Others

0

0

1

1

0

0

0

1

0

1

0

1

Selects interval time of prescaler

2

4

/f

W

µ

2

5

/f

W

µ

2

6

/f

W

(1.95 ms)

2

7

/f

W

(3.91 ms)

2

8

/f

W

(7.81 ms)

2

9

/f

W

(15.6 ms)

Setting prohibited

Caution Do not often clear the prescaler when the watch timer is used.

Remarks 1. f

W

: watch timer clock frequency (f

X

/2

8

or f

XT

)

2. ( ): at f

W

= 32.768 kHz

186

CHAPTER 7 APPLICATIONS OF WATCH TIMER

7.1 Watch and LED Display Program

As an example of using the watch timer, this section introduces a program that counts time by using an 0.5 second overflow and dynamically displays LED at intervals of 1.95 ms.

To count time, an overflow flag is tested each time a subroutine is called. When the flag is set, time is counted up in seconds. Because an overflow occurs every 0.5 second, it takes 1 minute to count 120 times. The overflow flag is tested at intervals of 1.95 ms so that the flag is tested without fail. The watch of this program is 24-hour watch.

The high-order and low-order digits of minute and hour data are stored in separate areas of memory.

Figure 7-6. Concept of Watch Data

Second data

0-120

Minute data Hour data

Low-order digit 0-9

High-order digit 0-5

Low-order digit 0-9

High-order digit 0-2

187

CHAPTER 7 APPLICATIONS OF WATCH TIMER

As LED dynamic display, four digits are displayed with the display digit changed at intervals of 1.95 ms. In this example, the high-order 4 bits of P3 are used as a digit signal, and P5 that can directly drive an LED is selected as a segment signal.

The digit of an LED specified by a display digit area (DIGCT) in an LED display area is displayed. To change the digit signal, the segment signal is turned off so that the adjacent digits are not displayed.

Figure 7-7. LED Display Timing

P34

P35

P36

P37

Port 5

DIGIT 0 1 2 3

Segment signal OFF

0 1 2 3 0 1 2 3

Figure 7-8. Circuit Example of Watch Timer

P50

P57

P37

P36

P35

P34

7-segment LED

×

4

188

CHAPTER 7 APPLICATIONS OF WATCH TIMER

(1) Description of package

<Public declaration symbol>

SECD : second data storage area

MINDP : minute data storage area

HOURDP : hour data storage area

LEDDP : LED display area

<Register used>

Bank 0: AX, B, HL

<RAM used>

Name

MINDP

HOURDP

SECD

DIGCT

LEDDP

Usage

Stores minute data

Stores hour data

Stores second data

Stores LED display digit data

LED display data

Attribute

SADDRP

<Hardware used>

Watch timer

P34-37

P5

<Initial setting>

TMC2 = #00100110B ; 0.5-second watch operation at 1.95 ms interval

TMMK3 = 0 ; enables watch timer interrupt

<Starting>

Started by the interval timer interrupt request of the watch timer.

(2) Example of use

EXTRN MINDP, HOURDP, SECD, LEDDP

TMC2 = #00100110B ; 0.5-second watch operation at 1.95 ms interval

CLR1 TMMK3 ; Enables watch timer interrupt

EI

Bytes

2

1

4

189

CHAPTER 7 APPLICATIONS OF WATCH TIMER

(3) SPD chart

INTTM3 Selects register bank 0

Watch count TIME

LED display LEDDSP

LEDDSP

TIME

THEN

Turns OFF segment signal

IF: digit counter (DIGCT) = 0

Initial setting of digit signal

ELSE

Shifts digit signal I bit higher

Outputs segment signal of digit indicated by digit counter

Increments digit counter

THEN

IF: Sets watch timer interrupt request flag

THEN

Increments second counter

IF: second counter = 120

Sets second counter to 0

Increments minute (low) counter

IF: minute (low) counter = 10

THEN

Clears minute (low) counter to 0

Increments minute (high) counter

IF: minute (high) counter = 6

THEN

Clears minute (high) counter to 0

Increments hour (low) counter

IF: hour data

0204H

THEN

THEN

IF: hour (low) counter = 10

Clears hour (low) counter to 0

Increments hour (high) counter

ELSE

Clears hour counter to 0

190

CHAPTER 7 APPLICATIONS OF WATCH TIMER

(4) Program list

PUBLIC HOURDP,MINDP,SECD,LEDDP

WT_DATP DSEG

MINDP: DS

HOURDP: DS

SECD: DS

DIGCT: DS

LEDDP: DS

SADDRP

2

2

1

1

4

; Minute data storage area

; Hour data storage area

; Second data storage area

; LED display digit area

; LED display area

VETM3 CSEG

DW

AT 1EH

INTTM3

;***************************************

;* Interval interrupt processing

;***************************************

TM3_SEG CSEG

INTTM3:

SEL RB0

CALL !TIME

CALL

RETI

!LEDDPSP

; Sets vector address of watch timer

191

192

CHAPTER 7 APPLICATIONS OF WATCH TIMER

;************************************

; LED display

;************************************

LEDDPSP:

P5=#0FFH

DIGCT&=#00000011B if(DIGCT==#0)

; Turns OFF segment output

; Adjusts digit counter (0-3)

A=P3

A&=#00001111B

A|=#00010000B else

P3=A

A=P3

A&=#11110000B

X=A

A=P3

A+=X

P3=A endif

; Initial setting of digit signal (high-order 4 bits)

; Shifts high-order 4 bits

B=DIGCT (A)

HL=#LEDDP

B=[HL+B] (A)

HL=#SEGDT

P5=[HL+B] (A)

; Sets address of display data

; Display area first address

; Sets display data

; Conversion to segment data

; Outputs segment signal

DIGCT++

RET

SEGDT:

$EJECT

DB 11000000B

DB 11111001B

DB 10100100B

DB 10110000B

DB 10011001B

DB 10010010B

DB 10000010B

DB 11111000B

DB 10000000B

DB 10010000B

DB 10001000B

DB 10000011B

DB 11000110B

DB 10100001B

DB 10000110B

DB 10001110B

; 0

; 1

; 2

; 3

; 4

; 5

; 6

; 7

; 8

; 9

; A

; B

; C

; D

; E

; F

CHAPTER 7 APPLICATIONS OF WATCH TIMER

;********************************

;* Watch count up

;********************************

TIME: if_bit(WTIF)

CLR1

SECD++

WTIF if(SECD==#120)

SECD=#0

(MINDP+0)++ if((MINDP+0)==#10)

(MINDP+0)=#0

(MINDP+1)++ if(MINDP+1==#6)

(MINDP+1)=#0

(HOURDP+0)++ if(HOURDP!=#0204H) (AX) if((HOURDP+0)==#10)

(HOURDP+0)=#0

(HOURDP+1)++ endif endif

RET endif endif else endif

HOURDP=#0000H endif

; 0.5 second test

; 120 = 60 seconds/0.5

; Increments minute (low)

; Carry occurs

; Increments minute (high)

; Carry occurs

; Hour data 24?

; Carry occurs

193

[MEMO]

194

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

The 78K/0 series is provided with the serial interface shown in Table 8-1.

µ

PD78054

µ

PD78054Y

µ

PD78064

µ

PD78064Y

µ

PD78078

µ

PD78078Y

µ

PD78083

µ

PD78098

µ

PD780018

µ

PD780018Y

µ

PD780058

µ

PD780058Y

µ

PD780308

µ

PD780308Y

µ

PD78058F

µ

PD78058FY

µ

PD78064B

µ

PD78070A

µ

PD78070AY

µ

PD78075B

µ

PD78075BY

µ

PD78098B

Subseries

×

×

×

Table 8-1. Serial Interface Channel of Each Subseries

Configuration

of Serial

Interface

Channel 0

3-wire 2-wire SBI

×

×

×

×

×

×

×

×

×

×

×

×

×

×

Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

×

×

×

×

×

×

×

I

2

C bus 3-wire 3-wire with automatic transmission/ reception function

3-wire UART 3-wire 3-wire I

2

C bus with time-

(multimaster division supfunction porting)

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

Note

Note

Note

Note

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

×

Note With time-division transfer function

Remark

: Function provided,

×

: Function not provided

195

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

The serial interface of the 78K/0 series has a different function depending on the subseries, as shown in Table

8-1. This chapter explains each function and application example of the serial interface. The function supported by each subseries are listed in Table 8-2. For details of application examples of using the serial interface function of a specific subseries, refer to the section or paragraph marked in this table.

Table 8-2. Items Supported by Each Subseries

Item 8.1.1

8.1.2

8.2

Communication Communication Interface in 2-wire serial I/O mode in I

2

C bus mode with OSD LSI

(

µ

PD6451A)

Subseries

µ

PD78054

µ

PD78054Y

µ

PD78064

µ

PD78064Y

µ

PD78078

µ

PD78078Y

µ

PD78083

µ

PD78098

µ

PD780018

µ

PD780018Y

µ

PD780058

µ

PD780058Y

µ

PD780308

µ

PD780308Y

µ

PD78058F

µ

PD78058FY

µ

PD78064B

µ

PD78070A

µ

PD78070AY

µ

PD78075B

µ

PD78075BY

µ

PD78098B

8.3

Interface in SBI Mode

8.4

8.5

Interface in Interface in

3-Wire Serial I/O Asynchronous

Mode Serial Interface

(UART) Mode

196

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

The functions and operations of the serial interface are specified by using the following registers:

Serial Interface

Channel 0

Channel 1

Channel 2

Table 8-3. Registers of Serial Interface

Register Used

• Timer clock select register (TCL3)

• Serial operation mode register 0 (CSIM0)

• Serial bus interface control register (SBIC)

• Interrupt timing specification register (SINT)

• Timer clock select register (TCL3)

• Serial operation mode register 1 (CSIM1)

• Automatic data transmission/reception control register (ADTC)

• Automatic data transmission/reception interval specification register (ADTI)

• Serial operation mode register 2 (CSIM2)

• Asynchronous serial interface mode register (ASIM)

• Asynchronous serial interface status register (ASIS)

• Baud rate generator control register (BRGC)

• Serial interface pin select register (SIPS)

Note

Note

This register is provided only on the

µ

PD780058, 780058Y, 780308, and 780308Y subseries.

Remark This chapter describes the register formats and application examples of serial interface channels 0, 1, and 2. For details of the register formats of channels 3, 4, and 5, refer to the User’s Manual of each subseries.

197

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-1. Format of Timer Clock Select Register 3

(

µ

PD78054, 78078, 780058, 78058F, 78075B subseries,

µ

PD78070A)

Symbol 7 6 5 4 3 2 1 0

TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30

Address

FF43H

At reset

88H

R/W

R/W

TCL33 TCL32 TCL31 TCL30

0

0

1

1

1

1

1

1

Others

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8

Setting prohibited

Selects serial clock of serial interface channel 0

MCS = 1

Setting prohibited f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2

7 f

X

/2

8

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

TCL37 TCL36 TCL35 TCL34

0

0

1

1

1

1

1

1

Others

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8

Setting prohibited

Selects serial clock of serial interface channel 1

MCS = 1

Setting prohibited f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2

7 f

X

/2

8

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

Caution Before writing new data to TCL3, stop serial transfer once.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. MCS : bit 0 of oscillation mode select register (OSMS)

4. ( ) : at f

X

= 5.0 MHz

198

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-2. Format of Timer Clock Select Register 3

(

µ

PD78054Y, 78078Y, 780058Y, 78058FY, 78075BY subseries,

µ

PD78070AY)

Symbol 7 6 5 4 3 2 1 0

TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30

Address

FF43H

At reset

88H

R/W

R/W

TCL33 TCL32 TCL31 TCL30

1

1

1

1

Others

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

10 f

XX

/2

11 f

XX

/2

12

Selects serial clock of serial interface channel 0

Serial clock in I

2

C bus mode

Serial clock in 3-wire serial I/O or 2-wire serial I/O mode f

X

MCS = 1

Setting prohibited f f

X

/2 f

X

/2 f

X

/2 f

X

/2 f

X

/2

/2

6

7

8

10

11

12

Setting prohibited

X

/2

(78.1 kHz) f

X

/2

(39.1 kHz) f

X

/2

(19.5 kHz) f

X

/2

(4.88 kHz) f

X

/2

(2.44 kHz) f

X

/2

(1.22 kHz) f

X

/2

MCS = 0

6

7

8

9

(78.1 kHz) f

XX

/2

(39.1 kHz) f

XX

/2

2

(19.5 kHz) f

XX

/2

3

(9.77 kHz) f

XX

/2

4 f

X

/2

9

(9.77 kHz) f

X

/2

10

11

12

13

(4.88 kHz) f

XX

/2

5

(2.44 kHz) f

XX

/2

6

(1.22 kHz) f

XX

/2

7

(0.61 kHz) f

XX

/2

8

MCS = 1 MCS = 0

Setting prohibited f

X

/2

2

(1.25 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

TCL37 TCL36 TCL35 TCL34

1

1

1

1

1

1

0

0

Others

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8

Setting prohibited

Selects serial clock of serial interface channel 1

MCS = 1

Setting prohibited f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2

7 f

X

/2

8

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

Caution Before writing new data to TCL3, stop serial transfer once.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. MCS : bit 0 of oscillation mode select register (OSMS)

4. ( ) : at f

X

= 5.0 MHz

199

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-3. Format of Timer Clock Select Register 3 (

µ

PD78064, 780308, 78064B subseries)

Symbol

TCL3

7

1

6

0

5

0

4

0

3 2 1 0

TCL33 TCL32 TCL31 TCL30

Address

FF43H

At reset

88H

R/W

R/W

TCL33 TCL32 TCL31 TCL30

0

0

1

1

1

1

1

1

Others

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8

Setting prohibited

Selects serial clock of serial interface channel 0

MCS = 1

Setting prohibited f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2

7 f

X

/2

8

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

MCS = 0 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

Cautions 1. Clear bits 4 through 6 to 0 and set bit 7 to 1.

2. Before writing new data to TCL3, stop serial transfer once.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. MCS : bit 0 of oscillation mode select register (OSMS)

4. ( ) : at f

X

= 5.0 MHz

200

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-4. Format of Timer Clock Select Register 3 (

µ

PD78064Y, 780308Y subseries)

Symbol

TCL3

7

1

6

0

5

0

4

0

3 2 1 0

TCL33 TCL32 TCL31 TCL30

Address

FF43H

At reset

88H

R/W

R/W

TCL33 TCL32 TCL31 TCL30

1

1

1

1

Others

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

XX

/2

10 f

XX

/2

11 f

XX

/2

12

Selects serial clock of serial interface channel 0

Serial clock in I

2

C bus mode

Serial clock in 3-wire serial I/O or

2-wire serial I/O mode f

X

MCS = 1

Setting prohibited f f

X

/2 f

X

/2 f

X

/2 f

X

/2 f

X

/2

/2

6

7

8

10

11

12

Setting prohibited

X

/2

(78.1 kHz) f

X

/2

(39.1 kHz) f

X

/2

(19.5 kHz) f

X

/2

(4.88 kHz) f

X

/2

(2.44 kHz) f

X

/2

(1.22 kHz) f

X

/2

MCS = 0

6

7

8

9

(78.1 kHz) f

XX

/2

(39.1 kHz) f

XX

/2

2

(19.5 kHz) f

XX

/2

3

(9.77 kHz) f

XX

/2

4 f

X

/2

9

(9.77 kHz) f

X

/2

10

11

12

13

(4.88 kHz) f

XX

/2

5

(2.44 kHz) f

XX

/2

6

(1.22 kHz) f

XX

/2

7

(0.61 kHz) f

XX

/2

8

MCS = 1 MCS = 0

Setting prohibited f

X

/2

2

(1.25 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz)

Cautions 1. Clear bits 4 through 6 to 0 and set bit 7 to 1.

2. Before writing new data to TCL3, stop serial transfer once.

Remarks 1.

f

XX

: main system clock frequency (f

X

or f

X

/2)

2.

f

X

: main system clock oscillation frequency

3.

MCS : bit 0 of oscillation mode select register (OSMS)

4.

( ) : at f

X

= 5.0 MHz

201

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-5. Format of Timer Clock Select Register 3 (

µ

PD78098, 78098B subseries)

Symbol 7 6 5 4 3 2 1 0

TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30

Address

FF43H

At reset

88H

R/W

R/W

TCL33 TCL32 TCL31 TCL30

0

0

1

1

1

1

0

1

Selects serial clock of serial interface channel 0 f

XX

/2

Note

f

XX

/2

2

(1.0 MHz)

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1 f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz)

Others Setting prohibited

TCL37 TCL36 TCL35 TCL34

0

0

1

1

1

1

0

1

Selects serial clock of serial interface channel 1 f

XX

/2

Note

f

XX

/2

2

(1.0 MHz)

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1 f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz)

Others Setting prohibited

Note

Can be set only when the main system clock frequency is 5.0 MHz or less.

Caution Before writing new data to TCL3, stop serial transfer once.

Remarks 1. f

XX

: main system clock frequency

2. ( ) : at f

XX

= 4.0 MHz

202

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-6. Format of Timer Clock Select Register 3 (

µ

PD780018, 780018Y subseries)

Symbol 7 6 5 4

TCL3 TCL37 TCL36 TCL35 TCL34

3

1

2

0

1

0

0

0

Address

FF43H

At reset

88H

R/W

R/W

TCL37 TCL36 TCL35 TCL34

0 1 1 1

1

1

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8

Others

Selects serial clock of serial interface channel 1 f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz)

Setting prohibited

Caution Before writing new data to TCL3, stop serial transfer once.

Remarks 1. f

XX

: main system clock frequency (f

X

)

2. f

X

: main system clock oscillation frequency

3. ( ) : at f

X

= 5.0 MHz

203

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-7. Format of Serial Operating Mode Register 0

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries,

µ

PD78070A)(1/2)

Symbol 7 6 5 4 3 2 1 0

CSIM0

CSIE

0

COI WUP

CSIM

04

CSIM

03

CSIM

02

CSIM

01

CSIM

00

Address

FF60H

At reset

00H

R/W

R/W

Note 1

R/W

CSIM CSIM

01 00

0

×

Clock externally input to SCK0 pin

Selects clock of serial interface channel 0

1 0 Output of 8-bit timer register 2 (TM2)

1 1 Clock specified by bits 0 through 3 of timer clock select register 3 (TCL3)

R/W

CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27

Operation mode First bit Function of

04 03 02

Function of Function of

SI0/SB0/P25 pin SO0/SB1/P26 pin SCK0/P27 pin

0

×

0

Note 2 Note 2

0 0 0 1 3-wire serial MSB SI0

Note 2

1

1

×

I/O mode LSB (input)

SO0

(CMOS output)

SCK0

(CMOS I/O)

1 0 0

Note 3 Note 3

0 0 0 1 SBI mode

×

×

MSB P25 SB1 SCK0

(CMOS I/O) (N-ch open drain (CMOS I/O)

I / O )

P26 1 0 0

Note 3 Note 3

× ×

0 1 SB0

(N-ch open drain (CMOS I/O)

I/O)

1 1 0

Note 3 Note 3

×

×

0 0 0 1 2-wire serial MSB P25

I/O mode (CMOS I/O)

SB1 SCK0

(N-ch open drain (N-ch open drain

I/O) I/O)

1 0 0

Note 3 Note 3

×

×

0 1 SB0 P26

(N-ch open drain (CMOS I/O)

I/O)

R/W

WUP

Controls wake-up function

Note 4

0 Generates interrupt request signal in all modes each time serial transfer is executed

1 Generates interrupt request signal when address received after bus has been released (when CMDD = RELD =

1) coincides with data of slave address register in SBI mode

Notes 1. Bit 6 (COI) is a read-only bit.

2. When only the transmission function is used, this pin can be used as P25 (CMOS I/O).

3. These pins can be used as port pins.

4. When using the wake-up function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register

(SINT) to 0.

Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation.

Remark

×

: don’t care

PM

××

: Port mode register

P

××

: Output latch of port

204

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-7. Format of Serial Operating Mode Register 0

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries,

µ

PD78070A)(2/2)

R

COI

Slave address comparison result flag

Note

0 Data of slave address register does not coincide with data of serial I/O shift register

1 Data of slave address register coincides with data of serial I/O shift register

R/W

CSIE0

0 Stops operation

1 Enables operation

Note

COI is 0 when CSIE0 = 0.

Controls operation of serial interface channel 0

Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation.

205

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-8. Format of Serial Operating Mode Register 0

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (1/2)

Symbol 7 6 5 4 3 2 1 0

CSIM0

CSIE

0

COI WUP

CSIM

04

CSIM

03

CSIM

02

CSIM

01

CSIM

00

Address

FF60H

At reset

00H

R/W

R/W

Note 1

R/W

CSIM CSIM

01 00

Selects clock of serial interface channel 0

0

×

Clock externally input to SCK0/SCL pin

1 0 Output of 8-bit timer register 2 (TM2)

Note 2

1 1 Clock specified by bits 0 through 3 of timer clock select register 3 (TCL3)

R/W

CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27

Operation mode First bit

Function of

04 03 02

Function of Function of

SI0/SB0/SDA0/P25 pin SO0/SB1/SDA1/P26 pin SCK0/SCL/P27 pin

0

×

0

Note 3 Note 3

0 0 0 1 3-wire serial MSB SI0

Note 3

1

1

×

I/O mode LSB (input)

SO0

(CMOS output)

SCK0

(CMOS I/O)

1 1 0

1

Note 4 Note 4

× ×

0

0 0 0 1 2-wire serial MSB P25

I/O mode or

I

2

C bus mode

(CMOS I/O)

0

Note 4 Note 4

× ×

0 1 SB0/SDA0

(N-ch open drain (CMOS I/O)

I/O)

SB1

I/O)

P26

SCK0/SCL

(N-ch open drain (N-ch open drain

I/O)

R/W

WUP

Controls wake-up function

Note 5

0 Generates interrupt request signal in all modes each time serial transfer is executed

1 Generates interrupt request signal when address received after start condition has been detected (when CMDD

= 1) coincides with data of slave address register in I

2

C mode

Notes 1. Bit 6 (COI) is a read-only bit.

2. In the I

2

C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2

3. When only the transmission function is used, this pin can be used as P25 (CMOS I/O).

4. These pins can be used as port pins.

5. When using the wake-up function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register

(SINT) to 0. While WUP = 1, do not execute an instruction that writes data to the I/O shift register 0

(SIO0).

Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/I

2

C bus) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation.

Remark

×

: don’t care

PM

××

: Port mode register

P

××

: Output latch of port

206

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-8. Format of Serial Operating Mode Register 0

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (2/2)

R

COI

Slave address comparison result flag

Note

0 Data of slave address register does not coincide with data of serial I/O shift register

1 Data of slave address register coincides with data of serial I/O shift register

R/W

CSIE0

0 Stops operation

1 Enables operation

Note

COI is 0 when CSIE0 = 0.

Controls operation of serial interface channel 0

Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/I

2

C bus) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation.

207

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-9. Format of Serial Bus Interface Control Register

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,

78098B subseries,

µ

PD78070A) (1/2)

Symbol 7 6 5 4 3 2 1 0

SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT

Address

FF61H

At reset

00H

R/W

R/W

Note

R/W RELT Used to output bus release signal.

When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to

0. It is also cleared to 0 when CSIE = 0.

R/W CMDT Used to output command signal.

When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.

R RELD

Clear condition (RELD = 0)

• On execution of transfer start instruction

Bus release detection

Set condition (RELD = 1)

• When bus release signal (REL) is detected

• If values of SIO0 and SVA do not coincide when address is received

• When CSIE0 = 0

• At RESET input

R CMDD

Clear condition (CMDD = 0)

• On execution of transfer start instruction

Command detection

Set condition (CMDD = 1)

• When command signal (CMD) is detected

• When bus release signal (REL) is detected

• When CSIE0 = 0

• At RESET input

R/W ACKT Outputs acknowledge signal in synchronization with falling edge of SCK0 clock immediately after instruction that sets this bit to 1 has been executed. After acknowledge signal has been output, this bit is automatically cleared to 0. ACKE is cleared to 0.

This bit is also cleared to 0 when transfer of serial interface is started and when CSIE0 = 0.

Note

Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.

Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are cleared to 0 when they are read after data has been set.

2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)

208

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-9. Format of Serial Bus Interface Control Register

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,

78098B subseries,

µ

PD78070A) (2/2)

R/W ACKE

0

Controls acknowledge signal output

Disables automatic output of acknowledge signal (output by ACKT is enabled)

1 Before completion of transfer

After completion of transfer

Acknowledge signal is output in synchronization with falling edge of 9th clock of SCK0 (automatically output when ACKE = 1)

Acknowledge signal is output in synchronization with falling edge of SCK0 clock immediately after instruction that sets this bit to 1 has been executed

(automatically output when ACKE = 1). However, this bit is not automatically cleared to 0 after acknowledge signal has been output.

R ACKD

Clear condition (ACKD = 0)

Acknowledge detection

• Falling edge of SCK0 clock immediately after busy mode has been released after execution of transfer start instruction

• When CSIE0 = 0

• At RESET input

Set condition (ACKD = 1)

• When acknowledge signal (ACK) is detected at rising edge of SCK0 clock after completion of transfer

R/W

BSYE

Note

0

1

Controls output of synchronization busy signal

Disables output of busy signal in synchronization with falling edge of SCK0 clock immediately after instruction that clears this bit to 0 has been executed

Outputs busy signal at falling edge of SCK0 clock following acknowledge signal

Note

The busy mode can be released by starting serial interface transfer and receiving of an address signal.

However, the BSYE flag is not cleared to 0.

Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)

209

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-10. Format of Serial Bus Interface Control Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (1/2)

Symbol 7 6 5 4 3 2 1 0

SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT

Address

FF61H

At reset

00H

R/W

R/W

Note

R/W RELT Used to output stop condition.

When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to

0. It is also cleared to 0 when CSIE0 = 0.

R/W CMDT Used to output start condition.

When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.

R RELD

Clear condition (RELD = 0)

Stop condition detection

Set condition (RELD = 1)

• Stop condition is detected • On execution of transfer start instruction

• If values of SIO0 and SVA do not coincide when address is received

• When CSIE0 = 0

• At RESET input

R CMDD

Clear condition (CMDD = 0)

• On execution of transfer start instruction

• When stop condition is detected

Start condition detection

Set condition (CMDD = 1)

• When start condition is detected

• When CSIE0 = 0

• At RESET input

R/W ACKT Makes SDA0 (SDA1) low immediately after instruction that sets this bit to 1 (ACKT = 1) until next

SCL falls. Used to generate ACK signal by software when 8-clock wait is selected.

Cleared to 0 when transfer by serial interface is started and CSIE0 = 0

Note

Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.

Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)

210

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-10. Format of Serial Bus Interface Control Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (2/2)

R/W ACKE

0

Controls automatic output of acknowledge signal

Note 1

Disables automatic output of acknowledge signal (output by ACKT is enabled).

Used for transmission or reception with 8-clock wait selected

Note 2

.

1 Enables automatic output of acknowledge signal.

Acknowledge signal is output in synchronization with falling edge of 9th clock of SCL (automatically output when ACKE = 1). After output, this bit is not automatically cleared to 0.

Used for reception when 9-clock wait is selected.

R ACKD

Clear condition (ACKD = 0)

• On execution of transfer start instruction

• When CSIE0 = 0

• At RESET input

Acknowledge detection

Set condition (ACKD = 1)

• When acknowledge signal is detected at rising edge of SCL clock after completion of transfer

R/W

BSYE

Note 3

0

Controls transmission N-ch open drain output in I

Enables output (transmission)

2

C bus mode

Note 4

1 Disables output (reception)

Notes 1.

Set this bit before starting transfer.

2.

Output the acknowledge signal on reception by using ACKT when 8-clock wait is selected.

3.

The wait status can be released by starting transfer of serial interface or receiving an address signal.

However, BSYE is not cleared to 0.

4.

Be sure to set BSYE to 1 when using the wake-up function.

Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)

211

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-11. Format of Interrupt Timing Specification Register

(

µ

PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,

78098B subseries,

µ

PD78070A)

Symbol

SINT

7

0

6

CLD

5

SIC

4

SVAM

3

0

2

0

1

0

0

0

Address

FF63H

At reset

00H

R/W

R/W

Note 1

R/W

SVAM Bits of SVA used as slave address

0

1

Bits 0 through 7

Bits 1 through 7

R/W

SIC

Selects INTCSI0 interrupt source

Note 2

0 Sets CSIIF0 at end of transfer of serial interface channel 0

1 Sets CSIIF0 at end of transfer of serial interface channel 0 or on detection of bus release

R

CLD Level of SCK0 pin

Note 3

0

1

Low level

High level

Notes 1. Bit 6 (CLD) is a read-only bit.

2. Clear SIC to 0 when using the wake-up function in the SBI mode.

3. CLD is 0 when CSIE0 = 0.

Caution Be sure to clear bits 0 through 3 to 0.

Remark SVA : slave address register

CSIIF0 : interrupt request flag corresponding to INTCSI0

CSIE0 : bit 7 of the serial operating mode register 0 (CSIM0)

212

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-12. Format of Interrupt Timing Specification Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (1/2)

Symbol

SINT

7

0

6

CLD

5

SIC

4

SVAM

3 2 1 0

CLC WREL WAT1 WAT0

Address

FF63H

At reset

00H

R/W

R/W

Note 1

R/W WAT1 WAT0

0 0

Controls wait and interrupt processing request

Generates interrupt request at rising edge of 8th clock of SCK0 (clock output goes into high-impedance state)

0

1

1

1

0

1

Setting prohibited

Used in I

2

C bus mode (8-clock wait).

Generates interrupt processing request at rising edge of 8th clock of SCL (master makes

SCL output low and waits after outputting 8 clocks. Slave makes SCL pin low and requests for wait after inputting 8 clocks).

Used in I

2

C bus mode (9-clock wait).

Generates interrupt processing request at rising edge of 9th clock of SCL (master makes

SCL output low and waits after outputting 9 clocks. Slave makes SCL pin low and requests for wait after inputting 9 clocks).

R/W WREL

0

1

Controls wait release

Wait release status

Releases wait status.

After wait status has been released, this bit is automatically cleared to 0 (used to release wait status set by WAT1 and WAT0)

R/W CLC

0

1

Controls clock level

Note 2

Used in I

2

C bus mode.

Makes output level of SCL pin low when serial transfer is not executed

Used in I

2

C bus mode.

Makes output level of SCL pin high impedance when serial transfer is not executed (clock line goes high).

Used by master to generate start/stop condition.

Notes 1. Bit 6 (CLD) is a read-only bit.

2. Clear CLC to 0 when the I

2

C bus mode is not used.

213

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-12. Format of Interrupt Timing Specification Register

(

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries,

µ

PD78070AY) (2/2)

R/W SVAM

0 Bits 0 through 7

1 Bits 1 through 7

Bits of SVA used as slave address

R/W SIC

0

1

Selects INTCSI0 interrupt source

Note 1

Sets CSIIF0 to 1 at end of transfer of serial interface channel 0

Sets CSIIF0 to 1 at end of transfer of serial interface channel 0 or on detection of stop condition

Level of SCK0/SCL/P27 pin

Note 2

R/W CLD

0

1

Low level

High level

Notes 1. Sets SIC to 1 when using the wake-up function in the I

2

C mode.

2. CLD is 0 when CSIE0 = 0.

Remark SVA : slave address register

CSIIF0 : interrupt request flag corresponding to INTCSI0

CSIE0 : bit 7 of the serial operating mode register 0 (CSIM0)

214

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-13. Format of Serial Operating Mode Register 1

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 780058, 780058Y,

78058F, 78058FY, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

4 3 Symbol 7 6 5

CSIM1

CSIE

1

DIR ATE

0 0

2 1 0

0

CSIM CSIM

11 10

Address

FF68H

At reset

00H

R/W

R/W

CSIM CSIM

11 10

Selects clock of serial interface channel 1

0

×

Clock externally input to SCK1 pin

Note 1

1 0 Output of 8-bit timer register 2 (TM2)

1 1 Clock specified by bits 4 through 7 of timer clock select register 3 (TCL3)

ATE

0 3-wire serial I/O mode

Selects operation mode of serial interface channel 1

1 3-wire serial I/O mode with automatic transfer/reception function

DIR

0 MSB

1 LSB

First bit Function of SI1 pin

SI1/P20

(input)

Function of SO1 pin

SO1

(CMOS output)

CSIE CSIM PM20 P20 PM21 P21 PM22 P22

1 11

Operation of shift register 1

0

×

Note 2 Note 2 Note 2 Note 2 Note 2 Note 2

Stops

× ×

× ×

× × operation

1 0

Note 3 Note 3

0 0 1

×

Enables

1

× operation

1 0 1

Controls operation of counter of serial clock

Clear

Function of Function of Function of

SI1/P20 pin SO1/P21 pin SCK1/P22

P20 P21 P22

(CMOS I/O) (CMOS I/O) (CMOS I/O)

Count operation SI1

Note 3

(input)

SO1 SCK1

(CMOS output) (input)

SCK1

(CMOS output)

Notes 1. Clear bit 2 (STRB) and bit 1 (BUSY1) of the automatic data transfer/reception control register (ADTC) to 0, 0 when the external clock input is selected by clearing CSIM11 to 0.

2. These pins can be used as port pins.

3. When only transmit is executed, this pin can be used as P20 (CMOS I/O). (Set bit 7 (RE) of the automatic data transfer/reception control register (ADTC) to 0.)

Remark

×

: don’t care

PM

××

: Port mode register

P

××

: Output latch of port

215

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-14. Format of Automatic Data Transfer/Reception Control Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY,

78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

Symbol

ADTC

7

RE

6 5

ARLD ERCE

4

ERR

3 2 1 0

TRF STRB BUSY1 BUSY0

Address

FF69H

At reset

00H

R/W

R/W

Note 1

R/W

BUSY1 BUSY0

0

×

1

1

0

1

Controls busy input

Does not use busy input

Enables busy input (active high)

Enables busy input (low active)

R/W

STRB Controls strobe output

0

1

Disables strobe output

Enables strobe output

R

TRF Status of automatic transfer/reception function

Note 2

0 Detects end of automatic transfer/reception (0 when automatic transfer/reception is stopped or when ARLD

= 0)

1 Automatic transfer/reception in progress (1 when SIO1 is written)

R

ERR Detects error of automatic transfer/reception function

0 No error on automatic reception (0 when 1 is written to

SIO1)

1 Error on automatic transfer/reception

R/W

ERCE Controls error check of automatic transfer/reception function

0

1

Disables error check on automatic transfer/reception

Enables error check on automatic transfer/reception

(only when BUSY1 = 1)

R/W

ARLD Selects operation mode of automatic transfer/ reception function

0

1

Single mode

Repetitive mode

R/W

RE

0

1

Controls reception of automatic transfer/reception function

Disables reception

Enables reception

Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits.

2. Identify the end of automatic transfer/reception by using TRF instead of CSIIF1. (interrupt request flag)

Caution When external clock input is selected by clearing bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0.

Remark

×

: don’t care

216

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-15. Format of Automatic Data Transfer/Reception Control Register

(

µ

PD780058, 780058Y subseries)

Symbol

ADTC

7

RE

6 5 4

ARLD ERCE ERR

3 2 1 0

TRF STRB BUSY1 BUSY0

Address

FF69H

At reset

00H

R/W

R/W

Note 1

R/W

BUSY1 BUSY0

0

×

1 0

1 1

Controls busy input

Does not use busy input

Enables busy input (active high)

Enables busy input (low active)

R/W

STRB Controls strobe output

0 Disables strobe output

1 Enables strobe output

R

TRF Status of automatic transfer/reception function

Note 2

0 Detects end of automatic transfer/reception (0 when automatic transfer/reception is stopped or when ARLD

= 0)

1 Automatic transfer/reception in progress (1 when SIO1 is written)

R

ERR Detects error of automatic transfer/reception function

0 No error on automatic reception (0 when 1 is written to

SIO1)

1 Error on automatic transfer/reception

R/W

ERCE Controls error check of automatic transfer/reception function

0

1

Disables error check on automatic transfer/reception

Enables error check on automatic transfer/reception

(only when BUSY1 = 1)

R/W

ARLD Selects operation mode of automatic transfer/ reception function

0

1

Single mode

Repetitive mode

R/W

RE

0

1

Controls reception of automatic transfer/reception function

Disables reception

Enables reception

Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits.

2. Identify the end of automatic transfer/reception by using TRF instead of CSIIF1. (interrupt request flag)

Cautions 1. When external clock input is selected by clearing bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0.

2. When using the P23/STB/TxD1 and P24/BUSY/RxD1 pins in the asynchronous serial interface

(UART) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid.

Remark

×

: don’t care

217

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) (1/4)

Symbol 7

ADTI ADTI7

6

0

5

0

4 3 2

1 0

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

Address

FF6BH

At reset

00H

R/W

R/W

ADTI7

0

Controls interval time of data transfer

Does not control interval time by ADTI

Note 1

1 Controls interval time by ADTI (ADTI0 through ADTI4)

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 5.0 MHz)

Minimum value

Note 2

18.4

µ s + 0.5/f

SCK

31.2

µ s + 0.5/f

SCK

44.0

µ s + 0.5/f

SCK

56.8

µ s + 0.5/f

SCK

69.6

µ s + 0.5/f

SCK

82.4

µ s + 0.5/f

SCK

95.2

µ s + 0.5/f

SCK

108.0

µ s + 0.5/f

SCK

120.8

µ s + 0.5/f

SCK

133.6

µ s + 0.5/f

SCK

146.4

µ s + 0.5/f

SCK

159.2

µ s + 0.5/f

SCK

172.0

µ s + 0.5/f

SCK

184.8

µ s + 0.5/f

SCK

197.6

µ s + 0.5/f

SCK

210.4

µ s + 0.5/f

SCK

Maximum value

20.0

µ s + 1.5/f

SCK

32.8

µ s + 1.5/f

SCK

45.6

µ s + 1.5/f

SCK

58.4

µ s + 1.5/f

SCK

71.2

µ s + 1.5/f

SCK

84.0

µ s + 1.5/f

SCK

96.8

µ s + 1.5/f

SCK

109.6

µ s + 1.5/f

SCK

122.4

µ s + 1.5/f

SCK

135.2

µ s + 1.5/f

SCK

148.0

µ s + 1.5/f

SCK

160.8

µ s + 1.5/f

SCK

173.6

µ s + 1.5/f

SCK

186.4

µ s + 1.5/f

SCK

199.2

µ s + 1.5/f

SCK

212.0

µ s + 1.5/f

SCK

Note 2

Notes 1. The interval time is dependent on only the CPU processing.

2. The interval time of data transfer includes an error. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ + f

XX

28 f

XX

0.5

f

SCK

Maximum value = (n+1)

×

2

6

+ + f

XX f

36

XX

1.5

f

SCK

218

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Cautions 1. Do not write ADTI during automatic transmission/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1.

f

XX

: main system clock frequency (f

X

or f

X

/2)

2.

f

X

: main system clock oscillation frequency

3.

f

SCK

: serial clock frequency

219

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) (2/4)

Symbol 7

ADTI ADTI7

6

0

5

0

4 3 2

ADTI4 ADTI3 ADTI2

1 0

ADTI1 ADTI0

Address

FF6BH

At reset

00H

R/W

R/W

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 5.0 MHz)

Minimum value

Note

223.2

µ s + 0.5/f

SCK

236.0

µ s + 0.5/f

SCK

248.8

µ s + 0.5/f

SCK

261.6

µ s + 0.5/f

SCK

274.4

µ s + 0.5/f

SCK

287.2

µ s + 0.5/f

SCK

300.0

µ s + 0.5/f

SCK

312.8

µ s + 0.5/f

SCK

325.6

µ s + 0.5/f

SCK

338.4

µ s + 0.5/f

SCK

351.2

µ s + 0.5/f

SCK

364.0

µ s + 0.5/f

SCK

376.8

µ s + 0.5/f

SCK

389.6

µ s + 0.5/f

SCK

402.4

µ s + 0.5/f

SCK

415.2

µ s + 0.5/f

SCK

Maximum value

224.8

µ s + 1.5/f

SCK

237.6

µ s + 1.5/f

SCK

250.4

µ s + 1.5/f

SCK

263.2

µ s + 1.5/f

SCK

276.0

µ s + 1.5/f

SCK

288.8

µ s + 1.5/f

SCK

301.6

µ s + 1.5/f

SCK

314.4

µ s + 1.5/f

SCK

327.2

µ s + 1.5/f

SCK

340.0

µ s + 1.5/f

SCK

352.8

µ s + 1.5/f

SCK

365.6

µ s + 1.5/f

SCK

378.4

µ s + 1.5/f

SCK

391.2

µ s + 1.5/f

SCK

404.0

µ s + 1.5/f

SCK

416.8

µ s + 1.5/f

SCK

Note

Note

The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ f

XX

28 f

XX

0.5

+ f

SCK

Maximum value = (n+1)

×

2

6

+ f

XX

36 f

XX

+

1.5

f

SCK

Cautions 1. Do not write ADTI during automatic transfer/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1.

f

XX

: main system clock frequency (f

X

or f

X

/2)

2.

f

X

: main system clock oscillation frequency

3.

f

SCK

: serial clock frequency

220

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) (3/4)

Symbol 7

ADTI ADTI7

6

0

5

0

4 3 2 1 0

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

Address

FF6BH

ADTI7

0

Controls interval time of data transfer

Does not control interval time by ADTI

Note 1

1 Controls interval time by ADTI (ADTI0 through ADTI4)

At reset

00H

R/W

R/W

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 2.5 MHz)

Minimum value

Note 2

36.8

µ s + 0.5/f

SCK

62.4

µ s + 0.5/f

SCK

88.0

µ s + 0.5/f

SCK

113.6

µ s + 0.5/f

SCK

139.2

µ s + 0.5/f

SCK

164.8

µ s + 0.5/f

SCK

190.4

µ s + 0.5/f

SCK

216.0

µ s + 0.5/f

SCK

241.6

µ s + 0.5/f

SCK

267.2

µ s + 0.5/f

SCK

292.8

µ s + 0.5/f

SCK

318.4

µ s + 0.5/f

SCK

344.0

µ s + 0.5/f

SCK

369.6

µ s + 0.5/f

SCK

395.2

µ s + 0.5/f

SCK

420.8

µ s + 0.5/f

SCK

Maximum value

40.0

µ s + 1.5/f

SCK

65.6

µ s + 1.5/f

SCK

91.2

µ s + 1.5/f

SCK

116.8

µ s + 1.5/f

SCK

142.4

µ s + 1.5/f

SCK

168.0

µ s + 1.5/f

SCK

193.6

µ s + 1.5/f

SCK

219.2

µ s + 1.5/f

SCK

244.8

µ s + 1.5/f

SCK

270.4

µ s + 1.5/f

SCK

296.0

µ s + 1.5/f

SCK

321.6

µ s + 1.5/f

SCK

347.2

µ s + 1.5/f

SCK

372.8

µ s + 1.5/f

SCK

398.4

µ s + 1.5/f

SCK

424.0

µ s + 1.5/f

SCK

Note 2

Notes 1. The interval time is dependent on only the CPU processing.

2. The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ + f

XX

28 f

XX

0.5

f

SCK

Maximum value = (n+1)

×

2

6

+ + f

XX

36 f

XX

1.5

f

SCK

221

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Cautions 1. Do not write ADTI during automatic transfer/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1.

f

XX

: main system clock frequency (f

X

or f

X

/2)

2.

f

X

: main system clock oscillation frequency

3.

f

SCK

: serial clock frequency

222

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F,

78058FY, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY) (4/4)

Symbol 7

ADTI ADTI7

6

0

5

0

4

ADTI4

3 2 1

ADTI3 ADTI2 ADTI1

0

ADTI0

Address

FF6BH

At reset

00H

R/W

R/W

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 2.5 MHz)

Minimum value

Note

446.4

µ s + 0.5/f

SCK

472.0

µ s + 0.5/f

SCK

497.6

µ s + 0.5/f

SCK

523.2

µ s + 0.5/f

SCK

548.8

µ s + 0.5/f

SCK

574.4

µ s + 0.5/f

SCK

600.0

µ s + 0.5/f

SCK

625.6

µ s + 0.5/f

SCK

651.2

µ s + 0.5/f

SCK

676.8

µ s + 0.5/f

SCK

702.4

µ s + 0.5/f

SCK

728.0

µ s + 0.5/f

SCK

753.6

µ s + 0.5/f

SCK

779.2

µ s + 0.5/f

SCK

804.8

µ s + 0.5/f

SCK

830.4

µ s + 0.5/f

SCK

Maximum value

449.6

µ s + 1.5/f

SCK

475.2

µ s + 1.5/f

SCK

500.8

µ s + 1.5/f

SCK

526.4

µ s + 1.5/f

SCK

552.0

µ s + 1.5/f

SCK

577.6

µ s + 1.5/f

SCK

603.2

µ s + 1.5/f

SCK

628.8

µ s + 1.5/f

SCK

654.4

µ s + 1.5/f

SCK

680.0

µ s + 1.5/f

SCK

705.6

µ s + 1.5/f

SCK

731.2

µ s + 1.5/f

SCK

756.8

µ s + 1.5/f

SCK

782.4

µ s + 1.5/f

SCK

808.0

µ s + 1.5/f

SCK

833.6

µ s + 1.5/f

SCK

Note

Note

The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ + f

XX f

28

XX

0.5

f

SCK

Maximum value = (n+1)

×

2

6

+ + f

XX f

36

XX

1.5

f

SCK

Cautions 1. Do not write ADTI during automatic transfer/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. f

SCK

: serial clock frequency

223

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-17. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78098, 78098B subseries) (1/2)

Symbol 7

ADTI ADTI7

6

0

5

0

4 3 2 1 0

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

Address

FF6BH

ADTI7

0

Controls interval time of data transfer

Does not control interval time by ADTI

Note 1

1 Controls interval time by ADTI (ADTI0 through ADTI4)

At reset

00H

R/W

R/W

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 4.0 MHz)

Minimum value

Note 2

23.0

µ s + 0.5/f

SCK

39.0

µ s + 0.5/f

SCK

55.0

µ s + 0.5/f

SCK

71.0

µ s + 0.5/f

SCK

87.0

µ s + 0.5/f

SCK

103.0

µ s + 0.5/f

SCK

119.0

µ s + 0.5/f

SCK

135.0

µ s + 0.5/f

SCK

151.0

µ s + 0.5/f

SCK

167.0

µ s + 0.5/f

SCK

183.0

µ s + 0.5/f

SCK

199.0

µ s + 0.5/f

SCK

215.0

µ s + 0.5/f

SCK

231.0

µ s + 0.5/f

SCK

247.0

µ s + 0.5/f

SCK

263.0

µ s + 0.5/f

SCK

Maximum value

25.0

µ s + 1.5/f

SCK

41.0

µ s + 1.5/f

SCK

57.0

µ s + 1.5/f

SCK

73.0

µ s + 1.5/f

SCK

89.0

µ s + 1.5/f

SCK

105.0

µ s + 1.5/f

SCK

121.6

µ s + 1.5/f

SCK

137.0

µ s + 1.5/f

SCK

153.0

µ s + 1.5/f

SCK

169.0

µ s + 1.5/f

SCK

185.0

µ s + 1.5/f

SCK

201.0

µ s + 1.5/f

SCK

217.0

µ s + 1.5/f

SCK

233.0

µ s + 1.5/f

SCK

249.0

µ s + 1.5/f

SCK

265.0

µ s + 1.5/f

SCK

Note 2

Notes 1. The interval time is dependent on only the CPU processing.

2. The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ + f

XX

28 f

XX

0.5

f

SCK

Maximum value = (n+1)

×

2

6

+ + f

XX

36 f

XX

1.5

f

SCK

224

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Cautions 1. Do not write ADTI during automatic transfer/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1. f

XX

: main system clock frequency

2. f

SCK

: serial clock frequency

225

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-17. Format of Automatic Data Transfer/Reception Interval Specification Register

(

µ

PD78098, 78098B subseries) (2/2)

Symbol 7

ADTI ADTI7

6

0

5

0

4 3 2 1 0

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

Address

FF6BH

At reset

00H

R/W

R/W

ADTI4 ADTI3 ADTI2 ADTI1 ADTI0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Specifies interval time of data transfer (f

XX

= 4.0 MHz)

Minimum value

Note

279.0

µ s + 0.5/f

SCK

295.0

µ s + 0.5/f

SCK

311.0

µ s + 0.5/f

SCK

327.0

µ s + 0.5/f

SCK

343.0

µ s + 0.5/f

SCK

359.0

µ s + 0.5/f

SCK

375.0

µ s + 0.5/f

SCK

391.0

µ s + 0.5/f

SCK

407.0

µ s + 0.5/f

SCK

423.0

µ s + 0.5/f

SCK

439.0

µ s + 0.5/f

SCK

455.0

µ s + 0.5/f

SCK

471.0

µ s + 0.5/f

SCK

487.0

µ s + 0.5/f

SCK

503.0

µ s + 0.5/f

SCK

519.0

µ s + 0.5/f

SCK

Maximum value

281.0

µ s + 1.5/f

SCK

297.0

µ s + 1.5/f

SCK

313.0

µ s + 1.5/f

SCK

329.0

µ s + 1.5/f

SCK

345.0

µ s + 1.5/f

SCK

361.0

µ s + 1.5/f

SCK

377.0

µ s + 1.5/f

SCK

393.0

µ s + 1.5/f

SCK

409.0

µ s + 1.5/f

SCK

425.0

µ s + 1.5/f

SCK

441.0

µ s + 1.5/f

SCK

457.0

µ s + 1.5/f

SCK

473.0

µ s + 1.5/f

SCK

489.0

µ s + 1.5/f

SCK

505.0

µ s + 1.5/f

SCK

521.0

µ s + 1.5/f

SCK

Note

Note

The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/f

SCK

, the minimum interval time is 2/f

SCK

.

Minimum value = (n+1)

×

2

6

+ + f

XX

28 f

XX

0.5

f

SCK

Maximum value = (n+1)

×

2

6

+ + f

XX

36 f

XX

1.5

f

SCK

Cautions 1. Do not write ADTI during automatic transfer/reception operation.

2. Be sure to clear bits 5 and 6 to 0.

3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid.

Remarks 1. f

XX

: main system clock frequency

2. f

SCK

: serial clock frequency

226

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-18. Format of Serial Operating Mode Register 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

Symbol 7

CSIM2 CSIE2

6

0

5

0

4

0

3

0

2 1

CSIM22

CSCK

0

0

Address

FF72H

At reset

00H

R/W

R/W

CSCK Selects clock in 3-wire serial I/O mode

0 Clock externally input to SCK2 pin

1 Output of dedicated baud rate generator

CSIM22

0

1

Specifies first bit

MSB

LSB

CSIE2 Controls operation in 3-wire serial I/O mode

0

1

Stops operation

Enables operation

Cautions 1. Be sure to clear bits 0 and 3 through 6 to 0.

2. Set CSIM2 to 00H in the UART mode.

227

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-19. Format of Asynchronous Serial Interface Mode Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

Symbol

ASIM

7

TXE

6

RXE

5

PS1

4

PS0

3

CL

2

SL

1

ISRM

0

SCK

Address

FF70H

At reset

00H

R/W

R/W

SCK Selects clock of asynchronous serial interface mode

0

1

Clock externally input to ASCK pin

Output of dedicated baud rate generator

Note

ISRM Controls receive end interrupt on occurrence of error

0

1

Generates receive end interrupt request when error occurs

Does not generate receive end interrupt request when error occurs

SL

0

1

Specifies stop bit length of transmit data

1 bit

2 bits

CL

0

1

Specifies character length

7 bits

8 bits

PS1

0

0

1

1

PS0

0

1

0

1

Specifies parity bit

No parity

Always append 0 parity during transmission.

Does not check parity during reception (does not generate parity error)

Odd parity

Even parity

RXE Controls reception operation

0

1

Stops reception operation

Enables reception operation

TXE Controls transmission operation

0

1

Stops transmission operation

Enables transmission operation

Note

When the baud rate generator output is selected by setting SCK to 1, the ASCK pin can be used as an

I/O port pin.

Cautions 1. Set ASIM to 00H when the 3-wire serial I/O mode is selected.

2. Before changing the operation mode, stop the serial transfer/reception operation.

228

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Table 8-4. Setting of Operation Modes of Serial Interface Channel 2

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 78058F, 78058FY,

78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

(1) Operation stop mode

ASIM CSIM2

TXE RXE SCK CSIE2CSIM22 CSCK

PM70 P70 PM71 P71 PM72 P72 First Shift Function of Function of Function of bit clock P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK pin pin pin

0 0

×

0

× × ×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

– – P70 P71 P72

Others Setting prohibited

(2) 3-wire serial I/O mode

ASIM CSIM2

TXE RXE SCK CSIE2CSIM22 CSCK

PM70 P70 PM71 P71 PM72 P72 First Shift Function of Function of Function of bit clock P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK

0 0 0 1 0 0 1

Note 2

×

Note 2

0 1 1 pin pin

×

MSB External SI2

Note 2

SO2 clock (CMOS output) pin

SCK2 input

1 0

Others

1 1 0

1

1

0

1 Internal

Internal clock

SCK2 output clock

×

LSB External SI2

Note 2

SO2 clock (CMOS output)

SCK2 input

1 SCK2 output

Setting prohibited

(3) Asynchronous serial interface mode

ASIM CSIM2

TXE RXE SCK CSIE2CSIM22 CSCK

PM70 P70 PM71 P71 PM72 P72 First Shift Function of Function of Function of bit clock P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK pin pin

1

0

1

Others

0

1

1

0

1

0

1

0

1

0

0

0

0

0

0 pin

0

×

Note 1

0 1

×

Note 1

0 1

× ×

Note 1

×

Note 1

1

×

LSB External P70 clock

×

Note 1

×

Note 1

Internal clock

1

×

External RxD clock

×

Note 1

×

Note 1

Internal clock

0 1

×

0 1 1

×

External clock

×

Note 1

×

Note 1

Internal clock

Setting prohibited

TxD

(CMOS output)

P71

TxD

(CMOS output)

ASCK input

P72

ASCK input

P72

ASCK input

P72

Notes 1. These pins can be used as port pins.

2. This pin can be used as P70 (CMOS I/O) when only transmission is executed.

Remark

×

: don’t care

PM

××

: port mode register

P

××

: output latch of port

229

Table 8-5. Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780058 and 780058Y Subseries) (1/2)

(1) Operation stop mode

ASIM CSIM2 SIPS

PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72

TXE RXE SCK

CSIE2 CSIM22 CSCK SIPS21 SIPS20

0 0

×

0

× ×

× ×

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

Others

First bit

Shift clock

Function of Function of Function of

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin

P70

Setting prohibited

Function of

P71

Function of

P23/STB P24/BUSY P72

(2) 3-wire serial I/O mode

ASIM CSIM2 SIPS

PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72

TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20

0 0 0 1 0 0

× ×

1

Note 2

×

Note 2

0 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

1

×

Others

1 1

1

0

1

0

1

0

1

×

1

First Shift Function of Function of Function of Function of Function of bit

MSB

LSB clock

External clock

Internal clock

External clock

Internal clock

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin

SI2

Note 2

SI2

Note 2

SO2

(CMOS output)

SO2

(CMOS output)

P23/STB P24/BUSY SCK2 input

SCK2 output

SCK2 input

SCK2 output

Setting prohibited

Notes 1. These pins can be used as port pins.

2. This pin can be used as P70 (CMOS I/O) when only transmission is executed.

Remark

×

: don’t care

PM

××

: port mode register

P

××

: output latch of port

Table 8-5. Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780058 and 780058Y Subseries) (2/2)

(3) Asynchronous serial interface mode

0

1

1

0

1

ASIM

1

1

0

1

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

CSIM2

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

SIPS

0

0

0

1

1

PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72

TXE RXE SCK CSIE2 CSIM22 CSCK

SIPS21 SIPS20

1 0 0 0 0 0 0 0

×

Note

×

Note

1

1

×

Note

×

Note

1

1

0 1

×

Note

×

Note

×

Note

×

Note

× ×

Note

×

Note

×

Note

×

Note

×

Note

×

Note

×

× ×

Note

×

Note

×

Note

×

Note

×

0

0

0

1

×

Note

×

Note

×

Note

×

Note

1

1

0

0

1

×

Note

×

Note

1

1

1

×

×

1

1

1

1

×

×

Note

×

Note

×

Note

×

Note

×

×

Note

×

Note

×

Note

×

Note

1

×

×

Note

×

Note

1

×

×

×

×

Note

×

Note

First Shift bit

LSB clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

Function of Function of Function of Function of Function of

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin

P70

RxD0

P70

P70

(input)

P70

(input)

TxD0

(CMOS output)

P71

TxD0

(CMOS output)

Output high

P71

Output high

P23/STB

TxD1

P23/STB

TxD1

P24/BUSY

P24/BUSY

RxD1

RxD1

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

Others Setting prohibited

Note

These pins can be used as port pins.

Remark

×

: don’t care

PM

××

: port mode register

P

××

: output latch of port

Table 8-6. Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780308 and 780308Y Subseries) (1/2)

(1) Operation stop mode

ASIM CSIM2 SIPS

PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72

TXE RXE SCK

CSIE2 CSIM22 CSCK SIPS21 SIPS20

0 0

×

0

× × × ×

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

Others

First Shift bit

– clock

Function of

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P113/TxD pin

P70

Setting prohibited

Function of

P71

Function of

P113

Function of

P114/RxD pin

P114

Function of

P72/SCK2/ASCK pin

P72

(2) 3-wire serial I/O mode

ASIM CSIM2 SIPS

PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72

TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20

0 0 0 1 0 0

× ×

1

Note 2

×

Note 2

0 1

×

Note 1

×

Note 1

×

Note 1

×

Note 1

1

×

Others

1 1

1

0

1

0

1

0

1

×

1

First Shift

Function of Function of Function of Function of Function of bit

MSB

LSB clock

External clock

Internal clock

External clock

Internal clock

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P113/TxD pin P114/RxD pin P72/SCK2/ASCK pin

SI2

Note 2

SI2

Note 2

Setting prohibited

SO2

(CMOS output)

SO2

(CMOS output)

P113 P114 SCK2 input

SCK2 output

SCK2 input

SCK2 output

Notes 1. These pins can be used as port pins.

2. This pin can be used as P70 (CMOS I/O) when only transmission is executed.

Remark

×

: don’t care

PM

××

: port mode register

P

××

: output latch of port

Table 8-6. Setting of Operation Modes of Serial Interface Channel 2 (

µ

PD780308 and 780308Y Subseries) (2/2)

(3) Asynchronous serial interface mode

ASIM CSIM2 SIPS

PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72

TXE RXE SCK CSIE2 CSIM22 CSCK

SIPS21 SIPS20

1 0 0 0 0 0 0 0

×

Note

×

Note

0 1

×

Note

×

Note

×

Note

×

Note

1

×

0

1

1

0

1

1

1

0

1

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

1

1

1

1

× ×

Note

×

Note

×

Note

×

Note

×

Note

×

Note

×

Note

×

Note

1

1

×

1

×

Note

×

Note

×

Note

×

Note

× ×

Note

×

Note

×

Note

×

Note

×

0

0

0

1

1

0

0

1

1

×

Note

×

Note

1

1

×

×

×

Note

×

Note

1

×

×

Note

×

Note

1

×

Note

×

Note

1

×

×

Note

×

Note

1

×

Note

×

Note

1

×

×

×

×

Note

×

Note

First Shift bit

LSB

Function of Function of Function of Function of Function of clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

External clock

Internal clock

P70/SI2/RxD0 pin P71/SO2/TxD0 pin P113/TxD pin P114/RxD pin P72/SCK2/ASCK pin

P70

RxD

P70

P70

(input)

P70

(input)

TxD

(CMOS output)

P71

TxD

(CMOS output)

Output high

P71

Output high

P113

TxD

P113

TxD

P114

P114

RxD

RxD

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

ASCK input

P72

Others Setting prohibited

Note

These pins can be used as port pins.

Remark

×

: don’t care

PM

××

: port mode register

P

××

: output latch of port

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-20. Format of Asynchronous Serial Interface Status Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

Symbol

ASIS

7

0

6

0

5

0

4

0

3

0

2

PE

1

FE

0

OVE

Address

FF71H

At reset

00H

R/W

R

OVE Overrun error flag

0

1

Overrun error does not occur

Overrun error occurs

Note 1

(if next reception operation is completed before data is read from receive buffer register)

FE

0

1

Framing error flag

Framing error does not occur

Framing error occurs

Note 2

(if stop bit is not detected)

PE

0

1

Parity error flag

Parity error does not occur

Parity error occurs (if parity of transmit data does not coincide)

Notes 1. If an overrun error occurs, be sure to read the receive buffer register (RXB). The overrun error persists each time data is received until RXB is read.

2. Even if the stop bit length is set to 2 bits by the bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only 1 stop bit is detected during reception.

234

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-21. Format of Baud Rate Generator Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) (1/2)

Symbol

BRGC

7 6

TPS3 TPS2

5 4 3 2 1 0

TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

Address

FF73H

At reset

00H

R/W

R/W

1

1

1

1

1

1

1

0

1

0

0

0

0

MDL3 MDL2 MDL1 MDL0

0 0 0 0

0

0

0

0

0

1

1

0

0

1

1

1

1

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

0 f

SCK

/23 f

SCK

/24 f

SCK

/25 f

SCK

/26 f

SCK

/27 f

SCK

/28 f

SCK

/29 f

SCK

/30 f

SCK

Note

f

SCK

/16

Selects input clock of baud rate generator f

SCK

/17 f

SCK

/18 f

SCK

/19 f

SCK

/20 f

SCK

/21 f

SCK

/22

11

12

13

14

9

10

7

8

5

6

3

4

1

2 k

0

Note

Can be used only in the 3-wire serial I/O mode.

Remarks 1. f

SCK

: source clock of 5-bit counter

2. k : value set by MDL0 through MDL3 (0

k

14)

235

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-21. Format of Baud Rate Generator Control Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308,

780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A,

78070AY) (2/2)

n TPS3 TPS2 TPS1 TPS0

1

1

1

1

0

0

0

0

1

1

1

Others

0

0

0

0

1

1

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0 f

XX

/2

10 f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XX

/2

8 f

XX

/2

9 f

Selects source clock of 5-bit counter

MCS = 1 f

X

/2

10

(4.9 kHz) f

X

(5.0 MHz)

MCS = 0 f

X

/2

11

(2.4 kHz)

X

/2 (2.5 MHz) f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5 f

X

/2

6 f

X

/2

7 f

X

/2

8 f

X

/2

9

(1.25 MHz)

(625 kHz)

(313 kHz)

(156 kHz)

(78.1 kHz)

(39.1 kHz)

(19.5 kHz)

(9.8 kHz) f

X

/2 (2.5 MHz) f

X

/2

2

(1.25 MHz) f

X

/2

3

(625 kHz) f

X

/2

4

(313 kHz) f

X

/2

5

(156 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

9

(9.8 kHz) f

X

/2

10

(4.9 kHz)

Setting prohibited

6

7

4

5

2

3

11

1

8

9

10

Caution If data is written to BRGC during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally.

Therefore, do not write data to BRGC during communication.

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. MCS : bit 0 of oscillation mode select register (OSMS)

4. n : value set by TPS0 through TPS3 (1

n

11)

5. ( ) : at f

X

= 5.0 MHz

236

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-22. Format of Baud Rate Generator Control Register (

µ

PD78098, 78098B subseries) (1/2)

Symbol

BRGC

7

TPS3

6

TPS2

5

TPS1

4 3 2 1 0

TPS0 MDL3 MDL2 MDL1 MDL0

Address

FF73H

At reset

00H

1

1

1

1

1

1

1

0

1

0

0

0

0

MDL3 MDL2 MDL1 MDL0

0 0 0 0

0

0

0

0

0

1

1

0

0

1

1

1

1

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

0 f

SCK

/23 f

SCK

/24 f

SCK

/25 f

SCK

/26 f

SCK

/27 f

SCK

/28 f

SCK

/29 f

SCK

/30 f

SCK

Note

f

SCK

/16

Selects input clock of baud rate generator f

SCK

/17 f

SCK

/18 f

SCK

/19 f

SCK

/20 f

SCK

/21 f

SCK

/22

R/W

R/W

11

12

13

14

9

10

7

8

5

6

3

4

1

2 k

0

Note

Can be used only in the 3-wire serial I/O mode.

Remarks 1. f

SCK

: source clock of 5-bit counter

2. k : value set by MDL0 through MDL3 (0

k

14)

237

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-22. Format of Baud Rate Generator Control Register (

µ

PD78098, 78098B subseries) (2/2)

1

1

1

1

1

1

0

1

TPS3 TPS2 TPS1 TPS0

0 0 0 0

0

0

1

1

0

1

1

0

1

0

0

0

1

0

0

1

1

0

1

0

1

1

0

1

0

1

1

0

1

0

1

0 f

XX

/2

10

(3.91 kHz)

Selects source clock of 5-bit counter f

XX

(4.0 MHz) f

XX

/2 (2.0 MHz) f

XX

/2

2

(1.0 MHz) f

XX

/2

3

(500 kHz) f

XX

/2

4

(250 kHz) f

XX

/2

5

(125 kHz) f

XX

/2

6

(62.5 kHz) f

XX

/2

7

(31.3 kHz) f

XX

/2

8

(15.6 kHz) f

XX

/2

9

(7.81 kHz)

Others Setting prohibited

5

6

3

4

1

2 n

11

7

8

9

10

Caution If data is written to BRGC during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally.

Therefore, do not write data to BRGC during communication.

Remarks 1. f

XX

: main system clock frequency

2. n : value set by TPS0 through TPS3 (1

n

11)

3. ( ) : at f

XX

= 4.0 MHz

238

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-23. Format of Serial Interface Pin Select Register

(

µ

PD780058 and 780058Y Subseries)

Symbol

SIPS

7

0

6

0

5 4

SIPS21 SIPS20

3

0

2

0

1

0

0

0

Address

FF75H

At reset

00H

R/W

R/W

SIPS21 SIPS20

0 0

0

1

1

1

0

1

Selects I/O pin of asynchronous serial interface

Input pin : RxD0/SI2/P70

Output pin : TxD0/SO2/P71

Input pin : RxD1/BUSY/P24

Output pin : TxD0/SO2/P71

Input pin : RxD0/SI2/P70

Output pin : TxD1/STB/P23

Input pin : RxD1/BUSY/P24

Output pin : TxD1/STB/P23

Cautions 1. Change the mode of an I/O Pin after stopping the serial transfer/reception operation.

2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transfer/reception function of the serial interface channel 1, the RxD1/

BUSY/P24 and TxD1/STB/P23 pins cannot be used as data I/O pins.

Figure 8-24. Format of Serial Interface Pin Select Register

(

µ

PD780308 and 780308Y Subseries)

Symbol

SIPS

7

0

6

0

5 4

SIPS21 SIPS20

3

0

2

0

1

0

0

0

Address

FF75H

At reset

00H

R/W

R/W

SIPS21 SIPS20

0 0

0

1

1

1

0

1

Selects I/O pin of asynchronous serial interface

Input pin : RxD/SI2/P70

Output pin : TxD/SO2/P71

Input pin : RxD/P114

Output pin : TxD/SO2/P71

Input pin : RxD0/SI2/P70

Output pin : TxD/P113

Input pin : RxD/P114

Output pin : TxD/P113

Cautions 1. Change the mode of an I/O Pin after stopping the serial transfer/reception operation.

2. Port 11 has a falling edge detection function. Do not input a falling edge to the pin used as a multiplexed pin of this port.

239

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.1 Interface with EEPROM

TM

(

µ

PD6252)

The

µ

PD6252

Note

is a 2048-bit EEPROM which can be electrically written or erased. To write or read data to or from the

µ

PD6252, the 3-wire serial interface is used.

Note

µ

PD6252 is for maintenance use.

Figure 8-25. Pin Configuration of

µ

PD6252

CE

IC

IC

GND

1

2

3

4

8

7

6

5

V

DD

CS

SCL

SDA

240

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Pin Number Pin Name I/O

1 CE CMOS input

Table 8-7. Pin Function of

µ

PD6252

Function

Keep this pin high during data transfer.

IC –

Caution Do not change the level of this pin from high to low during data transfer.

To change the level of this pin from high to low, make sure that the CS pin (pin 7) is low. By making both the CE and CS pins low, you can set the standby status in which the power consumption is reduced.

Fix the IC pins to the high or low level via resistor.

4

5

2

3

GND

SDA

– Ground

CMOS input/ Data input/output pin.

N-ch open-drain Because this pin is an N-ch open-drain I/O pin, externally pull it up with a resistor.

output

SDA

6

7

8

SCL

CS

V

DD

CMOS input

CMOS input

Inputs a clock for data transfer.

Chip select pin. When this pin is high, the

µ

PD6252 is enabled to operate.

When it is low, memory cells cannot be read or written.

When the level of this pin is changed from high to low with the SCL pin high, the operation of the serial bus interface is started. To end the operation of the serial bus interface, change the level of this pin from high to low.

Positive power: +5 V

±

10%

241

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.1.1 Communication in 2-wire serial I/O mode

The 3-wire mode of the

µ

PD6252

Note

is implemented by serial clock (SCL), data (SDA), and chip select (CS) lines.

Excluding the handshaking line, therefore, only two lines, clock and data lines, are necessary for interfacing. To interface the

µ

PD6252 with a 78K/0 series microcontroller, the 2-wire serial I/O mode is used. In the example shown in this section, the

µ

PD78054 subseries is used.

Note

µ

PD6252 is for maintenance use.

Figure 8-26. Example of Connection of

µ

PD6252

µ

PD78054

V

DD

µ

PD6252

V

DD

SCK0

SB1

P32

SCL CE

SDA

CS

Table 8-8 and Figure 8-27 shows the commands to write and read data to/from the

µ

PD6252 and communication format.

Table 8-8.

µ

PD6252 Commands

Command Name Command Operation

RANDOM WRITE 00000000B [00H] Transfers write data after setting an 8-bit word address (WA). Up to 3 bytes of write

MSB data can be set successively.

C

7

-C

0

Correspondence between word address and data

WA Data of first byte

WA+1 Data of second byte

WA+2 Data of third byte

The write operation is executed in the internal write cycle after the CS pin has gone low.

CURRENT READ 10000000B [80H] Transfers the contents of memory specified by the word address (WA) (current

MSB address) specified when the command is set, to the read data buffer. Each time 8

C

7

-C

0 bits of data have been read from the SDA pin, the word address (WA) is incremented, and the corresponding memory contents are transferred to the data buffer.

RANDOM READ 11000000B [C0H] Executes data read starting from a set word address (WA) after the word address has

MSB been set.

C

7

-C

0

The difference from CURRENT READ is that this command sets a word address (WA) after it has been executed.

After the word address has been set, this command performs the same operation as

CURRENT READ.

242

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-27. Communication Format of

µ

PD6252

(1) RANDOM WRITE

WA input

CS

Command input Write data input (WA) (WA + 1) (WA + 2)

SDA

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

0 0 0 0 0 0 0 0

WB flag output WA

7

WA

6

WA

5

WA

4

WA

3

WA

2

WA

1

WA

0

D

7

D

6

D

5

D

4

D

3

1st byte

D

2

D

1

D

0

2nd byte 3rd byte

SCL

Internal WA

SDA mode

IN

Starts by making CS pin high when SCL pin is high

(issuance of STA).

CURRENT ADDRESS

OUT IN

WA

WA retains input value until STP is detected, and is incremented each time

1 byte is written in the internal write cycle after STP has been detected.

WB flag is retained while eight clocks are input to SCL pin.

WA + 1 to WA + 3

Data of 1st byte is written to memory addressed by WA.

(2) CURRENT READ

Write is executed by making CS in low with SCL pin high.

WA is last written address + 1 and is retained

(current address) (issuance of STP).

Current address

CS

SDA

C

7

Command input

C

6

C

5

C

4

C

3

C

2

C

1

C

0

1 0 0 0 0 0 0 0

WB flag output D

7

Read data (WA)

D

6

D

5

D

4

D

3

D

2

D

1

D

0

(WA + 1) (WA + 2) (WA + n)

D

7

D

6

D

0

D

7

D

6

D

2

D

1

D

0

SCL

Internal WA

SDA mode

IN

CURRENT ADDRESS = WA

OUT

WA+1

OUT

WA+2 WA+n

Operation ends by making CS pin high with

SCL pin high. WA is last read address + 1 and retained (current address) (issuance of STP)

WA + n + 1

(3) RANDOM READ

CS

SDA

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

1 1 0 0 0 0 0 0

WB flag output

WA input

WA

7

WA

6

WA

5

WA

4

WA

3

WA

2

WA

1

WA

0

D

7

D

6

D

5

(WA)

D

4

D

3

D

2

(WA+1) ··· (WA+n)

D

1

D

0

D

7

D

1

D

0

SCL

Internal WA

SDA mode

IN

CURRENT ADDRESS

OUT IN

WB flag is retained while 8 clocks are input to SCL pin.

Starts by making CS pin high with SCL pin high (issuance of STA).

WA data of first byte.

OUT

WA+1 WA+n

Contents of WA are read as

WA + n + 1

Contents of WA+1, ··· WA+n are sequentially read each time 1 byte has been read.

Operation ends if CS pin is made low with

SCL pin high (issuance of STP).

WA is last read address + 1 and retained.

243

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Steps <1> through <5> below are the operating procedure of the

µ

PD6252. In this example, the number of data to be written or read per interface operation is fixed to 1 byte. If the

µ

PD6252 is in the write busy (WB) status when interfaced, the busy flag is set.

<1> Make the CS pin (P32) high to start interfacing.

<2> Transmit the write or read command.

<3> Receive the data of WRITE BUSY. If interfacing the

µ

PD6252 is enabled, 00H is received. If a code other than 00H is received, it is judged that the

µ

PD6252 is in the WRITE BUSY status. In this case, communication is stopped.

<4> Transfer the data corresponding to the command.

<5> Make the CS pin (P32) low to end the communication.

(1) Description of package

<Public declaration symbol>

T3_6252 :

µ

PD6252 transfer subroutine name

RWRITE : RANDOM WRITE command value

RREAD : RANDOM READ command value

CREAD : CURRENT READ command value

WADAT : Word address storage area

TRNDAT : Transmit data storage area

RCVDAT : Receive data storage area

CMDDAT : Command data storage area

BUSYFG : Busy status test flag

CS6252 : CS pin (P32) of

µ

PD6252

<Register used>

A

<RAM used>

Name

WAADR

TRNDAT

RCVDAT

CMDDAT

Usage

Stores word address (before start of transfer)

Stores transmit data (before start of transfer)

Stores receive data (after end of transfer)

Stores command data (before start of transfer)

Attribute Bytes

SADDR 1

244

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Flag used>

Name

BUSYFG

Usage

Sets WRITE BUSY status

<Nesting>

1 level 3 bytes

<Hardware used>

Serial interface channel 0

P32

<Initial setting>

OSMS = #00000001B

Setting of serial interface channel 0

CSIM0 = #10011011B

TCL3 = #

××××

1001B

RELT = 1

; Oscillation mode select register: does not use divider circuit

; Selects 2-wire serial I/O mode and SB1 pin

; Serial clock f

XX

/2

4

; Makes SB1 latch high

<Starting>

Set the necessary data corresponding to the commands and call T3_6252. After execution returns from the subroutine, the busy flag (BUSYFG) is tested. If the busy flag is set, transfer is not executed. It is therefore necessary to execute transfer again. In the receive mode, the receive data is stored RCVDAT after execution has returned from the subroutine.

245

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(2) Example of use

Sets each data to memory

UNTIL: Not WRITE BUSY

Clears busy flag

Calls T3_6252

Loads receive data

EXTRN

EXTRN

RWRITE,RREAD,CREAD

WADAT,TRNDAT,RCVDAT,CMDDAT,T3_6252

EXTBIT BUSYFG,CS6252

OSMS=#00000001B

CSIM0=#10011011B

TCL3=#10011001B

CLR1

CLR1

CLR1

SB0

CS6252

PM3.2

; Does not use divider circuit

; Sets 2-wire serial I/O mode and SB1 pin

; Sets SCK0 = 262 kHz

; Makes CS of

µ

PD6252 low

CMDDAT=A

.

.

.

.

WADAT=A

.

.

.

.

TRNDAT=A

.

.

.

.

repeat

CLR1 BUSYFG

CALL !T3_6252

until_bit(!BUSYFG)

.

.

.

.

A=RCVDAT

246

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

T3_6252 Clears busy flag

Issues start bit

Transfers command

WHILE: waits for end of transfer (CSIIF0 = 0)

Receives busy signal

WHILE: waits for end of transfer (CSIIF0 = 0)

THEN

IF: not WB status (SIO0 = 00H)

CASE: CMDDAT

OF: RWRITE

Transfers word address

WHILE: waits for end of transfer

Transfers data

WHILE: waits for end of transfer

BREAK

OF: RREAD

Transfers word address

WHILE: waits for end of transfer

OF: CREAD

Receives data

WHILE: waits for end of transfer

Stores receive data to memory

ELSE

Sets busy status

Sets BUSYFG

Issues stop bit

247

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(4) Program list

PUBLIC RWRITE,RREAD,CREAD

PUBLIC WADAT,TRNDAT,RCVDAT,CMDDAT,T3_6252

PUBLIC BUSYFG,CS6252

CSI_DAT DSEG SADDR

WADAT: DS 1

TRNDAT: DS

RCVDAT: DS

CMDDAT: DS

1

1

1

; Word address storage area

; Transmit data storage area

; Receive data storage area

; Command data storage area

CSI_FLG BSEG

BUSYFG DBIT

RWRITE

RREAD

CREAD

EQU

EQU

EQU

CS6252 EQU

00H

0C0H

080H

0FF03H.2

; Sets busy status

; RANDOM WRITE mode

; RANDOM READ mode

; CURRENT READ mode

; 0FF03H=PORT3

CSI_SEG CSEG

;*************************************

;*

µ

PD6252 (3-wire) communication

;*************************************

T3_6252:

CLR1 BUSYFG

SET1 CS6252

SI00=CMDDAT (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0

SIO0=#0FFH while_bit(!CSIIF0) endw

CLR1 CSIIF0 if(SIO0==#00H) switch (CMDDAT) case RWRITE:

SIO0=WADAT (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0

SIO0=TRNDAT (A) while_bit(!CSIIF0) endw

CLR1 break

CSIIF0

; Issues start bit

; Transfers command

; Waits for end of transfer

; Starts reception of busy signal

; Waits for end of transfer

; Busy check

; Transfers word address

; Waits for end of transfer

; Starts data transfer

; Waits for end of transfer ends case RREAD:

SIO0=WADAT (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0 case CREAD:

SIO0=#0FFH while_bit(!CSIIF0) endw

CLR1 CSIIF0

RCVDAT=SIO0 (A)

; Transfers word address

; Waits for end of transfer

; Starts data reception

; Waits for end of transfer

; Stores receive data

248

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

else

SET1 endif

CLR1

RET

BUSYFG

CS6252

; Sets busy status

249

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.1.2 Communication in I

2

C bus mode

In the 2-wire mode of the

µ

PD6252

Note

, two lines, serial clock (SCL) and data (SDA) lines are used for communication. This mode conforms to the communication format of I

2

C. Therefore, the I

2

C mode is selected when communicating with the

µ

PD6252 by using the

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY,

78075BY subseries, or

µ

PD78070AY.

In the example shown in this section, the

µ

PD78054Y subseries is used.

Note

µ

PD6252 is for maintenance use.

Figure 8-28. Example of Connection between

µ

PD6252 and I

2

C Bus Mode

µ

PD78054Y

SCL

SDA0 (SDA1)

µ

PD6252

SCL

SDA

A

2

= 0

A

1

= 0

SCL

SDA

SCL

SDA

SCL

SDA

A

A

A

A

A

A

2

1

2

1

2

1

= 0

= 1

= 1

= 0

= 1

= 1

Figure 8-29 shows the communication format in which data is written to or read from the

µ

PD6252.

250

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(a) Transmission to

µ

PD6252

Figure 8-29.

µ

PD6252 Operation Timing

Start condition

SDA

WRITE Stop condition

1 0 1 0 A

2

A

1

0 0 ACK WA

7

WA

6

WA

5

WA

4

WA

3

WA

2

WA

1

WA

0

ACK D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

ACK D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

ACK

SCL

Slave address

R/W command

Word address Write data Write data

(b) Reception from

µ

PD6252 (without word address specification)

Start condition

SDA

READ

1 0 1 0 A

2

A

1

0 1 ACK D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

ACK D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Stop condition

SCL

Slave address

R/W command

Read data Read data

(c) Reception from

µ

PD6252 (with word address specification)

Start condition

SDA

WRITE Start condition

1 0 1 0 A

2

A

1

0 0 ACK WA

7

WA

6

WA

5

WA

4

WA

3

WA

2

WA

1

WA

0

ACK

READ

1 0 1 0 A

2

A

1

0 1 ACK D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Stop condition

SCL

Slave address

R/W command

Word address Slave address

R/W command

Read data

251

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Steps <1> through <5> below are the communication procedure of the

µ

PD6252. In this example, the number of data to be written or read is fixed to 1 byte. If the master receives data in the I

2

C bus format, and if it has received the last data, the ACK signal is not output. Because the master does not output the ACK signal in this example, ACKE is always 0.

<1> Set a start condition to start communication.

Fall the data with the serial clock high.

<2> Transmit the slave address value (bits 1 through 7) of the

µ

PD6252 and write (bit 0 = 0)/read (bit 0 = 1) select bit.

1 0 1 0 A

2

A

1

0 R / W

Slave address

7-bit (bits 7 through 1)

R/W selection

1 bit (bit 0)

Remark A

2

and A

1

are set by external pins.

<3> Transfer the data.

In transmission mode

(i) Transmit the word address of the

µ

PD6252.

(ii) Transmit the write data.

In reception mode

Receive the read data.

<4> Set an end condition to end the communication.

Rise the data with the serial clock high.

<5> Because a word address is specified only in the write mode, to read data by specifying an address, the address must be specified by once setting the write mode.

If the

µ

PD6252 does not return the ACK signal during data transfer, communication is stopped.

The start and end conditions are set by CLC when the serial clock is manipulated, and by RELT and CMDT when data is manipulated.

252

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(1) Description of package

<Public declaration symbol>

T2_6252 :

µ

PD6252 transfer subroutine name

WAADR : Word address storage area

TRNDAT : Transmit data storage area

RCVDAT : Receive data storage area

SLVADR : Slave address storage area

BUSYFG : Busy status test flag

WRCHG : Write

read mode change flag

ERRFG : Error status test flag

<Register used>

A

<RAM used>

Name

WAADR

TRNDAT

RCVDAT

SLVADR

Usage

Stores word address (before start of transfer)

Stores transmit data (before start of transfer)

Stores receive data (after end of transfer)

Stores slave address

<Flag used>

Name

BUSYFG

WRCHG

ERRFG

Usage

Sets WRITE BUSY status

Changes write mode to read mode

Sets error status

<Nesting>

1 level 2 bytes

<Hardware used>

Serial interface 0

Attribute Bytes

SADDR 1

253

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

Setting of serial interface channel 0

CSIM0 = #10011011B ; Selects 2-wire serial I/O mode and SB0 pin

TCL3 = #

××××

1000B ; Selects serial clock f

XX

/2

3

and 16

SINT = #00001011B ; Generates interrupts at rising edge of 9th serial clock and sets clock line to high level

<Starting>

• Set the necessary data corresponding to the commands and call T2_6252. In the reception mode, the receive data is stored to RCVDAT after execution has returned from the subroutine.

• If the serial clock is low (busy status) when communication is started or if ACK cannot be received during data transfer, the BUSYFG and ERRFG are set. Test and clear these flags with the main processing.

(2) Example of use

Sets data

Calls T2_6252

(IF: sets BUSYFG)

Clears BUSYFG

To busy processing

(IF: sets ERRFG)

Clears ERRFG

To error processing

EXTRN WAADR,TRNDAT,RCVDAT,SLVADR,T2_6252

EXTBIT BUSYFG,WRCHG,ERRFG

SET1 SB0

OSMS=#00000001B

CSIM0=#10011011B

SINT=#00001011B

TCL3=#10001000B

SET1 RELT

SET1 SCK0

CLR1

.

.

WAADR=A

.

.

TRNDAT=A

SB0

; Does not use divider circuit

; Serial interface 2-wire, SB0

; Sets I

2

C mode

; SCK = 32.7 kHz

SLVADR=A

CALL !T2_6252

if_bit(BUSYFG)

CLR1 BUSYFG

.

.

endif

.

if|bit(ERRFG)

CLR1

.

.

ENDIF

ERRFG

254

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

T2_6252

STABIT

THEN

IF: SCK0 = LOW

ELSE

Sets busy status

Sets BUSYFG

THEN

Issues start bit

Transmits slave address

WHILE: waits for end of transfer (CSIIF0 = 0)

IF: ACK signal not detected

Sets error status

ELSE

THEN

Sets ERRFG

IF: transmit mode

THEN

WHILE: waits for end of transfer

IF: ACK signal not detected

ELSE

Sets error status

Sets ERRFG

IF: changes to read mode

THEN

WHILE: SCK0 = HIGH

Outputs high level in order of data and clock

Changes slave address to read mode

GOTO STABIT

ELSE

Transmits data

WHILE: waits for end of transfer

IF: ACK signal not detected

ELSE

THEN

Sets error status

Sets ERRFG

Receives data

WHILE: waits for end of transfer

Stores receive data to memory

Outputs low level in order of clock and data

Issues stop bit

255

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(4) Program list

PUBLIC WAADR,TRNDAT,RCVDAT,SLVADR,T2_6252

PUBLIC BUSYFG,WRCHG,ERRFG

CSI_DAT DSEG

WAADR: DS

TRNDAT: DS

RCVDAT: DS

SLVADR: DS

SADDR

1

1

1

1

; Word address storage area

; Transmit data storage area

; Receive data storage area

; Salve address storage area

CSI_FLG BSEG

BUSYFG DBIT

WRCHG

ERRFG

DBIT

DBIT

SCK0 EQU P2.7

; Sets busy status

; Changes mode

; Sets error status

CSI_SEG CSEG

;*************************************

;*

µ

PD6252 (2-wire) communication

;*************************************

T2_6252: if_bit(!CLD)

SET1 BUSYFG else

STABIT:

; Busy status

; Issues start bit

; Waits for start bit valid width

SET1

NOP

NOP

NOP

CMDT

NOP

NOP

CLR1 CLC

SIO0=SLVADR (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0 if_bit(!ACKD)

SET1 ERRFG elseif_bit(!SLVADR.0)

SI00=WAADR (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0 if_bit(!ACKD)

SET1 ERRFG elseif_bit(WRCHG) while_bit(CLD) endw

SET1

SET1

RELT

CLC while_bit(!CLD) endw

NOP

NOP

NOP

NOP

NOP

NOP

NOP

NOP

SET1 goto

SLVADR.0

STABIT

; Changes clock to low level

; Starts transmitting slave address

; Waits for end of transfer

; ACK signal not detected

; Transmission mode

; Starts transmitting word address

; Waits for end of transfer

; ACK signal not detected

; Checks high level of clock

; Waits for high level valid width of clock

; Changes to read mode address else

256

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

SIO0=TRNDAT (A) while_bit(!CSIIF0) endw

CLR1 CSIIF0 if_bit(!ACKD)

SET1 ERRFG endif else endif

SIO0=#0FFH while_bit(!CSIIF0) endw

CLR1 CSIIF0

RCVDAT=SIO0 (A) endif

NOP

NOP

NOP

NOP

NOP

NOP while_bit(CLD) endw

SET1 CMDT

SET1 CLC while_bit(!CLD) endw endif

RET

NOP

NOP

SET1 RELT

; Starts transmitting data

; Waits for end of transfer

; ACK signal detected

; Starts data reception

; Waits for end of transfer

; Stores receive data

; Checks high level of clock

; Waits for high level valid width of clock

; Issues stop bit

257

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(5) Limitation when using I

2

C bus mode

The following limitation applies when the

µ

PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY,

78075BY subseries, and

µ

PD78070AY are used. This section explains an example using the

µ

PD78054Y.

Limitation when the device is used as a slave device in the I

2

C bus mode

Description: If the wake-up function is executed (by setting the WUP flag (bit 5 of serial operation mode register 0 (CSIM0) to 1) in the serial transfer status

Note

, the data between other slave device and the master devices is checked as an address. If that data coincides with the slave address of the

µ

PD78054Y, therefore, the

µ

PD78054Y takes part in communication, destroying the communication data.

Note The serial transfer status is the status from when the serial I/O shift register 0 (SIO0) has been written until the interrupt request flag (CSIIF0) is set to 1 by completion of serial transfer.

Preventive measures: The above problem can be prevented by modifying the program.

Before executing the wake-up function, execute the following program that clears the serial transfer status. When executing the wake-up function, do not execute an instruction that writes data to SIO0. Even if such an instruction is executed, data can be received when the wake-up function is executed.

This program is to clear the serial transfer status. To clear the serial transfer status, serial interface channel 0 must be stopped (by clearing the CSIE0 flag (bit 7 of the serial operation mode register (CSIM0) to 0). If the serial interface channel 0 is stopped in the I

2

C bus mode, however, the SCL pin outputs a high level and the

SDA0 (SDA1) pin outputs a low level, affecting communication on the I

2

C bus.

Therefore, this program allows the SCL and SDA0 (SDA1) pin to go into a highimpedance state to prevent the I

2

C bus from being affected.

Note that, in this example, the serial data input/output pin is SDA0 (/P25). If SDA1

(/P26) is used as the serial data input/output pin, take P2.5 and PM2.5 in the program as P2.6 and PM2.6.

258

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Example of program that clears serial transfer status

SET1 P2.5

; <1>

SET1 PM2.5

; <2>

SET1 PM2.7

; <3>

CLR1 CSIE0 ; <4>

SET1 CSIE0 ; <5>

SET1 RELT ; <6>

CLR1 PM2.7

; <7>

CLR1 P2.5

; <8>

CLR1 PM2.5

; <9>

<1> When the I

2

C bus mode is restored by instruction <5>, the SDA0 pin does not output a low level. The output of the SDA0 pin goes into a high-impedance state.

<2> The P25(/SDA0) pin is set in the input mode to prevent the SDA0 line from being affected when the port mode is set by instruction <4>. The P25 pin is set in the input mode when instruction <2> is executed.

<3> The P27 (/SCL) pin is set in the input mode to prevent the SCL line from being affected when the port mode is set by instruction <4>. The P27 pin is set in the input mode when instruction <3> is executed.

<4> The I

2

C bus mode is changed to the port mode.

<5> The port mode is changed to the I

2

C bus mode.

<6> Instruction <8> prevents the SDA0 pin from outputting a low level.

<7> The P27 pin is set in the output mode because it must be in the output mode in the I

2

C bus mode.

<8> The output latch of the P25 pin is cleared to 0 because it must be cleared to 0 in the I

2

C bus mode.

<9> The P25 pin is set in the output mode because it must be in the output mode in the I

2

C bus mode.

Remark RELT: Bit 0 of serial bus interface control register (SBIC)

259

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.2 Interface with OSD LSI (

µ

PD6451A)

The OSD (On Screen Display) LSI

µ

PD6451A displays the program information of a VCR and TV channels on a display when used in combination with a microcontroller. The

µ

PD6451A is interface with four lines: DATA, CLK,

STB, and BUSY. In the example shown in this section, the

µ

PD78054 subseries is used to interface the

µ

PD6451A.

Figure 8-30. Example of Connecting

µ

PD6451A

µ

PD78054

SCK1

SO1

STB

BUSY

µ

PD6451A

CLK

DATA

STB

BUSY

RGB RGB

Display

Figure 8-31. Communication Format of

µ

PD6451A

SCK1

SO1

STB

BUSY

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The strobe signal (STB) is output and busy signal (BUSY) is tested automatically by the serial interface channel

1 of the 78K/0 series to establish handshaking with and to interface the

µ

PD6451A. To match the communication format of the

µ

PD6451A, the

µ

PD78054 subseries is set in a mode in which output of the strobe signal and input of the busy signal (high active) are enabled. By setting the transmit data (32 bytes MAX) in a buffer area (FAC0H through

FADFH) and the number of transmit data to the automatic data transmit/receive address pointer (ADTP), you can automatically transmit plural data successively.

260

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(1) Description of package

<Public declaration symbol>

TR6451 :

µ

PD6451A transfer subroutine name

DTVAL : Number of transmit data setting area

<Register used>

A

<RAM used>

Name

DTVAL

Usage

Stores number of transmit data

Attribute Bytes

SADDR 1

<Nesting>

1 level 2 bytes

<Hardware used>

• Serial interface channel 1

<Initial setting>

• Setting of serial interface channel 1

CSIM1 = #10100011B ; Enables automatic transmission/reception with MSB first

ADTC = #00000110B ; Enables busy input (high active) and strobe output in single mode

• ADTI = #00000000B ; Interval time of data transfer

• OSMS = #00000001B ; Oscillation mode select register; does not use divider circuit

• TCL3 = #1001

××××

B ; Serial clock f

XX

/2

4

• Makes P22 output latch high

• PM2 = #

×××

1000

×

B ; Sets P21, P22, and P23 in output mode and P24 in input mode

<Starting>

Set the data to be transmitted to the buffer RAM (starting from the highest address), and the number of data to be transmitted to DTVAL, and call TR6451. You can check the end of data transfer by testing the bit 3

(TRF) of the automatic data transfer/reception control register (ADTC).

261

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(2) Example of use

Sets data to buffer RAM

Sets number of data to be transmitted to DTVAL

Calls TR6451

WHILE: waits for end of transfer

SCK1

EXTRN TR6451,DTVAL

EQU P2.2

.

.

.

.

OSMS=#00000001B

P2=#00000100B

PM2=#11110001B

CSIM1=#10100011B

TCL3=#10011001B

ADTC=#00000110B

ADTI=#00000000B

.

.

.

.

DE=#TABLE1

HL=#0FAC0H

B=32 while(B>#0)

B––

[HL+B]=[DE] (A)

DE++ endw

DATVAL=#32

CALL !TR6451

while_bit(TRF) endw

; Does not use divider circuit

; Sets automatic transfer/reception function

; SCK1 = 262 kHz

; Enable strobe and busy signals

; Interval time of data transfer

; Sets table reference address of transmit data

; Sets first address of buffer RAM

; Sets number of data to be transmitted

; Transfers transmit data to buffer RAM

; Sets number of data to be transmitted

; Waits for end of transfer

262

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

TABLE1:

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

11111111B

01000000B

11000000B

10000000B

11111100B

11101001B

10001100B

11011011B

10010101B

10100000B

; Power-ON reset, command 1

; Vertical address 0

; Horizontal address 0

; Character size

; Command 0

; Turns LC transmission ON, blinking OFF, display ON

; Turns blinking ON. Character: red

; Color specification, background filled in cyan

; Number of display lines: 5

; Number of display digits: 0

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

13H

11H

24H

19H

00H

1EH

10H

1EH

00H

24H

15H

07H

08H

1BH

6DH

00H

10H

11H

20H

20H

1CH

19H

; A

; P

; P

; L

; I

; C

; A

; T

; I

; O

; N

; 7

; 8

; K

; /

; 0

; N

; O

; T

; E

Remark For the command and data of the output table data, refer to

µ

PD6451A Data Sheet (Document No. IC-

2337).

263

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

TR6451 Sets (number of data to be transmitted – 1) to ADTP

Sets status before transfer

Starts transfer

(4) Program list

PUBLIC TR6451,DTVAL

CSI_DAT DSEG

DTVAL: DS

SADDR

1

CSI_SEG CSEG

;*************************************

;*

µ

PD6451A communication

;*************************************

TR6451:

A=DTVAL

A––

ADTP=A

SIO1=#0FFH

RET

; Number of data setting area

; Sets number of data

; Starts transfer

264

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.3 Interface in SBI Mode

The 78K/0 series has an SBI mode conforming to NEC serial bus format. In this mode, one master CPU can communicate with two or more slave CPUs by using two lines: clock and data. In the example shown in this section, the

µ

PD78054 subseries is used.

Figure 8-32 shows an example of connection to use the SBI mode, and Figure 8-33 shows the communication format.

Figure 8-32. Example of Connection in SBI Mode

V

DD

µ

PD78054 master

SB0

SCK0

µ

PD78054 slave

SB0

SCK0

Slave CPU

SB

SCK

Slave CPU

SB

SCK

265

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(a) Address transmission

Figure 8-33. Communication Format in SBI Mode

SCK0

SB0

Sets

RELD

Sets

CMDD

A7 A6 A5 A4 A3 A2 A1 A0

(b) Command transmission

SCK0

SB0

Sets

CMDD

C7 C6 C5 C4 C3 C2 C1 C0

(c) Data transmission/reception

SCK0

SB0 D7 D6 D5 D4 D3 D2 D1 D0 ACK

Sets

ACKD

Signal Name

Address

Command

Data

Clock

ACK

BUSY

Table 8-9. Signals in SBI Mode

Output by:

Master

Master

Master/slave

Master

Receiver side

Note

Slave

Meaning

Selects slave device

Command to slave device

Data to be processed by slave or master

Serial data transmission/reception synchronization signal

Reception acknowledge signal

Busy status

Note

This signal is output by the receiver side during normal operation. However, it is output by the master CPU in case of an error such as time out.

266

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.3.1 Application as master CPU

When the

µ

PD78054 subseries is used as a master CPU, it performs processing (a) through (d) below with respect to slave CPUs.

(a) Address transmission

(b) Command transmission

(c) Data transmission

(d) Data reception

While the above processing is performed, errors <1> and <2> below are checked.

<1> Time out processing

If the master CPU transmits data and a slave does not return the ACK signal within a specific time (in this example, before the watch interrupt request occurs five times), the master judges that an error has occurred.

The master CPU then outputs an ACK signal and terminates the processing.

Figure 8-34. ACK Signal in Case of Time out

End of transfer Master output

SB0 ACK

(time out)

INTTM3 (ACKD test)

<2> Testing bus line

The master CPU tests whether data has been correctly output to the bus line by setting the transmit data to the serial I/O shift register 0 (SIO0) and the slave address register (SVA). Because the data on the bus line is received by SIO0, it confirms that the data has been output normally by testing bit 6 (COI) of the serial operating mode register 0 (CSIM0) (that is set when SIO0 coincides with SVA) at the end of transfer.

Figure 8-35. Testing Bus Line

SIO0 = 0FH

SB0 = 07H

0 0 0 0 1 1 1 1

0 0 0 0 0 1 1 1

In Figure 8-35, the values of SIO0 and SVA do not coincide (SIO0 = 07H and SVA = 0FH). Consequently, COI

= 0, and an error has occurred on the bus line.

267

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(1) Description of package

<Public declaration symbol>

M_TRANS : Master SBI transfer subroutine name

TR_MODE

TRNDAT

: Storage area of transfer mode select value

: Transmit data storage area

RCVDAT

TRADR

TRCMD

TRDAT

RCDAT

ERRORF

: Receive data storage area

: Address transmit mode select value

: Command transmit mode select value

: Data transmit mode select value

: Data reception mode select value

: Error status test flag

<Register used>

Subroutine A

<RAM used>

Name Usage

TR_MODE Stores transfer mode select value

ACKCT

TRNDAT

RCVDAT

Time out counter

Stores transmit data

Stores receive data

Attribute Bytes

SADDR 1

<Flag used>

Name

RCVFLG

BUSYFG

ERRORF

ACKWFG

Usage

Sets reception mode

Sets busy status

Sets error status

Sets ACK signal wait status

<Nesting>

2 levels 5 bytes

268

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Hardware used>

Serial interface channel 0

Watch timer

<Initial setting>

OSMS=#00000001B

Sets serial interface channel 0

; Oscillation mode select register: does not use divider circuit

CSIM0=#10010011B

TCL3=#

××××

1001B

RELT=1

P27=1

TMC2=#00100110B

Enables watch timer interrupt

; Selects SBI mode and SB1 pin

; Serial clock: f

XX

/2

4

; Makes SO0 latch high

; Makes P27 output latch high

; Watch timer interval: 1.95 ms

<Starting>

Set the transfer mode and necessary data, and call M_TRANS. When execution has returned from the subroutine, occurrence of a transfer error can be checked by testing the error flag (ERRORF). In the reception mode, the receive data is stored to RCVDAT after execution has returned from the subroutine.

269

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(2) Example of use

Sets transfer mode

Sets transmit data

Calls M_TRANS

IF: error occurs

Error processing

EXTRN

EXTRN

M_TRANS,TR_MODE,TRADR,TRCMD,TRDAT,RCDAT

TRNDAT,RCVDAT

EXTBIT ERRORF

SCK0 EQU P2.7

SB1 EQU

.

.

.

.

OSMS=#00000001B

SET1 SB1

CSIM0=#10010111B

P2.5

TCL3=#10011001B

TMC2=#00100110B

CLR1 BSYE

SET1

SET1

CLR1

CLR1

CLR1

EI

RELT

SCK0

SB1

CSIMK0

TMMK3

.

.

.

.

TR_MODE=#TRADR

TRNDAT=#5AH

CALL !M_TRANS

if_bit(ERRORF)

Error processing endif

; Does not use divider circuit

; Operates in SBI mode

; SCK0 = 262 kHz

; Sets interval of watch timer to 1.95 ms

; Disables output of busy signal

; Sets output latch

; Enables serial interface channel 0 interrupt

; Enables watch timer interrupt

; Enables master interrupt

270

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

M_TRANS CASE: TR_MODE

OF: TRADR

WHILE: SB0 = LOW

WHILE: SCK0 = LOW

Outputs command signal

Outputs bus release signal

OF: TRCMD

WHILE: SB0 = LOW

WHILE: SCK0 = LOW

Outputs command signal

OF: TRDAT

Sets transmission mode

Clears RCVFLG

BREAK

OF: RCDAT

Sets reception mode

Sets RCVFLG

Sets output off data (FFH) of bus line

BREAK

Sets transmission status

Sets BUSYFG

Sets transmit data to SIO0 and SVA

WHILE: transfer in progress (sets BUSYFG)

THEN

Stores data of SIO0 to RCVDAT

IF: transmission mode

THEN

IF: error occurs in bus line

Sets error status

Sets ERRORF

271

272

INTCSI0

INTTM3

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Selects register bank 0

IF: transmission mode

THEN

THEN

IF: ACK signal not received

Sets ACK wait status

Sets ACKWFG

ELSE

ELSE

Clears busy status

Clears BUSYFG

Clears error status

Clears ERRORF

Outputs ACK signal

Clears BUSYFG and ERRORF

Selects register bank 0

IF: ACK wait status

THEN

THEN

IF: ACK received

Clears ACK wait status

Clears ACKWFG

Clears busy status

Clears BUSYFG

ELSE

THEN

IF: time out

Time out error processing

Clears ACK wait status

Clears ACKWFG

Clears busy status

Clears BUSYFG

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(4) Program list

PUBLIC M_TRANS,TR_MODE,TRADR,TRCMD,TRDAT,RCDAT

PUBLIC TRNDAT,RCVDAT,ERRORF

VECSI0 CSEG

DW

VETM3 CSEG

DW

AT 14H

INTCSI0

AT 1EH

INTTM3

; Sets vector address of serial interface channel 0

; Sets vector address of watch timer

SBI_DAT DSEG

TRNDAT: DS

RCVDAT: DS

TR_MODE:DS

ACKCT: DS

1

1

SADDR

1

1

; Transmit data

; Receive data

; Sets transfer mode

; ACK time out count

SBI_FLG BSEG

RCVFLG DBIT

BUSYFG DBIT

ERRORF DBIT

ACKWFG DBIT

; Sets reception mode

; Transfer status

; Error display

; ACK wait status

SB0

SCK0

EQU

EQU

P2.5

P2.7

TRADR

TRCMD

TRDAT

RCDAT

EQU

EQU

EQU

EQU

1

2

3

4

; Selects address transmission mode

; Selects command transmission mode

; Selects data transmission mode

; Selects data reception mode

273

274

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

;*******************************************

;* SBI data transfer processing

;*******************************************

SBI_SEG CSEG

M_TRANS: switch(TR_MODE) case TRADR:

SET1 PM2.5

while_bit(!SB0)

CLR1 PM2.5

endw while_bit(!SCK0) endw

SET1

NOP

SET1

CMDT

A=#TRCMD case TRCMD:

RELT

SET1 PM2.5

while_bit(!SB0)

CLR1 endw

PM2.5

while_bit(!SCK0) endw

SET1

A=#TRDAT

CMDT case TRDAT:

CLR1

A=TRNDAT break

RCVFLG case RCDAT:

SET1 ends

MOV break

RCVFLG

A,#0FFH

; SB0 = high?

; SCK = high?

; Outputs command signal

; Wait

; Outputs bus release signal

; SB0 = high?

; SCK = high?

; Outputs command signal

; Sets transmission mode

; Sets transmit data

; Sets reception mode

; Turns off receive buffer

SET1

SVA=A

SIO0=A

BUSYFG while_bit(BUSYFG) endw

RCVDAT=SIO0 (A) if_bit(!RCVFLG) endif endif

RET if_bit(!COI)

SET1 ERRORF

; Sets transfer status

; Tests bus line

; Starts transfer

; Transfer in progress

; Stores receive data

; Transmission mode

; Bus line output abnormal

; Sets error status

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

;***************************************

;* INTCSI0 interrupt processing

;***************************************

CSI_SEG CSEG

INTCSI0:

SEL RB0 if_bit(!RCVFLG) if_bit(!ACKD)

ACKCT=#5

SET1 ACKWFG else

CLR1

CLR1 endif

BUSYFG

ERRORF else

SET1 endif

RET

CLR1

CLR1

ACKT

BUSYFG

ERRORF

;***************************************

;* Time out processing

;***************************************

TM3_SEG CSEG

INTTM3:

SEL RB0 if_bit(ACKWFG) if_bit(ACKD)

CLR1 ACKWFG

BUSYFG CLR1 else

ACKCT-if(ACKCT==#0)

SET1 ACKT

SET1 ERRORF

CLR1

CLR1 endif

ACKWFG

BUSYFG endif endif

; Transmission mode

; Acknowledge signal not received

; Sets acknowledge signal wait status

; Clears busy status

; Clears error status

; Outputs acknowledge signal

; Clears busy status

; Clears error status

; Acknowledge signal wait status?

; Acknowledge signal received?

; Clears acknowledge signal wait status

; Clears busy status

; Time out?

; Time out error processing

; Clears acknowledge signal wait status

; Clears busy status

275

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.3.2 Application as slave CPU

A slave CPU receives addresses, commands, and data from the master CPU and transmits data to the master

CPU.

In the example shown in this section, addresses are received by using the wake-up function. This function is to generate an interrupt only when the address value transmitted by the master to the slave coincides with the value set to the slave address register (SVA) of the slave in the SBI mode. Therefore, only the slave CPU selected by the master CPU generates INTCSI0, and the slave CPUs not selected operates without generating an inadvertent interrupt request.

The slave CPU clears the wake-up function when it has been selected by the master (the interrupt request signal is generated at the end of transmission), and interfaces with the master CPU. Addresses, commands, and data being transmitted are identified by using bits 2 and 3 (RELD and CMDD) of the serial bus interface control register (SB IC).

Because the slave CPU is not automatically placed in the unselect status, a program that returns the slave CPU to the unselect status must be prepared by processing commands between the master and CPU.

(1) Description of package

<Public declaration symbol>

RCVDAT: Receive data storage area

<Register used>

Bank 0: A

<RAM used>

Name

RCVDAT Stores receive data

Usage Attribute Bytes

SADDR 1

<Flag used>

Name

RCVFLG Sets reception mode

Usage

<Nesting>

1 level 3 bytes

<Hardware used>

Serial interface channel 0

<Initial setting>

Setting of serial interface channel 0

CSIM0=#10010011B; Sets SBI mode, SBI pin, and wake-up mode, and inputs serial clock from external source

BYSE=1

RELT=1

SVA=#SLVADR;

Enables serial interface channel 0 interrupt

Outputs synchronous busy signal

Makes SO0 latch high

Slave address

276

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Starting>

The interrupt processing is started by generation of INTCSI0. The interrupt processing performs the following processing:

Identifies address/command/data

Outputs ACK signal

Stores receive data to RCVDAT

(2) Example of use

EXTRN RCVDAT

EXTBIT RCVFLG

SLVADR EQU 5AH

SB1 EQU P2.5

.

.

.

.

SET1 SB1

CSIM0=#10110100B

SET1 RELT

SET1 BSYE

SVA=#SLVADR

SIO0=#0FFH

CLR1 SB1

CLR1 CSIMK0

EI

; Inputs external clock, sets SB1 pin, and selects wake-up mode

; Sets output latch to high level

; Sets busy automatic output

; Sets slave address

; Serial transfer start command

; Enables serial interface channel 0 interrupt

; Enables master interrupt

(3) SPD chart

INTCSI0 Selects register bank 0

IF: address received

THEN

Clears wake-up mode

Outputs ACK signal

Address coincidence processing

ELSE

THEN

IF: command received

Command reception processing

Outputs ACK signal

ELSE

THEN

IF: reception mode

Data reception processing

Outputs ACK signal

ELSE

Data transmission processing

Stores SIO0 data to memory

277

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(4) Program list

VECSI0 CSEG

DW

AT 14H

INTCSI0

SCI_DAT DSEG

RCVDAT: DS

SADDR

1

; Sets vector address of serial interface channel 0

; Receive data storage area

CSI_FLG BSEG

RCVFLG DBIT

CSI_SEG CSEG

;***************************************

;* INTCSI0 interrupt processing

;***************************************

INTCSI0:

SEL RB0 if_bit(RELD)

CLR1

SET1

WUP

ACKT

; User processing (address reception)

; Sets reception mode

; To address reception

; Clears wake-up mode

; Outputs acknowledge signal

;***************************************

; elseif_bit(CMDD)

User processing (command reception) else

SET1 ACKT

; To command reception

; Outputs acknowledge signal

; if_bit(RCVFLG)

User processing (data reception processing)

ACKT else

SET1

; User processing (data transmission processing) endif

;*************************************** endif

RCVDAT=SIO0 (A)

; Outputs acknowledge signal

RETI

278

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.4 Interface in 3-Wire Serial I/O Mode

In this section, examples of communication between the master and a slave by using the 3-wire serial I/O mode

(serial clock, data input, data output) of the serial channel 0 of the 78K/0 series are shown. In these examples, one extra busy signal is used as a handshake signal for simultaneous transmission/reception between the master and slave. This busy signal is active-low and is output by the slave. The data is 8 bits long and transmitted with the MSB first. In the examples in this section, the

µ

PD78054 subseries is used.

Figure 8-36. Example of Connection in 3-Wire Serial I/O Mode

Master

SCK0

SI0

SO0

BUSY

SCK0

SO0

SI0

BUSY

Slave

BUSY

SCK0

Figure 8-37. Communication Format in 3-Wire Serial I/O Mode

SO0

SI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

279

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.4.1 Application as master CPU

The serial clock is set to f

XX

/2

4

, and communication is executed in synchronization with this serial clock between the master and slave CPUs.

The master CPU starts transmission after it has set the transmit data. If the slave CPU is busy (when the busy signal is low), however, the master does not transmit data and sets the busy flag (BUSYFG).

(1) Description of package

<Public declaration symbol>

TRANS : Name of 3-wire transfer subroutine of master

TDATA

RDATA

: Transmit data storage area

: Receive data storage area

BUSY

TREND

: Busy signal input port

: Transfer end test flag

BUSYFG : Busy status test flag

<Register used>

Interrupt : Bank 0, A

Subroutine : A

<RAM used>

Name

TDATA

RDATA

Stores transmit data

Stores receive data

Usage Attribute Bytes

SADDR 1

<Flag used>

Name

TREND

BUSYFG

Usage

Sets transfer end status

Sets busy status

<Nesting>

2 levels 5 bytes

<Hardware used>

• Serial interface channel 0

• P33

<Initial setting>

• OSMS=#00000001B ; Oscillation mode select register: does not used divider circuit

• Setting of serial interface channel 0

CSIM0=#10000011B

• TCL3=#

××××

1001B

• P27=1

• P33 input mode

• Enables serial interface channel 0 interrupt

; 3-wire serial I/O mode, MSB first

; Serial clock f

XX

/2

4

; Makes P27 output latch high

280

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Starting>

Set the transmit data to TDATA and call TRANS. After execution has returned from the subroutine, test the busy flag (BUSYFG). If the busy flag is set, transfer has not been executed and therefore, you must execute it again. If the busy flag is cleared, transfer has ended and the receive data has been stored to RDATA.

(2) Example of use

Sets transmit data

UNTIL: BUSYFG cleared

Clears BUSYFG

Calls TRANS

WHILE: TREND cleared

Loads receive data

EXTRN TDATA,RDATA,TRANS

EXTBIT TREND,BUSYFG,BUSY

SCK0 EQU

.

.

.

.

P2.7

OSMS=#00000001B

CSIM0=#10000011B

TCL3=#10011001B

SET1 SCK0

SET1 PM3.3

CLR1

EI

CSIMK0

.

.

.

.

TDATA=A repeat

CLR1 BUSYFG

CALL !TRANS

until_bit(!BUSYFG) while_bit(!TREND) endw

A=RDATA

; Does not use divider circuit

; Sets 3-wire serial I/O mode with MSB first

; Sets SCK0 = 262 kHz

; Sets P3.3 input mode

; Enables serial interface channel 0

; Sets transmit data

; Busy test

; Ends transfer

; Loads receive data

281

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

TRANS

THEN

IF: transfer enabled

Sets transmit data to SIO0

ELSE

Sets busy status

Sets BUSYFG

INTCSI0 Selects register bank 0

Stores data of SIO0 to memory

Sets transfer end status

Sets TREND

(4) Program list

PUBLIC TRANS,RDATA,TDATA,BUSY,TREND,BUSYFG

VECSI0 CSEG AT 14H

DW INTCSI0

; Sets vector address of serial interface channel 0

BUSY EQU 0FF03H.3

; 0FF03H = PORT3

CSI_DAT DSEG

RDATA: DS

TDATA: DS

SADDR

1

1

; Receive data storage area

; Transmit data storage area

CSI_FLG BSEG

TREND DBIT

BUSYFG DBIT

; Sets transfer end status

; Sets busy status

CSI_SEG CSEG

;**************************************

;:* INTCSI0 interrupt processing

;**************************************

INTCSI0:

SEL RB0

RDATA=SIO0 (A)

SET1

RETI

TREND

;**************************************

;* 3-wire (master)

;**************************************

TRANS: if_bit(BUSY)

SIO0=TDATA (A) else

SET1 BUSYFG endif

RET

; Stores receive data

; Sets transfer end status

; Enables transfer

; Sets transmit data

; Sets busy status

282

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.4.2 Application as slave CPU

In this example, a slave CPU simultaneously transmits and receives 8-bit data in synchronization with the serial clock from the master CPU. The busy signal output by the slave CPU is low (busy status) while the transmit data is prepared. This busy signal is cleared (high level) when the transmit data is set (CALL !TRANS), and is output (low level) when interrupt INTCSI0 occurs at the end of transfer.

Therefore, the busy status remains after the end of transfer until the data is set.

Figure 8-38. Output of Busy Signal

Waits for transmission

Transmission in progress Transmit data being prepared

BUSY

Sets transmit data INTCSI0 Sets transmit data

(1) Description of package

<Public declaration symbol>

TRANS : Name of 3-wire transfer subroutine of slave

TDATA

RDATA

: Transmit data storage area

: Receive data storage area

BUSY

TREND

: Busy signal output port

: Transfer end test flag

<Register used>

Interrupt : Bank 0, A

Subroutine : A

<RAM used>

Name

TDATA

RDATA

Stores transmit data

Stores receive data

Usage Attribute Bytes

SADDR 1

<Flag used>

Name

TREND

Usage

Sets transfer end status

<Nesting>

2 level 5 bytes

<Hardware used>

• Serial interface channel 0

• P33

283

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Initial setting>

• Setting of serial interface channel 0

CSIM0=#10000000B ; Sets 3-wire serial I/O mode with MSB first, and inputs external clock

; P33 output mode • P33=0

• Setting of busy status

• Enables serial interface channel 0

<Starting>

Set the transmit data to TDATA and call TRANS. Because the busy signal is cleared by the processing of

TRANS, the slave waits for communication with the master. After the communication has ended, INTCSI0 occurs and interrupt processing is started. You can check the end of transfer by testing TREND. After TREND has been set, the receive data has been stored to RDTA.

(2) Example of use

Sets transmit data

Calls TRANS

WHILE: TREND cleared

Loads receive data

EXTRN TDATA,RDATA,TRANS

EXTBIT TREND,BUSY

.

.

.

.

CSIM0=#10000000B

CLR1 BUSY

CLR1

CLR1

EI

.

.

.

.

PM3.3

CSIMK0

TDATA=A

CALL !TRANS

while_bit(!TREND) endw

A=RDATA

; Sets 3-wire I/O mode with MSB first

; Busy status

; P3.3 output mode

; Enables serial interface channel 0

; Sets transmit data

; Ends transfer

; Loads receive data

284

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

TRANS Sets transmit data to SIO0

Clears busy signal

INTCSI0 Selects register bank 0

Outputs busy signal

Stores SIO0 data to memory

Sets transfer end status

(4) Program list

PUBLIC RDATA,TDATA,BUSY,TREND,BUSYFG

PUBLIC TRANS

VECSI0 CSEG

DW

AT 14H

INTCSI0

CSI_DAT DSEG

RDATA: DS

TRADA: DS

SADDR

1

1

; Sets vector address of serial interface channel 0

; Stores receive data

; Stores transmit data

CSI_FLG BSEG

TREND DBIT

BUSYFG DBIT

BUSY EQU 0FF03H.3

; Sets transfer end status

; Sets busy status

; 0FF03H = PORT3

CSI_SEG CSE

;**************************************

;* INTCSI0 interrupt processing

;**************************************

INTCSI0:

SEL RB0

CLR1 BUSY

RDATA=SI00 (A)

SET1

RETI

TREND

; Sets busy status

; Stores receive data

; Sets transfer end status

;**************************************

;* 3-wire (slave)

;**************************************

TRANS:

SIO0=TDATA (A)

SET1

RET

BUSY

; Sets transmit data

; Clears busy status

285

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

8.5 Interface in Asynchronous Serial Interface (UART) Mode

Serial interface channel 2 has two modes: asynchronous serial interface (hereafter referred to as “UART”) and

3-wire serial I/O modes.

Serial interface channel 2 is set by the following registgers:

Serial operating mode register 2 (CSIM2)

Asynchronous serial interface mode register (ASIM)

Asynchronous serial interface status register (ASIS)

Baud rate generator control register (BRGC)

Oscillation mode select register (OSMS)

UART using serial interface channel 2 is briefly described below.

The UART mode of serial interface channel 2 is to transmit or receive 1-byte data following a start bit and can perform full-duplex operation.

The operations of UART communication are described below.

(a) Communication format

One data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit. The character bit length, parity, and stop bit length in one data frame are specified by using the asynchronous serial interface mode register (ASIM).

(b) Setting of baud rate

A UART dedicated baud rate generator is provided that can set a wide range of baud rates. A baud rate can also be defined by dividing the clock input to the ASCK pin.

The transmit/receive clock for the band rate is generated by dividing the main system clock. The baud rate generated from the main system clock can be calculated by the following expression. Table 8-10 shows the relations between the main system clock and baud rate (at fx = 4.19 MHz).

f

XX

[Baud rate] = [Hz]

2 n

×

(k + 16)

Remarks 1. f

XX

: main system clock frequency (f

X

or f

X

/2)

2. f

X

: main system clock oscillation frequency

3. n : value set by TPS0-TPS3

(bits 4-7 of the baud rate generator control register (BRGC) (1

n

11)

4. k : value set by MDL0-MDL3 (bits 0-3 of BRGC) (0

k

14)

286

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Table 8-10. Relations between Main System Clock and Baud Rate (at f

X

= 4.19 MHz)

Baud rate (bps)

600

1200

2400

4800

75

110

150

300

9600

19200

31250

38400

76800

MCS = 1

Set value of BRGC

0BH

03H

EBH

DBH

CBH

BBH

ABH

9BH

8BH

7BH

71H

6BH

5BH

Error (%)

1.14

–2.01

1.14

1.14

1.14

1.14

1.14

1.14

1.14

1.14

–1.31

1.14

1.14

MCS = 0

Set value of BRGC

EBH

E3H

DBH

CBH

BBH

ABH

9BH

8BH

7BH

6BH

61H

5BH

Error (%)

1.14

–2.01

1.1.4

1.14

1.14

1.14

1.14

1.14

1.14

1.14

–1.31

1.14

Remark MCS: bit 0 of the oscillation mode select register (OSMS)

(c) Transmission

Transmission is started when transmit data has been written to the transmit shift register (TXS). The start bit and parity bit are automatically appended.

(d) Reception

Reception is enabled when bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set to

1, and the data input to the RxD pin is sampled. When reception of one frame of data has been completed, the receive data in the shift register is transferred to the receive buffer register (RXB) and a receive end interrupt request (INTSR) occurs.

(e) Receive error

During reception, three types of errors may occur: parity error, framing error, and overrun error. If the error flag of the asynchronous serial interface status register (ASIS) is set as a result of data reception, a receive error interrupt (INTSER) occurs. By reading the contents of ASIS in the receive error interrupt processing

(INTSER), which error has occurred can be identified. The contents of ASIS are reset (0) by either reading the receive buffer register (RXB) or receiving the next data. (if the next data includes an error, that error flag is set).

Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset to 0 when the receive buffer register (RXB) is read or the next data is received. To determine the nature of the error, be sure to read ASIS before reading RXB.

2. Be sure to read the receive buffer register (RXB) when a reception error has occurred.

Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist.

287

288

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

During communication, transmission and reception with a terminal is performed and RTS and CTS are controlled for handshaking. The communication protocol is shown below.

Baud rate: 9600 bps

No parity bit

Stop bit: 2 bits

LSB first

CTS input pin: P31

RTS output pin: P32

When transmission is started, the end of the previous transmission (in which case the transmission end interrupt request flag (STIF) is set to 1) is checked, and transmission is executed if the CTS input status is ready (“L”).

During reception, the busy signal (“H”) is output to the RTS output pin when a reception end interrupt request

(INTSR) occurs. “L” is output to the RTS output pin when reception is enabled.

A receive error interrupt request (INTSER) occurs if a receive error (parity error, framing error, or overrun error) occurs, and the error flag is set. Figure 8-39 shows a communication block diagram, and Figures 8-40 and

8-41 show the transmission/reception format.

Figure 8-39. Communication Block Diagram

T

X

D

R

X

D

CTS input

RTS output

T

X

D

Terminal

R

X

D

CTS input

RTS output

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-40. Communication Format

Reception at reception side OK

CTS input pin

P31

Data output

T

X

D

Transmission end interrupt request

INTST

Start bit

Communication start timing

D0 D1 D2 D3 D4 D5 D6 D7

Parity bit

Stop bit

Figure 8-41. Reception Format

RTS output pin

P32

Data input

R

X

D

Receive end interrupt request

INTSR

Receive error interrupt request

INTSER

Start bit

D0 D1 D2 D3 D4 D5 D6 D7

Parity bit

Stop bit

289

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(1) Description of package

<Public declaration symbol>

• Subroutine name

S_SOSHIN : Transmit routine

• Input parameter of S_SOSHIN routine

SOSHIN : Transmit data storage area

• Output parameter of S_SOSHIN routine

F_BUSY : Transmit busy flag

• Output parameter of INTSR interrupt

JUSHIN : Receive data storage area

F_TUSHIN : Reception end flag

• Output parameter of INTSER interrupt

F_ERR : Receive error flag

<Register used>

S_SOSHIN : Bank 0, A

INTSR

INTSER

: Bank 3, A

: Bank 3, A

<RAM used>

Name

SOSHIN

JUSHIN

Usage

Transmit data storage area

Receive data storage area

<Flag used>

Name Usage

F_TUSHIN Set at end of reception

F_BUSY

F_ERR

Set if transmission cannot be started by CTS input pin; cleared if transmission can be started

Set if receive error occurs

<Nesting level>

2 levels 5 bytes

Attribute Bytes

SADDR 1

SADDR 1

290

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

<Hardware used>

Serial interface channel 2 (UART mode)

<Initial setting>

OSMS=#00000001B ; Oscillation mode select register: does not use divider circuit

CLR1 P3.2

PM3=#

××××

10

×

B

; P31 = CTS input, P32 = RTS output

BRGC=#10001011B ; Sets baud rate to 9600 bps (error: 1.14%)

CSIM2=#00000000B ; Sets 0 to serial operation mode register 2 when UART is used

ASIM=#11001101B ; Sets asynchronous serial interface mode register

CLR1 SRIF ; Clears reception end receive error interrupt request flags

CLR1 SERIF

SET1 STIF

CLR1 SRMK

CLR1 SERMK

; Sets transmission end interrupt request flag (to end transmission)

; Enables reception end and receive error interrupts

Caution Before starting transmission, check the transmission end interrupt request flag (STIF) so that transmission is not executed during transmission. Therefore, set the transmission end interrupt request flag (STIF) after reset and start.

Remark To use the transmission end interrupt (to generate the interrupt request), use an additional flag.

Set the additional flag as the initial setting. Clear the flag at the start of transmission, and set it in the interrupt processing.

<Starting>

Store the transmit data to the SOSHIN area at the start of transmission and call the S_SOSHIN routine.

291

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(2) Example of use

EXTRN

EXTRN

EXTBIT F_TUSHIN,F_ERR,F_BUSY

;

RTS_0 EQU P3.2

;

S_SOSHIN

SOSHIN,JUSHIN

;

OSMS=#00000001B

CLR1

CLR1

CLR1

SET1

CLR1

CLR1

EI

RTS_0

PM3=#11111011B

BRGC=#10001011B

CSIM2=#00000000B

ASIM=#11001101B

SERIF

SRIF

STIF

SERMK

SRMK

; RTS output port

; Does not use divider circuit

;

; P31 = CTS input, P32 = RTS output

; 9600 bps (error: 1.41%)

; Initial setting when UART is used

; Enables receive error interrupt. Stop bit: 2 bits

; Transmit data: 8 bits. No parity. Enables reception and transmission.

;

; Clears receive error interrupt request flag

; Clears reception end interrupt request flag

; Sets transmit end interrupt request flag

;

Ends transmission

; Enables receive error interrupt

; Enables reception end interrupt

.

.

.

.

if_bit(transmission request)

SOSHIN=A

CALL !S_SOSHIN

; Sets transmission request flag?

; Stores transmit data

; Calls transmit routine endif if_bit(F_BUSY)

.

Communication busy processing

;

.

; End of transmission?

endif

;

.

.

if_bit(F_TUSHIN)

CLR1 F_TUSHIN

A=JUSHIN

.

Reception processing

.

CLR1 endif

.

.

RTS_0

;

;

; Sets reception end flag?

; Clears reception end flag

; Reads receive data

; RTS output pin

“L” (ready status) if_bit(F_ERR)

CLR1

.

F_ERR

Receive error processing

.

endif

.

.

;

;

;

; Receive error occurs?

292

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(3) SPD chart

S_SOSHIN (if: previous transmission ends ?)

THEN

THEN

(if: transmission enabled ?)

Clears transmit busy flag

Clears transmit end interrupt request flag

ELSE

TXS

transmit data

Sets transmit busy flag

ELSE

Sets transmit busy flag

INTSR

INTSER

Selects register bank 3

RTS output pin

"H" (sets busy status)

JUSHIN

RXB (loads receive data)

Sets reception end flag

Selects register bank 3

A

RXB (loads receive error data)

Sets receive error flag

293

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(4) Program list

PUBLIC S_SOSHIN

PUBLIC SOSHIN,JUSHIN

PUBLIC F_TUSHIN,F_ERR,F_BUSY

;

VESR

VESER

CSEG

DW

CSEG

DW

AT 1AH

INTSR

AT 18H

INTSER

;

RTS_0

CTS_I

;

EQU

EQU

P3.2

P3.1

; RTS output port

; CTS input port

UARTRAM

SOSHIN:

JUSHIN:

DSEG

DS

DS

SADDR

1

1

;

UARTFLG

F_TUSHIN

F_BUSY

BSEG

DBIT

DBIT

DBIT F_ERR

;

;************************************

; Transmission routine

; Transmit data storage area

; Receive data storage area

; Reception end flag

; Communication busy flag

; Reception error flag

;************************************

UARTPR0 CSEG

S_SOSHIN: if_bit(STIF) else if_bit(!CTS_I) else

TXS=SOSHIN (A)

CLR1 endif

SET1 endif

CLR1

SET1

STIF

F_BUSY

F_BUSY

F_BUSY

RET

;************************************

;

;

;

; Previous transmission end?

; Enables transmission?

; Clears transmit end interrupt request flag

; Stores transmit data

; Clears transmit busy flag

;

;

; Disables transmission

→ sets transmission busy flag

; Reception end routine

;************************************

INTSR:

SEL RB3

SET1

JUSHIN=RXB (A)

SET1

RETI

RTS_0

F_TUSHIN

;

; RTS

H

; Loads receive data

;

; Sets reception end flag

;************************************

; Reception error routine

;************************************

INTSER:

SEL

A=RXB

RB3

F_ERR

; Selects bank 3

; Reads error data

;

; Sets receive error flag

SET1

RETI

END

294

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

(f) Limitation when using UART mode

In the UART mode, the reception completion interrupt (INTSR) occurs a certain time after the reception error interrupt (INTSER) has occurred and cleared. As a result, the following phenomenon may take place.

Description

If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion interrupt (INTSR) does not occur when a reception error occurs. If the receive buffer register

(RXB) is read at certain timing (a in Figure 8-42) during reception error interrupt (INTSER) processing, the internal error flag is cleared to 0. Therefore, it is judged that a reception error has not occurred, and INTSR, which should not occur, occurs. Figure 8-42 illustrates this operation.

Figure 8-42. Timing of Reception Completion Interrupt (when ISRM = 1)

f

SCK

INTSER (when framing overrun error occurs)

Error flag

(internal flag) a

INTSR

Interrupt routine of CPU

Cleared when RXB is read

Reads RXB

It is judged that receive error has not occurred, and INTSR occurs.

Remark

ISRM : Bit 1 of asynchronous serial interface mode register (ASIM) f

SCK

: Source clock of 5-bit counter of baud rate generator

RXB : Receive buffer register

To prevent this phenomenon, take the following measures:

Preventive measures

In case of framing error or overrun error

Disable the receive buffer register (RXB) from being read for a certain period (T2 in Figure 8-43) after the receive error interrupt (INTSER) has occurred.

In case of parity error

Disable the receive buffer register (RXB) from being read for a certain period (T1 + T2 in Figure

8-43) after the reception error interrupt (INTSER) has occurred.

295

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

Figure 8-43. Receive Buffer Register Reading Disabled Period

RxD (input) D6 D7 Parity

STOP

START

D0 D1 D2

INTSR

INTSER (when framing or overrun error occurs)

INTSER (when parity error occurs)

T1 T2

T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate)

T2: Time of two source clocks (f

SCK

) of 5-bit counter selected by BRGC

Example of preventive measures

An example of preventive measures is shown below.

[Condition]

f

X

= 5.0 MHz

Processor clock control register (PCC) = 00H

Oscillation mode select register (OSMS) = 01H

Baud rate generator control register (BRGC) = 80H (2400 bps is selected as baud rate) t

CY

= 0.4

µ s (t

CY

= 0.2

µ s)

1

T1 = = 833.4

µ s

2400

T2 = 12.8

×

2 = 25.6

µ s

T1 + T2

= 4295 (clocks) t

CY

296

CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE

[Example]

Main processing

INTSER occurs

7 CPU clocks (min.)

(time from interrupt request to processing)

EI

UART receive error interrupt (INTSER) processing

Instructions of 4288

CPU clocks (MIN.) are necessary

MOV A, RXB

RETI

297

[MEMO]

298

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

The A/D converter of the 78K/0 series is a successive approximation type with an 8-bit resolution and eight channels. Although only a select mode is supported as the operation mode, conversion can be started by an external trigger. If the external trigger is not used, the analog data of a selected channel is repeatedly converted into a digital signal.

The A/D converter is set by the A/D converter mode register (ADM), A/D converter input select register (ADIS), external interrupt mode register 1 (INTM1), and A/D current cut select register (IEAD).

Caution IEAD is provided only to the

µ

PD78098 and 78098B subseries.

299

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Figure 9-1. Format of A/D Converter Mode Register

(

µ

PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y,

780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,

µ

PD78070A, 78070AY)

Symbol

ADM

7

CS

6

TRG

5

FR1

4

FR0

3 2 1

ADM3 ADM2 ADM1

0

HSC

Address

FF80H

At reset

01H

R/W

R/W

ADM3 ADM2 ADM1

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Selects analog input channel

FR1

1

1

0

0

Others

FR0

0

1

0

0

HSC Selects A/D conversion time

Note 1

At f

X

= 5.0 MHz At f

X

= 4.19 MHz

MCS = 1

1

80/f

X

(setting prohibited)

Note 2

1

40/f

X

(setting prohibited)

Note 2

0

50/f

X

(setting prohibited)

Note 2

1 100/f

X

(20.0

µ s)

160/f

X

MCS = 0

(32.0

µ s) 80/f

X

MCS = 1

(19.1

µ s)

80/f

X

(setting prohibited)

Note 2

40/f

X

(setting prohibited)

Note 2

100/f

X

(20.0

200/fx (40.0

µ

µ s) s)

50/f

X

(setting prohibited)

Note 2

100/f

X

(23.8

µ s)

MCS = 0

160/f

X

(38.1

µ s)

80/f

X

(19.1

µ s)

100/f

X

(23.8

µ s)

200/f

X

(47.7

µ s)

Setting prohibited

TRG

0

1

Selects external trigger

No external trigger (software start)

Conversion started by external trigger (hardware start)

CS

0

1

Stops operation

Starts operation

Controls A/D conversion operation

Notes 1. Set the A/D conversion time to 19.1

µ s or longer.

2. These settings are prohibited because the A/D conversion time is less than 19.1

µ s.

Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or

STOP instruction.

2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation.

Remarks 1. f

X

: main system clock oscillation frequency

2. MCS : bit 0 of the oscillation mode select register (OSMS)

300

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Figure 9-2. Format of A/D Converter Mode Register (

µ

PD78098, 78098B subseries)

Symbol

ADM

7

CS

6

TRG

5

FR1

4

FR0

3 2 1

ADM3 ADM2 ADM1

0

HSC

Address

FF80H

At reset

01H

Selects analog input channel ADM3 ADM2 ADM1

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

R/W

R/W

FR1 FR0 HSC

0 0 1

0

1

1

0

1

0

1

Others

0 1

Selects A/D conversion time

Note 1

80/f

XX

(20.0

µ s)

40/f

XX

(setting prohibited)

Note 2

50/f

XX

(setting prohibited)

Note 2

100/f

XX

(25.0

µ s)

Setting prohibited

TRG

0

1

Selects external trigger

No external trigger (software start)

Conversion started by external trigger (hardware start)

CS

0

1

Stops operation

Starts operation

Controls A/D conversion operation

Notes 1. Set the A/D conversion time to 19.1

µ s or longer.

2. These settings are prohibited because the A/D conversion time is less than 19.1

µ s.

Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or

STOP instruction.

2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation.

Remarks 1. f

XX

: main system clock frequency

2. ( ) : f

XX

= 4.0 MHz

301

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Figure 9-3. Format of A/D Converter Mode Register (

µ

PD780018, 780018Y subseries)

Symbol

ADM

7

CS

6

TRG

5

FR1

4

FR0

3 2 1

ADM3 ADM2 ADM1

0

HSC

Address

FF80H

At reset

01H

Selects analog input channel ADM3 ADM2 ADM1

0 0 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

R/W

R/W

FR1 FR0 HSC

0

0

1

1

Others

0

1

0

0

1

1

0

1

At f

X

= 5.0 MHz

80/f

X

(setting prohibited)

Note 2

40/f

X

(setting prohibited)

Note 2

50/f

X

(setting prohibited)

Note 2

100/f

X

(20.0

µ s)

Setting prohibited

Selects A/D conversion time

Note 1

At f

X

= 4.19 MHz

80/f

X

(19.1

µ s)

40/f

X

(setting prohibited)

Note 2

50/f

X

(setting prohibited)

Note 2

TRG

0

1

Selects external trigger

No external trigger (software start)

Conversion started by external trigger (hardware start)

CS

0

1

Stops operation

Starts operation

Controls A/D conversion operation

Notes 1. Set the A/D conversion time to 19.1

µ s or longer.

2. These settings are prohibited because the A/D conversion time is less than 19.1

µ s.

Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or

STOP instruction.

2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation.

Remark f

X

: main system clock oscillation frequency

302

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Symbol

ADIS

7

0

6

0

5

0

Figure 9-4. Format of A/D Converter Input Select Register

4

0

3 2 1 0

ADIS3 ADIS2 ADIS1 ADIS0

Address

FF84H

At reset

00H

R/W

R/W

ADIS3 ADIS2 ADIS1 ADIS0

0

0

0

0

0

0

0

0

1

Others

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Selects number of analog input channels

No analog input channel

(P10-P17)

1 channel (ANl0, P11-P17)

2 channels (ANl0, ANl1,

P12-P17)

3 channels (ANl0-ANl2,

P13-P17)

4 channels (ANl0-ANl3,

P14-P17)

5 channels (ANl0-ANI4,

P15-P17)

6 channels (ANl0-ANI5,

P16-P17)

7 channels (ANI0-ANl6, P17)

8 channels (ANI0-ANI7)

Setting prohibited

Cautions 1. Set analog input channels in the following steps:

<1> Set the number of analog input channels by using ADIS.

<2> Select one channel whose data is to be converted, from the channels selected by ADIS, by using the A/D converter mode register (ADM).

2. The internal pull-up resistor is not used to the channel selected by ADIS as an analog input channel, regardless of the value of the bit 1 (PUO1) of the pull-up resistor option register L

(PUOL).

303

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Figure 9-5. Format of External Interrupt Mode Register 1

(

µ

PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F,

78058FY, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY)

Symbol

INTM1

7

ES71

6

ES70

5

ES61

4

ES60

3 2

ES51 ES50

1

ES41

0

ES40

Address

FFEDH

At reset

00H

R/W

R/W

ES41

0

0

1

1

ES40

0

1

0

1

Selects valid edge of INTP3

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES51

0

0

1

1

ES50

0

1

0

1

Selects valid edge of INTP4

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES61

0

0

1

1

ES60

0

1

0

1

Selects valid edge of INTP5

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES71

0

0

1

1

ES70

0

1

0

1

Selects valid edge of INTP6

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

304

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Symbol

INTM1

7

0

6

0

Figure 9-6. Format of External Interrupt Mode Register 1

(

µ

PD78064, 78064Y, 780058, 780058Y, 780308, 780308Y, 78064B subseries)

5 4 3 2 1 0 Address At reset R/W

ES61 ES60 ES51 ES50 ES41 ES40 FFEDH 00H R/W

ES41

0

0

1

1

ES40

0

1

0

1

Selects valid edge of INTP3

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES51

0

0

1

1

ES50

0

1

0

1

Selects valid edge of INTP4

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES61

0

0

1

1

ES60

0

1

0

1

Selects valid edge of INTP5

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

305

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Symbol

INTM1

7

0

Figure 9-7. Format of External Interrupt Mode Register 1 (

µ

PD78083 subseries)

6

0

5

0

4

0

3

0

2

0

1

ES41

0

ES40

Address

FFEDH

At reset

00H

R/W

R/W

ES41

0

0

1

1

ES40

0

1

0

1

Selects valid edge of INTP3

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Caution Be sure to clear bits 2 through 7 to 0.

Figure 9-8. Format of A/D Current Cut Select Register (

µ

PD78098, 78098B subseries)

Symbol

IEAD

7

0

6

0

5

0

4

0

3

0

2

0

1

0

0

IEAD0

Address

F8E2H

At reset

00H

R/W

R/W

IEAD0 Controls connection between AV

DD

and AV

REF0

0 Disconnects AV

DD

from AV

REF0

1 Connects AV

DD

and AV

REF0

306

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

9.1 Level Meter

In this application example, the analog voltage input to the A/D converter is displayed on an LED matrix consisting of 4

×

4, i.e., 16 LEDs.

Because a level meter has been included in this example, the LED display is given in decibel units. Figure 9-9 shows the circuit of the level meter, and Figure 9-10 shows the relations between the result of the A/D conversion and the number of display digits.

Figure 9-9. Example of Level Meter Circuit

ANIn P64

P65

P66

P67

P60

P61

P62

P63

=

Figure 9-10. A/D Conversion Result and Display

LED(Units)

7

6

5

9

8

2

1

4

3

16

15

14

13

12

11

10

0 0AH

–22

12H

–17

20H

–12

2EH

–9

39H

–7

40H

–6

48H

–5

51H

–4

5BH

–3

66H

–2

72H

–1

80H

0

90H

1

A2H

2

B5H

3

FFH

6

Display value

[dB]

307

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

The level meter in this example operates with specifications <1> through <3> below.

<1> Measurement method

A/D conversion is performed every 20 ms, and the average value of four previous data is calculated and displayed on the LEDs.

<2> Display method

The LED display is updated every 20 ms. The LED matrix consists of 4

×

4 = 16 LEDs and performs dynamic display. For the dynamic display, 8-bit timer/event counter 1 (interval time: 2 ms) is used.

<3> Peak hold

Holding the maximum display level for a specific period (1 second) is called peak hold. Even if the display level drops during a specific period, only the LED at the maximum display level is held. Therefore, the hold period of the hold level is 20 ms to 1 s.

Figure 9-11. Concept of Peak Hold

Specific period (1 second)

Hold level 6 6 6 6 7 8 9 9 9 9 9 9 4 4 4 5 6 6

Display level 6 5 4 5 7 8 9 8 7 6 5 5 4 3 3 5 6 2

(1) Description of package

<Public declaration symbol>

LEVEL : Name of LED display subroutine

DSPLEV : Display level storage area

HLDLEV : Hold level storage area

CT20MS : Counter measuring 20 ms

CT1S : Counter measuring 1 s

<Register used>

AX, HL, BC (subroutine processing)

Bank 0: A, HL, B (interrupt processing)

308

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

<RAM used>

Name

ADDAT

DSPLEV

HLDLEV

CT20MS

CT1S

DIGCNT

DSPDAT

WORKCT

Usage

Stores A/D conversion value

Stores display level

Stores hold level

Counter measuring 20 ms

Counter measuring 1 s

Display digit counter

Stores display data

Work counter for loop processing

<Flag used>

Name

T20MSF

T1SF

Set every 20 ms

Set every 1 s

Usage

Attribute

SADDR

Bytes

4

1

4

1

<Nesting>

2 levels 5 bytes

<Hardware used>

A/D converter

8-bit timer/event counter 1

P6

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

ADM = #1000

×××

1B ; Selects channel of A/D converter and starts operation

TCL1 = #10111011B ; Interval time of 2 ms of 8-bit timer/event counter 1

TMC1 = #00000001B

CR10 = 130

P6 output mode

Makes P6 output latch low

Enables INTTM1 interrupt

309

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

<Starting>

This program performs two types of processing: A/D conversion (subroutine) and LED display (interrupt).

A/D conversion processing

Call LEVEL at least once every 20 ms from the main processing. The LEVEL processing performs A/D conversion processing only when 20 has elapsed.

LED display

The 4

×

4 LED matrix performs dynamic display by using the interrupt processing of 8-bit timer/event counter 1 (interval: 2 ms). The interrupt processing of 8-bit timer/event counter 1 sets the T20MSF (loading of A/D conversion value) and T1SF (end of hold period) used for the A/D conversion processing at an interval of 2 ms.

(2) Example of use

EXTRN LEVEL,CT20MS,CT1S

MOV

MOV

MOV

CLR1

CT20MS,#10

CT1S,#50

TMC2,#00100110B

TMMK3

; Turns OFF LED display

P6=#00H

PM6=#00000000B

OSMS=#00000001B

ADM=#10000001B

TCL1=#10111011B

; Does not use divider circuit

; ANI0 pin starts operation

; Sets 8-bit timer/event counter 1 to 2 ms

CR10=#130

TMC1=#00000001B

CLR1 TMMK1

EI

; Enables 8-bit timer/event counter 1 interrupt

310

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(3) SPD chart

LEVEL

INTTM1

THEN

IF: 20 ms elapses (T20MSF = 1)

Clears T20MSF

Stores A/D conversion value to memory

Averages four previous A/D conversion values

(FOR: WORKCT = #0; WORKCT < #16; WORKCT + +)

IF: conversion result > display level comparison data

THEN

Updates comparison data

ELSE

BREAK

Stores display data to memory

IF: less then 1 second (T1SF = 0)

THEN

THEN

IF: hold level < display level

Sets display level to hold level

ELSE

Clears T1SF

Sets display level to hold level

Converts display level and hold level to segment signal

Stores digit signal and segment signal to memory in combination

Selects register bank 0

Outputs OFF signal to digit and segment

Outputs memory contents indicated by digit counter

Increments digit counter

Decrements 20 ms counter

IF: 20 ms elapses (CT20MS = 0)

THEN

Sets 20 ms counter to 10

Sets 20 ms elapse status

Sets T20MSF

Decrements 1-s counter

THEN

IF: 1 second elapses (CT1S = 0)

Sets 1-s counter to 50

Sets 1-s elapse status

Sets T1SF

311

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(4) Program list

PUBLIC LEVEL,HLDLEV,DSPLEV,CT20MS,CT1S

AD_DAT DSEG

ADDAT: DS

DSPLEV: DS

HLDLEV: DS

CT20MS: DS

CT1S: DS

DIGCNT: DS

DSPDAT: DS

WORKCT: DS

SADDR

4

1

1

1

1

1

4

1

; A/D conversion result storage area

; Display level value

; Hold level value

; 20 ms counter

; 1 s counter

; Display digit counter

; Display data

AD_FLG BSEG

T20MSF DBIT

T1SF DBIT

; Measures 20 ms

; Measures 1 s

VETM1 CSEG

DW

AT 24H

INTTM1

; Sets vector address of 8-bit timer/event counter 1

AD_SEG CSEG

;*********************************

* Sets level meter data

;*********************************

LEVEL:

IF_BIT(T20MSF)

CLR1 T20MSF

A=ADCR

A<->ADDAT

A<->ADDAT+1

A<->ADDAT+2

A<->ADDAT+3

; Checks 20 ms

; Inputs A/D conversion value

; Stores A/D conversion value

; Averages four A/D conversion values

AX=#0H

HL=#ADDAT for(WORKCT=#0;WORKCT<#4;WORKCT++)

A+=[HL] next

HL++ if_bit(CY)

X++ endif

; Data storage address

; Carry

; Higher digit

A<->X

C=#4

AX/=C if(C>=#2) (A)

X++ endif

; Averages four values

; AX/C = AX (quotient) ... C (remainder)

; Remainder processing (2 or higher is carried)

; Carry processing

HL=#LEVTBL

B=#0 for(WORKCT=#0;WORKCT<#16;WORKCT++)

; Conversion result storage register if(X>=[HL+B]) (A)

; Compares data

B++ else break next endif

312

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

DSPLEV=B (A)

HL=#DSPDAT

A=C

A&=#0FH

A|=#00010000B

[HL]=A

HL++

A=C

A>>=1

A>>=1

A>>=1

A>>=1

A&=#0FH

A|=#00100000B

[HL]=A

HL++

A=B

A&=#0FH

A|=#01000000B

[HL]=A

HL++

A=B

A>>=1

A>>=1

A>>=1

A>>=1

A&=#0FH

A|=#10000000B

[HL]=A endif if_bit(!T1SF)

X=HLDLEV (A) if(X<DSPLEV) (A)

HLDLEV=DSPLEV (A) endif else

CLR1 T1SF

HLDLEV=DSPLEV (A) endif

HL=#DSPTBL

A=DSPLEV

A+=A

B=A

A=HLDLEV

A+=A

C=A

X=[HL+B] (A)

B++

A=[HL+B]

HL=#HLDTBL

A<->X

A|=[HL+C]

A<->X

C++

A|=[HL+C]

BC=AX

; Determines display data

; 1 s (hold level updated)

; Compares hold and display levels

; Creates display level

; Creates hold level

; Sets segment signal of first digit

; Sets digit signal

; Sets segment signal of second digit

; Sets digit signal

; Sets segment signal of third digit

; Sets digit signal

; Sets segment signal of fourth digit

; Sets digit signal

313

314

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

RET

LEVTBL:

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DSPTBL:

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

HLDTBL:

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

DW

$EJECT

0AH

12H

20H

2EH

39H

40H

48H

51H

5BH

66H

72H

80H

90H

0A2H

0B5H

0FFH

0000000000000000B

0000000000000001B

0000000000000011B

0000000000000111B

0000000000001111B

0000000000011111B

0000000000111111B

0000000001111111B

0000000011111111B

0000000111111111B

0000001111111111B

0000011111111111B

0000111111111111B

0001111111111111B

0011111111111111B

0111111111111111B

1111111111111111B

0000000000000000B

0000000000000001B

0000000000000010B

0000000000000100B

0000000000001000B

0000000000010000B

0000000000100000B

0000000001000000B

0000000010000000B

0000000100000000B

0000001000000000B

0000010000000000B

0000100000000000B

0001000000000000B

0010000000000000B

0100000000000000B

1000000000000000B

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

;*********************************

* Level meter data

;*********************************

TM1_SEG CSEG

INTTM1:

SEL RB0

; Turns OFF digit and segment signals

P6=#00000000B

HL=#DSPDAT

B=DIGCNT (A)

P6=[HL+B] (A)

DIGCNT++

DIGCNT&=#00000011B

; 20 ms?

CT20MS-if(CT20MS==#0)

CT20MS=#10

SET1

CT1S--

T20MSF endif

RETI if(CT1S==#0)

CT1S=#50

SET1 endif

T1SF

; Sets initial counter value

; 1s?

; Sets initial counter value

315

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

9.2 Thermometer

In this application example, a temperature in a range of –20

°

C to +50

°

C is measured by using a thermistor (6 k

/

0

°

C) as a temperature sensor. Changes in the resistance of the thermistor with respect to temperature are given by the following expression:

R = R

0 exp { B (1/T – 1/T

0

) } where,

R : resistance at given temperature T [

°

K]

T : given temperature [

°

K]

R

0

: resistance at reference temperature T

0

[

°

K]

T

0

: reference temperature [

°

K]

B : constant obtained by reference temperature T

0

[

°

K] and T

0

[

°

K]

Constant B changes with the temperature. This constant can be calculated by changing the above expression as follows:

1

B = In

(1/T–1/T

0

)

R

R

0

Figure 9-12 shows a circuit example. This circuit is designed to input 0 V at –20

°

C, and 5 V at + 50

°

C.

Figure 9-12. Circuit Example of Thermometer

Th

+

ANIn

µ

PD78054

316

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Because the characteristic of the thermistor is non linear in this example, the input analog voltage is not converted to a temperature in a range of –20

°

C to +50

°

C through calculation but by comparison with table data. This conversion result is stored to RAM (DSPDAT) as 2-digit BCD. Figure 9-13 shows the characteristics of the thermistor, and Table

9-1 shows the relations between temperature and A/D conversion value.

To measure the temperature, four conversion values are averaged and converted to a temperature. The result of the conversion is stored in a display area. Therefore, the data is updated once every four times. For example, if measurement processing is executed every 250 ms, the display updating cycle is 1 second.

Figure 9-13. Temperature vs. Output Characteristic

50

40

70

60

(%)

100

90

80

30

20

10

0

–20 –10 0 40 50 (°C) 10 20

Temperature

30

317

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

1F

23

26

2A

12

16

19

1C

Conversion Temperature

Value [

°

C]

00 –20.0

01

04

–19.5

–18.5

07

0A

0C

0F

–17.5

–16.5

–15.5

–14.5

2D

31

35

–5.5

–4.5

–3.5

–13.5

–12.5

–11.5

–10.5

–9.5

–8.5

–7.5

–6.5

Table 9-1. A/D Conversion Value and Temperature

64

69

6D

71

54

58

5C

60

Conversion Temperature Conversion

Value [

°

C] Value

38 –2.5

82

3C

40

–1.5

–0.5

86

8B

44

48

4C

50

0.5

1.5

2.5

3.5

8F

93

97

9B

75

7A

7E

4.5

5.5

6.5

7.5

8.5

9.5

10.5

11.5

12.5

13.5

14.5

BF

C3

C7

B0

B4

B7

BB

9F

A3

A8

AC

26.5

27.5

28.5

29.5

22.5

23.5

24.5

25.5

Temperature

[

°

C]

15.5

16.5

17.5

18.5

19.5

20.5

21.5

30.5

31.5

32.5

F0

F3

F6

F9

E3

E7

EA

ED

Conversion Temperature

Value [

°

C]

CB 33.5

CE

D2

34.5

35.5

D6

D9

DC

E0

36.5

37.5

38.5

39.5

FC

FE

FF

48.5

49.5

50.0

44.5

45.5

46.5

47.5

40.5

41.5

42.5

43.5

(1) Description of package

<Public declaration symbol>

THMETER : Thermometer subroutine call name

DSPDAT : Display data storage area

CNTPRO : Test counter counting number of inputs

MINUSF : Minus temperature display flag

T250MSF : 250-ms setting flag

<Register used>

AX, BC, HL

318

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

<RAM used>

Name

ADDAT

DSPDAT

CNTPRO

WORKCT

Usage

Stores A/D conversion value

Stores display data

Test counter for number of inputs

Work counter for loop processing

<Flag used>

Name

T250MSF

MINUSF

Usage

Executes measurement processing when set

Set when temperature is below zero

Attribute

SADDR

Bytes

4

2

1

<Nesting>

1 level 2 bytes

<Hardware used>

A/D converter

<Initial setting>

ADM = #1000

×××

1B; Selects A/D converter channel and starts operation

<Starting>

Set the T250MSF flag in each measurement cycle by using timer processing. After that, call THMETER at least once in measurement cycle.

319

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(2) Example of use

EXTRN THMETER,DSPDAT,CNTPRO

EXTBIT MINUSF,T250MSF

AD_DAT DSEG

CT250MS:DS

LEDD: DS

DIGCT: DS

SADDR

1

4

1

; 250 ms counter

; LED display area

; LED display digit counter

VETM3 CSEG

DW

AT 1EH

INTTM3

MOV TMC2,#00100110B

CLR1

.

.

.

.

TMMK3

CT250MS=#128

CNTPR0=#4

ADM=#10000011B

.

.

.

.

; Sets vector address of watch timer

; Sets watch timer to 1.95 ms

; Selects ANI1 pin and starts operation

;**********************************************

; Watch timer interrupt processing

; Interval time: 1.95 ms

;**********************************************

INTTM3:

.

.

.

.

; 1.95 ms interrupt processing

DBNZ

MOV

SET1

CT250MS,$RTNTM3

CT250MS,#128

T250MSF

; 250 ms elapses

RTNTM3:

.

.

.

.

RETI

320

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(3) SPD chart

THMETER

THEN

IF: 250 ms elapses (T250MS = 1)

Clears T250MS

Stores A/D conversion value to memory

IF: four values stored in memory

THEN

Averages four A/D conversion values

(FOR: WORKCT = #0; WORKCT < #70; WORKCT + +)

THEN

IF: conversion result > comparison data for temperature conversion

Updates comparison data

ELSE

THEN

BREAK

IF: minus temperature data

Sets minus status

Sets MINUSF

Converts temperature data to decimal number and stores in memory

321

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(4) Program list

PUBLIC THMETER,DSPDAT,CNTPR0,T250MSF,MINUSF

AD_DAT DSEG

ADDAT: DS

DSPDAT: DS

CNTPR0: DS

WORKCT: DS

AD_FLG BSEG

T250MSF DBIT

MINUSF DBIT

SADDR

4

2

1

1

; A/D conversion result storage area

; Display data

; Tests number of inputs

; Sets 250 ms

; Sets minus data

TH_SEG CSEG

;*********************************

* Sets temperature data

;*********************************

THMETER: if_bit(T250MSF)

CLR1

A=ADCR

T250MSF

A<->ADDAT

A<->ADDAT+1

A<->ADDAT+2

A<->ADDAT+3

A<->X

C=#4

AX/=C if(C>=#2) (A)

X++ endif

; 250 ms

CNTPR0-if(CNTPR0==#0)

CNTPR0=#4

AX=#0H

HL=#ADDAT for(WORKCT=#0;WORKCT<#4;WORKCT++)

A+=[HL]

; Data storage address next

HL++ if_bit(CY)

X++ endif

; Carry occurs

; Carry

; AX/C = AX (quotient) ... C (remainder)

; Remainder processing (2 digits or more carried)

; Carry processing

A=X

B=#0

HL=#THRTBL

; Converts to temperature data if(A==#0FFH)

B=#70 else for(WORKCT=#0;WORKCT<#70;WORKCT++) if(X>=[HL+B]) (A)

B++ else break next endif

322

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

endif

CLR1

A=#20

MINUSF

B–=A if_bit(CY)

SET1 MINUSF endif

X=#0

A=B

A=#0

A–=B

A<->B

A<->X

C=#10

AX/=C endif endif

RET

DSPDAT=C (A)

(DSPDAT+1)=X (A)

; Temperature data 20

; To decimal conversion

; Absolute value of data

; Decimal conversion

; Temperature data/10

; Updates display data

323

324

THRTBL;

;

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

0BBH

0BFH

0C3H

0C7H

0CBH

0CEH

0D2H

0D6H

9BH

9FH

0A3H

0A8H

0ACH

0B0H

0B4H

0B7H

7AH

7EH

82H

86H

8BH

8FH

93H

97H

58H

5CH

60H

64H

69H

6DH

71H

75H

38H

3CH

40H

44H

48H

4CH

50H

54H

1FH

23H

26H

2AH

2DH

31H

35H

1

4

7

0AH

0CH

0FH

12H

16H

19H

1CH

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

; 21.5

; 22.5

; 23.5

; 24.5

; 25.5

; 26.5

; 27.5

; 28.5

; 29.5

; 30.5

; 31.5

; 32.5

; 33.5

; 34.5

; 35.5

; 36.5

; 5.5

; 6.5

; 7.5

; 8.5

; 9.5

; 10.5

; 11.5

; 12.5

; 13.5

; 14.5

; 15.5

; 16.5

; 17.5

; 18.5

; 19.5

; 20.5

; –9.5

; –8.5

; –7.5

; –6.5

; –5.5

; –4.5

; –3.5

; –2.5

; –1.5

; –0.5

; +0.5

; 1.5

; 2.5

; 3.5

; 4.5

; –19.5

; –18.5

; –17.5

; –16.5

; –15.5

; –14.5

; –13.5

; –12.5

; –11.5

; –10.5

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

0D9H

0DCH

0E0H

0E3H

0E7H

0EAH

0EDH

0F0H

0F3H

0F6H

0F9H

0FCH

0FFH

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

; 37.5

; 38.5

; 39.5

; 40.5

; 41.5

; 42.5

; 43.5

; 44.5

; 45.5

; 46.5

; 47.5

; 48.5

; 49.5

325

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

9.3 Analog Key Input

In this example, sixteen keys are input by using the A/D converter. To input keys, a circuit must be designed so that a voltage peculiar to a key is input to the A/D converter when the key is pressed.

Because sixteen keys are input in this example, V

DD

is divided by 16 and the voltage of each key is converted into a key code. Table 9-2 shows the relations between the input voltages and key codes (00H through 0FH). When no key input is made, the key code is 10H.

Table 9-2. Input Voltage and Key Code

Input Voltage V A/D Conversion Value Key Code

GND 00-07H 00H

1/16V

DD

2/16V

DD

08-17H

18-27H

01H

02H

3/16V

DD

4/16V

DD

5/16V

DD

6/16V

DD

28-37H

38-47H

48-57H

58-67H

03H

04H

05H

06H

7/16V

DD

8/16V

DD

9/16V

DD

10/16V

DD

11/16V

DD

12/16V

DD

13/16V

DD

14/16V

DD

15/16V

DD

V

DD

68-77H

78-87H

88-97H

98-A7H

A8-B7H

B8-C7H

C8-D7H

D8-E7H

E8-F7H

F8-FFH

0BH

0CH

0DH

0EH

07H

08H

09H

0AH

0FH

10H

Figure 9-14 shows an example of the circuit that satisfies the above relations between the input voltages and key codes. Note, however, that this circuit gives a priority to the key with the lower number if two or more keys are pressed at the same time.

326

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

Figure 9-14. Example of Analog Key Input Circuit

V

DD

R0

K0

ANIn

R1

K1

µ

PD78054

K2

R2

K14

R14

R15

K15

Resistances R0 through R15 used in the circuit in Figure 9-14 can be calculated by the following expression: n

R

K

=

K=1 n

×

R0

16–n

Table 9-3 shows the resistances of R1 through R15 where R0 is 1 k

in the above expression (the calculation result of a resistance may slightly different from the resistance of commercial resistors indicated by a color code).

Table 9-3. Resistances of R1 through R5

Resistor No.

Resistance Value

Resistor No. Resistance Value

Resistor No. Resistance Value

R1 68 R6 150 R11 560

R2

R3

R4

R5

75

82

100

120

R7

R8

R9

R10

180

220

270

390

R12

R13

R14

R15

750

1.3 k

2.7 k

8.2 k

This program converts an input analog voltage into the corresponding key code shown in Table 9-2, absorbs chattering, and then stores the input voltage to RAM. To absorb chattering, a key code is assumed to be valid when it coincides with a given value five times in succession. For example, if an analog voltage is sampled every 5 ms, chattering of 20 to 25 ms is absorbed. If a key input is changed, a key change flag (KEYCHG) is set.

327

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(1) Description of package

<Public declaration symbol>

AKEYIN : Analog key input subroutine name

KEYDAT : Key code storage area

PASTDT : Key code storage area for chattering absorption

CHATCT : Chattering absorption counter

KEYCHG : Key change test flag

CHTENDF : Flag to test end of chattering absorption

KEYOFF : Key code when there is no key input

<Register used>

A

<RAM used>

Name

PASTDAT

KEYDAT

CHATCNT

Usage

Stores key code for chattering absorption

Stores key code

Chattering counter

Attribute

SADDR

Bytes

1

<Flag used>

Name

KEYCHG

CHTENDF

Usage

Set when key is changed

Sets when chattering absorption ends

<Nesting>

1 level 2 bytes

<Hardware used>

A/D converter

<Initial setting>

ADM = #1000

×××

1B; Selects A/D converter channel and starts operation

<Starting>

Call AKEYIN at fixed interval.

Input a key code after testing the key change flag. Note that this flag is not cleared by the subroutine and must be cleared after the flag has been tested.

328

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(2) Example of use

EXTRN

EXTRN

AKEYIN,KEYDAT,PASTDT,CHATCT

KEYOFF

EXTBIT KEYCHG,CHTENDF

VETM3 CSEG

DW

MAINDAT DSEG

CT5MS: DS

AT 1EH

INTTM3

SADDR

1

; Sets vector address of watch timer

TMC2=#00100110B

CLR1

CT5MS=#3

TMMK3

KEYDAT=#KEYOFF

PASTDT=#KEYOFF

CHATCT=#CHAVAL

CLR1

CLR1

CHTENDF

KEYCHG

ADM=#10000101B

EI

.

.

.

.

if_bit(KEYCHG)

CLR1 KEYCHG

; Sets OFF data as key data

; Sets number of times of chattering to five

; Selects ANI2 pin and starts operation

; Key changed?

; Key input processing endif

.

.

.

.

;**********************************************

; Watch timer interrupt processing

; Interval: 1.95 ms

;**********************************************

INTTM3:

; 1.95 ms interrupt processing

.

.

.

.

DBNZ

MOV

CALL

RTNTM3:

.

.

.

.

RETI

CT5MS,$RTNTM3

CT5MS,#3

!AKEYIN

; 1.95 ms

×

3 elapses

329

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(3) SPD chart

AKEYIN Inputs and adjusts A/D conversion value (adds 8)

IF: overflow occurs

THEN

Sets no key input status

ELSE

THEN

Decodes key

IF: key input not changed

IF: chattering being absorbed

THEN

THEN

IF: chattering absorption ends

Sets chattering absorption status

Sets CHTENDF

IF: valid key changed

ELSE

THEN

Updates key code

Sets key change status

Sets KEYCHG

Updates comparison key code

Sets chattering absorption start status

Clears CHTENDF

330

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(4) Program list

PUBLIC AKEYIN,KEYDAT,PASTDT

PUBLIC CHATCT,KEYOFF

PUBLIC KEYCHG,CHTENDF

AK_DAT DSEG SADDR

KEYDAT: DS

PASTDT: DS

CHATCT: DS

1

1

1

; Key data storage area

; Chattering key data

; Chattering counter

AK_FLG BSEG

KEYCHG DBIT

CHTENDF DBIT

KEYOFF EQU

CHAVAL EQU

; Key changed

; Chattering absorption end status

; OFF key data

; Number of times of chattering absorption

10H

5

AK_SEG CSEG

;******************************

* Analog key input

;******************************

AKEYIN:

A=ADCR

A+=#8 if_bit(CY)

A=#KEYOFF else

A>>=1

A>>=1

A>>=1

A>>=1

A&=0FH endif if(A==PASTDT) if_bit(!CHTENDF)

CHATCT-if(CHATCT==#0)

SET1 CHTENDF

A=PASTDT if(A!=KEYDAT)

KEYDAT=A

SET1 KEYCHG endif endif endif endif

PASTDT=A

CHATCT=#CHAVAL-1

CLR1 endif

CHTENDF

RET

; Inputs A/D conversion value

; Corrects data

; Sets no key input status

; Decodes key

; No key change

; Chattering being absorbed

; End of chattering absorption

; Sets chattering absorption status

; Valid key changed

; Updates key data

; Sets key change status

; Updates previous key data

; Starts chattering absorption

331

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

9.4 4-Channel Input A/D Conversion

This section describes the method to scan four channels for A/D conversion. The A/D conversion operation is started by the software.

The analog voltages input to the selected four channels are converted into digital signals. The result of the

A/D conversion of each channel is stored in RAM.

An interrupt request is generated by using 8-bit timer/event counter 1. The result of the conversion is loaded and channel is converted in the processing of this interrupt request. Because 8-bit timer/event counter 1 is set to 10 ms, it is not necessary to measure the wait time of the A/D conversion.

Caution To change the interrupt time, make the following setting:

• Set timer longer than A/D conversion end time + Interrupt entry return time + Interrupt processing time.

• Test flags that indicate the end of the conversion.

Figure 9-15. Timing Chart in 4-Channel Scan Mode

INTTM2

ADCR

10 ms

ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 ANI2 ANI3 ANI0

ADIn

0 1 2 3 0 1 2 3 0 1

332

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(1) Description of package

<Public declaration symbol>

Output parameter

M_CH0 : Stores conversion result of channel 0

M_CH1 : Stores conversion result of channel 1

M_CH2 : Stores conversion result of channel 2

M_CH3 : Stores conversion result of channel 3

<Register used>

A

<RAM used>

Name

M_CH0

M_CH1

M_CH2

M_CH3

M_MODE

Usage

Channel 0 conversion result storage area

Channel 1 conversion result storage area

Channel 2 conversion result storage area

Channel 3 conversion result storage area

Mode storage area

Attribute

SADDR

SADDR

SADDR

SADDR

SADDR

Bytes

1

1

1

1

1

<Nesting>

1 level 3 bytes

<Hardware used>

A/D converter

8-bit timer/event counter 1

Port 1 (P10-P13)

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

ADM = #1000

××××

B ; Selects A/D converter channel and starts operation

ADIS = #00000100B ; Selects number of A/D converter channels

TCL1 = #00001110B ; Interval time of 8-bit timer/event counter 1: 10 ms

TMC1 = #00000001B

CR10 = #81

Enables TMMK1 interrupt

333

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(2) Example of use

EXTRN M_CH0,M_CH1,M_CH2,M_CH3,M_MODE

;******************************************

; Initialize

;******************************************

M4 CSEG ;

RES_STA:

SEL RB0

DI

.

.

.

.

;

;

OSMS=#00000001B

ADM=#10000001B

ADIS=#00000100B

CR10=#81

TCL1=#00001110B

TMC1=#00000001B

CLR1

CLR1

EI

TMIF1

TMMK1

M_MODE=#0

; Does not use divider circuit

; Starts A/D operation and selects external trigger channel 0

; Selects analog input channel 4

; Sets modulo register 81

; Count clock: 8.2 kHz

; Enables 8-bit timer/register 1 operation

; Clears timer 1 interrupt request flag

;

; Enables timer 1 interrupt

; Sets initial value (0 channel) to mode area

.

.

; while(forever)

.

.

A=M_CH0

.

.

; A

data of channel 0

A=M_CH1

.

.

; A

data of channel 1

A=M_CH2

.

.

; A

data of channel 2

A=M_CH3

.

.

; A

data of channel 3

(3) SPD chart

[A/D conversion processing]

KASAN Loads conversion result of channel for previous A/D conversion

Changes channel

ADM

selects changed channel

334

CHAPTER 9 APPLICATIONS OF A/D CONVERTER

(4) Program list

;********************************************

; A/D conversion

;********************************************

;

$PC(054)

;

;

PUBLIC M_CH0,M_CH1,M_CH2,M_CH3,M_MODE

;

VEINTM1 CSEG AT 24H

;

DW KASAN

;********************************************

; RAM definition

;********************************************

M_CH0:

DSEG

DS

SADDR

1

M_CH1:

M_CH2:

M_CH3:

M_MODE:

DS

DS

DS

DS

1

1

1

1

; Area for channel 0 addition

; Area for channel 1 addition

; Area for channel 2 addition

; Area for channel 3 addition

; Mode storage area

;

CSEG

;

KASAN:

SEL RB2 switch(M_MODE) case 0: case 1: case 2: ends

RETI

END

M_CH0=ADCR (A)

M_MODE++

ADM=#10000011B break

M_CH1=ADCR (A)

M_MODE++

ADM=#10000101B break

M_CH2=ADCR (A)

M_MODE++

ADM=#10000111B break case 3:

M_CH3=ADCR (A)

M_MODE=#0

ADM=#10000001B break

; Selects bank 2

; Channel currently selected?

;

; Channel 0:

Transfers conversion result to RAM

;

;

;

;

Select channel 1:

;

; Channel 1:

Transfers conversion result to RAM

;

;

;

;

;

; Selects channel 2

;

; Channel 2:

Transfers conversion result to RAM

;

;

;

;

Selects channel 3

;

; Channel 3:

Transfers conversion result to RAM

Selects channel 0

335

[MEMO]

336

CHAPTER 10 APPLICATIONS OF D/A CONVERTER

The D/A converter of the 78K/0 series consists of two voltage output type D/A converter channels with an 8-bit resolution. This D/A can be used in two modes: normal mode and real-time output mode. In the normal mode, the output trigger is writing data to the D/A conversion value setting registers 0 and 1 (DACS0 and 1). In the real-time output mode, the output is triggered by the interrupt requests (INTTM1 and 2) of 8-bit timer/event counters 1 and 2.

In this mode, set data to DACS0 and DACS1 after an output trigger has been generated until the next output trigger is generated.

The D/A converter is set by the D/A converter mode register.

Figure 10-1. Format of D/A Converter Mode Register

Symbol

DAM

7

0

6

0

5 4

DAM5 DAM4

3

0

2

0

1 0

DACE1 DACE0

Address

FF98H

At reset

00H

R/W

R/W

DACE0 Controls D/A converter channel 0

0 Stops D/A conversion operation

1 Enables D/A conversion operation

DACE1 Controls D/A converter channel 1

0 Stops D/A conversion operation

1 Enables D/A conversion operation

DAM4 Operation mode of D/A converter channel 0

0 Normal mode

1 Real-time output mode

DAM5 Operation mode of D/A converter channel 1

0 Normal mode

1 Real-time output mode

Cautions 1. To use the D/A converter, set the multiplexed port pins in the input mode and disconnect the pull-up resistor.

2. Be sure to clear bits 2, 3, 6, and 7 to 0.

3. The output goes into a high-impedance state when D/A conversion operation is stopped.

4. The output trigger in the real-time output mode is INTTM1 for channel 0 and INTTM2 for channel 1.

337

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

10.1 SIN Wave Output

This section introduces an example that outputs a SIN wave with a frequency of 50 Hz by using the real-time output mode of D/A converter channel 0.

After the output operation has been started, an analog value resulting from the D/A conversion specified by the

D/A conversion value setting register 0 (DACS0) is output, and the next output data is set to DACS0 by interrupt processing. The value set by the interrupt processing is output at the next timing of 8-bit timer/event counter 1.

Figure 10-2 shows the output data writing timing and analog output timing.

Figure 10-2. Analog Output and Output Data Storage Timing

8-bit timer interrupt request

Writing output data

D1 D2 D3 D4 D5 D6 D7 D8

Analog output

D0 D1 D2 D3 D4 D5 D6 D7

The interval time of 8-bit timer/event counter 1 is set to about 668

µ s and a 50-Hz D/A output wave is generated as shown in Figure 10-3.

The SIN wave output data is stored in ROM. Data are sequentially referenced by the interrupt processing of 8bit timer/event counter 1 and written to DACS0.

Table 10-1 shows the voltages for SIN wave output and set values.

Figure 10-3. D/A Output Waveform

[V]

5

4

3

2

1

0

24 48 72 96 120 144 168 192 216 240 264 288 312 336 360

Degree [degree]

338

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

132

144

156

168

84

96

108

120

Degree

0

12

24

36

48

60

72

Table 10-1. Voltage of SIN Wave Output and Preset Value

4.9863

4.9863

4.8776

4.6651

4.3579

3.9695

3.5168

3.0200

Voltage (V)

2.5000

3.0200

3.5168

3.9695

4.3579

4.6651

4.8776

FFH

FFH

FAH

EFH

DFH

CBH

B4H

9BH

Set Value

80H

9BH

B4H

CBH

DFH

EFH

FAH

312

324

336

348

264

276

288

300

Degree

180

192

204

216

228

240

252

0.0137

0.0137

0.1224

0.3349

0.6421

1.0305

1.4832

1.9802

Voltage (V)

2.5000

1.9802

1.4832

1.0305

0.6421

0.3349

0.1224

21H

35H

4CH

65H

01H

01H

06H

11H

Set Value

80H

65H

4CH

35H

21H

11H

06H

Remark The analog voltage output to the ANO0 pin is determined by the following expression:

ANO0 pin output voltage =

AV

REF1

×

DACS0

256

Caution The voltage values shown in Table 10-1 is rounded off at the fifth position after the decimal point.

However, the preset value is calculated with the data before rounding off. The resultant data is rounded off at the first position after the decimal point.

339

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

The output analog value is processed by the SIN wave conversion circuit shown in Figure 10-4 to create a SIN wave without step.

Figure 10-4. SIN Wave Conversion Circuit

ANO0

10 kW

Amplifier

270 k

SlN wave

Integrating circuit Lowpass filter

(1) Description of package

<Public declaration symbol>

Data definition reference name

SDATA : First address of SIN wave output data to be stored to DACS0 register

ENDDAT : Last pointer of SIN wave data

Input/output parameter

C_DATA : ROM data counter

<Register used>

Bank 3; AX, HL, B

<RAM used>

Name

C_DATA

Usage

Counter indicating pointer that extracts SIN wave output data

Attribute Bytes

SADDR 1

<Flag used>

None

<Nesting level>

1 level 3 bytes

340

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

<Hardware used>

D/A converter

8-bit timer/event counter 1

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

PM13 = #

×××××××

1B ; Sets port 13 in input mode

TCL1 = #

××××

1001B ; Interval of 8-bit timer/event counter: 668

µ s

TMC1 = #000000

×

0B

CR10 = #174

DACS0 = #80H ; Sets D/A converter

DAM = #00000001B

SET1 DAM.4

SET1 TCE1

CLR1 TMIF1

; Sets D/A converter in real-time output mode

; Enables operation of 8-bit timer/event counter 1 and enables interrupt

CLR1 TMMK1

Caution To prevent output of a value on resetting and starting, once set the normal mode and write the initial value to the D/A conversion value setting register 0 (DACS0), and then output the initial value. After that, set the real-time output mode, and enable the operation of

8-bit timer/event counter 1 and interrupt.

If D/A conversion is started in the real-time output mode after reset and start with the initial value set to the DACS0 register, 0 V (data D0 in Figure 10-2. Analog Output and Output

Data Storage Timing) is output.

<Starting>

When starting output, enable the operation of the D/A converter (by setting bit 4 (DAM4) of the D/A converter mode register(DAM)), the operation of 8-bit timer/event counter 1 (by setting bit 0 (TCE) of the 8-bit timer mode control register (TMC1)), and interrupts (by clearing TMIF1 and TMMK1).

341

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

(2) Example of use

EXTRN C_DATA,SDATA,ENDDAT

;

DAM.4

F_RIARU

;

EQU

.

.

OSMS=#00000001B

TCL1=#00001001B

CR10=#175-1

TMC1=#00000000B

;

HL=#SDATA

B=C_DATA (A)

DACS0=[HL+B] (A)

DAM=#00000001B

PM13=#11111111B

EI

.

.

.

.

;

;

;

;

; Real-time output port setting flag

; Does not use divider circuit

; SIN_DAT; 8-bit timer 1. Count clock: 262 kHz

; 8-bit timer 1. Interval: 668

µ s

; Disables 8-bit timer 1 operation

; Enables D/A conversion operation of channel 0 in normal mode

; Sets P130 in input port mode if_bit(SIN wave output data start)

;

SET1 F_RIARU

; Sets channel 0 in real-time output mode

C_DATA=#0

HL=#SDATA

B=C_DATA (A)

DACS0=[HL+B] (A)

;

;

;

; Sets initial value to conversion value setting register

SET1

CLR1

CLR1

SET1 endif

TCE1

TMIF1

TMMK1

DACE0

;

; Enables 8-bit timer 1 operation

; Clears 8-bit timer 1 request flag

; Enables 8-bit timer 1 interrupt

; Enables D/A operation

.

.

.

.

(3) SPD chart

INTTM1 Switches register bank 3

Increments ROM counter

Table reference of SIN wave output data to be stored next to

DACS0 register and writes it to DACS0

THEN

(if: ROM counter

last pointer)

Writes initial value 0FFH to ROM counter

342

CHAPTER 10 APPLICATIONS OF A/D CONVERTER

(4) Program list

PUBLIC C_DATA,SDATA,ENDDAT

;

VETIM1 CSEG

DW

AT 24H

INTTM1

ENDDAT

;

EQU 1DH

; SIN wave data 1 cycle end value

SINRAM

C_DATA:

DSEG

DS

SADDR

1 ; ROM data counter

;********************************************************

; SIN wave data change interrupt processing

;********************************************************

SINDAT CSEG

INTTM1:

SEL RB3

C_DATA++

B=C_DATA (A)

HL=#SDATA

DACS0=[HL+B] (A) if(C_DATA >= #ENDDAT)

C_DATA=#0FFH endif

RETI

SDATA:

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

END

09BH

0B4H

0CBH

0DFH

0EFH

0FAH

0FFH

0FFH

0FAH

0EFH

0DFH

0CBH

0B4H

09BH

080H

065H

04CH

035H

021H

011H

006H

001H

001H

006H

011H

021H

035H

04CH

065H

080H

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

; Sets bank 3

; Increments ROM data counter

; Refers to SIN wave output data

; Stores data

; End of 1 cycle of SIN wave?

; Initializes ROM data counter

;

;

;

;

;

; SIN wave data

343

[MEMO]

344

CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT

This chapter describes the real-time output function of the 78K/0 series.

The real-time output function is used to output data set in advance in the real-time output buffer registers (RTBL and RTBH) to an external device by transferring the data to an output latch by hardware as soon as a timer interrupt request or external interrupt request occurs.

By using the real-time output port function, a jitter free signal can be output. Therefore, this function is ideal for controlling a stepping motor. The real-time output port can be set in the port mode or real-time output mode in 1bit units.

The real-time output data is written to the real-time output buffer registers (RTBL and RTBH). RTBL and RTBH are mapped to independent addresses in the SFR area.

When an operation mode of 4 bits

×

2 channels is selected, RTBL and RTBH can independently set data.

When an operation mode of 8 bits

×

1 channel is specified, data can be set to RTBL or RTBH by writing 8-bit data to either of RTBL or RTBH.

The real-time output port is set by using the real-time output port mode register (RTPM), real-time output control register (RTPC), and port mode register 12 (PM12).

345

CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT

Figure 11-1. Format of Real-Time Output Port Mode Register

Symbol 7 6 5 4 3 2 1 0

RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0

Address

FF34H

At reset

00H

R/W

R/W

RTPMn Selects real-time output port (n = 0-7)

0 Port mode

1 Real-time output port mode

Cautions 1. When the real-time output port mode is used, the port that performs real-time output must be set in the output mode (by clearing the corresponding bits of the port mode register 12

(PM12) to 0).

2. Data cannot be set to the output latch of the port set in the real-time output port mode. To set an initial value, therefore, set data to the output latch before setting the real-time output port mode.

Symbol

RTPC

7

0

6

0

5

0

Figure 11-2. Format of Real-Time Output Port Control Register

4

0

3

0

2

0

1 0

BYTE EXTR

Address

FF36H

At reset

00H

R/W

R/W

EXTR Controls real-time output by INTP2

0 Does not use INTP2 as real-time output trigger

1 Uses INTP2 as real-time output trigger

BYTE Operation mode of real-time output port

0 4 bits

×

2 channels

1 8 bits

×

1 channel

The relationship between operation mode and output trigger of the real-time output port is shown in Table 11-1.

0

Table 11-1. Operation Mode and Output Trigger of Real-Time Output Port

BYTE EXTR

0

Output Mode

4 bits

×

2 channels

RTBH

Port Output

INTTM2

RTBL

Port Output

INTTM1

1 INTTM1 INTP2

1 0 8 bits

×

1 channel INTTM1

1 INTP2

346

CHAPTER 11 APPLICATIONS OF REAL-TIME OUTPUT PORT

Figure 11-3. Format of Port Mode Register 12

Symbol 7 6 5 4 3 2

1 0

PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120

Address

FF2CH

At reset

FFH

R/W

R/W

PM12n Selects input/output mode of P12n pin (n = 0-7)

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

347

CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT

11.1 Stepping Motor

A 4-phase stepping motor is connected to the real-time output port (P120 through P123) and is controlled with

1-phase excitation pattern. A motor that rotates 1.8 degree per step is used for 1-phase excitation and is driven 200 revolutions per minute.

The time required for 1 step is calculated by the following expression:

1 step =

60 seconds

200 revolutions

×

Step

1.8 degree

= 1.5 ms

The compare register (CR01) of 8-bit timer/event counter 1 is set to 1.5 ms and the real-time output buffer register

(RTBL) is set.

By using the real-time output port control register (RTPC), set the 4 bit

×

2 channel real-time output mode, and the coincidence interrupt (INTTM1) of the 8-bit timer/event counter 1 as the output trigger (refer to

Table 11-1

).

Figure 11-4 shows the phase excitation output pattern and output timing.

Figure 11-4. Phase Excitation Output Pattern and Output Timing

1.5 ms

1-phase excitation pattern

Port P123 P122 P121 P120

0 0 0 1

0 0 1 0

0 1 0 0

1 0 0 0

INTTM1

P120

P121

P122

P123

348

CHAPTER 11 APPLICATIONS OF REAL-TIME OUTPUT PORT

(1) Description of package

<Public declaration symbol>

None

<Register used>

Bank 3, A

<RAM used>

None

<Flag used>

None

<Nesting level>

1 level 3 bytes

<Hardware used>

Real-time output port

8-bit timer/event counter 1

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit

P12 = #

××××

0000B ; Sets P120-P123 in output port mode

PM12 = #

××××

0000B

TCL1 = #

××××

1010B ; Timer clock select register 1 (count clock: 131 kHz)

CR10 = #195 ; Compare register (set to 1.5 ms)

TMC1 = #000000

×

1B ; 8-bit timer mode control register 1 (enables operation of 8-bit timer/event counter

1)

RTPM =

××××

1111B ; Real-time output port mode register (lower 4 bits are used as real-time output port)

RTPC = #00000000B ; Real-time output port control register (selects 4 bit

×

2 channel mode and

INTTM1 as output trigger)

RTBL = #00000001B ; Initial setting of real-time output buffer register

CLR1 TMIF1 ; Clears 8-bit timer/event counter 1 interrupt request flag

CLR1 TMMK1 ; Enables 8-bit timer/event counter 1

<Starting>

Clear the interrupt request flag of 8-bit timer/event counter 1 and enable the interrupt when the operation is started.

349

CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT

(2) Example of use

.

.

.

OSMS=#00000001B

TCL1=#00001010B

CR10=#196-1

.

.

.

RTPM=#00001111B

RTPC=#00000000B

RTBL=#00000001B

TMC1=#00000001B

CLR1

CLR1

EI

TMIF1

TMMK1

.

.

.

(3) SPD chart

INTTM1

; Does not use divider circuit

; MORTER_DAT: 8-bit timer 1. Count clock: 131 kHz

;

; Sets compare register to 1.5 ms

; Sets P120-P123 in output port mode

; Sets low-order 4 bits in output port mode

;

; Uses INTTM1 as output trigger

; Enables 8-bit timer 1 operation

; Clears 8-bit timer 1 interrupt request flag

;

; Enables 8-bit timer 1 interrupt

Suitches register bank 3

A

RTBL (loads data currently output)

THEN

(if: A < #00001000B)

Shifts A register 1 bit to left

ELSE

A

#00000001B (returns to initial value)

RTBL

A

(4) Program list

VETIM1 CSEG AT 24H

DW INTTM1

;**************************************************

; Stepping motor data output processing

;**************************************************

MOTER

INTTM1:

CSEG

SEL

A=RTBL

RB3 if(A < #8)

A <<= 1 else

A=#01H endif

RTBL=A

RETI

END

;

; Bank 3

;

; Prepares next output data

;

;

;

;

; RTPL

output data

350

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

The LCD controller/driver of the

µ

PD78064, 78064Y, 780308, 780308Y, and 78064B subseries is set by using the

LCD display mode register (LCDM) and LCD display control register (LCDC).

351

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-1. Format of LCD Display Mode Register

(

µ

PD78064, 78064Y, 78064B subseries)

Symbol 7 6 5 4

LCDM LCDON LCDM6 LCDM5 LCDM4

3 2 1 0

0 LCDM2 LCDM1 LCDM0

Address

FFB0H

LCDM2 LCDM1 LCDM0

0 0 0 4

0

0

0

1

1

0

3

2

0

1

Others

1

0

1

0

Time division

3

Static

Setting prohibited

1/3

1/3

1/2

1/2

At reset

00H

Bias

R/W

R/W

LCDM6 LCDM5 LCDM4

0

0

0

0

Others

0

0

1

1

0

1

0

1

At f

XX

= 5.0 MHz f

W

/2

9

(76 Hz) f

W

/2

8

(153 Hz) f

W

/2

7

(305 Hz) f

W

/2

6

(610 Hz)

Setting prohibited

Selects LCD clock

Note

At f

XX

= 4.19 MHz f

W

/2

9

(64 Hz) f

W

/2

8

(128 Hz) f

W

/2

7

(256 Hz) f

W

/2

6

(512 Hz)

At f

XT

= 32.768 kHz f

W

/2

9

(64 Hz) f

W

/2

8

(128 Hz) f

W

/2

7

(256 Hz) f

W

/2

6

(512 Hz)

LCDON

0

Enables/disables LCD display

Display off (all segment outputs are unselect signal outputs)

1 Display on

Note

The LCD clock is supplied by the watch timer. To perform LCD display, set the bit 1 (TMC21) of watch timer mode control register (TMC2) to 1.

If TMC21 is reset to 0 during LCD display, supply of the LCD clock is stopped and the display is disturbed.

Remarks 1. f

W

: watch timer clock frequency (f

XX

/2

7

or f

XT

)

2. f

XX

: main system clock frequency (f

X

or f

X

/2)

3. f

X

: main system clock oscillation frequency

4. f

XT

: subsystem clock oscillation frequency

352

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-2. Format of LCD Display Mode Register

(

µ

PD780308, 780308Y subseries)

Symbol 7 6 5 4 3 2 1 0

LCDM LCDON LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0

Address

FFB0H

At reset

00H

LCDM2 LCDM1 LCDM0

0 0 0 4

0

0

0

1

1

0

3

2

0

1

Others

1

0

1

0

Time division

3

Static

Setting prohibited

1/3

1/3

1/2

1/2

Bias

R/W

R/W

Note 1

LCDM3

0

1

Operation mode of

LCD controller/driver

Normal operation

Supply voltage of LCD controller/driver

Static display mode 1/3 bias mode

2.0 to 5.5 V

Low-voltage operation 2.0 to 3.4 V

2.5 to 5.5 V

1/2 bias mode

2.7 to 5.5 V

LCDM6 LCDM5 LCDM4

0

0

0

0

Others

0

0

1

1

0

1

0

1

At f

XX

= 5.0 MHz f

W

/2

9

(76 Hz) f

W

/2

8

(153 Hz) f

W

/2

7

(305 Hz) f

W

/2

6

(610 Hz)

Setting prohibited

Selects LCD clock

Note

At f

XX

= 4.19 MHz f

W

/2

9

(64 Hz) f

W

/2

8

(128 Hz) f

W

/2

7

(256 Hz) f

W

/2

6

(512 Hz)

At f

XT

= 32.768 kHz f

W

/2

9

(64 Hz) f

W

/2

8

(128 Hz) f

W

/2

7

(256 Hz) f

W

/2

6

(512 Hz)

LDON

0

1

Enables/disables LCD display

Display off (all segment outputs are unselect signal outputs)

Display on

Notes 1. To lower the power consumption, clear LCDM3 to 0 when LCD display is not used. To manipulate

LCDM3, be sure to turn off the LCD display.

If TMC21 is cleared to 0 during LCD display, the supply of the LCD clock is stopped and the display is disturbed.

2. The LCD clock is supplied by the watch timer. To perform LCD display, set the bit 1 (TMC21) of watch timer mode control register (TMC2) to 1.

If TMC21 is reset to 0 during LCD display, supply of the LCD clock is stopped and the display is disturbed.

Remarks 1. f

W

: watch timer clock frequency (f

XX

/2

7

or f

XT

)

2. f

XX

: main system clock frequency (f

X

or f

X

/2)

3. f

X

: main system clock oscillation frequency

4. f

XT

: subsystem clock oscillation frequency

353

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-3. Format of LCD Display Control Register

Symbol 7 6 5 4

LCDC LCDC7 LCDC6 LCDC5 LCDC4

3

0

2

0

1

LEPS

0

LIPS

Address

FFB2H

At reset

00H

R/W

R/W

LEPS

0

0

1

LIPS

0

1

0

1 1

Selects LCD drive power supply

Does not supply power for LCD driving

Supplies LCD driving power from V

DD

Supplies driving power from BIAS pin (BIAS and V

LC0

pins are internally short-circuited)

Setting prohibited

LCDC7 LCDC6 LCDC5 LCDC4 Function of P80/S39-P97/

S24 pins

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

Port pin

P80-P97

P80-P95

P80-P93

P80-P91

P80-P87

P80-P85

P80-P83

Segment pin

None

S24, S25

S24-S27

S24-S29

S24-S31

S24-S33

S24-S35 0

0

1

Others

0

1

1

1

1

0

0

1

0

P80, P81

None

S24-S37

S24-S39

Setting prohibited

Cautions 1. Pins that output segments cannot be used as output port pins even if 0 is set to the corresponding port mode register.

2. When pins that output segments are read as port pins, 0 is returned.

3. Pins set by LCDC to output segments are not used with the internal pull-up resistor, regardless of the values of the bits 0 and 1 (PUO8 and PUO9) of the pull-up resistor option register H (PUOH).

354

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

The LCD controller/driver of the

µ

PD78064, 78064Y, 780308, and 780308Y subseries is described next.

(a) Function of LCD controller/driver

The LCD controller/driver has the following functions:

<1> Automatically outputs segment and common signals by automatically reading the display data memory.

<2> Five types of display modes are available:

Static mode

1/2 duty mode (1/2 bias)

1/3 duty mode (1/2 bias)

1/3 duty mode (1/3 bias)

1/4 duty mode (1/3 bias)

<3> Four types of frame frequencies can be selected in each display mode.

<4> Up to 40 segment signal outputs (S0 through S39) and four common signal outputs (COM0 through

COM3) are available. Sixteen segment outputs can be set in the input/output port mode in 2-bit units

(P80/S39 through P87/S32, and P90/S31 through P97/S24).

<5> Divider resistors for generating the LCD drive voltage can be provided to the mask ROM model by mask option.

<6> Can operate on the subsystem clock.

Bias

1/2

1/3

Table 12-1 shows the maximum number of pixels that can be displayed in each display mode.

Table 12-1. Maximum Number of Pixels for Display

Time Division

Static

2

3

3

4

Common Signal Used

COM0 (COM0-COM3)

COM0, COM1

COM0-COM2

COM0-COM2

COM0-COM3

Maximum Number of Pixels

40 (40 segments

×

1 common)

Note 1

80 (40 segments

×

2 common)

Note 2

120 (40 segments

×

3 common)

Note 3

160 (40 segments

×

4 common)

Note 4

Notes 1. Can display 5 digits with eight segments for each digit on an 8-segment LCD panel.

2. Can display 10 digits with four segments for each digit on an 8-segment LCD panel.

3. Can display 13 digits with three segments for each digit on an 8-segment LCD panel.

4. Can display 20 digits with two segments for each digit on an 8-segment LCD panel.

355

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(b) Setting of LCD controller/driver

Set the LCD controller/driver as follows. When using the LCD controller/driver, set the watch timer in the operating status in advance.

<1> Enables the watch operation by using the timer clock select register 2 (TCL2) and watch timer mode control register (TMC2).

<2> Set the initial value to the display data memory (FA58H through FA7FH).

<3> Specify the pins used for segment output by using the LCD display control register (LCDC).

<4> Set the display mode and LCD clock by using the LCD display mode register.

After that, set data to the display data memory according to the contents to be displayed.

(c) LCD display data memory

The LCD display data memory is mapped to addresses FA58H through FA7FH. The data stored to the LCD display data memory can be displayed on the LCD panel by using the LCD controller/driver.

Figure 12-4 shows the relations between the contents of LCD display data memory and the segment/common outputs.

The area not used for display can be used as an ordinary RAM area.

Figure 12-4. Relations between Contents of LCD Display Data Memory and Segment/Common Output

Address

FA7FH

FA7EH

FA7DH

FA7CH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

S0

S1

S2

S3

FA5AH

FA59H

FA58H

S37/P82

S38/P81

S39/P80

COM3 COM2 COM1 COM0

Caution The high-order 4 bits of the LCD display data memory are not used as memory bits. Be sure to clear these bits to 0.

356

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(d) Common and segment signals

Each pixel on an LCD panel lights when the potential difference between the corresponding common and segment signals reaches to a specific level (LCD drive voltage V

LCD

).

Because an LCD panel degrades if DC voltages are applied as common and segment signals, it is driven by

AC voltages.

<1> Common signal

The common signal is selected as shown in Table 12-2 according to the set number of time divisions and repeatedly operates in the cycles shown in the table. In the static mode, the same signal is output to COM0 through COM3.

In the 2-time division mode, open the COM2 and COM3 pins. Open the COM3 pin in the 3-time division mode.

Table 12-2. COM Signal

Number of Time

Divisions

COM Signal

Static

COM0 COM1 COM2 COM3

Open 2 time divisions

3 time divisions

4 time divisions

Open

Open

<2> Segment signal

Segment signals correspond to a 40-byte LCD display data memory (FA58H through FA7FH). Bits 0,

1, 2, and 3 of the display data memory are read in synchronization of COM0, COM1, COM2, and COM3, respectively. If the content of each bit is 1, the corresponding segment signal is converted to a select voltage and is output to the segment pin (S0 to S39). If the content of a bit is 0, the segment signal is converted to an unselect voltage. (Note that S24 through S39 are multiplexed with input/output port pins.)

Therefore, confirm what combination of the front panel electrode (corresponding to a segment signal) and rear panel electrode (corresponding to a common signal) of the LCD panel generates a display pattern, and write the bit data corresponding to the pattern to be displayed on a one-to-one basis to the

LCD display memory.

In the static mode, bits 1, 2, and 3 of the LCD display data memory are not used for LCD display. In the 2- and 3-time division modes, bits 2 and 3, and bit 3 are not used for LCD display, respectively. These bits therefore can be used for any other purposes.

Bits 4 through 7 are fixed to 0.

357

358

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

<3> Output waveforms of common and segment signals

Only when the voltage levels of specific common and segment signals reach the select levels,

±

V

LCD

(LCD drive voltage) level is reached and the corresponding pixel on the LCD panel lights. The pixel remains dark with any other combination of the common and segment signals.

Figure 12-5 shows the waveform of the common signal, and Figure 12-6 shows the phase difference in voltage between the common and segment signals.

Figure 12-5. Common Signal Waveform

(a) Static display mode

COMn

(static)

V

LC0

V

SS

V

LCD

T

F

= T

(b) 1/2 bias

COMn

(2-time division)

V

LC0

V

LC2

V

SS

V

LCD

T

F

= 2T

COMn

(3-time division)

V

LC0

V

LC2

V

SS

V

LCD

T

F

= 3T

(c) 1/3 bias

COMn

(3-time division)

V

LC0

V

LC1

V

LC2

V

SS

V

LCD

T

F

= 3T

COMn

(4-time division)

V

LC0

V

LC1

V

LC2

V

SS

V

LCD

T

F

= 4T

Remarks 1. T : one cycle of LCDCL

2. T

F

: frame frequency

3. V

LCD

: LCD drive voltage

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-6. Phase Difference in Voltage between Command Signal and Segment Signal

(a) Static display mode

Common signal

Segment signal

Select Unselect

V

LC0

V

LCD

V

SS

V

LC0

V

SS

V

LCD

T T

(b) 1/2 bias

Common signal

Segment signal

Select Unselect

V

LC0

V

LC2

V

SS

V

LC0

V

LC2

V

SS

V

LCD

V

LCD

T T

(c) 1/3 bias

Common signal

Segment signal

Select Unselect

V

LC0

V

LC1

V

LC2

V

SS

V

LC0

V

LC1

V

LC2

V

SS

V

LCD

V

LCD

T T

Remarks 1. T : one cycle of LCDCL

2. V

LCD

: LCD drive voltage

(e) Supplying LCD drive voltage

The mask ROM model can be provided by mask option with a divider resistor that is used to create the LCD drive voltage (the PROM model is not provided with a divider resistor). By providing the divider resistor, an

LCD drive voltage corresponding to each bias can be created without an external divider resistor.

In addition, an LCD drive voltage can be supplied to the BIAS pin to support various LCD drive voltages.

359

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

12.1 Static Display

This section explains an example using the

µ

PD78064 subseries. A 4-digit static LCD is driven by using the 32 segment signals (S0 through S31) and a common signal (COM0). Figure 12-7 shows the display pattern and electrode wiring of the static LCD. Figure 12-8 shows the connections among the segment signals and common signal. Figure

12-9 shows an example of connecting an LCD driving power supply in the static display mode (with an external divider resistor, V

DD

= 5 V, and V

LCD

= 5 V). The display example in Figure 12-8 is “1234”, and the contents of the display data memory (addresses FA60H through FA7FH) correspond to this.

In this section, how to display the second digit, “3”, is described. According to the display pattern in Figure 12-

8, the select and unselect voltages must be output to the S8 through S15 pins in the timing of the common signal

COM0, as shown in Table 12-3.

Table 12-3. Select and Unselect Voltages (COM0)

Segment

Common

COM0

S8

Unselect

S9

Select

S10

Select

S11

Select

S12

Unselect

S13

Select

S14

Unselect

S15

Select

From Table 12-3, it is clear that 10101110 must be set to bit 0 of the display data memory (addresses FA70H through

FA77H) corresponding to S8 through S15.

Figure 12-10 shows the LCD driving waveforms of S11, S12, and COM0.

Because the same waveform as COM0 is output to COM1, 2, and 3, the driving capability can be increased by connecting COM0, 1, 2, and 3.

Figure 12-7. Display Pattern and Electrode Wiring of Static LCD

S8 n

+ 3

S8 n

+ 4

S8 n

+ 6

S8 n

+ 2

S8 n

+ 5

S8 n

+ 1

S8 n

COM0

S8 n

+ 7

Remark n = 0-3

360

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-8. Connection of Static LCD

DATA MEMORY ADDRESS

×

×

0

×

×

×

0

×

×

×

0

×

×

×

0

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

0

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

0

×

×

×

0

×

×

×

1

×

×

×

0

×

×

×

1

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

1

×

×

×

0

×

×

×

0

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

0

×

×

×

1

×

×

×

1

×

×

×

0

×

BIT0

BIT1

BIT2

BIT3

TIMING STROBE

LCD PANEL

Figure 12-9. Example of Connecting LCD Driving Power in Static Display Mode

(with external divider resistor, V

DD

= 5 V, and V

LCD

= 5 V)

V

DD

BIAS pin

LIPS

LEPS

(= 0)

V

LCD

V

LC0

V

LC1

V

LC2

V

SS

V

LCD =

V

DD

361

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-10. Example of Static LCD Driving Waveform

T

F

COM0

S11

S12

COM0–S11

COM0–S12

V

LC0

Common signal

V

SS

V

LC0

Segment signal

V

SS

V

LC0

Segment signal

V

SS

+ V

LCD

0 LCD lights

– V

LCD

+ V

LCD

0

– V

LCD

LCD extinguishes

Remark T

F

: frame frequency

To display the LCD, segment signals are output based on the waveform of the common signal.

The static LCD is lit by a segment signal (S11) output at a frame frequency half a cycle shifted from that of the common signal (COM0) as shown in Figure 12-10. This means that a potential difference is generated between the common signal and segment signal, and this potential difference is responsible for lighting the LCD. As can be seen from COM0 and S11 in Figure 12-10, a potential difference

±

V

LCD

(LCD drive voltage) is generated between these signals.

To extinguish the LCD, the segment signal (S12) is output in a waveform synchronous to that of the common signal

(COM0). In this way, the potential difference between COM0 and S12 is eliminated and the LCD remains dark.

362

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(1) Description of package

<Public declaration symbol>

Subroutine name

S_LCD : Static display data storage routine

Input parameter

B_LCD : LCD display content storage buffer area

Data definition reference name

S0 : LCD display data memory reference address (FA7FH)

<Register used>

Bank 0 : AX, DE, HL

<RAM used>

j i

Name

B_LCD

WORKP

Usage

LCD display data storage buffer area

Display digit loop counter

Segment setting loop counter

Display data storage area address saving area

Attribute Bytes

SADDR 1

SADDR

SADDR

SADDRP

1

1

2

<Flag used>

None

<Nesting level>

1 level 2 bytes

<Hardware used>

LCD controller/driver

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register

TCL2 = #

×××

00

×××

B ; Count clock of watch timer = selects system clock

TMC2 = #0

×××××

1

×

B ; Supplies LCD clock (enables prescaler operation)

LCDC = #01000010B ; LCD display control register (supplies LCD drive power from BIAS pin with segment pins S24 through S31 used)

LCDM = #10100100B ; LCD display mode register (sets static display, selects LCD clock, and turns on display)

Caution Set the initial value to the LCD display data memory (FA58H through FA7FH) before turning on the LCD display.

<Starting>

Set the display contents in the B_LCD area and call the S_LCD routine.

363

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(2) Example of use

EXTRN SLCD,B_LCD,S0

.

.

.

HL=#S0

BC=#0FA80H-0FA58H while(BC!=#0) (AX)

A=#0

[HL]=A endw

HL--

BC--

;

B_LCD=#0

B_LCD+1=#0

B_LCD+2=#0

B_LCD+3=#0

;

TCL2=#00000000B

TMC2=#00000010B

LCDC=#01000010B

LCDM=#10100100B

;

.

.

B_LCD+3=A

.

.

B_LCD+2=A

.

.

B_LCD+1=A

.

.

B_LCD=A

CALL

.

.

!S_LCD

(3) SPD chart

S_LCD

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

; Clears LCDRAM

; (from FA58H to FA7FH)

; Count clock of watch timer = selects main system clock

; Enables operation of prescaler

; Supplies LCD drive power from BIAS pin with segments S24 through 31 used

; Turns ON static display with 256-Hz clock selected

Stores address S0 (RAM address of first digit of LCD) to HL register

Stores B_LCD address (buffer area of first digit of LCD) – 1 to WORKP area

(for: i = #0; i < #4; i + +)

Increments WORKP area (display area address of next digit)

Saves display data to A register by table reference

(for: j = #0; j < #8; j + +)

Shifts A register 1 bit to right and transfers bit 0 to CY

Transfers CY to bit 0 of [HL]

Decrements HL register (next segment address of LCD)

364

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(4) Program list

PUBLIC S_LCD,B_LCD,S0

;

EQU S0

;

LCDRAM1 DSEG

0FA7FH

SADDR

; 1st digit of LCD

B_LCD: i: j:

DS

DS

DS

4

1

1

; Display BUF area

; Work counter

; Work counter

LCDRAM2 DSEG SADDRP

WORKP: DS 2

; Work area

;******************************************************

; LCD display (static display) processing

;******************************************************

LSDS CSEG

S_LCD:

HL=#S0

WORKP=#B_LCD-1 for(i=#0;i<#4;i++) next

RET

LCDDAT:

DE=WORKP (AX)

DE++

WORKP=DE (AX)

X=[DE] (A)

A=#0

AX+=#LCDDAT

DE=AX

A=[DE] for(j=#0;j<#8;j++) next

RORC

[HL].0=CY

HL--

A,1

;

;

; HL

address S0

; Work area

address of B_LCD - 1

;

;

;

; References display data of contents of next digit

;

;

;

;

;

;

;

;

;

; Stores display data to bit 0 from address S0

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

DB

END

11011110B

00000110B

11101100B

10101110B

00110110B

10111010B

11111010B

00011110B

11111110B

10111110B

01111110B

11110010B

11011000B

11100110B

11111000B

01111000B

00000000B

; 4

; 5

; 6

; 7

; 8

; 9

; 0

; 1

; 2

; 3

; A

; B

; C

; D

; E

; F

; Extinguishes

365

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

12.2 4-Time Division Display

This section explains an example using the

µ

PD78064 subseries. Four LCD digits are driven by means of 1/3 bias and 4-time division by using the 16 segment signals (S0 through S15) and four common signals (COM0 through

COM3). Figure 12-12 shows the connection of a 4-time division 4-digit LCD panel with 10 display patterns shown in Figure 12-11 and the segment (S0 through S15) and common (COM0 through COM4) signals of the

µ

PD78064 subseries. Figure 12-13 shows an example of connecting an LCD drive power supply in the 4-time division display mode (with external divider resistor, V

DD

= 5 V, and V

LCD

= 5 V). The display example in Figure 12-12 is “12345678”, and the contents of the display data memory (addresses FA70H through FA7FH) correspond to this.

In this case, “6” at the third digit has been taken as an example. According to the display pattern in Figure 12-

12, the select and unselect voltages shown in Table 12-4 must be output to the S4 and S5 pins in the timing of the common signals COM0 through COM3.

Table 12-4. Select and Unselect Voltages (COM0, 1, 2, 3)

S4 S5 Segment

Common

COM0

COM1

COM2

COM3

Select (a)

Unselect (b)

Select (c)

Unselect (d)

Select (e)

Select (f)

Select (g)

Select (h)

Remark (a) through (h) in the table corresponds to the segments a through h in Figure 12-12.

S4.

Table 12-4 indicates that 0101 should be stored to the display data memory address (FA7BH) corresponding to

Figure 12-14 shows the LCD drive waveforms between S4 and COM0 and COM1 signals.

Figure 12-11. Display Pattern of 4-Time Division LCD and Electrode Wiring

COM1 S2 n

COM0

COM2

COM3

S2 n

+ 1

Remark n = 0-7

366

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

Figure 12-12. Connections of 4-Time Division LCD Panel

DATA MEMORY ADDRESS

TIMING STROBE

0

0

0

0

1

0

0

1

1

1

0

1

0

0

1

1

0

1

0

1

1

0

1

1

0

0

1

1

1

0

0

1

0

1

1

1

1

0

1

0

1

1

1

1

1

0

1

0

0

0

1

0

1

0

1

1

1

1

1

1

1

1

1

BIT0

BIT1

BIT2

BIT3

0

LCD PANEL a e f g h b c d

Figure 12-13. Example of Connecting LCD Drive Power in 4-Time Division Mode

(with external divider resistor, V

DD

= 5 V, V

LCD

= 5 V)

V

DD

BIAS pin

LIPS

LEPS

(= 0)

V

LCD

V

LC0

V

LC1

V

LC2

V

SS

V

LCD

= V

DD

R

R

R

367

368

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

COM0

COM1

COM2

COM3

S4

COM0–S4

COM1–S4

Figure 12-14. Example of 4-Time Division LCD Driving Waveform

T

F

Select Unselect Select Unselect

V

LC0

V

LC1

V

LC2

V

SS

V

LC0

V

LC1

V

LC2

V

SS

V

LC0

V

LC1

V

LC2

V

SS

V

LC0

V

LC1

V

LC2

V

SS

V

LC0

V

LC1

V

LC2

V

SS

+ V

LC0

+ 1/3V

LCD

0

– 1/3V

LCD

– V

LCD

+ V

LC0

+ 1/3V

LCD

0

– 1/3V

LCD

+ V

LCD

Remarks 1 .

T

F

: frame frequency

2. The valid waveform of each common signal is enclosed in dotted line.

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

For 4-time division LCD display, the valid timing (enclosed in dotted line in Figure 12-14) of each common signal is output in a cycle 1/4 of the frame frequency (T

F

) as shown in Figure 12-14. In this timing,each segment signal is output to light or extinguish the LCD.

For example, segment signal S4 outputs a waveform that lights the LCD in the timing of COM0 and COM2, in respect to each common signal (COM0 through COM3) in Figure 12-14.

When the relations between each common signal and S4 is examined, it can be seen that a potential difference of

±

V

LCD

(LCD drive voltage) is generated at the COM0 select timing between COM0 and S4, as can be seen from the waveform of COM0-S4. In the case of COM2 and S4, a voltage difference of

±

V

LCD

(LCD drive voltage) is also generated between COM2 and S4 at the COM2 select timing. Therefore, the segment indicated by COM0, COM2 and S4 lights.

Because a voltage difference between COM1 and S4 is always

±

1/3 V

LCD

(COM1-S4 in Figure 12-14) at the select timing of COM1 (COM1 in Figure 12-14), the LCD remains dark.

369

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(1) Description of package

<Public declaration symbol>

Subroutine name

S_4LCD : 4-time division display data storage routine

Input parameter

B_LCD : LCD display content storage buffer area

Data definition reference name

S0 : LCD display data memory reference address (FA7FH)

<Register used>

Bank 0; AX, DE, HL

<RAM used>

Name

B_LCD i

WORKP

Usage

LCD display data storage buffer area

Display digit loop counter

Display data storage area address saving area

Attribute Bytes

SADDR 1

SADDR

SADDRP

1

2

<Flag used>

None

<Nesting level>

1 level 2 bytes

<Hardware used>

LCD controller/driver

<Initial setting>

OSMS = #00000001B ; Oscillation mode select register

TCL2 = #

×××

00

×××

B ; Count clock of watch timer = selects system clock

TMC2 = #0

×××××

1

×

B ; Supplies LCD clock (enables operation of prescaler)

LCDC = #00000001B ; LCD display control register (LCD driving power is supplied from V

DD

with segment signal pins S24 through S31 not used)

LCDM = #10100000B ; LCD display mode register (sets 4-time division display, selects LCD clock, turns

ON display)

Caution Set the initial value to the LCD display data memory (FA58H through FA7FH) before turning ON the LCD.

<Starting>

Set the display contents to the B_LCD area and call the S_4LCD routine.

370

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(2) Example of use

EXTRN S_4LCD,B_LCD,S0

.

.

.

HL=#S0

BC=#0FA80H-0FA58H while(BC!=#0) (AX)

A=#0

[HL]=A

HL-endw

BC--

;

B_LCD=#0

B_LCD+1=#0

B_LCD+2=#0

B_LCD+3=#0

;

TCL2=#00000000B

TMC2=#00000010B

LCDC=#00000001B

LCDM=#10100000B

;

.

.

B_LCD+3=A

.

.

B_LCD+2=A

.

.

B_LCD+1=A

.

.

B_LCD=A

CALL

.

.

!S_4LCD

;

;

;

;

;

;

;

;

;

;

;

; Clears LCDRAM

; (from FA58H to FA7FH)

;

;

;

;

; Count clock of watch timer = selects main system clock

; Enables prescaler operation

; Supplies driving power from V

DD

with segments S24 through S31 not used

; Turns on 4-time division display with 256-Hz clock selected, turns ON display

(3) SPD chart

S_4LCD Stores address S0 (RAM address of first digit of LCD) to HL register

Stores address B_LCD (buffer area of first digit of LCD) – 1 to WORKP area

(for: i = #0; i < #8; i + +)

Increments WORKP area (display area address of next digit)

Stores display data to A register by table reference

Rotates address [HL] 1 digit to left

(transfers low-order 4 bits of A register to low-order 4 bits of address [HL])

Shifts A register 4 bits to right

Decrements HL register

(LCD RAM area corresponding to odd segments of one digit of LCD)

Rotates address [HL] 1 digit to left

Decrements HL register

(LCD RAM area corresponds to even segment of 1 digit of LCD)

371

CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER

(4) Program list

PUBLIC S_4LCD,B_LCD,S0

S0 EQU 0FA7FH

; 1st digit of LCD

LCD4RAM1

B_LCD: i:

DSEG

DS

DS

SADDR

8

1

; Display BUF area

; Work counter

LCD4RAM2

WO4RKP:

DSEG

DS

SADDRP

2

;***************************************************************

; LCD display (4-time division display) processing

;***************************************************************

CSEG

; Work area

LSD4

S_4LCD:

HL=#S0

WORKP=#B_LCD-1 for(i=#0;i<#8;i++) next

RET

DE=WORKP (AX)

DE++

WORKP=DE (AX)

X=[DE] (A)

A=#0

AX+=#LCDDAT

DE=AX

A=[DE]

ROL4

A >>= 1

A >>= 1

A >>= 1

A >>= 1

HL--

ROL4

HL--

[HL]

[HL]

;

;

;

; HL

address S0

;

;

;

; References display data of contents of next digit

;

;

;

;

;

;

; [HL]

low-order 4 bits of A register

; Shifts high-order 4 bits of A register to lower 4 bits

;

;

; HL– –

; [HL]

low-order 4 bits of A register

; HL– –

LCDDAT:

DB 11010111B

DB 00000110B

DB 11100011B

DB 10100111B

DB 00110110B

DB 10110101B

DB 11110101B

DB 00010111B

DB 11110111B

DB 10110111B

DB 01110111B

DB 11110100B

DB 11010001B

DB 11100110B

DB 11110001B

DB 01110001B

DB 00000000B

END

; 0

; 1

; 2

; 3

; 4

; 5

; 6

; 7

; 8

; 9

; A

; B

; C

; D

; E

; F

; Extinguishes

372

CHAPTER 13 APPLICATIONS OF KEY INPUT

This chapter introduces an example of a program that inputs signals from a key matrix of 4

×

8 keys. The key scan be pressed successively, and two or more keys can be pressed simultaneously. In the circuit shown in this section, the high-order 4 bits of port 3 (P34 through P37) are used as key scan signals, and port 4

Note

is used as key return signals. As the pull-up resistor of port 4 for key return, the internal pull-up resistor set by software is used

(refer to Figure 13-1).

Port 4 of the 78K/0 series has a function to detect the falling edges of the eight port pins in parallel. If port 4 is used for key return signals, therefore, the standby mode can be released through detection of a falling edge, i.e., by key input.

In this example, the

µ

PD78054 subseries is used.

Note

With the

µ

PD78064, 78064Y, 780308, 780308Y, and 78064B subseries, port 11 is used instead of port 4.

Figure 13-1. Key Matrix Circuit

P34

P35

P36

P37

Pull-up resistors connected

P40

P41

P42

P43

P44

P45

P46

P47

=

The input keys are stored to RAM on a one key-to-1 bit basis. The RAM bit corresponding to a pressed key is set and the bit corresponding to a released key is cleared. By testing the RAM data on a 1-bit-by-1-bit basis starting from the first bit, the key status can be checked. To absorb chattering, the key is assumed to be valid when four successive key codes coincide with a given code. For example, if a key code is sampled every 5 ms, chattering of

15 ms to 20 ms can be absorbed. If the key input is changed, a key change flag (KEYCHG) is set.

373

CHAPTER 13 APPLICATIONS OF KEY INPUT

(1) Description of package

<Public declaration symbol>

KEYIN : Key input subroutine name

KEYDATA : Key data storage area

CHATCT : Chattering counter

KEYCHG : Key change test flag

<Register used>

AX, DE, HL

<RAM used>

Name

KEYDATA

WORK

CHATCT

WORKCT

Usage

Stores valid key data

Stores key data during chattering

Chattering counter

Loop processing work counter

<Flag used>

Name

CHGFG

KEYCHG

CHTEND

Usage

Set if key input changes

Set if valid key changes

Confirms end of chattering

Attribute

SADDR

Bytes

4

1

<Nesting>

1 level 2 bytes

<Hardware used>

P4

P3 (P34-P37)

<Initial setting>

PUO4 = 1 ; Connects pull-up resistor to P4

PM3 = #0000

××××

B ; Sets high-order 4 bits of P3 in output mode

<Starting>

Call KEYIN at specific intervals.

Before inputting the key data, test the key change flag. The key change flag is not cleared by the subroutine.

Clear the flag after it has been tested.

374

CHAPTER 13 APPLICATIONS OF KEY INPUT

(2) Example of use

VETM3

EXTRN KEYDATA,CHATCT,KEYIN

EXTBIT KEYCHG

CSEG

DW

AT 1EH

INTTM3

; Sets vector address of watch timer

MAINDAT DSEG

CT5MS: DS

.

.

.

.

SADDR

1

TMC2=#00100110B

CLR1

CT5MS=#3

TMMK3

PM3=#00000000B

SET1 PUO.4

CHATCT=#3

.

.

.

.

if_bit(KEYCHG)

CLR1 KEYCHG

; Key input processing endif

.

.

.

.

;**********************************************

;

;

Watch timer interrupt processing

Interval time: 1.95 ms

;**********************************************

INTTM3:

.

.

.

.

DBNZ

MOV

CALL

RTNTM3:

.

.

.

.

RETI

CT5MS,$RTNTM3

CT5MS,#3

!ANKEYIN

; Sets P3 in output mode

; Pulls P4 up

; Initial setting of chattering counter

; Key changed?

; 1.95 ms interrupt

; 1.95 ms

×

3 elapses

375

CHAPTER 13 APPLICATIONS OF KEY INPUT

(3) SPD chart

KEYIN Outputs key scan signal to P34-P37

UNTIL: key scan signal output ends

THEN

Key return signal input from P4

IF: key input changes

THEN

Sets status in which key input changes

CHTFG

Shifts key scan signal 1 bit

IF: no key input change

IF: chattering being absorbed

THEN

THEN

IF: chattering ends

THEN

IF: valid key changes

Sets key change status

Sets KEYCHG

Updates key data

ELSE

Sets chattering absorption start status

Clears CHTEND

376

CHAPTER 13 APPLICATIONS OF KEY INPUT

(4) Program list

PUBLIC KEYDATA,KEYCHG,KEYIN,CHATCT

KEY_DAT DSEG

KEYDATA:DS

WORK: DS

CHATCT: DS

WORKCT: DS

SADDR

4

4

1

1

; Key data storage area

; Chattering key data

; Chattering counter

KEY_FLG BSEG

CHGFG

KEYCHG

CHTEND

DBIT

DBIT

DBIT

; Key change status

; Key changed

; Chattering absorption end status

KEY_SEG CSEG

;*******************************

* Matrix key input

;*******************************

KEYIN:

CLR1 CHGFG

P3&=#00001111B

P3|=#00010000B

HL=#WORK repeat

A=P4

A^=#11111111B if(A!=[HL])

SET1 CHGFG

[HL]=A endif

HL++

A=P3

A&=#11110000B

X=A

A=P3

A+=X

P3=A until_bit(CY)

; Sets address of key work area

; Data inverted

; Key changed?

; Shifts key scan 1 bit if_bit(!CHGFG) if_bit(!CHTEND)

CHATCT-if(CHATCT==#0)

SET1

DE=#WORK

CHTEND

HL=#KEYDATA for(WORKCT=#0;WORKCT<#4;WORKCT++) else endif if([DE]!=[HL]) (A)

SET1 KEYCHG endif

A<->[HL] next endif

HL++

DE++ endif

RET

CHATCT=#3

CLR1 CHTEND

; Key changed

; Chattering absorbed

; Chattering ends

; Key changed

; Transfers WORK to KEYDATA

377

[MEMO]

378

APPENDIX A DESCRIPTION OF SPD CHART

SPD stands for Structured Programming Diagrams.

Structuring means structuring the logical processing of a program, and designing and formulating the logic by using the basic structure of the logic elements.

All programs can be created by only combining the basic structure of logic elements, (sequentially, selectively, or repeatedly). (This is called a structured theorem). Through structuring, the flow of a program is clarified, and the reliability is improved. Although various methods are available for expressing the structuring of a program, NEC employs a diagram technique called SPD.

The following table describes the SPD symbols used for the SPD technique and compares them with flowchart symbols.

Table A-1. Comparison between SPD Symbols and Flowchart Symbol (1/2)

Processing Name

Sequential processing

SPD Symbol Flowchart Symbol

Processing 1

Processing 1

Processing 2

Processing 2

Conditional branch

(IF)

(IF: condition)

[THEN]

Processing 1

[ELSE]

Processing 2

Condition

THEN

Processing 1

ELSE

Processing 2

Conditional branch

(SWITCH)

(SWITCH: condition)

[CASE: 1]

Processing 1

[CASE: 2]

Processing 2

.

.

.

[CASE: n]

Processing n

Condition

Processing 1 Processing 2 Processing n

379

APPENDIX A DESCRIPTION OF SPD CHART

Table A-1. Comparison between SPD Symbols and Flowchart Symbol (2/2)

SPD Symbol Flowchart Symbol Processing Name

Conditional loop

(WHILE)

ELSE

(WHILE: condition)

Processing

Condition

THEN

Processing

Conditional loop

(UNTIL)

(UNTIL: condition)

Processing

Processing

ELSE

Condition

THEN

Conditional loop

(FOR)

(FOR: initial value; condition; increment/decrement specification)

Processing

Initial value

Condition

THEN

Processing

ELSE

Increment/ decrement

Infinite loop

(WHILE: forever)

Processing

Processing

Connector

(IF: condition)

[THEN]

GOTO A

Condition

THEN

A

ELSE

A

Processing

A

Processing

380

APPENDIX A DESCRIPTION OF SPD CHART

1. Sequential processing

Sequential processing executes processing from top to bottom in the sequence in which processing appears.

SPD chart

Processing 1

Processing 2

2. Conditional branch: 2 branch (IF)

Processing contents are selected according to the condition specified by IF is true or false (THEN/ELSE).

SPD chart

(IF: condition)

[THEN]

Processing 1

[ELSE]

Processing 2

Example 1. Identification of positive or negative of X

(IF: X > 0)

[THEN]

X is positive number

[ELSE]

X is 0 or negative number

2. STOP if signal is red

(IF: signal = red)

[THEN]

STOP

381

APPENDIX A DESCRIPTION OF SPD CHART

3. Conditional branch: multiple branch (SWITCH)

The condition specified by SWITCH is compared with the status indicated by CASE to select the processing. The processing of the SWITCH statement may be executed only when the given values coincide, or continued downward starting from when the given values coincide (if the processing is not continued downward, ‘break’ is described). If there is no coincide status, ‘default’ processing is executed (description of ‘default’ is arbitrary).

(1) Execution only on coincidence

SPD chart

(execution)

(SWITCH: condition)

[CASE: status 1]

Processing 1 break

[CASE: status 2]

Processing 2

.

.

.

break

.

.

.

[CASE: status n]

Processing n

[default]

Processing 0

When status 1: processing 1

When status 2: processing 2

.

.

.

.

.

.

.

.

.

.

When status n: processing n

If status does not coincide: processing 0

Example Displays name of month by input characters

(SWITCH: input character)

[CASE: '1']

Displays Jan break

[CASE: '2']

Displays Feb

.

.

.

[default] break

.

.

.

Displays ERROR

382

APPENDIX A DESCRIPTION OF SPD CHART

(2) If processing continues from coincidence status

SPD chart

(SWITCH: condition)

[CASE: Status 1]

Processing 1

[CASE: Status 2]

.

.

.

Processing 2

.

.

.

[CASE: Status n]

Processing n

[default]

Processing 0

(execution)

When status 1: processing 1

processing 2

...

processing n

When status 2: processing 2

...

processing n

.

.

.

.

.

.

.

.

.

.

When status n: processing n

If status does not coincide: processing 0

Example Transmission/reception of serial interface

(execution)

(SWITCH: transfer mode)

[CASE: 1]

Address transmission

[CASE: 2]

Data transmission break

[CASE: 3]

Data reception

When status 1: address transmission

data transmission

When status 2: data transmission

When status 3: data reception

4. Conditional Loop (WHILE)

The condition indicated by WHILE is judged. If the condition is satisfied, processing is repeatedly executed (if the condition is not satisfied from the start, the processing is not executed).

SPD chart

(WHILE: condition)

Processing

Example Buffers key until RETURN key is input

(WHILE: not RETURN key)

Inputs 1 character key

Stores input key to buffer

383

APPENDIX A DESCRIPTION OF SPD CHART

5. Conditional Loop (UNTIL)

The condition indicated by UNTIL is judged after processing has been executed, and the processing is repeatedly executed until a given condition is satisfied (even if the condition is not satisfied from the start, the processing is executed once).

SPD chart

(UNTIL: condition)

Processing

Example Multiplies value of B register by 10 and stores result to A register

Initializes A register

Sets value to B register

Stores 10 to counter

(UNTIL: counter = 0)

A = A + B

Decrements counter

6. Conditional Loop (FOR)

While the condition of the parameter indicated by FOR is satisfied, processing is repeatedly executed.

SPD chart

(FOR: initial value; condition; increment/decrement specification)

Processing

Example Clears 256 bytes to 0 starting from address HL

Sets first address to HL register

(FOR: WORKCT = #0; WORKCT < #256; WORKCT + +)

Clears address HL to 0

Increments HL register

384

APPENDIX A DESCRIPTION OF SPD CHART

7. Infinite Loop

If ‘forever’ is set as the condition of WHILE, processing is infinitely executed.

SPD chart

(WHILE: forever)

Processing

Example To execute main processing repeatedly

(WHILE: forever)

Decodes key

Stores key code to display area

Main processing

8. Connector (GOTO)

Unconditionally branches to a specified address.

SPD chart

(1) To branch to same module

ERR

(IF: condition)

[THEN]

GOTO ERR

.

.

.

Processing

385

APPENDIX A DESCRIPTION OF SPD CHART

(2) To branch to different module

(IF: condition)

[THEN]

GOTO ERR

(SUB_ER) ; Module name

SUB_ER Processing

.

.

.

ERR

Processing

Example To select a parameter at the start address of a subroutine and set wait state

WAIT10

WAIT20

WAIT30

WAIT

Sets 10 to A register

GOTO WAIT

Sets 20 to A register

GOTO WAIT

Sets 30 to A register

(UNTIL: A = 0)

Decrements A

9. Connector (continuation)

Used when the SPD of one module requires two or more pages to indicate the flow of processing.

SPD chart

Processing 1

Processing 2

1

1

Processing 3

Processing 4

386

APPENDIX B REVISION HISTORY

The revision history of this document is as follows. “Chapter” indicates the chapter number in the preceding edition.

(1/2)

Edition

2nd edition

Major Revision from Preceding Edition

Addition of following products as target products:

µ

PD780018, 780018Y, 780058, 780058Y, 780308, 780308Y,

78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries,

µ

PD78070A, 78070AY

µ

PD78052(A), 78053(A), 78054(A)

µ

PD78062(A), 78063(A), 78064(A)

µ

PD78081(A), 78082(A), 78P083(A), 78081(A2)

µ

PD78058F(A), 78058FY(A)

µ

PD78064B(A)

Deletion of following products as target products:

µ

PD78P054Y, 78P064Y, 78074, 78075, 78074Y, 78075Y

Addition of Note 2 and Caution 2 to Figure 4-5 Format of

Watchdog Timer Mode Register

Throughout

Chapter

CHAPTER 4 APPLICATION OF

WATCHDOG TIMER

Addition of Caution to Figure 5-8 Format of External Interrupt

Mode Register 0

CHAPTER 5 APPLICATION OF

16-BIT TIMER/EVENT COUNTER

Addition of Table 8-2 Items Supported by Each Subseries

CHAPTER 8 APPLICATION OF

SERIAL INTERFACE

Addition of Table 8-3 Registers of Serial Interface

Addition of note on using wake-up function and note on changing operation mode to Figures 8-7 and 8-8 Format of

Serial Operating Mode Register 0

Addition of Caution to Figures 8-16 and 8-17 Format of

Automatic Data Transmission/Reception Interval Specification

Register

Addition of Figures 8-23 and 8-24 Format of Serial Interface Pin

Select Register

µ

PD6252 as maintenance product in 8.1 Interface with

EEPROM

TM

(

µ

PD6252)

Addition of (5) Limitations when using I

2

C bus mode to 8.1.2

Communication in I

2

C bus mode

Addition of (f) Limitations when using UART mode to 8.5

Interface in Asynchronous Serial Interface (UART) Mode

387

Edition

2nd edition

APPENDIX B REVISION HISTORY

Major Revision from Preceding Edition

Description of following register formats and tables for each subseries:

Figures 8-14 and 8-15 Format of Automatic Data Transfer/

Reception Control Register

Tables 8-4, 8-5, and 8-6 Setting of Operating Modes of Serial

Interface Channel 2

Figures 12-1 and 12-2 Format of LCD Display Mode Register

Addition of Figure 11-3 Format of Port Mode Register 12

Description of following register formats for each subseries:

Figures 12-1 and 12-2 Format of LCD Display Mode Register

Chapter

CHAPTER 8 APPLICATION OF

SERIAL INTERFACE

CHAPTER 11 APPLICATION OF

REAL-TIME OUTPUT PORT

CHAPTER 12 APPLICATION OF

LCD CONTROLLER/DRIVER

(2/2)

388

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