C1-Q Series 2009-2 3/27/09 5:22 PM Page 17

The MELSEC Q Series Automation Platform

Q Series PACs are multi-disciplinary automation platforms addressing the needs of both OEMs and end users. The Q Series is the original multi-CPU system, with up to 4 CPUs to divide-and-conquer larger applications. It provides scalable automation solutions to both small and very large systems, offering a broad spectrum of automation capabilities. Additional CPUs and intelligent function module expansions allow the Q series to handle sophisticated motion, process control, PC and C language based control, MES IT interfacing, and numerous types of communication and networking.

Key Features: n CPU types ranging from small/medium systems, to complex networked systems with tens of thousands of I/O n Reduced lifecycle costs via remote system management & maintenance n Redundant CPU capability available for hot-backup of critical systems n Multiple CPU capability (up to 4 CPUs) adding open ended system performance and flexibility n Multiple programs allowing concurrent development, code reuse, better program organization and faster troubleshooting for less downtime n Multiple simultaneous access to the system allowing for faster system debugging and maintenance n Networking & communication options distribute Q Series systems over wide areas while reducing wiring costs n Sequence CPUs can also address process applications by means of built-in PID capabilities n Extremely compact package saves panel costs n Certified by UL, cUL, CE (as indicated), as well as DNV, ABS, RINA, BV,

LR and NK shipping approvals for all Q Series products

Required Manuals

Model Number

IB(NA)0800061

Description

QCPU(Q mode) CPU Module User’s Manual

(Hardware)

Contents

General specs, CE compliance information, Installation, safety requirements,

Power supply wiring, overview of system parts

Included with CPU?

No

(included with base units)

SH(NA)080483ENG

Q CPU (Q Mode) User’s Manual (Hardware

Design, Maintenance & Inspection)

CPU H/W specs, PSU spec, Base Unit specs, CE compliance information,

Maintenance & inspection, Installation, Troubleshooting

No (purchase separately)

SH(NA)080484ENG

SH(NA)080485ENG

SH(NA)080039

SH(NA)080041

SH(NA)080076

QCPU(Q Mode) User’s Manual (Function

Explanation, Program Fundamentals)

QCPU User’s Manual (Multiple CPU

System)

QCPU(Q Mode)/QnACPU Programming

Manual (Common Instructions)

QCPU(Q Mode)/QnACPU Programming

Manual (SFC)

Q CPU (Q Mode) Programming Manual

(MELSAP-L)

CPU specifications, system configuration, programming basics, I/O assignments, memory organization, CPU functions, communication with intelligent function modules, parameters & devices, program up/downloads, overview of multiple program architecture, programming basics, overview of multiple CPU system

Outline, system configuration, concept for multiple CPU system, communication between CPU modules, processing time of QCPU in multiple CPU system, parameter added for multiple CPU system, precautions for use of AnS Series module, starting up the multiple CPU system

General Description, Instruction Tables, Configuration of Instructions, How To

Read Instructions, Sequence Instructions, Basic Instructions, Application

Instructions, Instructions For Data Link, QCPU Instructions, Redundant System

Instructions, Error Codes

General Description, System Configuration, Specifications, SFC Program

Configuration, SFC Program Processing Sequence, SFC Program Execution

General Description, System Configuration, Specifications, SFC Program

Configuration, SFC Program Processing Sequence, SFC Program Execution

SH(NA)080040

QCPU(Q Mode)/QnACPU Programming

Manual (PID Control Instructions)

General Description, System Configuration for PID Control, PID Control

Specifications, Functions of PID Control, PID Control Procedure, PID Control

Instructions, How To Read Explanations For Instructions, Incomplete Derivative

PID Control Instructions and Program Examples, Complete Derivative PID Control

Instructions and Program Examples

SH(NA)080366

Programming Guide Book for

Structured Text (ST)

Covers Structured Text programming method

Note: Many of these manuals are available by free download from our website, www.meau.com

No (purchase separately)

No (purchase separately)

No (purchase separately)

No (purchase separately)

No (purchase separately)

No (purchase separately)

No (purchase separately)

Stk Item

–

–

–

–

–

–

–

–

–

A

MELSEC Q Series CPUs

Basic Model Sequence CPUs

These CPUs offer an economical entry-level version of the Q Series for small scale systems.

Key Features: n Multiple CPU support; use up to three CPUs to combine sequence, process, motion & PC control on a single system (Version B or later) n Compatible with Q Series Intelligent Function Utility configuration tools n Offers full range of Q Series network & communication features, including CC-Link IE 100Mbit Ethernet, MELSECNET/H n Integrated PSU, CPU and base unit available to simplify system construction with Q00JCPUs n Built in serial communications via CPU port (using MELSEC

Communication (MC) protocol) n Security functions n Flash memory for programs & parameters n Supports floating point, function block, PID and SFC programming

(Version B or later)

|

Programmable Automation Controller / PAC 17

C1-Q Series 2009-2 3/27/09 5:22 PM Page 18

18

MELSEC Q Series Basic Sequence CPU

Model Number

Stocked Item

Certification

Hardware Format

Control Method

I/O Control Method

Programming Language (Sequence Control Dedicated

Language)

Processing Speed

(Sequence Instruct)

LD X0

MOV (MOV D0 D1)

Total Number of Instructions

Q00JCPU-E

S

UL • cUL • CE

Combined CPU, PSU and

5-Slot Base Unit

200ns

700ns

Q00JCPU-S8 (*5)

S

UL • cUL • CE

Combined CPU, PSU and

8 slot Base Unit

Q00CPU

S

UL • cUL • CE

CPU only

Repeated operation using stored program

Refresh mode

Relay symbol type (ladder) logic symbolic language (list)

160ns

560ns

249 (excluding intelligent function module dedicated instructions)

Q01CPU

S

UL • cUL • CE

CPU only

100ns

350ns

Constant Scan (ms) (Program Start at Given Time Intervals)

Program Capacity (*1)

Program Memory (Drive 0)

8k steps (32 kbyte)

58 kbyte

1 to 2000ms (can be specified in 1ms increments)

8k steps (32 kbyte) 14k steps (56 kbyte)

Memory Capacity Standard RAM (Drive 3) 0

94 kbyte

128 kbyte

Number of Stored Programs

Number of Stored

File Registers

Number of I/O Device Points

Number of I/O Points

Internal Relay [M]

Latch Relay [L]

Link Relay [B]

Timer [T]

Retentive Timer [ST]

Counter [C]

Data Register [D]

Link Register [W]

Annunciator [F]

Edge Relay [V]

File Register

Special Link Relay [SB]

Special Link Register [SW]

Step Relay (*4)

Index Register [Z]

Pointer [P]

Interrupt Pointer [I]

Special Relay [SM]

Special Register [SD]

Function Input [FX]

Function Output [FY]

Function Register [FD]

Link Direct Device

Intelligent Function Module Direct Device

Latch (Power Failure Comp.) Range

Remote RUN/PAUSE Contact

Clock Function

Permissible Instantaneous Power Failure Time

5VDC Internal Current Consumption (A)

Weight (kg)

Dimensions W x H x D mm (in)

Standard ROM (Drive 4)

Program Memory

Standard ROM

Standard RAM

[R]

[ZR]

1

1

—

58 kbyte

1

1

—

1

1

1

94 kbyte

1

1

1

2048 points (X/Y0 to 7FF) (*2)

256 points (X/Y0 to FF) 1024 points (X/Y0 to 3FF) (*3)

Default 8192 points (M0 to 8191)

2048 points (L0 to 2047)

2048 points (B0 to 7FF)

Default 512 points (T0 to 511) (used as low-speed or high-speed timer)

Switching between low-speed and high-speed timers is set by instruction

Low-speed/high-speed timer timing increments are parameter-set

(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)

(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Default 0 point (ST0 to 511) (used as low-speed or high-speed timer)

Switching between low-speed and high-speed timers is set by instruction

Low-speed/high-speed timer timing increments are parameter-set.

(Low-speed timer: 1 to 1000ms, 1ms increments, default 100ms)

(High-speed timer: 0.1 to 100ms, 0.1ms increments, default 10ms)

Normal counters Default 512 points (C0 to 511)

Interrupt counters Max. 128 (Default 0 points, parameter setting)

Default 11136 points (D0 to 11135)

Default 2048 points (W0 to 7FF)

Default 1024 points (F0 to 1023)

Default 1024 points (V0 to 1023)

None

None

32768 points (R0 to 32767)

65536 points (ZR0 to 65535)

1024 points (SB0 to 3FF)

1024 points (SW0 to 3FF)

2048 points (SW0 to 3FF)

10 points (Z0 to 9)

300 points (P0 to 299)

128 points (I0 to 127)

In parameters, set the cyclic intervals of the system interrupt pointers I28 to I31 (2 to 1000ms, 1ms increments)

1024 points (SM0 to 1023)

245 (9.65) x 98 (3.86) x

98 (3.86)

1024 points (SD0 to 1023)

16 points (FX0 to F)

16 points (FY0 to F)

5 points (FD0 to 4)

Device for direct access to link device.

Dedicated. Specified format: J n

\ n

Device for direct access to buffer memory of intelligent function module.

Specified format: U n

\G n

L0 to 2047 (default)

(Latch range setting can be made for B, F, V, T, ST, C, W and D)

1 point can be set for each RUN and PAUSE contacts from X0-7FF.

Year, month, day, hour, minute, second, day of week

(Automatic leap year judgment)

Accuracy –3.2 to +5.27 (TYP +1.98) s/day at 0°C

20ms

Accuracy –2.57 to +5.27 (TYP +2.22) s/ day at 25°C

Accuracy –11.68 to +3.65 (TYP –2.64) s/ day at 55°C

Depends on power supply module

0.26 0.25

0.27

0.66

0.13

328 (12.92) x 98 (3.86) x

98 (3.86)

27.4 (1.08) x 98 (3.86) x 89.3 (3.52)

Notes:

1. Maximum actual program size is (program capacity—34 steps).

2. Sum of the number of I/O points on the main/extension base directly controlled by the CPU module and the number of I/O points controlled as remote I/O by the remote I/O network.

3. Number of I/O points on the main/extension base directly controlled by the CPU module.

4. The “Step relay” is a device for the SFC function, only applicable to version B CPUs or higher.

5. Q00JCPU-S8 has the same functionalities as Q00JCPU-E.

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