1.1 Product Summary - Panasonic Corporation

MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.1 Product Summary
This LSI user's manual describes MN101LR05D/04D/03D/02D.
The detail of product specification is described mainly about MN101LR05D.
For the difference between each product, See [1.3 Comparison of Product Specification] and [1.4.1 Pin Configuration].
VDD18 voltage after reset release, oscillation stabilization wait time after reset release and ROM capacity vary
depending on the ROM name of each product. Table: 1.1.1 shows the difference of specifications between the
ROM name.
Table:1.1.1 Product Summary
Product Name
ROM name * VDD18 voltage after
reset release
Oscillation stabilization wait time after
reset release
ROM (ReRAM) capacity
(Program area/Data area)
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
XW
211/(fSRC/2)
62 KB / 2 KB
1.1 V
XX
59 KB / 4 KB
XY
53 KB / 8 KB
XZ
41 KB / 16 KB
XA
1.8 V
28/(fSRC/2)
62 KB / 2 KB
XB
59 KB / 4 KB
XC
53 KB / 8 KB
XD
41 KB / 16 KB
* ROM name: XA/XB/XC/XD/XW/XX/XY/XZ indicates the product that ReRAM is blank.
When using the debugger or programmer, set "Product name + ROM name"
(e.g.: MN101LR05DXA/XW) in the field "Product type" or "Microcomputer product type".
..
When "ROM name" is set incorrectly, connect error is occurred.
When nothing is set to "ROM name", XA/XW is selected.
(e.g.: MN101LR05D  MN101LR05DXA/XW)
..
Publication date: October 2014
1
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.2 Hardware Features
 Features
In this document, the divided clock and the frequency of it are described as follows:
Divided clock:Clock name/n (n: division ratio)
Frequency: fClock name
• CPU Core
- AM13L core
- LOAD-STORE architecture (3- or 4-stage Pipeline)
• Machine Cycle and Operating Voltage
- High-Speed mode
100 ns / 10 MHz (Max) (VDD30: 1.8 V to 3.6 V)
1.0 s / 1 MHz (Max) (VDD30: 1.3 V to 3.6 V)
- Low-Speed Mode
25 s / 40 kHz (Max) (VDD30: 1.1 V to 3.6 V)
• Operating Mode
- NORMAL mode (High-Speed mode)
- SLOW mode
(Low-Speed mode)
- HALT mode
(High-Speed/Low-Speed mode)
- STOP mode
• Embedded Memory
- ROM (ReRAM): 64 KB (Programmable area and Data area vary depending on the ROM name.
For details, see Table:1.1.1.)
- RAM:
4 KB
• ReRAM Specification
- Program voltage (VDD30): 1.8 V to 3.6 V
- Program cycles:
1000 times (Program area), 100000 times (Data area)
- Data is rewritable in bytes without data erase.
• Clock Oscillator (4 circuits)
- External Low-Speed Oscillation (SOSCCLK): 32.768 kHz (crystal or ceramic)
- External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic)
- Internal Low-Speed Oscillation (SRCCLK):
40 kHz ± 20 % (VDD30: 1.1 V to 3.6 V)
- Internal High-Speed Oscillation (HRCCLK): 10/8 MHz ± 3 % (VDD30: 1.8 V to 3.6 V)
1 MHz ± 10 % (VDD30: 1.3 V to 3.6 V)
* MN101LR02D does not have external high-speed oscillation (HOSCCLK).
• Internal Operating Clock
- System Clock (SYSCLK): 10 MHz (Max)
SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32.
HCLK: HOSCCLK or HRCCLK
SCLK: SOSCCLK or SRCCLK
* MN101LR02D cannot be selected HOSCCLK.
Publication date: October 2014
2
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
• Interrupt Circuit
MN101LR05D/04D/03D: 31 internal interrupts (except for NMI)
8 external interrupts (IRQ interrupt: 7, KEY interrupt: 1)
MN101LR02D:
29 internal interrupts (except for NMI)
3 external interrupts (IRQ interrupt: 2, KEY interrupt: 1)
• DMA (1 channel)
- Data transfer size:
8 bits/16 bits
- Maximum transfer counts: 1023
- Activation trigger:
external interrupts / internal interrupts / software (setting the DMA start bit)
• Watchdog Timer (WDT)
- Function:
1st watchdog time-out generates NMI, and 2nd consecutive time-out generates a LSI reset.
- Clock Source: WDTCLK (SOSCCLK or SRCCLK)
• Timer Counter: 13 units
- General-purpose 8-bit timer (Timer 0/1/2/3/4/5): 6 units
- General-purpose 16-bit timer (Timer 7/8/9):
3 units
- 8-bit free-run (Timer 6) /Time-base timer:
1 unit each
- RTC time base timer (RTC-TBT):
1 unit
- Real Time Clock (RTC):
1 unit
<Timer 0>
- Function:
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM0IO input
<Timer 1 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 0)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM1IO input
<Timer 2>
- Function:
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM2IO input
* MN101LR02D cannot be used simple pulse width measurement.
<Timer 3 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 2)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM3IO input
<Timer 4>
- Function:
Square wave output, additional pulse PWM output, event count,
simple pulse width measurement
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/32, HCLK/64, SCLK, SYSCLK/2, SYSCLK/4,
or TM4IO input
<Timer 5 >
- Function:
Square wave output, event count, 16-bit cascade connection (connected with Timer 4)
- Clock Source: HCLK, HCLK/4, HCLK/16, HCLK/64, HCLK/128, SCLK, SYSCLK/2, SYSCLK/8,
or TM5IO input
* MN101LR02D cannot be used square wave output, event count and TM5IO.
Publication date: October 2014
3
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
<Timer 6>
- Function:
One-minute timer can be generated in combination with a time base timer.
- Clock Source: HCLK, HCLK/27, HCLK/213, SYSCLK, SCLK, SCLK/27 or SCLK/213
<Time Base Timer>
- Function:
An interrupt can be generated at a given set time.
- Clock Source: HCLK or SCLK
- Interrupt generation cycle: 2N/fHCLK, 2N/fSCLK (N = 7, 8, 9, 10, 12, 13, 14, 15)
<Timer 7>
- Function:
Square wave output, PWM output (duty/cycle are programmable), one-shot pulse output,
IGBT output, event count, and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM7IO input by 1, 2, 4 or 16.
<Timer 8 >
- Function:
Square wave output, PWM output (duty/cycle are programmable), event count,
and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM8IO input by 1, 2, 4 or 16.
<Timer 9 >
- Function:
Square wave output, PWM output (duty/cycle are programmable), event count,
and input capture
- Clock Source: Generated clock by dividing HCLK, SYSCLK, SCLK, or TM9IO input by 1, 2, 4 or 16.
* MN101LR03D and MN101LR02D
cannot be used square wave output, PWM output, event count and TM9IO.
<RTC time base timer (RTC-TBT)>
- Function:
Clock generation for the Real Time Clock (RTC)
Frequency correction
(Correction Range: ±488 ppm to ±31220 ppm, Accuracy: approx. 0.48 ppm to 30.52 ppm)
- Clock Source: SOSCCLK or SRCCLK
<Real Time Clock (RTC)>
- Function: Calendar calculation, adjustment of leap year
Periodic interrupt (0.5 s, 1 s, 1 min or 1 hour)
Alarm0 interrupt (date/hour/minute), Alarm1 interrupt (month/day/hour/minute)
• Buzzer Output/Inverted Buzzer Output
- Output frequency: fHCLK/2M (M = 9, 10, 11, 12, 13, 14), fSCLK/2N (N = 3, 4)
* MN101LR02D can be used inverted buzzer output only.
• Serial Interface: 4 units
<Serial Interface 0, 1> (Full duplex UART/Clock synchronous serial)
- Function:
Full duplex UART:
Parity check, Detection of overrun error/framing error, Selectable transfer bits of 7 or 8
Clock synchronous serial (SPI compatible):
2,3 or 4-wire communication, MSB/LSB first selectable, multiple bytes transmission is available.
- Clock Source: external clock, dedicated baud rate timer
<Serial Interface 2, 3> (Multi-master IIC/Clock synchronous serial)
- Function:
Multi-master IIC
Clock synchronous serial (SPI compatible):
2,3 or 4-wire communication, MSB/LSB first selectable, multiple bytes transmission is available.
- Clock Source: external clock, dedicated baud rate timer
Publication date: October 2014
4
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
* MN101LR03D
Serial Interface 3: Clock synchronous serial can be used in 2-wire communication only,
and is not compatible with SPI. (Chip select pin is not assigned.)
* MN101LR02D
Serial Interface 1: Not implemented
Serial Interface 3: Clock synchronous serial can be used in 2 or 3-wire communication,
and is not compatible with SPI. (Chip select pin is not assigned.)
• A/D Converter (ADC): 1 unit
- Resolution: 12 bits
- Analog signal input channel
MN101LR05D: 8 channels
MN101LR04D: 6 channels
MN101LR03D: 4 channels
MN101LR02D: 3 channels
• I/O ports
MN101LR05D: 69 pins (selectable N-channel transistor drive strength: 55 pins)
MN101LR04D: 53 pins (selectable N-channel transistor drive strength: 41 pins)
MN101LR03D: 37 pins (selectable N-channel transistor drive strength: 27 pins)
MN101LR02D: 22 pins (selectable N-channel transistor drive strength: 19 pins)
• Clock Output
- HCLK, SCLK, SYSCLK or RTCCLK can be output.
• Automatic Reset Circuit
• Low-voltage Detection Circuit (LVI)
• LCD Driver
<MN101LR05D>
43 segment outputs, 4 common outputs (39 segment outputs, 8 common outputs)
Display mode: Static, 1/2 to 1/8 duty
Bias: 1/2, 1/3 (Built-in boost/ External resistor divider)
<MN101LR04D>
31 segment outputs, 4 common outputs
Display mode: Static, 1/2 to 1/4 duty
<MN101LR03D>
21 segment outputs, 4 common outputs
Display mode: Static, 1/2 to 1/4 duty
* MN101LR02D does not have LCD driver function.
Publication date: October 2014
5
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
• Package
MN101LR05D: TQFP080-P-1212
MN101LR04D: TQFP064-P-1010
MN101LR03D: TQFP048-P-0707
MN101LR02D: HQFN032-A-0505
(12 mm square, 0.5 mm pitch, halogen free)
(10 mm square, 0.5 mm pitch, halogen free)
( 7 mm square, 0.5 mm pitch, halogen free)
( 5 mm square, 0.5 mm pitch, halogen free)
Panasonic "halogen free" semiconductor products refer to the products made of molding resin and interposer
which conform to the following standards.
- Bromine:
900 ppm (Maximum Concentration Value)
- Chlorine:
900 ppm (Maximum Concentration Value)
- Bromine + Chlorine: 1500 ppm (Maximum Concentration Value)
The above-mentioned standards are based on the numerical value described in IEC61249-2-21.
Antimony and its compounds are not added intentionally.
• Operating Ambient Temperature: Ta = -40 C to 85 C
Publication date: October 2014
6
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.3 Comparison of Product Specification
Table:1.3.1 Functions
Function
Specification
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
Port
I/O port
69 pins
53 pins
37 pins
22 pins
55 pins
41 pins
27 pins
19 pins
Internal interrupt
31
31
31
29
External interrupt
8
8
8
3
(7: IRQ0-6, 1: KEY0-7) (7: IRQ0-6, 1: KEY1-7) (7: IRQ0-6, 1: KEY1-5) (2: IRQ4-5, 1: KEY1-7)
Timer 5
Timer I/O
TM5IO
TM5IO
TM5IO
- (*1)
Timer 9
Timer I/O
TM9IO
TM9IO
- (*1)
- (*1)



-
Serial communication
pins
SBO3/SDA3
SBT3/SCL3
SBI3
SBCS3
SBO3/SDA3
SBT3/SCL3
SBI3
SBCS3
SBO3/SDA3
SBT3/SCL3
-
SBO3/SDA3
SBT3/SCL3
SBI3
-
Clock synchronous
2, 3 or 4-wire
2, 3 or 4-wire
2-wire
2 or 3-wire
SPI compatible


- (*2)
- (*2)
N-channel transistor
drive strength
Interrupt
Serial
interface 1
Serial
interface 3
Buzzer
Buzzer output
BUZ
/Inverted buzzer output NBUZ
BUZ
NBUZ
BUZ
NBUZ
NBUZ
ADC
Analog input
8 pins (AN0-7)
6 pins (AN2-7)
4 pins (AN2-5)
3 pins (AN3-5)
43 pins (SEG0-42)
/39 pins (SEG4-42)
31 pins (SEG0-30)
21 pins (SEG0-20)
-
4 pins (COM0-3)
/8 pins (COM0-7)
4 pins (COM0-3)
4 pins (COM0-3)
-
Oscillation
HOSCCLK
SOSCCLK
HRCCLK
SRCCLK
HOSCCLK
SOSCCLK
HRCCLK
SRCCLK
HOSCCLK
SOSCCLK
HRCCLK
SRCCLK
SOSCCLK
HRCCLK
SRCCLK
Package
80-pin TQFP
64-pin TQFP
48-pin TQFP
32-pin HQFN
LCD driver Segment output
Common output
*1 Timer function is available.
*2 Chip select pin is not assigned.
Publication date: October 2014
7
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Table:1.3.2 Functions of I/O Port
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
I/O
Port
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port0














-
-
-
-


-
-
-
-
-



-
-
-
-
Port1














-
-
-
-




-
-
-
-



-
-
-
Port2










-
-
-
-




-
-
-
-
-
-

-
-
-
-
-
-
-
Port3




























-
-
-
-
Port4
















-
-
-





-
-
-





Port5











-
-
-
-




-
-
-
-
-



-
-
-
-
-
Port6
















-
-
-
-








-
-
-
-
Port7








-
-
-
-




-
-
-
-




-
-
-
-
-
-
-
-
Port8
-
-






-
-






-
-






-
-
-
-
-
-
-
-

: implemented I/O port

: implemented I/O port (selectable N-channel transistor drive strength)
-
: not implemented
Table:1.3.3 Functions of LCD Control
MN101LR05D
I/O
Port
7
Port2
-
6
5
4
3
MN101LR04D
2
1
0
SEG SEG SEG SEG SEG SEG SEG
36
37
38
39
40
41
42
MN101LR03D
7
6
5
4
3
2
-
SEG
28
-
-
-
-
1
0
SEG SEG
29
30
7
6
5
4
3
2
1
0
-
SEG
20
-
-
-
-
-
-
Port3 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
28
29
30
31
32
33
34
35
20
21
22
23
24
25
26
27
12
13
14
15
16
17
18
19
Port4 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
20
21
22
23
24
25
26
27
12
13
14
15
16
17
18
19
Port5 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
12
13
14
15
16
17
18
19
8
9
10
-
-
-
-
-
-
-
SEG SEG SEG SEG
11
4
5
6
SEG SEG SEG SEG SEG
7
8
9
10
11
-
-
-
-
-
Port6 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
-
-
-
-
SEG SEG SEG SEG
0
1
2
3
Port7 COM COM COM COM COM COM COM COM
0
1
2
3
4/
5/
6/
7/
SEG SEG SEG SEG
0
1
2
3
-
-
-
-
-
-
COM COM COM COM
0
1
2
3
Port8
-
-
-
-
-
-
-
VLC VLC
2
3
C2
C1
-
-
VLC1
-
-
COM COM COM COM
0
1
2
3
VLC VLC
2
3
C2
VLC1
C1
-
-
VLC VLC
2
3
C2
C1
-
VLC1
-: not implemented
LCD control function is not implemented in MN101LR02D.
Set "0" to the registers and bits corresponding to the functions which are not implemented.
..
Publication date: October 2014
8
-
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Table:1.3.4 Pin Functions
Pin No.
MN101 MN101 MN101 MN101
LR05D LR04D LR03D LR02D
Power supply
/Oscillations
/Reset
/Mode control
Port
External
interrupt
/KEY interrupt
1
1
1
32
2
2
2
1
XI
3
3
3
2
XO
4
4
4
3
NATRON
5
5
5
4
NRST
P27
6
6
6
OSC1
P80
IRQ2A
7
7
7
OSC2
P81
IRQ3A
Timer
Serial
interface
Buzzer
/Clock output
A/D
VSS
8
P00
TM9IOC
9
P01
TM4IOB
10
8
P02
TM2IOB/TM8IOC
BUZB
11
9
P03
TM0IOB/TM7IOC
NBUZB
12
10
8
5
P04
13
11
9
6
P05
14
12
7
P06
15
13
TM7IOA
SBO3A/SDA3A
TM0IOA/TM2IOA SBT3A/SCL3A
P07
TM8IOB
SBI3A
TM9IOA
SBCS3A
CLKOUTA
16
P10
IRQ0A/KEY0A
AN0
17
P11
IRQ1A/KEY1A
AN1
18
14
10
19
15
11
8
P12
IRQ4C/KEY2A
AN2
P13
IRQ5C/KEY3A
AN3
20
16
12
9
21
17
13
10
DMOD
22
18
14
11
OCD_CLK
P14
IRQ4A/KEY4A
AN4
23
19
15
12
24
20
OCD_DATA
P15
IRQ5A/KEY5A
AN5
P16
IRQ6A/KEY6A
25
21
AN6
P17
KEY7A
AN7
VREFP
26
22
P20
TM1IOB/TM9IOB
27
23
P21
TM5IOA
28
P22
SBI2B
29
P23
SBO2B/SDA2B
30
P24
SBT2B/SCL2B
31
P25
SBCS2B
32
24
16
P26
SBI1A/RXD1A
33
25
17
P30
SBO1A/TXD1A
34
26
18
P31
SBT1A
35
27
19
P32
SBCS1A
36
28
20
37
29
21
13
P34
38
30
22
14
P35
SBI0B/RXD0B
SBO0B/TXD0B
P33
BUZA
TM4IOA/TM7IOB
NBUZA
39
31
23
15
P36
40
32
24
16
P37
SBT0B
41
33
25
17
P40
SBCS0B
42
34
26
18
P41
SBI2A
43
35
27
19
P42
SBO2A/SDA2A
44
36
28
20
P43
SBT2A/SCL2A
Publication date: October 2014
9
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Pin No.
Power supply
/Oscillations
MN101 MN101 MN101 MN101
/Reset
LR05D LR04D LR03D LR02D
/Mode control
Port
45
37
P44
SBCS2A
46
38
P45
SBI1B/RXD1B
SBO1B/TXD1B
29
21
External
interrupt
/KEY interrupt
Timer
Serial
interface
47
39
P46
48
40
P47
SBT1B
49
41
P50
SBCS1B
50
P51
SBI3B
51
P52
SBO3B/SDA3B
52
P53
SBT3B/SCL3B
53
P54
KEY0B
54
42
30
22
P55
KEY1B
TM1IOA
55
43
31
23
P56
KEY2B
TM3IOA
56
44
32
24
P57
KEY3B
TM8IOA
57
45
33
P60
IRQ0B
58
46
34
P61
IRQ1B
59
47
35
P62
IRQ2B
60
48
36
P63
IRQ3B
61
49
25
P64
KEY4B
SBI0A/RXD0A
62
50
26
P65
KEY5B
SBO0A/TXD0A
CLKOUTB
51
27
P66
KEY6B
SBT0A
64
52
28
P67
KEY7B
SBCS0A
65
53
37
P70
IRQ6B
66
54
38
P71
IRQ5B
67
55
39
P72
IRQ4B
68
56
40
P73
P74
70
P75
71
P76
72
A/D
SBCS3B
63
69
Buzzer
/Clock output
TM3IOB
TM5IOB
P77
73
57
41
C1
74
58
42
C2
P83
75
59
43
VLC3
P84
76
60
44
VLC2
P85
77
61
45
78
62
46
29
VDD30
79
63
47
30
VDD18
80
64
48
31
VDD11
P82
VLC1
* See Table:1.3.3 for LCD control pins.
Publication date: October 2014
10
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.4 Pin Description
Pin Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VDD11
VDD18
VDD30
VLC1
P85/VLC2
P84/VLC3
P83/C2
P82/C1
P77/COM0
P76/COM1
P75/COM2
P74/COM3
P73/COM4/SEG0 /TM5IOB
P72/COM5/SEG1 /IRQ4B/TM3IOB
P71/COM6/SEG2 /IRQ5B
P70/COM7/SEG3 /IRQ6B
P67/SEG4/SBCS0A/KEY7B
P66/SEG5/SBT0A /KEY6B
P65/SEG6/SBO0A /TXD0A/KEY5B
P64/SEG7/SBI0A /RXD0A/KEY4B
1.4.1
MN101LR05D
80 pin
(Top View)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P63/SEG8 /IRQ3B
P62/SEG9 /IRQ2B
P61/SEG10/IRQ1B
P60/SEG11/IRQ0B
P57/SEG12/TM8IOA /KEY3B/CLKOUTB
P56/SEG13/TM3IOA /KEY2B
P55/SEG14/TM1IOA /KEY1B
P54/SEG15/SBCS3B/KEY0B
P53/SEG16/SBT3B /SCL3B
P52/SEG17/SBO3B /SDA3B
P51/SEG18/SBI3B
P50/SEG19/SBCS1B
P47/SEG20/SBT1B
P46/SEG21/SBO1B /TXD1B
P45/SEG22/SBI1B /RXD1B
P44/SEG23/SBCS2A
P43/SEG24/SBT2A /SCL2A
P42/SEG25/SBO2A /SDA2A
P41/SEG26/SBI2A
P40/SEG27/SBCS0B
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DMOD
OCD_CLK/IRQ4A/ KEY4A/ AN4/P14
OCD_DATA/IRQ5A/ KEY5A/ AN5/P15
IRQ6A/ KEY6A/ AN6/P16
KEY7A/ AN7/P17
TM9IOB/TM1IOB/SEG42/P20
TM5IOA/SEG41/P21
SBI2B/SEG40/P22
SBO2B/ SDA2B/SEG39/P23
SBT2B/ SCL2B/SEG38/P24
SBCS2B/SEG37/P25
SBI1A/ RXD1A/SEG36/P26
SBO1A/ TXD1A/SEG35/P30
SBT1A/SEG34/P31
SBCS1A/SEG33/P32
BUZA/SEG32/P33
NBUZA/TM4IOA/TM7IOB/SEG31/P34
SBI0B/ RXD0B/SEG30/P35
SBO0B/ TXD0B/SEG29/P36
SBT0B/SEG28/P37
VSS
XI
XO
NATRON
P27/NRST
IRQ2A/ OSC1/P80
IRQ3A/ OSC2/P81
TM9IOC/P00
TM4IOB/P01
TM8IOC/TM2IOB/ BUZB/P02
TM7IOC/TM0IOB/ NBUZB/P03
TM7IOA/ SBO3A/ SDA3A/P04
CLKOUTA/TM2IOA/TM0IOA/ SBT3A/ SCL3A/P05
TM8IOB/ SBI3A/P06
TM9IOA/SBCS3A/P07
IRQ0A/ KEY0A/
AN0/P10
IRQ1A/ KEY1A/
AN1/P11
IRQ4C/ KEY2A/
AN2/P12
IRQ5C/ KEY3A/
AN3/P13
VREFP
Figure:1.4.1 MN101LR05D Pin Configuration
Publication date: October 2014
11
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD11
VDD18
VDD30
VLC1
P85/VLC2
P84/VLC3
P83/C2
P82/C1
P73/COM0/TM5IOB
P72/COM1/IRQ4B /TM3IOB
P71/COM2/IRQ5B
P70/COM3/IRQ6B
P67/SEG0/SBCS0A/KEY7B
P66/SEG1/SBT0A /KEY6B
P65/SEG2/SBO0A /TXD0A/KEY5B
P64/SEG3/SBI0A /RXD0A/KEY4B
PubNo. 21705-019E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MN101LR04D
64 pin
(Top View)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P63/SEG4 /IRQ3B
P62/SEG5 /IRQ2B
P61/SEG6 /IRQ1B
P60/SEG7 /IRQ0B
P57/SEG8 /TM8IOA/KEY3B/CLKOUTB
P56/SEG9 /TM3IOA/KEY2B
P55/SEG10/TM1IOA/KEY1B
P50/SEG11/SBCS1B
P47/SEG12/SBT1B
P46/SEG13/SBO1B /TXD1B
P45/SEG14/SBI1B /RXD1B
P44/SEG15/SBCS2A
P43/SEG16/SBT2A /SCL2A
P42/SEG17/SBO2A /SDA2A
P41/SEG18/SBI2A
P40/SEG19/SBCS0B
DMOD
OCD_CLK/IRQ4A/ KEY4A/ AN4/P14
OCD_DATA/IRQ5A/ KEY5A/ AN5/P15
IRQ6A/ KEY6A/ AN6/P16
KEY7A/ AN7/P17
TM9IOB/TM1IOB/SEG30/P20
TM5IOA/SEG29/P21
SBI1A/ RXD1A/SEG28/P26
SBO1A/ TXD1A/SEG27/P30
SBT1A/SEG26/P31
SBCS1A/SEG25/P32
BUZA/SEG24/P33
NBUZA/TM4IOA/TM7IOB/SEG23/P34
SBI0B/ RXD0B/SEG22/P35
SBO0B/ TXD0B/SEG21/P36
SBT0B/SEG20/P37
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
XI
XO
NATRON
P27/NRST
IRQ2A/ OSC1/P80
IRQ3A/ OSC2/P81
TM8IOC/TM2IOB/ BUZB/P02
TM7IOC/TM0IOB/ NBUZB/P03
TM7IOA/ SBO3A/ SDA3A/P04
CLKOUTA/TM2IOA/TM0IOA/ SBT3A/ SCL3A/P05
TM8IOB/ SBI3A/P06
TM9IOA/SBCS3A/P07
IRQ4C/ KEY2A/
AN2/P12
IRQ5C/ KEY3A/
AN3/P13
VREFP
Figure:1.4.2 MN101LR04D Pin Configuration
Publication date: October 2014
12
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
48
47
46
45
44
43
42
41
40
39
38
37
VDD11
VDD18
VDD30
VLC1
P85/VLC2
P84/VLC3
P83/C2
P82/C1
P73/COM0/TM5IOB
P72/COM1/IRQ4B/TM3IOB
P71/COM2/IRQ5B
P70/COM3/IRQ6B
PubNo. 21705-019E
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
MN101LR03D
48 pin
(Top View)
P63/SEG0 /IRQ3B
P62/SEG1 /IRQ2B
P61/SEG2 /IRQ1B
P60/SEG3 /IRQ0B
P57/SEG4 /TM8IOA/KEY3B/CLKOUTB
P56/SEG5 /TM3IOA/KEY2B
P55/SEG6 /TM1IOA/KEY1B
P44/SEG7 /SBCS2A
P43/SEG8 /SBT2A /SCL2A
P42/SEG9 /SBO2A /SDA2A
P41/SEG10/SBI2A
P40/SEG11/SBCS0B
DMOD
OCD_CLK/IRQ4A/ KEY4A/ AN4/P14
OCD_DATA/IRQ5A/ KEY5A/ AN5/P15
SBI1A/ RXD1A/SEG20/P26
SBO1A/ TXD1A/SEG19/P30
SBT1A/SEG18/P31
SBCS1A/SEG17/P32
BUZA/SEG16/P33
NBUZA/TM4IOA/TM7IOB/SEG15/P34
SBI0B/ RXD0B/SEG14/P35
SBO0B/ TXD0B/SEG13/P36
SBT0B/SEG12/P37
13
14
15
16
17
18
19
20
21
22
23
24
VSS
XI
XO
NATRON
P27/NRST
IRQ2A/ OSC1/P80
IRQ3A/ OSC2/P81
TM7IOA/SBO3A/SDA3A/P04
CLKOUTA/TM2IOA/TM0IOA/ SBT3A/SCL3A/P05
IRQ4C/ KEY2A/ AN2/P12
IRQ5C/ KEY3A/ AN3/P13
VREFP
VDD30
P67/SBCS0A/KEY7B
P66/SBT0A /KEY6B
P65/SBO0A /TXD0A/KEY5B
P64/SBI0A /RXD0A/KEY4B
27
26
25
VDD18
30
28
VDD11
31
29
VSS
32
Figure:1.4.3 MN101LR03D Pin Configuration
XI
1
24
XO
2
23
P56/TM3IOA/KEY2B
NATRON
3
22
P55/TM1IOA/KEY1B
21
P44/SBCS2A
20
P43/SBT2A /SCL2A
19
P42/SBO2A /SDA2A
MN101LR02D
32 pin
(Top View)
P57/TM8IOA/KEY3B/CLKOUTB
13
14
15
16
NBUZA/TM4IOA/TM7IOB/P34
SBI0B/ RXD0B/P35
SBO0B/ TXD0B/P36
SBT0B/P37
P40/SBCS0B
12
17
AN3/P13
AN5/P15
P41/SBI2A
8
IRQ5C/KEY3A/
OCD_DATA/IRQ5A/ KEY5A/
18
11
7
10
TM8IOB/ SBI3A/P06
DMOD
6
AN4/P14
CLKOUTA/TM2IOA/TM0IOA/SBT3A/SCL3A/P05
OCD_CLK/IRQ4A/ KEY4A/
5
9
4
VREFP
P27/NRST
TM7IOA/SBO3A/SDA3A/P04
Figure:1.4.4 MN101LR02D Pin Configuration
Publication date: October 2014
13
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.4.2
Pin Description
Table:1.4.1 Power Supply/Oscillation/Reset/Mode Pin
Pin name
MN101LR
05D/04D/03D
MN101LR
02D
Input/
Output
Description
VDD30
VSS
-
Power supply pin
Connect the capacitor of 1 F or more between VDD30 and VSS.
Apply 0 V to VSS.
VDD18
-
Internal power output pin
Connect the capacitor of 1 F between VDD18 and VSS to stable VDD18.
Connect the bypass capacitor of 0.1 F between VDD18 and VSS.
VDD11
-
Internal power output pin (1.1 V)
Connect the capacitor of 1 F or more between VDD11 and VSS.
VLC1
VLC2
VLC3
-
-
LCD power supply pin
Supply the power under the following conditions.
(VDD30  VLC1  3.6 V and 0 V  VLC3  VLC2  VLC1)
Capacitors described in [17.3.4 LCD Drive Voltage Selection] must be connected in each pin.
When LCD function is not used, connect VLC1 to VDD30.
C1
C2
-
-
LCD voltage boost capacitor pin
When using the internal LCD booster circuit, connect the capacitor of 0.22 F between C1 and
C2.
-
ADC Reference power supply pin
When ADC is not used, connect VREFP to VDD30.
The voltage level of VREFP must be over 0.8 VDD30 at any time including LSI power on.
VREFP
OSC1
OSC2
-
Input
Output
External high-speed oscillation pin
When the external high-speed oscillation is needed, connect the oscillator to the pins.
The external clock can be input through OSC1, and leave OSC2 open.
XI
XO
Input
Output
External low-speed oscillation pin
When the external low-speed oscillation is needed, connect the oscillator to the pins.
NRST
Input
Output
Reset pin (N-channel open drain pin)
When NRST is set to "Low", LSI is initialized. LSI reset condition is described in [2.5 Reset].
DMOD
Input
Mode setting pin
Always set DMOD to "Low" level, except for connecting the external LSI debugger or serial programmer.
NATRON
Input
Auto reset control pin
To use the auto reset function, set NATRON to "Low" level.
If not, set NATRON to "High" level.
The voltage level of VREFP must be over 0.8 VDD30 at any time including LSI power on.
..
..
Publication date: October 2014
14
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Table:1.4.2 General-purpose Port Function Pin
Pin name
MN101LR MN101LR MN101LR MN101LR
05D
04D
03D
02D
Input/
Output
Output
drive strength
selectable
P00
-
-
-
Yes
P01
-
-
-
Yes
P02
P02
-
-
Yes
P03
P03
-
-
P04
P04
P04
P04
P05
P05
P05
P05
Yes
P06
P06
-
P06
Yes
P07
P07
-
-
Yes
P10
-
-
-
No
P11
-
-
-
No
P12
P12
P12
-
No
P13
P13
P13
P13
P14
P14
P14
P14
P15
P15
P15
P15
No
P16
P16
-
-
No
P17
P17
-
-
No
P20
P20
-
-
Yes
P21
P21
-
-
Yes
P22
-
-
-
Input/
Output
Input/
Output
Yes
Port 1
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
No
No
P23
-
-
-
P24
-
-
-
Yes
P25
-
-
-
Yes
P26
P26
P26
-
Yes
P27
P27
P27
P27
P30
P30
P30
P31
P31
P32
Yes
Port 2
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
No
Port 2
-LSI is reset by setting P2OUT.P2OUT7 to "0".
-
Yes
P31
-
Yes
P32
P32
-
Yes
P33
P33
P33
-
Port 3
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
P34
P34
P34
P34
P35
P35
P35
P35
Yes
P36
P36
P36
P36
Yes
P37
P37
P37
P37
Yes
Publication date: October 2014
Input/
Output
Port 0
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
Yes
Yes
Input/
Output
Description
Input/
Output
Yes
Yes
15
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Pin name
MN101LR MN101LR MN101LR MN101LR
05D
04D
03D
02D
Input/
Output
Output
drive strength
selectable
P40
P40
P40
P40
Yes
P41
P41
P41
P41
Yes
P42
P42
P42
P42
Yes
P43
P43
P43
P43
P44
P44
P44
P44
P45
P45
-
-
Yes
P46
P46
-
-
Yes
P47
P47
-
-
Yes
P50
P50
-
-
Yes
P51
-
-
-
Yes
P52
-
-
-
Yes
P53
-
-
-
P54
-
-
-
P55
P55
P55
P55
Yes
P56
P56
P56
P56
Yes
P57
P57
P57
P57
Yes
P60
P60
P60
-
Yes
P61
P61
P61
-
Yes
P62
P62
P62
-
Yes
P63
P63
P63
-
P64
P64
-
P64
P65
P65
-
P65
Yes
P66
P66
-
P66
Yes
P67
P67
-
P67
Yes
P70
P70
P70
-
Yes
P71
P71
P71
-
Yes
P72
P72
P72
-
Yes
P73
P73
P73
-
P74
-
-
-
P75
-
-
-
Yes
P76
-
-
-
Yes
P77
-
-
-
Yes
P80
P80
P80
-
No
P81
P81
P81
-
No
P82
P82
P82
-
P83
P83
P83
-
P84
P84
P84
-
No
P85
P85
P85
-
No
Publication date: October 2014
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Yes
Description
Port 4
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
Yes
Yes
Port 5
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
Yes
Yes
Port 6
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
Yes
Yes
Port 7
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
-The drive strength of output Nch transistor can be changed.
Yes
No
Port 8
-At each port, the I/O direction and the pull-up resistor connection is controlled individually.
-At LSI reset, each pin is set to input mode and the pull-up
resistor is not connected.
No
16
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Table:1.4.3 Special Function Pin
Pin name
MN101LR05D
MN101LR04D
SBI0A(RXD0A)
SBI0B(RXD0B)
SBI1A(RXD1A)
SBI1B(RXD1B)
SBI2A
SBI2B
SBI3A
SBI3B
SBI0A(RXD0A)
SBI0B(RXD0B)
SBI1A(RXD1A)
SBI1B(RXD1B)
SBI2A
SBO0A(TXD0A)
SBO0B(TXD0B)
SBO1A(TXD1A)
SBO1B(TXD1B)
SBO2A(SDA2A)
SBO2B(SDA2B)
SBO3A(SDA3A)
SBO3B(SDA3B)
SBO0A(TXD0A)
SBO0B(TXD0B)
SBO1A(TXD1A)
SBO1B(TXD1B)
SBO2A(SDA2A)
SBT0A
SBT0B
SBT1A
SBT1B
SBT2A(SCL2A)
SBT2B(SCL2B)
SBT3A(SCL3A)
SBT3B(SCL3B)
SBT0A
SBT0B
SBT1A
SBT1B
SBT2A(SCL2A)
SBI3A
SBO3A(SDA3A)
MN101LR03D
SBI0B(RXD0B)
SBI1A(RXD1A)
MN101LR02D
SBI0A(RXD0A)
SBI0B(RXD0B)
SBI2A
SBI2A
SBI3A
SBI3A
SBO0B(TXD0B)
SBO1A(TXD1A)
SBO0A(TXD0A)
SBO0B(TXD0B)
SBO2A(SDA2A)
SBO2A(SDA2A)
SBO3A(SDA3A)
SBO3A(SDA3A)
SBT0A
SBT0B
SBT0B
SBT1A
SBT2A(SCL2A)
SBT2A(SCL2A)
SBT3A(SCL3A)
SBT3A(SCL3A)
SBT3A(SCL3A)
SBCS0A/SBCS0B
SBCS1A/SBCS1B
SBCS2A/SBCS2B
SBCS3A/SBCS3B
SBCS0A/SBCS0B
SBCS1A/SBCS1B
SBCS2A
SBCS3A
SBCS1A
SBCS2A
SBCS3A
TM0IOA/TM0IOB
TM1IOA/TM1IOB
TM2IOA/TM2IOB
TM3IOA/TM3IOB
TM4IOA/TM4IOB
TM5IOA/TM5IOB
TM7IOA/TM7IOB/
TM7IOC
TM8IOA/TM8IOB/
TM8IOC
TM9IOA/TM9IOB
TM9IOC
TM0IOA/TM0IOB
TM1IOA/TM1IOB
TM2IOA/TM2IOB
TM3IOA/TM3IOB
TM4IOA
TM5IOA/TM5IOB
TM7IOA/TM7IOB/
TM7IOC
TM8IOA/TM8IOB
TM8IOC
TM9IOA/TM9IOB
SBCS0B
SBCS0A/SBCS0B
SBCS2A
SBCS3A
TM0IOA
TM1IOA
TM2IOA
TM3IOA/TM3IOB
TM4IOA
TM5IOB
TM7IOA/TM7IOB
TM0IOA
TM1IOA
TM2IOA
TM3IOA
TM4IOA
TM8IOA
TM8IOA/TM8IOB
TM7IOA/TM7IOB
AN0/AN1/AN2/AN3/
AN2/AN3/
AN2/AN3/
AN4/AN5/AN6/AN7 AN4/AN5/AN6/AN7 AN4/AN5
AN4/AN5
IRQ0A/IRQ0B
IRQ1A/IRQ1B
IRQ2A/IRQ2B
IRQ3A/IRQ3B
IRQ4A/IRQ4B/
IRQ4C
IRQ5A/IRQ5B/
IRQ5C
IRQ6A/IRQ6B
IRQ0B
IRQ1B
IRQ2A/IRQ2B
IRQ3A/IRQ3B
IRQ4A/IRQ4B/
IRQ4C
IRQ5A/IRQ5B/
IRQ5C
IRQ6A/IRQ6B
Publication date: October 2014
IRQ0B
IRQ1B
IRQ2A/IRQ2B
IRQ3A/IRQ3B
IRQ4A/IRQ4B/
IRQ4C
IRQ5A/IRQ5B/
IRQ5C
IRQ6B
AN3/
Input/
Output
Input
Description
Serial data input pins
-Pull-up resistor can be added by setting
PnPLUP.
-Select the input mode by setting PnDIR.
-Select the serial data input by setting
SCnMD1.SCnSBIS. (n = 0,1,2,3)
Input/ Serial data I/O pins
Output -Pull-up resistor can be added by setting
PnPLUP.
-Select the output mode by setting PnDIR.
-Select the serial data output by setting
SCnMD1.SCnSBOS. (n = 0,1,2,3)
-Select the push-pull or Nch-open drain by
setting PnODC.
Input/ Serial clock I/O pins
Output -Pull-up resistor can be added by setting
PnPLUP.
-Select the input or output mode by setting
PnDIR.
-Select the serial clock I/O by setting
SCnMD1.SCnSBTS. (n = 0,1,2,3)
-Select the push-pull or Nch-open drain by
setting PnODC.
Input/ Serial chip select I/O pins
Output -Pull-up resistor can be added by setting
PnPLUP.
-Select the input or output mode by setting
PnDIR.
-Select the serial chip select I/O by setting
SCnMD3.SCnSBTS. (n = 0,1) or
SCnMD2.SCnSBCSEN(n = 2,3)
Input/ Timer I/O pins
Output -When capturing the external event signal,
select the input mode by setting PnDIR.
-To output the timer output signal, select
the output mode by setting PnDIR, and the
output port with TMIOENn/TMIOSELn (n =
0,1).
Input
Analog input pins for ADC
-Select the analog input pin with ANEN0.
Input
External interrupt input pins
-Select the external interrupt pin with
IRQIEN, IRQISEL0 and IRQISEL1.
IRQ4A
IRQ5A/
IRQ5C
17
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
Pin name
MN101LR05D
MN101LR04D
MN101LR03D
MN101LR02D
Input/
Output
Input
Description
KEY0A/KEY0B
KEY1A/KEY1B
KEY2A/KEY2B
KEY3A/KEY3B
KEY4A/KEY4B
KEY5A/KEY5B
KEY6A/KEY6B
KEY7A/KEY7B
KEY1B
KEY2A/KEY2B
KEY3A/KEY3B
KEY4A/KEY4B
KEY5A/KEY5B
KEY6A/KEY6B
KEY7A/KEY7B
KEY1B
KEY2A/KEY2B
KEY3A/KEY3B
KEY4A
KEY5A
KEY6A
COM0-7
COM0-3
COM0-3
Output LCD common output pins
-Select the common output pin with
LCCTRn.
SEG0-42
SEG0-30
SEG0-20
Output LCD segment output pins
-Select the segment output pin with
LCCTRn.
BUZA/BUZB
BUZA/BUZB
BUZA
Output Buzzer output pin
-Select the buzzer output pin with BUZCNT.
NBUZA/NBUZB
NBUZA/NBUZB
NBUZA
NBUZA
Output Inverted Buzzer output pin
-Select the inverted buzzer output pin with
BUZCNT.
CLKOUTA/
CLKOUTB
CLKOUTA/
CLKOUTB
CLKOUTA/
CLKOUTB
CLKOUTA/
CLKOUTB
Output Clock output pins
-Select the clkout pin with CLKOUT.
OCD_CLK
OCD_DATA
OCD_CLK
OCD_DATA
OCD_CLK
OCD_DATA
OCD_CLK
OCD_DATA
Input/ On-board debugger I/O pins
Output These pins are used for on-board debugging.
Publication date: October 2014
KEY1B
KEY2B
KEY3A/KEY3B
KEY4A/KEY4B
KEY5A/KEY5B
KEY6A/KEY6B
KEY7B
Key interrupt input pins
-Select the key interrupt pin with KEYIEN
and KEYSEL.
18
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5 Electrical Characteristics
1.5.1
Absolute Maximum Ratings
VSS = 0 V
A. Absolute Maximum Ratings *2 *3
Parameter
Symbol
Rating
Unit
VDD30
-0.3 to +4.6
V
A1
Supply voltage
A2
Input pin voltage
VI
-0.3 to VDD30 + 0.3 (up to 4.6)
A3
Output pin voltage
VO
-0.3 to VDD30 + 0.3 (up to 4.6)
A4 Input/Output pin voltage
VIO1
-0.3 to VDD30 + 0.3 (up to 4.6)
Except
P1/8 *4
IOL1 (peak)
30
A6 Peak output current P1/8 *5
IOL2 (peak)
10
A7
All pins
IOH (peak)
-10
A8
Except
P1/8 *4
IOL1 (avg)
20
P1/8 *5
IOL2 (avg)
5
All pins
IOH (avg)
-5
ITOL
60
ITOH
-60
PT
230 (Ta = +85 C)
Topr
-40 to +85
Tstg
-55 to +125
A5
Average output
A9 current *1
A10
A11 Total output current for all pins
A12 *1
A13 Power dissipation
A14
Operating ambient
temperature
A15 Storage temperature
V
mA
mW
C
*1
The values are applied to any period of 100 ms.
*2
To stabilize the internal power supply voltage, connect bypass capacitors as follows to at least one or more points close to the
LSI: Capacitors of 1F or more between VDD30 and VSS, Capacitors of 0.1 F and 1F or more between VOUT18 and VSS.
*3
The absolute maximum ratings are the limit values beyond which the IC may be damaged.
Operation is not guaranteed under these conditions.
*4
The value is applied when selecting the large current output by setting PnNLC register. Except P1 corresponds in MN101LR02D.
*5
P1 corresponds in MN101LR02D.
Publication date: October 2014
19
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5.2
Operating Condition
VSS = 0 V
Ta = -40 C to +85 C
B. Operating Condition
Limits
Parameter
Symbol
Condition
Unit
MIN
TYP
MAX
Supply voltage *6
B1
B2
Supply voltage
B3
B4
RAM retention
supply voltage
VDD1
fSYSCLK  10.0 MHz
1.8
--
3.6
VDD2
fSYSCLK 1.0 MHz *7
1.3
--
3.6
VDD3
fSYSCLK  40 kHz *8 *10
1.1
--
3.6
VDD4
At STOP mode *10
1.1
--
3.6
tc1
VDD30 = 1.8 V to 3.6 V
0.1
--
--
tc2
VDD30 = 1.3 V to 3.6 V
1.0
--
--
tc3
VDD30 = 1.1 V to 3.6 V *10
25.0
--
--
V
Operating speed *9
B5
B6
Instruction execution time
1/fSYSCLK
B7
*6
fSYSCLK: Frequency for the system clock
*7
When fSYSCLK is generated by using the internal high-speed oscillation.
*8
When fSYSCLK is generated by using the external low-speed oscillation or the internal low-speed oscillation.
*9
tc1,2: When fSYSCLK is generated by using the internal high-speed oscillation or the external high-speed oscillation.
(However, for tc2, only by using the internal high-speed oscillation)
tc3: When fSYSCLK is generated by using the internal low-speed oscillation.
s
*10 When using auto reset function, the lowest voltage is the auto reset detection voltage.
VDD30 = VRSTL to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85C
Parameter
Symbol
Condition
External high-speed oscillation Figure:1.5.1 (MN101LR02D is not applicable.)
FHOSCCLK VDD30 = 1.8 V to 3.6 V
B8 Frequency
MIN
Limits
TYP
MAX
Unit
1.0
--
10.0
MHz
--
32.768
--
kHz
--
10
--
MHz
--
8
--
MHz
--
1
--
MHz
External low-speed oscillation Figure:1.5.2
B9
Frequency
FSOSCCLK
VDD30 = VRSTL to 3.6 V
Internal high-speed RC oscillation *11
B10
FHRCCLK10
B11 Frequency
FHRCCLK8
B12
FHRCCLK1
Publication date: October 2014
VDD30 = 1.8 V to 3.6 V
FCNT = "00"
VDD30 = 1.8 V to 3.6 V
FCNT = "01"
VDD30 = 1.3 V to 3.6 V
FCNT = "10"
20
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
VDD30 = VRSTL to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85C
Parameter
B13
Symbol
Temperature/Voltage
dependence
EF2
B14
B15
EF1
Temperature/Voltage
dependence
EF5
Condition
MIN
fHRCCLK = 8/10 MHz
Ta = 0 C to +50 C
fHRCCLK = 8/10 MHz
Ta = -40 C to +85 C
fHRCCLK = 1 MHz
Ta = -40 C to +85 C
Temperature/Voltage
dependence
EF6
MAX
Unit
-1.5
--
1.5
-3.0
--
3.0
-10.0
--
10.0
%
--
40
--
kHz
-20.0
--
20.0
%
%
Internal low-speed RC oscillation
FSRCCLK VDD30 = VRSTL to 3.6 V
B16 Frequency
B17
Limits
TYP
Ta = -40 C to +85 C
*11 Output frequency of the internal high-speed RC oscillation can be selected by setting the FCNT bit of HCLKCNT register.
OSC1
Rf10
XI
fHOSCCLK
Rf20
fSOSCCLK
OSC2
XO
LSI
C12
C11
Feedback resistor is embedded.
Figure:1.5.1 High-speed oscillation
LSI
C22
C21
Feedback resistor is embedded.
Figure:1.5.2 Low-speed oscillation
Connect the external capacitance to match the oscillator used.
When using the crystal or ceramic oscillator, consult your oscillator manufacturer to decide
the external capacitance value since the oscillation frequency changes depending on the
capacitor value.
..
..
The external low-speed oscillation of other than 32.768 kHz can't be used.
..
Publication date: October 2014
21
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
VDD30 = 1.8 V to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85 C
Parameter
Symbol
Condition
Limits
MIN
TYP
MAX
1.0
--
10.0
45
--
--
45
--
--
--
--
5.0
--
--
5.0
Unit
External clock input 1 OSC1 (OSC2 is open.) (MN101LR02D is not applicable.)
B18 Clock frequency
fHOSCCLK
twh1
B19 High period time *12
B20 Low period time *12
twl1
B21 Rise time
twr1
B22 Fall time
twf1
Figure:1.5.3
Figure:1.5.3
MHz
ns
*12 Set the clock duty ratio to the value from 45 % to 55 %.
0.9VDD30
0.1VDD30
twh1
twl1
twr1
twf1
twc1
Figure:1.5.3 OSC1 timing diagram
Publication date: October 2014
22
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5.3
DC Characteristics
VSS = 0 V
Ta = -40 C to +85C
C. DC Characteristics
Parameter
Symbol
Condition
MIN
Limits
TYP
MAX
Unit
Supply current *13
C1
*14
IDD1
fHOSCCLK = 10 MHz
VDD30 = 3.0 V, VDD18 = 1.8 V
[fSYSCLK = fHOSCCLK]
--
2.1
3.1
C2
IDD2
fHRCCLK = 10 MHz
VDD30 = 3.0 V, VDD18 = 1.8 V
[fSYSCLK = fHRCCLK]
--
2.1
3.0
C3
IDD3
fHRCCLK = 8 MHz
VDD30 = 3.0 V, VDD18 = 1.8 V
[fSYSCLK = fHRCCLK]
--
1.72
2.5
IDD4
fHRCCLK = 8 MHz
VDD30 = 3.0 V, VDD18 = 1.8 V
[fSYSCLK = fHRCCLK/2]
--
0.94
1.5
C5
*14
IDD5
fHOSCCLK = 4 MHz
VDD30 = 3.0 V, VDD18 = 1.8 V
[fSYSCLK = fHOSCCLK]
--
0.84
1.3
C6
IDD6
fHRCCLK = 1 MHz
VDD30 = 3.0 V, VDD18 = 1.3 V
[fSYSCLK = fHRCCLK]
--
0.22
0.36
C7
IDD7
fSOSCCLK = 32.768 kHz
VDD30 = 3.0 V, VDD18 = 1.1 V
[fSYSCLK = fSOSCCLK]
--
5.6
9.5
IDD8
fSRCCLK = 40 kHz
VDD30 = 3.0 V, VDD18 = 1.1 V
[fSYSCLK = fSRCCLK]
--
C4
Operating supply
current
C8
mA
A
6.7
11.6
*14 MN101LR02D is not applicable.
Publication date: October 2014
23
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
VSS = 0 V
Ta = -40 C to +85C
C. DC Characteristics
Parameter
Symbol
IDD9
C9
IDD10
C10
Supply current in
HALT
C11
IDD11
C12
IDD12
C13
IDD13
Supply current in
STOP
C14
IDD14
Condition
HALT0 mode
fHRCCLK = 8 MHz
VDD30 = 3.0 V, VDD18 = 1.1 V
HALT2 mode
fSOSCCLK = 32.768 kHz
VDD30 = 3.0 V, VDD18 = 1.1 V
Ta = 25 C
(HOSCCLK/HRCCLK/SRCCLK are stopped)
HALT3 mode
fSOSCCLK = 32.768 kHz
VDD30 = 3.0 V, VDD18 = 1.1 V
Ta = 25 C, HALTMOD = 1
(HOSCCLK/HRCCLK/SRCCLK are stopped)
HALT3 mode
fSOSCCLK = 32.768 kHz
VDD30 = 3.0 V, VDD18 = 1.1 V
Ta = 85 C, HALTMOD = 1
(HOSCCLK/HRCCLK/SRCCLK are stopped)
VDD30 = 3.0 V, VDD18 = 1.1 V
Ta = 25 C
(HOSCCLK/HRCCLK/
SOSCCLK/SRCCLK are stopped)
VDD30 = 3.0 V, VDD18 = 1.1 V
Ta = 85 C
(HOSCCLK/HRCCLK/
SOSCCLK/SRCCLK are stopped)
MIN
Limits
TYP
MAX
--
0.24
0.33
--
0.2
0.4
--
0.5
0.7
--
--
2.9
--
0.06
0.24
--
--
2.6
Unit
mA
A
*13 The supply current is measured with Ta = 25 C, no-load, and all the analog part in the power-down state. (The pull-up/down resistors are not connected.) Each supply current is measured with the following conditions.
IDD1, 5 (Operating supply current): After setting all input and output pins to the input mode, VDD18 (the Logic supply voltage) to 1.8 V,
the oscillation mode to NORMAL (the external oscillation), hold the input pins to VDD30 level and input the 10/4 MHz square wave,
which has the amplitude from VDD30 to VSS, from OSC1 pin.
IDD2, 3, 4 (Operating supply current): After setting all input and output pins to the input mode, VDD18 (the Logic supply voltage) to 1.8
V, the oscillation mode to NORMAL (the internal high-oscillation: 10/8 MHz), hold the input pins to VDD30 level.
IDD6 (Operating supply current): After setting all input and output pins to the input mode, VDD18 (the Logic supply voltage) to 1.3 V,
the oscillation mode to NORMAL (the internal high-oscillation: 1 MHz), hold the input pins to VDD30 level.
IDD7 (Operating supply current): After setting all input and output pins to the input mode, VDD18 (the Logic supply voltage) to 1.1 V,
the oscillation mode to SLOW (the external oscillation), hold the input pins to VDD30 level and input the 32.768 kHz square wave,
which has the amplitude from VDD11 to VSS, from XI pin.
IDD8 (Operating supply current): After setting all input and output pins to the input mode, VDD18 (the Logic supply voltage) to 1.1 V,
the oscillation mode to SLOW (the internal low-oscillation: 40 kHz), hold the input pins to VDD30 level.
IDD9 (Supply current in HALT): After setting all input and output pins to the input mode, the oscillation mode to HALT0 (the internal
high-oscillation), hold the input pins to VDD30 level.
IDD10 (Supply current in HALT): After setting all input and output pins to the input mode, the oscillation mode to HALT2 (the external
low-oscillation), hold the input pins to VDD30 level and input the 32.768 kHz square wave, which has the amplitude from VDD11 to
VSS, from XI pin.
IDD11,12 (Supply current in HALT): After setting all input and output pins to the input mode, the oscillation mode to HALT3 (the external low-oscillation), hold the input pins to VDD30 level and input the 32.768 kHz square wave, which has the amplitude from VDD11 to
VSS, from XI pin.
IDD13,14 (Supply current in STOP): After setting VDD18 (the Logic supply voltage) to 1.1 V and the oscillation mode to STOP, hold the
input pins to VDD30 level and make OSC1 and XI pins open.
Publication date: October 2014
24
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
VDD30 = VRSTL to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85 C
Parameter
Symbol
Condition
Limits
MIN
TYP
MAX
Unit
Input pin 1 NATRON (Schmitt input)
C15 High-level input voltage
VIH1
0.8VDD30
--
VDD30
C16 Low-level input voltage
VIL1
0
--
0.2VDD30
C17 Input leakage current
ILK1
--
--
±1
VI = 0 V to VDD30
V
A
Input pin 2 DMOD (Schmitt input)
C18 High-level input voltage
VIH2
0.8VDD30
--
VDD30
C19 Low-level input voltage
VIL2
0
--
0.2VDD30
C20 Pull-down resistance
IRL2
30
100
300
VDD30 = 3.0 V, VI = VDD30
V
k
Input/Output pin 3 (Schmitt input)
MN101LR05D: P10 to P17, P80 to P85
MN101LR04D: P12 to P17, P80 to P85
MN101LR03D: P12 to P15, P80 to P85
MN101LR02D: P13 to P15
C21 High-level input voltage
VIH3
0.8VDD30
--
VDD30
C22 Low-level input voltage
VIL3
0
--
0.2VDD30
C23 Input leakage current
ILK3
VI = 0 V to VDD30
--
--
±1
A
C24 Pull-down resistance
IRH3
VDD30 = 3.0 V, VI = VSS
with pull-up resistor
30
100
300
k
C25
High-level output
voltage
VOH3
VDD30 = 3.0 V, IOH = -2.0 mA
2.4
--
--
C26
Low-level output
voltage
VOL3
VDD30 = 3.0 V, IOL = 2.0 mA
--
--
0.4
V
V
Input/Output pin 4 (Schmitt input)
MN101LR05D: P00 to P07, P20 to P26,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77
MN101LR04D: P02 to P07, P20, P21, P26, P30 to P37, P40 to P47, P50, P55 to P57, P60 to P67, P70 to P73
MN101LR03D: P04, P05,
P26, P30 to P37, P40 to P44,
P55 to P57, P60 to P63, P70 to P73
MN101LR02D: P04 to P06,
P34 to P37, P40 to P44,
P55 to P57, P64 to P67
C27 High-level input voltage
VIH4
0.8VDD30
--
VDD30
C28 Low-level input voltage
VIL4
0
--
0.2VDD30
C29 Input leakage current
ILK4
VI = 0 V to VDD30
--
--
±1
A
C30 Pull-down resistance
IRH4
VDD30 = 3.0 V, VI = VSS
with pull-up resistor
30
100
300
k
C31
High-level output
voltage
VOH4
VDD30 = 3.0 V, IOH = -2.0 mA
2.4
--
--
C32
Low-level output
voltage 1
VOL41
VDD30 = 3.0 V, IOL = 2.0 mA
at Large output current OFF
--
--
0.4
C33
Low-level output
voltage 2
VOL42
VDD30 = 3.0 V, IOL = 8.0 mA
at Large output current ON
--
--
0.4
Publication date: October 2014
V
V
25
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
VDD30 = VRSTL to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85 C
Parameter
Symbol
Condition
Limits
MIN
TYP
MAX
Unit
Input pin 5 P27(NRST) (Schmitt input)
C34 High-level input voltage
VIH5
0.8VDD30
--
VDD30
C35 Low-level input voltage
VIL5
0
--
0.15VDD30
C36 Pull-down resistance
IRH5
30
100
300
k
--
--
0.6
V
--
--
0.6
V
VDD30 = 3.0 V, VI = VSS
with pull-up resistor
V
Display output pin 1
MN101LR05D: COM0 to COM7 (at VLC1, VSS output)
MN101LR04D: COM0 to COM3 (at VLC1, VSS output)
MN101LR03D: COM0 to COM3 (at VLC1, VSS output)
MN101LR02D: C37
Potential difference of
output waveform
VOCM
VDD30 = VLC1 = 3.0 V
ICOM = 10 A
Display output pin 2
MN101LR05D: SEG0 to SEG42 (at VLC1, VSS output)
MN101LR04D: SEG0 to SEG30 (at VLC1, VSS output)
MN101LR03D: SEG0 to SEG20 (at VLC1, VSS output)
MN101LR02D: C38
Voltage difference of
output waveform
VOSG
VDD30 = VLC1 = 3.0 V
ISEG = 2 A
LCD boost output pin 1
MN101LR05D: VLC1, VLC2, VLC3 (VLC3: Triple output compared to the reference voltage output)
MN101LR04D: VLC1, VLC2, VLC3 (VLC3: Triple output compared to the reference voltage output)
MN101LR03D: VLC1, VLC2, VLC3 (VLC3: Triple output compared to the reference voltage output)
MN101LR02D: VLC1
C39
C40
Output voltage
C41
Publication date: October 2014
VLC2
VLC3
VDD30=VRSTL to 3.0 V
VLC3 = 1.0 V, Ta = 25 C
LCD display OFF, SEG/COM
with no load,
LCD boost clock = 125 kHz
2.7
3.0
3.3
1.8
2.0
2.2
0.9
1.0
1.1
V
26
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5.4
A/D Converter Characteristics
VDD30 = 3.0 V VSS = 0 V
Ta = -40 C to +85 C
D. A/D Converter characteristics *14
Limits
Parameter
Symbol
Condition
Unit
MIN
TYP
MAX
D1
Resolution
RSL
--
--
12
D2
Nonlinearity error
INL
--
--
±4
D3
Differential non-linearity
error
DNL
--
--
±3
D4
Zero voltage transition
EZS
--
10
30
D5
full-scale voltage
transition
EFS
2970
2990
--
D6
AD conversion time
tCV
fSYSCLK = 8 MHz, TAD = 750 ns
15.38
--
--
D7
Sampling time
tS
TAD = 750 ns
1.5
--
--
D8
Reference voltage
1.8
--
VDD30
D9
Analog input voltage
VAIN
VSS
--
VREFP
D10
Analog input leakage
current
IAINL
--
--
±1
*14
Bits
LSB
VDD30 = 3.0 V, VSS = 0 V
VREFP = 3.0 V
TAD = 750 ns
mV
VREFP
VREFP  VDD30
At channel off
VADIN = 0 V to VDD30
s
V
A
TAD denotes the clock cycle for A/D conversion.
The value from D2 to D5 are guaranteed under the condition of VDD30 = VREFP = 3.0 V and VSS = 0 V.
Publication date: October 2014
27
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5.5
Reset/Power supply Detection Characteristics
VDD30 = VRSTL to 3.6 V, VSS = 0 V
VRSTL = 1.1 V at auto reset function
Ta = -40 C to +85C
E. Reset/Power supply Detection
Characteristics
Parameter
Symbol
Condition
Limits
MIN
TYP
MAX
VRSTL
--
3.6
Unit
Reset
E1
E2
E3
E4
Operating supply
current
Auto reset voltage
detection level
Slope of voltage
startup
VDD3
With auto reset
VRSTH
VDD30 = "Low" --> "High"
1.10
1.23
1.35
VRSTL
VDD30 = "High" --> "Low"
1.10
1.18
1.30
--
--
1.0
1.00
1.10
1.20
1.05
1.15
1.25
1.10
1.20
1.30
1.15
1.25
1.35
1.20
1.30
1.40
1.25
1.35
1.45
1.30
1.40
1.50
1.40
1.50
1.60
1.50
1.60
1.70
1.60
1.70
1.80
1.70
1.80
1.90
1.80
1.90
2.00
1.90
2.00
2.10
2.00
2.10
2.20
2.10
2.20
2.30
2.20
2.30
2.40
2.30
2.40
2.50
2.40
2.50
2.60
2.50
2.60
2.70
2.60
2.70
2.80
2.70
2.80
2.90
2.80
2.90
3.00
SLVDD30
V
V/ms
Power supply Detection
E5
Detection voltage
Publication date: October 2014
VLVI
V
28
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.5.6
ReRAM Program Condition
VDD30 = 1.8 V to 3.6 V, VSS = 0 V
Ta = -40 C to +85 C
F. ReRAM Program Condition
Limits
Parameter
F1
Supply voltage
for programming
F2
Guaranteed number of
rewriting *15
Condition
Symbol
VDDEW
NUMw1
Program area
NUMw2
Data area
TYP
MAX
1.8
--
3.6
1000
--
--
100000
--
--
10
--
--
V
time
THOLD
F3
Data hold time
*15
The number of rewriting is counted by a byte unit.
Publication date: October 2014
Unit
MIN
year
29
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
1.6 Package Dimension
 Package code: TQFP080-P-1212Unit: mm
Figure:1.6.1 80-pin TQFP Package Dimension
Publication date: October 2014
30
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
 Package code: TQFP064-P-1010Unit: mm
Figure:1.6.2 64-pin TQFP Package Dimension
Publication date: October 2014
31
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
 Package code: TQFP048-P-0707Unit: mm
Figure:1.6.3 48-pin TQFP Package Dimension
Publication date: October 2014
32
MN101LR05D/04D/03D/02D
8-bit Single-chip Microcontroller
PubNo. 21705-019E
 Package code: HQFN032-A-0505Unit: mm
Figure:1.6.4 32-pin HQFN Package Dimension
This package dimension is subject to change. Before using this product, obtain product specifications from our sales offices.
..
Publication date: October 2014
33
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Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
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