Single Chip Wireless
Power Transmitter IC for TX-A1
Product Datasheet
IDTP9030
Features
Description
 Single-Chip 5W Solution for Wireless Power
Consortium (WPC)-compliant power transmitter
design A1
 Conforms to WPC specification version 1.1
specifications
 19±1V Operating Input Voltage
 Integrated Half-Bridge Inverter
 Closed-Loop Power Transfer Control between Base
Station and Mobile Device
 Demodulates and Decodes WPC-Compliant
Message Packets
 5V Regulated DC/DC Converter
 Integrated RESET Function
 Proprietary Back –Channel Communication
 I2C Interface
 Open-Drain LED Indicator Outputs
 Over-Temperature/Voltage/Current Protection
 Security and encryption up to 64 bits
 Foreign Object Detection (FOD) for safety
The IDTP9030 is a highly-integrated single-chip WPC-compliant
wireless power transmitter IC for power transmitter design A1. The
device operates with a 19V (±1V) adapter, and supplies an integrated
half-bridge inverter for DC/AC conversion. It controls the transferred
power by modulating the switching frequency of the half-bridge inverter
from 110kHz to 205kHz at a fixed 50% duty cycle specified by the WPC
specification for an “A1” transmitter. It contains logic circuits required to
demodulate and decode WPC-compliant message packets sent by the
mobile device to adjust the transferred power.
Applications
The device includes over-temperature/voltage/current protection and a
Foreign Object Detection (FOD) method to protect the base station and
mobile device from overheating in the presence of a metallic foreign
object. It manages fault conditions associated with power transfer and
controls status LEDs to indicate operating modes.
The IDTP9030 is an intelligent device that periodically pings the area
surrounding the base station to detect a mobile device for charging
while minimizing idle power. Once the mobile device is detected and
authenticated, the IDTP9030 continuously monitors all communications
from the mobile device, and adjusts the transmitted power accordingly
by varying the switching frequency of the half-bridge inverter.
The IDTP9030 features a proprietary back-channel communication
mode which enables the device to communicate to IDT’s wireless
power receiver solutions (e.g. IDTP9020). This feature enables
additional layers of capabilities relative to standard WPC requirements.
This device also features optional security and encryptions to securely
authenticate the receiver before transferring power. This feature is
available when an IDTP9020 is used for the receiver.
 WPC-Compliant Wireless Charging Base Stations
Typical Application Circuit
Wireless
Interface
Transmitter(s)
Mobile Device
Receiver
Control
Input Power
Control System
Control System
Comm
Cont
Sensing
Control
Comm
DeMod
Comm
Load
Reflection
Power Generation
IN
PWR
Cont
Sensing
Control
Mod
Power Pick-Up
Induction
Output Load
Base Station
Out
PWR
Package: 6x6-48 TQFN (See page 27)
Ordering Information (See page 28)
Revision 1.0.2
1
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
ADAPTOR
IDTP9030
IN
SW
WPC TX-A1
88uF
(4x22uF)
100nF
1
VO
PGND
(3x33nF)
250V
1.5K
GPIO_1
22nF
VOSNS
4.7nF
REG_IN
1
20K
47K
10K
1.2nF
1uF
1
20K
10K
ISNS
2.2nF
BUCK5VT_IN
10uF
1
BUCK5VT_SNS
1
1uF
LDO2P5V
LDO2P5V
1uF
1.8nF
LDO5V
LDO5V
BUCK5VT
LDO2P5V_IN
`
3.3nF
HPF
1uF/25V
BUCK5VT
4.7uH
LX
47nF
BST
SCL
SDA
10uF
EN
EN
RESET
RESET
1uF
GPIO_4
Buzzer
47K
SCL
SDA
3
GPIO_2
GPIO_3
5.1K
47K
2
RTOP
RNTC
5.1K
GND
EP
REFGND
GPIO_0
AGND
DGND
LEDA
LEDB
Figure 1. IDTP9030 Simplified Application Schematic
Note 1: NPO/C0G-type ceramic capacitor.
Note 2: For PCB layout, use single-point reference (“star” ground), refer to design schematic in Figure 15).
Note 3: In circuit at GPIO_2, RTOP is required to linearize the temperature range of the thermistor, RNTC. Please contact IDT for a spreadsheet calculator to guide thermistor
selection.
Revision 1.0.2
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© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
ABSOLUTE MAXIMUM RATINGS
These absolute maximum ratings are stress ratings only. Stresses greater than those listed below (Table 1 and Table 2) may
cause permanent damage to the device. Functional operation of the IDTP9030 at absolute maximum ratings is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect long-term reliability.
Table 1. Absolute Maximum Ratings Summary. All voltages are referred to ground, unless otherwise noted.
PINS
MAXIMUM
RATING
UNITS
BUCK5VT_IN, IN, REG_IN. THESE PINS MUST BE CONNECTED TOGETHER AT ALL TIMES.
-0.3 to 24
V
-0.3 to 24
V
-0.3 to 29
V
LDO2P5V, XTAL/CLK_IN, XTAL/CLK_OUT
-0.3 to 2.75
V
AGND, DGND, PGND, REFGND
-0.3 to +0.3
V
BUCK5VT_SNS, BUCK5VT, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, HPF,
ISNS, LDO2P5V_IN, LDO5V, RESET, SCL, SDA, VOSNS
-0.3 to +5.5
V
, LX, SW5
BST5
Table 2. Package Thermal Information
MAXIMUM
RATING
UNITS
Thermal Resistance Junction to Ambient (NTG48 - TQFN)
30.8
C/W
JC
Thermal Resistance Junction to Case (NTG48 - TQFN)
14.6
C/W
JB
Thermal Resistance Junction to Board (NTG48 - TQFN)
0.75
C/W
TJ
Junction Temperature
-40 to +150
C
TA
Ambient Operating Temperature
-40 to +85
C
TSTG
Storage Temperature
-55 to +150
C
TLEAD
Lead Temperature (soldering, 10s)
+300
C
SYMBOL
DESCRIPTION
JA
Note 1:The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 125°C. Exceeding the maximum allowable power dissipation will
result in excessive die temperature, and the device will enter thermal shutdown.
Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions.
Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables.
Note 4: For the NTG48 package, connecting the 4.1 mm X 4.1 mm EP to internal/external ground planes with a 5x5 matrix of PCB plated-through-hole
(PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance.
Note 5: If the voltage at VIN is less than 24V, limit the voltages on
, LX, SW to V(VIN)+0.3V and the voltage on BST to V(VIN)+5V.
Revision 1.0.2
3
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Table 3. ESD Information
TEST
MODEL
MAXIMUM
RATINGS
PINS
All, except IN
±1000
Only IN (37, 38 and 39)
±800
All
±500
HBM
CDM
Revision 1.0.2
UNITS
V
4
V
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
BLOCK DIAGRAM
Figure 2. IDTP9030 Internal Functional Block Diagram
Revision 1.0.2
5
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.
Table 4. Device Characteristics
SYMBOL
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNITS
20
V
15
mA
750
µA
Half-Bridge Inverter
Input Supply
Operating Voltage
Range1
VIN
IIN_A
Standby Input
Current
IIN_S
Sleep Mode Input
Current
IIN2
FSW_LOW
FSW_HIGH
RDS(ON)_HS
RDS(ON)_LS
Switching Frequency
at SW
18
After power-up sequence complete.
No coil, no load at SW, LDO5V,
LDO2P5V, LX. (No wireless power
transfer to battery.)
8
= 5V to VIN
WPC Operating Range, in
compliance with WPC requirements
110
205
Between IN and SW
Between SW and PGND
175
130
kHz
kHz
mΩ
mΩ
UVLO and Inverter OCP
VIN_UVLO
Under-Voltage
Protection Trip Point
IIN_OCP
Over-Current
Protection Trip Point
VIN rising
VIN falling
Hysteresis
VIN = 20V, cycle-by-cycle
protection.
10.3
9.0
625
V
mV
1.8
2.4
A
18
20
V
5.5
80
V
mA
3
MHz
5
2.5
V
V
mA
DC-DC Converter (For Biasing Internal Circuitry Only)3
VBUCK5VT_IN
VBUCK5VT
IOUT
FSW
Input Voltage
Range1
Output Voltage
External Load4
Switching Frequency
at LX
External ILoad = 25mA
4.5
Low Drop Out Regulators (For Biasing Internal Circuitry Only)3
LDO2P5V3
VLDO2P5V_IN
VLDO2P5V
IOUT
Input Voltage Range
Output Voltage
External Load
Supplied from BUCK5VT
ILoad = 2mA
Input Voltage Range
Output Voltage
See Note 1.
ILoad = 2mA
5
LDO5V3
VREG_IN
VLDO5V
Revision 1.0.2
18
20
5
6
V
V
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.
Table 5. Device Characteristics, Continued
SYMBOL
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNITS
Thermal Shutdown
TSD
Thermal Shutdown
Temperature Rising Threshold
Temperature Falling Threshold
140
110
C
900
550
mV
mV
VEN
¯¯ = 5V
7.5
μA
VEN
¯¯ = VIN = 20V
56
μA
VIH
VIL
IEN
¯¯
EN
¯¯ input current
General Purpose Inputs / Outputs (GPIO)
VIH
VIL
ILKG
VOH
VOL
IOH
IOL
Input Threshold High
Input Threshold Low
Input Leakage
Output Logic High
Output Logic Low
Output Current High
Output Current Low
3.5
8
1.5
+1
V
V
µA
1.5
+1
-1
4
IOH=-8mA
IOL=8mA
V
V
µA
V
V
mA
mA
0.5
-8
RESET
VIH
VIL
ILKG
SCL, SDA
Input Threshold High
Input Threshold Low
Input Leakage
(I2C
Clock Frequency
fSCL
Clock Frequency
fSCL
Clock Frequency
Hold Time
(Repeated) for
START Condition
tHD;DAT
Data Hold Time
tLOW
tHIGH
Clock Low Period
Clock High Period
Set-up Time for
Repeated START
Condition
tSU;STA
Revision 1.0.2
-1
Interface)
fSCL
tHD;STA
3.5
EEPROM loading, Step 1,
IDTP9030 as Master
EEPROM loading, Step 2,
IDTP9030 as Master
IDTP9030 as Slave
0
CBUS-compatible masters
I2C-bus devices
7
100
kHz
300
kHz
400
kHz
0.6
μs
5
10
1.3
0.6
μs
ns
μs
μs
100
ns
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
ELECTRICAL CHARACTERISTICS
= RESET = 0V, IN = REG_IN = BUCK5VT_IN = 19V. TA = -40 to +85C, unless otherwise noted. Typical values are at
25C, unless otherwise noted.
Table 6. Device Characteristics, Continued
SYMBOL
DESCRIPTION
Bus Free Time
TBUF
Between STOP and
START Condition
Capacitive Load for
CB
Each Bus Line
SCL, SDA Input
CBIN
Capacitance5
VIL
Input Threshold Low
VIH
Input Threshold High
ILKG
Leakage Current
Output Logic Low
VOL
(SDA)
IOH
Output Current High
IOL
Output Current Low
Analog-to-Digital Converter
ADC Conversion
N
Resolution
fSAMPLE
Sampling Rate
Number of Channels
Channel
at ADC MUX input
ADC Clock
ADCCLK
Frequency
Full-Scale Input
VIN_FS
Voltage
CONDITIONS
MIN
TYP
MAX
1.3
μs
100
5
When powered by device 5V
UNITS
pF
pF
1.5
V
1.0
µA
0.5
V
2
mA
mA
3.5
V
-1.0
IPD= 2mA (Note 1)
-2
12
Bit
62.5
KSPS
8
1
MHz
2.5
V
40
2.5
MHz
V
Microcontroller
FCLOCK
VIN
Clock Frequency
Input Voltage
Note 1: BUCK5VT_IN, IN, REG_IN. These pins must be connected together at all times.
Note 2: This current is the sum of the input currents for IN, REG_IN and BUCK5VT_IN.
Note 3: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM,
thermistor, LED, buzzer and pull up resistor loads (up to an absolute maximum of 25mA), as recommended in Figure 15 WPC “Qi” Compliance Schematic
and Table 6 WPC “Qi” Compliance Bill of Materials.
Note 4: Any external load at the output of the DC/DC converter must not inject noise onto the output node, and care must be taken with parasitic
inductance and capacitance.
Note 5: Guaranteed by design.
Revision 1.0.2
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© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
PIN CONFIGURATION
NC
NC
NC
NC
NC
GND
NC
HPF
ISNS
IN
IN
IN
TQFN-48L
48
47
46
45
44
43
42
41
40
39
38
37
GPIO_6
1
36
NC
GPIO_5
2
35
SW
GPIO_4
3
34
SW
GPIO_3
4
33
SW
GPIO_2
5
32
PGND
GPIO_1
6
31
NC
GPIO_0
7
30
PGND
SCL
8
29
PGND
SDA
9
28
PGND
XTAL/CLK_IN
10
27
VOSNS
XTAL/CLK_OUT
11
26
LX
RESET
12
25
BUCK5VT_SNS
14
15
16
17
18
19
20
21
22
23
24
REG_IN
LDO5V
LDO2P5V
LDO2P5V_IN
BUCK5VT
BST
AGND
DGND
NC
BUCK5VT_IN
EN
13
REFGND
EP (Center Exposed Pad)
Figure 3. IDTP9030 Pin Configuration (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm, 0.4mm pitch)
Revision 1.0.2
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IDTP9030
Product Datasheet
PIN DESCRIPTION
Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()
PIN
NAME
TYPE
DESCRIPTION
1
GPIO_6
I/O
General purpose input/output 6
2
GPIO_5
I/O
General purpose input/output 5
3
GPIO_4
I/O
General purpose input/output 4
4
GPIO_3
I/O
General purpose input/output 3
5
GPIO_2
I/O
General purpose input/output 2
6
GPIO_1
I/O
General purpose input/output 1
7
GPIO_0
I/O
General purpose input/output 0
8
SCL
I/O
I2C clock
9
SDA
I/O
I2C data
10
XTAL/CLK_IN
I
Crystal or clock input. If not used, must be connected to GND.
11
XTAL/CLK_OUT
O
Crystal or clock output. If not used, must be left unconnected.
12
RESET
I
Active-high chip reset pin. A 1µF ceramic capacitor must be connected between this pin
and LDO5V, and a 100kΩ resistor to G D.
I
Active-low enable pin. Device is suspended and placed in low current (sleep) mode when
pulled high. Tie to GND for stand-alone operation.
13
14
REFGND
-
Signal ground connection. Must be connected to AGND.
15
REG_IN1
I
A 1µF ceramic capacitor must be connected between this pin and GND. This pin must be
connected to pins 37, 38, and 39.
16
LDO5V2
O
A 1µF ceramic capacitor must be connected between this pin and GND.
17
LDO2P5V2
O
2.5V LDO output. A 1µF ceramic capacitor must be connected between this pin and GND.
18
LDO2P5V_IN
I
2.5V LDO input. The LDO2P5V_IN input must be connected to BUCK5VT. A 1µF ceramic
capacitor must be connected between this pin and GND.
19
BUCK5VT2
I
Power and digital supply input to internal circuitry.
Revision 1.0.2
10
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()
PIN
NAME
TYPE
DESCRIPTION
20
BST
I
Bootstrap pin for BUCK converter top switch gate drive supply.
21
AGND
-
Analog ground connection. Connect to signal ground. Must be connected to REFGND.
22
DGND
-
Digital ground connection. Must be connected to GND.
23
NC
NC
24
BUCK5VT_IN1
I
Buck converter power supply input. Connect 0.1uF and 1µF ceramic capacitors between
this pin and PGND.. This pin must be connected to pins 37, 38, and 39.
25
BUCK5VT_SNS
I
Buck regulator feedback. Connect to the high side of the buck converter output capacitor.
26
LX
O
Switch Node of BUCK converter. Connects to one of the inductor’s terminals.
27
VOSNS
I
TX-A1 coil voltage sense input.
28
PGND
-
Power ground.
29
PGND
-
Power ground.
30
PGND
-
Power ground.
31
NC
NC
32
PGND
-
33
SW
O
34
SW
O
35
SW
O
36
NC
NC
37
IN1
I
38
IN1
I
39
IN1
I
40
ISNS
O
Revision 1.0.2
Not internally connected.
Not internally connected.
Power ground.
Pins 33, 34, and 35 must be connected together. Inverter switch node. Must be connected
to capacitor in series with TX-A1 coil.
Not internally connected.
Inverter power supply input. Connect at least four 22µF x 25V ceramic capacitors and a
0.1μF capacitor between this pin and ground, as close to the pin as possible. Connect all
three pins (37, 38, 39) in parallel.
ISNS output signal
11
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Table 7. IDTP9030 NTG48 Package Pin Functions by Pin Number ()
PIN
NAME
TYPE
I
DESCRIPTION
41
HPF
High pass filter input
42
NC
43
GND
44
NC
Internal connection, must be connected to GND.
45
NC
Internal connection, must be connected to GND.
46
NC
Internal connection, must be connected to GND.
47
NC
Internal connection, must be connected to GND.
48
NC
Internal connection, do not connect.
EP
Center Exposed
Pad
Internal connection, must be connected to GND.
-
Thermal
Ground
EP is on the bottom of the package and must be electrically tied to GND. For thermal
performance, solder to a large copper pad embedded with a pattern of plated through-hole vias.
The die is not electrically bonded to the EP, and the EP must not be used as current-carrying
electrical connection.
Note 1: IN, REG_IN, BUCK5VT_IN. These pins must be connected together at all times.
Note 2: DC-DC BUCK5VT, LDO2P5V, and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM,
thermistor, LED, buzzer and pull up resistor loads (up to an absolute maximum of 25mA), as recommended in Figure 15 WPC “Qi” Compliance Schematic
and Table 6 WPC “Qi” Compliance Bill of Materials.
Revision 1.0.2
12
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
TYPICAL PERFORMANCE CHARACTERISTICS
, IN = BUCK5VT_IN = REG_IN = 19V, TA = 25oC. Unless otherwise noted.
System Efficiency versus RX Output Power: TX Input to RX Output
(IDTP9030 "Qi" TX-A1 Evaluation Kit and IDTP9020 CSP Engineering Sample PCB V1.0)
80.00%
70.00%
Efficiency
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
RX Output Power (W)
Figure 4. Efficiency vs. RX Output Power with IDTP9020 Receiver
Efficiency versus RX Output Power: TX DC-to-AC
(IDTP9030 "Qi" TX-A1 Evaluation Kit and AVID Technologies, Inc., Qi Receiver
Simulator)
0.9
Efficiency
0.8
0.7
0.6
0.5
0.4
0.3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
RX Output Power (W)
Figure 5. Spacing between TX and RX coils is 2 mm
Revision 1.0.2
13
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
SYSTEMS APPLICATIONS DIAGRAM
Inverter
Cp
+
Ls
-
C
Cd
Rm
Power
IDTP9030
IN
Modulation
Cm
Load
Lp
ADAPTOR
Modulation
Cs
SW
EN
EN
WPC TX-A1
88uF
10K
IDTP9020
330nF
ZREF_P
(4x22uF)
100nF
22nF
1
VO
PGND
(3x33nF)
IN_P
IN_P
1.5K
22nF
VOSNS
4.7nF
1
11.4uH
20K
47K
1uF
ISNS
330nF
USB/ADP_IN
HPF
LDO5V
BUCK5VT
LDO2P5V_IN
`
22nF
2.2nF
10uF
3.3nF
1
BUCK5VT_SNS
PGND
ACM_M
ZREF_M
USB_IN
USB_OUT
1
BUCK5VR_IN
REC_OUT
LDO5V_T
BUCK5VR_IN
BUCK5VR_IN
10uF
1uF
BUCK5VR_SNS
LX
LX
LX
4.7uF
BUCK5VR
47nF
LDO2P5V_T
LDO2P5V
1uF
1.8nF
REC_OUT
40uF
IN_M
IN_M
1
20K
10K
REC_OUT
REC_OUT
REC_OUT
2nF
IN_M
10K
1.2nF
BUCK5VT_IN
IN_P
250V
GPIO_1
REG_IN
ACM_P
183nF
GND
1uF/25V
BUCK5VT
REC_OUT
4.7uH
REG_IN
1uF
BST
ISNS
47nF
LX
BST
SCL_T
SDA_T
47nF
LDO2P5V_IN
LDO5V
LDO5V
1uF
RESET
1uF
LDO2P5V_IN
10uF
EN
_T
RESET_T
10uF
1uF
GPIO_4
Buzzer
47K
BUCK5VR
BUCK5VR
SCL
SDA
LDO2P5V
LDO2P5V
1uF
3
GPIO_2
GPIO_3
5.1K
RTOP
47K
2
GND
EP
REFGND
LDO5V
100
5.1K
DGND
LEDA
RESET
GPIO _5
100K
GPIO_0
AGND
GPIO _6
RESET
RNTC
GPIO _4
LEDB
LDO5V
2.7K
SCL
SDA
GPIO _3
2.7K
SCL
SDA
REFGND
AGND
DGND
GPIO_6
5K
GPIO_5
5K
GPIO_4
5K
GPIO_3
5K
GPIO _2
GPIO _1
GPIO _0
GPIO_2
GPIO_1
100nF
5K
GPIO_0
5K
Figure 6. IDTP9030/IDTP9020 Simplified Systems Application Diagram
Revision 1.0.2
14
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
THEORY OF OPERATION
Figure 2 shows the block diagram of the IDTP9030.
When the VIN_UVLO block detects that the voltage at IN,
REG_IN, and BUCK5VT_IN (all connected together
externally) is above the Vin_rising threshold and EN
¯¯ is at
a logic LOW, the Enable Sequence circuitry activates the
voltage reference, the 5V and 2.5V LDOs, the 5V buck
switching regulator, and the Driver Control for the output
inverter.
The voltages at the outputs of the LDOs and the buck
regulator are monitored to ensure that they remain in
regulation, and the adapter voltage, coil current, and
internal temperature are monitored .
The Driver Control block converts a PWM signal from the
MCU to the gate drive signals required by the output
inverter to drive the external resonant tank.
Communication packets from the receiver in the mobile
device are recovered by the Demodulator and converted
to digital signals that can be read by the MCU.
Several internal voltages and the external thermistor
voltage (through GPIO2) are converted to their digital
representations by the ADC and supplied to the MCU.
Five GPIO ports are available to the system designer for
measuring an external temperature (ambient or inductor,
for example) and driving LEDs and a buzzer.
The clock for the MCU and other circuitry is generated by
either an external crystal or an internal RC oscillator.
I2C SDA and SCL pins permit communication with an
external device or host.
Note 1 - Refer to the WPC specification at
http://www.wirelesspowerconsortium.com/ for the most current information
Revision 1.0.2
15
The IDTP9030 has a built-in UVLO circuit that monitors
the input voltage and enables normal operation, as shown
in Figure 7.
UVLO exit event
VCOIL (10V/div)
OVERVIEW
UNDER VOLTAGE LOCKOUT (UVLO)
0V
VIN (5V/div)
The IDTP9030 is a highly-integrated WPC1 (Wireless
Power Consortium)-compliant wireless power charging IC
solution for the transmitter base station. It can deliver
more than 5W of power to the receiver when used with the
IDTP9020 or 5W in WPC “Qi” mode using near-field
magnetic induction as a means to transfer energy. It is the
industry’s first single-chip WPC-compliant solution
designed to drive a WPC-compliant Type-A1 transmitter
coil.
VIN=10V
0V
Time (1s/div)
Figure 7. VIN versus UVLO threshold with /EN low.
OVER-CURRENT/VOLTAGE/TEMPERATURE
PROTECTION
The current in the inverter is monitored by an analog
Current Limit block. If the instantaneous coil current
exceeds 2A, the chip is shut down. VIN_OVP monitors the
voltage applied to the IDTP9030 by the external AC
adapter and shuts the part down if the adapter voltage
rises above 24V, to protect against excessive power
transfer to the receiver. The internal temperature is also
monitored, and the part is temporarily deactivated if the
temperature exceeds 140°C and reactivated when the
temperature falls below 110°C.
DRIVER CONTROL BLOCK and INVERTER
The Driver Control block contains the logic, shoot-through
protection, and gate drivers for the on-chip power FETs.
The FETs are configured as a very large inverter that
switches the SW pin between the voltage at IN and
ground at a rate set by the MCU.
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
100 nF
19V
DEMODULATOR
Driver
Power is transferred from the transmitter to the receiver
through their respective coils: a loosely-coupled
transformer. How much power is transferred is
determined by the transmitter’s switching frequency
(110kHz-205kHz), and is controlled by the receiver
through instructions sent back through the coils to the
transmitter to change its frequency, end power transfer, or
do something else. The instructions take the form of data
packets, which are capacitively coupled into the
IDTP9030’s Demodulator through the HPF pin.
Recovering the data packets is the function of the
Demodulator. Understanding the packets is up to the
MCU.
24 H
A1 Coil
Fsw
Figure 8. Half Bridge inverter TX Coil Driver.
Figure 8 shows the resonant tank configuration from the
WPC specification. IDT has found that the circuit of
Figure 9 is preferred for lower noise in the demodulation
channel.
OUTPUT VOLTAGE SENSE
The voltage at the junction of the external inductor and
capacitor that comprise the resonant tank is monitored by
the VOSNS block, digitized by the ADC, and fed to the
digital control logic. The control algorithm also requires
knowledge of the voltage across the inverter, so that
voltage is also processed by the ADC and sent to the
digital block.
Driver
A1 Coil
100 nF
Fsw
MICRO-CONTROLLER UNIT (MCU)
Figure 9. Half Bridge inverter TX Coil Driver.
The IDTP9030’s MCU processes the algorithm,
commands, and data that control the power transferred to
the reciever. The MCU is provided with RAM and ROM,
and parametric trim and operational modes are set at the
factory through the One-Time Programming (OTP) block,
read by the MCU at power-up. Communication with
external memory is performed through I2C via the SCL
and SDA pins.
EXTERNAL CHIP RESET and EN
¯¯
The IDTP9030 can be externally reset by pulling the
RESET pin to a logic high above the VIH level.
The RESET pin is a dedicated high-impedance active-high
digital input, and the effect is similar to the power-up reset
function. Because of the internal low voltage monitoring
scheme, the use of the external RESET pin is not
mandatory. A manual external reset scheme can be
added by connecting 5V to the RESET pin through a
simple switch. When RESET is HIGH, the
microcontroller’s registers are set to the default
configuration. When the RESET pin is released to a LOW,
the microcontroller starts executing the code from the boot
address. If the application is in a noisy environment, an
external RC filter is recommended (see Figure 10 for
reference)
APPLICATIONS INFORMATION
The recommended applications schematic diagram is
shown in Figure 15. The IDTP9030 operates with a 19VDC
(±1V) input. The switching frequency varies from 110kHz
to 205kHz. At the 205kHz limit the duty cycle is also
variable. The power transfer is controlled via changes in
switching frequency. The base or TX-side has a series
resonance circuit made of a WPC Type-A1 coil (~24H)
and a series resonant capacitor (~100nF) circuit driven by
a half-bridge inverter, as shown in Figure 8.
Revision 1.0.2
24 H
19V
16
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
chip RC oscillator is provided to the input of a PLL to
generate the system clock. IDT recommends using the
internal oscillator.
LDO5V
PUSH
BUTTON
SWITCH
C2
1F
C1
0.1F
SYSTEM FEEDBACK CONTROL (WPC)
RESET
R
10K ~ 100K
Figure 10. External Pushbutton Reset Circuit.
When the EN
¯¯ pin is pulled high, the device is suspended
and placed in low current (sleep) mode. If pulled low, the
device is active.
EN\ (5V/Div)
Buck 5VOUT (2.5V/Div)
EN\ rising edge function
The IDTP9030 contains logic to demodulate and decode
error packets sent by the mobile device (Rx-side), and
adjusts power transfer accordingly. The IDTP9030 varies
the switching frequency of the half bridge inverter between
110kHz to 205 kHz. to adjust power transfer. The mobile
device controls the amount of power transferred via a
communication link that exists from the mobile device to
the base station. The mobile device (IDTP9020 or another
WPC-compliant receiver) communicates with the
IDTP9030 via communication packets. Each packet has
the following format:
Table 5 – Data Packet Format.
Preamble
Header
Message
Checksum
The overall system behavior between the transmitter and
receiver follows the state machine diagram below:
0V
0V
Time (1ms/div)
Figure 11. /EN Function.
The current into EN
¯¯ is about
,
or close to zero if V(EN
¯¯) is less than 2V.
Figure 12. System state machine diagram
XTAL_CLK/IN and XTAL_CLK/OUT
A 32.768kHz crystal connected between the
XTAL/CLK_IN and XTAL/CLK_OUT pins establishes a
precise time base. Either that clock or the output of an onRevision 1.0.2
17
The IDTP9030 performs four phases: Selection, Ping,
Identification & Configuration, and Power Transfer.
START (SELECTION) PHASE
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
In this phase, the IDTP9030 operates in a low power
mode to determine if a potential receiver has been placed
on the coil surface prior to the PING state. Twice a second,
the IDTP9030 applies a brief ac signal to its coil and
listens for a response.
Also, the IDTP9030 must correctly receive the following
sequence of packets without changing the operating point
(175 kHz @ 50% duty cycle):
1. Identification Packet (0x71)
2. Extented Identification (0x81)
3. Up to 7 optional configuration Packets
from the following set:
a. Power Control Hold-Off Packet
(0x06)
b. Proprietary Packet (0x18 –
0xF2)
c. Reserved Packet
4. Configuration Packet (0x51)
PING PHASE
In this phase, the IDTP9030 applies a power signal at 175
kHz with a fixed 50% duty cycle and attempts to establish
a communication link with a mobile device.
Required packet(s) in PING:
1. Signal strength packet (0x01)
The mobile device must send a Signal Strength Packet
within a time period specified by the WPC, otherwise the
power signal is terminated and the process repeats.
If the IDTP9030 does not detect the start bit of the header
byte of the next Packet in the sequence within a WPCspecified time after receiving the stop bit of the checksum
byte of the preceding Signal Strength Packet, then the
Power Signal is removed within after a delay. If a correct
control packet in the above sequence is received late, or if
control packets that are not in the sequence are received,
the IDTP9030 removes the Power Signal after a delay.
The mobile device calculates the Signal Strength Packet
value, which is an unsigned integer value between 0-255,
based on this formula:
POWER TRANSFER PHASE
where U is a monitored variable (i.e. rectified
voltage/current/power) and Umax is a maximum value of
that monitored variable expected during the digital ping
phase at 175 kHz.
In this phase, the IDTP9030 adapts the power transfer to
the receiver based on control data it receives in control
error packets.
Required packet(s) in Power Transfer:
If the IDTP9030 does not detect the start bit of the header
byte of the Signal Strength Packet during the Ping Phase,
it removes the power signal after a delay. If a signal
strength packet is received, the IDTP9030 goes to the
Identification and Configuration Phase. If the IDTP9030
does not move to the Identification and Configuration
Phase after receiving the signal strength packet, or if a
packet other than a signal strength packet is received,
then power is terminated.
1. Control Error Packet (0x03)
2. Rectified Power Packet (0x04)
For this purpose, the IDTP9030 may receive zero or more
of the following Packets:
1.
2.
3.
4.
5.
6.
IDENTIFICATION AND CONFIGURATION (ID & Config)
In this phase, the IDTP9030 tries to identify the mobile
device and collects configuration information.
Required packet(s) in ID & Config:
If the IDTP9030 does not correctly receive the first Control
Error Packet in time, it removes the Power Signal after a
delay. Because Control Error Packets come at a regular
interval, the IDTP9030 expects a new Control Error
Packet after receiving the stop bit of the checksum byte of
the preceding Control Error Packet. If that does not
1. Identification packet (0x71)
2. Extended Identification packet (0x81)*
3. Configuration packet (0x51)
* If
Ext bit of 0x71 packet is set to 1.
Revision 1.0.2
Control Error Packet (0x03)
Rectified Power Packet (0x04)
Charge Status Packet (0x05)
End Power Transfer Packet (0x02)
Any Proprietary Packet
Any reserved Packets
18
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
happen, then the IDTP9030 removes the Power Signal.
Similary, the IDTP9030 must receive a Rectified Power
Packet within a WPC-specified time after receiving the
stop bit of the checksum byte of the Configuration Packet
(which was received earlier in the identification and
configuration phase). Otherwise, it removes the Power
Signal.
Upon receiving a Control Error value, the IDTP9030
makes adjustments to its operating point after a delay to
enable the Primary Coil current to stabilize again after
communication.
If the IDTP9030 correctly receives a Packet that does not
comply with the sequence, then it removes the Power
Signal.
FOREIGN OBJECT DETECTION (FOD)
In addition to over-temperature protection, the IDTP9030
employs a proprietary FOD technique for safety which
detects foreign objects placed on the base station. The
FOD algorithm is multi-layered and issues warnings
depending on the severity of the warning.
The FOD warning comes on during the PING phase
indicating the presence of a smaller object and larger
object respectively. The FOD warning is asserted during
the Power Transfer phase, indicating presence of a
foreign object. With this warning ON, the IDTP9030 stops
power transfer, goes back to the PING phase, and stays
there until the surface is cleared and the process starts
over again.
Revision 1.0.2
19
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
APPLICATIONS INFORMATION
1
2
3
AC Adapter
C2
+
J3
C6
VIN
C7
22uF/25V
0.1uF
LEDA
C10
22uF/25V
C13
22uF/25V
C14
22uF/25V
R69
RED
R7
GREEN
R8
D1
VIN
C4
82uF/25V OSCON
0.1uF
LDO2P5_OUT
NP
5.1K
4
LDO2P5_OUT
2
LEDC
R9
NP
NP
3
5
D4
36
LDO2P5_OUT
R71
31
NP
23
R21
R20
422
BZ1
NP
10
1
11
2
R22
47k
21
14
PS1240P02CT3
43
Th1
R17
10K
49
22
10K
1
SCL
8
2
SDA
9
3
VIN
4
LDO5_OUT
5
EN
39
37
38
IN
IN
IN
45
46
44
NC
NC
PGND
GPIO_2
PGND
NC
PGND
U1
NC
PGND
IDTP9030
NC
VOSNS
XTAL_CLK_IN
GPIO_1
AGND
ISNS
R18
R24
100K
10K
HPF
U2
A0
A1
A2
VSS
VCC
WP
SCL
SDA
R16
10K
R19
2.7K
C23
33nF/250V
C20
33nF/250V
D6
200V Diode
29
R31
28
C27
27
6
D5
C19
R27
4.7n
47K
22n/50V
1.5K
R30
20K
R28
R29
C28
20K
10K
1.2nF/100V
40
C15
10K
R26
41
C18
DGND
C24
3.3n
1.8nF
SCL
BUCK5VT_IN
BST
LX
C16
C21
0.1u/50V
10u/25V
25
20
C17
EN
RESET
VIN
24
SDA
VIN
C1
0.1uF
30
2.2n
EP
LDO2P5_OUT
+5V
24uH
32
26
BUCK5VT
WP
WPC TX-A1 COIL,
VO
33nF/250V
47nF
L2
4.7uH
+5V
C22
C26
0.1uF
10uF/6.3V
19
LDO2P5_OUT
9
L1,
3x33nF/250V, C0G)
GND
LDO2P5V_IN
8
C29
(2x47nF/250V, C0G or
REFGND
18
RESET
C20, C23, C25
33
XTAL_CLK_OUT
REG_IN
1u
7
1
2
3
4
47
GPIO_4
LDO2P5V
12
34
C25
17
13
35
GPIO_6
BUCK5VT_SNS
6
10
SW
15
I2C connector
J1
C5
100n
GPIO_5
NC
R10
SW
42
NP
LEDD
NP
SW
GPIO_3
LDO5V
NP
D3
1
R72
GPIO_0
NC
7
47k
NC
R70
NC
5.1k
16
LEDB
48
D2
LDO5_OUT
LDO2P5_OUT
R23
2.7K
C8
C9
C11
C12
1u
1u
1u
1u
8
7
6
5
24LC64
Figure 15. IDTP9030 WPC “Qi” Compliance Schematic (See IDTP9030 valuation Kit User Manual for complete details)
Revision 1.0.2
20
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Table 6. IDTP9030 WPC “Qi” Compliance Bill of Materials
Item # Qty Ref Design
C2,C16,C22
1
3
Description
Manufacturer
Part #
PCB Footprint
TDK
C2012X7R1H104K/0.85
805
TDK
C4532C0G2E333JT
1812
3
C20,C23,C25 Option 1
CAP CER 0.1UF 50V 10% X7R
CAP CER 0.033UF 250V 5% NP0/C0G1
2
C20,C23
CAP CER 0.047UF 250V 5% NP0/C0G1
TDK
C4532C0G2E473JT
1812
3
5
C8,C9,C11,C12,C29
CAP CER 1UF 25V 10% X7R
Taiyo Yuden
TMK107B7105KA-T
0603
4
4
C7, C10, C13, C14
CAP CER 22UF 25V 10% X7R
Taiyo Yuden
TMK325B7226MM-TR
5
1
C4
OSCON 82UF 25V 20% 105DEGC
Panasonic
25SVPF82M
1210
E7
5
1
C17
CAP CER 0.047UF 16V 10% X7R
Murata
GRM188R71C473KA01D
0603
6
1
C21
CAP CER 10UF 25V 10% X5R
TDK
C2012X5R1E106K
0805
7
1
C15
CAP CER 2200PF 16V 10% X7R
AVX
0603YC222KAT2A
603
8
1
C6
CAP CER 0.1UF 50V 10% X7R
Murata
GRM188R71H104KA93D
0603
9
1
C26
Taiyo Yuden
JMK212B7106KG-T
805
10
1
C18
CAP CER 10UF 6.3V 10% X7R
CAP CER 3300PF 50V 5% NP0/C0G1
Murata
GCM1885C1H332JA16D
0603
11
1
C24
CAP CER 1800PF 50V 5% NP0/C0G1
Murata
GRM1885C1H182JA01D
0603
12
1
C27
TDK
C1608X7R2A223K
0603
12
1
C28
CAP CER 0.022UF 100V X7R 10%
CAP CER 1200PF 100V 5% NP0/C0G1
TDK
C1608C0G2A122J
0603
13
1
C19
CAP CER 4700PF 50V 5% NP0/C0G1
TDK
CGJ3E2C0G1H472J
0603
14
1
D6
DIODE SWITCH 200V 250MW
Diodes Inc
BAV21W-7-F
SOD123
15
1
D5
DIODE SWITCH 75V 300mA
Micro Comm Co
1N4148W-TP
SOD123
16
1
L2
4.7uH 20% 580mA
Coilcraft
E&E
XPL2010-472ML
Y31-60014F
2ML
17
1
L1
24uH Transmitter Coil WPC TX-A1
TDK
TTx-52-T2V
53mmx53mm
Toko
X1387
2
Option 2
18
1
R18
RES 100K OHM 1/16W 1%
Yageo
RC0402FR-07100KL
402
19
2
R28,R30
RES 20.0K OHM 1/10W 1%
Panasonic
ERJ-3EKF2002V
0603
20
1
R31
RES 1.50K OHM 1/10W 1%
Panasonic
ERJ-3EKF1501V
0603
20
1
R24
RES 10.0K OHM 1/16W 1%
RC0402FR-0710KL
402
21
1
R29
RES 10.0K OHM 1/10W 1% 0603 SMD
Yageo
Panasonic
ERJ-3EKF1002V
603
22
1
R27
RES 47K OHM 1/10W 5%
Panasonic
ERJ-2GEJ473X
402
23
1
U1
IC EEPROM 64KBIT 400KHZ
Microchip
24AA64T-I/MNY
8TDFN
24
1
U2
IC Wireless Power Transmitter
IDT
IDTP9030
6x6x0.8-48TQFN
WPC "Qi" Compliance Components
1
1
D1
LED SMARTLED 630NM RED
OSRAM
L29K-G1J2-1-0-2-R18-Z
0603_LED
2
D2
19
1
2
R7, R8
LED SMARTLED GREEN 570NM
RES 4.9K OHM 1/10W 5%
OSRAM
Panasonic
LG L29K-G2J1-24-Z
ERJ-2RKF4991X
0603_LED
402
20
3
R16,R17,R24
RES 10.0K OHM 1/16W 1%
Yageo
RC0402FR-0710KL
402
21
1
R20
RES 422 OHM 1/10W 1%
Panasonic
ERJ-2RKF4220X
402
22
2
R19,R23
RES 2.7K OHM 1/10W 5%
Panasonic
ERJ-2GEJ272X
402
23
2
C1,C5
CAP CER 0.1UF 50V 10% X7R
Murata
GRM188R71H104KA93D
0603
24
1
TH1
THERMISTOR NTC 10K OHM 1% RAD
TDK
B57551G0103F000
Through-hole
25
1
BZ1
BUZZER PIEZO 4KHZ PC MNT
TDK
PS1240P02CT3
12.2mmx3.5mm
I2C Communication
Note 1: Recommended capacitor temperature/dielectric and voltage ratings:
250V capacitors are recommended because 200Vp-p voltage levels may appear
on the resonance capacitors as stated in the WPC specification. C0G/NPO-type
capacitor values stay relatively constant with voltage while X7R and X5R
ceramic capacitor values de-rate from 40% to over 80%. The decision to use
lower voltage 100V capacitors or other type temperature/dielectric capacitors is
left to the end user.
The IDTP9030 includes an I2C block which can support
either I2C Master or I2C Slave operation. After power-onreset (POR), the IDTP9030 will initially become I2C Master
for the purpose of uploading firmware from an external
memory device, such as an EEPROM. The I2C Master
mode on the IDTP9030 does not support multi-master
mode, and it is important for system designers to avoid
any bus master conflict until the IDTP9030 has finished
any firmware uploading and has released control of the
bus as I2C Master. After any firmware uploading from
external memory is complete, and when the IDTP9030
begins normal operation, the IDTP9030 is normally
configured by the firmware to be exclusively in I2C Slave
mode.
External Components
The IDTP9030 requires a minimum number of external
components for proper operation (see the BOM in Table
10). A complete design schematic compliant to the WPC
“Qi” standard is given in Figure 19. It includes WPC “Qi”
LED signaling, buzzer, thermistor circuit, and EEPROM for
loading IDTP9030 firmware.
Revision 1.0.2
21
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet

For maximum flexibility, the IDTP9030 tries to
communicate with the first address on the EEPROM at
100kHz. If no ACK is received, communication is
attempted at the other addresses at 300kHz.
GPIO5 LEDC and GPIO6 LEDD are for future
development, and are currently not defined.
EEPROM
LED FUNCTIONS
The IDTP9030 uses an external EEPROM which contains
either standard or custom TX firmware. The external
EEPROM memory chip is pre-programmed with a
standard start-up program that is automatically loaded
when 19V power is applied. The IDTP9030 uses I2C slave
address 0x52 to access the EEPROM. The IDTP9030
slave address is 0x39. The EEPROM can be
reprogrammed to suit the needs of a specific application
using the IDTP9030 software tool (see the IDTP9030-Qi
Demo Board User Manual for complete details). The IC
will look initially for an external EEPROM and use the
firmware built into the IC ROM only if no custom firmware
is found. A serial 8Kbyte (8Kx8 64Kbits) external
EEPROM is sufficient.
Two GPIOs are used to drive LEDs which indicate,
through various on/off and illumination options, the state of
charging and some possible fault conditions.
A red L D indicates various Fault and FOD (“Foreign
Object Detection”) states. The green L D indicates
Power Transfer and Charge Complete state information.
Upon power up, the two LEDs together may optionally
indicate the Standby State and remain in this state until
another of the defined Operational States occurs
As shown in Figure 16, one or two resistors configure the
defined LED option combinations. The DC voltage set in
this way is read one time during power-on to determine
the LED configuration. To avoid interfering with the LED
operation, the useful DC voltage range must be limited to
not greater than 1Vdc.
If the standard default/built-in firmware is not suitable for
the application, custom ROM options are possible. Please
contact IDT sales for more information. IDT will provide
the appropriate image in the format best suited to the
application.
LDO2P5V_OUT
IDTP9030
Overview of Standard GPIO Usage
Ra
There are 7 GPIO’s on the IDTP9030 transmitter IC, of
which five are available for use as follows:




GPIO3
GPIO0: Red LED_A to indicate standby, fault
conditions, and FOD warnings; see table 7.
Resistor
to set
options
GPIO2: Temperature sensor input. Contact IDT
for a spreadsheet facilitating selection and use of
thermistors.
LED Mode Resistor Configuration
Figure 16. IDTP9030 LED Resistor Options.
GPIO3: Green LED_B to indicate standby, power
transfer, and power complete. Table 7 lists how
the red and green LEDs can be used to display
information about the IDTP9030’s operating
modes. The table also includes information
about external resistors or internal pull up/down
options to select LED modes. Eight of the ten
LED modes (those associated with advanced
charging modes) are currently designated as
“Future” modes.
LED Pattern Operational Status Definitions:
Blink Slow: 1s ON, 1s OFF, repeat.
Blink Fast: 400ms ON, 800ms OFF, 400ms ON, 800ms
OFF, repeat.
The red FOD warning LED is synchronized with the
buzzer (if implemented) such that a 400ms tone
corresponds with the FOD red LED illumination and
800ms of silence corresponds with the LED being off.
During the 30s that the buzzer is off, the FOD LED must
continue to blink.
GPIO4: AC or DC buzzer (optional) with resistor
options for different buzzer configurations.
Revision 1.0.2
To ADC
Rb
22
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Table 7 – IDTP9030 LED Resistor Optioning (Not all options supported, shaded rows are for future development).
LED Control
Option
LED Select
Resistor Value
Description
1
Pull Down
Standby LEDs ON
2
R1
Standby LEDs ON plus
3
R2
Standby LEDs ON plus
4
R3
Standby LEDs ON plus
5
R4
Standby LEDs ON plus
6
Pull Up
Standby LEDs OFF
7
R5
Standby LEDs OFF plus
8
R6
Standby LEDs OFF plus
9
R7
Standby LEDs OFF plus
10
R8
Standby LEDs OFF plus
Operational Charge
Status
Power
LED #/
Transfer
Complete
Color
Standby
LED1- Green
ON
BLINK SLOW
ON
LED2- Red
ON
OFF
OFF
LED1- Green
ON
BLINK SLOW
ON
LED2- Red
ON
OFF
OFF
LED1- Green
ON
BLINK SLOW
ON
LED2- Red
ON
OFF
OFF
LED1- Green
ON
BLINK SLOW
ON
LED2- Red
ON
OFF
OFF
LED1- Green
ON
BLINK SLOW
ON
LED2- Red
ON
OFF
OFF
LED1- Green
OFF
BLINK SLOW
ON
LED2- Red
OFF
OFF
OFF
LED1- Green
OFF
BLINK SLOW
ON
LED2- Red
OFF
OFF
OFF
LED1- Green
OFF
BLINK SLOW
ON
LED2- Red
OFF
OFF
OFF
LED1- Green
OFF
BLINK SLOW
ON
LED2- Red
OFF
OFF
OFF
LED1- Green
OFF
BLINK SLOW
ON
LED2- Red
OFF
OFF
OFF
Fault
Condition
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
FOD
Warning
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
OFF
BLINK FAST
R1-R8 are created using combination of two 1% resistors.
Designates Future Option
Buzzer Function
An optional buzzer feature is supported on GPIO4. The
default configuration is an “AC” buzzer. The signal is
created by toggling GPIO4 active-high/active-low at a
2KHz frequency.
For 30 seconds: 400ms ON, 800ms OFF, repeat
Next 30 seconds: Off/silence (but no change to LED
on/off patterns)
The pattern is repeated while the error condition exists
Buzzer Action: Power Transfer Indication
The IDTP9030 supports audible notification when the
device operation successfully reaches the Power Transfer
state. The duration of the power transfer indication sound
is 400ms.
The buzzer is synchronized with the FOD LED such that
the 400ms on tone corresponds with the Red LED
illumination and 800ms off (no sound) corresponds with
Red LED being off.
The latency between reaching the Power Transfer state
and sounding the buzzer does not exceed 500ms.
Additionally, the buzzer sound is concurrent within
±250ms of any change to the LED configuration indicating
the start of power transfer.
Buzzer Action: No Power Transfer due to Foreign
Object Detected (FOD)
When a major FOD situation is detected such that, for
safety reasons, power transfer is not initiated, or that
power transfer is terminated, the buzzer is sounded in a
repeating sequence:
Revision 1.0.2
23
Decoupling/Bulk Capacitors
As with any high-performance mixed-signal IC, the
IDTP9030 must be isolated from the system power supply
noise to perform optimally. A decoupling capacitor of
0.1μF must be connected between each power supply and
the PCB ground plane as close to these pins as possible.
For optimum device performance, the decoupling
capacitor must be mounted on the component side of the
PCB. Avoid the use of vias in the decoupling circuit.
Additionally, medium value capacitors in the 22μF range
must be used at the VIN input to minimize ripple current
and voltage droop due to the large current requirements of
the resonant half Half-Bridge driver. At least four 22μF
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
capacitors must be used close to the IN pins of the device.
Since the operating voltage is 18V to 20V, the value of the
capacitors will decrease due to voltage derating
characteristics. For example, a 22μF X7R 25V capacitor’s
value is actually 6μF when operating at 20V.
together to minimize any DC regulation errors caused by
ground potential differences.
The bootstrap pin requires a small capacitor; connect a
47nF bootstrap capacitor rated above 25V between the
BST pin and the LX pin.
There must also be an 82μF to 100μF bulk capacitor
connected at the node where the input voltage to the
board is applied. A 25V Oscon-type or aluminum
electrolytic must be connected between the input supply
and ground as shown in Figure 20. Oscon capacitors have
much lower ESR than aluminum electrolytic capacitors
and will reduce voltage ripple.
The output-sense connection to the feedback pins must
be separated from any power trace. Connect the outputsense trace as close as possible to the load point to avoid
additional load regulation errors. Sensing through a highcurrent load trace will degrade DC load regulation.
The power traces, including PGND traces, the SW or OUT
traces and the VIN trace must be kept short, direct and
wide to allow large current flow. The inductor connection
to the SW or OUT pins must be as short as possible. Use
several via pads when routing between layers.
ADC Considerations
The GPIO pins are connected internally to a successive
approximation ADC with a multiplexed input. The GPIO
pins that are connected to the ADC have limited input
range, so attention must be paid to the maximum VIN
(2.5V). 0.01μF decoupling capacitors can be added to the
GPIO inputs to minimize noise.
LDOs
Input Capacitor
The input capacitors must be located as physically close
as possible to the power pin (LDO2P5V_IN) and power
ground (GND). Ceramic capacitors are recommended for
their higher current operation and small profile. Also,
ceramic capacitors are inherently more capable than are
tantalum capacitors to withstand input current surges from
low impedance sources such as batteries used in portable
devices. Typically, 10V- or 16V-rated capacitors are
required. The recommended external components are
shown in Table 10.
WPC TX-A1 Coil
The SW pin connects to a series-resonance circuit
comprising a WPC Type-A1 coil (~24H) and a series
resonant capacitor (~100nF), as shown in Figures 8 and 9.
The inductor serves as the primary coil in a looselycoupled transformer, the secondary of which is the
inductor connected to the power receiver (IDTP9020 or
another receiver).
Output Capacitor
For proper load voltage regulation and operational stability,
a capacitor is required on the output of each LDO
(LDO2P5V and LDO5V). The output capacitor must be
placed as close to the device and power (PGND) pins as
possible. Since the LDOs have been designed to function
with very low ESR capacitors, a ceramic capacitor is
recommended for best performance.
The TX-A1 power transmitter coil is mounted on a ferrite
shield to reduce EMI. The coil assembly can be mounted
next to the IDTP9030. Either ground plane or grounded
copper shielding can be added beneath the ferrite shield
for added reduction in radiated electrical field emissions.
The coil ground plane/shield must be connected to the
IDTP9030 ground plane by a single trace.
Resonance Capacitors
The resonance capacitors must be C0G type dielectric
and have a DC rating to 250V. The highest-efficiency
combination is three 33nF in parallel to get the lowest
ESR. Using a single 100nF or two 47nF capacitors is also
an option. The part numbers are shown in Table 6.
PCB Layout Considerations
Buck Converter
The input capacitors (CIN) must be connected directly
between the power VIN and power PGND pins. The output
capacitor (COUT) and power ground must be connected
Revision 1.0.2
24
-
For optimum device performance and lowest output
phase noise, the following guidelines must be
observed. Please contact IDT for Gerber files that
contain the recommended board layout.
-
As for all switching power supplies, especially those
providing high current and using high switching
frequencies, layout is an important design step. If
layout is not carefully done, the regulator could show
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
instability as well as EMI problems. Therefore, use
wide and short traces for high current paths.
-
-
-
The 0.1μF decoupling capacitors must be mounted on
the component side of the board as close to the VDD
pin as possible. Do not use vias between decoupling
capacitors and VDD pins. Keep PCB traces to each
VDD pin and to ground vias as short as possible.
To optimize board layout, place all components on
the same side of the board and limit the use of vias.
Route other signal traces away from the IDTP9030.
For example, use keepouts for signal traces routing
on inner and bottom layers underneath the device.
The NQG48 6.0 mm x 6x0 mm x 75mm 48L package
has an inner thermal pad which requires blind
assembly. It is recommended that a more active flux
solder paste be used such as Alpha OM-350 solder
paste
from
Cookson
Electronics
(http://www.cooksonsemi.com). Please contact IDT
for Gerber files that contain recommended solder
stencil design.
-
The package center exposed pad (EP) must be
reliably soldered directly to the PCB. The center land
pad on the PCB (set 1:1 with EP) must also be tied to
the board ground plane, primarily to maximize thermal
performance in the application.
The ground
connection is best achieved using a matrix of PTH
vias embedded in the PCB center land pad for the
NTG48. The PTH vias perform as thermal conduits to
the ground plane (thermally, a heat spreader) as well
as to the solder side of the board. There, these
thermal vias embed in a copper fill having the same
dimensions as the center land pad on the component
side. Recommendations for the via finished hole-size
and array pitch are 0.3mm to 0.33mm and 1.3mm,
respectively.
-
Layout and PCB design have a significant influence
on the power dissipation capabilities of power
management ICs. This is due to the fact that the
surface mount packages used with these devices rely
heavily on thermally conductive traces or pads to
transfer heat away from the package. Appropriate PC
layout techniques must then be used to remove the
heat due to device power dissipation. The following
general guidelines will be helpful in designing a board
layout for lowest thermal resistance:
1. PC board traces with large cross sectional
areas remove more heat. For optimum
Revision 1.0.2
25
2.
3.
4.
5.
results, use large area PCB patterns with
wide and heavy (2 oz.) copper traces, placed
on the top layer of the PCB.
In cases where maximum heat dissipation is
required, use double-sided copper planes
connected with multiple vias.
Thermal vias are needed to provide a
thermal path to the inner and/or bottom
layers of the PCB to remove the heat
generated by device power dissipation.
Where possible, increase the thermally
conducting surface area(s) openly exposed
to moving air, so that heat can be removed
by convection (or forced air flow, if
available).
Do not use solder mask or place silkscreen
on the heat-dissipating traces/pads, as they
increase the net thermal resistance of the
mounted IC package.
Power Dissipation/Thermal Requirements
The IDTP9030 is offered in a TQFN-48L package. The
maximum power dissipation capability is 2W, limited by
the die’s specified maximum operating junction
temperature, Tj, of 125°C. The junction temperature rises
with the device power dissipation based on the package
thermal resistance. The package offers a typical thermal
resistance, junction to ambient (JA), of 31°C/W when the
PCB layout and surrounding devices are optimized as
described in the PCB Layout Considerations section. The
techniques as noted in the PCB Layout section need to be
followed when designing the printed circuit board layout,
as well as the placement of the IDTP9030 IC package in
proximity to other heat generating devices in a given
application design. The ambient temperature around the
power IC will also have an effect on the thermal limits of
an application. The main factors influencing θJA (in the
order of decreasing influence) are PCB characteristics,
die/package attach thermal pad size, and internal package
construction. Board designers should keep in mind that
the package thermal metric θJA is impacted by the
characteristics of the PCB itself upon which the TQFN is
mounted. For example, in a still air environment, as is
often the case, a significant amount of the heat that is
generated (60 - 85%) sinks into the PCB. Changing the
design or configuration of the PCB changes impacts the
overall thermal resistivity and, thus, the board’s heat
sinking efficiency.
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
Implementation of integrated circuits in low-profile and
fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many systemdependant issues such as thermal coupling, airflow,
added heat sinks, and convection surfaces, and the
presence of other heat-generating components, affect the
power-dissipation limits of a given component.
state ambient temperature (TA) of 85°C. Therefore, the
maximum recommended power dissipation is:
PD(Max) = (150°C - 85°C) / 30°C/W
Thermal Overload Protection
The IDTP9030 integrates thermal overload shutdown
circuitry to prevent damage resulting from excessive
thermal stress that may be encountered under fault
conditions. This circuitry will shut down or reset the device
if the die temperature exceeds 140°C. To allow the
maximum load current on each regulator and resonant
transmitter, and to prevent thermal overload, it is important
to ensure that the heat generated by the IDTP9030 is
dissipated into the PCB. The package exposed paddle
must be soldered to the PCB, with multiple vias evenly
distributed under the exposed paddle and exiting the
bottom side of the PCB. This improves heat flow away
from the package and minimizes package thermal
gradients.
Three basic approaches for enhancing thermal
performance are listed below:
1. Improving the power dissipation capability of the
PCB design
2. Improving the thermal coupling of the component
to the PCB
3. Introducing airflow into the system
First, the maximum power dissipation for a given situation
must be calculated:
PD(MAX) = (TJ(MAX) - TA)/θJA
Where:
Special Notes
NQG TQFN-48 Package Assembly
Note 1: Unopened Dry Packaged Parts have a one year
shelf life.
Note 2: The HIC indicator card for newly opened Dry
Packaged Parts should be checked. If there is any
moisture content, the parts must be baked for minimum of
8 hours at 125˚C within 24 hours of the assembly reflow
process.
PD(MAX) = Maximum Power Dissipation (W)
θJA = Package Thermal Resistance (°C/W)
TJ(MAX) = Maximum Device Junction Temperature (°C)
TA = Ambient Temperature (°C)
The maximum recommended junction temperature (TJ(MAX))
for the IDTP9030 device is 150°C. The thermal resistance
of the 48-pin NQG package (NGQ48) is optimally
θJA=30°C/W. Operation is specified to a maximum steady-
Revision 1.0.2
2 Watt
26
© 2012 Integrated Device Technology, Inc.
IDTP9030
Product Datasheet
PACKAGE OUTLINE DRAWING
REVISIONS
DCN
REV
DESCRIPTION
DATE
00
INITIAL RELEASE
3/16/10
APPROVED
POD IN BOTTOM VIEW
37
DAP SIZE 4.5x4.5
48
36
1
C0.35
25
12
24
13
IDT
TOLERANCES
UNLESS SPECIFIED
POD IN SIDE VIEW
DECIMAL
X± .1
XX± .05
XXX± .030
APPROVALS
DRAWN
PKP
CHECKED
TM
ANGULAR
±1°
DATE
12/04/09
6024 SILVER CREEK
VALLEY ROAD. SAN JOSE,
CA 95138
PHONE: (408) 284-8200
FAX: (408) 284-3572
www.IDT.com
TITLE NT/NTG48 PACKAGE OUTLINE
6.0 x 6.0 mm BODY
0.4 mm PITCH TQFN
SIZE
C
DRAWING No.
REV
PSC-4294
DO NOT SCALE DRAWING
00
SHEET
1OF
1
Figure 17. IDTP9030 Package Outline Drawing (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm48L, 0.4mm pitch)
Revision 1.0.2
27
© 2012 Integrated Device Technology, Inc.
VPAxxxx
Preliminary Product Data
ORDERING GUIDE
Table 8. Ordering Summary
PART
NUMBER
MARKING
PACKAGE
AMBIENT TEMP.
RANGE
SHIPPING
CARRIER
QUANTITY
P9030-0NTGI
P9030-0NTGI8
P9030NTG
P9030NTG
NTG48 - TQFN-48 6x6x0.75mm
NTG48 - TQFN-48 6x6x0.75mm
-40°C to +85°C
-40°C to +85°C
Tape or Canister
Tape and Reel
25
2,500
www.IDT.com
6024 Silver Creek Valley Road
San Jose, California 95138
Tel: 800-345-7015
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in c ustomer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of
merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT
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© Copyright 2012. All rights reserved.
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