SETHER - Electrocomponents

J193 SETHER

SETHER

STEbus Ethernet

Network Board

User’s Manual

Section

Contents

Page

1.

Introduction 3

The SETHER Board and Ethernet 3

Features

2.

Ethernet (IEEE 802.3)

3

4

Introduction

Ethernet Packet Structure

3.

Hardware Installation

Storage and Handling

7

7

4

5

Links and Options

Installation

7

10

Network Cabling and Connectors

4.

Circuit Description

10

13

5.

Troubleshooting 16

Appendix

A.

Component List

B.

STEbus Connector Pin Assignments

C.

Specification

D.

Example Program

F.

Circuit Diagrams

© Arcom Control Systems Ltd 1991

Arcom Control Systems Ltd

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18

19

20

28

29

Page 1

J193 SETHER

Manual

V1 Iss 2

V2 Iss 1

V2 Iss 1a

V2 Iss 1b

PCB

V1 Iss 2

V2 Iss 1

Revision History

Revision History

Comments

900807 First Full Release

910807 Released in new format

[ECO 418] Various edits

New example program

920809 [ECO837,915]

940809 New AUI Connector Diagram

© Arcom Control Systems Ltd.

Cambridge, England

1991

The choice of boards or systems is the responsibility of the buyer, and the use to which they are put cannot be the liability of Arcom Control Systems Ltd. However,

Arcom’s sales team is always available to assist you in making your decision.

Page 2 Arcom Control Systems Ltd

Section 1. Introduction J193 SETHER

Section 1. Introduction

The SETHER board and Ethernet

The SETHER board provides a high performance interface between STEbus based processor systems and the IEEE 802.3

Ethernet network. Ethernet is a 10 Mbits/s high-performance networking system, allowing many different types of computer

(PCs, STEbus, VMEbus) to interchange messages and share files, hard disks, and other peripherals. This manual provides a brief overview of Ethernet and shows how the SETHER board is implemented. The SETHER utilises the National Semiconductor DP8390 Ethernet chip set which consists of the DP8390

Network Interface Chip (NIC), DP8391 Serial Network Interface

(SNI) and DP8392 Coaxial Transceiver Interface (CTI).

A number of network driver packages are available from Arcom for DOS based, OS/9 systems and standalone target systems.

For detailed hardware and programming information relating to the 8390 chip set refer to the National Semiconductor’s "Data

Comms, Local Area Network, UART Handbook".

The board includes two useful LED’s to indicate when data is being received or transmitted by the 8390 NIC.

Features include:

Full STEbus slave interface

Full Ethernet interface

Thin-wire Ethernet (Cheapernet) interface

National Semiconductors’ DP8390 controller chip

Software compatible with PCbus Ethernet board

Ethernet BIOS ROM socket

Dual-port RAM with local DMA

LED indication of Ethernet Rx and Tx traffic

Interrupts on any level (ATNRQ0-7)

SETHER board network ’burned in address’ stored in PROM

Complete TCP/IP protocol package available

Software drivers available from Arcom for various operating systems such as OS-9

Arcom Control Systems Ltd Page 3

J193 SETHER Section 2. Ethernet (IEEE 802.3)

Section 2. Ethernet (IEEE 802.3)

Page 4

Introduction

The DP8390 chip set is designed to provide the physical and media access control layer functions of the local area network as defined by the IEEE 802.3 standard. The standard is based on the access method known as carrier-sense multiple access with collision detect (CSMA/CD). The operational principle is such that if a network node wants to transmit, it first listens to the network for other transmitted traffic. If the medium is quiet the network controller will begin transmission while monitoring for a possible collision with another transmitter. If two or more stations should simultaneously transmit, they will detect the collision and back off for a random amount of time before making another attempt.

The physical layer of Ethernet may be implemented in two forms according to the performance required from the system. Thick wire Ethernet (referenced as 10BASE5) uses high specification coaxial cable which is connected to the network node via a transceiver unit (Medium Attachment Unit, MAU) and drop cable

(Attachment Unit Interface, AUI). The AUI cable consists of four individually shielded twisted pairs fitted with D15 connectors.

Thin wire Ethernet or Cheapernet (referenced as 10BASE2) uses a more flexible coaxial cable with BNC connectors. The

SETHER board supports interfaces for both Cheapernet and a

D15 AUI cable connector for connection to standard Ethernet.

A comparison of performance characteristics is shown below:-

Parameter

Data Rate

Segment Length

Network Span

Nodes per Segment

Node Spacing

Cable Type

Ethernet

10 Mbits

500m

2500m

100

2.5m (cable marked)

Belden 9880

50

Double Shielded

Rugged

N Series Connectors

Cheapernet

10 Mbits

185m

925m

30

0.5m

Cheapernet

50

(RG58A/U)

Single Shielded

Flexible

BNC Connectors

Transceiver Drop Cable Belden 9892 multi-way cable with D15 connectors (max drop length 50m)

Not needed due to high flexibility of RG59A/U cable

Arcom Control Systems Ltd

Section 2. Ethernet (IEEE 802.3) J193 SETHER

Each Ethernet board has a unique 6 byte identifying code

(stored in PROM and referred to as the burned in address) which is issued by the IEEE. This identifier is used to indicate the source and the destination of packets transferred on the network, the Arcom burned in addresses start at 008066000001

Ethernet Packet Structure

The structure of an Ethernet packet is as follows:

6 bytes destination address

6 bytes

2 bytes source address type/length field

46-1500 bytes user data

If the destination address has all bits set, the packet is broadcast and will be received by all nodes that have broadcast reception enabled.

The source address is normally the sender’s Burned In Address, copied from the on-board PROM into the 8390 chip. This ensures that every Ethernet card has a unique identity, no matter how large the network.

The type/length field is used by some protocols to indicate packet length, in others it serves as an identifier of the protocol used e.g 0806H for ARP, 0800H for IP. When creating a new protocol, it is advisable to choose a unique value for this field, to try to avoid clashes with other protocols. In accordance with

Ethernet standards, this field is in high-low byte order.

The user data may be in any format, and will be passed across the network unaltered. If it is less than 46 bytes long, it must be padded with dummy bytes.

The hardware performs automatic CRC generation and checking, this operation is transparent to the programmer.

To transmit the packet, it is placed at the base of the SETHER dual-port RAM, and a transmit command is sent to the 8390

Ethernet chip. The 8390 will then put the packet onto the network. The 8390 returns error codes if it is unable to send the packet (e.g. the retry limit has been exceeded). There is no built-in mechanism for checking whether the packet has arrived at its destination: the higher-level protocols are responsible for ensuring an acknowledgement is returned.

When receive has been enabled, the 8390 will automatically stack up incoming packets in the dual-port RAM without any processor intervention. The 8390 treats the RAM area as a

Arcom Control Systems Ltd Page 5

J193 SETHER Section 2. Ethernet (IEEE 802.3)

circular buffer, and will only cease reception if the buffer is full.

The format of the received packet is as described above, but with a 4-byte hardware header:-

1 byte packet status

1 byte

2 bytes next hardware page packet length

The status byte mirrors the Receive Status Register at the time of reception: if bit 0 is set, the packet is error-free.

The ’next hardware page’ refers to the next 256-byte block of dual-port RAM used by the 8390.

The packet length is in low-high byte order, and includes the length of the 4-byte hardware header.

A simple Ethernet monitor program written in Aztec ’C’ has been included in Appendix D of this manual. It uses ’promiscuous mode’ which means that all network packets are received, irrespective of destination address. This mode is useful for network diagnosis, though it will result in a very high data throughput if used on a heavily-loaded network.

Page 6 Arcom Control Systems Ltd

Section 3. Hardware Installation J193 SETHER

Section 3. Hardware Installation

Storage and Handling

The SETHER is supplied in static protective packing. It is important that normal precautions against static should be observed at all times.

The boards should always be kept in dry conditions at a controlled temperature.

Under the terms of Arcom’s warranty, any boards returned with damage attributed to incorrect handling or storage will not be repaired, nor replaced free of charge.

See also the specifications in Appendix C.

Links and Options

This section describes how to set the link defined features. The link positions are shown below. ’+’ indicates a standard setting.

Note that all, links are viewed with the pcb edge connector to the right

Link Position Diagram

LK15

LK17

LK14

A

B

C

D

E

F

LK12

C

B

A

G

F

E

D

LK3

LK16

A

B

LK1

A

B

LK13

LK8

LK11

LK10

A

B

LK9

A

B

LK4

A

B

LK2

A

B

LK7

LK5

LK6

A B C D E F G H

A

B

C

D

E

F

= Default Link Position

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J193 SETHER

Page 8

Section 3. Hardware Installation

Links 1 and 16. RAM buffer size select.

+

LK1

B

A

LK16

A

B

8K RAM

32K RAM

Links 2 and 4. ROM decode size select.

+

LK2

A

A

B

B

LK4

A

A

A

B

2764

27128

27256

27512

Link 3. RAM base address A19

(8k)

(16k)

(32k)

(64k)

LK3 Insert to respond if A19 low

The RAM can appear at any multiple of its size in STEbus memory space. A18-13 are software programmable, but this link defines A19.

On reset the base address is set to80000H and the RAM is disabled

By default the software will generally set the RAM base-address to be D0000H and RAM will be enabled.

Link 5. ATNRQ select.

+

LK5A Interrupt on ATNRQ0*

LK5B Interrupt on ATNRQ1*

LK5C Interrupt on ATNRQ2*

LK5D Interrupt on ATNRQ3*

LK5E Interrupt on ATNRQ4*

LK5F Interrupt on ATNRQ5*

LK5G Interrupt on ATNRQ6*

LK5H Interrupt on ATNRQ7*

Link 6. ROM socket base address.

+

+

LK6A Respond if A14 low

LK6B Respond if A15 low

LK6C Respond if A16 low

LK6D Respond if A17 low

LK6E Respond if A18 low

LK6F Respond if A19 low

The ROM can be mapped to any 16K boundary.The default link settings map the ROM at address D8000H

Arcom Control Systems Ltd

Section 3. Hardware Installation J193 SETHER

Link 7. Disable ROM space.

+ LK7 Insert to disable ROM.

Link 8. Ethernet ’burned in address’ PROM high/low select

+ LK 8 Omit to select the top half of the Ethernet

’burned in address’ PROM

Note:

This link should be inserted to make the boards compatible with the standard drivers supplied on the distribution disk.

Link 9 and 10. ROM device size select.

+

LK 9 LK 10

B B

B

B

B

A

A A

2764 (8k)

27128 (16k)

27258 (32k)

27512 (64k)

Link 11. RAM device size select.

+ LK 11 Insert for 62256 (32k), Omit for 6264 (8k)

Link area 12. I/O base address

+

+

+

LK12A Respond if A5 low

LK12B Respond if A6 low

LK12C Respond if A7 low

LK12D Respond if A8 low

LK12E Respond if A9 low

LK12F Respond if A10 low

LK12G Respond if A11 low

+

+

The I/O address can be mapped to any 32-byte boundary of the

STEbus I/O space (000 to FE0). Inserting a link in this area sets the corresponding register base address bit low. The default link settings map the I/O at address 280H.

Link 13. Connect +12V to AUI cable.

LK13 Insert to connect +12v to an external transceiver unit (MAU).

Link 14. Enable Thin Wire Ethernet Transceiver Interface.

+

+

+

+

+

+

LK 14A

LK 14B

LK 14C

LK 14D

LK 14E

LK 14F

TX+

TX-

RX+

RX-

CD-

CD+

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J193 SETHER Section 3. Hardware Installation

These links transfer the outputs from the Serial Network Interface chip DP8391 to the isolation transformer and on to the

Coaxial Transceiver Interface, DP8392. If the D15 connector is used to drive an external thick/thin wire transceiver unit, all

LK14 links should be removed.

Link 15. Network Segment Length Option.

+ LK15 Insert for standard IEEE 802.3 networks.

Omit for extended segment lengths.

Each standard Ethernet segment has a maximum length of

185m. If it is necessary to expand this up to 300m, then Link 15 should be inserted.

IMPORTANT : If this option is selected then the network is

limited to a single segment, ie no repeaters may be used and also all other SETHER cards on the segment must be set with

Link 15 made. This configuration does not comply with the electrical specification of IEEE 802.3.

The state of Link 15 is only relevant if Thin Wire Ethernet is used, ie all Link area 14 are made.

Link 17. Network Version Select.

Omit for Ethernet Version 2, IEEE 802.3 networks,

Cheapernet.

Insert for older version 1 networks.The network version is determined by the MAU transceiver used for the network. (This will be indicated on the MAU).

Installation

It is important to follow normal good practice associated with the installation and removal of boards from the backplane. Make sure all power to the backplane is off. Follow standard anti-static precautions, including earthed wrist straps and conductive carpets, when installing the board. If in doubt, consult your

supplier.

Network Cabling and Connectors

Page 10

Thin-wire Ethernet (Cheapernet) requires RG58A/U co-axial

cable and 50 Ohm BNC connectors. Each BNC connector should be fitted with a BNC ’T’ piece such that the network cabling can continue to the next node. If the SETHER board is the last node in the network chain, one side of the ’T’ piece should be fitted with a 50 ohm terminator. (The network will not work without terminations fitted at both ends.) A few important parameters should be noted :-

Arcom Control Systems Ltd

Section 3. Hardware Installation J193 SETHER

Minimum separation between nodes

Minimum bend radius of cable

Maximum length of any one segment

500mm

30mm

185m

Maximum number of nodes per segment 30

IMPORTANT NOTE: the network cable screen is independent

from chassis ground, and that ALL CONNECTORS, BULK-

HEAD or LINE, MUST BE ISOLATED FROM CHASSIS

GROUND. Failure to observe this requirement may result in loss of noise immunity. Also the BNC ’T’ pieces should be connected directly onto the SETHER board BNC connector, ie do not use any drop cable between these two.

Thick-wire Ethernet uses special multi-wire co-axial Ethernet

cable, and can be up to 500m long. The SETHER board should be connected to a transceiver unit via a multiple twisted pair (78 ohm impedance) drop cable (such as Belden 9892 or similar) fitted with D15 connectors.This cable should be a maximum of

50m long. The network should also be terminated with 50 ohm terminators

Arcom Control Systems Ltd Page 11

J193 SETHER User Configuration Record Sheet

User Configuration Record Sheet

This sheet may be duplicated.

Page 12 Arcom Control Systems Ltd

Section 4. Circuit Description J193 SETHER

Section 4. Circuit Description

Arcom Control Systems Ltd

The core of the SETHER is the DP8390 Network Interface Chip

(IC20) which handles all the media access control to the Ethernet. The NIC interchanges packets of information via dual port memory (IC14) using an on chip DMA controller.

The SETHER also includes 28 pin EPROM socket (IC9) for network BIOS software, a PROM socket (IC11) for the Ethernet

’burned in address’ and a control register (IC7). The control register is used to set the base address of the RAM buffer, control the local reset and enable or disable the RAM (bit assignments shown below).

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SETHER board reset (high)

RAM Enabled (high)

A18

A17

A16

A15

A14

A13

The base addresses for the I/O registers and EPROM space are decoded by 74HCT688’s (IC21 and IC6 respectively) and

Link areas 12 and 6. A part of the RAM buffer base address

(A18-A13) is selected by the value written to the control register

(and compared by IC4). Bit A19is selected by LK3. Bit 7 of the control register serves as a software invoked reset. The board is reset when this bit is set high, this board reset will also clear the control register thus removing the local reset. Bit 6 is used to enable access (when high) to the RAM from the STEbus.

Access to the EPROM, PROM and control register is independent of NIC accesses to dual port memory. The RAM is double buffered and is accessed under the control of the dual port arbiter.

The arbitration is performed by the 16R4 PAL (IC18) and is programmed to give priority to the NIC in preference to a

STEbus access. Access to the I/O registers with in the NIC are arbitrated by the NIC, ie when /CS and /SRD or /SWR are asserted the control circuit will wait for an /ACK to be asserted by the NIC. At this time the data buffers from STEbus to the NIC are enabled and the STEbus access is terminated.

Device decodes, strobe signals and STEbus /DATACK are generated by the 22V10 PAL (IC10) and 16L8 PAL (IC12). These also use the arbitration signals /STE GNT and NIC GNT to enable the appropriate buffers and direction controls. STEbus

/DATACK is driven by NMOS FET TR1.

Page 13

J193 SETHER

Page 14

Section 4. Circuit Description

The EPROM base address is set by Link area 6 and compared with the STEbus address lines using IC6. Similarly the I/O base address (PROM, control reg. and NIC registers) is selected by

Link area 12 and IC 21. The base address of RAM set in the control register is compared by IC4.

The ’burned in address’ PROM, 74S288 (IC11) is a 32byte one time programmable device which is programmed by ARCOM with a valid IEEE Ethernet address. This information is mapped twice into the 16 bytes above the I/O base address. Only the higher image should be used (ie I/O base +08H to I/O base

+0FH) for compatibility with comparable PC-bus boards.

The format of the ’burned in address’ is shown by the following

I/O register map :

B

C

D

E

F

10 - 1F

Offset

0

1-7

8

9

A

Write

Board Control Register

Read

Do Not Use

Do Not Use

Burned in address byte

0

Burned in address byte

1

Burned in address byte

2

Burned in address byte

3

Burned in address byte

4

Burned in address byte

5

Type Byte

Checksum Byte

8390 Controller

Registers

The DP8390 NIC and DP8391 SNI both require a 20MHz clock input to drive the 10 Mbits/s Ethernet transmission. The clock has a high specification in order to comply with the IEEE 802.3

limit of 0.01% absolute accuracy. The tolerance must be +-

0.001% @ 25deg.C with a stability of +-0.005% in the range

0-70 deg.C. This is achieved by using the crystal module, XL1.

The 8391 SNI provides the Manchester data encoding and decoding for the IEEE802.3 Ethernet. The device includes the differential Tx data line drivers (with 270R pull-down resistors on the outputs, R1, R4) and differential line receivers for the Rx and collision detect (CD) signals. These input lines must be terminated if used with the standard 78 ohm AUI cable with 78 ohm loads. This is provided by two 39R resistors in series which are then by-passed to GND.

Arcom Control Systems Ltd

Section 4. Circuit Description J193 SETHER

The AUI cable output can be used to power the external MAU transceiver unit. This +12v (@ 300mA typ.) supply is connected if Link 13 is made.

The two LED’s are useful for monitoring Ethernet traffic through the board. LED1 (red) and LED2 (green) indicate activity on the

Tx and Rx data lines respectively. The RxD and TxD lines of the

NIC are connected to two pulse stretching monostables (IC24) configured from four high drive current nand gates.

In order to satisfy the IEEE 802.3 specification for Cheapernet, the 8392 Coaxial Transceiver Interface must be fully isolated from the main Ethernet interface. This is achieved using pulse transformers (T1) to connect the signal lines (CD,Tx and Tx) and a DC/DC converter (IC15) to provide the isolated -9v supply.

This device is a 2W, +5V to -9V converter.

Functional Block Diagram

DP8390

Network

Controller

PL1

PL2

DP8391

Ethernet

Interface

Arbiter and controller for local RAM

Isolation

Transformer

DP8392

Thin

Ethernet

Transceiver

8K/32K

RAM

Buffer

D0-7

Identity

PROM

BIOS

EPROM

A0-19

Buffer

STEbus slave interface

ATNRQ0-7

Arcom Control Systems Ltd Page 15

J193 SETHER Section 5. Troubleshooting

Section 5. Troubleshooting

Board does not appear in memory or appears at the wrong address

Interrupts do not work correctly

Network will not configure

Network configures but board does not appear on the network

Check address jumpers

LK 12 locates the I/O block

LK 3 defines the 8K RAM A19

LK6,7 locates the 8K ROM socket

LK2 ,4,9,10 defines the ROM size

Ensure that the correct RAM base address has been written to the control register. When setting the address jumpers :-

Install a jumper for a zero address bit

Remove a jumper for a one address bit

Check that the interrupt links are correctly set, note that

SETHER does not support vectored interrupts.

1. Check that at least one other node is connected to the network and it is switched on.

2. Check that the network cabling is not faulty.

3. Check that 50

terminators are fitted at both ends of the network.

Check that the node ID is correctly set .The identify PROM -

IC11 can be read in I/O SPACE.

Page 16 Arcom Control Systems Ltd

Appendix A. Component List

IC1,16

IC2,5,8,13,19,24

IC3

IC7

IC6,4,21

IC12

IC10

IC9

IC11

IC18

IC14

IC15

IC20

IC24

IC22

IC17

IC23

TR1,2

D1

LED1

LED2

R6,15

R14

R13

R17

R16

R7,8,10,11

R2

R1,4

RP1-4

R3,5,9,12

C1,2,9,14,18

C3-8,10-13,15,17,19,

21-25,29

C12

C20,26,27,28

C16

T1

XL1

J193 SETHER

Appendix A. Component List

ACT245

HCT244

HCT14

HCT273

HCT688 Comparators

PAL16L8

PAL22V10 DATACK functions

BIOS ROM Socket

74S288 Ethernet Identity PROM

PAL16R4

6264/55257 8K/32K RAM (32K fitted as standard)

NMB0509 +5V to -9V DC-DC converter

DP8390 Ethernet Network Interface Controller

ACT00

DP8391 Ethernet Serial Network Interface

ACT373

DP8392 Ethernet Co-axial Transceiver Interface

(for thin-wire networks)

2N7000 N-channel Enhancement MOSFET

1N4148

0.1 inch Red LED

0.1 inch Green LED

820K

10k

330R

130R

1M0

39R

1k0

270R

4k7 C SIL

510R

22

µ

F 16V Tantalum

100nF 25V Ceramic

47

µ

F 16V Aluminium

10nF 25V Ceramic

10nF 1kV Ceramic

Quad 1:1 DIL-package isolation transformers

20MHz Oscillator Module

Arcom Control Systems Ltd Page 17

J193 SETHER Appendix B. STE Bus Connections

Appendix B. STE Bus Connections

PL1 is the 64-way STEbus connector.

Pin Row A Row C

1 GND

2 +5V

3

4

D0

D2

5 D4

6

7

D6

A0

GND

+5V

D1

D3

D5

D7

GND

8 A2

9 A4

A1

A3

10 A6

11

A5

A8 A7

12 A10

13 A12

14

15

A14

A16

A9

A11

A13

A15

16

17

A18

CMO

A17

A19

18 CM2

19

CM1

ADRSTB* GND

22 ATNRQ0*

23

SYSRST*

ATNRQ2* ATNRQ1*

25

26

27

28

ATNRQ6*

GND

ATNRQ5*

ATNRQ7*

BUSRQ0* BUSRQ1*

BUSAK0* BUSAK1*

30 -12V +12V

31 +5V +5V

32 GND GND

Page 18 Arcom Control Systems Ltd

Appendix C. Specification J193 SETHER

Appendix C. Specification

Operating temperature 5°C to 55°C

Power consumption +5v 1.0A (typical)

+12v (depends on the MAU transceiver)

Bus

I/O

Memory

STEbus

32 bytes

8K/32K RAM packet buffer

8K/16K/32K/64K BIOS extension EPROM

Recommended EPROM type: 27128

Maximum access time: 250ns

Interrupts ATNRQ0-7*, no bus-vectored acknowledge

Arcom Control Systems Ltd Page 19

J193 SETHER Appendix D. Example Program

Appendix D. Example Program

/* SETHMON.C: Simple Ethernet Monitor JPB 9/8/91

This utility takes in packets from the network and displays them.

Written in Aztec/Borland C (small model), low-level drivers in ETHER.C

For use on an Arcom PC with SETHER card.

Compile & link using:

Aztec: c sethmon.c ether.c

Borland: bcc sethmon.c ether.c

To use on a target system, replace ’while(!kbhit())’ with ’while (1)’, and

link in the standard target files.

Copyright (c) Arcom Control Systems Ltd 1991 */

#define ADRLEN 6

#define MAXDATA 1500

/* No of bytes in ethernet address */

/* Maximum Ethernet data size */

/* Data type definitions */ typedef unsigned long typedef unsigned short typedef unsigned char uint32; uint16; uint8;

/* 32-bit unsigned */

/* 16-bit unsigned */

/* 8-bit unsigned */

/* Data structures */ struct dlinkh { /* Datalink (Ethernet) header */ uint8 dadr[ADRLEN], /* Destination Enet addr */ sadr[ADRLEN]; /* Source Enet addr */ uint16 type; /* Enet packet type/length field */

}; typedef struct dlinkh DHEAD;

/* MOST SIGNIFICANT BYTE IS FIRST! */ struct dlinkp {

DHEAD d;

/* Datalink (Ethernet) packet */

/* Datalink header */ uint8 data[MAXDATA]; /* Data area */

}; typedef struct dlinkp DPKT;

DPKT rxd; /* Rx datalink packet buffer */ extern int promisc; /* Promiscuous physical addr flag */ extern unsigned char myeth[]; /* My ether addr (from ROM) */

/* Prototypes */ void swap(uint16 *p); void pr6byt(uint8 *str); void hexdump(uint8 *buff, int len); int getpack(void *buff); void main() {

uint16 type, len;

printf("Simple Ethernet Monitor\n");

promisc = 1; /* Enable promiscuous mode */

Page 20 Arcom Control Systems Ltd

Appendix D. Example Program J193 SETHER

if (! etinit()) { /* Initialise hardware */ printf("ERROR: can’t access Ethernet card\n"); exit(0); }

printf("My Ethernet address is "); /* Print Burned In Addr */

pr6byt(myeth);

printf("\nWaiting for packet... press any key to exit\n");

while (!kbhit()) { if ((len = getpack(&rxd))0) {

/* Loop until key hit */

/* If packet recd.. */

printf("From "); pr6byt(rxd.d.sadr); /* Print header */

printf(" to "); pr6byt(rxd.d.dadr);

type = rxd.d.type; swap(&type); /* Byte-swap type.. */

printf(" type/len %04X hex\n", type); /* ..before printing */

hexdump(rxd.data, len-sizeof(DHEAD)); /* Dump rest of packet */

}

}

} void swap(p) /* Swap bytes in int */ uint16 *p; {

uint8 c, *q;

q = (uint8 *)p;

c = *q; *q = *(q+1); *(q+1) = c;

} void pr6byt(str) /* Print a 6-byte ethernet address */ uint8 *str; {

int i;

if (*(str+5) == 0xff) { printf("----BROADCAST----"); return; }

printf("%02x", *str++);

for (i=1; i<ADRLEN; i++) printf(":%02x", *str++);

}

#ifndef __BORLANDC__ kbhit() {

/* Return true if key hit */

return(bdos(0xb, 0, 0));

}

#endif void hexdump(buff,len) /* Print hex dump of buffer */ uint8 *buff; int len; {

int i, j, m, n;

uint8 c, str[17];

n = len/16;

for (i=0; i<=n; i++) { if (len>0) {

printf(" %04x: ", i*16);

for (j=0; j<16; j++) { if (len>0) {

if (j==8) printf(" ");

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J193 SETHER Appendix D. Example Program

printf("%02x ", c=buff[i*16+j]);

str[j] = (c>=’ ’ && c<=’~’) ? c : ’.’; } else {

printf(" "); str[j] = 0; } len--; }

str[j] = 0; printf(" %s\n", str); }

}

}

Page 22 Arcom Control Systems Ltd

Appendix D. Example Program

/* SETHER/WD8003E/WD8003EB Ethernet hardware drivers JPB 9/8/91 */

/* Suitable for Aztec or Borland ’C’ compilers (small model) */

/* Copyright (c) Arcom Control Systems Ltd. 1991 */

J193 SETHER

#include "ETHER.H"

#define IOBASE 0x280 /* I/O base address for Ethernet card */

#define RSEG 0xd000 /* Segment for dual-port RAM buffer */

#ifdef __BORLANDC__ /* If Borland ’C’... */

/* ..all segments and offsets in opposite order to Aztec! */ unsigned char peekb(unsigned seg, unsigned off);

#define peekb_(off,seg) peekb(seg,off)

#define peekw_(off,seg) peek(seg,off)

#define movblock(o1,s1,o2,s2,len) movedata(s1,o1,s2,o2,len)

#define _dsval _DS

#else

#define peekb_ peekb

/* If Aztec ’C’... */

#define peekw_ peekw extern int _dsval; /* Data seg value from linker */

#endif

#define MAXPACK 1514 /* Maximum packet size (excl hardware bytes) */

#define MINPACK 60 /* Minimum packet size */ unsigned char myeth[6]; /* My Ethernet addr (from ROM) */ int promisc=0; /* Flag to enable promiscuous mode */

/* Prototypes */ void etopen(unsigned char s[], unsigned addr); int getpack(unsigned char buff[]); int putpack(unsigned char pack[], unsigned len); int egetb(int port); void eputb(int port, int byt); void rpage(int n); int wrapp(int page); int etinit() { /* Initialise card, return 0 if error */

int i, sum=0;

for (i=0; i; i++) /* Get 6 byte h/ware addr.. */

sum += (myeth[i] = egetb(AROM+i)); /* ..keeping sum of bytes */

sum += egetb(AROM+6); /* Add on 7th, 8th bytes */

sum += egetb(AROM+7);

if ((sum & 0xff) != 0xff) return(0); /* ..total should be FF */ eputb(W83CREG, MSK_RESET); /* Reset card */

eputb(W83CREG, 0);

etopen(myeth, RSEG); /* Set up card */

return(1); }

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J193 SETHER Appendix D. Example Program

void etopen(s, addr) /* Set up hardware */ unsigned char s[]; /* Ethernet addr */ unsigned addr; /* Mem addr */

{

int i;

eputb(W83CREG, addr>9); /* Set dual-port RAM addr */

rpage(0); /* Reg page 0, abort remote DMA */

eputb(DCR, 0x48); /* FIFO 8 bytes, no loopback */

eputb(RBCR0,0); eputb(RBCR1,0); /* Clear remote byte count */

eputb(RCRW, 0x20); /* Monitor mode */

eputb(TCR, 0);

eputb(PSTOP,STOP_PG); eputb(PSTART,STRT_PG); /* Mem stop, start */

eputb(BNRY, STRT_PG); /* Mem boundary */

eputb(ISR, -1); eputb(IMR,0); /* Clear & mask all interrupts */

rpage(1); /* Reg page 1 */

for (i=0; i; i++) eputb(PAR0+i, s[i]); /* Set Phys addr */

for (i=0; i; i++) eputb(MAR0+i, 0); /* Set Mcast addr to 0 */

eputb(CURR, STRT_PG+1); /* Current page = start+1 */

rpage(0); eputb(CMDR, 0x22); /* Reg page 0, start 8390 */

eputb(RCRW, promisc ? 0x14 : 0x04);/* Accept Bcast, also promiscuous? */

}

/* Get packet into buffer, return length (0 if none received) */ getpack(buff) /* Length includes dest addr, srce addr, type */ unsigned char buff[]; {

unsigned curr, bdry, raddr;

unsigned stat, plen, p1, p2;

rpage(1); curr = egetb(CURR); /* Page after the incoming data */

rpage(0); bdry = egetb(BNRY); /* Page of data already read */

bdry = wrapp(bdry+1); /* Move up to unread page */

if (curr == bdry) return(0); /* Return 0 if nothing received */

raddr = bdry<8; /* Calculate addr of unread page */

stat = peekb_(raddr, RSEG); /* Get status and length of packet */

plen = peekw_(raddr+2,RSEG)-HWB; /* Deduct 4 hardware bytes from len */

if (!(stat & 1) || plenMAXPACK) /* If error in packet, ignore it */

plen = 0;

else {

/* No error in packet, copy it */

if (plen+raddr STOP_RAM) { /* If packet wraps around end of RAM */

p1 = STOP_RAM-raddr-HWB; /* ..copy it in 2 parts */

p2 = plen - p1; /* Only 1st part has hardware bytes */ movblock(raddr+HWB, RSEG, buff, _dsval, p1);

movblock(STRT_RAM, RSEG, buff+p1, _dsval, p2); }

else { /* If no wrap, copy whole packet */

movblock(raddr+HWB, RSEG, buff, _dsval, plen); }

}

bdry = wrapp(peekb_(raddr+1,RSEG)-1); /* Move pointer to next packet */

eputb(BNRY, bdry);

return(plen); } /* Return packet length, or 0 */

Page 24 Arcom Control Systems Ltd

Appendix D. Example Program J193 SETHER

putpack(pack, len) /* Send Ethernet packet, return 0 if error */ unsigned char pack[]; /* See above for packet format */ unsigned len; { /* Length includes dest addr, srce addr, type */

unsigned timout = 60000; /* Arbitrary timout value */

while(egetb(CMDR) & 4) /* Ensure transmitter is idle */

if (! timout--) return(0); /* ..return 0 if timout */

if (len>MAXPACK) return(0); /* Error if packet too long */

movblock(pack, _dsval, 0, RSEG, len); /* Copy packet into RAM page 0 */

if (len<MINPACK) len = MINPACK; /* Must be = >60 bytes */

eputb(TBCR0, len); eputb(TBCR1, len>>8);/* Set length regs */

eputb(TPSR, 0); /* Select transmit page 0 */

eputb(CMDR, 0x24); /* Transmit */

return(len); } egetb(port) { /* Read byte from card register */

return(inportb(IOBASE+port)); } void eputb(port,byt) { /* Write byte to card register */

outportb(IOBASE+port,byt); } void rpage(n) { /* Select 8390 register page */

outportb(CMDR+IOBASE, (n<6)+0x20); } /* Abort remote DMA */ wrapp(page) /* Return a wrapped value of Rx memory page */ int page; {

if (page = >STOP_PG) return(STRT_PG); /* Wrap if overflow */

if (page < STRT_PG) return(STOP_PG-1); /* Wrap if underflow */

return(page); }

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J193 SETHER Appendix D. Example Program

/* Equates for SETHER/WD8003E/WD8003EB Ethernet cards JPB 23/6/90 */

/* Copyright (c) Arcom Control Systems Ltd. 1990 */

/* SETHER/8003E/8003EB control register operations */

#define W83CREG 0 /* Control reg offset from base */

#define MSK_RESET 0x80 /* Control bit to reset LAN controller */

#define MSK_ENASH

#define MSK_DECOD

0x40

0x3Fh

/* Control bit to enable shared mem */

/* Bits to set mem address lines A18-A13 */

/* Address line A19 assumed to be 1 */

/* On-board Ethernet address ROM */

#define AROM 8 /* ROM offset from I/O base addr */

/* To keep compatibility with all 3 boards, do not use ROM image at base+0 */

/* 8390 LAN Controller (page0) register offset for read and write */

#define CMDR 0x10 /* command register for read & write */

#define CLDA0 0x11

#define PSTART 0x11

/* current local dma addr 0 for read */

/* page start register for write */

#define CLDA1 0x12

#define PSTOP 0x12

#define BNRY 0x13

/* current local dma addr 1 for read */

/* page stop register for write */

/* boundary reg for rd and wr */

#define TSR

#define TPSR

0x14

0x14

#define NCR 0x15

#define TBCR0 0x15

#define FIFO 0x16

#define TBCR1 0x16

#define ISR 0x17

#define CRDA0 0x18

#define RSAR0 0x18

#define CRDA1 0x19

#define RSAR1 0x19

#define RBCR0 0x1A

#define RBCR1 0x1B

/* tx status reg for rd */

/* tx start page start reg for wr */

/* number of collision reg for rd */

/* tx byte count 0 reg for wr */

/* FIFO for rd */

/* tx byte count 1 reg for wr */

/* interrupt status reg for rd and wr */

/* current remote dma address 0 for rd */

/* remote start address reg 0 for wr */

/* current remote dma address 1 for rd */

/* remote start address reg 1 for wr */

/* remote byte count reg 0 for wr */

/* remote byte count reg 1 for wr */

#define RSR

#define RCRW

0x1C

0x1C

#define CNTR0 0x1D

#define TCR 0x1D

#define CNTR1 0x1E

#define DCR 0x1E

#define CNTR2 0x1F

#define IMR 0x1F

/* rx status reg for rd */

/* rx configuration reg for wr */

/* tally cnt 0 for frm alg err for rd */

/* tx configuration reg for wr */

/* tally cnt 1 for crc err for rd */

/* data configuration reg for wr */

/* tally cnt 2 for missed pkt for rd */

/* interrupt mask reg for wr */

/* 8390 LAN Controller (page1) register offset for read and write */

#define PAR0 0x11 /* physical addr reg 0 for rd and wr */

#define CURR

#define MAR0

0x17

0x18

/* current page reg for rd and wr */

/* multicast addr reg 0 for rd and WR */

Page 26 Arcom Control Systems Ltd

Appendix D. Example Program J193 SETHER

/* Buffer Length and Field Definition Info */

#define HWB 4 /* Number of bytes in hardware header */

#define STRT_PG 6 /* Receive buffer start page */

#define STOP_PG 32 /* Receive buffer end page */

#define STRT_RAM (STRT_PG<8) /* Receive buffer start addr */

#define STOP_RAM (STOP_PG<8) /* Receive buffer end addr */

Arcom Control Systems Ltd Page 27

J193 SETHER Appendix E. AUI Connector Pin Assignments

Appendix E. AUI Connector Pin Assignments

PL2. AUI Connector n/c 15

GND

14

+12V 13

RX12

GND 11

TX10

CD9

PL2. AUI Connector

6

5

8

7

4

3

2

1

GND n/c

GND

RX+

GND

TX+

CD+

GND

PL3. BNC

Page 28 Arcom Control Systems Ltd

Appendix E. Circuit Diagrams J193 SETHER

Appendix E. Circuit Diagrams

Arcom Control Systems Ltd Page 29

J193 SETHER Appendix E. Circuit Diagrams

Page 30 Arcom Control Systems Ltd

Appendix E. Circuit Diagrams J193 SETHER

Arcom Control Systems Ltd Page 31

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