MSC
EXM32-Au1250
CPU-Module
User's Manual
Revision 1.0
Hardware Revision V5.0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Preface
Copyright Notice
Copyright © 2008 MSC Vertriebs GmbH. All rights reserved.
Copying of this document, and giving it to others and the use or communication of the
contents thereof, are forbidden without express authority. Offenders are liable to the payment
of damages.
All rights are reserved in the event of the grant of a patent or the registration of a utility model
or design.
Important Information
This documentation is intended for qualified audience only. The product described herein is
not an end user product. It was developed and manufactured for further processing by trained
personnel.
Disclaimer
Although this document has been generated with the utmost care no warranty or liability for
correctness or suitability for any particular purpose is implied. The information in this
document is provided “as is”and is subject to change without notice.
EMC Rules
This unit has to be installed in a shielded housing. If not installed in a properly shielded
enclosure, and used in accordance with the instruction manual, this product may cause radio
interference in which case the user may be required to take adequate measures at his or her
own expense.
Trademarks
All used product names, logos or trademarks are property of their respective owners.
Certification
MSC Vertriebs GmbH is certified according to DIN EN ISO 9001:2000 standards.
Life-Cycle-Management
MSC products are developed and manufactured according to high quality standards. Our lifecycle-management assures long term availability through permanent product maintenance.
Technically necessary changes and improvements are introduced if applicable. A productchange-notification and end-of-life management process assures early information of our
customers.
Product Support
MSC engineers and technicians are committed to provide support to our customers whenever
needed.
Before contacting Technical Support of MSC Vertriebs GmbH, please consult the respective
pages on our web site at www.msc-ge.com/support-boards for the latest documentation,
drivers and software downloads.
If the information provided there does not solve your problem, please contact our Technical
Support:
Email: support.boards@msc-ge.com
Phone: +49 8165 906-200
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Contents
Contents ...............................................................................................................................................3
Document change history......................................................................................................................4
1 General Information .......................................................................................................................5
1.1
Introduction ..........................................................................................................................5
1.2
Functional Blocks .................................................................................................................6
1.2.1
Block Diagram.................................................................................................................7
2 Overview .......................................................................................................................................8
2.1
Connectors...........................................................................................................................8
2.2
Specification.........................................................................................................................8
2.3
Mechanical Dimensions........................................................................................................9
2.4
Connector Positions .............................................................................................................9
3 Interfaces..................................................................................................................................... 10
3.1
Connectors.........................................................................................................................10
3.1.1
EXM32 Connector Pin Definition ....................................................................................10
3.1.2
Connector X1 (CPU Bus, Compact Flash, SPI, AC’
97/I²S, PCI-E)................................... 11
Connector X2 (Interfaces) ............................................................................................................12
3.2
Connector X1 .....................................................................................................................13
3.3
Connector X2 .....................................................................................................................17
3.4
Debug Connector ...............................................................................................................23
4 Hardware Description................................................................................................................... 24
4.1
Functional Blocks ...............................................................................................................24
4.1.1
CPU...............................................................................................................................24
4.1.2
MMC/SD/SDIO...............................................................................................................25
4.1.3
PC-Card/Compact Flash Interface..................................................................................25
4.1.4
Linear Flash ...................................................................................................................26
4.1.5
NAND-Flash................................................................................................................... 26
4.1.6
DDR2-SDRAM ...............................................................................................................26
4.1.7
Ethernet .........................................................................................................................26
4.1.8
USB ...............................................................................................................................26
4.1.9
Graphics Controller ........................................................................................................27
4.1.10 Camera Interface ...........................................................................................................29
4.1.11 GPIO-/( LCD2) Interface (V0.5 Update) ..........................................................................30
4.1.12 CAN Bus........................................................................................................................31
4.1.13 Serial Communication Interfaces (COM0,COM1)............................................................32
4.1.14 SPI-Interface..................................................................................................................38
4.1.15 I²C-Interface...................................................................................................................41
4.1.16 Audio Codec Interface (AC’
97/I²S/LJ/RJ)........................................................................ 45
4.2
Power Management ...........................................................................................................47
4.3
Data Bus ............................................................................................................................48
4.3.1
16-Bit (standard) ............................................................................................................48
4.3.2
16-write timing................................................................................................................50
4.3.3
32-Bit (optional).............................................................................................................. 51
4.4
Power Supply .....................................................................................................................54
5 FPGA........................................................................................................................................... 55
5.1
FPGA Register Description.................................................................................................56
5.1.1
BRDREV Board Revision Register (Offset 0x00) ............................................................ 57
5.1.2
BRDSTAT Board Status Register (Offset 0x04).............................................................. 58
5.1.3
BRDCTRL Board Control Register (Offset 0x08) ............................................................ 59
5.1.4
LEDCTRL LED Control Register (Offset 0x0C)............................................................... 60
5.1.5
LCDCTRL LCD Control Register (Offset 0x10) ............................................................... 61
5.1.6
CFCTRL Compact Flash Control Register (Offset 0x14) ................................................. 62
5.1.7
PDCTRL Peripheral Devices Control Register (Offset 0x18) ........................................... 63
5.1.8
IRQSETEN IRQ Set Enable Register (Offset 0x20) ........................................................ 64
5.1.9
IRQCLREN IRQ Clear Enable Register (Offset 0x24) ..................................................... 65
5.1.10 IRQSETMSK IRQ Set Mask Register (Offset 0x28) ........................................................ 66
5.1.11 IRQCLRMSK IRQ Clear Mask Register (Offset 0x2C) .................................................... 67
5.1.12 SIGSTAT Signal Status Register (Offset 0x30)............................................................... 68
5.1.13 IRQSTAT IRQ Status Register (Offset 0x34) .................................................................. 69
5.1.14 SWITCHES Board Configuration Register (Offset 0x38) ................................................. 70
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5.1.15 GPOUT General Purpose Output Register (0x3C).......................................................... 71
5.1.16 GPIO Direction Register (0x40) ......................................................................................72
5.1.17 GPIO Data Output Register (0x44) .................................................................................73
5.1.18 GPIO Pin Status Register (0x48)....................................................................................74
5.1.19 Test Register 0 Input Signals (0xE0) .............................................................................75
5.1.20 Test Register 1 Input Signals (0xE4) .............................................................................76
5.1.21 Test Register 2 Input Signals (0xE8) .............................................................................78
5.1.22 Test Register 3 Input Signals (0xEC).............................................................................79
5.1.23 Test Register 0 Output Signals (0xF0)...........................................................................80
5.1.24 Test Register 1 Output Signals (0xF4)...........................................................................81
5.1.25 Test Register 2 Output Signals (0xF8)...........................................................................82
5.1.26 Test Register 3 Output Signals (0xFC) ..........................................................................83
6 Programming Guide..................................................................................................................... 84
6.1
Peripheral Memory Map .....................................................................................................84
6.2
Off-chip Memory Map.........................................................................................................84
6.2.1
DDR2 Memory Area.......................................................................................................86
6.2.2
Area 0............................................................................................................................86
6.2.3
Area 1............................................................................................................................87
6.2.4
Area 2............................................................................................................................87
6.2.5
Area 3............................................................................................................................87
6.3
Interrupt Handling...............................................................................................................89
6.3.1
IRQ ................................................................................................................................89
6.4
Au1250 Initialisation (preliminary).......................................................................................91
6.4.1
Clock .............................................................................................................................91
6.4.2
Bus State Controller .......................................................................................................91
6.4.3
DDR2 Memory Controller ...............................................................................................98
6.4.4
Interrupt Controller ....................................................................................................... 101
7 Appendix ................................................................................................................................... 110
7.1
ID-EEPROM Register Map ............................................................................................... 110
Document change history
Date
Version
Document change description
2005-09-14
01
EXM32 AU1200 CPU Module - Initial Version
2008-03-12
08
Update to EXM32 AU1250 CPU Module V30
2008-09-08
09
Register Definition Update
2008-09-17
1.0
released
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1 General Information
1.1 Introduction
The EXM32 Au1250 CPU Module is designed to operate with an EXM32 compatible motherboard to
form a complete system. The motherboard will provide power supply and legacy interface connectors,
as required by the specific application. With the possibility to add expansion modules, an EXM32
system can be easily adopted to very specific applications, such as gigabit transmission interfaces,
wireless communication, etc… An example EXM32 system is shown in figure 1:
Side View
Expansion Module
(optional)
CPU Module
Motherboard
Figure 1: EXM32 System
Special notice is given to meet the enhanced environment requirements in automotive and industrial
applications: the EXM32 system is designed to
EXM32 is a new form factor to develop compact industrial control systems. It is small enough for most
applications, yet provides enough space to implement complete systems with very few modules.
Special notice is given to meet the enhanced environment requirements in industrial applications:
EXM32 CPU modules can operate in the extended industrial temperature range and meet DIN EN
60068 (environmental conditions for electrical and electronic equipment for road vehicles).
The revolutionary EXM32 connector technology uses very reliable elastomeric contact elements in a
robust shell. This is no plug and socket system, only one EXM32 connector element is used for every
connector location. This allows also an easy preparation of system extensions without cost penalty.
The inter-board connection between Module and Motherboard or between two modules is established
by compressing the contact elements in between two module boards that have matching contact pads.
The connection has 'zero insertion force', is compressed and secured by screws and therefore
withstands shock and vibration.
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1.2 Functional Blocks
The EXM32 Au1250 CPU Module includes the following functional blocks:
CPU
AMD Alchemy Au1250 (MIPS) CPU 500 MHz
Memory ( on-board )
up to 256 MByte DDR-RAM (32 bit bus-width)
up to 128 Mbyte linear Flash (16 bit bus-width)
optional NAND Flash up to 256 Mbyte (8 bit bus-width)
Peripherals
Au1250 integrated LCD STN/TFT controller with a maximum resolution 2048x2048 pixel.
PCMCIA/CF Interface (dual slot supported)
Camera Interface
Ethernet 10/100T Controller
USB 2.0 high Speed OTG Host/Function controller (2-port)
CAN (2x)
Asynchr. Serial Interface (2x)
I2C(3x)
SPI
AC97/I²S Sound Interface
RTC
Bus
The 16-Bit (optional 32-Bit) CPU bus for SRAM- or VLIO-type peripherals available on module
connector (buffered, 5V tolerant). EXM32 allows to stack multiple CPU modules that share the
motherboard’
s or extension module’
s resources .
Connectors
Two EXM32 Connectors carries all interfaces, the system CPU bus and the power supply.
A Debug connector allows the connection of an JTAG based debug tool.
EXM32_AU1250_User-Manual-V10.doc
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1.2.1
© MSC Vertriebs GmbH
Block Diagram
EXM32 AU1250 CPU Module
AU1250
256 MByte
DDR RAM
DDR-SDRAM
Interface
2x USB
Host/Client
OTG
MAE
(MPEG1,2,4)
UART0
UART
RMI
MIPS Core
500 MHz
FPU, MMU
16 kB Instr. Cache
16 kB Data Cache
RTC
LCD Controller
MMC/SD
Bus State
Controller
Audio
I²S/AC97
CTRL
Internal Bus
CTRL
Processor Bus
Internal Data Buffer
External Bus
I²S/AC97
Ethernet
10/100 BaseT
System
FPGA
EXM32_AU1250_User-Manual-V10.doc
SPI
I2C0 /I2C1
I²S/AC97
UART1
page 7 of 110
Linear Flash
8...128MByte
Linear Flash
8...128MByte
CTRL
Figure 2: EXM32-Au1250 block diagram
2xCAN
Controller
EXM32-Connector X2
IDE/ CFInterface
External Data Buffer
EXM32-Connector X1
Video-in
(CCIR 656)
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
2 Overview
2.1 Connectors
EXM32 Connectors
Two EXM32 208 pin connectors. These connectors support EXM32 compatible
modules.
Debug Connector
Allows the connection of an JTAG based Debugger Tool.
Board type
Compact CPU module size 90 x 65 mm, stackable with other EXM32 modules.
2.2 Specification
Environment
Temperature
operating
-40° .. + 85°C
non operating -40° .. + 85°C
Humidity (rel.) operating
10 - 90 %
non operating
5 - 95 %
EMI
The EXM32 Au1250 CPU Module is designed to meet DIN EN55022 (emission) and DIN EN
61000-6-2 (immunity) when mounted into in an appropriate shielded and grounded enclosure.
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2.3
© MSC Vertriebs GmbH
Mechanical Dimensions
86
80
X1
X2
Mounting Hole
Ø 2.7 (6x)
61
54
65
Top View
Location Peg for
Bottom Connector
Ø 1.5 (4x)
Location Peg for
Top Connector
Ø 1.5 (4x)
83
90
Expansion
Module
A
B
1.6 typ.
D
C
Side View
Expansion Connector Height A
all dimensions in mm
CPU
Module
6.5
Top Component Height B*
4.0
CPU Connector Height C
6.5
Bottom Component Height D**
2.0
Figure 3: EXM32-Au1250 CPU Module mechanical dimensions
2.4 Connector Positions
Figure 4: EXM32-AU1250 CPU-module connector positions
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3 Interfaces
3.1 Connectors
3.1.1
EXM32 Connector Pin Definition
Orientation Mark
A
Strip A
B
Strip B
Pad
Defintion
1
3
2
4
Top View
X1
C
X2
Strip C
D
Strip D
connector
alignment pin
49
51
50
52
pin definiton for 0.8mm pitch
Figure 5: EXM32-Au1250 CPU-module Connectors
Note:
The EXM32 CPU Module is secured by six M2.5 screws that have to be fastened
with 30 Ncm clamping torque.
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3.1.2
© MSC Vertriebs GmbH
Connector X1 (CPU Bus, Compact Flash, SPI, AC’97/I²S, PCI-E)
Strip A
Strip B
Pin
Signal
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
reserved, don't use
reserved, don't use
reserved, don't use
CF0_PWEN
CF1_PWEN
reserved, don't use
CF0_RESET
CF1_RESET
SPI_SS0#
SPI_SS1#
reserved, don't use
SPI_SCK
SPI_MOSI
SPI_MISO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Signal
Pin
CF_SCKSEL
CF_CE1#
CF_CE2#
CF_IORD#
CF_IOWR#
CF_POE#
CF_PWE#
CF_WAIT#
CF_IOIS16#
CF_PREG#
CF0_RDY_IRQ#
CF1_RDY_IRQ#
CF0_CD#
CF1_CD#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Strip C
Signal
D00
D02
D04
D06
D08
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
BE0#
BE2#
IRQ_EXT1#
IRQ_EXT0#
IRQ_MB2#
IRQ_MB1#
IRQ_MB0#
CLK_GND
CLKOUT
CLK_GND
Pin
Signal
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
D01
D03
D05
D07
D09
D11
D13
D15
D17
D19
D21
D23
D25
D27
D29
D31
BE1#
BE3#
reserved, don't use
CSA#
CSB#
BS#
OE#
WE#
R/W#
RDY
Pin
Signal
A01
A03
A05
A07
A09
A11
A13
A15
A17
A19
A21
A23
A25
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
PCIE_GND
reserved, don't use
reserved, don't use
Strip D
Pin
Signal
Pin
Signal
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VBAT
reserved, don't use
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3STB
VCC3V3STB
VCC3V3STB
VCC3V3STB
VCC3V3STB
VCC3V3STB
VCC5V0
VCC5V0
VCC5V0
VCC5V0
VCC5V0
VCC5V0
reserved, don't use
reserved, don't use
AC’
97_SDIN1
AC’
97_SDIN0 /
I²S0_SCK
I²S1_SCK
AC’
97_SDOUT /
I²S0_SDIO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
A00
A02
A04
A06
A08
A10
A12
A14
A16
A18
A20
A22
A24
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
PCIE_GND
PCIE_GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
43
PCIE_GND
44
45
PCIE_GND
46
47
PCIE_GND
48
PWROFF / SUSPEND
45
SLEEP#
WAKEUP
PWRFLT#
RESET_IN#
RESET_OUT#
AC_RESET#
AC’
97_SYNC/
I²S0_LRCLK
I²S1_LRCLK
47
AC_GND
43
49
51
AC’
97_BCLK /
I²S_MCLK
AC_GND
44
46
48
Signal
50
I²S1_SDIO
49
PCIE_GND
50
52
reserved, don't use
51
PCIE_GND
52
EXM32_AU1250_User-Manual-V10.doc
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PCIE_GND
reserved, don't use
reserved, don't use
PCIE_GND
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Connector X2 (Interfaces)
Strip A
Pin
Signal
Strip B
Pin
Signal
Pin
Signal
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
DA_GND
DA0_SPDIF
DA_GND
DA0_MCLK
DA_GND
DA0_SCLK
DA0_LRCLK
DA0_SDIN0
DA0_SDIN1
DA0_SDIN2
DA_MUTE
DV_GND
DV0_CLK
DV_GND
DV0_AV#
DV0_HSYNC /
DV0_SYNC
DV0_VSYNC /
DV0_DVALID
DV_GND
DV0_D0
DV0_D1
DV0_D2
DV0_D3
DV0_D4
DV0_D5
DV0_D6
DV0_D7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
FW_GND
reserved, don't use
reserved, don't use
FW_GND
reserved, don't use
reserved, don't use
FW_GND
reserved, don't use
reserved, don't use
FW_GND
reserved, don't use
reserved, don't use
FW_GND
reserved, don't use
reserved, don't use
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
reserved, don't use
JTAG_TDO
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TRST#
CAN0_EN
CAN1_RX
CAN0_ERR#
CAN1_TX
31
SATA_GND
32
CAN0_STB#
31
34
CAN1_EN
33
36
38
40
42
44
46
48
50
52
CAN0_RX
CAN1_ERR#
CAN0_TX
CAN1_STB#
USB0_ID
USB0_VBUS
USB0(2)_PWEN
USB1(3)_PWEN
USB_OC#
35
37
39
41
43
45
47
49
51
33
35
37
39
41
43
45
47
49
51
reserved, don't use
reserved, don't use
GND
USB_GND
(3)
USB0(2)_D+
(3)
USB0(2)_DUSB_GND
(3)
USB1(3)_D+
(3)
USB1(3)_DUSB_GND
(1)
(1)
32
34
36
38
40
42
44
46
48
50
52
Signal
DA_GND
DA1_SPDIF
DA_GND
DA1_MCLK
DA_GND
DA1_SCLK
DA1_LRCLK
DA1_SDOUT0
reserved, don't use
reserved, don't use
DA_ERR
DV_GND
DV1_CLK
DV_GND
DV1_AV#
DV1_HSYNC /
DV1_SYNC
DV1_VSYNC /
DV1_DVALID
DV_GND
DV1_D0
DV1_D1
DV1_D2
DV1_D3
DV1_D4
DV1_D5
DV1_D6
DV1_D7
(3) = USB0,1 is available on bottom pad layout, USB2,3 on top pad layout
Strip C
Pin
Signal
Strip D
Pin
Signal
Pin
Signal
GPIO Mode
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
LCD_D00 (B0)
LCD_D01 (B1)
LCD_D02 (B2)
LCD_D03 (B3)
LCD_D04 (B4)
LCD_D05 (B5)
LCD_D06 (G0)
LCD_D07 (G1)
LCD_D08 (G2)
LCD_D09 (G3)
LCD_D10 (G4)
LCD_D11 (G5)
LCD_D12 (R0)
LCD_D13 (R1)
LCD_D14 (R2)
LCD_D15 (R3)
LCD_D16 (R4)
LCD_D17 (R5)
LCD_VDON
LCD_M_DE
LCD_VCON
LCD_HSYNC
LCD_VSYNC
LCD_DON
LCD_SHFCLK
LCD_BLON
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
ETH_ACTLED#
ETH_LILED#
ETH_SPLED#
ETH_GND
(1)
ETH_TXD+
(1)
ETH_TXDETH_GND
(1)
ETH_RXD+
(1)
ETH_RXDETH_GND
reserved, don't use
reserved, don't use
VGA_GND
reserved, don't use
VGA_GND
reserved, don't use
VGA_GND
reserved, don't use
VGA_GND
reserved, don't use
reserved, don't use
VGA_GND
(1) = signal connected only to bottom pad layout
EXM32_AU1250_User-Manual-V10.doc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Pin
LCD2 Mode
not available
GP_IN7
not available
GP_IN6
not available
GP_IN5
not available
GP_IN4
not available
GP_IN3
not available
GP_IN2
not available
GP_IN1
not available
GP_IN0
GP_OUT7 not available
GP_OUT6 not available
GP_OUT5 not available
GP_OUT4 not available
GP_OUT3 not available
GP_OUT2 not available
GP_OUT1 not available
GP_OUT0 not available
reserved, don't use
MODULE_DETECT
COM0_TXD
COM0_RXD
COM0_RTS#
COM0_CTS#
COM1_TXD
COM1_RXD
COM1_RTS#
COM1_CTS#
Signal
GPIO Mode
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
LCD2 Mode
not available
nc
not available
nc
not available
nc
not available
nc
not available
nc
not available
nc
not available
nc
not available
nc
SDIO_WP
SDIO_CLK
SDIO_CD#
SDIO_CMD
SDIO_DAT0
SDIO_DAT1/IRQ#
SDIO_DAT2/RW
SDIO_DAT3
(2)
CPUID0
(2)
CPUID1
FR_TXD
FR_RXD
FR_TXEN#
FR_RXEN#
FR_BGE
FR_EN
FR_STB#
FR_ERR#
(2 ) = signal input on bottom pad layout / signal output on top pad layout
page 12 of 110
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© MSC Vertriebs GmbH
Please note that all pins, that are marked with "reserved, don't use" must not be used
for general purpose hardware. They may be used in specific combinations of CPU
modules and motherboards.
3.2
Connector X1
3.2.1.1
Power Supply
All Signals are TTL level signals unless other specified.
N.C.
not connected
I.C.
internal connected - not to be used by customer
GND
logic ground
VCC3V3
3.3 VDC ± 5% main power supply
VCC3V3STB
3.3 VDC standby voltage (e.g. for self-refreshing SDRAM, CPU in sleep mode)
VCC5V0
5.0 VDC ± 10% optional power supply
VBAT
battery voltage (e.g. for real-time clock, battery is on EXM32 Motherboard)
3.2.1.2
SPI Bus Interface
Up to two SPI (Serial Peripheral Interface) bus channels may be provided on EXM32
CPU Modules. All signals are LV-TTL level signals.
SPI_SCK
Serial Clock output signal
SPI_MOSI
Master Output / Slave Input signal
SPI_MISO
Master Input / Slave Output signal
SPI_SS<1:0>#
Slave Select signals, active low
3.2.1.3
Compact Flash Interface
The Compact Flash interface can be used in 2 Modes: "Memory Mode" and in "I/O
Mode". Address and data lines are connected the CPU bus.
CF<1:0>_CD#
These Card Detect pins are connected to GND on the Compact Flash Storage Card or
CF+ Card. They are used by the host to determine that the CompactFlash Storage
Card or CF+ Card is fully inserted into its socket.
CF_SCKSEL
Allows to multiplex between 2 CF-Slots (0: Slot0; 1: Slot1), glue logic is required, is an
output of the EXM32 CPU Module.
CF_CE<2:1>#
These input signals are used both to select the card and to indicate to the card whether
a byte or a word operation is being performed. CE2# always accesses the odd byte of
the word. CE1# accesses the even byte or the Odd byte of the word depending on A0
and CE2#. A multiplexing scheme based on A0, CE1# and CE2 # allows 8 bit hosts to
access all data on D0-D7.
CF_IORD#
This signal is not used in PC Card Memory Mode.
in "PC Card I/O Mode" this signal is an I/O Read strobe generated by the host. It gates
I/O data onto the bus from the CompactFlash Storage Card or CF+ Card when the
card is configured to use the I/O interface, active low.
CF_IOWR#
This signal is not used in PC Card Memory Mode.
in "PC Card I/O Mode" the I/O Write strobe pulse is used to clock I/O data on the Card
Data bus into the CompactFlash Storage Card or CF+ Card controller registers when
the CompactFlash Storage Card or CF+ Card is configured to use the I/O interface.
The clocking will occur on the negative to positive edge of the signal (raising edge),
active low.
CF_POE#
This is an Output Enable strobe generated by the host interface.
It is used to read data from the CompactFlash Storage Card or CF+ Card in Memory
Mode and to read the CIS and configuration registers, active low.
EXM32_AU1250_User-Manual-V10.doc
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CF<1:0>_RDY_IRQ#
© MSC Vertriebs GmbH
in PC Card Memory Mode:
In Memory Mode this signal is set high when the CompactFlash Storage Card or CF+
Card is ready to accept a new data transfer operation and held low when the card is
busy. The Host memory card socket must provide a pull-up resistor. At power up and
at Reset, the RDY/-BSY signal is held low (busy) until the CompactFlash Storage Card
or CF+ Card has completed its power up or reset function. No access of any type
should be made to the CompactFlash Storage Card or CF+ Card during this time. The
RDY/-BSY signal is held high (disabled from being busy) whenever the following
condition is true: The CompactFlash Storage Card or CF+ Card has been powered up
with +RESET continuously disconnected or asserted.
in PC Card I/O Mode:
The signal is IREQ# . After the CompactFlash Storage Card or CF+ Card has been
configured for I/O operation, this signal is used as Interrupt Request. This line is
strobed low to generate a pulse mode interrupt or held low for a level mode interrupt.
CF<1:0>_RESET
When the pin is high, this signal resets the CompactFlash Storage Card or CF+ Card.
The CompactFlash Storage Card or CF+ Card is reset only at power up if this pin is left
high or open from power-up. The CompactFlash Storage Card or CF+ Card is also
reset when the Soft Reset bit in the Card Configuration Option Register is set.
CF<1:0>_ PWEN
When the pin is set high, the power supply for Compact Flash socket is enabled.
CF_PWE#
in PC Card Memory Mode:
This is a signal driven by the host and used for strobing memory write data to the
registers of the CompactFlash Storage Card or CF+ Card when the card is configured
in the memory interface mode. It is also used for writing the configuration registers.
in PC Card I/O Mode:
In PC Card I/O Mode, this signal is used for writing the configuration registers only.
CF_WAIT#
The WAIT# signal is driven low by the CompactFlash Storage Card or CF+ Card to
signal the host to delay completion of a memory or I/O cycle that is in progress.
CF_IOIS16#
in PC Card Memory Mode:
Used as Write Protect signal. The CompactFlash Storage Card or CF+ Card does not
have a write protect switch. This signal is held low after the completion of the reset
initialization sequence.
in PC Card I/O Mode:
When the CompactFlash Storage Card or CF+ Card is configured for I/O Operation,
the signal indicates if the selected I/O is a 16 Bit Port (IOIS16#). A Low signal indicates
that a 16 bit or odd byte only operation can be performed at the addressed data port.
CF_PREG#
in PC Card Memory Mode:
This signal is used during Memory Cycles to distinguish between Common Memory
and Register (Attribute) Memory accesses. High for Common Memory, Low for
Attribute Memory.
in PC Card I/O Mode:
The signal must also be active (low) during I/O Cycles when the I/O address is on the
Bus.
3.2.1.4
CPU Bus
D<31:00>
CPU Data bus lines
A<25:00>
CPU Address bus lines
BE<3:0>#
Byte Enable signals for write cycles only, BE0# indicates the least significant byte,
active low
CSA#, CSB#
Chip Select signals for external devices, active low
OE#
Output Enable signal (read strobe), active low
WE#
Write Enable signal (write strobe), active low
R/W#
Read/Write signal for direction control of Data Bus buffers, output from CPU Module,
write cycle = low
RDY
Ready signal from peripheral, indicates that a transfer is complete, active high
BS#
Bus Start signal, indicates the start of a bus cycle, active low
EXM32_AU1250_User-Manual-V10.doc
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RESET_IN#
CPU Module Reset Input, active low
RESET_OUT#
This output is the system reset generated from the CPU Module to reset external
devices, active low
CLKOUT
System Clock, generated from the CPU Module
CLK_GND
Clock GND, used for shielding / controlled impedance
IRQ_EXT<1:0>#
Interrupt Request from Extension Modules, active low, IRQ_EXT0# has highest priority
IRQ_MB<2:0>#
Interrupt Request from Motherboard, active low, IRQ_MB0# has highest priority
(DREQ<1:0>#)
DMA Request Inputs are used by external devices to indicate whether they need
service from the CPU modules DMA controller, active low (not available on the EXM32
AU1250 CPU Module).
(DRAK<1:0>#)
DMA Request Acknowledge outputs, notifies acceptance of DMA transfer request to
external device which has output DREQ#; active low (not available on the EXM32
AU1250 CPU Module).
(DACK<1:0>#)
DMA Acknowledge outputs, notification Strobe output to external device which has
output DREQ#; active low. (not available on the EXM32 AU1250 CPU Module)
PWRFLT#
Module input, indicates that the primary power supply voltage of the motherboard is
dropping below the operating voltage range. This signal can be used to save a limited
amount of data in a non-volatile memory before the CPU shuts down or to enter sleep
mode using VCC BAT.
SLEEP#
Sleep output, this signal is used to indicate the CPUs sleep mode to external devices,
active low.
PWROFF/SUSPEND
Power Off/Suspend output, this signal is used to shutdown supply voltages, only
VSTBY and VBAT may be available, active high.
WAKEUP
Wakeup CPU from Sleep mode, input for CPU module, active high.
3.2.1.5
Audio Codec AC’
97/I²S Interface
Serial data can be received from and transmitted to an AC’
97 or I²S codec, that may be
mounted on the motherboard. All signals are LVTTL level signals. Up to two digital
sound channels may be provided on EXM32 CPU Modules:
AC_RESET#
AC’97_BCLK
/ I²S_MCLK
I²S Mode:
AC’97 Mode:
Codec Reset
Codec Reset
Master Clock (only master mode)
Serial Data Clock (Bit
Clock)
Channel 0:
AC’97_SYNC
/ I²S0_LRCLK
AC’97_SDIN0 / I²S0_SCK
Left/Right Channel Select (Word Select)
Frame Sync
Serial Bit Clock
Serial Data In (Primary
Codec)
AC’97_SDIN1
no function
Serial Data In (Secondary
Codec)
AC’97_SDOUT / I²S0_SDIO
Serial Data In/Out
Serial Data Out
I²S1_LRCLK
Left/Right Channel Select (Word Select)
no function
I²S1_SCK
Serial Bit Clock
no function
I²S1_SDIO
Serial Data In/Out
no function
Channel 1:
EXM32_AU1250_User-Manual-V10.doc
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AC_GND
3.2.1.6
© MSC Vertriebs GmbH
Audio Codec Ground for shielding purposes
PCI Express Interface (not available on the EXM32-AU1250 CPU Module)
The PCI Express Interface is a new upcoming standard. It is a high performance
general purpose I/O Interconnect defined for a wide variety of future computing and
communication platforms. Key PCI attributes, such as its usage model, load-store
architecture, and software interfaces, are maintained, whereas its bandwidth-limiting,
parallel bus implementation is replaced by a highly scalable, fully serial interface. The
PCI Express Interface takes advantage of recent advances in point-to-point
interconnects, Switch-based technology, and packetized protocol to deliver new levels
of
performance
and
features.
More
information
is
available
at
www.intel.com/technology/pciexpress/ and http://www.pcisig.com/home
Contact pads for up to two PCIE connection lanes are provided in the EXM32 CPU
modules specification. The PCIE signals are intended to serve as:
(PCIE<1:0>_PET0+)
Transmitter Signal positive (not available on EXM32-AU1250 CPU Module)
(PCIE<1:0>_PET0-)
Transmitter Signal negative (not available on EXM32-AU1250 CPU Module)
(PCIE<1:0>_PER0+)
Receiver Signal positive (not available on EXM32-AU1250 CPU Module)
(PCIE<1:0>_PER0-)
Receiver Signal negative (not available on EXM32-AU1250 CPU Module)
(PCIE<1:0>_PRSNT#)
present signal (active low) (not available on EXM32-AU1250 CPU Module)
PCIE_GND
PCIE GND for shielding / controlled impedance
EXM32_AU1250_User-Manual-V10.doc
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3.3
© MSC Vertriebs GmbH
Connector X2
3.3.1.1
IEEE1394 (FireWire™ ) (not available on the EXM32-AU1250 CPU Module)
Up to two IEEE1394 ports may be provided on EXM32 CPU Modules.
(FW_TP<1:0>A+)
Twisted-Pair A Differential-Signals pos.
(FW_TP<1:0>A-)
Twisted-Pair A Differential-Signals neg.
(FW_TP<1:0>B+)
Twisted-Pair B Differential-Signals pos.
(FW_TP<1:0>B-)
Twisted-Pair B Differential-Signals neg.
(FW_CPS)
Cable Power Status
FW_GND
IEEE1394 GND for shielding / controlled impedance
3.3.1.2
Serial ATA (not available on the EXM32-AU1250 CPU Module)
One Serial ATA port may be provided on EXM32 CPU Modules.
(SATA_TX+)
Transmitter Signal positive
(SATA_TX-)
Transmitter Signal negative
(SATA_RX+)
Receiver Signal positive
(SATA_RX-)
Receiver Signal negative
SATA_GND
SATA GND for shielding / controlled impedance
3.3.1.3
USB
Four USB ports are provided on the EXM32 AU1250 CPU Module. USB<1:0> signals
are available on bottom pad layout, USB<3:2> signals are available on top pad layout.,
intended to be used on expansion modules.
Note: All pull-up resistors are integrated on the EXM32 CPU Module.
USB<3:0>_D+
Signal positive
USB<3:0>_D-
Signal negative
USB0_ID
USB OTG Configuration ID, High= peripheral, Low=host
(signal available only on bottom pad layout)
USB0_VBUS
USB Supply Voltage, also used for OTG Session Request Protocol
(signal available only on bottom pad layout)
USB<3:0>_PWEN
USB Bus Power Enable signal, active high, enables the USB ports +5V supply
USB_OC#
Overcurrent Detect Signal for the USB +5V power line from motherboard, common for
two USB ports, active low
USB_GND
USB GND for shielding / controlled impedance
3.3.1.4
JTAG Interface
JTAG signals are used only for boundary scan and PLD programming.
JTAG_TDO
Data is read from external device in synchronization with a TCK signal.
JTAG_TDI
Data is sent to external device in synchronization with a TCK signal.
JTAG_TCK
Functions as the serial clock input pin stipulated in the JTAG standard (IEEE standard
1149.1).
JTAG_TMS
Mode Select input - Changing this signal determines the significance of data input via
the TDI pin. Its protocol conforms to the JTAG standard.
EXM32_AU1250_User-Manual-V10.doc
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JTAG_TRST#
© MSC Vertriebs GmbH
JTAG Reset signal is received asynchronously with TCK signal. Asserting this signal
resets the JTAG interface circuit.
3.3.1.5 MOST Media Local Bus Interface (not available on the EXM32-AU1250 CPU
Module)
All signals are LV-TTL level signals.
5-pin mode (default):
3-pin mode:
(MLB_CLK)
clock input
(MLB_SI)
signal information input
no function
(MLB_SO)
signal information output
signal information in/out (MLBSIG)
(MLB_DI)
data input
no function
(MLB_DO)
data output
data in/out (MLBDAT)
3.3.1.6
clock input (MLBCLK)
CAN
Up to two CAN Bus Interfaces are provided on EXM32 CPU Modules. All signals are
LV-TTL level signals. External CAN Transceivers are required to convert the LV-TTL
signals to the physical CAN interface.
CAN<1:0>_TX
CAN Bus Transmit
CAN<1:0>_RX
CAN Bus Receive
CAN<1:0>_ERR#
CAN Bus Error Flag, active low
CAN<1:0>_EN
CAN Transceiver Enable, active high
CAN<1:0>_STB#
CAN Transceiver Standby, active low
3.3.1.7
Serial Audio Interface
Up to two digital audio interfaces provided on the EXM32 CPU Modules. All signals are
LV-TTL level signals.
Audio Channel 0:
DA0_SPDIF
Digital Audio signal (IEC 60958)
DA0_MCLK
Master Clock
DA0_SCLK
Serial Bit Clock
DA0_LRCLK
Left/Right Channel Select (Word Select)
DA0_SDIN0
Serial Data Input
Audio Channel 1:
DA1_SPDIF
Digital Audio signal (IEC 60958)
DA1_MCLK
Master Clock
DA_SCLK
Serial Bit Clock
DA1_LRCLK
Left/Right Channel Select (Word Select)
DA1_SDOUT0
Serial Data Output 0, contains channel 1 (Left) and channel 2 (Right) information
(DA1_SDOUT1)
Serial Data Output 1, contains channel 3 (Left Surround) and channel 4 (Right
Surround) information (not available on the EXM32-AU1250 CPU Module)
EXM32_AU1250_User-Manual-V10.doc
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(DA1_SDOUT2)
Serial Data Output 2, contains channel 5 (Center) and channel 6 (Low Frequency
Effect) information (not available on the EXM32-AU1250 CPU Module)
DA_ERR
Audio Error signal
DA_MUTE
Audio Mute signal
AUDIO_GND
Digital Audio Ground for shielding purposes
3.3.1.8
Digital Video Interface
Two digital video interfaces may be provided on EXM32 CPU Modules. All signals are
LV-TTL level signals.
Video Channel 0:
DV0_CLK
Video Clock signal
DV0_D<7:0>
Channel 0 data lines
DV0_EN#
Port Enable, active low
DV0_AV#
Available signal, active low
DV0_HSYNC
Horizontal Sync signal, high active
DV0_SYNC
Sync signal, indicates the start of packet, high
DV_VSYNC
Vertical Sync signal, high active
DV0_DVALID
Data Valid signal, indicates if data is valid for reading or writing, high
Video Channel 1:
DV 1_CLK
Video Clock signal
DV 1_D<7:0>
Channel 1 data lines
DV 1_EN#
Port Enable, active low
DV 1_AV#
Available signal, active low
DV 1_HSYNC
Horizontal Sync signal, high active
DV 1_SYNC
Sync signal, indicates the start of packet, high active
DV 1_VSYNC
Vertical Sync signal, high active
DV 1_DVALID
Data Valid signal, indicates if data is valid for reading or writing, high active
DV_GND
Digital Video Ground for shielding purposes
3.3.1.9 Primary LCD Port
All signals are LV-TTL level signals.
LCD_D<17:00>
Data for LCD panel
LCD_HSYNC
LCD Horizontal Sync signal
LDC_VSYNC
LCD Vertical Sync signal
LCD_SHFCLK
LCD Pixel Clock
LCD_VDON
enables Supply Voltage for Display Logic
LCD_VCON
enables Power Inverter Voltage
LCD_DON
Display On signal for STN displays
LCD_BLON
enables Backlight
EXM32_AU1250_User-Manual-V10.doc
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LDC_M_DE
© MSC Vertriebs GmbH
in case of STN Display:
in case of TFT Display:
AC Bias signal (M)
LCD Data Enable (DE)
3.3.1.10 I2C Interface
Up to two I2C channels may be provided on EXM32 CPU Modules. All signals are LVTTL level signals.
I2C<1:0>_SDA
Serial Data Input/Output signal, used to connect the CPU Modules on board I²S units
I2C<1:0>_SCL
Serial Clock Input/Output signal, reserved for Motherboard and Extension Modules I²S
units
3.3.1.11 Ethernet (10/100Mbit)
The signal termination is integrated on the EXM32 CPU Module. The EXM32 Ethernet
Interface is designed for use with Ethernet Magnetics.
ETH_TXD+
ETH_TXD-
Analog Twisted Pair - Ethernet Transmit Differential Pair. These pins transmit the serial
bit stream for transmission on the Unshielded Twisted Pair (UTP) cable. Available on
bottom pad layout only.
ETH_RXD+
ETH_RXD-
Analog Twisted Pair - Ethernet Receive Differential Pair. These pins receive the serial
bit stream from the Ethernet Magnetics. Available on bottom pad layout only.
ETH_GND
Ethernet GND for shielding / controlled impedance
ETH_ACTLED#
The Activity LED pin indicates either transmit or receive activity. When activity is
present, the activity LED is on; when no activity is present, the activity LED is off.
ETH_LILED#
The Link Integrity LED pin indicates link integrity. If the link is valid in either 10 or 100
Mbps, the LED is on; if link is invalid, the LED is off.
ETH_SPLED#
The Speed LED pin indicates the speed. The speed LED will be on at 100 Mbps and
off at 10 Mbps.
All LED signals pull external LEDs with max. 5 mA to GND.
3.3.1.12 CRT (not available on EXM32-AU1250 CPU Module)
A standard analogue CRT interface may be provided on EXM32 CPU Modules. The 75
Ohm termination resistors are integrated on the EXM32 CPU Module.
VGA_R
Red analogue video output signal for CRT displays (not available on EXM32-AU1250
CPU Module)
VGA_G
Green analogue video output signal for CRT displays (not available on EXM32-AU1250
CPU Module)
VGA_B
Blue analogue video output signal for CRT displays (not available on EXM32-AU1250
CPU Module)
VGA_H
Horizontal sync signal: This output supplies the horizontal synchronisation pulse (not
available on EXM32-AU1250 CPU Module)
VGA_V
Vertical sync signal: This output supplies the vertical synchronisation pulse (not
available on EXM32-AU1250 CPU Module)
VGA_GND
VGA Ground
VGA_DDC_SCL
VGA_DDC_SDA
Display Data Channel: the signals DDC_SCL and DDC_SDA, can be used for a DDC
interface between the graphics controller chip and the CRT monitor.
EXM32_AU1250_User-Manual-V10.doc
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All signals are LV-TTL level signals.
3.3.1.13 GPIO (LCD2 is not available on the EXM32-AU1250 CPU Module)
All signals are LV-TTL level signals.
16 I/O signals are provided by an EXM32 CPU module. These signal pins can
alternatively be used as secondary LCD data signals. The usage is defined by the logic
level LCD2_EN that is controlled by the EXM32 CPU Module:
(LCD2_EN)
when set to high, it enables the 2nd LCD Port on GPIO Pins:
high = LCD on GPIO pins
low = GPIO (default)
LCD Mode:
(LCD2_D<15:00>)
Data for LCD panel
(LCD2_HSYNC)
LCD Horizontal Sync signal
(LDC2_VSYNC)
LCD Vertical Sync signal
(LCD2_SHFCLK)
LCD Pixel Clock
(LCD2_VDON)
enables Supply Voltage for Display Logic
(LCD2_VCON)
enables Power Inverter Voltage
(LCD2_DON)
Display On signal for STN displays
(LCD2_BLON)
enables Backlight
(LDC2_M_DE)
in case of STN Display:
in case of TFT Display:
AC Bias signal (M)
LCD Data Enable (DE)
GPIO Mode:
GP_IN<7:0>
General Purpose Input signals for EXM32 CPU Module
GP_OUT<7:0>
General Purpose Output signals for EXM32 CPU Module
3.3.1.14 MultiMedia Card / Secure Digital Memory Card/Secure Digital Input/Output Card
A MultiMedia / Secure Digital Memory / Secure Digital Input/Output Card interface may
be provided. All signals are LV-TTL level signals.
SDIO_DAT0
Bidirectional data line 0 (4-bit and 1-bit mode)
SDIO_DAT1/IRQ#
Bidirectional data line 1 (4-bit mode), interrupt signal (1-bit mode, only SDIO Card, low
active)
SDIO_DAT2/RW
Bidirectional data line 2 (4-bit mode), read wait signal (1-bit mode, only SDIO Card,
optional)
SDIO_DAT3
Bidirectional data line 3 (4-bit mode)
SDIO_CLK
Host to card clock signal
SDIO_CMD
Bidirectional command / response signal
SDIO_WP
Write protect, active high
EXM32_AU1250_User-Manual-V10.doc
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SDIO_CD#
© MSC Vertriebs GmbH
Card detect, active low
3.3.1.15 Serial Ports
All signals are LV-TTL level signals. External drivers are required to convert the LV-TTL
signals to the desired physical interface like RS232, RS422, RS485.
COM0_TXD
Transmitter serial data output from serial port
COM0_RXD
Receiver serial data input
COM0_CTS#
handshake signal which notifies the UART that the modem is ready to receive data
COM0_RTS#
handshake signal which notifies the modem that the UART is ready to receive data
COM1_TXD
Transmitter serial data output from serial port
COM1_RXD
Receiver serial data input
COM1_CTS#
handshake signal which notifies the UART that the modem is ready to receive data
COM1_RTS#
handshake signal which notifies the modem that the UART is ready to receive data
3.3.1.16 FlexRay (not available on the EXM32-AU1250 CPU Module)
A FlexRay interface is provided on EXM32 CPU Modules. All signals are LV-TTL level
signals. An external transceiver is required to convert the LV-TTL signals to the desired
physical interface.
(FR_TXD)
transmit data
(FR_RXD)
receive data
(FR_TXEN#)
transmitter enable, active low
(FR_RXEN#)
receive data enable, active low
(FR_BGE)
bus guardian enable
(FR_EN)
transceiver enable, active high
(FR_STB#)
transceiver standby, active low
(FR_ERR#)
bus error flag, active low
3.3.1.17 MISC
MODULE_DETECT
A lower EXM32 Module can detect if another Module is mounted on top, this feature is
used for automatic JTAG chain configuration:
a) the pad on every modules bottom side is connected to VCC3V3
b) the top side pad is used for readout - there is no connection to the bottom side pad!
CPUID<1:0>
There are no direct connections between the top and bottom side pads of
CPUID<1:0>!
The modules ID value (binary) is available on the top side signal pads for the next
upper Module.
The ID value is generated by reading the lower module's ID value vie the bottom side
pads and incrementing this value by 1.
A EXM32 motherboard has the ID value '00', the CPU Module ID value is '01', …
As a second function, the module ID value may be used to address the
modules/motherboards ID-EEPROM on the I²C Bus, refer to.
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3.4 Debug Connector
The Debug Connector accepts a FPC cable, Channel 0 connects the debug adaptor to the
on board PLDs (FPGA,CPLD) and Channel 1 to the CPUs JTAG Debug Port. The on board
PLDs (FPGA,CPLD) can be accessed via the debug adaptor or the EXM32 Connector.
DEBUG
31 Pin FPC Connector, RM0.50, 90°, Bottom contact
Weitronic 570-31-30-(10)
Pin
Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VCC
VCCIO
TCK0
TRST0#
TDI0
TDO0
TMS0
SRESET#
GND
TCK1
TRST1#
TDI1
TDO1
TMS1
ASEBRK#
GND
TRACECLK (nc)
TRACESYNC (nc)
GND
TRACEDATA0 (nc)
TRACEDATA1 (nc)
TRACEDATA2 (nc)
TRACEDATA3 (nc)
TRACEDATA4 (nc)
TRACEDATA5 (nc)
TRACEDATA6 (nc)
TRACEDATA7 (nc)
DEBUG DETECT
TXD (nc)
RXD (nc)
BOOT# (nc)
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4 Hardware Description
4.1 Functional Blocks
4.1.1
CPU
The EXM32-Au1250 CPU module is equipped with the Au1250 processor. The user can choose to
run the CPU at three different frequencies per option of assembly. The chosen CPU speed determines
the maximum peripheral clock frequency available on the EXM32-Connector (X1B_CLKOUT).
CPU Speed
336 Mhz
396 Mhz
492 Mhz
600 Mhz
AU1250 CLKOUT (EXM32-Connector)
56 Mhz
66Mhz
61,5Mhz
66,67Mhz
Clocks
There are three crystal oscillators populated on the EXM32-AU1250. A 12 MHz crystal oscillator is
feed to the AU1250 for generation of internal and external frequencies. A 25.000 MHz crystal oscillator
provides the clock for a phase-locked loop (PLL) clock generator.
PLL clock generator CY22393
The PLL clock synthesiser populated on the CPU module generates the clocks for all peripheral
modules..
The Cypress CY22393 clock generator features three independent phase-locked loops. The device is
in-system serial and flash programmable, thus all frequency settings can be changed.
On the EXM32-SHAu1250 CPU module, the PLL clock generator is connected to Channel 0 of the
integrated I²C-Bus. To access the PLL, device address 1101001 must be used.
PLL device address:
1101001x (0xD2)
The CY22393 clock generator provides up to six output clocks:
OUTPUT
FREQUENCY
MODULE CLOCK
XBUF
25.000 MHz
Ethernet Clock
CLKA
variable (default: 33.33 MHz)
Digital Video Clock
CLKB
2.000 MHz
VRG synchronisation clock
CLKC
27.000 MHz
Digital Video clock/ HSDI clock
CLKD
14.769231 MHz
Not Used
CLKE
48 Mhz
USB clock
The Cypress clock generator offers power saving features that are controlled by a programmable logic
device (FPGA). The input pin SHUTDOWN#/OE three-states all outputs, when pulled LOW. If
shutdown is enabled, a LOW on this pin disables all phase-locked loops, counters, the reference
oscillator and all other active components. The S2/SUSPEND# connected to the SUSPEND signal
input of the clock generator can be configured to shut down a customisable set of outputs and/or
phase-locked loops, when LOW. This feature can be used for power saving.
For a detailed description of the PLL clock generator device please refer to the Cypress CY22393
Datasheet.
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I²C ID-EEPROM
The ID-EEPROM is used to store module specific parameters. For a parameter overview and a
memory map of the ID-EEPROM please refer to appendix A.
The Catalyst Supervisor CAT1026 device used on the board provides 2048 byte of serial electrical
erasable and programmable read-only memory and is equipped with a two wire interface (I²C). On the
EXM32-Au1250 CPU Module, the CAT1026 is connected to Channel 0 of the integrated I²C-Bus. To
access the ID-EEPROM, device address 1010000 must be used.
ID-EEPROM device address:
1010000x (0xA0)
For a detailed description of the ID-EEPROM device please refer to the Catalyst CAT1026 Datasheet.
Real Time Clock
The EXM32-Au1250 CPU Module is equipped with a discrete RTC device. This module is a serial
interface real time clock with built-in crystal oscillator. The Seiko Epson RTC-8564NB real time clock
module offers many functions such as calendar clock, alarm, timer and frequency output (1 Hz, 32 Hz,
1024 Hz, 32.768 kHz).
The device functions can be controlled by a two wire interface (I²C). On the EXM32-Au1250 CPU
Module, the RTC is connected to channel 0 of the integrated I²C-Bus.
To access the real time clock module, device address 1010001 must be used.
RTC device address:
1010001x (0xA2)
For a detailed description of the real time clock module please refer to the Seiko Epson RTC-8564NB
Application Manual.
4.1.2
MMC/SD/SDIO
MultiMedia Card (MMC)/
Secure Digital Memory Card (SD)/
Secure Digital Input/Output Card (SDIO)
The EXM32-Au1250 CPU Module supports a SD/SDIO/MMC I/O Card interface.
Secure Digital Memory Card support a mechanical write protect switch. An input of the programmable
logic device (FPGA) is used to readout the status of this switch. When the signal EXT_SDIO_WP is
LOW, the SD Card is fully accessible. The card is write-protected, when EXT_SDIO_WP is HIGH. To
readout the actual status of the write protect switch, access to the internal registers of the FPGA is
necessary. The device driver must support this feature. BRDSTAT Board Status Register.
4.1.3
PC-Card/Compact Flash Interface
The EXM32-Au1250 CPU Module features a PC-Card/Compact Flash interface. This interface
supports two sockets. A signal CF_SCKSEL on the EXM32 connector is used to multiplex between
the two sockets 0 and 1. When CF_SCKSEL is low, socket 0 is active. Socket 1 is active, when
CF_SCKSEL is HIGH. CF_SCKSEL is generated by a programmable logic device (Lattice CPLD). The
reset signals CF<1:0>_RESET (active high) are generated by the programmable logic device. To
reset the PC-Card/Compact Flash Card, access to the internal registers of the CPLD is necessary.
The device driver must support this feature.
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4.1.4
© MSC Vertriebs GmbH
Linear Flash
Flash Memory is used for program and data storage. The EXM32 Module supports up to 128 MByte
flash memory, provided by one device (see memory map). Linear Flash memory is mapped into Area
0 and 3 of the external memory space. This allows the system to boot from flash. The Linear Flash
shares memory space with the Ethernet Controller, the USB Controller, the UART, two I2C-controller,
the SPI-Controller, the CAN-Controller the programmable logic device (FPGA).
The EXM32 CPU Module supports write protection for Linear Flash Memory. An output of the
programmable logic device (FPGA) is used to enable or disable the write protection (shared with
NAND Flash write protection). When the output is HIGH, the Flash Memory is fully accessible. The
card is write-protected, when the programming voltage is turned off. The programming voltage is
disabled, when the output is LOW. To enable or disable the write protection, access to the internal
registers of the FPGA is necessary. The device driver must support this feature.
For detailed description of the memory space mapping please refer to chapter 6.2 "Off-chip Memory
Map".
4.1.5
NAND-Flash
The Au1250 CPU module is availabel with a optional 8 Bit NAND Flash assembly.
The EXM32 CPU Module supports write protection for NAND-Flash Memory. When the output is
HIGH, the Flash Memory is fully accessible. The card is write-protected, when the output is LOW. To
enable or disable the write protection, access to the internal registers of the FPGA is necessary. The
device driver must support this feature.
4.1.6
DDR2-SDRAM
The EXM32-Au1250-CPU Module provides up to 256 Mbyte DDR2-SDRAM.
The CPU Module uses two DDR2-banks, each bank with two memory modules.
Each memory module is organised x16-bit, in order to provide the 32-bit wide working memory,
directly interfaced to the CPU. All SDRAM signals are driven directly by the processor. For detailed
description of the memory space mapping and for detailed setup and initialization of the Au1250
SDRAM Controller please refer to chapter 6.2 "Off-chip Memory Map".
4.1.7
Ethernet
The EXM32-Au1250 CPU Module is equipped with an SMSC LAN91C111I Single Chip MAC + PHY,
to support 10/100BaseT Ethernet.
Power saving modes can be controlled individually for the MAC and the PHY by software.
The Ethernet Controller I/O space is mapped into Area 0 and 3 of the external memory space. The
SMSC LAN91C111I shares its I/O space with the Flash Memory, the USB Controller and the
programmable logic device (FPGA).
For detailed description of the memory space mapping please refer chapter 6.2 "Off-chip Memory
Map". For a detailed description of the Ethernet Controller please refer to the SMSC LAN91C111I
Datasheet.
4.1.8
USB
The Au1250 microprocessor features two integrated USB 2.0 high speed ports. A 2.0 compatible
enhanced host controller and and a 2.0 compatible USB device with OTG support. The USB host
controller of the Au1250 processor is connected to port 1, the device controller to port 0 of the EXM32Au1250 CPU Module.
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An external power switch and over-current detection is implemented in a programmable device
(FPGA). The Power Enable for USB Port 0 and 1 can be set in the peripheral devices control register
(PDCTRL). The status of the overcurrent is available in the board status register (BRDSTAT). 6.1.7
PDCTRL Peripheral Devices Control Register.
For a detailed description of the integrated USB controller please refer to Au1250 Datasheet.
4.1.9
Graphics Controller
4.1.9.1 Integrated Graphics Controller
The Au1250 features an integrated LCD Controller with a maximum resolution of 2048x2048 pixel.
This controller is capable of driving 4-24 bit color STN and TFT displays. If 24-Bit Interface is
necessary additional 6 Bit of the LCD 2 Interface have to be used. In this case no GPIO function is
available on the EXM Connector. Refer to Table 6 and section 5.1.12 GPIO Interface for details.
The Au1250 CPU Module provides four signals used to control display power sequences:
Signal
TYPE
INIT
SIGNAL
DESCRIPTION
X1C_LCD2_VDON
O
0
VDON
enables digital power supply
X1C_LCD2_VCON
O
0
VCON
enables power inverter voltage
X1C_LCD2_BLON
O
0
BLON
Enables backlight inverter
X1C_LCD2_DON
O
0
DON
enables display (only STN/D-STN Displays)*
* connect to pin DISP_OFF# on STN/D-STN displays
Software controlls the timing for the LCD power up seqence. The LCD power control signals can be
set in the LCD Control Register. Refer to section 6.1.5 LCDCTRL LCD Control Register for details.
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LCD power-supply control sequence:
Figure 6: EXM32-Au1250 CPU-module LCD power-on timing
For valid timing values please refer to the display manufacturer’
s datasheet.
The AU1250 LCD interface is connected to the EXM32-Connector as follows.
LCD
Signal
LCD_D[0]
LCD_D[1]
LCD_D[2]
LCD_D[3]
LCD_D[4]
LCD_D[5]
LCD_D[6]
LCD_D[7]
LCD_D[8]
LCD_D[9]
LCD_D[10]
LCD_D[11]
LCD_D[12]
LCD_D[13]
LCD_D[14]
LCD_D[15]
LCD_D[16]
LCD_D[17]
LCD_D[18]
LCD_D[19]
LCD_D[20]
LCD_D[21]
LCD_D[22]
LCD_D[23]
LCD_BIAS
LCD_FCLK
LCD_LCLK
LCD_PCLK
Mono STN
Panel
4-bit
8-bit
M0
M0
M1
M1
M2
M2
M3
M3
M4
M5
M6
M7
Color STN Panel
Single
D0
D1
D2
D3
Dual
D0
D1
D2
D3
D4
D5
D6
D7
Table 6: EXM32-Au1250 LCD-Interface
EXM32_AU1250_User-Manual-V10.doc
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Color TFT Panel
12-bit
18-bit
B0
B1
B2
B3
B0
B1
B2
B3
B4
B5
G0
G1
G2
G3
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R0
R1
R2
R3
R4
R5
24-bit
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
EXM32-Connector
Signals
GP_OUT[2]/LCD2_D[13]
GP_OUT[3]/LCD2_[D12]
LCD_B[0]
LCD_B[1]
LCD_B[2]
LCD_B[3]
LCD_B[4]
LCD_B[5]
GP_OUT[4]/LCD2_D[11]
GP_OUT[5]/LCD2_[D10]
LCD_G[0]
LCD_G[1]
LCD_G[2]
LCD_G[3]
LCD_G[4]
LCD_G[5]
GP_OUT[6]/LCD2_D[9]
GP_OUT[7]/LCD2_D[8]
LCD_G[0]
LCD_G[1]
LCD_G[2]
LCD_G[3]
LCD_G[4]
LCD_G[5]
LCD_M_DE
LCD_VSYNC
LCD_HSYNC
LCD_SHFCLK
EXM32 AU1250 CPU Module - User’
s Manual
4.1.9.2
© MSC Vertriebs GmbH
Spread Spectrum LCD Clock Modulator
The AU1250 CPU Module is equiped with a DS1081L Clock Modulator.
The AU1250 LCD Clock can be feed through the DS1081L for EMV purposes or bypassed by an
analog switch. Refer to section 6.1.5 LCDCTRL LCD Control Register and the Maxim DS1081L
datasheet for details.
4.1.10 Camera Interface
The LCD 2 interface, available at the EXM32-connector, is directly connected to the Au1250 CPU
Camera Interface (8-bit data). For details refer to the AU1250 Datasheet.
LCD2_SHFCLK
LCD2_HSYNC
CIM_FS
LCD2_VSYNC
AU-1200
CIM_LS
CIM_D[2]
LCD2_D[0]
CIM_D[9]
LCD2_D[7]
Figure 7: EXM32-AU1250 CPU-module camera interface
EXM32 Connector
Camera Interface Signal
LCD2_D[0]/GP_IN[7]
CIM_D2
LCD2_D[1]/GP_IN[6]
CIM_D3
LCD2_D[2]/GP_IN[5]
CIM_D4
LCD2_D[3]/GP_IN[4]
CIM_D5
LCD2_D[4]/GP_IN[3]
CIM_D6
LCD2_D[5]/GP_IN[2]
CIM_D7
LCD2_D[6]/GP_IN[1]
CIM_D8
LCD2_D[7]/GP_IN[0]
CIM_D9
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EXM32 Module Connector
CIM_CLK
EXM32 AU1250 CPU Module - User’
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4.1.11 GPIO-/( LCD2) Interface (V0.5 Update)
The AU1250 LCD2 Interface can be used either in LCD2 or GPIO mode. The Camera Interface of the
AU1250 CPU is directly connected to the dual function pins LCD2_D[7:0]/GP_IN[7:0] on the EXM
Connector. Refer to the AU1250 Datasheet to set these pins in GPIN Mode if necessary. The MSB of
the LCD2 Interface LCD2_D[8:15]/ GP_OUT[7:0] can be used either in GPOUT Mode or in LCD Mode.
If 24-Bit TFT Mode on LCD 1 Interface is necessary, the LCD 2 interface is used to provide the
additional 6 Bit to the EXM Connector (see Table 6)
LCD[17:0]
LCD_D[17:0]
LCD[17:0]/GPOUT[7:0]
LCD Interface (LCD_D[23:0])
LCD_D2[17:8]/GP_OUT[7:0]
GPOUT[5]/GPOUT[7]
GPOUT[7:0]
EXM32 Module Connector
BUFFER
BUF_EN
LCD_D[9]/LCD_D[17]
AU-1200
GPOUT[7:0]
Data/Addr
FPGA
LCD2 ENABLE
Camera Interface(CIM[7:0])
LCD_D2[7:0]/GP_IN[7:0]
Figure 8: EXM32-LCD2-Interface
To set the LCD Interface in GPIO Mode reset Bit 5 in BRDCTRL Resister (6.1.3 BRDCTRL Board
Control Register). Signal LCD2_ENABLE reflects the Status of Bit 5 to the EXM Connector. It can be
used to control external buffers on the Motherboard. If LCD mode is disabled the GPOUT Register
(Baseaddress 0x3FFF_003C ) takes control of the Signals LCD2_D[8:15]/ GP_OUT[7:0]. Refer to
section 6.1.16 GPOUT General Purpose Output Register.
LCD Mode
BRD_CTRL[5]=LCD2_EN=0
Baseaddress=0x3FFF0008
AU1250
CIM[D9 :D2]/GPIO[209:202]
(Refer to AU1250 Datasheet to
set these pins to Camera
Interface Mode )
AU1250 LCD2[17]
(24-Bit-TFT)
AU1250 LCD_D[16]/GPIO[211]
(24-Bit-TFT)
EXM32_AU1250_User-Manual-V10.doc
GPIO Mode
BRD_CTRL[5]=LCD2_EN=1
Baseaddress=0x3FFF0008
EXM32 Connector Signals
AU1250
CIM[D9 :D2]/GPIO[209:202]
(Refer to AU1250 Datasheet to
set these pins to GPIN Mode)
GPI[7:0]/LCD2_D[7:0]
GPOUT[7]
(Baseaddress=0x3FFF003C)
GPOUT[6
(Baseaddress=0x3FFF003C)
page 30 of 110
GPO[7]/LCD2_D[8]
GPO[6]/LCD2_D[9]
EXM32 AU1250 CPU Module - User’
s Manual
AU1250 LCD_D[9]
(24-Bit-TFT)
AU1250 LCD_D[8]/GPIO[210]
(24-Bit-TFT)
AU1250 LCD_D[1]/GPIO[201]
(24-Bit-TFT)
AU1250 LCD_D[0]/GPIO[200]
(24-Bit-TFT)
© MSC Vertriebs GmbH
GPOUT[5]
(Baseaddress=0x3FFF003C)
GPOUT[4]
(Baseaddress=0x3FFF003C)
GPOUT[3]
(Baseaddress=0x3FFF003C)
GPOUT[2]
(Baseaddress=0x3FFF003C)
GPOUT[1]
(Baseaddress=0x3FFF003C)
GPOUT[0]
(Baseaddress=0x3FFF003C)
Not used
Not used
GPO[5]/LCD2_D[10]
GPO[4]/LCD2_D[11]
GPO[3]/LCD2_D[12]
GPO[2]/LCD2_D[13]
GPO[1]/LCD2_D[14]
GPO[0]/LCD2_D[15]
Table 7: Signal routing in LCD2-/GPIO-Mode
4.1.12 CAN Bus
Data
CTRL
CAN0_INT
RXD
CAN0_RXD
TXD
CAN0_TXD
INT
Addresses
FPGA
AU-1200
CAN0_EN/ CAN1_EN
CAN0_EN/ CAN1_EN
CAN0_STB#/ CAN1_STB#
CAN0_ERR#/ CAN1_ERR#
CAN0_STB#/ CAN1_STB#
CAN0_ERR#/ CAN1_ERR#
Data
CAN-Controller
CAN1_INT
CTRL
Addresses
Data
Figure 8: EXM32-Au1250 CAN interface
EXM32_AU1250_User-Manual-V10.doc
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RXD
CAN1_RXD
TXD
CAN1_TXD
EXM32 Module Connector
Addresses
CAN-Controller
The EXM32-AU1250 CPU Module features two independent OKI ML9620 CAN bus controllers. The
operation mode of the CAN transceivers (on an EXM32-Motherboard) is controlled by the signals
CAN<1:0>_EN and CAN<1:0>_STB#. Those signals can be controlled in peripheral devices control
register (PDCTRL, section 6.1.7) in the FPGA.
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
4.1.13 Serial Communication Interfaces (COM0,COM1)
The EXM32-AU1250 CPU module features a two channel serial communication Interface.
COM0: The Au1250 integrated serial interface 1 is connected to the EXM32 Connector . The second
serial interface (PSC1) of the AU1250 is not used. Refer to the AU1250 datasheet for a detailed
description of the AU1250 integrated UART.
COM1: COM1 is implemented in an FPGA. The FPGA integrated IP is a 16550 compatible UART. The
8 bit interface of the UART is connected to the lower 8 bit of the external 16 bit data bus of the
Au1250-CPU Module.
UART1_TXD
COM0_TXD
UART1_RXD
COM0_RTS
UART1_CTS
COM0_CTS
AU-1200
UART1_RTS
ADDRESSE
DATA
UART 16550-IP (FPGA)
CTRL
UART_TXD
COM1_TXD
UART_RXD
COM1_RXD
UART_RTS
COM1_RTS
UART_CTS
COM1_CTS
EXM32 Module Connector
COM0_RXD
Figure 9: EXM32- Au1250 serial interfaces
4.1.13.1 UART Clock (COM1)
The FPGA integratet UART uses the AU1250 CLOCKOUT. Refer to chapter 5.1 for details.
Name
Source
Min
Max
clk
CPU
14.0625 bps
115200 bps
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Resolution
Description
UART Clock
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
4.1.13.2 Registers of the FPGA integrated UART (COM1)
Base Address: 0x1FFF4000/0x3FFF4000
Name
Receiver Buffer
Transmitter
Holding
Register (THR)
Interrupt Enable
Address
0
0
Width
8
8
Access
R
W
Description
Receiver FIFO output
Transmit FIFO input
1
8
RW
Interrupt Identification
FIFO Control
Line Control Register
Modem Control
Line Status
Modem Status
2
2
3
4
5
6
8
8
8
8
8
8
R
W
RW
W
R
R
Enable/Mask
interrupts
generated by the UART
Get interrupt information
Control FIFO options
Control connection
Controls modem
Status information
Modem Status
In addition, there are 2 cascaded 8-bit clock dividers.
The registers can be accessed when the 7th (DLAB) bit of the Line Control Register is set to ‘
1’
. At this
time the above registers at addresses 0-1 can’
t be accessed.
Name
Divisor Latch Byte 1 (LSB)
Address
0
Width
8
Access
RW
Divisor Latch Byte 2
1
8
RW
Description
The LSB of the divisor
latch
The MSB of the divisor
latch
4.1.13.2.1 Interrupt Enable Register (IER)
This register allows enabling and disabling interrupt generation by the UART.
Bit #
0
Access
RW
1
RW
2
RW
3
RW
7-4
RW
Description
Received Data available interrupt
‘
0’– disabled
‘
1’– enabled
Transmitter Holding Register empty interrupt
‘
0’– disabled
‘
1’– enabled
Receiver Line Status Interrupt
‘
0’– disabled
‘
1’– enabled
Modem Status Interrupt
‘
0’– disabled
‘
1’– enabled
Reserved. Should be logic ‘
0’
.
Table 7: External UART Interrupt Enable Register (IER)
Reset Value: 00h
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4.1.13.2.2 Interrupt Identification Register (IIR)
The IIR enables the programmer to retrieve what is the current highest priority pending interrupt.
Bit 0 indicates that an interrupt is pending when it’
s logic ‘
0’
. When it’
s‘
1’– no interrupt is pending.
The following table displays the list of possible interrupts along with the bits they enable, priority, and
their source and reset control.
Bit 3
Bit 2
Bit 1
Priority
Interrupt Type
0
1
1
1st
0
1
0
2nd
1
1
0
2nd
0
0
1
3rd
0
0
0
4th
Receiver
Line
Status
Receiver Data
available
Timeout
Indication
Transmitter
Holding Register
empty
Modem Status
Interrupt Source
Interrupt Reset Control
Parity, Overrun or Framing
errors or Break Interrupt
FIFO trigger level reached
Reading the Line Status
Register
FIFO
drops
below
trigger level
Reading from the FIFO
(Receiver
Buffer
Register)
There’
s at least 1 character in
the FIFO but no character has
been input to the FIFO or read
from it for the last 4 Char
times.
Transmitter Holding Register
Empty
CTS, DSR, RI or DCD.
Writing
to
the
Transmitter
Holding
Register or reading IIR.
Reading the Modem
status register.
Bits 4 and 5: Logic ‘
0’
.
Bits 6 and 7: Logic ‘
1’for compatibility reason.
Reset Value: C1h
4.1.13.2.3 FIFO Control Register (FCR)
The FCR allows selection of the FIFO trigger level (the number of bytes in FIFO required to enable the
Received Data Available interrupt). In addition, the FIFOs can be cleared using this register.
Bit #
0
Access
W
1
W
2
W
5-3
7-6
W
W
Description
Ignored (Used to enable FIFOs in NS16550D). Since this UART only
supports FIFO mode, this bit is ignored.
Writing a ‘
1’to bit 1 clears the Receiver FIFO and resets its logic. But it
doesn’
t clear the shift register, i.e. receiving of the current character
continues.
Writing a ‘
1’to bit 2 clears the Transmitter FIFO and resets its logic. The
shift register is not cleared, i.e. transmitting of the current character
continues.
Ignored
Define the Receiver FIFO Interrupt trigger level
‘
00’– 1 byte
‘
01’– 4 bytes
‘
10’– 8 bytes
‘
11’– 14 bytes
Reset Value : 11000000b
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4.1.13.2.4 Line Control Register (LCR)
The line control register allows the specification of the format of the asynchronous data
communication used. A bit in the register also allows access to the Divisor Latches, which define the
baud rate. Reading from the register is allowed to check the current settings of the communication.
Bit #
1-0
Access
RW
2
RW
3
RW
4
RW
5
RW
6
RW
7
RW
Description
Select number of bits in each character
‘
00’– 5 bits
‘
01’– 6 bits
‘
10’– 7 bits
‘
11’– 8 bits
Specify the number of generated stop bits
‘
0’– 1 stop bit
‘
1’– 1.5 stop bits when 5-bit character length selected and
2 bits otherwise
Note that the receiver always checks the first stop bit only.
Parity Enable
‘
0’– No parity
‘
1’– Parity bit is generated on each outgoing character and
is checked on each incoming one.
Even Parity select
‘
0’– Odd number of ‘
1’is transmitted and checked in each word
(data and parity combined). In other words, if the data has an even
number of ‘
1’in it, then the parity bit is ‘
1’
.
‘
1’– Even number of ‘
1’is transmitted in each word.
Stick Parity bit.
‘
0’– Stick Parity disabled
‘
1’- If bits 3 and 4 are logic ‘
1’
, the parity bit is transmitted and
checked as logic ‘
0’
. If bit 3 is ‘
1’and bit 4 is ‘
0’then the parity bit is
transmitted and checked as ‘
1’
.
Break Control bit
‘
1’– the serial out is forced into logic ‘
0’(break state).
‘
0’– break is disabled
Divisor Latch Access bit.
‘
1’– The divisor latches can be accessed
‘
0’– The normal registers are accessed
Reset Value: 00000011b
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4.1.13.2.5 Modem Control Register (MCR)
The modem control register allows transferring control signals to a modem connected to the UART.
Bit #
0
Access
W
Description
Data Terminal Ready (DTR) signal control
‘
0’– DTR is ‘
1’
‘
1’– DTR is ‘
0’
Request To Send (RTS) signal control
‘
0’– RTS is ‘
1’
‘
1’– RTS is ‘
0’
Out1. In loopback mode, connected Ring Indicator (RI) signal input
Out2. In loopback mode, connected to Data Carrier Detect (DCD) input.
Loopback mode
‘
0’– normal operation
‘
1’– loopback mode. When in loopback mode, the Serial Output Signal
(STX_PAD_O) is set to logic ‘
1’
. The signal of the transmitter shift register is
internally connected to the input of the receiver shift register.
The following connections are made:
DTR
DSR
RTS
CTS
Out1
RI
Out2
DCD
1
W
2
3
4
W
W
W
5
W
RTS/CTS Autoflow.
‘
0’-RTS/CTS is exclusively controled by software. (Set RTS bit in modem control
register mcr[1], Read CTS bit in the modem status register mcr[0/4] )
‘
1’–RTS/CTS is controled by hardware, but can be set or read by software as
well.
- RTS is set as soon as the trigger level is reached and reset as soon as
the trigger level is underflown.
- If CTS is set, the transmission of a full transmitt-fifo is interrupted
immediately and will be continued at the point of interruption if CTS is
reset.
Software can take take control on the hardware-handshake in addition, if
autoflow is selected.
7-6
W
Ignored
Reset Value: 0
4.1.13.2.6 Line Status Register (LSR)
Bit #
0
Access
R
1
R
2
R
Description
Data Ready (DR) indicator.
‘
0’– No characters in the FIFO
‘
1’– At least one character has been received and is in the FIFO.
Overrun Error (OE) indicator
‘
1’– If the FIFO is full and another character has been received in
the receiver shift register. If another character is starting to arrive, it will
overwrite the data in the shift register but the FIFO will remain intact. The
bit is cleared upon reading from the register. Generates Receiver Line
Status interrupt.
‘
0’– No overrun state
Parity Error (PE) indicator
‘
1’– The character that is currently at the top of the FIFO has
been received with parity error. The bit is cleared upon reading from the
register. Generates Receiver Line Status interrupt.
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Bit #
Access
3
R
4
R
5
R
6
R
7
R
© MSC Vertriebs GmbH
Description
‘
0’– No parity error in the current character
Framing Error (FE) indicator
‘
1’– The received character at the top of the FIFO did not have a
valid stop bit. Of course, generally, it might be that all the following data is
corrupt. The bit is cleared upon reading from the register. Generates
Receiver Line Status interrupt.
‘
0’– No framing error in the current character
Break Interrupt (BI) indicator
‘
1’–A break condition has been reached in the current character.
The break occurs when the line is held in logic 0 for a time of one
character (start bit + data + parity + stop bit). In that case, one zero
character enters the FIFO and the UART waits for a valid start bit to
receive next character. The bit is cleared upon reading from the register.
Generates Receiver Line Status interrupt.
‘
0’– No break condition in the current character
Transmit FIFO is empty.
‘
1’– The transmitter FIFO is empty. Generates Transmitter
Holding Register Empty interrupt. The bit is cleared when data is being
been written to the transmitter FIFO.
‘
0’– Otherwise
Transmitter Empty indicator.
‘
1’– Both the transmitter FIFO and transmitter shift register are
empty. The bit is cleared when data is being been written to the
transmitter FIFO.
‘
0’– Otherwise
‘
1’– At least one parity error, framing error or break indications
have been received and are inside the FIFO. The bit is cleared upon
reading from the register.
‘
0’– Otherwise.
4.1.13.2.7 Modem Status Register (MSR)
The register displays the current state of the modem control lines. Also, four bits also provide an
indication in the state of one of the modem status lines. These bits are set to ‘
1’when a change in
corresponding line has been detected and they are reset when the register is being read.
Bit #
0
Access
R
1
R
2
R
3
R
4
5
6
7
R
R
R
R
Description
Delta Clear To Send (DCTS) indicator
‘
1’– The CTS line has changed its state.
Delta Data Set Ready (DDSR) indicator
‘
1’– The DSR line has changed its state.
Trailing Edge of Ring Indicator (TERI) detector. The RI line has changed
its state from low to high state.
Delta Data Carrier Detect (DDCD) indicator
‘
1’– The DCD line has changed its state.
Complement of the CTS input or equals to RTS in loopback mode.
Complement of the DSR input or equals to DTR in loopback mode.
Complement of the RI input or equals to Out1 in loopback mode.
Complement of the DCD input or equals to Out2 in loopback mode.
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4.1.13.2.8 Divisor Latches
The divisor latches can be accessed by setting the 7th bit of LCR to ‘
1’
. You should restore this bit to ‘
0’
after setting the divisor latches in order to restore access to the other registers that occupy the same
addresses. The 2 bytes form one 16-bit register, which is internally accessed as a single number. You
should therefore set all 2 bytes of the register to ensure normal operation. The register is set to the
default value of 0 on reset, which disables all serial I/O operations in order to ensure explicit setup of
the register in the software. The value set should be equal to (system clock speed) / (16 x desired
baud rate).
The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the
MSB first and the LSB last.
4.1.14 SPI-Interface
An external SPI controller is used on the Au1250 CPU to support the the serial protocol interface
(SPI). The SPI-IP is integrated in the FPGA. The SPI Interface is available on the EXM32 Connector.
UART_MOSI
SPI_MOSI
UART_MISO
SPI_MISO
UART_SS[1]
SPI_SS[1]
UART_SS[0]
SPI_SS[0]
DATA
Figure 10: EXM32-Au1250 SPI interface
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EXM32 Module Connector
ADDRESSE
SPI-IP (FPGA)
AU-1200
CTRL/INT
EXM32 AU1250 CPU Module - User’
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© MSC Vertriebs GmbH
4.1.14.1 SPI Clock
The variable SPI Clock depends on the used CPU frequency. Refer to chapter 5.1.1 CPU for details.
The clock divider register has to be initialized according to the used clock frequency.
Name
Source
Min
Max
Resolution
clk
AU1250
CLKOUT
113 bps
7.373 Mbps
Description
4.1.14.2 SPI Core Registers
Base Address: 0x1FFF2000/ 0x3FFF2000
Name
Rx0
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
Rx7
Tx0
Tx1
Tx2
Tx3
Tx4
Tx5
Tx6
Tx7
CTRL
DIVIDER
SS
Address
offset
0x00
0x02
0x04
0x06
0x08
0x0a
0x0c
0x0e
0x00
0x02
0x04
0x06
0x08
0x0a
0x0c
0x0e
0x10
0x12
0x14
Width
Access
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data receive register 0
Data receive register 1
Data receive register 2
Data receive register 3
Data receive register 4
Data receive register 5
Data receive register 6
Data receive register 7
Data transmit register 0
Data transmit register 1
Data transmit register 2
Data transmit register 3
Data transmit register 4
Data transmit register 5
Data transmit register 6
Data transmit register 7
Control and status register
Clock divider register
Slave select register
All registers are 16-bit wide and accessible only with 16 bits (all wb_sel_i signals must be active).
4.1.14.2.1 Data receive registers (RxX)
Bit #
Access
Name
15:0
R
Rx
Reset Value: 0x0000
RxX
The Data Receive registers hold the value of received data of the last executed transfer. Valid bits
depend on the character length field in the CTRL register (i.e. if CTRL[9:3] is set to 0x08, bit RxL[7:0]
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holds the received data). If character length is less or equal to 16 bits, Rx1-Rx7 are not used, if
character length is less than 32 bits, Rx2-Rx7 are not used and so on.
NOTE: The Data Received registers are read-only registers. A Write to these registers will actually
modify the Transmit registers because those registers share the same FFs.
4.1.14.2.2 Data transmit register (TxX)
Bit #
Access
Name
15:0
R/W
Tx
Reset Value: 0x0000
TxX
The Data Receive registers hold the data to be transmitted in the next transfer. Valid bits depend on
the character length field in the CTRL register (i.e. if CTRL[9:3] is set to 0x08, the bit Tx0[7:0] will be
transmitted in next transfer). If character length is less or equal to 16 bits, Tx1-Tx7 are not used, if
character len is less than 32 bits, Tx2-Tx7 are not used and so on.
4.1.14.2.3 Control and status register (CTRL)
Bit #
Access
Name
15:14
R
Reserve
d
13
R/W
ASS
12
R/W
IE
11
R/W
LSB
10
R/W
Tx_NEG
9
R/W
Rx_NE
G
8
R/W
GO_BSY
7
R
Reserve
d
6:0
R/W
CHAR_LEN
Reset Value: 0x0000
ASS
If this bit is set, ss_pad_o signals are generated automatically. This means that slave select signal,
which is selected in SS register is asserted by the SPI controller, when transfer is started by setting
CTRL[GO_BSY] and is de-asserted after transfer is finished. If this bit is cleared, slave select signals
are asserted and de-aserted by writing and clearing bits in SS register.
IE
If this bit is set, the interrupt output is set active after a transfer is finished. The Interrupt signal is
deasserted after a Read or Write to any register.
LSB
If this bit is set, the LSB is sent first on the line (bit TxL[0]), and the first bit received from the line will
be put in the LSB position in the Rx register (bit RxL[0]). If this bit is cleared, the MSB is
transmitted/received first (which bit in TxX/RxX register that is depends on the CHAR_LEN field in the
CTRL register).
Tx_NEG
If this bit is set, the mosi_pad_o signal is changed on the falling edge of a sclk_pad_o clock signal, or
otherwise the mosi_pad_o signal is changed on the rising edge of sclk_pad_o.
Rx_NEG
If this bit is set, the miso_pad_i signal is latched on the falling edge of a sclk_pad_o clock signal, or
otherwise the miso_pad_i signal is latched on the rising edge of sclk_pad_o.
GO_BSY
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Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically
cleared after the transfer finished. Writing 0 to this bit has no effect.
NOTE: All registers, including the CTRL register, should be set before writing 1 to the GO_BSY bit in
the CTRL register. The configuration in the CTRL register must be changed with the GO_BSY bit
cleared, i.e. two Writes to the CTRL register must be executed when changing the configuration and
performing the next transfer, firstly with the GO_BSY bit cleared and secondly with GO_BSY bit set to
start the transfer.
When a transfer is in progress, writing to any register of the SPI Master core has no effect.
CHAR_LEN
This field specifies how many bits are transmitted in one transfer. Up to 127 bits can be transmitted.
CHAR_LEN = 0x01 … 1 bit
CHAR_LEN = 0x02 … 2 bits
…
CHAR_LEN = 0x7f … 127 bits
4.1.14.2.4 Divider register (DIVIDER)
Bit #
Access
Name
15:0
R/W
DIVIDER
Reset Value: 0xffff
DIVIDER
The value in this field is the frequency divider of the system clock wb_clk_i to generate the serial clock
on the output sclk_pad_o. The desired frequency is obtained according to the following equation:
f sclk
f wb _ clk
DIVIDER 1 2
4.1.14.2.5 Slave select register (SS)
Bit #
Access
Name
15:8
R
Reserved
7:0
R/W
SS
Reset Value: 0x0000
SS
If CTRL[ASS] bit is cleared, writing 1 to any bit location of this field sets the proper ss_pad_o line to an
active state and writing 0 sets the line back to inactive state. If CTRL[ASS] bit is set, writing 1 to any bit
location of this field will select appropriate ss_pad_o line to be automatically driven to active state for
the duration of the transfer, and will be driven to inactive state for the rest of the time.
4.1.15 I²C-Interface
The EXM32-Au1250 CPU Module offers three different I²C-Bus channels. The PSC0 port of the
Au1250 is configured to act as a integrated I2C-controller. The PSC0 is connected to the peripheral
devices on the CPU module (EPROM, RTC, PLL) and the external I2C0 bus, available on the EXM32
Connector. Refer to the Au1250 datasheet for details. In addition two separate exernal I2C controller
are available on the Au1250 CPU module. The additional external I2C Controller IPs are integrated in
the FPGA.
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RTC-8564
Real Time Clock
Supervisor
Address:1010001x
CY22933
Clock Generator
Supervisor
Address:1101001x
(PSC0) I2C_SDA
I2C0_SDA
(PSC0) I2C_SCL
I2C0_SCL
ADDRESSE
DATA
I2C-IP (FPGA)
CTRL_INT
I2C0_SDA
I2C1_SDA
I2C0_SCL
I2C1_SCL
I2C1_SDA
I2C_DDC_SDA
I2C1_SCL
I2C_DDC_SCL
EXM32 Module Connector
AU-1200
CAT1026
EEPROM
Supervisor
Address:1010000x
© MSC Vertriebs GmbH
Figure 11: EXM32-Au1250 CPU-module I²C interfaces
In the following explanations only the the external I2C-controller (I2C1- and VGA_DDC_I2C-Bus) is
described. For a detailed description of internal Au1250 (SMBus/-) I2C-Controller refer to the Au1250
datasheet.
4.1.15.1 Features
Compatible with Philips I2C standard
Multi Master Operation
Software programmable clock frequency
Clock Stretching and Wait state generation
Software programmable acknowledge bit
Interrupt or bit-polling driven byte-by-byte data-transfers
Arbitration lost interrupt, with automatic transfer cancelation
Start/Stop/Repeated Start/Acknowledge generation
Start/Stop/Repeated Start detection
Bus busy detection
Supports 7 and 10bit addressing mode
Operates from a wide range of input clock frequencies
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4.1.15.2 I²C-Clock
The external I2C-Controller clock source is the variable CPU output clock . This clock signal is feed
into the SPI-controller as well. For each I2C controller a maximum wire speed of 400khz is possible.
CHANNEL
SPEED
Device
0
400 kHz/
100kHz
Au1250
interface(SMBUS)
1
DDC
400Khz/
100 kHz
400Khz/
100 kHz
DEVICE ADDRESS
PSC
Refer to Au12500 datasheet
External I2C-Controller
0x1FFF1000/ 0x3FFF1000
External I2C-Controller
0x1FFF1800/ 0x3FFF1800
Each I²C-Bus channel is available on the module connector/motherboard.
4.1.15.3 Registers list
Name
PRERlo
PRERhi
CTR
TXR
RXR
CR
SR
Address
0x00
0x01
0x02
0x03
0x03
0x04
0x04
Width
8
8
8
8
8
8
8
Access
RW
RW
RW
W
R
W
R
Description
Clock Prescale register lo-byte
Clock Prescale register hi-byte
Control register
Transmit register
Receive register
Command register
Status register
4.1.15.4 Register description
4.1.15.4.1 Prescale Register (PRERx)
This register is used to prescale the SCL clock line. Due to the structure of the I 2C interface, the core
uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency
(minus 1). Change the value of the prescale register only when the ‘
EN’bit is cleared.
Example1: I2C-Clock = 66 MHz, desired SCL = 100KHz
prescale
66 MHz
5 100 KHz
1
131 ( dec )
83 ( hex )
effective SCL = 100 kHz
Example2: I2C-Clock = 66 MHz, desired SCL = 400KHz
prescale
66 MHz
5 400 KHz
1
32 ( dec )
20 ( hex )
effective SCL = 400 kHz
Reset value: 0xFFFF
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4.1.15.4.2 Control register (CTR)
Bit #
7
Access
RW
6
RW
5:0
RW
Reset Value: 0x00
Description
EN, I2C core enable bit.
When set to ‘
1’
, the core is enabled.
When set to ‘
0’
, the core is disabled.
IEN, I2C core interrupt enable bit.
When set to ‘
1’
, interrupt is enabled.
When set to ‘
0’
, interrupt is disabled.
Reserved
The core responds to new commands only when the ‘
EN’bit is set. Pending commands are finished.
Clear the ‘
EN’bit only when no transfer is in progress, i.e. after a STOP command, or when the
command register has the STO bit set. When halted during a transfer, the core can hang the I2C bus.
4.1.15.4.3 Transmit register (TXR)
Bit #
7:1
0
Access
W
W
Description
Next byte to transmit via I2C
In case of a data transfer this bit represent the data’
s LSB.
In case of a slave address transfer this bit represents the RW bit.
‘
1’= reading from slave
‘
0’= writing to slave
Reset value: 0x00
4.1.15.4.4 Receive register (RXR)
Bit #
Access
7:0
R
Reset value: 0x00
Description
Last byte received via I2C
4.1.15.4.5 Command register (CR)
Bit #
Access
7
W
6
W
5
W
4
W
3
W
2:1
W
0
W
Reset Value: 0x00
Description
STA, generate (repeated) start condition
STO, generate stop condition
RD, read from slave
WR, write to slave
ACK, when a receiver, sent ACK (ACK = ‘
0’
) or NACK (ACK = ‘
1’
)
Reserved
IACK, Interrupt acknowledge. When set, clears a pending interrupt.
The STA, STO, RD, WR, and IACK bits are cleared automatically. These bits are always read as
zeros.
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4.1.15.4.6 Status register (SR)
Bit #
7
Access
R
6
R
5
R
4:2
1
R
R
0
R
Description
RxACK, Received acknowledge from slave.
This flag represents acknowledge from the addressed slave.
‘
1’= No acknowledge received
‘
0’= Acknowledge received
Busy, I2C bus busy
‘
1’after START signal detected
‘
0’after STOP signal detected
AL, Arbitration lost
This bit is set when the core lost arbitration. Arbitration is lost when:
a STOP signal is detected, but non requested
The master drives SDA high, but SDA is low.
See bus-arbitration section for more information.
Reserved
TIP, Transfer in progress.
‘
1’when transferring data
‘
0’when transfer complete
IF, Interrupt Flag. This bit is set when an interrupt is pending, which will cause
a processor interrupt request if the IEN bit is set.
The Interrupt Flag is set when:
one byte transfer has been completed
arbitration is lost
Reset Value: 0x00
Please note that all reserved bits are read as zeros. To ensure forward compatibility, they should be
written as zeros.
4.1.16 Audio Codec Interface (AC’97/I²S/LJ/RJ)
The EXM32-Au1250 CPU Module features one audio codec interface. This channel supports various
serial interfaces (e.g. AC’
97, I²S, Left Justified, Right Justified) and is configurable in master or slave
mode. By default it is set to slave mode.The on-board FPGA is responsible for the audio signal
routing. The register setting of the board controll register (brdctrl) determines the signal routing for the
respective audio mode (AC97/I2S/master/slave). Refer to section 6.1.3 brdctrl board control register
for details.
The audio codec channel is available on the EXM32 Connector /motherboard.
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AC97_RESET
PSC1_CLK
AC97_SYNC
PSC1_SYNC1
AC97_BCLK/ I2S1_MCLK
AC97_SDIN0
PSC1_D0
AC97_SDOUT
PSC1_EXTCLK
EXM32 Module Connector
AC97_SDIN1
PSC1_D1
FPGA
AU-1200(PSC1-Interface)
PSC1_SYNC0
I2S1_LRCLK
CTRL
Data
I2S1_SCLK
DATA
Adresses
I2S1_SDIO
Figure 12: EXM32-Au1250 audio codec interface
Au1250
Signals
PSC1_CLK
PSC1_SYNC1
PSC1_SYNC0
PSC1_D1
PSC1_D0
PSC1_EXTCLK
I2S
EXM32Connector
AC97_SDIN0
AC97_SYNC
I2S1_SDIO
AC97_SDOUT
I2S_MCLK
EXM32_AU1250_User-Manual-V10.doc
Signal
SCLK
LRCLK
DIN
DOUT
MCLK
page 46 of 110
AC97
EXM32Connector
AC97_BCLK
AC_RESET
AC97_SYNC
AC97_SDIN0
AC97_SDOUT
-
Signal
BCLK
RST#
SYNC
DIN
DOUT
EXM32 AU1250 CPU Module - User’
s Manual
4.2
© MSC Vertriebs GmbH
Power Management
CTRL
GPIO[5]
IRQs
FWTOY
AU-1200
PWR_OFF
PWR_OFF
UART_SS[1]
IRQs
EXM32 Module Connector
DATA
FPGA_INT#
FPGA
ADDRESSE
FWTOY
CPLD
SUSPEND
SLEEP#
WAKEUP#
UART_SS[0]
GPIO[7]
AU_WAKE_IRQ
PWRFLT#
Figure 13: EXM32-Au1250 power management
The complete EXM32-System can be set to power-off, sleep or hibernate mode by the Au1250-CPU.
To turn the systems power off the Au1250 has to access the Board Controll Register and set the
SW_PWR_OFF bit. Refer to section 6.1.3 BRDCTRL Board Controll Register for details.
To set the EXM32-System in sleep mode follow the instructions in Au1250 datasheet section “10.4.4
Device Power Management – Sleep”for details. The System can be wake-up by asserting the wakeup interrupt signals
-
AU_RTC-IRQ#
FPGA_INT#
AU_WAKE_IRQ#.
Refer to section 7.3 Interrupt handling of this manual and the AU1250 datasheet for details. Only the
core voltage of the AU1250 is turned off in sleep mode.
To enter hibernate mode, the FWTOY bit in the board controll register of the FPGA has to be set. The
FPGA releases the FWTOY signal, connected to the according pin on the AU1250 and the CPLD. The
CPLD sets the SLEEP# signal. This signal is available on the EXM32-connector and can be used to
shutdown external voltage regulators in the EXM32-System. A standby voltage still remains to supply
the system with the required standby voltage. To enter a proper hybernate mode refer to the AU1250
datasheet for details. The EXM32-system can be wake-up by releasing the WAKEUP# signal,
available on the EXM32 connector.
EXM32_AU1250_User-Manual-V10.doc
page 47 of 110
EXM32 AU1250 CPU Module - User’
s Manual
4.3
© MSC Vertriebs GmbH
Data Bus
The EXM32-AU1250 is available in a standard 16-bit and in a optional 32-bit Databus version.
4.3.1
16-Bit (standard)
EXM32 Module Connector
CTRL
CTRL
DATA[16:0]
16-Bit Data
Buffer
AU-1200
CTRL
FPGA
In the 16-bit version the 16-bit Databus of the Au1250 is buffered with a 74LVCR162245. The FPGA
generates the output enable and data direction signals for the 16 bit-data buffer from the Au1250 bus
state controller signals.
DATA[16:0]
Figure 14: EXM32-Au1250 16-Bit Bus
The following timing diagrams show the EXM32-connector signals, depending on the AU1250 bus
state controller signals. Refer to section 3.2 Static Bus Controller of the AU1250datasheet and section
7.4.2 Bus state controller of the EXM32-AU1250 user manual. A external 16- Bit device is connected
to the bits [15:0] of the external data bus X1B_D [15:0]. The device is selected with the chip select
X1B_CSA# and a address match on the Address bus X1B_A[25:1]. For the timing Values of the
AU1250 Bus state controller signals Ta,Tcsoe,Tcsoe,Twp, Twcs, Tcsw refer to the AU1250 datasheet
and section “Initialization”. The resulting Timing Values on the EXM32 connector are affected by the
delay time of the FPGA and the external bus buffers. The timing diagrams show a minimum and a
maximum delay time between AU1250 bus state controller and EXM32 connector signals and the
resulting minimum and maximum time for the EXM32 connector bus state controller signals. A 16 Bit
device can be accessed 8 or 16 bit wide, by analysing the byte enables X1B_BE#[1:0].
EXM32_AU1250_User-Manual-V10.doc
page 48 of 110
EXM32 AU1250 CPU Module - User’
s Manual
4.3.1.1
© MSC Vertriebs GmbH
16-bit read timing
EXM32_AU1250_User-Manual-V10.doc
page 49 of 110
EXM32 AU1250 CPU Module - User’
s Manual
4.3.2
© MSC Vertriebs GmbH
16-write timing
EXM32_AU1250_User-Manual-V10.doc
page 50 of 110
EXM32 AU1250 CPU Module - User’
s Manual
32-Bit (optional)
DATA[16:0]
16-Bit Data
Latch
CTRL
DATA[31:16]
EXM32 Module Connector
16-Bit Data
Buffer
CTRL
CTRL
AU-1200
CTRL
FPGA
4.3.3
© MSC Vertriebs GmbH
DATA[15:0]
Figure 14: EXM32-Au1250 32-Bit Bus
The AU1250 CPU Module is available with an optional 32-bit data bus X1B_D[31:0].
In the 32-bit version two consecutive 16 bit accesses are necessary. With the first 16bit access the lower 16 bit are stored in a data latch. With the second beat the upper
16 bit of the 32 bit word are issued by the AU1250. During the second beat the
complete 32 bit word is available on X1B_D[31:0]. The control signals for the data
latch, the data buffer and the EXM32 bus state controller are issued by the FPGA. A
32 bit databus thus isn’
t an advantage in access time. The time remains the same
like in two separate 16 bit memory accesses. A 32 bit device is always selected with
the chip select X1B_CSB# and an address match on the address bus X1B_A[25:2].
A 8, 16 and 32 bit access is possible on a 32 bit device by analyzing the byte enable
X1B_BE[3:0]. The AU1250 timing values in the timing diagrams Ta, Toecs, Tcoes,
Twcs, Tcsw and Tcsoff are defined by initialization. The values on the EXM32
connector show the minimum and maximum possible timing for this signals. The
timing diagrams show the minimum timing requirements for a 32 bit read/write
access. To guarantee the correct function of the AU1250 CPU module it is prohibited
to change this values. To extend access time the signal X1B_RDY, available on the
EXM32 connector, has to be pulled low. The cycle is extended until the signal is
released. The chip select X1B_CSA# and X1B_CSB# are configured in normal
mode, no page mode is possible.
EXM32_AU1250_User-Manual-V10.doc
page 51 of 110
EXM32 AU1250 CPU Module - User’
s Manual
4.3.3.1
32-bit read timing
EXM32_AU1250_User-Manual-V10.doc
page 52 of 110
© MSC Vertriebs GmbH
EXM32 AU1250 CPU Module - User’
s Manual
4.3.3.2
32-bit read timing
EXM32_AU1250_User-Manual-V10.doc
page 53 of 110
© MSC Vertriebs GmbH
EXM32 AU1250 CPU Module - User’
s Manual
4.4
© MSC Vertriebs GmbH
Power Supply
EXM32 Modules are supplied via the EXM32 Elastomeric Connectors X1 and X2 form the
EXM32 Motherboards power supplies.
The maximum available current is:
Main supply voltage:
current rating:
3.3 VDC 5%
max. 8.8 A
Optional supply voltage:
current rating:
5.0 VDC 10%
max. 2,0 A
Battery supply voltage:
current rating:
2.4 .. 3.6 VDC
max. 100 mA
Standby supply voltage (for SDRAM):
current rating:
3.3 VDC 5%
max. 100 mA
EXM32_AU1250_User-Manual-V10.doc
page 54 of 110
EXM32 AU1250 CPU Module - User’
s Manual
5
© MSC Vertriebs GmbH
FPGA
(Software Driver required)
The EXM-AU1250 module is equipped with a LFEC3E FPGA. This programmable logic device
controls many operations of the CPU-Module:
-
address decoding
address- and data-buffer control
LED control
Hardware Power Saving Modes control
Control for 32Bit Data Bus Mode
Integrated SPI Master
2 Integrated I2C Master
Integrated UART 16550
LCD Power-up Controller
The FPGA I/O space is mapped into area 0 (RCE3) and area 3 (RCE3). The FPGA shares its I/O
space with the Ethernet Controller, CAN Controller and external chip select CSA and CSB memory
space.
Example (preliminary):
IRQ
BIT
SIGNAL
DESCRIPTION
IRQ15
IRQ14
IRQ13
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWRFLT#
I2C1_IRQ
I2CDDC_IRQ
SPI_IRQ
CF0_IRQ
CF1_IRQ
CF0_CD
CF1_CD
SDIO_CD
UART0_IRQ
UART1_IRQ
UART2_IRQ
CAN0_IRQ
CAN1_IRQ
CAN0_ERR
CAN1_ERR
Primary Power Supply Fault
I2C1 controller interrupt
I2CDDC controller interrupt
SPI controller interrupt
CF/ATA0 interrupt
CF/ATA1 interrupt
CF0 card detect
CF1 card detect
SD card detect
UART0 interrupt
UART1 interrupt
UART2 interrupt
EXM32_AU1250_User-Manual-V10.doc
reserved for CAN0 interrupt
reserved for CAN1 interrupt
CAN channel 0 error interrupt
CAN channel 1 error interrupt
page 55 of 110
INTEVT
CODE
EXM32 AU1250 CPU Module - User’
s Manual
5.1
© MSC Vertriebs GmbH
FPGA Register Description
16
16
16
16
RCE0
ADDRESS
0x1FFF_0000
0x1FFF_0004
0x1FFF_0008
0x1FFF_000C
RCE3
ADDRESS
0x3FFF_0000
0x3FFF_0004
0x3FFF_0008
0x3FFF_000C
RESET
VALUE
0x0000
0x0000
16
16
16
16
0x1FFF_0010
0x1FFF_0014
0x1FFF_0018
0x1FFF_001C
0x3FFF_0010
0x3FFF_0014
0x3FFF_0018
0x3FFF_001C
0x0000
0x0000
0x0000
0x0000
16
16
16
16
0x1FFF_0020
0x1FFF_0024
0x1FFF_0028
0x1FFF_002C
0x3FFF_0020
0x3FFF_0024
0x3FFF_0028
0x3FFF_002C
0x0000
0x0000
0x0000
0x0000
16
16
16
16
16
16
8
0x1FFF_0030
0x1FFF_0034
0x1FFF_0038
0x1FFF_003C
0x1FFF_0040
0x1FFF_0044
0x1FFF_0048
0x3FFF_0030
0x3FFF_0034
0x3FFF_0038
0x3FFF_003C
0x3FFF_0040
0x3FFF_0044
0x3FFF_0048
0x0000
0x0000
0x00FF
0x0000
16
16
16
16
16
16
16
16
0x1FFF_00E0
0x1FFF_00E4
0x1FFF_00E8
0x1FFF_00EC
0x1FFF_00F0
0x1FFF_00F4
0x1FFF_00F8
0x1FFF_00FC
0x3FFF_00 E0
0x3FFF_00 E4
0x3FFF_00 E8
0x3FFF_00 EC
0x3FFF_00F0
0x3FFF_00F4
0x3FFF_00F8
0x3FFF_00FC
REGISTER
ACCESS
SIZE
BRDREV
BRDSTAT
BRDCTRL
LEDCTRL
R
R
R
W
R
W
LCDCTRL
CFCTRL
PDCTRL
FWCTRL
R
IRQCLREN
IRQSETEN
IRQCLRMSK
IRQSETMSK
R
SIGSTAT
IRQSTAT
SWITCHES
GPOUT
GPIO_DIR
GPIO_DOUT
GPIO_PINSTAT
TST_REG_IN0
TST_REG_IN1
TST_REG_IN2
TST_REG_IN3
TST_REG_OUT0
TST_REG_OUT1
TST_REG_OUT2
TST_REG_OUT3
W
R
W
R
W
R
W
W
R
W
R
W
R
W
R
R
R
R
W
R
W
R
W
R
R
R
R
R
R
W
R
W
R
W
R
W
EXM32_AU1250_User-Manual-V10.doc
page 56 of 110
0x0000
0x0000
0x0000
0x0000
INIT
VALUE
EXM32 AU1250 CPU Module - User’
s Manual
5.1.1
© MSC Vertriebs GmbH
BRDREV Board Revision Register (Offset 0x00)
entspricht WHO_AM_I
BIT
R
W
DEFAULT
BIT
15
12
11
8
7
4
3
0
15
R
-
NAME
14
R
-
13
R
-
VALUE
12
R
-
11
R
-
10
R
-
9
R
-
8
R
-
7
R
-
6
R
-
5
R
-
4
R
-
3
R
-
2
R
-
DESCRIPTION
HW
REV
-
CPU-Module Revision
HW
SUBREV
-
CPU-Module Subrevision
FPGA
REV
-
FPGA Software Revision, used for major updates
FPGA
SUBREV
-
FPGA Software Subrevision, used for minor updates
EXM32_AU1250_User-Manual-V10.doc
page 57 of 110
1
R
-
0
R
-
EXM32 AU1250 CPU Module - User’
s Manual
5.1.2
© MSC Vertriebs GmbH
BRDSTAT Board Status Register (Offset 0x04)
entspricht BOARD_STATUS
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
USB OC
10
SDIO
WP
9
-
8
FLASH
BUSY#
7
-
6
SWAP
BOOT
5
4
CPUID
3
2
CF1
VS
1
0
CF0
VS
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
00
01
10
11
00
01
10
11
12
R
0
11
R
0
10
R
0
9
R
1
8
R
1
0
7
R
0
6
R
0
5
R
4
R
1
1
0
0
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
USB Overcurrent
USB no Overcurrent
SD-Card is fully accessible
SD-Card is write protected
Flash device is busy
Flash device is idle
boot from ROM
boot from FLASH
reserved
CPU Module #1
CPU Module #2
CPU Module #3
3.3 V (default)
3.3 V or 5.0 V
3.3 V
5.0 V
3.3 V (default)
3.3 V or 5.0 V
3.3 V
5.0 V
page 58 of 110
3
R
0
2
R
0
1
R
0
0
R
0
EXM32 AU1250 CPU Module - User’
s Manual
5.1.3
© MSC Vertriebs GmbH
BRDCTRL Board Control Register (Offset 0x08)
entspricht SYSTEM_CONTROL und CONTROL / RESETS
BIT
15
14
R
R
R
BIT
15
14
13
W
W
W
DEFAULT
0
NAME
SW
RST
SW PWR
OFF
PSC1
CFG
12
-
11
-
10
FWTOY
9
-
8
-
0
13
R
1
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
R
0
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0
0
0
0
W
W
W
W
W
W
W
0
0
0
DESCRIPTION
De-assert System Reset
Assert System Reset
no change
turn off power supply
AC97 selection
I2S selection (default)
normal operation(Default)
set system to hibernate mode
7
6
5
Test
Mode
Enable
LCD2
ENABLE
4
FLWE
3
-
2
1
0
ETH
RST
PD
RST
MB
RST
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Test Mode is deactivated
Test Mode is activated. Certain EXM Signals can be set/read manually
in TST_REG_IN/OUT. (V0.6 Update)
LCD2-/GPIO-Interface is configured in LCD Mode
LCD2-/GPIO-Interface is configured in GPIO Mode
Flash is write protected (common for Strata-Flash and NAND-Flash)
Flash is fully accessible
EXM32_AU1250_User-Manual-V10.doc
De-assert Ethernet Controller Reset
Assert Ethernet Controller Reset
De-assert Peripheral Devices Reset
Assert Peripheral Devices Reset
De-assert Motherboard Reset
Assert Motherboard Reset
page 59 of 110
EXM32 AU1250 CPU Module - User’
s Manual
5.1.4
© MSC Vertriebs GmbH
LEDCTRL LED Control Register (Offset 0x0C)
entspricht DISC_LEDS
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
LED4
IDLE
2
LED3
1
LED2
0
LED1
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
2
1
0
R
R
R
R
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
LED4 is turned off (green)
LED4 is turned on (green)
LED3 is turned off (red)
LED3 is turned on (red)
LED2 is turned off (yellow/green)
LED2 is turned on (yellow/green)
LED1 is turned off (yellow)
LED1 is turned on (yellow)
page 60 of 110
0
W
W
W
W
0
0
0
EXM32 AU1250 CPU Module - User’
s Manual
5.1.5
© MSC Vertriebs GmbH
LCDCTRL LCD Control Register (Offset 0x10)
entspricht BOARD_SPECIFIC
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
LCD_CLK_
SEL
8:7
CM_CR_
SEL[1:0]
6
CM_
ENABLE
5:4
CM_
SEL[1:0]
3
LCD
DON
2
LCD
BLON
1
LCD
VDON
0
LCD
VCON
14
R
0
13
R
0
12
R
0
11
R
0
10
R
0
9
R
1
8
R
0
7
R
0
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0
0
0
0
W
W
W
W
W
W
W
0
0
0
VAL
DESCRIPTION
UE
0
1
0
1
0
1
0
1
0
1
0
1
0
LCD Display is feed by AU1250 (Default)
1
LCD Display is feed by Spread Spectrum Clock Modulator
Clock Range and Dither Rate Select. Three-level input that determines the
dither rate
CM_CR_SEL[1:0
10
01
00 (Default)
CLKIN Range
Dither Rate
66MHz to 134MHz
33MHz to 80MHz
fIN/2048
fIN/1024
20MHz to 38MHz
fIN/512
0
Spread Spectrum Modulator disabled (Default)
1
Spread Spectrum Modulator enabled
Spread-Spectrum Magnitude Select Inputs. These digital inputs select the
desired spread-spectrum magnitude as shown in the table below
CM_
SEL[1:0]
Magnitude
11
10
01
00(Defau
lt)
0
1
0
1
0
1
0
1
+0.5%
+1%
+1.5%
EXM32_AU1250_User-Manual-V10.doc
+2%
Display off (only STN displays)
Display on (only STN displays)
disable backlight
enable backlight
disable digital power supply (VDD)
enable digital power supply (VDD)
disable power inverter voltage (VEE)
enable power inverter voltage (VEE)
page 61 of 110
EXM32 AU1250 CPU Module - User’
s Manual
5.1.6
© MSC Vertriebs GmbH
CFCTRL Compact Flash Control Register (Offset 0x14)
entspricht PCMCIA_CONTROL
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIT
15
0
NAME
CF1
RST
14
-
13
-
12
CF1
EN
11
10
CF1
VCC
9
-
8
-
7
CF0
RST
6
-
5
4
ATA0_
EN
CF0
EN
3
2
CF0
VCC
1
-
0
-
0
0
VALUE
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
0
0
DESCRIPTION
De-assert Compact Flash Card 1 Reset
Assert Compact Flash Card 1 Reset
Disable Compact Flash 1 Interface
Enable Compact Flash 1 Interface
power supply disabled
set CF1 card power supply to 3.3 V
set CF1 card power supply to 5.0 V (not supported by EXM-AU1250)
set CF1 card power supply to 3.3 V
De-assert Compact Flash Card 0 Reset
Assert Compact Flash Card 0 Reset
Compact Flash Interrupt
IDE Interrupt
Disable Compact Flash 0 Interface
Enable Compact Flash 0 Interface
power supply disabled
set CF0 card power supply to 3.3 V
set CF0 card power supply to 5.0 V (not supported by EXM-Au1250)
set CF0 card power supply to 3.3 V
EXM32_AU1250_User-Manual-V10.doc
page 62 of 110
EXM32 AU1250 CPU Module - User’
s Manual
5.1.7
PDCTRL Peripheral Devices Control Register (Offset 0x18)
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
12
CAN1
STB
CAN1
EN
11
-
10
-
9
8
CAN0
STB
CAN0
EN
7
-
6
-
5
4
© MSC Vertriebs GmbH
USB1
TRI
USB1
PWEN
3
-
2
-
1
-
0
USB0
PWEN
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
0
R
R
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
de-assert CAN1 standby signal
assert CAN1 standby signal
de-assert CAN1 enable signal
assert CAN1 enable signal
de-assert CAN0 standby signal
assert CAN0 standby signal
de-assert CAN0 enable signal
assert CAN0 enable signal
X2A_USB1_PWEN is high impedance
X2A_USB1_PWEN is has a defined value (PDCTRL[4])
USB1 power disable
USB1 power enable
USB0 power disable
USB0 power enable
page 63 of 110
W
W
0
0
EXM32 AU1250 CPU Module - User’
s Manual
5.1.8
© MSC Vertriebs GmbH
IRQSETEN IRQ Set Enable Register (Offset 0x20)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
NAME
IRQ15
EN
IRQ14
EN
IRQ13
EN
IRQ12
EN
IRQ11
EN
IRQ10
EN
IRQ9
EN
IRQ8
EN
IRQ7
EN
IRQ6
EN
IRQ5
EN
IRQ4
EN
IRQ3
EN
IRQ2
EN
IRQ1
EN
IRQ0
EN
0
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
Power Fault Interrupt is disabled
Power Fault Interrupt is enabled
I2C1 Interrupt is disabled
I2C1 Interrupt is enabled
I2CDDC Interrupt is disabled
I2CDDC Interrupt is enabled
SPI Interrupt is disabled
SPI Interrupt is enabled
CF0/ATA0 interrupt is disabled
CF0/ATA0 interrupt is enabled
CF1/ATA1 interrupt is disabled
CF1/ATA1 interrupt is enabled
CF0 card detect interrupt is disabled
CF0 card detect interrupt is enabled
CF1 card detect interrupt is disabled
CF1 card detect interrupt is enabled
SD card detect interrupt is disabled
SD card detect interrupt is enabled
UART0 Interrupt is disabled
UART0 Interrupt is enabled
UART1 Interrupt is disabled
UART1 Interrupt is enabled
UART2 Interrupt is disabled
UART2 Interrupt is enabled
CAN0 controller interrupt is disabled
CAN0 controller interrupt is enabled
CAN1 controller interrupt is disabled
CAN1 controller interrupt is enabled
CAN0 error interrupt is disabled
CAN0 error interrupt is enabled
CAN1 error interrupt is disabled
CAN1 error interrupt is enabled
page 64 of 110
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W
W
W
W
W
W
0
0
EXM32 AU1250 CPU Module - User’
s Manual
5.1.9
© MSC Vertriebs GmbH
IRQCLREN IRQ Clear Enable Register (Offset 0x24)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
NAME
IRQ15
EN
IRQ14
EN
IRQ13
EN
IRQ12
EN
IRQ11
EN
IRQ10
EN
IRQ9
EN
IRQ8
EN
IRQ7
EN
IRQ6
EN
IRQ5
EN
IRQ4
EN
IRQ3
EN
IRQ2
EN
IRQ1
EN
IRQ0
EN
0
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
Power Fault Interrupt is disabled
Power Fault Interrupt is enabled
I2C1 Interrupt is disabled
I2C1 Interrupt is enabled
I2CDDC Interrupt is disabled
I2CDDC Interrupt is enabled
SPI Interrupt is disabled
SPI Interrupt is enabled
CF0/ATA0 interrupt is disabled
CF0/ATA0 interrupt is enabled
CF1/ATA1 interrupt is disabled
CF1/ATA1 interrupt is enabled
CF0 card detect interrupt is disabled
CF0 card detect interrupt is enabled
CF1 card detect interrupt is disabled
CF1 card detect interrupt is enabled
SD card detect interrupt is disabled
SD card detect interrupt is enabled
UART0 Interrupt is disabled
UART0 Interrupt is enabled
UART1 Interrupt is disabled
UART1 Interrupt is enabled
UART2 Interrupt is disabled
UART2 Interrupt is enabled
CAN0 controller interrupt is disabled
CAN0 controller interrupt is enabled
CAN1 controller interrupt is disabled
CAN1 controller interrupt is enabled
CAN0 error interrupt is disabled
CAN0 error interrupt is enabled
CAN1 error interrupt is disabled
CAN1 error interrupt is enabled
page 65 of 110
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W
W
W
W
W
W
0
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.10 IRQSETMSK IRQ Set Mask Register (Offset 0x28)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
NAME
IRQ15
MASK
IRQ14
MASK
IRQ13
MASK
IRQ12
MASK
IRQ11
MASK
IRQ10
MASK
IRQ9
MASK
IRQ8
MASK
IRQ7
MASK
IRQ6
MASK
IRQ5
MASK
IRQ4
MASK
IRQ3
MASK
IRQ2
MASK
IRQ1
MASK
IRQ0
MASK
1
1
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
Power Fault Interrupt is disabled
Power Fault Interrupt is masked
I2C1 Interrupt is disabled
I2C1 Interrupt is masked
I2CDDC Interrupt is disabled
I2CDDC Interrupt is masked
SPI Interrupt is disabled
SPI Interrupt is masked
CF0/ATA0 interrupt is disabled
CF0/ATA0 interrupt is masked
CF1/ATA1 interrupt is disabled
CF1/ATA1 interrupt is masked
CF0 card detect interrupt is disabled
CF0 card detect interrupt is masked
CF1 card detect interrupt is disabled
CF1 card detect interrupt is masked
SD card detect interrupt is disabled
SD card detect interrupt is masked
UART0 Interrupt is disabled
UART0 Interrupt is masked
UART1 Interrupt is disabled
UART1 Interrupt is masked
UART2 Interrupt is disabled
UART2 Interrupt is masked
CAN0 controller interrupt is disabled
CAN0 controller interrupt is masked
CAN1 controller interrupt is disabled
CAN1 controller interrupt is masked
CAN0 error interrupt is disabled
CAN0 error interrupt is masked
CAN1 error interrupt is disabled
CAN1 error interrupt is masked
page 66 of 110
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W
W
W
W
W
W
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.11 IRQCLRMSK IRQ Clear Mask Register (Offset 0x2C)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
NAME
IRQ15
MASK
IRQ14
MASK
IRQ13
MASK
IRQ12
MASK
IRQ11
MASK
IRQ10
MASK
IRQ9
MASK
IRQ8
MASK
IRQ7
MASK
IRQ6
MASK
IRQ5
MASK
IRQ4
MASK
IRQ3
MASK
IRQ2
MASK
IRQ1
MASK
IRQ0
MASK
1
1
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
Power Fault Interrupt is disabled
Power Fault Interrupt is masked
I2C1 Interrupt is disabled
I2C1 Interrupt is masked
I2CDDC Interrupt is disabled
I2CDDC Interrupt is masked
SPI Interrupt is disabled
SPI Interrupt is masked
CF0/ATA0 interrupt is disabled
CF0/ATA0 interrupt is masked
CF1/ATA1 interrupt is disabled
CF1/ATA1 interrupt is masked
CF0 card detect interrupt is disabled
CF0 card detect interrupt is masked
CF1 card detect interrupt is disabled
CF1 card detect interrupt is masked
SD card detect interrupt is disabled
SD card detect interrupt is masked
UART0 Interrupt is disabled
UART0 Interrupt is masked
UART1 Interrupt is disabled
UART1 Interrupt is masked
UART2 Interrupt is disabled
UART2 Interrupt is masked
CAN0 controller interrupt is disabled
CAN0 controller interrupt is masked
CAN1 controller interrupt is disabled
CAN1 controller interrupt is masked
CAN0 error interrupt is disabled
CAN0 error interrupt is masked
CAN1 error interrupt is disabled
CAN1 error interrupt is masked
page 67 of 110
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W
W
W
W
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W
W
W
W
W
W
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.12 SIGSTAT Signal Status Register (Offset 0x30)
BIT
R
W
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
SIG15
STAT
SIG14
STAT
SIG13
STAT
SIG12
STAT
SIG11
STAT
SIG10
STAT
SIG9
STAT
SIG8
STAT
SIG7
STAT
SIG6
STAT
SIG5
STAT
SIG4
STAT
SIG3
STAT
SIG2
STAT
SIG1
STAT
SIG0
STAT
15
R
0
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
DESCRIPTION
PWRFLT# (active low)
PWRFLT# (active low)
I2C1_IRQ# (active low)
I2C1_IRQ# (active low)
I2CDDC_IRQ# (active low)
I2CDDC_IRQ# (active low)
SPI_IRQ (active high)
SPI_IRQ (active high)
CF0_IRQ# (active low)
ATA0_IRQ (active high)
CF0_IRQ# (active low)
ATA0_IRQ (active high)
CF1_IRQ# (active low)
ATA1_IRQ (active high)
CF1_IRQ# (active low)
ATA1_IRQ (active high)
CF0_CD# (active low)
CF0_CD# (active low)
CF1_CD# (active low)
CF1_CD# (active low)
SDIO_CD# (active low)
SDIO_CD# (active low)
UART0_IRQ (active high)
UART0_IRQ (active high)
UART1_IRQ (active high)
UART1_IRQ (active high)
UART2_IRQ (active high)
UART2_IRQ (active high)
CAN0_IRQ# (active low)
CAN0_IRQ# (active low)
CAN1_IRQ# (active low)
CAN1_IRQ# (active low)
CAN0_ERR# (active low)
CAN0_ERR# (active low)
CAN1_ERR# (active low)
CAN1_ERR# (active low)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
page 68 of 110
3
R
0
2
R
0
1
R
0
0
R
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.13 IRQSTAT IRQ Status Register (Offset 0x34)
BIT
R
W
DEFAULT
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
R
0
NAME
IRQ15
STAT
IRQ14
STAT
IRQ13
STAT
IRQ12
STAT
IRQ11
STAT
IRQ10
STAT
IRQ9
STAT
IRQ8
STAT
IRQ7
STAT
IRQ6
STAT
IRQ5
STAT
IRQ4
STAT
IRQ3
STAT
IRQ2
STAT
IRQ1
STAT
IRQ0
STAT
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
DESCRIPTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
no power fault interrupt
pending power fault interrupt
no I2C1 interrupt request
Pending I2C1 interrupt request
no I2CDDC interrupt request
pending I2CDDC interrupt request
no SPI interrupt request
pending SPI interrupt request
no CF0/ATA0 interrupt
pending CF0/ATA0 interrupt
no CF1/ATA1 interrupt
pending CF1/ATA1 interrupt
no CF0 card detect interrupt
(writing a 0 has no effect)
pending CF0 card detect interrupt
(writing a 1 clears the interrupt status bit to 0)
no CF1 card detect interrupt
(writing a 0 has no effect)
pending CF1 card detect interrupt
(writing a 1 clears the interrupt status bit to 0)
no SD card detect interrupt
(writing a 0 has no effect)
pending SD card detect interrupt
(writing a 1 clears the interrupt status bit to 0)
no UART0 interrupt request
pending UART0 interrupt request
no UART1 interrupt request
pending UART1 interrupt request
no UART2 interrupt request
pending UART2 interrupt request
no CAN0 controller interrupt request
pending CAN0 controller interrupt request
no CAN1 controller interrupt request
pending CAN1 controller interrupt request
no CAN0 error interrupt request
pending CAN0 error interrupt request
no CAN1 error interrupt request
pending CAN1 error interrupt request
page 69 of 110
1
R
0
0
R
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.14 SWITCHES Board Configuration Register (Offset 0x38)
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
S7
6-3
14
R
0
13
R
0
12
R
0
S2
1
S1
0
S0
10
R
0
9
R
0
8
R
0
7
R
1
6
R
0
5
R
0
4
R
0
3
R
0
2
R
1
1
R
1
VALUE DESCRIPTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Big Endian
1
Little Endian
The Value in this Register sets the maximum CPU Clock Frequency
S[6:3]
2
11
R
0
Switches[6:3]
Frequency (Mhz)
1011
600
1101
492
1110
396
1111
336
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
Default
Default
Default
page 70 of 110
0
R
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.15 GPOUT General Purpose Output Register (0x3C)
BIT
15
R
0
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
GPOUT[7]
6
GPOUT[6]
5
GPOUT[5]
4
GPOUT[4]
3
GPOUT[3]
2
GPOUT[2]
1
GPOUT[1]
0
GPOUT[0]
14
R
0
13
R
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
R
0
11
R
0
10
R
0
9
R
0
8
R
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0
0
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
Default
Default
Default
Default
Default
Default
Default
Default
page 71 of 110
0
0
0
0
W
W
W
W
W
W
W
W
0
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.16 GPIO Direction Register (0x40)
BIT
R
W
DEFAULT
BIT
15
W
0
NAME
15
GPIO_DIR_
EN [7]
14
GPIO_DIR_
EN [6]
13
GPIO_DIR_
EN [5]
12
GPIO_DIR_
EN [4]
11
GPIO_DIR_
EN [3]
10
GPIO_DIR_
EN [2]
9
GPIO_DIR_
EN [1]
8
GPIO_DIR_
EN [0]
7
GPIO_DIR
[7]
6
GPIO_DIR
[6]
5
GPIO_DIR
[5]
4
GPIO_DIR
[[4]
3
GPIO_DIR
[3]
2
GPIO_DIR
[2]
1
GPIO_DIR
[1]
0
GPIO_DIR
[0]
14
W
0
13
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
W
0
11
W
0
10
W
0
9
W
0
8
W
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
1
1
1
1
1
DESCRIPTION
GPIO_DIR[7] write operation is disabled
GPIO_DIR[7] write operation is enabled
GPIO_DIR[6] write operation is disabled
GPIO_DIR[6] write operation is enabled
GPIO_DIR[5] write operation is disabled
GPIO_DIR[5] write operation is enabled
GPIO_DIR[4] write operation is disabled
GPIO_DIR[4] write operation is enabled
GPIO_DIR[3] write operation is disabled
GPIO_DIR[3] write operation is enabled
GPIO_DIR[2] write operation is disabled
GPIO_DIR[2] write operation is enabled
GPIO_DIR[1] write operation is disabled
GPIO_DIR[1] write operation is enabled
GPIO_DIR[0] write operation is disabled
GPIO_DIR[0] write operation is enabled
GPOUT[7] used as input
GPOUT[7] used as output
GPOUT[6] used as input
GPOUT[6] used as output
GPOUT[5] used as input
GPOUT[5] used as output
GPOUT[4] used as input
GPOUT[4] used as output
GPOUT[3] used as input
GPOUT[3] used as output
GPOUT[2] used as input
GPOUT[2] used as output
GPOUT[1] used as input
GPOUT[1] used as output
GPOUT[0] used as input
GPOUT[0] used as output
EXM32_AU1250_User-Manual-V10.doc
page 72 of 110
1
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W
W
W
W
W
W
W
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.17 GPIO Data Output Register (0x44)
BIT
R
W
DEFAULT
BIT
15
W
0
NAME
15
GPIO_DOU
T_EN [7]
14
GPIO_DOU
T_EN [6]
13
GPIO_DOU
T_EN [5]
12
GPIO_DOU
T_EN [4]
11
GPIO_DOU
T_EN [3]
10
GPIO_DOU
T_EN [2]
9
GPIO_DOU
T_EN [1]
8
GPIO_DOU
T_EN [0]
7
GPIO_DOU
T[7]
6
GPIO_DOU
T [6]
5
GPIO_DOU
T [5]
4
GPIO_DOU
T [[4]
3
GPIO_DOU
T [3]
2
GPIO_DOU
T [2]
1
GPIO_DOU
T [1]
0
GPIO_DOU
T [0]
14
W
0
13
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
W
0
11
W
0
10
W
0
9
W
0
8
W
0
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
1
1
1
1
1
1
DESCRIPTION
GPIO_DOUT [7] write operation is disabled
GPIO_ DOUT [7] write operation is enabled
GPIO_DOUT [6] write operation is disabled
GPIO_ DOUT [6] write operation is enabled
GPIO_ DOUT [5] write operation is disabled
GPIO_ DOUT [5] write operation is enabled
GPIO_ DOUT [4] write operation is disabled
GPIO_ DOUT [4] write operation is enabled
GPIO_ DOUT [3] write operation is disabled
GPIO_ DOUT [3] write operation is enabled
GPIO_ DOUT [2] write operation is disabled
GPIO_ DOUT [2] write operation is enabled
GPIO_ DOUT [1] write operation is disabled
GPIO_ DOUT [1] write operation is enabled
GPIO_ DOUT [0] write operation is disabled
GPIO_ DOUT [0] write operation is enabled
EXM32_AU1250_User-Manual-V10.doc
page 73 of 110
W
W
W
W
W
W
W
W
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.18 GPIO Pin Status Register (0x48)
BIT
15
R
-
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
GPIO_PIN_
STAT[7]
6
GPIO_PIN_
STAT [6]
5
GPIO_PIN_
STAT [5]
4
GPIO_PIN_
STAT [4]
3
GPIO_PIN_
STAT [3]
2
GPIO_PIN_
STAT [2]
1
GPIO_PIN_
STAT [1]
0
GPIO_PIN_
STAT [0]
14
R
-
13
R
-
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12
R
-
11
R
-
10
R
-
9
R
-
DESCRIPTION
EXM32_AU1250_User-Manual-V10.doc
page 74 of 110
8
R
-
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.19 Test Register 0 Input Signals (0xE0)
BIT
R
W
DEFAULT
BIT
15
R
-
14
R
-
NAME
15
X2D_SDIO_CD#
14
X2D_SDIO_WP
13
X1D_DREQ0#
12
X1D_DREQ1#
11
X2D_COM1_RXD
10
X2D_COM1_CTS#
9
X2A_CAN1_ERR#
8
X2A_USB_OC#
7
X2A_CAN0_ERR#
6
X1A_CF0_CD#
5
X1A_CF1_CD#
4
X2A_FW_LINKON
3
X1C_AC97_BCLK
2
X1C_AC97_SDIN1
1
X1A_CF0_RDY_IRQ#
0
X1A_CF1_RDY_IRQ#
13
R
-
12
R
-
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
11
R
-
10
R
-
9
R
-
DESCRIPTION
page 75 of 110
8
R
-
7
R
-
6
R
-
5
R
-
4
R
-
3
R
-
2
R
-
1
R
-
0
R
-
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.20 Test Register 1 Input Signals (0xE4)
BIT
R
W
DEFAULT
BIT
15
R
-
14
R
-
NAME
15
FREQUENCY_SET[1]
14
FREQUENCY_SET[0]
13
AU_PSC1_D0
12
AU_PSC1_SYNC1
11
X2D_FR_RXD
10
X2D_FR_STB#
9
X2D_FR_ERR#
8
X1C_PWRFLT#
7
X1A_SPI_MISO
6
AU_PSC1_CLK
5
AU_PSC1_SYNC0
4
X1C_AC97_SYNC
3
X2C_I2C1_SDA
2
X2C_I2C1_SCL
1
X2C_DDC_SCL
0
X2C_DDC_SDA
13
R
-
12
R
-
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
11
R
-
10
R
-
9
R
-
DESCRIPTION
page 76 of 110
8
R
-
7
R
-
6
R
-
5
R
-
4
R
-
3
R
-
2
R
-
1
R
-
0
R
-
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.21 Test Register 2 Input Signals (0xE8)
BIT
R
W
DEFAULT
BIT
15
R
-
14
R
-
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
X1C_AC97_SDIN0
1
X1C_I2S1_SCLK
0
X1C_I2S1_LRCLK
13
R
-
12
R
-
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
11
R
-
10
R
-
9
R
-
DESCRIPTION
page 78 of 110
8
R
-
7
R
-
6
R
-
5
R
-
4
R
-
3
R
-
2
R
-
1
R
-
0
R
-
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.22 Test Register 3 Input Signals (0xEC)
BIT
15
R
-
R
W
DEFAULT
BIT
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
X1B_RDY
1
-
0
-
14
R
-
13
R
-
12
R
-
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
11
R
-
10
R
-
9
R
-
DESCRIPTION
page 79 of 110
8
R
-
7
R
-
6
R
-
5
R
-
4
R
-
3
R
-
2
R
-
1
R
-
0
R
-
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.23 Test Register 0 Output Signals (0xF0)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIT
W
W
W
DEFAULT
0
0
NAME
15
X2A_CAN0_EN
14
X2A_FW_LPS
13
X1A_CF1_RESET
12
X2D_COM1_RTS#
11
X2D_COM1_TXD
10
X2C_LCD_DON
9
X2C_LCD_VCON
8
X2C_LCD_BLON
7
X2C_LCD_VDON
6
X1A_CF1_PWEN#
5
X1A_CF0_PWEN#
4
X1A_CF0_RESET
3
X1A_SPI_SCK
2
X1A_SPI_SS0#
1
X1A_SPI_SS1#
0
X1A_SPI_MOSI
W
0
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
W
0
W
0
W
0
DESCRIPTION
page 80 of 110
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.24 Test Register 1 Output Signals (0xF4)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIT
W
W
W
DEFAULT
0
0
NAME
15
X2D_FR_EN
14
X2D_FR_TXEN#
13
X2D_FR_RXEN#
12
X1C_AC97_RESET#
11
AU_DREQ0#
10
AU_DREQ1#
9
AU_PSC1_D1
8
AU_PSC1_EXTCLK
7
X1C_AC97_RESET#
6
X2A_USB1_PWEN
5
X2A_USB0_PWEN
4
X2A_USB1_PWEN
3
XA_CAN1_EN#
2
X2A_CAN0_STB#
1
X1D_DACK0#
0
X1D_DACK1#
W
0
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
W
0
W
0
W
0
DESCRIPTION
page 81 of 110
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.25 Test Register 2 Output Signals (0xF8)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIT
W
W
W
DEFAULT
0
0
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
X2D_LCD2_EN
2
X1C_AC97_SDOUT
1
X2D_FR_TXD
0
X2D_FR_BGE
W
0
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
W
0
W
0
W
0
DESCRIPTION
page 82 of 110
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
5.1.26 Test Register 3 Output Signals (0xFC)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
W
W
DEFAULT
BIT
0
W
0
NAME
15
-
14
-
13
-
12
-
11
-
10
-
9
X1A_CF_CE1#
8
X1A_CF_CE2#
7
X1A_CF_SCKSEL
6
X1B_CSB#
5
X1B_BE0#
4
X1B_BE1#
3
X1B_BE2#
2
X1B_BE3#
1
X1B_BS
0
X1B_R/W#
W
0
W
0
VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXM32_AU1250_User-Manual-V10.doc
W
0
W
0
W
0
DESCRIPTION
page 83 of 110
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
6 Programming Guide
6.1
Peripheral Memory Map
For a description of the peripheral memory space please refer to the AU1250 Hardware Manual.
6.2
Off-chip Memory Map
The Au1250 processor supports four external chip select spaces:
AREA/
OFF-CHIP Base ADDRESSES
CS
SIZE
WAIT
BUS
STATES WIDTH
INTERFACE
0
0x0_1800_0000 to
0x0_1FFF_FFFF
128MB
16-Bit
NOR Flash (BOOT)/
Peripheral Devices
1
0x0_2000_0000 to
0x0_2FFF_FFFF
256MB
16-Bit
NAND Flash
3
0x0_3000_0000 to
0x0_3FFF_FFFF
256MB
16/32-Bit
Peripheral devices
2
0xF_0000_0000 to
0xF_FFFF_FFFF
-
8/16-Bit
PCMCIA/CF
EXM32_AU1250_User-Manual-V10.doc
page 84 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
0x0_1FFF_0000
FPGA
0x0_1FFF_0FFF
0x0_1FFF_1000
I2C1
0x0_0000_0000
0x0_1FFF_17FF
0x0_1FFF_1800
0x0_0000_0000
DDR MEMORY Bank 0 (D_CS0)
NO TLB TRANSLATION REQUIRED 512MByte
DDR MEMORY 256 MByte
I2C_DDC
0x0_1FFF_1FFF
0x0_1FFF_2000
0x0_07FF_FFFF
0x0_0800_0000
DDR MEMORY Bank 1 (D_CS1)
0x0_0FFF_FFFF
0x0_1000_0000
0x0_0FFF_FFFF
SPI
0x0_1FFF_2FFF
0x0_1FFF_3000
I/O Devices 32 MByte
RESERVED
0x0_11FF_FFFF
0x0_1200_0000
0x0_1FFF_3FFF
0x0_1FFF_4000
reserved
UART1(COM1)
0x0_1FFF_4FFF
0x0_1FFF_5000
0x0_13FF_FFFF
0x0_1400_0000
I/O Devices 64 MByte
0x0_17FF_FFFF
0x0_1800_0000
UART2 (optional)
0x0_1FFF_5FFF
0x0_1FFF_6000
0x0_1800_0000
Flash
(up to 992 x 128 kByte)
0x0_1BFF_FFFF
0x0_1FC0_0000
Area 0 (RCE0)
0x0_1FFD_FFFF
0x0_1FFE_0000
NOR-Flash
IDE
Bootloader
(31 x 128 kByte)
UART3 (optional)
0x0_1FFF_6FFF
0x0_1FFF_7000
reserved
0x0_1FFF_9FFF
0x0_1FFF_A000
reserved
ATA/IDE
0x0_1FFF_AFFF
0x0_1FFF_B000
0x0_1FFE_FFFF
0x0_1FFF_0000
PERIPHERAL DEVICES
0x0_1FFF_FFFF
0x0_2000_0000
0x0_1FFF_FFFF
unused
0x0_1FFF_BFFF
0x0_1FFF_C000
CAN0 (Optional, HW Rev.2.0)
0x0_1FFF_CFFF
0x0_1FFF_D000
CAN1 (Optional, HW Rev.2.0)
Area 1 (RCE1)
0x0_1FFF_DFFF
0x0_1FFF_E000
NAND-Flash
0x0_3FFF_0000
ETHERNET
0x0_1FFF_EFFF
0x0_1FFF_F000
FPGA
0x0_3FFF_0FFF
0x0_3FFF_1000
FIREWIRE (Optional HW Rev.2.0)
0x0_1FFF_FFFF
0x0_2FFF_FFFF
0x0_3000_0000
0x0_3000_0000
I2C1
0x0_3FFF_17FF
0x0_3FFF_1800
CSA 64MByte
0x0_33FF_FFFF
0x0_3400_0000
Area 3 (RCE3)
I2C_DDC
0x0_3FFF_1FFF
0x0_3FFF_2000
CSB 64MByte
0x0_37FF_FFFF
0x0_3800_0000
Peripheral Devices
CSA
CSB
SPI
0x0_3FFF_2FFF
0x0_3FFF_3000
reserved
0x0_3FFE_FFFF
0x0_3FFF_0000
RESERVED
0x0_3FFF_3FFF
0x0_3FFF_4000
PERIPHERAL DEVICES
0x0_3FFF_FFFF
0x0_5000_0000
0x0_3FFF_FFFF
UART1(COM1)
0x0_3FFF_4FFF
0x0_3FFF_5000
reserved
UART2 (optional, HW Rev.2.0)
0x0_7FFF_FFFF
0x0_8000_0000
0x0_3FFF_5FFF
0x0_3FFF_6000
UART3 (optional, HW Rev.2.0)
0x0_3FFF_6FFF
0x0_3FFF_7000
reserved
0x0_3FFF_9FFF
0x0_3FFF_A000
reserved
ATA/IDE
0x0_3FFF_AFFF
0x0_3FFF_B000
unused
0xE_FFFF_FFFF
0xF_0000_0000
0x0_3FFF_BFFF
0x0_3FFF_C000
0xF_0000_0000
I/O
0xF_3FFF_FFFF
0xF_4000_0000
CAN0 (Optional HW Rev.2.0)
0x0_3FFF_CFFF
0x0_3FFF_D000
Attribute
Area 2 (RCE2)
0xF_7FFF_FFFF
0xF_8000_0000
PCMCIA
CAN1 (Optional HW Rev.2.0)
0x0_3FFF_DFFF
0x0_3FFF_E000
Memory
0xF_BFFF_FFFF
0xF_C000_0000
ETHERNET
0x0_3FFF_EFFF
0x0_3FFF_F000
reserved
0xF_FFFF_FFFF
0xF_FFFF_FFFF
Figure 13: EXM32-Au1250 CPU-module memory map
EXM32_AU1250_User-Manual-V10.doc
page 85 of 110
FIREWIRE (Optional HW Rev.2.0)
0x0_3FFF_FFFF
EXM32 AU1250 CPU Module - User’
s Manual
6.2.1
DDR2 Memory Area
AU_DDR_CS0#
AU_DDR_CS1#
6.2.2
© MSC Vertriebs GmbH
0x0_0000_0000
0x0_0800_0000
Area 0
Area 0 contains the flash memory space and I/O spaces of the peripheral devices. The whole address
decoding is done by a programmable logic device (FPGA). The FPGA generates from chip select 0
multiple address decoded chip selects. One chip select for each device. The interface type of Area 0 is
set to SRAM with a bus width of 16-bit.
Flash (FLASH_CS#)
FLASH base address:
0x0_1800_0000
Linear Flash memory is provided by one device. The l chip select signals for the two flash memories
are address decoded. There is an Address Space of 128 MByte Reserved for Linear Flash on the
Au1250 CPU Module
FPGA Register ( in FPGA integrated )
FPGA base address:
0x0_1FFF_0000
I2C (in FPGA integrated)
I2C1 base address:
0x0_1FFF_1000
I2CDDC base address:
0x0_1FFF_1800
SPI (in FPGA integrated)
SPI base address:
0x0_1FFF_2000
UART16550 (in FPGA integrated)
UART0 base address:
UART1 base address (not available):
UART2 base address (not available):
0x0_1FFF_4000
0x0_1FFF_5000
0x0_1FFF_6000
ATA/IDE (ATA0_CS#, ATA1_CS# )
ATA0 base address:
ATA1 base address:
0x0_1FFF_A000
0x0_1FFF_B000
CAN (CAN0_CS#, CAN1_CS# )
CAN0 base address:
EXM32_AU1250_User-Manual-V10.doc
0x0_1FFF_C000
page 86 of 110
EXM32 AU1250 CPU Module - User’
s Manual
CAN1 base address:
© MSC Vertriebs GmbH
0x0_1FFF_D000
Ethernet (ETH_CS#)
Ethernet base address:
6.2.3
0x0_1FFF_E000
Area 1
Area 1 contains the NAND Flash memory space. The Au1250 can be equipped with a optional 32 to
128 MByte NAND Flash memory device.
NAND Flash (LBSC_RCS1#)
NAND Flash base address:
6.2.4
0x0_2000_0000
Area 2
The AU1250 CPU provides the Chip Selects AU_CF_CE1#, AU_CF_CE2# instead of LBSC-RCS2.
Refer to the Au1250 Datasheet for details. X1C_A26 and consequently X1A_CF_SCKSEL determines
if Compact Flash or an IDE drive is selected.
X1C_A26 (X1A_CF_SCKSEL) = 0
X1C_A26 (X1A_CF_SCKSEL) = 1
Compact Flash Socket A
Compact Flash Socket B
Compact Flash: (AU_CF_CE1#, AU_CF_CE2#)
Compact Flash base address:
6.2.5
0xF_0000_0000
Area 3
The Area 3 Address Space is reserved for peripheral devices like SRAM or I/O devices.
CSA (X1C_CSA#))
CSA base address:
0x0_3000_0000
The CSA address space is reserved for 16-bit devices
CSB (X1C_CSB#))
CSB base address:
0x0_3400_0000
The CSB address Space is reserved for 32-bit devices
FPGA Register (in FPGA integrated)
FPGA base address:
0x0_3FFF_0000
I2C (in FPGA integrated)
EXM32_AU1250_User-Manual-V10.doc
page 87 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
I2C1 base address:
0x0_3FFF_1000
I2CDDC base address:
0x0_3FFF_1800
SPI (in FPGA integrated)
SPI base address:
0x0_3FFF_2000
UART16550 (in FPGA integrated)
UART1 (COM1) base address:
UART2 base address (not available):
UART3 base address (not available):
0x0_3FFF_4000
0x0_3FFF_5000
0x0_3FFF_6000
CAN (CAN0_CS#, CAN1_CS# )
CAN0 base address:
CAN1 base address:
0x0_3FFF_C000
0x0_3FFF_D000
Ethernet (ETH_CS#)
Ethernet base address:
EXM32_AU1250_User-Manual-V10.doc
0x0_3FFF_E000
page 88 of 110
EXM32 AU1250 CPU Module - User’
s Manual
6.3
© MSC Vertriebs GmbH
Interrupt Handling
There are two types of interrupt Sources:
-
Exerternal IRQ request
Integrated Peripheral modules
The AU1250 GPIO pins are configurable as a level sensitive or edge triggered interrupt Source.
6.3.1
IRQ
There are two interrupt controllers in the Au1250 processor. Each interrupt controller supports 32
interrupt sources. Each interrupt source is individually maskable to either enable or disable the core
from detecting the interrupt. Interrupts are generated by software, integrated interrupt controllers,
performance counters and timers. All interrupt sources are equal in priority; that is, the interrupt
sources are not prioritized in hardware. As a result, software determines the relative priority of the
interrupt sources. See the Au1250 datasheet and chapter 2.6.2 Interrupt Architecture and chapter 5
Interrupt Controller for details.
Interrupt sources connected to the Au1250:
Au1250
Interrupt
Active
Interrupt
Interrupt
Number
Controller
X1B_IRQ_EXT0#
low level
GPIO[0]
B9
0
1
X1B_IRQ_EXT1#
low level
GPIO[1]
C7
1
1
AU_RTC_IRQ#
low level
GPIO[2]
D8
2
1
FPGA_INT#
low level
GPIO[5]
C10
5
1
AU_WAKE_IRQ#
low level
GPIO[7]
A9
7
1
X1B_IRQ_MB2#
low level
GPIO[16]
C22
16
1
X1B_IRQ_MB0#
low level
GPIO[27]
D17
27
1
X1B_IRQ_MB1#
low level
GPIO[29]
C15
29
1
ETH_IRQ
high level
GPIO[31]
C21
31
1
AU_WATCHDOG
high level
GPIO[215] D20
28
0
The FPGA Interrupt is the described in chapter 1.1.2 IRQSTAT CPLD IRQ Status Register.
Port
Pin
The FPGA_INT# is the logical or of the signals:
Name
PWRFLT#
I2C0_INT#
I2C1_INT#
SPI_INT#
CF0_RDY_IRQ#
CF1_RDY_IRQ#
CF0_CD#
CF1_CD#
SDIO_CD#
UART1_INT
UART2_INT
UART3_INT
CAN0_INT#
CAN1_INT#
EXM32_AU1250_User-Manual-V10.doc
Description
Powerfault#
I2C-Controller 0 Interrupt
I2C-Controller 1 Interrupt
SPI_IRQ#
Compact
Flash
0
Ready
Interrupt
Compact
Flash
1
Ready
Interrupt
Compact Flash 0 Card Detect
Compact Flash 1 Card Detect
SDIO Card Detect
UART1 Interrupt
UART2 Interrupt (optional)
UART3 Interrupt (optional)
CAN-Controller 0 Interrupt
CAN-Controller 1 Interrupt
page 89 of 110
Source
EXM32-Connector
Au1250 CPU Module
Au1250 CPU Module
Au1250 CPU Module
EXM32-Connector
EXM32-Connector
EXM32-Connector
EXM32-Connector
EXM32-Connector
Au1250 CPU Module
Au1250 CPU Module
Au1250 CPU Module
Au1250 CPU Module
Au1250 CPU Module
EXM32 AU1250 CPU Module - User’
s Manual
CAN0_ERR#
CAN1_ERR#
CAN-Controller 0 Error
CAN-Controller 1 Error
© MSC Vertriebs GmbH
Au1250 CPU Module
Au1250 CPU Module
To detect the wake-up interrupt source the Interrupt Status register has to be read out. Refer to
section 1.1.2 IRQSTAT CPLD IRQ Status Register for details.
The AU_WAKE_IRQ# is the logical or of the signals:
Name
AU_PM_WAKE#
WAKEUP
IRQ_EXT1#
IRQ_EXT0#
IRQ_MB2#
IRQ_MB1#
IRQ_MB0#
WATCHDOG
ETH_IRQ
Description
Wake up from hibernate
Source
Au1250
EXM32-Connector
EXM32-Connector
EXM32-Connector
EXM32-Connector
EXM32-Connector
EXM32-Connector
Extension module 1 Interrupt
Extension module 0 Interrupt
Motherboard 2 Interrupt
Motherboard 1 Interrupt
Motherboard 0 Interrupt
Externer
Watchdogtimer
Au1250 CPU module
Interrupt (optional)
Ethernet Interrupt
Au1250 CPU module
Both Signals FPGA_INT#, AU_WAKE_IRQ# and AU_RTC_IRQ# can generate a Wake up interrupt
to the Au1250 CPU.
EXM32_AU1250_User-Manual-V10.doc
page 90 of 110
EXM32 AU1250 CPU Module - User’
s Manual
6.4
6.4.1
Au1250 Initialisation
© MSC Vertriebs GmbH
(preliminary)
Clock
CPU PLL Control
sys_cpupll
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
Address: 0x0_1190_0060
31
0
0
0
0
0
30
0
0
0
0
0
29
0
0
0
0
0
28
0
0
0
0
0
27
0
0
0
0
0
26
0
0
0
0
0
25
0
0
0
0
0
24
0
0
0
0
0
23
0
0
0
0
0
22
0
0
0
0
0
15
0
0
0
0
0
14
0
0
0
0
0
13
0
0
0
0
0
12
0
0
0
0
0
11
0
0
0
0
0
10
0
0
0
0
0
9
0
0
0
0
0
8
0
0
0
0
0
7
0
0
0
0
0
6
0
0
0
0
0
21
0
0
0
0
0
20
0
0
0
0
0
19
0
0
0
0
0
18
0
0
0
0
0
17
0
0
0
0
0
16
0
0
0
0
0
5
4
3
2
1
0
R
R
R
R
R
R
1
1
0
0
1
0
1
0
1
0
0
1
0
0
0
W
W
W
W
W
W
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0x0000001C (INIT (336Mhz))
0x00000021 (INIT (396Mhz))
0x00000029 (INIT (492Mhz))
0x00000032 (INIT (600Mhz))
6.4.2
Bus State Controller
6.4.2.1 Configuration for RCS0 (SRAM/ On-board Peripherals)
Chip Select 0 Configuration Register
mem_stcfg0
Address: 0x0_1400_1000
BIT
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
11
R
0
0
0
BIT
15
14
13
12
R
R
R
R
R
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
0
0
0
1
1
1
W
W
W
W
W
1
0
0
0
0
0
EXM32_AU1250_User-Manual-V10.doc
W
W
W
W
W
W
W
W
DEFAULT
1
0
0
0
0
1
0
0
0
0
24
R
0
0
0
0
0
23
R
0
0
0
0
0
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
W
W
W
W
W
W
W
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
page 91 of 110
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
1
0
0
1
0
0
EXM32 AU1250 CPU Module - User’
s Manual
0
0
INIT (492Mhz)
INIT (600Mhz)
0x003D40C0
0x003D40C0
0x003D60C0
0x003D40C0
1
1
1
0
0
0
0
0
0
0
© MSC Vertriebs GmbH
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
(INIT (336Mhz))
(INIT (396Mhz))
(INIT (492Mhz))
(INIT (600Mhz))
Chip Select 0 Timing Register
mem_sttime0
Address: 0x0_1400_1004
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
1
0
0
0
0
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
1
0
0
0
0
1
1
1
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
0
0
0
0
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0x06610002
0x06610002
0x06610002
0x06610002
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
0
1
1
1
1
1
0
0
0
0
(INIT (336Mhz))
(INIT (396Mhz))
(INIT (492Mhz))
(INIT (600Mhz))
Chip Select 0 Adress Region Register
mem_staddr0
BIT
R
W
DEFAULT
INIT
Address: 0x0_1400_1008
31
R
0
0
30
R
0
0
29
R
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
1
1
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
INIT
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0x10003000
EXM32_AU1250_User-Manual-V10.doc
page 92 of 110
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
1
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
6.4.2.2 Configuration for RCS1 (NAND-Flash)
Chip Select 1 Configuration Register
mem_stcfg1
Address: 0x0_1400_1010
BIT
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
1
0
0
0
0
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
11
R
0
0
0
0
0
BIT
15
14
13
12
R
R
R
R
R
DEFAULT
0
0
0
0
0
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
W
W
W
W
W
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
DEFAULT
1
0
0
0
0
1
0
0
0
0
24
R
0
0
0
0
0
23
R
0
0
0
0
0
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
W
W
W
W
W
W
W
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
W
W
W
W
W
W
W
W
W
W
W
1
0
0
0
0
1
1
1
1
1
0x00450045 (INIT (336Mhz))
0x00450045 (INIT (396Mhz))
0x00450045 (INIT (492Mhz))
0x00450045 (INIT (600Mhz))
Chip Select 1 Timing Register
mem_sttime1
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0x00006664
0x00007774
0x00009996
0x00007774
Address: 0x0_1400_1014
31
R
1
0
0
0
0
30
R
1
0
0
0
0
29
R
1
0
0
0
0
28
R
1
0
0
0
0
15
R
1
0
0
0
0
14
R
1
1
1
1
1
13
R
1
1
1
1
1
12
R
1
1
1
1
1
27
R
1
0
0
0
0
26
R
1
0
0
0
0
25
R
1
0
0
0
0
23
R
1
0
0
0
0
22
R
1
0
0
0
0
21
R
1
0
0
0
0
20
R
1
0
0
0
0
19
R
1
0
0
0
0
18
R
1
0
0
0
0
17
R
1
0
0
0
0
16
R
1
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
1
1
page 93 of 110
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
W
W
W
W
W
W
W
W
W
W
W
W
1
0
0
0
0
(INIT (336Mhz))
(INIT (396Mhz))
(INIT (492Mhz))
(INIT (600Mhz))
EXM32_AU1250_User-Manual-V10.doc
24
R
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Chip Select 1 Adress Region Register
mem_staddr1
BIT
R
W
DEFAULT
INIT
Address: 0x0_1400_1018
31
R
0
0
30
R
0
0
29
R
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
1
0
1
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
1
0
1
0
0x12503C00
6.4.2.3 Configuration for RCS2 (Compact Flash/ PCMCIA)
Chip Select 2 Configuration Register
mem_ stcfg2
Address: 0x0_1400_1020
BIT
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
11
R
0
0
0
0
0
BIT
15
14
13
12
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0
0
0
0
0
1
0
0
0
0
W
W
W
W
W
DEFAULT
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
DEFAULT
1
0
0
0
0
1
0
0
0
0
23
R
0
0
0
0
0
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
W
W
W
W
W
W
W
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
page 94 of 110
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
0
0
0
0
0
0x00040042 (INIT (336Mhz))
0x00040042 (INIT (396Mhz))
0x00040042 (INIT (492Mhz))
0x00040042 (INIT (600Mhz))
EXM32_AU1250_User-Manual-V10.doc
24
R
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Chip Select 2 Timing Register
mem_sttime2
Address: 0x0_1400_1024
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
1
1
0
0
0
1
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
0
0
0
0
0
1
1
0
0
0
0x1F1A3BED (INIT (336Mhz))
0x262044D0 (INIT (396Mhz))
0x2F2855F4 (INIT (492Mhz))
0x262044D0 (INIT (600Mhz))
Chip Select 2 Adress Region Register
mem_staddr2
BIT
R
W
DEFAULT
INIT
Address: 0x0_1400_1028
31
R
0
0
30
R
0
0
29
R
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
0
1
1
0
1
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
INIT
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0x18003C00
EXM32_AU1250_User-Manual-V10.doc
page 95 of 110
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
1
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
6.4.2.4 Configuration for RCS3 (External Devices)
Chip Select 3 Configuration Register
mem_stcfg3
Address: 0x0_1400_1030
BIT
31
30
29
28
27
26
25
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
11
R
0
0
0
0
0
BIT
15
14
13
12
R
R
R
R
R
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0x222C00C0
0x222C00C0
0x422C00C0
0x222C00C0
0
0
0
0
0
1
0
0
0
0
W
W
W
W
W
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
DEFAULT
1
0
0
0
0
1
1
1
1
1
24
R
0
0
0
0
0
23
R
0
0
0
0
0
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
W
W
W
W
W
W
W
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
1
0
0
0
0
1
0
0
0
0
(INIT (336Mhz))
(INIT (396Mhz))
(INIT (492Mhz))
(INIT (600Mhz))
Chip Select 3 Timing Register
mem_sttime3
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
Address: 0x0_1400_1014
31
R
0
0
0
0
0
30
R
0
0
0
0
0
29
R
0
0
0
1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
1
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
1
1
1
0
0
0
0
1
1
1
0
1
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0x1231C58B (INIT (336Mhz))
0x123205CD (INIT (396Mhz))
EXM32_AU1250_User-Manual-V10.doc
1
0
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
0
0
0
0
0x22428A8F (INIT (492Mhz))
0x123205CD (INIT (600Mhz))
page 96 of 110
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
1
1
0
1
0
1
1
1
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Chip Select 3 Adress Region Register
mem_staddr3
BIT
R
W
DEFAULT
INIT
Address: 0x0_1400_1018
31
R
0
0
30
R
0
0
29
R
0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
R
R
R
R
R
0
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
1
0
1
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
1
0
1
0
0x14003C00
6.4.2.5 Global Chip Select Configuration
Addresslatch Timing Register
mem_staltime
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
Address: 0x0_1400_1040
31
-
30
-
29
-
28
-
27
-
26
-
25
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
0x00000049 (INIT (336Mhz))
0x00000049 (INIT (396Mhz))
0x00000049 (INIT (492Mhz))
0x00000049 (INIT (492Mhz))
EXM32_AU1250_User-Manual-V10.doc
page 97 of 110
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
W
W
W
W
W
W
W
W
W
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Static Bus NAND Control Register
mem_stndctrl
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1400_1100
31
-
30
-
29
-
28
-
27
-
26
-
25
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
3
R
0
2
R
0
1
R
0
8
7
6
5
4
R
R
R
R
R
0
1
0
0
0
0
W
W
W
W
W
0
0
0
0
16
0
R
W
1
0
0x00000100
6.4.3
DDR2 Memory Controller
Chip Select 0 Timing Register
mem_sdmode0
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
31
15
-
Address: 0x0_1400_0800
30
-
29
-
28
-
27
11
-
14
13
12
R
R
R
1
0
0
0
0
W
W
W
1
1
1
1
1
1
0
0
1
0
26
25
24
R
R
R
1
0
0
1
0
1
1
1
0
1
10
9
8
R
R
R
1
0
0
0
0
W
W
W
1
1
1
1
1
0x01272224 (INIT (336Mhz))
0x01272224 (INIT (396Mhz))
0x02393335 (INIT (492Mhz))
0x01272224 (INIT (600Mhz))
EXM32_AU1250_User-Manual-V10.doc
W
W
W
1
0
0
0
0
page 98 of 110
1
0
0
1
0
23
7
-
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
1
1
1
1
1
0
0
1
0
1
0
0
1
0
3
-
6
5
4
R
R
R
1
0
0
0
0
W
W
W
1
1
1
1
1
1
0
0
1
0
1
1
1
0
1
W
W
W
W
W
W
W
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
2
1
0
R
R
R
1
1
1
1
1
W
W
W
1
0
0
0
0
1
0
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Chip Select 1 Timing Register
mem_sdmode1
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
BIT
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
Address: 0x0_1400_0808
31
15
-
30
-
29
-
28
-
27
11
-
14
13
12
R
R
R
W
W
W
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
26
25
24
R
R
R
W
W
W
1
0
0
0
0
1
0
0
1
0
1
1
1
0
1
10
9
8
R
R
R
W
W
W
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
23
7
-
22
21
20
19
18
17
16
R
R
R
R
R
R
R
1
1
1
1
1
1
0
0
1
0
1
0
0
1
0
3
-
6
5
4
R
R
R
W
W
W
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
1
1
0
1
W
W
W
W
W
W
W
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
2
1
0
R
R
R
W
W
W
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0x01272224 (INIT (336Mhz))
0x01272224 (INIT (396Mhz))
0x02393335 (INIT (492Mhz))
0x01272224 (INIT (600Mhz))
Chip Select 0 Adress Configuration and Enable
mem_sdaddr0
BIT
Address: 0x0_1400_0820
31
R
30
29
28
R
R
R
DEFAULT
INIT
0
0
0
W
W
W
W
0
1
0
1
27
0
26
25
24
R
R
R
0
1
W
W
W
0
0
1
0
23
0
22
0
21
0
20
19
18
17
16
R
R
R
R
R
0
1
1
0
1
1
W
W
W
W
W
1
0
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0x341503E0
EXM32_AU1250_User-Manual-V10.doc
page 99 of 110
1
1
1
1
1
1
1
1
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
1
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Chip Select 1 Adress Configuration and Enable
mem_sdaddr1
BIT
Address: 0x0_1400_0828
31
R
30
29
28
R
R
R
DEFAULT
INIT
0
0
0
W
W
W
W
0
1
0
1
27
0
26
25
24
R
R
R
0
1
W
W
W
0
0
1
0
23
0
22
0
21
0
20
19
18
17
16
R
R
R
R
R
0
1
1
0
1
1
W
W
W
W
W
1
0
1
1
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
1
0
1
0
0x341583E0
Global Configuration Register A
mem_sdconfiga
BIT
31
R
R
W
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
1
0
0
0
0
Address: 0x0_1400_0840
30
-
29
28
27
26
25
24
23
22
21
20
R
R
R
R
R
R
R
R
R
R
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
W
W
W
W
W
W
W
W
W
W
0
1
1
1
1
1
0
0
0
0
1
1
0
1
0
19
-
18
-
17
16
R
R
W
W
1
0
0
0
0
1
0
0
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
W
DEFAULT
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
W
1
0
0
0
0
W
1
0
0
0
0
W
1
0
0
0
0
W
1
0
0
0
0
W
1
0
0
0
0
W
1
1
1
1
1
W
1
0
1
1
1
0x31100520 (INIT (336Mhz))
0x3140060A (INIT (396Mhz))
0x31900781 (INIT (492Mhz))
0x3140060A (INIT (600Mhz))
EXM32_AU1250_User-Manual-V10.doc
page 100 of 110
W
1
1
0
1
0
W
1
0
0
1
0
W
1
0
0
0
0
W
1
1
0
0
0
W
1
0
0
0
0
W
1
0
1
0
1
W
1
0
0
0
0
W
1
0
1
0
1
W
1
0
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Global Configuration Register B
mem_sdconfigb
Address: 0x0_1400_0848
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
R
R
R
R
R
R
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
-
BIT
15
14
13
12
11
10
9
8
7
R
R
R
R
R
R
R
R
R
R
INIT (336Mhz)
INIT (396Mhz)
INIT (492Mhz)
INIT (600Mhz)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
DEFAULT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
0
0
0
0
0
0
0
0
0
0
18
-
17
16
R
R
W
W
0
1
1
1
1
0
0
0
0
0
5
4
3
2
1
0
R
R
R
R
R
R
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
W
W
W
W
W
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xA002000C (INIT (336Mhz))
0xA002000C (INIT (396Mhz))
0xA002000C (INIT (492Mhz))
0xA002000C (INIT (600Mhz))
6.4.4
Interrupt Controller
Setting up the GPIOs Controller as Interrupts
sys_pinfunc
BIT
R
W
DEFAULT
INIT
Address: 0x0 1190002C
31
R
0
1
30
R
0
1
29
R
0
0
28
R
0
0
27
R
0
0
26
R
0
1
25
R
0
1
24
R
0
0
23
R
0
0
22
R
1
0
21
R
1
0
20
R
1
0
19
R
1
1
18
R
1
1
17
R
1
0
16
R
0
0
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
1
1
1
-
1
0
0
1
0
0
0
0
0xC60CCCCC
EXM32_AU1250_User-Manual-V10.doc
page 101 of 110
0
0
0
1
0
1
1
0
1
0
1
1
1
1
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
-
-
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
sys_trioutclr
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0 11900100
31
W
0
0
30
W
0
0
29
W
0
0
28
W
0
0
27
W
0
0
26
W
0
0
25
W
0
0
24
W
0
0
23
W
0
0
22
W
0
0
21
W
0
0
20
W
0
1
19
W
0
1
18
W
0
1
17
W
0
1
16
W
0
0
15
W
0
0
14
W
0
0
13
-
12
W
0
0
11
W
0
0
10
W
0
1
9
W
0
1
8
W
0
1
7
W
0
0
6
W
0
0
5
W
0
0
4
W
0
0
3
W
0
1
2
W
0
0
1
-
0
-
0x100E0708
sys_outputclr
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0 1190010C
31
W
0
30
W
0
29
W
0
28
W
0
27
W
0
26
W
0
25
W
0
24
W
0
23
W
0
22
W
0
21
W
0
20
W
0
19
W
0
18
W
0
17
W
0
16
W
0
15
W
0
14
W
0
13
W
0
12
W
0
11
W
0
10
W
0
9
W
0
8
W
0
7
W
0
6
W
0
5
W
0
4
W
0
3
W
0
2
W
0
1
W
0
0
W
0
0x00000000
Setting GPIO Block 2 Port Direction
gpio2_dir
BIT
R
W
DEFAULT
INIT
Address: 0x0_1170_0000
31
R
0
-
30
R
0
-
29
R
0
-
28
R
0
-
27
R
0
-
26
R
0
-
25
R
0
-
24
R
0
-
23
R
0
-
22
R
0
-
21
R
0
-
20
R
0
-
19
R
0
-
18
R
0
-
17
R
0
-
16
R
0
-
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000000
EXM32_AU1250_User-Manual-V10.doc
page 102 of 110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
0
0
1
0
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Enable GPIOs Block 2 as a Interrupt Source
gpio2_inten
BIT
R
W
DEFAULT
INIT
Address: 0x0_1170_0010
31
R
0
-
30
R
0
-
29
R
0
-
28
R
0
-
27
R
0
-
26
R
0
-
25
R
0
-
24
R
0
-
23
R
0
-
22
R
0
-
21
R
0
-
20
R
0
-
19
R
0
-
18
R
0
-
17
R
0
-
16
R
0
-
7
R
0
-
6
R
0
-
5
R
0
-
4
R
0
-
3
R
0
-
2
R
0
-
1
R
0
-
0
R
1
-
BIT
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
R
0
1
0
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
W
DEFAULT
INIT
0
0
0
0
0x00008000
Enable Block 2
gpio2_enable
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1170_0014
31
R
0
-
30
R
0
-
29
R
0
-
28
R
0
-
27
R
0
-
26
R
0
-
25
R
0
-
24
R
0
-
23
R
0
-
22
R
0
-
21
R
0
-
20
R
0
-
19
R
0
-
18
R
0
-
15
R
0
-
14
R
0
-
13
R
0
-
12
R
0
-
11
R
0
-
10
R
0
-
9
R
0
-
8
R
0
-
7
R
0
-
6
R
0
-
5
R
0
-
4
R
0
-
3
R
0
-
2
R
0
-
17
R
0
-
16
R
0
-
1
0
R
R
W
W
1
0
0
1
0x00000001
Interrupt Controller 0 Configuration Register
The Bits in the Following Registers correspond with the interrupt described in the Following Table.
Refer to the Au1250 Datasheet chapter 5.1 Interrupt Controller sources
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NAME
MAE Done
LCD Controll
USB Controller
GPIO[208:215]
GPIO[207]
GPIO[206]
GPIO[205]
GPIO[204]
NAND Controlller
GPIO[203]
RTC Match 2
RTC Match 1
RTC Match 0
RTC(tick)
TOY Match 2
DESCRIPTION
Optional external Watchdog Timer Interrupt (GPIO215)
Not Used
Not Used
Not Used
Not Used
Not Used
EXM32_AU1250_User-Manual-V10.doc
page 103 of 110
EXM32 AU1250 CPU Module - User’
s Manual
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TOY Match 1
TOY Match 0
TOY (tick)
Camera
Interface
Module
AES Cryptographie
Engine
PSC1
PSC0
MAE Frontend
UART1
GPIO[202]
GPIO[201]
GPIO[200]
MAE Backend
DDMA Controller
Secure
Digital
Decoder
Software
Counter
Match
UART0
© MSC Vertriebs GmbH
Not Used
Not Used
Not Used
ic_cfg0set
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0040
31
W
?
0
30
W
?
0
29
W
?
0
28
W
?
0
27
W
?
0
26
W
?
0
25
W
?
0
24
W
?
0
23
W
?
0
22
W
?
0
21
W
?
0
20
W
?
0
19
W
?
0
18
W
?
0
17
W
?
0
16
W
?
0
15
W
?
0
14
W
?
0
13
W
?
0
12
W
?
0
11
W
?
0
10
W
?
0
9
W
?
0
8
W
?
0
7
W
?
0
6
W
?
0
5
W
?
0
4
W
?
0
3
W
?
0
2
W
?
0
1
W
?
0
0
W
?
0
0x00000000
ic_cfg1set
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0048
31
W
?
0
30
W
?
0
29
W
?
0
28
W
?
1
27
W
?
0
26
W
?
0
25
W
?
0
24
W
?
0
23
W
?
0
22
W
?
0
21
W
?
0
20
W
?
0
19
W
?
0
18
W
?
0
17
W
?
0
16
W
?
0
15
W
?
0
14
W
?
0
13
W
?
0
12
W
?
0
11
W
?
0
10
W
?
0
9
W
?
0
8
W
?
0
7
W
?
0
6
W
?
0
5
W
?
0
4
W
?
0
3
W
?
0
2
W
?
0
1
W
?
0
0
W
?
0
0x10000000
EXM32_AU1250_User-Manual-V10.doc
page 104 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
ic_cfg2set
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0050
31
W
?
0
30
W
?
0
29
W
?
0
28
W
?
1
27
W
?
0
26
W
?
0
25
W
?
0
24
W
?
0
23
W
?
0
22
W
?
0
21
W
?
0
20
W
?
0
19
W
?
0
18
W
?
0
17
W
?
0
16
W
?
0
15
W
?
0
14
W
?
0
13
W
?
0
12
W
?
0
11
W
?
0
10
W
?
0
9
W
?
0
8
W
?
0
7
W
?
0
6
W
?
0
5
W
?
0
4
W
?
0
3
W
?
0
2
W
?
0
1
W
?
0
0
W
?
0
0x10000000
Interrupt Controller 0 Source Select Register
ic_srcset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0058
31
W
?
1
30
W
?
1
29
W
?
1
28
W
?
1
27
W
?
1
26
W
?
1
25
W
?
1
24
W
?
1
23
W
?
1
22
W
?
1
21
W
?
1
20
W
?
1
19
W
?
1
18
W
?
1
17
W
?
1
16
W
?
1
15
W
?
1
14
W
?
1
13
W
?
1
12
W
?
1
11
W
?
1
10
W
?
1
9
W
?
1
8
W
?
1
7
W
?
1
6
W
?
1
5
W
?
1
4
W
?
1
3
W
?
1
2
W
?
1
1
W
?
1
0
W
?
1
0xFFFFFFFF
Interrupt Assignment Register 0
ic_assignset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0060
31
W
?
1
30
W
?
1
29
W
?
1
28
W
?
1
27
W
?
1
26
W
?
1
25
W
?
1
24
W
?
1
23
W
?
1
22
W
?
1
21
W
?
1
20
W
?
1
19
W
?
1
18
W
?
1
17
W
?
1
16
W
?
1
15
W
?
1
14
W
?
1
13
W
?
1
12
W
?
1
11
W
?
1
10
W
?
1
9
W
?
1
8
W
?
1
7
W
?
1
6
W
?
1
5
W
?
1
4
W
?
1
3
W
?
1
2
W
?
1
1
W
?
1
0
W
?
1
0xFFFFFFFF
EXM32_AU1250_User-Manual-V10.doc
page 105 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Interrupt STAT Register 0
ic_STATset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1040_0070
31
W
0
0
30
W
0
0
29
W
0
0
28
W
0
1
27
W
0
0
26
W
0
0
25
W
0
0
24
W
0
0
23
W
0
0
22
W
0
0
21
W
0
0
20
W
0
0
19
W
0
0
18
W
0
0
17
W
0
0
16
W
0
0
15
W
0
0
14
W
0
0
13
W
0
0
12
W
0
0
11
W
0
0
10
W
0
0
9
W
0
0
8
W
0
0
7
W
0
0
6
W
0
0
5
W
0
0
4
W
0
0
3
W
0
0
2
W
0
0
1
W
0
0
0
W
0
0
0x10000000
6.4.4.1 Interrupt Controller 1
Interrupt Controller 1 Configuration Register
The Signal in the Following Table corresponds with the according Bit in the following Interrupt register
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
GPIO[31]
GPIO[30]
GPIO[29]
GPIO[28]
GPIO[27]
GPIO[26]
GPIO[25]
GPIO[24]
GPIO[23]
GPIO[22]
GPIO[21]
GPIO[20]
GPIO[19]
GPIO[18]
GPIO[17]
GPIO[16]
GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
GPIO[9]
GPIO[8]
GPIO[7]
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]
DESCRIPTION
ETH_IRQ
not used
X1B_IRQ_MB1#
not used
X1B_IRQ_MB0#
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
X1B_IRQ_MB2#
not used
not used
not used
AU_DREQ1#
not used
not used
not used
not used
AU_WAKE_IRQ#
not used
FPGA_INT#
AU_DREQ0#
not used
AU_RTC_IRQ#
X1B_IRQ_EXT1#
X1B_IRQ_EXT0#
EXM32_AU1250_User-Manual-V10.doc
page 106 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
ic_cfg0set
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0040
31
W
?
1
30
W
?
0
29
W
?
0
28
W
?
0
27
W
?
0
26
W
?
0
25
W
?
0
24
W
?
0
23
W
?
0
22
W
?
0
21
W
?
0
20
W
?
0
19
W
?
0
18
W
?
0
17
W
?
0
16
W
?
0
15
W
?
0
14
W
?
0
13
W
?
0
12
W
?
0
11
W
?
0
10
W
?
0
9
W
?
0
8
W
?
0
7
W
?
0
6
W
?
0
5
W
?
0
4
W
?
0
3
W
?
0
2
W
?
0
1
W
?
0
0
W
?
0
0x80000000
ic_cfg1set
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0048
31
W
?
0
30
W
?
0
29
W
?
1
28
W
?
0
27
W
?
1
26
W
?
0
25
W
?
0
24
W
?
0
23
W
?
0
22
W
?
0
21
W
?
0
20
W
?
0
19
W
?
0
18
W
?
0
17
W
?
0
16
W
?
1
15
W
?
0
14
W
?
1
13
W
?
0
12
W
?
0
11
W
?
0
10
W
?
1
9
W
?
0
8
W
?
0
7
W
?
1
6
W
?
0
5
W
?
1
4
W
?
1
3
W
?
0
2
W
?
1
1
W
?
1
0
W
?
1
0x280144A7
ic_cfg2set
Address: 0x0_1180_0050
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
?
1
W
?
0
W
?
1
W
?
0
W
?
1
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
0
W
?
1
DEFAULT
15
W
?
14
W
?
13
W
?
12
W
?
11
W
?
10
W
?
9
W
?
8
W
?
7
W
?
6
W
?
5
W
?
4
W
?
3
W
?
2
W
?
1
W
?
0
W
?
INIT
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
1
W
DEFAULT
INIT
BIT
R
W
0x280144A7
EXM32_AU1250_User-Manual-V10.doc
page 107 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Interrupt Controller 1 Source Select Register
ic_srcset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0058
31
W
?
1
30
W
?
1
29
W
?
1
28
W
?
1
27
W
?
1
26
W
?
1
25
W
?
1
24
W
?
1
23
W
?
1
22
W
?
1
21
W
?
1
20
W
?
1
19
W
?
1
18
W
?
1
17
W
?
1
16
W
?
1
15
W
?
1
14
W
?
1
13
W
?
1
12
W
?
1
11
W
?
1
10
W
?
1
9
W
?
1
8
W
?
1
7
W
?
1
6
W
?
1
5
W
?
1
4
W
?
1
3
W
?
1
2
W
?
1
1
W
?
1
0
W
?
1
0xFFFFFFFF
Interrupt Assignment Register 1
ic_assignset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0060
31
W
?
1
30
W
?
1
29
W
?
1
28
W
?
1
27
W
?
1
26
W
?
1
25
W
?
1
24
W
?
1
23
W
?
1
22
W
?
1
21
W
?
1
20
W
?
1
19
W
?
1
18
W
?
1
17
W
?
1
16
W
?
1
15
W
?
1
14
W
?
1
13
W
?
1
12
W
?
1
11
W
?
1
10
W
?
1
9
W
?
1
8
W
?
1
7
W
?
1
6
W
?
1
5
W
?
1
4
W
?
1
3
W
?
1
2
W
?
1
1
W
?
1
0
W
?
1
0xFFFFFFFF
Wake up Source Selection
ic_wakeset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0068
31
W
0
0
30
W
0
0
29
W
0
0
28
W
0
0
27
W
0
0
26
W
0
0
25
W
0
0
24
W
0
0
23
W
0
0
22
W
0
0
21
W
0
0
20
W
0
0
19
W
0
0
18
W
0
0
17
W
0
0
16
W
0
0
15
W
0
0
14
W
0
0
13
W
0
0
12
W
0
0
11
W
0
0
10
W
0
0
9
W
0
0
8
W
0
0
7
W
0
1
6
W
0
0
5
W
0
1
4
W
0
0
3
W
0
0
2
W
0
0
1
W
0
0
0
W
0
0
0x000000A0
EXM32_AU1250_User-Manual-V10.doc
page 108 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
Interrupt STAT Register 1
ic_STATset
BIT
R
W
DEFAULT
INIT
BIT
R
W
DEFAULT
INIT
Address: 0x0_1180_0070
31
W
0
1
30
W
0
0
29
W
0
1
28
W
0
0
27
W
0
1
26
W
0
0
25
W
0
0
24
W
0
0
23
W
0
0
22
W
0
0
21
W
0
0
20
W
0
0
19
W
0
0
18
W
0
0
17
W
0
0
16
W
0
1
15
W
0
0
14
W
0
1
13
W
0
0
12
W
0
0
11
W
0
0
10
W
0
1
9
W
0
0
8
W
0
0
7
W
0
1
6
W
0
0
5
W
0
1
4
W
0
0
3
W
0
0
2
W
0
1
1
W
0
1
0
W
0
1
0xA8014497
EXM32_AU1250_User-Manual-V10.doc
page 109 of 110
EXM32 AU1250 CPU Module - User’
s Manual
© MSC Vertriebs GmbH
7 Appendix
7.1
ID-EEPROM Register Map
EEPROM-Content
Field
Boot Counter
Offset
0x000
Size
(Byte)
4
Format
Content (hex), Example
Binary
C8 45 00 00
0x004
6
BCD
24 12 04 20 18 15
Content
(ASCII),
Example
Manufacturin
g Date
Maintenance
Time
HW Platform
0x00A
6
BCD
01 07 05 20 10 45
0x010
16
ASCII
HW Revision
0x020
16
ASCII
4D 53 43 20 45 58 4D 2D
53 48 37 37 36 30 00 00
34 30 2D 61 62 63 64 65
66 67 68 69 00 00 00 00
MSC
EXMSH7760
40-abcdefghi
Serial
Number
0x030
16
ASCII
30 33 30 30 30 39 36 30
30 31 31 2D 31 00 00 00
03000960011
User-Area
0x080
1968
User specific
User specific
ASCII-Fields must be terminated by 0x00.
Binary: LSB on lowest address, ascending
Manufacturing Date, Maintenance Time:
o 0, when not supported
o BCD: Day,Month,Year,Hour,Minute
Location of the ID-EEPROM
Hardware
I2C Bus
EXM32 AU1250
0
Device Adr.
0xA0
Size:
2048 Byte
Partitioning System area: 0x000 -0x07F (128 Byte)
User area: 0x080-0x7FF (11968 Byte)
Speed:
400 kHz
Protocol: 8 Bit Register-Offset
EXM32_AU1250_User-Manual-V10.doc
page 110 of 110
Offset
0x00
Remarks
Counter=17864,
increased by bootloader
Production Date, e.g.
24.12.2004, 18:15
Last
Service, e.g.
01.07.2005, 10:45
Board ID String
40: V4.0
abc… : Board Revision
and Variant Code
10-digit series number
(Also on barcode-label
on the module )
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