Method and apparatus for rearranging data between multiple registers

US007631025B2
(12) Ulllted States Patent
(10) Patent N0.:
Debes et a].
(54)
(75)
US 7,631,025 B2
(45) Date of Patent:
Dec. 8, 2009
METHOD AND APPARATUS FOR
REARRANGING DATA BETWEEN MULTIPLE
4,418,383 A
4,490,786 A
11/1983 Doyle et al.
12/1984 Nakatani
REGISTERS
4,498,177 A
Inventors: Eric L. Debes, Santa Clara, CA (US);
4’707’800 A
William W. Macy, Jr., Palo A110, CA
4,771,379 A
9/1988 And" ‘ft a1~
(US); Patrice L. Roussel, Portland, OR
4,903,228 A
2/1990 Gregolre et a1~
2/1985 Larson
11/1987 Montrone et al'
(US); Yen-Kuang Chen, Sunnyvale, CA
(Us)
(73) Assignee: Intel Corporation, Santa Clara, CA
(Continued)
(Us)
( * ) Notice:
OTHER PUBLICATIONS
5:221???loeilgn?sglfinségggi§l?llgitgig
Philips Electronics, “TriMedia TMlOOO Preliminary Data Book,”
U.S.C. 154(1)) by 528 days.
1997, 496
pgs
.
(21) Appl. No.: 10/612,061
(
Continued
)
Primary ExamineriDavid H MalZahn
(22) Filed:
Jun- 30, 2003
(74) Attorney, Agent, or FirmiBlakely, Sokoloff, Taylor &
Zafman LLP
(65)
Prior Publication Data
US 2004/0054878 A1
Mar. 18, 2004
(57)
ABSTRACT
Related US. Application Data
_
_
_
_
_
Method, apparatus, and program means for rearranging data
(63) E10 lzinnuglongg'gglg 10f applljcatll?n
e
on
(51)
Int Cl
52
U 5 Cl
Ct‘
)
(58)
I. .
’ now
at‘
O‘
’
’
betWeen multiple registers. The method of one embodiment
'
comprises shuffling ?rst set of packed data from a ?rst source
based on a ?rst set of masks to produce a ?rst set of shuffled
G08]? /01
(
’
2’891’
(200601)
data. The ?rst set of masks is to include a ?rst plurality of
708/209
control entr1es to set des1gnated data element pos1t1ons 1n the
. ...... .... ...... ... ................................... ..
Field of~Class1?cat1on Search .............
?rstsetofshuf?eddatato ZerO'Asecondpackeddatafroma
708/209
Second Source is shuffled based on a Second Set of masks to
See apphcanon ?le for Complete Search hlstory'
(56)
3,711,692
3,723,715
4,139,899
4,161,784
4,393,468
produce a second set of shuffled data. The second set of masks
References Cited
includes a secondplurality of control entries to set to Zero data
U.S. PATENT DOCUMENTS
element positions in the second set of shuffled data opposite
to said designated data element positions in the ?rst set of
A
A
A
A
A
shuffled data. The ?rst set of shuffled data and said second set
of shuffled data are merged together to form a packed data
resultant.
1/1973 Batcher
3/1973 Chen et al.
2/1979 Tulpule et a1.
7/1979 Cushing et a1.
7/1983 New
45 Claims, 30 Drawing Sheets
LOAD FIRST REGISTER DATA
1402
SHUFFLE FIRST REGISTER DATA BASED
ON FIRST SET OF MASKS
1404
LOAD SECOND REGISTER DATA
1405
SHUFFLE SECOND REGISTER DATA
BASED ON SECOND SET OF MASKS
LOGICAL OR MERGES TOGETHER
SHUFFLED FIRST AND SECOND
REGISTER DATA
1410
US 7,631,025 B2
Page 2
1/1991 Kurodaet al.
5/1991 Wang et al.
1/1992 Kohn
Intel Corporation, “i860 TM Microprocessor Family Programmer’s
Reference Manual,” 1992, Chapters 1, 3, 8 and 11.
Lee, R. B., “Accelerating Multimedia With Enhanced Microproces
sors,” IEEE Micro, Apr. 1995, pp. 22-32.
Intel Corporation, “Pentium Processor’s User’s Manual, vol. 3;
3/1992 Jeong
Architecture and Programming Manual,” 1993, Chapters 1, 3, 4, 6, 8,
US. PATENT DOCUMENTS
4,989,168 A
5,019,968 A
5,081,698 A
5,095,457 A
5,168,571
5,187,679
5,268,995
5,321,810
5,390,135
5,408,670
5,423,010
5,426,783
5,465,374
5,487,159
5,497,497
5,524,256
5,579,253
A
A
A
A
A
A
A
A
A
A
A
A
A
5,594,437 A
5,625,374
5,680,161
5,781,457
5,819,117
5,822,619
5,838,984
5,909,572
A
A
A
A
A
A
A
12/1992
2/1993
12/1993
6/1994
2/1995
4/1995
6/1995
6/1995
11/1995
1/1996
3/1996
6/1996
11/1996
Hooveretal.
Vassiliadis et al.
Diefendorffet al.
Case etal.
Lee et al.
Davies
Mizukami
Norrie et al.
Dinkjian et al.
Byers etal.
Miller et al.
Turkowski
Lee et al.
1/1997 O’Malley
4/1997
10/1997
7/1998
10/1998
10/1998
11/1998
6/1999
Turkowski
Lehman et al.
Cohen et al.
Hansen
Sidwell
Nguyen et al.
Thayer et al.
and 18.
Margulis, N., “i860 Microprocessor Architecture,” McGraW Hill,
Inc., 1990, Chapters 6, 7, 8, 10, and 11.
Intel Corporation, Intel i750, i860 TM, i960 Processors and Related
Products, 1993, pp. 1-3.
Motorola, Inc., “Motorola MC88110 Second Generation RISC
Microprocessor User’s Manual,” 1991.
Motorola, Inc., “Errata to MC88110 Second Generation RISC
Microprocessor User’s Manual,” 1992, pp. 1-11.
Motorola, Inc., MC88110 Programmer’s Reference Guide, 1992, pp.
1-4.
Shipnes, 1., “Graphics Processing With the 88110 RISC Micropro
cessor,” Motorola, Inc. IEEE, No. 0-8186-26455-0/92, 1992, pp.
169-174.
Advanced Micro Devices, Inc., “AMD-3D Technology Manual,”
Feb. 1998, pp. 1-58.
Hansen, C., “Architecture of a Broadband Mediaprocessor,” Pro
ceedings of Compcon, IEEE, 1996, pp. 334-340.
Levinthal, et al., “ChapiA SIMD Graphics Processor,” Computer
Graphics Project, ACM, vol. 18, No. 3, Jul. 1984, pp. 77-81.
Levinthal, et al., “Parallel Computers for Graphics Applications,”
5,933,650 A
8/1999 van Hook et al.
Proceedings: Second International Conference on Architectural Sup
6,041,404
6,115,812
6,192,467
6,211,892
3/2000
9/2000
2/2001
4/2001
port for Programming Languages and Operating Systems, (ASPLOS
A
A
B1
B1
6,223,277 B1
6,288,723 B1
6,381,690 B1
6,484,255 B1
6,546,480 B1
6,745,319 B1*
6,816,961 B2*
Rousselet al.
Abdallah et al.
Abdallah et al.
Huffet al.
4/2001 Karguth
9/2001 Huffet al.
4/2002 Lee
11/2002 Dulong
4/2003 Mandavilliet al.
6/2004
11/2004
Balmer et al. ............. .. 712/223
Rice et al. ................. .. 712/223
2001/0016902 A1
8/2001 Abdallah et al.
2002/0002666 A1*
1/2002 Dulong et al. ............ .. 712/224
2002/0112147
2002/0159529
2002/0172287
2003/0084082
A1
A1
A1
A1
2003/0123748 A1*
2003/0131030 A1*
2003/0231711 A1
2005/0188182 A1*
8/ 2002 Chennupaty et al.
10/2002 Wang et a1.
11/2002 Kim
II), IEEE, 1987, pp. 193-198.
Wang, et al., “A Processor Architecture for 3D Graphics Calcula
tions,” Computer Motion, Inc., Goleta, CA, 23 pgs, Sep. 1992.
US. Appl. 10/611,344 109 pages.
Non-Final Of?ce Action dated Dec. 29, 2005 for US. Appl. No.
10/611,344 21 pages.
Final Of?ce Action dated Sep. 20, 2006 for US. Appl. 10/611,344 26
pages.
Advisory Action dated Dec. 19, 2006 for US. Appl. 10/611,344 3
pages.
Non-Final Of?ce Action dated Apr. 4, 2007 for US. Appl.
10/611,344 22 pages.
Final Of?ce Action dated Dec. 27, 2007 for US. Appl. 10,611,344 17
pages.
Advisory Action dated Mar. 18, 2008 for US. Appl. 10,611,344 3
5/2003 Debes et al.
pages.
7/2003
7/2003
Notice of Abandonment dated Jul. 18, 2008 for US. Appl.
10,611,344 2 pages.
Petition Decision dated May 12, 2009 for US. Appl. 10,611,344 1
Sebot et a1. ............... .. 382/254
Sebot et a1. ............... .. 708/209
12/2003 Zhang et a1.
8/2005
Hoyle et a1. .............. .. 712/224
OTHER PUBLICATIONS
“MIPS Digital Media Extension,” Set Architecture Speci?cation,
page.
US. Appl. 10/612,592 108 pages.
Non-Final Of?ce Action dated Aug. 17, 2006 for US. Appl.
10/612,592 4 pages.
Final Of?ce Action dated Mar. 26, 2007 for US. Appl. 10/612,592 5
Web Siteimipscom/MDMXspecps, Oct. 21, 1997. 8 pgs.
HeWlet Packard, “64-bit and Multimedia Extensions in the PA-RISC
pages.
2.0 Architecture,” Microprocessors Precision Architecture, 1997, 18
Woody.imag.fr/MPEG4/syssite/syspub/docs/tutoriall, May 28, 1998,
PgS~
pp. 1-71 plus Yahoo site ref.
Kawakami, Y., et al., “A Single-Chip Digital Signal Processor for
Bierling, M., Displacement Estimation by Hierarchical Blockmatch
ing, SPIE, vol. 1001, Visual Communications and Image Processing,
Voiceband Applications,”IEEE, 1980 International Solid-State Cir
cuits Conference, pp. 40-41.
Sun Microsystems, Inc., “UltraSPARC Multimedia Capabilities On
Chip Support for Real-Time Video andAdvanced Graphics,” SPARC
Technology Business, Sep. 1994, 8 pgs.
Case, B., “Philips Hopes to Displace DSPs With VLIW, TriMedia
Avaro, Olivier, et al., MPEG-4 Systems Overview and Architecture,
May 1998, pp. 942-951.
Chan, Y.L and WC. Siu, Adaptive Multiple-Candidate Hierarchical
Search for BlockMatching Algorithm, IEE Electronics Letters, vol.
31, No. 19, Sep. 14, 1995, pp. 1637-1639.
Chan, Yui-Lam and Wan-Chi Siu, New/Adaptive Pixel Decimationfor
Processors Aimed at Future Multimedia Embedded Apps,” Micro
processor Report, Dec. 1994, pp. 12-18.
GWennap, L., “New PA-RISC Processor Decodes MPEGVideo, H‘”s
PA-7100LC Uses New Instructions to Eliminate Decoder Chip,
Chen, Liang-Gee, Wai-Ting Chen, Yeu-Shen Jetrng TZi-Dar Chuieh,
An Ej?cient Parallel Motion Estimation Algorithm for Digital Image
Microprocessor Report, Jan. 1994, pp. 16-17.
Processing,IEEE Transactions on Circuits and Systems on Video
Texas Instruments, “TMS320C2X User’s Guide,” 1993, pp. 3:2
Technology, vol. 1, No. 4, Dec. 1991, pp. 378-384.
Block Motion Vector Estimation, IEEE Transactions on Circuits and
Systems on Video Technology, vol. 6, No. 1, Feb. 1996, pp. 113-118.
3:11; 3:28-3:34; 4:1-4:22; 4:41; 4:103; 4:119-J;120; 4:122; 4:150
Cheng, K.W., S.C. Chan, FastBlockMatchingAlgorithmsforMotion
4:151.
Estimation, ICASSP96, 1996, pp. 2318ff.
US 7,631,025 B2
Page 3
Corbal, Jesus, et al., DLP+TLP Processorsfor theNext Generation of
Media Workloads, 0/7695-1019-1/01, IEEE, 2001, pp. 219-228.
Day, Neil, Ed.,Introduction to MPEG-7 (v3.0), International Orga
nization for Standardization, ISO/IEC JT C1/ SC29/WG1 1, Coding of
Moving Pictures and Audio, #N4032, Mar. 2001, pp. 1-10.
DufauX, Frederic, et al., Ej?cient, Robust, and Fast Global Motion
Estimation for J/ideo Coding, 1057-7149/00, IEEE, 2000, pp. 497
501.
Eckart, Stefan, Chad Fogg, ISO/IEC MPE G-2 Software J/ideo Codec,
SPIE vol. 2419, Digital Video Compression: Algorithms and Tech
nologies, 1995, San Jose, CA.
Edirisinghe, EA, et al., ShapeAdaptive Paddingfor MPEG-4 , 0098
3063/00, IEEE, 2000, pp. 514-520.
Feng, J., Lo, K. T. Mehrpour, H. KarboWiak, A.E, Adaptive Block
Matching Motion Estimation Algorithm for J/ideo Coding, IEE Elec
tronics Letters, vol. 31, No. 18, 1995, pp. 1542-1543.
Furht, Botho, Joshua Greenberg, Raymond Westwater, Motion Esti
mation Algorithm for J/ideo Compression, KluWer Academic Pub
lishers, Boston, 1997, pp. cover-vi, 11, 49-95.
Ghanbarli, M., The Cross-Search Algorithm for Motion Estimation,
IEEE Transactions on Communications, vol. 38, No. 7, Jul. 1990, pp.
950-953.
Kuhn, P., Algorithms, Complexity Analysis and VLSI Architectures
for MPEG-4 Motion Estimation, 1999 KluWer Academic Publishers,
Boston, pp. cover-vi, 15, 17-59, 107-109, 119-121, 147-167, and
189-204.
Kuhn, P., Stechele W., ComplexityAnalysis ofthe EmergingMPE G-4
Standard as a Basis for VLSIImplementation,vol. SPIE 3309 Visual
Communications and Image Processing, San Jose, Jan.1998, pp.
498-509.
Lee, Liang-Wei, Jhing-Fa Wang, Jau- Yien Lee, Jung-Dar Shie,
Dynamic Search-Window Adjustment and Interlaced Search Block
MatchingAlgorithm, IEEE Transactions on circuits and systems for
video technology, vol. 3, No. 1, Feb. 1993, pp. 85-87.
Lee, W.,Y. Kim, R.I. Gove, C.J. Read, Media Station 5 000.‘ Integrat
ing J/ideo and Audio, IEEE Multimedia, vol. 1, No. 4, 1994, pp.
50-61 .
Lee, Xiaobing, Ya-Qin Zhang, A Fast Hierarchical Motion-Compen
sation Scheme for J/ideo Coding Using Block-Feature Matching,
IEEE Transactions on Circuits and Systems for Video Technology,
vol. 6, No. 6, Dec. 1996, pp. 627-635.
LengWehasatit, Krisda, et al., A Novel Computationally Scalable
Algorithm for Motion Estimation, SPIE 3309 VCIP Visual Commu
nications and Image processing, San Jose, CA, Jan. 1998, pp. 66-79.
He, Zhongli, M.L. Liou, A High Performance Fast SearchAlgorithm
Li, R., B. Zeng, M.L. Liu, A New Three-Step Search Algorithmfor
for Block Matching Motion Estimation, IEEE Transactions on Cir
cuits and Systems on Video Technology, vol. 7, No. 5, Oct. 1997, pp.
Block Motion Estimation, IEEE Transactions on Circuits and Sys
tems on Video Technology, vol. 4, No. 4, Aug. 1994, pp. 438-442.
826-828.
Li, W., E. Salari, Successive Elimination Algorithm for Motion Esti
mation, IEEE Trans. Image Processing, vol. 4, Jan. 1995, pp. 105
He, Zhong-Li, M.L. Liou, Design of Fast Motion Estimation Algo
rithm based on Hardware Consideration, IEEE Transactions on Cir
107.
cuits and Systems on Video Technology, vol. 7, No. 5, Oct. 1997, pp.
Liang, Jie, et al., Region-Based J/ideo Coding with Embedded Zero
Trees, 1068-0314/97, IEEE, 1997, p. 449.
819-823.
Heising, G., et al., MoMuSys .' MPEG-4 Version 2 J/ideo Reference
Liu, B., A. Zaccarin, NewFastAlgorithmsfor theEstimation ofBlock
Software Package, AC098/HHI/WP5.1/DS/P/049/B1,1998, Abstract
Motion Vector, IEEE Transactions on Circuits and Systems on Video
and pp. 1-8.
Technology, vol. 3, No. 2, Apr. 1993, pp. 148-157.
Liu, Lumg-Kuo, Ephraim Feig, A Block-Based Gradient Descent
Intel Corporation, Block-Matching in Motion Estimation Alforithms
Using Streaming SIMD Extensions 2 (SSEZ), Vers. 2 .0 Sep. 22, 2000,
Order No. 248605-001, pp. 1-13, A-1, A-2.
International Organisation for Standardisation, Optimization Model,
Version 2.0, ISO/IEC JTC1/SC29/WG11, Coding of Moving Pic
tures and Audio, #N3675, Oct. 2000, 12 pp.
International Organisation for Standardisation, New MPEG-4 Pro
Search Algorithm for Block-Based Motion Estimation in J/ideo Cod
ing, IEEE Transactions on Circuits and Systems on Video Technol
ogy, vol. 6, No. 4, Aug. 1996, pp. 419-422.
Mo, Hyeon-Cheol, et al.,A High-Speed Pattern Decoder in MPEG-4
Padding Block Hardware Accelerator, 0-7803-6685-9/01, IEEE,
2001, pp. II-197-II-200.
?les Under Consideration, ISO/IEC JTC1/SC29/W G11, Coding of
Moving Pictures and Audio, #N3932, Jan. 2001, pp. 1-35.
Estimation on IA-64, Proc. of 2001 IEEE Int’l. Conf. on Multimedia
Jain, J ., A. Jain, Displacement Measurement and its Application in
and Expo ((ICME 2001), Tokyo, Japan, Aug. 2001, 4 pp.
Interframe Image Coding, IEEE Transactions on Communications,
Moschetti, F., et al., A Fast Block Matching for SIMD Processors
Using Subsampling, IEEE #0-7803-5482-6/99, pp. IV-321-IV-324.
vol. 29, No. 12, Dec. 1981, pp. 1799-1808.
Ju, John C.-H., et al., A Fast Rate-Optimized Motion Estimation
Algorithm for Low-Bit-Rate J/ideo Coding, 1051-8215/99, IEEE,
Moschetti, F., et al., About Macroblock Subsampling for Motion
Nam, KWon Moon, Joon-Seek Kim, Rae-Hong Park, Young Serk
1999, pp. 994-1002.
Shim, A Fast Hierarchical Motion Vector Estimation Algorithm
UsingMean Pyramid, IEEE Transactions on Circuits and Systems on
Jung, Hae Mook, Duch Dong Hwang Coong Soo Park, Han Soo Kim,
An Annular Search Algorithm for E?cient Motion Estimation, Inter
national Picture Coding Symposium, PCS96, 1996, pp. 171-174.
Video Technology, vol. 5, No. 4, Aug. 1995, pp. 344-351.
Netravali, A., B. Haskell, Digital Pictures Representation and Com
pression, NeWYork, Plenum, 1988, pp. cover-Xv, 334-340, 537-542,
Kappagantula, S., K.R. Rao, Motion Compensated InterframeImage
and 354-355.
Prediction, IEEE Transactions on Communications, 33(9), Sep.
1985, pp. 1011-1015.
Pirsch, Peter, Nicolas DemassieuX, Winfried Gehrke, VLSIArchitec
turesfor J/ideo Compression -A Survey, Proceedings of the IEEE, vol.
Kim, Joon-Seek, Rae-Hong Park, A Fast Feature-Based Block
Matching Algorithm Using Integral Projections, IEEE Journal on
Po, Lai-Man, Wing-Chung Ma. A Novel Four-Step SearchAlgorithm
83, No. 2, Feb. 1995, pp. 220-246.
968-971.
for Fast Blockmatching, IEEE Transactions on Circuits and Systems
on Video Technology, vol. 6, No. 3, Jun. 1996, pp. 313-317.
Kim, Michelle, Ed., MPEG-4 Systems, International Organization for
Standardization, ISO/IEC JTC1/SC29/WG11, Coding of Moving
Puri, A., H.M. Hang, D.L. Schilling, An E?cient Blockmatching
Algorithm for Motion Compensated Coding, Proc. IEEE ICASSP,
Selected areas in communications, vol. 10, No. 5, Jun. 1992, pp.
Pictures and Audio, #N3383, Jun. 2000, pp. 1-19.
1987, pp. 2.4.1-25.4.4.
Kneip, Johannes, et al., Applying and Implementing the MPEG-4
Multimedia Standard, 0272-1732/99, IEEE, 1999, pp. 64-74.
Kneip, J. (Johannes), et al., The MPEG-4 J/ideo Coding Standardia
VLSI Point of Wew, IEEE Workshop on Signal Processing Systems
(SIPS98), Oct. 8-10, 1998, pp. 43-52, A-1, A-2.
Koga, J ., et al., Motion Compensated Interframe Coding for J/ideo
Conferencing, Proceedings of the National Telecommunications
Ragsdale, Gary L., et al, Relationships of Popular Transmission
Conference, 1981, pp. G5.3.1- 5.3.3.
Koenen, Rob, Ed., Overview of the MPE G-4 Standard, International
Organization for Standardization, ISO/IEC JTC1/ SC29/WG1 1, Cod
ing of Moving Pictures and Audio, #N4030, Mar. 2001, pp. 1-69.
Characteristics to Perceived Quality for Digital J/ideo Over ATM,
National Communications System, Technical Information Bulletin
99-2, Jan. 1999, 64 pp.
Ramkishor, K., et al., Real Time Implementation ofMPEG-4 J/ideo
Decoder on ARM 7TDMI, Proc. of 2001 Int’l. Symposium on Intel
ligent Multimedia, Video and Speech Processing, May 2-4, 2001, pp.
522-526.
Shi, Y.Q., X. Xia, A Thresholding Multiresolution Block Matching
Algorithm, IEEE Transactions on Circuits and Systems on Video
Technology, vol. 7, No. 2, Apr. 1997, pp. 437-440.
US 7,631,025 B2
Page 4
Sikora, Thomas, MPEG Digital I/ideo Coding Standards, Preprint
from Digital Consumer Electronics Handbook, 15’ Ed., McGraW-Hill
Book Co., Ch. 9, pp. 1-43.
Sikora, Thomas, MPEG-1 and MPEG-2 Digital I/ideo Coding Stan
dards, Preprint from Digital Consumer Electronics Handbook, 15’
van der Schaar, M., et al., Near-Lossless Complexity-Scalable
Embedded Compression Algorithm for Cost Reduction in DTV
Receivers, 0098 3063/00, IEEE, 2000, pp. 923-933.
Wang, Chung-Neng, et al., Improved MPE G-4 I/isual Texture Coding
Using Double Transform Coding, 0/7803-6685-9/01, IEEE, 2001,
Ed., McGraW-Hill Book Co., pp. 1-43.
pp. V-227-V-230.
Sikora, Thomas, The Structure of the MPEG-4 I/ideo Coding Algo
rithm, Preprint from Digital Consumer Electronics Handbook, 15’
Westerink, P. H., et al., TWo-Pass MPE G02 Variable-Bit-RateEncod
ing, IBM J. Res. Develop, vol. 43, No. 4, Jul. 1999, pp. 471-488.
Wittenburg, J .P., et al., HiPAR-DSP: A Parallel VLIWRISC Proces
Ed., McGraW-Hill Book Co., pp. 1-16.
Song, Byung Cheol, Jong Beom Ra, A Hierarchical BlockMatching
Algorithm UsingPartial Distortion Criteria, SPIE 3309 VCIPVisual
Communications and Image Processing, 1998, San Jose, CA, pp.
88-95.
Srinivasan, Ram and KR. Rao, Predictive Coding Based on E?cient
Motion Estimation, IEEE Transactions on Circuits and Systems on
Video Technology, vol. Com-33, No. 8, Aug. 1985, pp. 888-896.
Stolberg, H.-J., et al., The M-Pire MPEG-4 Codec DSP and Its
MacroblockEngine, 0-7803-548206/99, IEEE, 2000, pp. II-192-II
195.
Tham, Jo Yew, et al., Transactions Letters.‘ A Novel Unrestricted
Center-Biased Diamond SearchAlgorithm for BlockMotion Estima
tion, IEEE, 1051-8215/98, 1998, pp. 369-377.
sor for Real Time Image Processing Applications, (0-7803-4229-1/
97) IEEE, 1997, pp. 155-162.
Xu, Jie-Bin, Lai-man Po, and Chok-KWan Cheung, A New Prediction
Model SearchAlgorithm for FastBlockMotion Estimation, IEEE Int.
Conf. Image Processing, ICIP97, Santa Barbara, 1997.
Yu, Fengqi and Alan N. Willson, Jr., A Flexible Hardware-Oriented
FastAlgorithmfor Motion Estimation, ICASSP97, 1997, pp. 2681ff.
Zhu, Shan, Kai-Kuang Ma, A New Diamond Search Algorithm for
FastBlockMatching, IEEE Transactions on Circuits and Systems on
Video Technology, vol. 9, No. 2, Feb. 2000, pp. 287-290.
Diefendorff, K., et al., “AltiVec Extension to PoWerPC Accelerates
Media Processing,” IEEE, #0272-1732/00, 2000, pp. 85-95.
* cited by examiner
US. Patent
Dec. 8, 2009
Sheet 1 0f 30
PROCESSOR
CACHE
104
L
4
US 7,631,025 B2
EXECUTION UNIT 10s
PACKED INSTRUCTION
SET
109
REGISTER FILE
106
PROCESSOR BUS
110 —/
MEMORY
GRAPHICS!
VIDEO
CARD
112
114
MEMORY
CONTROLLER
HUB
INSTRUCTION
118
DATA
116
120
:
DATA
LEGACY l/O
<}-__{>
STORAGE
<]:>
124
-
....99.'.“.T'39FP'?'3....
;
USER
5
INPUT
..... HWTERFAQEW.
l/O
WIRELESS
<:|>
TRANSCEIVER
CONTROLLER
HUB
SERIAL EXPANSION
126
<}:I>
FLASH BIOS <r‘:'_|>
128
130 <}:I'>
PORT
AUDIo
CONTROLLER
ii
100
134
FIG, 1 A
US. Patent
Dec. 8, 2009
Sheet 2 0f 30
PROCESSING
CORE
7 159
142
141
144 —-'
:
SDRAM
V
US 7,631,025 B2
‘
CTL
4+
'
A
l/O BRIDGE
,
V
<
>
156 <
>
146
‘ '
SRAM
'
154
0
CTL
UART
147
BURST FLASH
'
155
H
4 >
USB
INTERFACE
14s
BLUETOOTH
‘ '
A
>
PCMCIA/CF CARD CTL
‘
UART
<+
‘
'
157
149
A
7
A
7
A
LCD CTL
+>
l ‘
I/o EXPANSION
‘
‘ '
INTERFACE
'
150
DMA CTL
151
158
4+
1
153
ALTERNATE BUS MASTER 0
INTERFACE
152
V
FIG. 1B
140
US. Patent
Dec. 8, 2009
Sheet 3 0f 30
US 7,631,025 B2
09.
Il|I0
M
2:
mm?
Qmow>=
6?
wow#2.I
M
9%:
N-.o.?
mow
US. Patent
Dec. 8, 2009
Sheet 5 0f 30
US 7,631,025 B2
...
.....2m
....
o
n
w
vwNm
_
/Qw2x<OmnE_
o5
.<.250.3. E.0wosmjz?w.
. .Sm9m3m. . . .
8m.
9m
Cm
E0oQ2wm9<>5t.k_w“uNm ?‘
o
v
n
o
wmmm
Rm@Nmmam.
\2Qo0E9w>mmm.5H‘PmwN
Rm@8m8.
\z5o0%0kEm?mlzwN
US. Patent
Dec. 8, 2009
Sheet 7 0f 30
US 7,631,025 B2
GEmv
US. Patent
Dec. 8, 2009
Sheet 8 0f 30
US 7,631,025 B2
05v
mow
8mv898www3%
[X
Owm\-@mw2‘PMNmmm
0
m
X...
or
mw
w
h
my?Owmil
-
Em2mNBEm
w:Qv.@\H\
US. Patent
Dec. 8, 2009
Sheet 9 0f 30
US 7,631,025 B2
0mm
mwm
mwm
um
mmm
N?
I.
mmm
.QImv.
0w
2.
mwm
cm
9.
vwm
mm
Pu
mwm
wm
mm
mwm
mm
Fmm
wm
oww
US. Patent
Dec. 8, 2009
Sheet 11 0130
US 7,631,025 B2
Download PDF