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phyCARD -i.MX 6
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Hardware Manual
L-800e_0
SOM Prod. No.:
SOM PCB. No.:
PCA-A-XL3-xxx
1371.2
CB Prod. No.:
CB PCB. No.:
PBA-A-03
1360.2
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Document No.:
Edition:
August 2014
A product of a PHYTEC Technology Holding company
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™, or ®)
and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents
and trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is considered to be entirely reliable.
However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik
GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the
right to alter the information contained herein without prior notification and accepts no responsibility for
any damages that might result.
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Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising
from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH
further reserves the right to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
EUROPE
NORTH AMERICA
PHYTEC Messtechnik GmbH
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
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Address:
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© Copyright 2014 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and
storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur
without the express written consent from PHYTEC Messtechnik GmbH.
1 (800) 278-9913
[email protected]
Technical
Support:
+49 (6131) 9221-31
[email protected]
1 (800) 278-9913
[email protected]
Fax:
+49 (6131) 9221-33
1 (206) 780-9135
Web Site:
http://www.phytec.de
http://www.phytec.eu
http://www.phytec.com
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Ordering
+49 (6131) 9221-32
Information: [email protected]
Preliminary Edition August 2014
© PHYTEC Messtechnik GmbH 2014
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Contents
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List of Figures ........................................................................................................... iii
List of Tables ............................................................................................................ iv
Conventions, Abbreviations and Acronyms ................................................................... vii
Preface .................................................................................................................... ix
1
Introduction ...................................................................................................... 1
1.1 Block Diagram.............................................................................................. 3
1.2 View of the phyCARD-i.MX 6 ............................................................................ 4
1.3 Minimum Requirements to Operate the phyCARD-i.MX 6........................................ 6
2
Pin Description ................................................................................................... 7
3
Jumpers .......................................................................................................... 13
4
Power.............................................................................................................. 17
4.1 Primary System Power (VDD_3V3) ...................................................................17
4.2 Backup Voltage (VSTBY) ................................................................................18
4.3 Power Management IC (U29) / Control Management IC (U17) ...............................18
4.3.1 Power Management IC (PMIC, U29).......................................................18
4.3.2 Control Management IC (CMIC, U17) .....................................................18
4.3.3 Power Domains.................................................................................19
4.4 Supply Voltage for external Logic ....................................................................21
5
Power Management ........................................................................................... 23
6
System Configuration and Booting....................................................................... 25
7
System Memory................................................................................................. 27
7.1 DDR3 SDRAM (U2-U9) ...................................................................................27
7.2 NAND Flash Memory (U13) .............................................................................27
7.3 I²C EEPROM (U10) ........................................................................................28
7.3.1 EEPROM Write Protection Control (J3) ...................................................28
8
SD / MMC Card Interfaces.................................................................................... 29
9
Serial Interfaces ............................................................................................... 31
9.1 Universal Asynchronous Interface ...................................................................32
9.2 USB OTG Interface........................................................................................32
9.3 USB Host Interface.......................................................................................33
9.4 Ethernet Interface .......................................................................................34
9.4.1 Ethernet PHY (U11) ...........................................................................34
9.4.2 MAC Address ....................................................................................35
9.5 I2C Interface ...............................................................................................35
9.6 SPI Interface...............................................................................................36
9.7 I2S Audio Interface (SSI) ...............................................................................36
10 General Purpose I/Os......................................................................................... 38
11 User LEDs......................................................................................................... 39
12 Debug Interface (X3)) ....................................................................................... 40
13 LVDS Display Interface....................................................................................... 43
13.1 LVDS Display Interface pixel mapping ..............................................................43
14 LVDS Camera Interface....................................................................................... 45
14.1 Signal Configuration (J31) ............................................................................45
15 Technical Specifications ..................................................................................... 46
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Hints for Integrating and Handling the phyCARD-i.MX 6 ......................................... 50
16.1 Integrating the phyCARD-i.MX 6..................................................................... 50
16.2 Handling the phyCARD-i.MX 6........................................................................ 52
17 The phyCARD-i.MX 6 on the phyBASE .................................................................... 54
17.1 Concept of the phyBASE Board....................................................................... 55
17.2 Overview of the phyBASE Peripherals .............................................................. 56
17.2.1 Connectors and Pin Header ................................................................ 57
17.2.2 Switches ........................................................................................ 58
17.2.3 LEDs.............................................................................................. 60
17.2.4 Jumpers......................................................................................... 61
17.3 Functional Components on the phyBASE Board ................................................. 65
17.3.1 phyCARD-i.MX 6 SOM Connectivity (X27)............................................... 65
17.3.2 Power Supply (X28) .......................................................................... 66
17.3.3 RS-232 Connectivity (P1)................................................................... 68
17.3.4 Ethernet Connectivity (X10) ............................................................... 69
17.3.5 USB Host Connectivity (X6, X7, X8, X9, X33) .......................................... 70
17.3.6 USB OTG Connectivity (X29) ............................................................... 72
17.3.7 Display / Touch Connectivity (X6, X32) ................................................. 73
17.3.7.1 PDI Data Connector (X6)....................................................... 74
17.3.7.2 Display Power Connector (X32) .............................................. 76
17.3.7.3 Touch Screen Connectivity .................................................... 77
17.3.8 Audio Interface (X1, X2, X3)............................................................... 78
17.3.9 I2C Connectivity ............................................................................... 80
17.3.10 SPI Connectivity .............................................................................. 82
17.3.11 User programmable GPIOs ................................................................. 82
17.3.12 Extension connectors (X8A, X9A) ........................................................ 83
17.3.13 Secure Digital Memory Card/ MultiMedia Card (X26)................................ 85
17.3.14 Boot Mode Selection (JP1)................................................................. 86
17.3.15 System Reset Button (S1) .................................................................. 88
17.3.16 RTC at U3........................................................................................ 89
17.3.17 PLD at U25...................................................................................... 91
17.3.18 Carrier Board Physical Dimensions....................................................... 92
18 Revision History................................................................................................ 93
Index ...................................................................................................................... 95
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© PHYTEC Messtechnik GmbH 2014
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Contents
List of Figures
Block Diagram of the phyCARD-i.MX 6 ............................................................. 3
Figure 2:
phyCARD-i.MX 6 Component Placement (top view) ............................................. 4
Figure 3:
phyCARD-i.MX 6 Component Placement (bottom view)........................................ 5
Figure 4:
Pinout of the phyCARD-Connector (top view, with cross section insert) .................. 8
Figure 5:
Typical Jumper Pad Numbering Scheme ..........................................................13
Figure 6:
Jumper Locations (top view) ........................................................................14
Figure 7:
Jumper Locations (bottom view)...................................................................15
Figure 8:
Power Supply Diagram ................................................................................20
Figure 9:
JTAG Interface at X2 and X3 (top view) ...........................................................40
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Figure 10: JTAG Interface at X2 and X3 (bottom view) ......................................................41
Figure 11: Physical Dimensions ...................................................................................46
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Figure 12: Footprint of the phyCARD-i.MX 6 ...................................................................51
Figure 13: phyBASE Overview of Connectors, LEDs and Buttons..........................................56
Figure 14: Typical Jumper Numbering Scheme................................................................61
Figure 15: phyBASE Jumper Locations ..........................................................................62
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Figure 16: phyCARD-i.MX 6 SOM Connectivity to the Carrier Board ......................................65
Figure 17: Powering Scheme.......................................................................................66
Figure 18: Power Connector corresponding to Wall Adapter Input X28.................................66
Figure 19: RS-232 Interface Connector P1 .....................................................................68
Figure 20: RS-232 Connector P1 Signal Mapping.............................................................68
Figure 21: Ethernet Interface at Connector X10 ..............................................................69
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Figure 22: Components supporting the USB Host Interface ...............................................70
Figure 23: USB OTG Interface at Connector X29 ..............................................................72
Figure 24: Universal LVDS Interface at Connector X6........................................................73
Figure 25: Audio Interface at Connectors X1, X2, X3 ........................................................78
Figure 26: Extension Connector X8A, X9A ......................................................................83
Figure 27: SD / MM Card interface at connector X26.........................................................85
Figure 28: Boot Mode Selection Jumper JP1 ..................................................................86
Figure 29: System Reset Button S1...............................................................................88
Figure 30: RTC with Battery Buffer ...............................................................................89
Figure 31: Carrier Board Physical Dimensions.................................................................92
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
List of Tables
Abbreviations and Acronyms used in this Manual .............................................viii
Table 2:
X-Arc Bus Pinout ......................................................................................... 9
Table 3:
Pinout of the phyCARD-Connector X1, Row A................................................... 10
Table 4:
Pinout of the phyCARD-Connector X1, Row B................................................... 11
Table 5:
Jumper Settings ....................................................................................... 16
Table 6:
Power Management Pins ............................................................................. 23
Table 7:
Power States ............................................................................................ 23
Table 8:
Boot Modes of the phyCARD-i.MX 6 ............................................................... 26
Table 9:
Boot Configuration Signals generated by the CM ............................................. 26
Table 10:
EEPROM write protection states via J3 ........................................................... 28
Table 11:
Location of SD/ MMC Card Interface Signals.................................................... 29
Table 12:
Location of the UART Signals ....................................................................... 32
Table 13:
Location of the USB OTG Signals................................................................... 33
Table 14:
Location of the USB-Host Signals ................................................................. 33
Table 15:
Location of the Ethernet Signals .................................................................. 34
Table 16:
I2C Interface Signal Location ....................................................................... 35
Table 17:
SPI Interface Signal Location....................................................................... 36
Table 18:
SSI Interface Signal Location....................................................................... 37
Table 19:
Location of GPIO and IRQ pins...................................................................... 38
Table 20:
JTAG Connector X3 Signal Assignment ........................................................... 42
Table 21:
Debug interface Connector X2 Signal Assignment ............................................ 42
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Table 1:
Table 22:
Display Interface Signal Location ................................................................. 43
Table 23:
Pixel Mapping of 18-bit LVDS Display Interface................................................ 44
Table 24:
Pixel Mapping of 24-bit LVDS Display Interface................................................ 44
Table 25:
Camera Interface Signal Location at X1.......................................................... 45
Table 26:
LVDS Signal Configuration J31..................................................................... 45
Table 27:
phyBASE Connectors and Pin Headers............................................................ 57
Table 28:
phyBASE Push Buttons Descriptions.............................................................. 58
Table 29:
phyBASE DIP-Switch S3 Descriptions............................................................. 59
Table 30:
phyBASE LEDs Descriptions ......................................................................... 60
Table 31:
phyBASE Jumper Descriptions ..................................................................... 63
Table 32:
LEDs Assembled on the Carrier Board ............................................................ 67
Table 33:
Distribution of the USB Hub's (U4) Ports ....................................................... 71
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Contents
Universal USB Pin Header X33 Signal Description .............................................71
Table 35:
Display Data Connector X6 Signal Description ..................................................74
Table 36:
Auxiliary Interfaces at PDI Data Connector X12 ................................................75
Table 37:
SPI and GPIO Connector Selection .................................................................76
Table 38:
LVDS Power Connector X32 Signal Description..................................................76
Table 39:
Selection of the Touch Screen Controller.........................................................77
Table 40:
Selection of the Audio Codec ........................................................................79
Table 41:
I2C Connectivity .........................................................................................80
Table 42:
I2C Addresses in Use ...................................................................................80
Table 43:
SPI Connector Selection ..............................................................................82
Table 44:
SPI and GPIO Connector Selection .................................................................84
Table 45:
PHYTEC Extension Connectors X8A, X9A ..........................................................84
Table 46:
Boot Options for the phyCARD-i.MX 6 .............................................................87
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Table 34:
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
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© PHYTEC Messtechnik GmbH 2014
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Conventions, Abbreviations and Acronyms
Conventions, Abbreviations and Acronyms
This hardware manual describes the PCA-A-XS1 System on Module in the following referred
to as phyCARD®-i.MX 6. The manual specifies the phyCARD®-i.MX 6's design and function.
Precise specifications for the Freescale Semiconductor i.MX 6 microcontrollers can be
found in the enclosed microcontroller Data Sheet/User's Manual.
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Conventions
The conventions used in this manual are as follows:
ƒ Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or
that have a dash on top of the signal name (e.g.: RD) are designated as active low
signals. That is, their active state is when they are driven low, or are driving low.
ƒ A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or
high-level signal.
ƒ The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the
address byte. The correct value of the LSB which depends on the desired command
(read (1), or write (0)) must be added to get the complete address byte. E.g. given
address in this manual 0x41 => complete address byte = 0x83 to read from the device
and 0x82 to write to the device.
ƒ Tables which describe jumper settings show the default position in bold, blue text.
ƒ Text in blue italic indicates a hyperlink within, or external to the document. Click these
links to quickly jump to the applicable URL, part, chapter, table, or figure.
ƒ References made to the phyCARD-Connector always refer to the high density molex
connector on the undersides of the phyCARD-i.MX 6 System on Module.
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Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to
navigate unfamiliar terms used in this document.
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
J
JP
PCB
PDI
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PEB
PMIC
PoE
PoP
POR
RTC
SMT
SOM
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EMB
EMI
GPI
GPIO
GPO
IRAM
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CB
Definition
Board Support Package (Software delivered with the Development Kit
including an operating system (Windows, or Linux) preinstalled on the
module and Development Tools).
Carrier Board; used in reference to the phyBASE Development Kit
Carrier Board.
D flip-flop.
External memory bus.
Electromagnetic Interference.
General purpose input.
General purpose input and output.
General purpose output.
Internal RAM; the internal static RAM on the Freescale Semiconductor
i.MX 6 microcontroller.
Solder jumper; these types of jumpers require solder equipment to
remove and place.
Solderless jumper; these types of jumpers can be removed and placed
by hand with no special tools.
Printed circuit board.
PHYTEC Display Interface; defined to connect PHYTEC display adapter
boards, or custom adapters
PHYTEC Extension Board
Power management IC
Power over Ethernet
Package on Package
Power-on reset
Real-time clock.
Surface mount technology.
System on Module; used in reference to the PCA-A-XS1 /phyCARD®i.MX 6 module
User button Sx (e.g. S1, S2) used in reference to the available user
buttons, or DIP-Switches on the CB.
Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the
carrier board.
SOM standby voltage input
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Abbreviation
BSP
Sx
Sx_y
VSTBY
Table 1:
Abbreviations and Acronyms used in this Manual
Note: The BSP delivered with the phyCARD®-i.MX 6 usually includes drivers and/or software
for controlling all components such as interfaces, memory, etc. Therefore programming
close to hardware at register level is not necessary in most cases. For this reason, this
manual contains no detailed description of the controller's registers, or information
relevant for software development. Please refer to the i.MX 6 Reference Manual, if such
information is needed to connect customer designed applications.
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© PHYTEC Messtechnik GmbH 2014
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Preface
Preface
As a member of PHYTEC's new phyCARD® product family the phyCARD-i.MX 6 is one of a
series of PHYTEC System on Modules (SOMs) that can be populated with different
controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
as the basis for Rapid Development Kits which serve as a reference and evaluation
platform
(2)
as insert-ready, fully functional phyCARD® OEM modules, which can be embedded
directly into the user’s peripheral hardware design.
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Implementation of an OEM-able SOM subassembly as the "core" of your embedded design
allows you to focus on hardware peripherals and firmware without expending resources to
"re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCARD®
module lies in its layout and test.
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PHYTEC's new phyCARD® product family consists of a series of extremely compact embedded
control engines featuring various processing performance classes while using the newly
developed X-Arc embedded bus standard. The standardized connector footprint and pin
assignment of the X-Arc bus makes this new SOM generation extremely scalable and
flexible. This also allows to use the same carrier board to create different applications
depending on the required processing power. With this new SOM concept it is possible to
design entire embedded product families around vastly different processor performances
while optimizing overall system cost. In addition, future advances in processor technology
are already considered with this new embedded bus standard making product upgrades
very easy. Another major advantage is the forgone risk of potential system hardware
redesign steps caused by processor or other critical component discontinuation. Just use
one of PHYTEC's other phyCARD® SOMs thereby ensuring an extended product life cycle of
your embedded application.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware will
further reduce your development time and risk and allow you to focus on your product
expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With this new innovative
full system solution you will be able to bring your new ideas to market in the most timely
and cost-efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
www.phytec.eu/europe/oem-integration/evaluation-start-up.html
or
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Ordering Information
The part numbering of the phyCARD has the following structure:
PCA-A-XL3-xxxxxx
Generation
A
=
First generation
Performance class
lowest
low
middle
high
highest
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=
=
=
=
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XS
S
M
L
XL
Controller No. of specified performance class and
Assembly options (depending on model)
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In order to receive product specific information on changes and updates in the best way
also in the future, we recommend to register at
http://www.phytec.de/de/support/registrierung.html or
http://www.phytec.eu/europe/support/registration.html
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For technical support and additional information concerning your product, please visit the
support section of our web site which provides product specific information, such as errata
sheets, application notes, FAQs, etc.
http://www.phytec.de/de/support/faq/faq-phyCARD-i.MX 6.html or
http://www.phytec.eu/europe/support/faq/faq-phyCARD-i.MX 6.html
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© PHYTEC Messtechnik GmbH 2014
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Preface
Declaration of Electro Magnetic Conformity of the PHYTEC phyCARD®-i.MX 6
PHYTEC System on Module (henceforth products) are designed for installation
in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and
prototype platform for hardware/software development) in laboratory environments.
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Caution:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence,
may only be unpacked, handled or operated in environments in which sufficient
precautionary measures have been taken in respect to ESD-dangers. It is also necessary
that only appropriately trained personnel (such as electricians, technicians and engineers)
handle and/or operate these products. Moreover, PHYTEC products should not be operated
without protection circuitry if connections to the product's pin header rows are longer
than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic
Conformity only in accordance to the descriptions and rules of usage indicated in this
hardware manual (particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
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Implementation of PHYTEC products into target devices, as well as user modifications and
extensions of PHYTEC products, is subject to renewed establishment of conformity to, and
certification of, Electro Magnetic Directives. Users should ensure conformance following
any modifications to the products as well as implementation of the products into target
systems.
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Product Change Management and information in this manual on parts populated on
the SOM
When buying a PHYTEC SOM, you will, in addition to our HW and SW offerings, receive a free
obsolescence maintenance service for the HW we provide.
Our PCM (Product Change Management) Team of developers, is continuously processing, all
incoming PCN's (Product Change Notifications) from vendors and distributors concerning
parts which are being used in our products.
Possible impacts to the functionality of our products, due to changes of functionality or
obsolesce of a certain part, are being evaluated in order to take the right masseurs in
purchasing or within our HW/SW design.
Our general philosophy here is: We never discontinue a product as long as there is
demand for it.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Therefore we have established a set of methods to fulfill our philosophy:
Avoiding strategies
•
•
•
Avoid changes by evaluating long-livety of parts during design in phase.
Ensure availability of equivalent second source parts.
Stay in close contact with part vendors to be aware of roadmap strategies.
Change management in case of functional changes
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•
Avoid impacts on product functionality by choosing equivalent replacement parts.
Avoid impacts on product functionality by compensating changes through HW redesign
or backward compatible SW maintenance.
Provide early change notifications concerning functional relevant changes of our
products.
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•
•
Change management in rare event of an obsolete and non replaceable part
•
Ensure long term availability by stocking parts through last time buy management
according to product forecasts.
Offer long term frame contract to customers.
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•
Therefore we refrain from providing detailed part specific information within this
manual, which can be subject to continuous changes, due to part maintenance for our
products.
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In order to receive reliable, up to date and detailed information concerning parts used
for our product, please contact our support team through the contact information
given within this manual.
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© PHYTEC Messtechnik GmbH 2014
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Introduction
1
Introduction
The phyCARD-i.MX 6 belongs to PHYTEC’s phyCARD System on Module family. The
phyCARD SOMs represent the continuous development of PHYTEC System on Module
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCARD boards
integrate all core elements of a microcontroller system on a subminiature board and are
designed in a manner that ensures their easy expansion and embedding in peripheral
hardware developments.
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PHYTEC's phyCARD family introduces the newly developed X-Arc embedded bus standard.
Apart from processor performance, a large number of embedded solutions require a
corresponding number of standard interfaces. Among these process interfaces are for
example Ethernet, USB, UART, SPI, I2C, audio, display and camera connectivity. The X-Arc
bus exactly meets this requirement. As well the location of the commonly used interfaces
as the mechanical specifications are clearly defined. All interface signals of PHYTEC's new
X-Arc bus are available on a single, 100-pin , high-density pitch (0.635 mm) connector,
allowing the phyCARDs to be plugged like a "big chip" into a target application. The
reduced complexity of the phyCARD SOM as well as the smaller number of interface signals
greatly simplifies the SOM carrier board design helping you to reduce your time-to-market.
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As independent research indicates that approximately 70% of all EMI (Electro Magnetic
Interference) problems stem from insufficient supply voltage grounding of electronic
components in high frequency environments approximately 20% of all pin header
connectors on the X-Arc bus are dedicated to Ground. This improves EMI and EMC
characteristics and makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCARD boards even in high noise environments.
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phyCARD boards achieve their small size through modern SMD technology and multi-layer
design. In accordance with the complexity of the module, 0402-packaged SMD components
and laser-drilled microvias are used on the boards, providing phyCARD users with access to
this cutting edge miniaturization technology for integration into their own design.
The phyCARD-i.MX 6 is a subminiature (60 mm x 60 mm) insert-ready System on Module
populated with the Freescale Semiconductor i.MX 6 microcontroller. Its universal design
enables its insertion in a wide range of embedded applications.
Precise specifications for the controller populating the board can be found in the
applicable controller Reference Manual or datasheet. The descriptions in this manual are
based on the Freescale Semiconductor i.MX 6. No description of compatible
microcontroller derivative functions is included, as such functions are not relevant for the
basic functioning of the phyCARD-i.MX 6.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
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The phyCARD-i.MX 6 offers the following features:
• Subminiature System on Module (60 mm x 60 mm) achieved through modern SMD
technology
• Populated with the Freescale Semiconductor i.MX 6 microcontroller (BGA624
packaging)
• Improved interference safety achieved through multi-layer PCB technology and
dedicated ground pins
• X-Arc bus including commonly used interfaces such as Ethernet, USB, UART, SPI, I2C,
audio, camera and display connectivity (LVDS) available at one 100-pin high-density
(0.635 mm) Molex connector, enabling the phyCARD-i.MX 6 to be plugged like a "big
chip" into the target application
• Max. 1 GHz core clock frequency
• Boot from different memory devices (NAND Flash (standard))
• RAM memory device with 512 MB (up to 4 GB) DDR3 SDRAM
• 256 MB (up to 4 GB) on-board NAND Flash (VFBGA)
• Up to 32 Kbit I2C EEPROM
• Serial interface with 4 lines (TTL) allowing simple hardware handshake
• High-Speed USB OTG interface
• High-Speed USB HOST interface
• Auto HDX/FDX 10/100MBit Ethernet interface, with HP Auto MDI/MDI-X support
• One I2C interfaces
• One SPI interfaces
• I2S (SSI) audio interface
• 4 channel LVDS (24 bit) LCD interface
• LVDS camera interface; phyCAM-S(+) compatible
• SD/MMC card interface with DMA
• Support of standard 20 pin debug interface through JTAG connector
• Additional serial interface connector for debugging
• 3 GPIO/IRQ ports
• 2 Power State outputs to support applications requiring a power management
• 1 Wake Up input
• Two user programmable LEDs
• Single supply voltage of 3.3 V (max 1.5 A).
• All controller required supplies are generated on board
• On-board power management IC (PMIC) with integrated RTC
• Control Management IC (CMIC)
• Industrial temperature range (-40°C..+80°C)
2
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Introduction
Pr
el
im
in
a
ry
1.1 Block Diagram
Figure 1:
Block Diagram of the phyCARD-i.MX 6
© PHYTEC Messtechnik GmbH 2014
L-800e_0
3
C256
R215
C429
ry
C249
C399 C397
C403
R225
R227
C355
C409
C408
C396
C384
C402
J33
C395
R224
J6
J5
J17
J11
J8
R226
C426 Q16
in
a
C244
C383
C401
J14
J16
J15
J12
J13
R14
C66
J34
R82
R81
R84
R83
R5
R9
R86
XT1
C225 C255
C248
C243
R112
C427
XT4
C428
R116
Q8
Q15
R174
J20
J7
J19
J28
R176
J27
J30
R169
J29
J24
R99
R188
R170 R69 R173
R76
J21 R98
R104
el
im
C250 C251 C252
C247
C242 C227
C237
C232
C218
C221 C222 C223 C219
C214 C212
C213 C254 C217
C145 C140
J1
J18
R6
C436
R64
R63
R61
R8
R60
R7
C39 C102
R241
Q12
U32
C434
Q11
C245 C224 R22 C246
C241 C238 C174
C234
C228 C239 C229
R23 C236 C233
R24
C230 C231 C187
C235 C226
C220 C240
C215 C216
C253
J10
J9
R4
R79
R244
R245
L6
D2
R3
R80
R10
R109
R108
R114
R115
R168
C375
C96
C106
C101
C157 C156 R1 C154 R15 C155
C394
R197
C308
C309
R103
R242
L4
L8
R221
R222
R209
R239
U11
XT3
Q4
D1
R208
R166
C435
L-800e_0
© PHYTEC Messtechnik GmbH 2014
4
C356
R240 R211
R218
R212
C388
U26
C374
L5
U29
C398
C366
R16
Q9
XT2
R77
phyCARD-i.MX 6 Component Placement (top view)
Figure 2:
C160
C342
C343
U17
Q5
C344
U2
U3
U4
C377
U31
C105
C99
R111
U10
R119
R120
R179
C357
R196
R78
R42
U5
R45
R40
R29
R28
C159
R217
R216
C422
C430
J3
R62
R41
R31
U1
Q7
R44
R37
R35
R33
R49
R25
R53
R57
R55
C266
C265
C267
C260
C268
C264
4 2
X2
6
2
4
6
X3
8
20 18 16 14 12 10
C407
R223
Q6
C150
C165 C167
R246 R243
Pr
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
1.2 View of the phyCARD-i.MX 6
Introduction
1
3 5
X2
1
3
R11
5
9 11
X3
7
R117 R118
R177
13 15 17 19
R12
TP24
TP27 TP28
C211
C358
C168
C194
C201
C206 C205
C193
C162
C164
C169
C291 R123 R85
ry
C210
R91
R92
C207
C347
C185
U9
C376
C204 C203 C202
C152
C197 C171 C200
C192
C196 R21
U8
C195
C189
C190 C191
C186 R20 C180 C153 C188
C349
C183
C177
C208 C353 C351
TP33
C182
C175
U7
C170 C181
C151
C146
C198 C176
C199 C144
C184
C173 R19 C149
C178 C179
C172
C147 C148
C141 C142 C143 R17
U6
C166
R38 R43
R36 R39
R34 R32
R48 R30
R56 R47
R52
R51
C163
R50
R54
R46
R27
C158
R26
C161
C257
C42
C258
C263
C6 C137
C5 C2
C1
R68
C90
C438 C441
R248
R250
TP15
C30
C59
R70
R65
R71
R247
R89 C290 R90
Q13
R58
Q19
R253
R178
R252
C41
R184
Q20
C85
C58
C72 C92
C113
R251
C442
C439
C31
C14 C17
C32 C18
C12 C19
R87
C93
C91
C48
C95
C100
C69
el
im
J4
C70
C7
U13
C79
C84
R162
C33
C15
C23
C21
C22
C74
C75
C55
C16
C47
C24
C76
C26
C35
C86
C38
C34
R161
C83
C71 C9
C10
C37 C11
C36
C440 C437
C64
C4
C50 C52
R249
C87
C138
C262
C3
C139
C261
C209
C89
J2
C54
C368
C65
C13
C133 C8 C82 C28
C63 C81 C29
C62 C25
C80
C77
C51
C88
C43
in
a
R18
C20
C134 C49
C135
C44
C94
C78
C56
C40
C73
C53
C68
25
C259
C129
TP1
C46
C114
C373
C67
R94 R93
D3
C433
C98
Q18
R95
C97
L1
C104
C103
C136
C27
C360
C369
C390
R214
R220
C414
C391
Q17
R13
C413
R198
R199
C354
C61
C60
R195
R193 R194
C45
C385
TP31
C404
TP30 TP23
C361
C387
C415
C379
C410
C412
C381
C411
C380
C359
C371
C416
TP26
C389 C392
C57
C382
C370
TP40 TP39
C130
C352
C367
TP41 TP38
TP25
C350
U27
J31
TP34 TP37
C345 C346
C348
TP36 TP35
R88
TP16 TP10 TP22
R67
TP11 TP12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
X1
1
1
TP17
TP14
Pr
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99100
Figure 3:
phyCARD-i.MX 6 Component Placement (bottom view)
© PHYTEC Messtechnik GmbH 2014
L-800e_0
5
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
1.3 Minimum Requirements to Operate the phyCARD-i.MX 6
Basic operation of the phyCARD-i.MX 6 only requires supply of a +3.3 V input voltage with
1.5 A load and the corresponding GND connection.
These supply pins are located at the phyCARD-Connector X1:
VDD_3V3:
X1
1A, 2A, 3A, 1B, 2B, 3B
Connect all +3.3 V VCC input pins to your power supply and at least the matching number of
GND pins.
X1
4A, 8A, 13A, 4B, 8B, 13B
ry
Corresponding GND:
in
a
Please refer to section 2 for information on additional GND Pins located at the phyCARDConnector X1.
el
im
Caution:
We recommend connecting all available +3.3 V input pins to the power supply system on a
custom carrier board housing the phyCARD-i.MX 6 and at least the matching number of
GND pins neighboring the +3.3 V pins.
In addition, proper implementation of the phyCARD-i.MX 6 module into a target
application also requires connecting all GND pins neighboring signals that are being used
in the application circuitry.
Pr
Please refer to section 4 for more information.
6
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Pin Description
2
Pin Description
Please note that all module connections are not to exceed their expressed maximum
voltage or current. Maximum signal input values are indicated in the corresponding
controller manuals/data sheets. As damage from improper connections varies according to
use and application, it is the user's responsibility to take appropriate safety measures to
ensure that the module connections are protected from overloading through connected
peripherals.
ry
As Figure 4 indicates, all X-Arc bus signals extend to one surface mount technology (SMT)
connector (0.635 mm) lining on side of the module (referred to as phyCARD-Connector).
This allows the phyCARD-i.MX 6 to be plugged into any target application like a "big chip".
in
a
The numbering scheme for the phyCARD-Connector is based on a two dimensional matrix in
which column positions are identified by a letter and row position by a number. Pin 1A, for
example, is always located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin connector rows progresses
alphabetically from left to right (refer to Figure 4).
el
im
The numbered matrix can be aligned with the phyCARD-i.MX 6 (viewed from above;
phyCARD-Connector pointing down) or with the socket of the corresponding phyCARD
Carrier Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin
1A) is thus covered with the corner of the phyCARD-i.MX 6 marked with "1A". The
numbering scheme is always in relation to the PCB as viewed from above, even if all
connector contacts extend to the bottom of the module.
Pr
The numbering scheme is thus consistent for both the module’s phyCARD-Connector as
well as the mating connector on the phyCARD Carrier Board or target hardware, thereby
considerably reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described,
the phyCARD-Connector is usually assigned a single designator for its position (X1 for
example). In this manner the phyCARD-Connector comprises a single, logical unit
regardless of the fact that it could consist of more than one physical socketed connector.
The following figure illustrates the numbered matrix system. It shows a phyCARD-i.MX 6
with an SMT phyCARD-Connector on its underside (defined as dotted lines) mounted on a
carrier board. In order to facilitate understanding of the pin assignment scheme, the
diagram presents a cross-view of the phyCARD-i.MX 6 module showing the phyCARDConnector mounted on the underside of the module’s PCB.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
7
Pinout of the phyCARD-Connector (top view, with cross section insert)
el
im
Figure 4:
in
a
X2
ry
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Table 2 shows the pinout of the X-Arc bus with the functional grouping of the signals, while
Table 3 and Table 4 provide an overview of the pinout of the phyCARD-Connector with
signal names and descriptions specific to the phyCARD-i.MX 6. They also provide the
appropriate signal level interface voltages listed in the SL (Signal Level) column and the
signal direction.
Pr
The Freescale Semiconductor i.MX 6 is a multi-voltage operated microcontroller and as
such special attention should be paid to the interface voltage levels to avoid unintentional
damage to the microcontroller and other on-board components. Please refer to the
Freescale Semiconductor i.MX 6 Reference Manual for details on the functions and features
of controller signals and port pins.
8
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Pin Description
AC'97/I2S
ry
in
a
el
im
Supply
Display
Ethernet
USB OTG
SD/MMC
SPI
Pr
L-800e_0
I/O
In
In
In
Out
In
Out
Out
Out
Out
Out
In
In
Out
Bi
Out
In
In
Out
In
Out
Bi
Bi
Out
Bi
Bi
Bi
Out
Out
In
In
Out
Bi
Out
Out
In
Bi
Bi
In
I2C
USB Host
USB Host
UART
AC'97/I2S
© PHYTEC Messtechnik GmbH 2014
Signal
VCC
VCC
VCC
GND
VCC_LOGIC
VSTBY
nRESET_OUT
GND
LVDS_TX1+
LVDS_TX1LVDS_TX3+
LVDS_TX3GND
LVDS_CAM_RX+
LVDS_CAM_RXLVDS_CAM_nLOCK
I2C_DATA
GND
ETH_LINK
ETH_RX+
ETH_RXGND
nUSB_HOST_PWR
nUSB_HOST_OC
GND
nSuspend_to_RAM
USB_HOST_DUSB_HOST_D+
nPower_Off
GND
SDIO_D1
SDIO_D3
SDIO_CMD
GND
SPI_CS1
SPI_MOSI
SPI_MISO
GND
UART_RXD
UART_CTS
GND
AC97/I2S_BIT_CLK
AC97/I2S_SYNC
AC97/I2S_nRESET
GND
SDIO_CD
GPIO1/IRQ
for internal use only
GND
CONFIG1
SPI
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
27B
28B
29B
30B
31B
32B
33B
34B
35B
36B
37B
38B
39B
40B
41B
42B
43B
44B
45B
46B
47B
48B
49B
50B
SD/MMC
GPIO
Pin
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
25A
26A
27A
28A
29A
30A
31A
32A
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
43A
44A
45A
46A
47A
48A
49A
50A
Ethernet
UART
Pin
Camera
X-Arc Bus Pinout
VCC
VCC
VCC
GND
VCC_LOGIC
FEEDBACK
nRESET_IN
GND
LVDS_TX0+
LVDS_TX0LVDS_TX2+
LVDS_TX2GND
LVDS_TXCLK+
LVDS_TXCLKLVDS_CAM_MCLK
I2C_CLK
GND
ETH_SPEED
ETH_TX+
ETH_TXGND
nUSB_OTG_PWR
nUSB_OTG_OC
GND
USB_OTG_VBUS
USB_OTG_DUSB_OTG_D+
USB_OTG_UID1
GND
SDIO_D0
SDIO_D2
SDIO_CLK
GND
SPI_CS0
SPI_RDY
SPI_CLK
GND
UART_TXD
UART_RTS
GND
I2S_SEL/AC97_INT
AC97/I2S_SDATA_OUT
AC97/I2S_SDATA_IN
GND
GPIO0/IRQ
GPIO2/IRQ/PWM
nWKUP
GND
CONFIG0
Display
Table 2:
Camera
I2C
Signal
Supply
Boot Opt.
I/O
In
In
In
Out
In
Out
Out
Out
Out
Out
Out
Out
Bi
Out
Out
Out
Out
In
Bi
Bi
Bi
In
Bi
Bi
Out
Out
In
Out
Out
In
Bi
Out
In
Bi
Bi
In
In
SD/MMC
GPIO
Boot Opt.
9
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin.
Those pins marked as “N/A” have a range of applicable values that constitute proper
operation.
Please refer to the phyCARD Design-In Guide (LAN-051) for layout recommendations
and example circuitry.
I/O
SL
Description
1A
2A
3A
4A
5A
6A
VDD_3V3
VDD_3V3
VDD_3V3
GND
VDD_3V3_LOGIC 1
FEEDBACK
I
I
I
O
O
Power
Power
Power
Power
Power
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
X_nRESET_IN
GND
X_LVDS_TX0+
X_LVDS_TX0X_LVDS_TX2+
X_LVDS_TX2GND
X_LVDS_TXCLK+
X_LVDS_TXCLKX_LVDS_CAM_MCLK
X_I2C_CLK
GND
X_ETH_SPEED
X_ETH_TX+
I
O
O
O
O
O
O
O
O
O (I)
VBAT
Power
LVDS
LVDS
LVDS
LVDS
Power
LVDS
LVDS
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_ETH_3V3
VDD_ETH_3V3
21A
X_ETH_TX-
O (I)
VDD_ETH_3V3
22A
23A
24A
25A
26A
27A
28A
29A
GND
X_nUSB_OTG_PWR
X_nUSB_OTG_OC
GND
X_USB_OTG_VBUS
X_USB_OTG_DX_USB_OTG_D+
X_USB_OTG_UID
O
I
I
I/O
I/O
I
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
Power
USB
USB
VDD_3V3_LOGIC
30A
GND
-
Power
3.3 V Primary voltage supply input
3.3 V Primary voltage supply input
3.3 V Primary voltage supply input
Ground 0 V
VCC Logic output
Feedback output to indicate the supply voltage
required (floating in order to configure the CB or
target application for 3.3 V)
Active low Reset In
Ground 0 V
LVDS Chanel 0 positive output
LVDS Chanel 0 negative output
LVDS Chanel 2 positive output
LVDS Chanel 2 negative Output
Ground 0V
LVDS Clock positive output
LVDS Clock negative output
Camera master clock output
I2C2 Clock output
Ground 0 V
Ethernet speed indicator (open drain)
Transmit positive output (normal)
Receive positive input (reversed)
Transmit negative output (normal)
Receive negative input (reversed)
Ground 0 V
USB-OTG power switch output open drain
USB-OTG over current input signal
Ground 0 V
USB OTG VBUS voltage (5 V optional)
USB OTG transceiver cable interface, DUSB OTG transceiver cable interface, D+
USB OTG on the go transceiver cable ID resistor
connection
Ground 0 V
1
:
10
in
a
el
im
Pr
Table 3:
ry
Pin Row X1A
Pin #
Signal
Pinout of the phyCARD-Connector X1, Row A
Caution! The current draw at VDD_3V3_LOGIC must not exceed 500 mA.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Pin Description
I/O
SL
Description
31A
32A
33A
34A
35A
36A
37A
38A
39A
40A
41A
42A
X_SDIO_D0
X_SDIO_D2
X_SDIO_CLK
GND
X_SPI_CS0
X_SPI_RDY
X_SPI_SCLK
GND
X_UART_TXD
X_UART_RTS
GND
X_AC97_INT
I/O
I/O
O
O
O
O
O
O
I/O-
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
43A
44A
45A
46A
47A
48A
49A
50A
X_I2S_SDATA_OUT
X_I2S_SDATA_IN
GND
X_GPIO0/IRQ0
X_GPIO2/IRQ/PWM
X_nWKUP
GND
X_CONFIG0
O
I
I/O
I/O
I
I
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VSTBY
SD/MMC Data line D0 both in 1-bit and 4-bit mode
SD/MMC Data line D 2both in 1-bit and 4-bit mode
SD/MMC Clock for MMC/SD/SDIO
Ground 0 V
SPI3 Chip select 0
SPI3 Data ready in master mode
SPI3 Clock
Ground 0 V
Serial transmit signal UART3
Request to send UART 3
Ground 0 V
I2S Selection ( 1 kΩ pull-down (R67) to configure CB or
target application for I2S audio interface)
I2S Transmit output (AUD5)
I2S Receive input (AUD5)
Ground 0 V
GPIO0/IRQ (μC port GPIO2_24))
GPIO2/IRQ/PWM (μC port GPIO4_29)
Wakeup interrupt input (Port P2.1 of CMIC at U17)
Ground 0 V
Boot-Mode input 0
Pin Row X1B
Pin # Signal
VDD_3V3
VDD_3V3
VDD_3V3
GND
VDD_3V3_LOGIC 1
VSTBY_IN
X_nRESET_OUT
GND
X_LVDS_TX1+
X_LVDS_TX1X_LVDS_TX3+
X_LVDS_TX3GND
X_LVDS_CAM_RX+
X_LVDS_CAM_RXX_LVDS_CAM_nLOCK
X_I2C_SDA
GND
X_ETH_LINK
Pr
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
Table 4:
1
:
in
a
Pinout of the phyCARD-Connector X1, Row A (continued)
el
im
Table 3:
ry
Pin Row X1A
Pin #
Signal
I/O
SL
Description
O
O
O
O
O
I
I
O
I/O
O
Power
Power
Power
Power
Power
Power
VDD_3V3_LOGIC
Power
LVDS
LVDS
LVDS
LVDS
Power
LVDS
LVDS
LVDS
VDD_3V3_LOGIC
Power
VDD_ETH_3V3
3.3 V Primary voltage supply input
3.3 V Primary voltage supply input
3.3 V Primary voltage supply input
Ground 0 V
VCC Logic output
Standby voltage input
Active low reset output
Ground 0 V
LVDS Chanel 1 positive output
LVDS Chanel 1 negative output
LVDS Chanel 3 positive output
LVDS Chanel 3 negative output
Ground 0 V
Camera data positive input
Camera data negative input
Camera lock output (active low)
I2C2 Data
Ground 0 V
Ethernet Link Indicator (open drain)
Pinout of the phyCARD-Connector X1, Row B
Caution! The current draw at VDD_3V3_LOGIC must not exceed 500 mA.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
11
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Pin Row X1B
Pin #
Signal
I/O
20B
X_ETH_RX+
I (O) VDD_ETH_3V3
21B
X_ETH_RX-
I (O) VDD_ETH_3V3
22B
23B
24B
25B
26B
GND
X_nUSB_HOST_PWR
X_nUSB_HOST_OC
GND
X_nSUSPEND_TO_RAM
O
I
OC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
27B
28B
29B
30B
31B
32B
33B
34B
35B
36B
37B
38B
39B
40B
41B
42B
43B
44B
45B
46B
X_USB_HOST_DX_USB_HOST_D+
X_nPOWER_OFF
GND
X_SDIO_D1
X_SDIO_D3
X_SDIO_CMD
GND
X_SPI_CS1
X_SPI_MOSI
X_SPI_MISO
GND
X_UART_RXD
X_UART_CTS
GND
X_I2S_BIT_CLK
X_I2S_SYNC
X_I2S_nRESET
GND
X_SDIO_CD
I/O
I/O
OC
I/O
I/O
O
O
I/O
I/O
I
I
I/O
O
O
I
USB
USB
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Power
VDD_3V3_LOGIC
Description
X_GPIO1/IRQ1
X_HW_INTROSPECTION/
GPIO5_26
I/O
I/O
VDD_3V3_LOGIC
VDD_3V3_LOGIC
49B
50B
GND
X_CONFIG1
I
Power
VSTBY
12
ry
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47B
48B
Table 4:
Receive positive input (normal)
Transmit positive output (reversed)
Receive negative input (normal)
Transmit negative output (reversed)
Ground 0 V
USB-HOST1 Power switch output open drain
USB-HOST1 over current input signal
Ground 0 V
Suspend to RAM open collector output (μC port
GPIO1_24)
USB HOST1 transceiver cable interface, DUSB HOST1 transceiver cable interface, D+
Power Off open collector output (μC port GPIO1_25)
Ground 0 V
SD/MMC Data line both in 1-bit and 4-bit mode
SD/MMC Data line both in 1-bit and 4-bit mode
SD/MMC Command for MMC/SD/SDIO
Ground 0 V
SPI3 Chip select 1
SPI3 Master data out; slave data in
SPI3 Master data in; slave data out
Ground 0 V
Serial data receive signal UART3
Clear to send UART3
Ground 0 V
I2S Clock (AUD5)
I2S Frame SYNC (AUD5)
Reset for external I2S device (connects to GPIO7_12)
Ground 0 V
SD/MMC Card detect for MMC/SD/SDIO (μC port
GPIO5_22)
GPIO1/IRQ (μC port GPIO1_06)
Hardware introspection interface
for internal use only
in
a
SL
Ground 0 V
Boot-Mode input 1
Pinout of the phyCARD-Connector X1, Row B (continued)
© PHYTEC Messtechnik GmbH 2014
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Jumpers
3
Jumpers
For configuration purposes, the phyCARD-i.MX 6 has several solder jumpers, some of which
have been installed prior to delivery. Figure 5 illustrates the numbering of the solder
jumper pads, while Figure 6 and Figure 7 indicate the location of the solder jumpers on the
board. Table 5 provides a functional summary of the solder jumpers which can be changed
to adapt the phyCARD-i.MX 6 to your needs. It shows their default positions, and possible
alternative positions and functions. A detailed description of each solder jumper can be
found in the applicable chapter listed in the table.
in
a
closed
e.g.: J3
e.g.: J3
e.g.: J31
Typical Jumper Pad Numbering Scheme
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Figure 5:
ry
Note:
Jumpers not listed should not be changed as they are installed with regard to the
configuration of the phyCARD-i.MX 6.
Pr
If manual jumper modification is required please ensure that the board as well as
surrounding components and sockets remain undamaged while de-soldering. Overheating
the board can cause the solder pads to loosen, rendering the module inoperable. Carefully
heat neighboring connections in pairs. After a few alternations, components can be
removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and
loosen the bonds.
© PHYTEC Messtechnik GmbH 2014
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13
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Please pay special attention to the "TYPE" column to ensure you are using the correct type
of jumper (0 Ω, 10 kΩ, etc…). The jumpers are either 0805 package or 0402 package with a
1/8 W or better power rating.
8
6
4
2
6
4
2
Pr
J3
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in
a
ry
20 18 16 14 12 10
Figure 6:
14
Jumper Locations (top view)
© PHYTEC Messtechnik GmbH 2014
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Jumpers
3
5
1
3
5
7
9
11 13 15 17 19
ry
1
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in
a
J31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
25
1
1
Pr
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99100
Figure 7:
Jumper Locations (bottom view)
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15
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
The jumpers (J = solder jumper) have the following functions:
Jumper
Description
J3
J3 connects the write protect input of the on board EEPROM at U10
with GND. If this jumper is not populated, the EEPROM is write
protected.
closed EEPROM is not write protected
Type
Chapter
0R
(0402)
7.3.1
0R
(0402)
14.1
open EEPROM is write protected. The protection can be changed by the
EEPROM_WP/GPIO3_19 signal
J31 selects rising, or falling edge strobe for the LVDS Deserializer at
U27 used for the camera connectivity of the phyCARD-i.MX 6
J31
ry
2+3 rising edge strobe used for the LVDS camera signals
1+2 falling edge strobe used for the LVDS camera signals
Jumper Settings
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in
a
Table 5:
16
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Power Requirements
4
Power
The phyCARD-i.MX 6 operates off of a single power supply voltage.
The following sections of this chapter discuss the primary power pins on the
phyCARD-Connector X1 in detail.
4.1 Primary System Power (VDD_3V3)
ry
The phyCARD-i.MX 6 operates off of a primary voltage supply with a nominal value of
+3.3 V. The on-board power management IC (PMIC) at U29 generates the 2.5 V, 1.375 V,
1.5 V, 0.75 V, 1.2 V and 3.0 V voltage supplies required by the i.MX 6 MCU and on-board
components from the primary 3.3 V (VDD_3V3) supplied to the SOM.
VDD_3V3:
X1
in
a
For proper operation the phyCARD-i.MX 6 must be supplied with a voltage source of 3.3 V
±5% with 1.5 A load at the VCC pins on the phyCARD-Connector X1.
1A, 2A, 3A, 1B, 2B, 3B
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Connect all +3.3 V VCC input pins to your power supply and at least the matching number of
GND pins.
Corresponding GND:
X1
4A, 8A, 13A, 4B, 8B, 13B
Please refer to section 2 for information on additional GND Pins located at the
phyCARD-Connector X1.
Pr
Caution!
As a general design rule we recommend connecting all GND pins neighboring signals which
are being used in the application circuitry. For maximum EMI performance all GND pins
should be connected to a solid ground plane.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
4.2 Backup Voltage (VSTBY)
VSTBY is an additional supply voltage input which has to be connected to a supply voltage
of 3.3 V +/- 5% if power management functions will be used. This input voltage supplies
the control management IC (CMIC) at U17, which is necessary for all power management
functions of the phyCARD module, and the RTC of the power management IC at U29.
ry
To backup the RTC of the power management IC (PMIC) on the module, it is necessary to
attach a secondary voltage source of 3.3 V to the phyCARD-i.MX 6 at pin X1B6. This voltage
source is supplying the internal backup voltage domain VBACKUP of the PMIC which again
supplies the RTC and some critical registers if the primary system power (VDD_3V3) is
removed. Applications not requiring a backup mode or power management functions can
connect the VSTBY_IN pin to the primary system power supply (VDD = 3.3 V).
4.3 Power Management IC (U29) / Control Management IC (U17)
in
a
The phyCARD-i.MX 6 provides a Power Management IC (PMIC) at U29 (DA9063) and a
Control Management IC (CMIC) at U17 (MSP430G2153).
Figure 8 presents a graphical depiction of the powering scheme.
Power Management IC (PMIC, U29)
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4.3.1
The PMIC at U29 generates the different voltages required by the processor and on-board
components, and provides features such as on-chip RTC and different power management
functionalities. It is connected to the i.MX 6 via the I2C bus I2C1. The I2C1 addresses for
the PMIC at U29 is 0x58 (page 0 and 1) and 0x59 (page 2 and 3).
Please refer to the dialog SEMICONDUTOR DA9063 datasheet for further information.
Control Management IC (CMIC, U17)
Pr
4.3.2
The control management IC at U17 is monitoring the supply voltages and generates
necessary control signals for the i.MX 6 processor in respect to the different input signals.
It also ensures the correct power sequencing during powering up of the module and
configures the boot mode of the i.MX 6 (s. section 6).
U17 generates a reset if the on-board voltage generator senses a voltage drop on the
primary supply voltage and generates a reset signal, or if a reset is applied at pin X1A7 of
the phyCARD-Connector.
18
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Power Requirements
4.3.3
Power Domains
The PMIC has two input voltage rails VDD_3V3 and VSTBY_IN as can be seen in Figure 8.
VDD_3V3 is directly connected to the primary voltage input pins VDD_3V3 of the
phyCARD-i.MX 6, whereas VDD_3V3_LOGIC is attached to the primary voltage input pins
VDD_3V3 via switch Q17. Q17 is controlled by the PMIC at U29. Not all devices on the
phyCARD-i.MX 6 are supplied by the internally generated voltages. Some devices, such as
the Ethernet PHY, the LVDS FlatLink™ transmitter, etc. are powered by the primary input
voltage VDD_3V3. The following list summarizes the relation between the different voltage
rails and the devices on the phyCARD-i.MX 6:
ry
External voltages: VDD_3V3 and VSTBY_IN
Internally generated voltages: VDD_MX6_ARM_1V4 (1.375 V), VDD_MX6_SOC (1.375 V),
VDD_3V3_LOGIC (3.3 V), VDD_MX6_SNVS (3.0 V), VDD_HIGH (3.0 V), VDD_DDR3_TERM
(1.2V), VDD_DDR3_1V5 (1.5 V), DDR3_VTT (0.75 V), DDR3_VREF (0.75 V).
VDD_MX6_ARM_1V4: i.MX 6 core (VDDARM_IN, VDDARM23_IN)
(1.375 V)
•
VDD_MX6_SOC:
(1.375 V)
i.MX 6 SOC (VDDSOC_IN)
•
VDD_HIGH:
(3.0 V)
i.MX 6 internal regulator (VDDHIGH_IN)
•
VDD_MX6_SNVS:
(3.0 V)
i.MX 6 backup supply (VDD_SNVS_IN)
•
VDD_DDR3_1V5:
(1.5 V)
i.MX 6 DDR (NVCC_DRAM), RAM devices supply voltage
•
DDR3_VTT:
(0.75 V)
RAM devices termination voltage
•
DDR3_VREF:
(0.75 V)
i.MX 6 DDR3 reference voltage (DRAM_VREF), RAM
devices reference voltage
•
VDD_3V3_LOGIC:
(3.3 V)
i.MX 6 pad supply (NVCC_NANDF, NVCC_JTAG, NVCC_LCD,
NVCC_CSI, NVCC_EIM, NVCC_GPIO), I2C EEPROM, SPI Flash,
NAND Flash, Camera Deserializer, Ethernet PHY, EMIC
•
USB_VBUS
(5V)
USB Host/OTG PHY
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in
a
•
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19
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
VSTBY_IN
VDD_3V3
SWITCH
VDD_3V3_LOGIC
SWITCH
SWITCH
in
a
VDD_MX6_SOC
VDD_DDR3_1V5
DA9063
LDOs
20
DDR3 LDO
DDR3_VREF
VDD_MX6_SNVS
Pr
Figure 8:
DDR3_VTT
VDD_DDR3_TERM
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Switching regulators
VDD_MX6_ARM_1V4
ry
PERI_SWG
VDD_MX6_HIGH
USB_VBUS
USB 5V
(Chargepump)
Power Supply Diagram
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Power Requirements
4.4 Supply Voltage for external Logic
The voltage level of the phyCARDs logic circuitry is VDD_3V3 (3.3 V) which is derived from
the main input voltage VDD_3V3 of the SOM. In order to follow the power-up and power–
down sequencing mandatory for the i.MX 6 external devices have to be supplied by the I/O
supply voltage VDD_3V3_LOGIC which is brought out at pins X1A5 and X1B5 of the
phyCARD-Connector. Use of VDD_3V3_LOGIC ensures that external components are only
supplied when the supply voltages of the i.MX 6 are stable.
ry
Caution!
The current draw for VDD_3V3_LOGIC must not exceed 500 mA. If devices with a higher
power consumption are to be connected to the phyCARD-i.MX 6 they should be switched on
and off by use of VDD_3V3_LOGIC. This way the power-up and power–down sequencing will
be considered even if the devices are not supplied directly by VDD_3V3_LOGIC.
el
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in
a
If used to control, or supply bus switches on the phyCARD side VDD_3V3_LOGIC also serves
to strictly separate the supply voltages generated on the phyCARD-i.MX 6 and the supply
voltages used on the carrier board/custom application. That way voltages at the IO pins of
the phyCARD-i.MX 6 which are sourced from the supply voltage of peripheral devices
attached to the SOM are avoided. These voltages can cause a current flow into the
controller especially if peripheral devices attached to the interfaces of the i.MX 6 are
supposed to be powered while the phyCARD-i.MX 6 is in suspend mode, or turned off. The
bus switches can either be supplied by VDD_3V3_LOGIC on the phyCARD side, or the bus
switches' output enable to the SOM can be controlled by VDD_3V3_LOGIC to prevent these
voltages from occurring.
Pr
Use of VDD_3V3_LOGIC to supply level shifters allows converting the signals according to
the needs on the custom target hardware. Alternatively signals can be connected to an
open drain circuitry with a pull-up resistor attached to VDD_3V3_LOGIC.
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21
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a
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
22
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Power Management
5
Power Management
The phyCARD-i.MX 6 was designed to support applications requiring a power management.
Three pins of the X-Arc bus are designated for this purpose. X_nPOWER_OFF and
X_nSUSPEND_TO_RAM are output pins which can be used to indicate the power status of
the phyCARD-i.MX 6, whereas X_nWKUP is an input pin to apply a wake up signal to the
phyCARD-i.MX 6.
ry
The three power management signals are connected to ports of the control management IC
(CMIC) at U17. Thus their functionality can be programmed to your needs (refer to
section 4.3.2).
The following table shows the location of the power management pins on the phyCARDConnector and the corresponding ports of the CMIC.
X1A48
X_nWKUP
X1B26
X_nSUSPEND_TO_RAM
X1B29
X_nPOWER_OFF
Table 6:
I/O SL
Description
in
a
Signal
I
VDD_3V3_LOGIC
OC
VDD_3V3_LOGIC
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Pin #
OC
VDD_3V3_LOGIC
Wakeup Interrupt Input
(port P2.1 of CMIC at U17)
Suspend to RAM Open Collector
Output
(port P3.3 of CMIC at U17)
Power Off Open Collector Output
(port P3.2 of CMIC at U17)
Power Management Pins
Pr
With the two output signals X_nPOWER_OFF (pin X1B29) and X_nSUSPEND_TO_RAM (pin
X1B26) three different power states can be defined.
Power State
Signal
X_nSUSPEND_TO_RAM
X_nPOWER_OFF
VDD_3V3
VSTBY
Power On
Standby
Off
High
High
On
X
Low
High
Off
On
X
Low
Off
Off
X=don’t care
Table 7:
Power States
Please refer to the chapter "Power Management" in the phyCARD Design-In Guide for more
information about the implementation of the power management into your design.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Caution!
According to the specification for the phyCARD family writing custom software to utilize
pins X_nSUSPEND_TO_RAM and X_nPOWER_OFF requires them to be configured as Open
Collector Output.
Pr
el
im
in
a
ry
The power management features of the phyCARD are implemented with the devices at U29
(PMIC) and U17 (CMIC) and allow for a higher granularity in control of the power
consumption. To implement power management with the PMIC it can be programmed via
an I2C interface at I2C address 0x58. Please refer to the PMIC's User's Guide for more
information.
24
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System Configuration and Booting
6
System Configuration and Booting
Although most features of the i.MX 6 microcontroller are configured and/or programmed
during the initialization routine, other features, which impact program execution, must be
configured prior to initialization via pin termination.
The system start-up configuration includes:
• Boot device order configuration
in
a
ry
During the reset cycle the operational system boot mode of the i.MX 6 processor is
determined by the configuration of two BOOTMODE pins BOOT_MODE[1:0]. These pins
select the boot type. If the boot type is set to “Internal boot” (BOOT_MODE[1:0]=10, pins
BOOT_CFGx[7:0] are used to configure further boot options. You can find further
information about these boot pins in the i.MX 6 Reference Manual.
el
im
To allow flexible selection of the booting device not all of the BOOT_CFGx[7:0] pins are
preconfigured 10 kΩ pull-up, or pull-down configuration resistors, or by jumpers on the
phyFLEX-i.MX 6. Some signals are set by the CMIC at U17. During powering up the boot
configuration pins X_CONFIG1 and X_XONFIG2 of the module are read by the CMIC.
Depending on the setting of these pins the CMIC configures BOOT_MODE[1:0],
BOOT_CFG1[7] and BOOT_CFG2[1]. It also ensures the correct power up sequencing so that
the i.MX 6 is powered only after the configuration of the boot mode pins. Table 8 shows the
possible settings of pins X_CONFIG1 and X_XONFIG2 and the resulting boot configuration
of the i.MX 6. This mechanism provides the possibility to customize the boot behavior by
changing the code of the CMIC.
Pr
After the i.MX 6 is powered up the internal ROM code is the first code executed during the
initialization process of the controller. The ROM code detects which boot devices the
controller has to check by using the previously set BOOT_MODE[1:0] and particular
BOOT_CFGx[7:0] pin configuration. For serial boot devices, the ROM code polls the
communication interface selected, initiates the download of the code into the internal
RAM and triggers its execution from there. For memory booting, the ROM code finds the
bootstrap in permanent memories such as NAND-Flash or SD-Cards and executes it. Please
refer to the i.MX 6 Reference Manual for more information.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Boot Mode
X_CONFIG1
X_CONFIG0
0
1
1
NAND
1
1
0
SD0 external
2
0
1
Serial USB OTG (USB0)
3
0
0
Bootconfig from eFUSE
Table 8:
Bootsource
Boot Modes of the phyCARD-i.MX 6 1
The X_CONFIG[1:0] lines have 10 kΩ pull-up resistors populated on the module. Hence
leaving the two pins unconnected sets the controller to boot mode 0, NAND boot.
in
a
ry
If boot configurations are needed that require change of other boot configuration pins
than BOOT_MODE[1:0], BOOT_CFG1[7] and BOOT_CFG2[1] the specific boot settings can
also be changed by modifying the resistors and jumpers on the module. Please consider
that any change of the default BCFG configuration can also influence other boot modes,
which might result in faulty boot behavior.
For further information about the different boot modes and the influence of the BCFG pins
please see the i.MX 6 Reference Manual.
0
:
26
BCFG1[7]
0b10
BCFG2[1]
Description
1
High-Z
NAND
1
0b10
0
High-Z
SD0
2
0b01
High-Z
High-Z
USB OTG
3
0b00
High-Z
High-Z
eFUSE
Table 9:
1
BOOT_MODE
[1:0]
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Boot
Mode
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The following table shows to which level the CMIC sets the different configuration signals
for the boot modes. “High-Z” means that the CMIC sets the signal to high impedance, and
thus the value of the configuration resistor is used.
Boot Configuration Signals generated by the CM
Default settings are in bold blue text
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System Memory
7
System Memory
The phyCARD-i.MX 6 provides three types of on-board memory:
• 2 Banks DDR3 RAM:
• NAND Flash (VFBGA):
• I²C-EEPROM:
512 MB DDR3 SDRAM (up to 4 GB) 1
256 MB (up to 4 GB)1
4 kB1
The following sections of this chapter detail each memory type used on the
phyCARD-i.MX 6.
ry
7.1 DDR3 SDRAM (U2-U9)
in
a
The RAM memory of the phyCARD-i.MX 6 is comprised of up to two 64 bit wide banks each of
four 16-bit wide DDR3-SDRAM chips (Bank 1: U2-U5, Bank 2: U6-U9). The chips are
connected to the special DDR interface called Multi Mode DDR Controller (MMDC) of the
i.MX 6 processor.
The DDR3 memory is accessed via the second AHB port starting at 0x1000 0000.
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im
Typically the DDR3 SDRAM initialization is performed by a boot loader or operating system
following a power-on reset and must not be changed at a later point by any application
code. When writing custom code independent of an operating system or boot loader,
SDRAM must be initialized by accessing the appropriate SDRAM configuration registers on
the i.MX 6 controller. Refer to the i.MX 6 Reference Manual for accessing and configuring
these registers.
Pr
7.2 NAND Flash Memory (U13)
Use of Flash as non-volatile memory on the phyCARD-i.MX 6 provides an easily
reprogrammable means of code storage.
These Flash devices are programmable with 3.3 V. No dedicated programming voltage is
required.
As of the printing of this manual these NAND Flash devices generally have a life expectancy
of at least 100,000 erase/program cycles and a data retention rate of 10 years.
The NAND Flash memories are connected to the External Interface Module (EIM). /CS0
(NANDF_CS0) of the EIM interface selects the NAND Flash at U13.
Any parts that are footprint (TSOP-48-50-C3) and functionally compatible may be used
with the phyCARD-i.MX 6 .
1
:
Please contact PHYTEC for more information about additional module configurations.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
7.3 I²C EEPROM (U10)
The phyCARD-i.MX 6 is populated with a non-volatile 4 kB I²C 1 EEPROM at U10. This memory
can be used to store configuration data or other general purpose data. This device is
accessed through I²C port 1 on the i.MX 6. The control registers for I²C port 1 are mapped
between addresses 0x021A 0000 and 0x021A 3FFF. Please see the i.MX 6 Reference Manual
for detailed information on the registers.
The three lower address bits are fixed to zero which means that the EEPROM can be
accessed at I2C address 0x50.
7.3.1
ry
Write protection to the device is accomplished via jumper J3. Refer to section 7.3.1 for
further details on setting this jumper.
EEPROM Write Protection Control (J3)
in
a
Jumper J3 controls write access to the EEPROM (U10) device. Closing this jumper allows
write access to the device, while removing this jumper will cause the EEPROM to enter write
protect mode, thereby disabling write access to the device.
The following configurations are possible:
Table 10:
J3
closed
open
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EEPROM Write Protection State
Write access allowed
Write protected
EEPROM write protection states via J3 2
Pr
Note: If the jumper is not set, the write protection signal can also be changed by GPIO3_19
of the i.MX 6 controller.
1
:
:
2
28
See the manufacturer’s data sheet for interfacing and operation.
Defaults are in bold blue text
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SD / MMC Card Interfaces
8
SD / MMC Card Interfaces
ry
The X-Arc bus features an SD / MMC Card interface. On the phyCARD-i.MX 6 the interface
signals extend from the controllers third Ultra Secured Digital (uSDHC3) Host Controller to
the phyCARD-Connector. Table 11 shows the location of the different interface signals on
the phyCARD-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD
Memory Card Specification 3.0 and SD I/O Specification, Part E1, v1.10. The SDC / MMC
interface (uSDHC3 of the i.MX 6) of the phyCARD-i.MX 6 supports 4 of the host controller's
8 data channels with a maximum data rate of 104 Mbps (refer to the i.MX 6 Reference
Manual for more information). The MMC/SD/SDIO Host Controller is supplied by the
VDD_3V3_LOGIC voltage, which is derived from the main power supply of the phyCARDi.MX 6 (3.3 V).
Pin #
X1A31
X1A32
Signal
X_SDIO_D0
X_SDIO_D2
X1A33
X_SDIO_CLK
O
VDD_3V3_LOGIC
X1B31
X1B32
X_SDIO_D1
X_SDIO_D3
I/O
I/O
VDD_3V3_LOGIC
VDD_3V3_LOGIC
X1B33
X_SDIO_CMD
I/O
VDD_3V3_LOGIC
X1B46
X_SDIO_CD
I
VDD_3V3_LOGIC
Pr
Table 11:
SL
VDD_3V3_LOGIC
VDD_3V3_LOGIC
el
im
I/O
I/O
I/O
in
a
Because of compatibility reasons a card detect signal (X_SDIO_CD) is added to the SD /
MMC Card Interface. The card detect function is implemented by using GPIO5_22 of the
i.MX 6.
Description
SD/MMC data bit 0
SD/MMC data bit 2
SD/MMC clock for
MMC/SD/SDIO0
SD/MMC data bit 1
SD/MMC data bit 3
SD/MMC command for
MMC/SD/SDIO0
SD/MMC card insertion and
extraction detection (GPIO5_22
of the i.MX 6)
Location of SD/ MMC Card Interface Signals
© PHYTEC Messtechnik GmbH 2014
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29
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Note:
In order to follow the power-up and power–down sequencing mandatory for the i.MX 6 the
SD / MMC card interface should be supplied by the I/O supply voltage VDD_3V3_LOGIC
which is brought out at pins X1A5 and X1B5 of the phyCARD-Connector. Use of
VDD_3V3_LOGIC ensures that the interface is only supplied when the supply voltages of the
i.MX 6 are stable.
ry
Caution!
The current draw for VDD_3V3_LOGIC must not exceed 500 mA. If devices with a higher
power consumption are to be connected to the GPIOs of the phyCARD-i.MX 6 they should be
switched on and off by use of VDD_3V3_LOGIC. This way the power-up and power–down
sequencing will be considered even if the devices are not supplied directly by
VDD_3V3_LOGIC.
in
a
The i.MX 6's requires strict separation of the supply voltages generated on the
phyCARD-i.MX 6 and the supply voltages used on the carrier board/custom application. To
avoid voltages which are sourced from the supply voltage of the SD / MMC card interface
bus switches powered by VDD_3V3_LOGIC on the phyCARD side should be used.
Alternatively, the bus switches' output enable to the SOM can be controlled by
VDD_3V3_LOGIC (please refer to section 4.4 for more information).
Pr
el
im
Please refer to the chapter "SD / MMC" in the phyCARD Design-In Guide for more
information about connecting an SD / MMC Card slot to the phyCARD-i.MX 6.
30
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Serial Interfaces
9
Serial Interfaces
The phyCARD-i.MX 6 provides seven serial interfaces some of which are equipped with a
transceiver to allow direct connection to external devices:
3.
4.
5.
6.
7.
ry
2.
High speed UART (TTL, derived from UART3 of the i.MX 6) with up to 4 MHz and
hardware flow control (RTS and CTS signals)
High speed USB OTG interface (extended directly from the i.MX 6 USB-HS OTG PHY
(USB-PHY))
High speed USB HOST interface (extended directly from the i.MX 6 USB HOST PHY
(USB-PHY))
Auto-MDIX enabled 10/100 Ethernet interface (implemented with an Ethernet PHY
attached to the i.MX 6 MII (ENET) interface)
I2C interface (derived from second I2C port (I2C2) of the i.MX 6)
Serial Peripheral Interface (SPI) interface (extended from the third SPI module
(eCSPI3) of the i.MX 6)
I2S audio interface Synchronous Serial Interface (SSI5)) (originating from the fifth
port of the i.MX 6’s Synchronous Serial Interface (SSI5))
in
a
1.
el
im
The following sections of this chapter detail each of these serial interfaces and any
applicable configuration jumpers.
Pr
Caution!
The i.MX 6's power sequencing requires strict separation of the supply voltages generated
on the phyCARD-i.MX 6 and the supply voltages used on the carrier board/custom
application. Especially if peripheral devices attached to the interfaces of the i.MX 6 are
supposed to be powered while the phyCARD-i.MX 6 is in suspend mode, or turned off. This
situation might result in voltages at the IO pins of the phyCARD-i.MX 6 which are sourced
from the supply voltage of the peripheral device, and which cause a current flow into the
controller. To avoid these voltages bus switches powered by VDD_3V3_LOGIC on the
phyCARD side should be used. Alternatively, the bus switches' output enable to the SOM
can be controlled by VDD_3V3_LOGIC.
Please refer to the phyCARD Design-In Guide (LAN-051) for more information about using
the serial interfaces of the phyCARD-i.MX 6 in customer applications.
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31
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
9.1 Universal Asynchronous Interface
The phyCARD-i.MX 6 provides a high speed universal asynchronous interface with up to
4 MHz and hardware flow control (RTS and CTS signals). The following table shows the
location of the signals on the phyCARD-Connector.
Table 12:
Signal
X_UART_TXD
X_UART_RTS
X_UART_RXD
X_UART_CTS
I/O
O
O
I
I
SL
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Location of the UART Signals
Description
Serial data transmit signal UART 3
Request to send UART 3
Serial data receive signal UART 3
Clear to send UART 3
ry
Pin #
X1A39
X1A40
X1B39
X1B40
9.2 USB OTG Interface
in
a
The signals extend from UART3 of the i.MX 6 directly to the phyCARD-Connector without
conversion to RS-232 level. External RS-232 transceivers must be attached by the user if
RS-232 levels are required.
el
im
The phyCARD-i.MX 6 provides a high speed USB OTG interface which uses the i.MX 6
embedded HS USB OTG PHY.
Because of the processor is not featuring the USB over current detection GPIO1_20 can be
used as USB-OTG over current input signal. The signal is active low.
Pr
For self-powered devices an external USB Standard-A (for USB host), or USB mini-AB (for
USB OTG) connector is all that is needed to interface the phyCARD-i.MX 6 USB OTG
functionality. To attach devices which require the VBUS supply voltage an external power
logic (or charge pump) capable of sourcing 5 V power must be provided on the carrier
board. Signal X_nUSB_OTG_PWR (X1A23) allows control of the external power logic. After
reset signal X_nUSB_OTG_PWR is low (meaning active). Therefore an external power switch
is enabled and booting via USB is possible.
The applicable interface signals can be found on the phyCARD-Connector as shown in Table
13.
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Serial Interfaces
Pin #
Signal
X1A23
X_nUSB_OTG_PWR O
X1A24
X_nUSB_OTG_OC
I
X1A26
X1A27
X1A28
X_USB_VBUS
X_USB_DM
X_USB_DP
I
I/O
I/O
X1A29
X_USB_UID
I
SL
Description
USB OTG power switch output open
VDD_3V3_LOGIC
drain, low active
USB OTG over current input signal,
VDD_3V3_LOGIC
low active
5V
USB VBUS voltage
USB transceiver cable interface, DUSB transceiver cable interface, D+
USB on the go transceiver cable ID
resistor connection
Location of the USB OTG Signals
ry
Table 13:
I/O
in
a
In order to use the phyCARD-i.MX 6 as USB device an USB Standard-B connector) and an
appropriate configuration of the ID pin on the carrier board is all that is needed.
9.3 USB Host Interface
el
im
The i.MX 6 provides a high speed USB Host interface which uses the i.MX 6 embedded HS
USB Host PHY.
Neither VBUS detection, nor the ID pin is required. Therefore USB_VBUS and ID are not
brought out to the phyCARD-Connector.
Pr
For self-powered devices an external USB Standard-A (for USB Host) connector is all that is
needed to interface the phyCARD-i.MX 6 USB Host functionality. To attach devices which
require the VBUS supply voltage an external power logic (or charge pump) capable of
sourcing 5 V power must be provided on the carrier board. Signal X_nUSB_HOST_ PWR
(X1B23) allows control of the external power logic. It can be used to switch an external
VBUS power supply and is derived from the USB HOST interface of the i.MX 6.
The applicable interface signals (D+/D-/ PWR/OC) can be found on the phyCARD-Connector
as shown in the following table.
Pin #
Signal
I/O
SL
X1B23 X_nUSB_HOST_PWR O
VDD_3V3_LOGIC
X1B24 X_nUSB_HOST_OC
I
VDD_3V3_LOGIC
X1B27 X_USB_HOST_D-
I/O
X1B28 X_USB_HOST_D+
I/O
Table 14:
Description
USB-HOST power switch output
open drain
USB-HOST over current input
signal
USB HOST transceiver cable
interface, DUSB HOST transceiver cable
interface, D+
Location of the USB-Host Signals
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
9.4 Ethernet Interface
Connection of the phyCARD-i.MX 6 to the world wide web or a local area network (LAN) is
possible using the on-board PHY at U11. It is connected to the MII interface of the i.MX 6.
The FEC operates with a data transmission speed of 10 Mbit/s or 100 Mbit/s.
9.4.1
Ethernet PHY (U11)
With an Ethernet PHY mounted at U11 the phyCARD-i.MX 6 has been designed for use in
10Base-T and 100Base-T networks. The 10/100Base-T interface with its LED signals
extends to phyCARD-Connector X1.
I/O
O
X1A20
X_ETH_TX+
O (I) VCC_3V3
X1A21
X_ETH_TX-
O (I) VCC_3V3
X1B19
X_ETH_LINK
O
X1B20
X_ETH_RX+
I (O) VCC_3V3
X1B21
X_ETH_RX-
Description
Ethernet Speed Indicator (Open Drain)
Transmit positive output (normal)
Receive positive input (reversed)
Transmit negative output (normal)
Receive negative input (reversed)
Ethernet Link Indicator (Open Drain)
Receive positive input (normal)
Transmit positive output (reversed)
Receive negative input (normal)
Transmit negative output (reversed)
VCC_3V3
el
im
Table 15:
SL
VCC_3V3
ry
Signal
X_ETH_SPEED
in
a
Pin #
X1A19
I (O) VCC_3V3
Location of the Ethernet Signals
Pr
The Ethernet transceiver supports HP Auto-MDIX technology, eliminating the need for the
consideration of a direct connect LAN cable, or a cross-over patch cable. It detects the TX
and RX pins of the connected device and automatically configures the PHY TX and RX pins
accordingly. The Ethernet controller also features an Auto-negotiation to automatically
determine the best speed and duplex mode.
The Ethernet transceiver is directly connected to the MII Interface of the i.MX 6. Please
refer to the i.MX 6 Reference Manual for more information about this interface.
In order to connect the module to an existing 10/100Base-T network some external
circuitry is required. The required 49.9 Ω +/-1% termination resistors on the analog
signals (ETH_RX±, ETH_TX±) are already populated on the module. Connection to an
external Ethernet magnetics should be done using very short signal traces. The TPI+/TPIand TPO+/TPO- signals should be routed as 100 Ω differential pairs. The same applies for
the signal lines after the transformer circuit. The carrier board layout should avoid any
other signal lines crossing the Ethernet signals.
An example for the external circuitry is shown in the phyCARD's Design Guide.
34
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Serial Interfaces
If you are using the applicable carrier board for the phyCARD-i.MX 6 (part number
PBA-A-03), the external circuitry mentioned above is already integrated on the board
(refer to section 17.3.4).
Caution!
Please see the datasheet of the Ethernet transceiver as well as the phyCARD's Design Guide
(LAN-051) when designing the Ethernet transformer circuitry.
The reset input of the Ethernet controller is permanently connected to the reset output
signal POR_B of the control management IC U17 on the phyCARD-i.MX 6 (refer to section
4.3.2).
MAC Address
ry
9.4.2
in
a
In a computer network such as a local area network (LAN), the MAC (Media Access Control)
address is a unique computer hardware number. For a connection to the Internet, a table is
used to convert the assigned IP number to the hardware's MAC address.
el
im
In order to guarantee that the MAC address is unique, all addresses are managed in a
central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the
phyCARD-i.MX 6 is located on the bar code sticker attached to the module. This number is a
12-digit HEX value.
9.5 I2C Interface
Pr
The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that
provides a simple and efficient method for data exchange among devices. The i.MX 6
contains three identical and independent multimaster Fast mode I2C modules. The
interface of the third module (I2C3) extends directly to the phyCARD-Connector. No other
components are connected to this I2C module. The following table lists the I2C port on the
phyCARD-Connector:
Pin #
X1A17
X1B17
Signal
X_I2C_SCL
X_I2C_SDA
Table 16:
I2C Interface Signal Location
© PHYTEC Messtechnik GmbH 2014
I/O
O
I/O
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SL
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Description
I2C Clock Output
I2C Data
35
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
9.6
SPI Interface
The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that
provides a simple and efficient method for data exchange among devices. 6 pins of the XArc bus are designated to the SPI interface (refer to Table 2). In addition to the four
standard signals a second chip select and the SPI ready signal are provided at the X-Arc
bus. The later signal allows to also use SPI devices with "5-wire protocol". The Enhanced
Configurable SPI (ECSPI) of the i.MX 6 has five separate modules (ECSPI1 to ECSPI5). The
interface signals of the third module (ECSPI3) are made available on the phyCARDConnector. This module is Master/Slave configurable.
Signal
X_SPI0_CS0
X_SPI0_CS1
X_SPI0_RDY
I/O
O
O
O
X1A37
X1B36
X_SPI0_CLK
X_SPI0_MOSI
O VDD_3V3_LOGIC
I/O VDD_3V3_LOGIC
X1B37
X_SPI0_MISO
I/O VDD_3V3_LOGIC
el
im
Table 17:
SL
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
Description
ECSPI3 Chip select 0
ECSPI3 Chip select 1
SPI Ready signal implemented by
use of GPIO1_9
ECSPI3 clock
ECSPI3 Master data out; slave
data in
ECSPI3 Master data in; slave data
out
in
a
Pin #
X1A35
X1B35
X1A36
ry
The i.MX 6 does not provide the SPI ready signal. Because of that an additional GPIO
(GPIO1_9) is attached to pin X1A36 instead. The following table lists the SPI signals on the
phyCARD-Connector:
SPI Interface Signal Location
Pr
9.7 I2S Audio Interface (SSI)
The Synchronous Serial Interface (SSI) of the phyCARD-i.MX 6 is a full-duplex, serial
interface that allows to communicate with a variety of serial devices, such as standard
codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular
industry audio codecs that implement the inter-IC sound bus standard (I2S) and Intel
AC’97 standard. The i.MX 6 provides three instances of the SSI module. On the
phyCARD-i.MX 6 SSI5 is brought out to the phyCARD -Connector.
With reference to the X-Arc bus specification, the main purpose of this interface is to
connect to an external codec, such as I2S. Four signals extend from the i.MX 6 SSI module
to the phyCARD-Connector (I2S_BIT_CLK, I2S_SYNC, I2S_SDATA_OUT, I2S_SDATA_IN). X_
AC97_INT and X_I2S_nRESET are two additional pins assisting the functionality of this
interface. X_ AC97_INT is used as input and output. As output it signals which codec is
supported by the phyCARD. Use of this pin as an input enables to attach an external
interrupt to GPIO (GPIO5_14). X_I2S_nRESET is connected to GPIO7_12 of the i.MX 6
allowing to perform a software reset for the device attached to the interface.
36
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Serial Interfaces
Please also read the phyCARD Design-In Guide for more information about how to use the
I2S interface.
Signal
X_AC97_INT
X1A43
X1A44
X1B42
X1B43
X1B44
X_I2S_SDATA_OUT
X_I2S_SDATA_IN
X_I2S_BIT_CLK
X_I2S_SYNC
X_I2S_nRESET
SSI Interface Signal Location
Pr
el
im
in
a
Table 18:
I/O SL
Description
I/O VDD_3V3_LOGIC I2S Interrupt Input (connected
to GPIO5_14)
O VDD_3V3_LOGIC I2S Transmit Output
I
VDD_3V3_LOGIC I2S Receive Input
I
VDD_3V3_LOGIC I2S Transmit Clock
O VDD_3V3_LOGIC I2S Transmit Frame Sync
O VDD_3V3_LOGIC Reset for external I2S device
(derived from GPIO7_12)
ry
Pin #
X1A42
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37
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
10 General Purpose I/Os
The X-Arc bus provides 3 GPIO / IRQ signals. Table 19 shows the location of the GPIO / IRQ
pins on the phyCARD-Connector, as well as the corresponding ports of the i.MX 6.
Signal
X1A46 X_GPIO0/IRQ0
I/O SL
I/O VDD_3V3_LOGIC
X1A47 X_GPIO2/IRQ/PWM I/O VDD_3V3_LOGIC
X1B47 X_GPIO1/IRQ1
Location of GPIO and IRQ pins
in
a
Table 19:
I/O VDD_3V3_LOGIC
Description
General purpose input/output 0
(GPIO2_24 of i.MX 6)
General purpose input/output 2
(GPIO4_29 of i.MX 6)
General purpose input/output 1
(GPIO1_6 of i.MX 6)
ry
Pin #
el
im
As can be seen in the table above the voltage level is VDD_3V3_LOGIC, which is 3.3 V. In
other words VDD_3V3_LOGIC is identical with the supply voltage of the phyCARD-i.MX 6.
But in order to follow the power-up and power–down sequencing mandatory for the i.MX 6
VDD_3V3_LOGIC is switched on with a certain delay. Because of that use of
VDD_3V3_LOGIC ensures that external components are only supplied when the supply
voltages of the i.MX 6 are stable. External devices connected to the GPIO pins should be
supplied by VDD_3V3_LOGIC available at X1A5 and X1B5 (refer to section 4.4).
Alternatively an open drain circuit with a pull-up resistor attached to VDD_3V3_LOGIC can
be connected to the GPIOs of the phyCARD-i.MX 6.
Pr
Caution!
The current draw for VDD_3V3_LOGIC must not exceed 500 mA. If devices with a higher
power consumption are to be connected to the GPIOs of the phyCARD-i.MX 6 they should be
switched on and off by use of VDD_3V3_LOGIC. This way the power-up and power–down
sequencing will be considered even if the devices are not supplied directly by
VDD_3V3_LOGIC.
Caution!
The i.MX 6's requires strict separation of the supply voltages generated on the
phyCARD-i.MX 6 and the supply voltages used on the carrier board/custom application. To
avoid voltages which are sourced from the supply voltage of peripheral devices attached to
the GPIOs bus switches powered by VDD_3V3_LOGIC on the phyCARD side should be used.
Alternatively, the bus switches' output enable to the SOM can be controlled by
VDD_3V3_LOGIC (please refer to section 4.4 for more information).
Please refer to the chapter "GPIOs" in the phyCARD Design-In Guide for more information
about how to integrate the GPIO pins in your design.
38
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Debug Interfaces
11 User LEDs
Pr
el
im
in
a
ry
The phyFLEX-i.MX 6 provides two user LEDs on board, a red (D2) and a green (D1). D2 can
be controlled by setting GPIO3_20 (pad EIM_D20) and D1 can by controlled by setting
GPIO1_7 (pad GPIO_7) to the desired output level. A high-level turns the LED on, a lowlevel turns it off.
© PHYTEC Messtechnik GmbH 2014
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39
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
12 Debug Interface (X3))
The phyCARD-i.MX 6 is equipped with a JTAG interface for downloading program code into
the external flash, internal controller RAM or for debugging programs currently executing.
The JTAG interface extends to a 2.54 mm pitch contact pad row at X3 which allows for
attaching a 2x10 pin, 2.54 mm pitch pin header on the edge of the module PCB. Figure 9
and Figure 10 show the position of the debug interface (JTAG connector X3, DEBUG
INTERFACE X2) on the phyCARD-i.MX 6 module. Software debugging via DEBUG INTERFACE
connector X2 requires special tools (hardware/software). For further information please
see the i.MX 6 Reference Manual.
8
6
2
6
4 2
X2
UART2
Pr
el
im
in
a
JTAG
4
ry
X3
20 18 16 14 12 10
Figure 9:
40
JTAG Interface at X2 and X3 (top view)
© PHYTEC Messtechnik GmbH 2014
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Debug Interfaces
1
3 5
X2
1
3
5
7
9 11
X3
13 15 17 19
JTAG
el
im
in
a
ry
UART2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
25
1
1
Pr
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99100
Figure 10:
JTAG Interface at X2 and X3 (bottom view)
Pin 1 of the JTAG connector X3 is on the connector side of the module. Pin 2 of the JTAG
connector is on the controller side of the module.
Note:
The connectors X2 and X3 only populates phyCARD-i.MX 6 modules with a special order
code. DEBUG/JTAG connectors X2 and X3 are not populated on the standard phyCARD
module. We recommend integration of a standard (2.54 mm pitch) pin header connector in
the user target circuitry to allow easy program updates via the JTAG interface.
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41
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
See the following table for details on the JTAG signal pin assignment (X3).
Table 20:
4
6
8
10
12
14
16
18
20
3
5
7
9
11
13
15
17
19
Signal
TREF
(VDD_3V3_LOGIC via 0 Ω)
X_JTAG_TRSTB (10 kΩ pull-up)
X_JTAG_TDI (10 kΩ pull-up)
X_JTAG_TMS (10 kΩ pull-up)
X_JTAG_TCK
Connected to X_JTAG_TCK via 0 Ω
X_JTAG_TDO
X_nRESET_IN
NC
NC
ry
VSUPPLY
(VDD_3V3_LOGIC)
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Row*
A
B
2
1
in
a
Signal
JTAG Connector X3 Signal Assignment
el
im
*Note: Row A is on the controller side of the module and row B is on the connector side of
the module
The following table shows details on the debug interface pin assignment (X2).
Pin Row*
A
B
2
1
4
3
6
5
Pr
Signal
VDD_3V3
VDD_3V3_LOGIC
GND
Table 21:
42
Signal
GND
UART2_TX
UART2_RX
Debug interface Connector X2 Signal Assignment
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LVDS Camera Interface
13 LVDS Display Interface
The LVDS-Signals from channel serializer #0 of the i.MX 6's on-chip LVDS Display Bridge
(LDB) are brought out at the X-Arc Connector X1. Thus an LVDS-Display can connect
directly to the phyCARD-i.MX 6. The location of the applicable interface signals
(X_LVDS_TX0-3+, X_LVDS_TX0-3-, X_LVDS_TXCLK+ and X_LVDS_TXCLK-) can be found in
the table below.
Table 22:
SL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
Description
LVDS0 data0+
LVDS0 data0LVDS0 data2+
LVDS0 data2LVDS0 clock+
LVDS0 clockLVDS0 data1+
LVDS0 data1LVDS0 data3+
LVDS0 data3-
ry
I/O
O
O
O
O
O
O
O
O
O
O
in
a
Signal
X_LVDS_TX0+
X_LVDS_TX0X_LVDS_TX2+
X_LVDS_TX2X_LVDS_TXCLK+
X_LVDS_TXCLKX_LVDS_TX1+
X_LVDS_TX1X_LVDS_TX3+
X_LVDS_TX3-
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Pin #
X1A9
X1A10
X1A11
X1A12
X1A14
X1A15
X1B9
X1B10
X1B11
X1B12
Display Interface Signal Location
13.1 LVDS Display Interface pixel mapping
Pr
The phyCARD specification defines the pixel mapping of the LVDS display interface. The
pixel mapping equates to the OpenLDI respectively Intel 24.0 standard. Thus you can
connect 18-bit as well as 24-bit LVDS displays to the phyCARD. Table 23 and Table 24 show
the recommended pixel mapping of the LVDS display. For further information please see
the phyCARD Design Guide.
Note:
Make sure that the LVDS display you want to use provides the same pin mapping as the
phyCARD. Normally this is only important for 24-bit LVDS displays because due to the
organization of the LVDS pixel mapping all common 18-bit LVDS displays should work.
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
18-bit LVDS Display
1
2
CLK
1
1
A0
G0
R5
A1
B1
B0
A2
DE
VSYNC
A3
0
0
5
0
R2
G3
B4
0
6
1
R1
G2
B3
0
7
1
R0
G1
B2
0
6
1
R3
G4
B5
R1
7
1
R2
G3
B4
R0
3
0
R6
G7
HSYNC
B0
4
0
R5
G6
B7
G1
5
0
R4
G5
B6
G0
ry
Pixel Mapping of 18-bit LVDS Display Interface
24-bit LVDS Display
1
2
CLK
1
1
A0
G2
R7
A1
B3
B2
A2
DE
VSYNC
A3
0
B1
Pixel Mapping of 24-bit LVDS Display Interface
Pr
el
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Table 24:
4
0
R3
G4
B5
0
in
a
Table 23:
3
0
R4
G5
HSYNC
0
44
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LVDS Camera Interface
14 LVDS Camera Interface
The phyCARD-i.MX 6 uses one 10-Bit LVDS Random Lock Deserializer (U27) to receive LVDSSignals from a LVDS Camera Interface (1-channel). The LVDS Deserializer converts the LVDS
Signals to a 10-bit wide parallel data bus and separate clock which can be used as inputs
for the i.MX 6 Camera Sensor Interfaces (U27 is connected to CSI0). The 10-bit wide data
bus consists of 8 color information bits and 2 sync bits (HSYNC/VSYNC).
The following table shows the location of the applicable interface signals on the phyCARD Connector.
X1B16 X_LVDS_CAM_nLOCK
Table 25:
ST
O
LVDS_I
LVDS_I
Voltage Domain
VDD_3V3_LOGIC
VDD_3V3_LOGIC
VDD_3V3_LOGIC
O
VDD_3V3_LOGIC
Description
Camera master clock
Camera data+
Camera0 dataLOCK output of the
Deserializer at U27
ry
Signal
X_LVDS_CAM_MCLK
X_LVDS_CAM_RX+
X_LVDS_CAM_RX-
in
a
Pin #
X1A16
X1B14
X1B15
Camera Interface Signal Location at X1
el
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To assists the implementation of a power management the Deserializer’s REN input is
connected to the CSI0_DATA_EN signal (P3) of the i.MX 6. Furthermore the nPWRDN signal
of the Deserializer is connected to CAM_LVDS_PRWDN/GPIO5_27 (N5) of the i.MX 6.
Thereby the LVDS Deserializer can be turned off by software.
14.1 Signal Configuration (J31)
Pr
J31 selects rising, or falling edge strobe for the LVDS Deserializer at U27 used for the
camera connectivity of the phyCARD-i.MX 6 CSI0 port.
Position Description
Type
0R
2+3
rising edge strobe used for the LVDS camera
(0402)
signals
1+2
falling edge strobe used for the LVDS camera
signals
Table 26:
LVDS Signal Configuration J31
© PHYTEC Messtechnik GmbH 2014
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45
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
15 Technical Specifications
The physical dimensions of the phyCARD-i.MX 6 are represented in Figure 11. The module's
profile is max. 11.4 mm thick, with a maximum component height of 5.0 mm on the bottom
(connector) side of the PCB and approximately 3.0 mm on the top (microcontroller) side.
The board itself is approximately 1.4 mm thick.
60mm
4mm
52mm
ry
4mm
phyCARD-XL3
Pr
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60mm 52mm
in
a
D2.7mm
Figure 11:
Physical Dimensions
Note:
To facilitate the integration of the phyCARD-i.MX 6 into your design, the footprint of the
phyCARD-i.MX 6 is available for download (see section 16.1).
46
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Technical Specifications
Additional specifications:
60 mm x 60 mm
approximately 16 g with all
optional components mounted on
the circuit board
-40 °C to +125 °C
0 °C to +70 °C (commercial)
-40 °C to +80 °C (industrial)
95% r.F. not condensed
VCC 3.3 V
Storage temperature:
Operating temperature:
Humidity:
Operating voltage:
Power consumption:
Supply voltage:
Condition hardware:
Max. 2.2 W
ry
Dimensions:
Weight:
el
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in
a
VCC = 3.3 V, VSTBY = 0 V,
256 MB LP-DDR-RAM,
512 MB
NAND Flash, Ethernet, 720 MHz
Condition software / commands CPU frequency at 20 °C
executed
Linux; seriell and Ethernet
communication + dd + fbtest
Pr
These specifications describe the standard configuration of the phyCARD-i.MX 6 as of the
printing of this manual.
© PHYTEC Messtechnik GmbH 2014
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47
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Connectors on the phyCARD:
Manufacturer
Number of pins per contact rows
Molex part number (lead free)
Molex
100 (2 rows of 50 pins each)
52885-1074 (receptacle)
Matting connectors on the phyBASE:
Component height 6 mm
Molex
100 (2 rows of 50 pins each)
55091-1075/1074 (header)
VB090
ry
Manufacturer
Number of pins per contact row
Molex part number (lead free)
PHYTEC part number (lead free)
Manufacturer
Number of pins per contact row
Molex part number (lead free)
in
a
Component height 10 mm
Molex
100 (2 rows of 50 pins each)
53553-1079 (header)
el
im
Two different heights are offered for the receptacle sockets that correspond to the
connectors populating the underside of the phyCARD—i.MX 6. The given connector height
indicates the distance between the two connected PCBs when the module is mounted on
the corresponding carrier board. In order to get the exact spacing, the maximum
component height (3 mm) on the bottom side of the phyCARD must be subtracted.
Pr
Please refer to the corresponding data sheets and mechanical specifications provided by
Molex (www.molex.com).
48
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in
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Technical Specifications
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
16 Hints for Integrating and Handling the phyCARD-i.MX 6
16.1 Integrating the phyCARD-i.MX 6
Besides this hardware manual much information is available to facilitate the integration of
the phyCARD-i.MX 6 into customer applications.
3.
4.
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el
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5.
ry
2.
the design of the standard phyCARD Carrier Board can be used as a reference for any
customer application
many
answers
to
common
questions
can
be
found
at
http://www.phytec.de/de/support/faq/faq-phyCARD-i.MX 6.html,
or
http://www.phytec.eu/europe/support/faq/faq-phyCARD-i.MX 6.html.
a Design-In Guide can be downloaded from the same web side. It provides
recommendations as to development of customized carrier board target hardware in
which the phyCARD-i.MX 6 (and other phyCARDs) can be deployed.
the link "Carrier Board" within the category Dimensional Drawing leads to the layout
data as shown in Figure 12. It is available in different file formats.
different support packages are available to support you in all stages of your
embedded development. Please visit http://www.phytec.de/de/support/supportpakete.html, or http://www.phytec.eu/europe/support/support-packages.html, or
contact our sales team for more details.
in
a
1.
50
© PHYTEC Messtechnik GmbH 2014
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100mm
80mm
60mm
52mm
D0.9mm
D0.7mm
D2.7mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
4mm
2mm
2.1mm
D
101
102
103
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
104
9.19mm
9.2mm
51
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© PHYTEC Messtechnik GmbH 2014
10.44mm
10.45mm
ry
4mm
60mm
52mm
20mm
105
106
in
a
20mm
107
108
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109
110
Footprint of the phyCARD-i.MX 6
Figure 12:
31.11mm
7.23mm
Ref Des
7.24mm
0.635mm
Pr
Hints for Handling
alle Maße mit Toleranz von +/- 0,1mm
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
16.2 Handling the phyCARD-i.MX 6
•
Modifications on the phyCARD Module
Removal of various components, such as the microcontroller and the standard quartz, is
not advisable given the compact nature of the module. Should this nonetheless be
necessary, please ensure that the board as well as surrounding components and sockets
remain undamaged while de-soldering. Overheating the board can cause the solder pads to
loosen, rendering the module inoperable. Carefully heat neighboring connections in pairs.
After a few alternations, components can be removed with the solder-iron tip.
Alternatively, a hot air gun can be used to heat and loosen the bonds.
Integrating the phyCARD into a Target Application
in
a
•
ry
Caution!
If any modifications to the module are performed, regardless of their nature, the
manufacturer guarantee is voided.
el
im
Successful integration in user target circuitry greatly depends on the adherence to the
layout design rules for the GND connections of the phyCARD module. As a general design
rule we recommend connecting all GND pins neighboring signals which are being used in
the application circuitry. For maximum EMI performance all GND pins should be connected
to a solid ground plane.
Pr
Note!
Please refer to the phyCARD Design-In Guide (LAN-051) for additional information, layout
recommendations and example circuitry.
52
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in
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Hints for Handling
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17 The phyCARD-i.MX 6 on the phyBASE
PHYTEC phyBASE Boards are fully equipped with all mechanical and electrical components
necessary for the speedy and secure start-up and subsequent communication to and
programming of applicable PHYTEC System on Module (SOM) modules. phyBASE Boards are
designed for evaluation, testing and prototyping of PHYTEC System on Module in
laboratory environments prior to their use in customer designed applications.
ry
The phyCARD-i.MX 6 Carrier Board provides a flexible development platform enabling quick
and easy start-up and subsequent programming of the phyCARD-i.MX 6 System on Module.
The carrier board design allows easy connection of additional extension boards featuring
various functions that support fast and convenient prototyping and software evaluation.
Pr
el
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in
a
The phyBASE supports the following features for the phyCARD-i.MX 6 modules:
• Power supply circuits to supply the modules and the peripheral devices
• Support of different power modes of appropriate phyCARD
• Full featured 4 line RS-232 transceiver supporting data rates of up to 120 kbps,
hardware handshake and RS-232 connector
• Seven USB-Host interfaces
• USB-OTG interface
• 10/100 Mbps Ethernet interface
• Complete audio and touch screen interface
• LVDS display interface with separate connectors for data lines and display / backlight
supply voltage
• Circuitry to allow dimming of a backlight
• Secure Digital Card / Multi Media Card Interface
• Two extension connectors for PHYTEC Extension Boards (PEBs) or customer prototyping
purposes featuring one USB, one I2C and one SPI interface, as well as one GPIO/IRQ at
either connector
• DIP-Switch to configure various interface options
• Jumper to configure the boot options for the phyCARD-i.MX 6 module mounted
• RTC with battery supply/backup
54
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The phyCARD®-i.MX 6 on the phyBASE
17.1 Concept of the phyBASE Board
The phyCARD Carrier Board provides a flexible development platform enabling quick and
easy start-up and subsequent programming of the phyCARD System on Module. The carrier
board design allows easy connection of additional extension boards featuring various
functions that support fast and convenient prototyping and software evaluation. The
carrier board is compatible with all phyCARDs.
This modular development platform concept includes the following components:
the phyCARD-i.MX 6 module populated with the i.MX 6 processor and all applicable
SOM circuitry such as DDR SDRAM, Flash, PHYs, and transceivers to name a few.
•
the phyBASE which offers all essential components and connectors for start-up
including: a power socket which enables connection to an external power adapter,
interface connectors such as DB-9, USB and Ethernet allowing for use of the SOM's
interfaces with standard cable.
in
a
ry
•
The following sections contain specific information relevant to the operation of the
phyCARD-i.MX 6 mounted on the phyCARD Carrier Board.
Pr
el
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Note:
Only features of the phyBASE which are supported by the phyCARD-i.MX 6 are described.
Jumper settings and configurations which are not suitable for the phyCARD-i.MX 6 are not
described in the following chapters.
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.2 Overview of the phyBASE Peripherals
X6
U23
U8
U9
D39
phyBASE is depicted in Figure 13. It is equipped with the components and peripherals
listed in Table 27, Table 28, Table 29 and Table 30. For a more detailed description of each
peripheral refer to the appropriate chapter listed in the applicable table. Figure 13
highlights the location of each peripheral for easy identification.
D38
äThe
ry
X28
JP2 JP1
PWR
LVDS
X32
U43
D48
U30
U21
D41
U12
U25
U29
U3
X8
phyCARD XL cooling area
U32
56
U17
BAT1
S3
U7
MMC / SD card
X26
U5
S1
Reset
S2
ON / OFF
U28
U20
J3
U16
Expansion 2
U1
X9
J1 CAM
AUDIO
X3 X2 X1
MIC
OUT
IN
Figure 13:
D45
U13
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
X5
U31
U2
X34
D46
U10
U22
U4
D30
U11
Pr
RS232
U6
P1
D50
X33
USB Host
U27
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U14
Expansion 1
J2
D49
JP3
USB Host
9.4mm
U19
U15
U33
in
a
1
50
D37
D40
B
A
X27
U26
Ethernet
USB OTG
X29
X7
Front
phyCARD Connector
X10
U24
phyBASE Overview of Connectors, LEDs and Buttons
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
17.2.1 Connectors and Pin Header
Table 27 lists all available connectors on the phyBASE. Figure 13 highlights the location of
each connector for easy identification.
X26
X27
X28
X29
X32
X33
P1
Table 27:
See
Section
17.3.8
17.3.8
17.3.8
17.3.7.1
17.3.5
17.3.12
17.3.12
17.3.4
ry
CPLD JTAG connector
Pr
X34
Stereo Microphone input connector
Stereo Line out connector
Stereo Line In connector
Display data connector
Dual USB Host connector
Extension connector 0
Extension connector 1
Ethernet connector, RJ45 with speed and
link led
Secure Digital/MultiMedia Card slot
phyCARD-Connector for mounting the
phyCARD-i.MX 6
Wall adapter input power jack to supply
main board power (+9 - +36 V)
USB On-The-Go connector
Display / Backlight supply voltage
connector
USB Host connector
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X10
Description
in
a
Reference
Designator
X1
X2
X3
X6
X7
X8A
X9A
Serial Interface, DB-9F
17.3.13
17.3.1
17.3.2
17.3.6
17.3.7.2
17.3.5
for
internal
use only
17.3.3
phyBASE Connectors and Pin Headers
Note:
Ensure that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller User's
Manual/Data Sheets. As damage from improper connections varies according to use and
application, it is the user‘s responsibility to take appropriate safety measures to ensure
that the module connections are protected from overloading through connected
peripherals.
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.2.2 Switches
The phyBASE is populated with two switches which are essential for the operation of the
phyCARD-i.MX 6 module on the carrier board. Figure 13 shows the location of the switches
and push buttons.
S2
Table 28:
Description
System Reset Button – system reset signal
generation
Power Button – powering on and off main
supply voltages of the carrier board
phyBASE Push Buttons Descriptions
17.3.15
17.3.2
ry
Button
S1
See
Section
Issues a system reset signal. Pressing this button will toggle the X_nRESET_IN pin
(X2A7) of the phyCARD SOM low, causing the module to reset. Additionally, a
peripheral reset is generated by the PLD on the CB to reset peripherals such as the
USB Hub, etc.
S2
Issues a power on/off event. Pressing this button less than 2 seconds will toggle the
nPWR_KEY pin of the phyBASE CPLD LOW, causing the CPLD to turn on the supply
voltages. Pressing this button for more than 2 seconds causes the CPLD to turn off
the supply voltages.
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S1
Additionally a DIP-Switch is available at S3. The following table gives an overview of the
functions of the DIP-switch.
Pr
Note:
The following table describes only settings suitable for the phyCARD-i.MX 6. Other settings
must not be used with the phyCARD-i.MX 6.
58
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The phyCARD®-i.MX 6 on the phyBASE
S3_1/
S3_2
0/0
1/0
S3_3/
S3_4
CPLD Address 0x40 (7 MSB)
Switch 5 of DIP-Switch S3 selects the interface used for the
communication between CPLD and phyCARD.
0
I2C communication selected
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Switch 6 of DIP-Switch S3 turns the SPI Multiplexer on, or off.
0
SPI multiplexer off
Switches 7 and 8 of DIP-Switch S3 map the two slave select signals of
the SPI interface and the two GPIO_IRQ signals (GIO0_IRQ, GPIO1_IRQ)
to two of the three available connectors.
0/0
0/1
SS0/GPIO0 -> extension 0 (X8A),
SS1/GPIO1 -> extension 1 (X9A)
SS0/GPIO0 -> extension 0 (X8A),
SS1/GPIO1 -> display data connector (X6)
SS0/GPIO0 -> extension 1 (X9A),
SS1/GPIO1 -> display data connector (X6)
Pr
S3_7/
S3_8
Auto Detection: based on the low level of the HDA_SEL/AC_INT signal 17.3.7.3
generated on the phyCARD-i.MX 6 the TI audio CODEC (U17) is 17.3.8
selected to process the I2S compliant audio signals, while the
dedicated touch contrl. at U28 handles the signals from a touch
screen.
Regardless of the signal HDA_SEL/AC_INT the TI audio CODEC (U17) is
selected to process the I2S compliant audio signals, while the dedicated
touch contrl. at U28 handles the signals from a touch screen.
Switches 3 and 4 of DIP-Switch S3 configure the I2C address for the
communication between CPLD and phyCARD.
0/0
S3_5
S3_6
See
Description
Section
Depending on the audio standard supported by the phyCARD the audio
and touch panel signals are either processed by the Wolfson
audio/touch contrl. at U1 (AC'97) or the TI Audio CODEC at U17 (I2S)
and a dedicated touch contrl. at U28.
Switches 1 and 2 of DIP-Switch S3 select which device processes the
audio and touch panel signals.
ry
Setting
in
a
Switch
1/x
Table 29:
1
:
17.3.7.1
17.3.10
17.3.11
17.3.12
phyBASE DIP-Switch S3 Descriptions 1
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2014
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59
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.2.3 LEDs
The phyBASE is populated with numerous LEDs to indicate the status of the various USBHost interfaces, as well as the different supply voltages. Figure 13 shows the location of
the LEDs. Their function is listed in the table below:
See
Section
Color
Description
D16
yellow USB1 amber led
D17
yellow USB2 amber led
D18
yellow USB3 amber led
D19
yellow USB4 amber led
D20
yellow USB5 amber led
D21
yellow USB6 amber led
D22
yellow USB7 amber led
D23
green
USB1 green led
D24
green
USB2 green led
D25
green
USB3 green led
D26
green
USB4 green led
D27
green
D28
green
D29
green
D30
red
D50
red
D49
red
Indicates presence of VBUS at the USB OTG interface
D37
green
5 V supply voltage for peripherals on the phyBASE
D38
green
supply voltage of the phyCARD
D39
green
3.3 V supply voltage for peripherals on the phyBASE
D40
green
3.3 V standby voltage of the phyBASE
D41
green
standby voltage of the phyCARD
D45
yellow SSI interface compliant with the AC'97 standard
USB5 green led
USB6 green led
USB7 green led
Active/Suspend status LED of the USB hub at U4
Pr
Hi-Speed indicator LED for USB hub's upstream port connection
speed
2
D46
green
D48
yellow user LED driven by the LED dimmer at U21
Table 30:
60
17.3.5
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in
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LED
SSI interface compliant with the I S standard
17.3.6
17.3.2
17.3.8
phyBASE LEDs Descriptions
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
17.2.4 Jumpers
The phyCARD Carrier Board comes pre-configured with 2 removable jumpers (JP) and 3
solder jumpers (J). The jumpers allow the user flexibility of configuring a limited number of
features for development constraint purposes. Table 31 ists the jumpers, their default
positions, and their functions in each position. Figure 14 depicts the jumper pad
numbering scheme for reference when altering jumper settings on the development board.
Figure 15 provides a detailed view of the phyBase jumpers and their default settings. In
these diagrams a beveled edge indicates the location of pin 1.
e.g.: JP1
Figure 14:
in
a
ry
Before making connections to peripheral connectors it is advisable to consult the
applicable section in this manual for setting the associated jumpers.
e.g.: J1
e.g.: JP2
Typical Jumper Numbering Scheme
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Table 31 provides a comprehensive list of all carrier board jumpers. The table only provides
a concise summary of jumper descriptions. Only jumpers supporting features of the
phyCARD-i.MX 6 are described. For a detailed description of each jumper see the applicable
chapter listing in the right hand column of the table.
Pr
If manual modification of the solder jumpers is required please ensure that the board as
well as surrounding components and sockets remain undamaged while de-soldering.
Overheating the board can cause the solder pads to loosen, rendering the board
inoperable. Carefully heat neighboring connections in pairs. After a few alternations,
components can be removed with the solder-iron tip. Alternatively, a hot air gun can be
used to heat and loosen the bonds.
© PHYTEC Messtechnik GmbH 2014
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61
Figure 15:
62
BAT1
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
D50
X33
X34
U4
phyCARD XL cooling area
D46
D30
X8
U29
U25
U3
Expansion 1
U14
J2
D41
U12
D49
JP3
J4
USB OTG
X29
U19
D48
U21
U43
U33
U30
ry
in
a
USB Host
U27
USB Host
X7
U15
S3
MMC / SD card
X26
U5
S1
Reset
S2
U17
U6
U11
ON / OFF
J3
U16
U31
U10
U22
RS232
el
im
U2
U28
Expansion 2
X9
D45
X5
Pr
J1 CAM
U13
U20
U1
AUDIO
X3 X2 X1
P1
9.4mm
X10
50
A
D37
D40
X32
B
X27
U26
Ethernet
1
phyCARD Connector
MIC
OUT
IN
PWR
JP2 JP1
X28
X6
LVDS
Front
U23
D39
U9
U8
D38
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
U24
U32
U7
phyBASE Jumper Locations
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
The following conventions were used in the Jumper column of the jumper table (Table 31)
• J = solder jumper
• JP = removable jumper
Jumper
Setting
Description
Jumper JP1 selects the boot device of the phyCARDi.MX 6
JP1
open
1+2
3+4
1+2,
3+4
NAND 1
SD0 external 1
Serial USB OTG (USB0) 1
Bootconfig from eFUSE
See
Section
ry
17.3.14
in
a
other settings must not be used with the phyCARDi.MX 6
Jumper JP2 connects the input voltage to connector X32
as supply voltage for a backlight.
open
VCC12V Backlight disabled
closed
VCC12V Backlight connected to power supply. Only 12V
DC power supplies allowed
17.3.7.2
el
im
JP2
Jumper JP3 forces the USB OTG interface of the
phyCARD-i.MX 6 to function either as host (master), or
device (slave).
open
USB_OTG_ID floating, phyCARD-i.MX 6 in slave mode, 17.3.6
or according to the mode configured by software
Pr
JP3
closed
J2
J3
Table 31:
1
:
USB_OTG_ID connected to GND, phyCARD-i.MX 6 in host
mode
Jumper J2 configures the I2C address of the LED dimmer
at U21
2
17.3.7.2
17.3.9
closed
I C device address of LED dimmer set to 0x60
open
I2C device address of LED dimmer set to 0x61
1+2
2+3
Jumper J3 configures the I2C address of the touch screen
controller at U28
17.3.7.3
17.3.9
I2C device address set to 0x44
I2C device address set to 0x41
phyBASE Jumper Descriptions 1
please see section 6 for more information on the different boot modes
© PHYTEC Messtechnik GmbH 2014
L-800e_0
63
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
See
Section
Setting
Description
Jumper J4 selects the reset source of the audio devices
at U1 and U17. The source of the reset can be either the
peripheral reset signal X_nRES_OUT (X27B7), or the
dedicated audio device reset SSI_RESET 2 (X27B44) from
the phyCARD-i.MX 6.
J4
1+2
Dedicated audio device reset SSI_RESET (X27B44) from 17.3.7.3
the phyCARD-i.MX 6 connected to the reset input of the
audio devices at U1 and U17
Peripheral reset signal X_nRES_OUT (X27B7) from the
phyCARD-i.MX 6 connected to the reset input of the
audio devices at U1 and U17
2+3
phyBASE Jumper Descriptions 3(continued)
in
a
Table 31:
ry
Jumper
Pr
el
im
Note:
Detailed descriptions of the assembled connectors, jumpers and switches can be found in
the following chapters.
1
:
:
3
:
2
64
Default settings are in bold blue text
The reset signal at X27B44 originates from GPIO3_21 of the i.MX 6
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
17.3 Functional Components on the phyBASE Board
This section describes the functional components of the phyCARD Carrier Board supporting
the phyCARD-i.MX 6. Each subsection details a particular connector/interface and
associated jumpers for configuring that interface.
17.3.1 phyCARD-i.MX 6 SOM Connectivity (X27)
Front
9.4mm
P1
X7
USB Host
U13
D49
U27
U12
U22
U14
USB Host
D45
X9
U11
U10
X8
Expansion 2
D41
U32
U16
U17
ON / OFF
D30
Reset
S1
U19
el
im
A
D37
D40
U21
U23
U24
50
U25
D39
B
X34
U30
U33
J2
U43
D48
U7
X32
X6
JP2 JP1
phyCARD-i.MX 6 SOM Connectivity to the Carrier Board
Pr
Figure 16:
J4
U29
phyCARD XL cooling area
MMC / SD card
U15
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U9
X27
U4
BAT1
U5
D50
1
D46
S2
U8
U26
in
a
Expansion 1
U31
J3
D38
Ethernet
U6
U1
PWR
JP3
ry
U2
X33
LVDS
MIC
OUT
IN
RS232
J1 CAM
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
phyCARD Connector
X3 X2 X1
Connector X27 on the carrier board provides the phyCARD System on Module connectivity.
The connector is keyed for proper insertion of the SOM. Figure 16 above shows the location
of connector X27, along with the pin numbering scheme as described in section 2.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
65
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.2 Power Supply (X28)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
X9
U11
U10
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
X27
1
D46
S2
Reset
U4
BAT1
U3
U21
U23
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 17:
D37
D40
50
U25
phyCARD XL cooling area
MMC / SD card
J4
in
a
X34
D39
B
U24
X26
U29
U19
S3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
ON / OFF
D50
D30
phyCARD Connector
U32
U17
J3
S1
U8
U12
U22
U16
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Powering Scheme
Pr
Caution:
Do not use a laboratory adapter to supply power to the carrier board! Power spikes during
power-on could destroy the phyCARD module mounted on the carrier board! Do not change
modules or jumper settings while the carrier board is supplied with power!
Permissible input voltage at X28: +9 V - +36 V DC unregulated.
The required current load capacity of the power supply depends on the specific
configuration of the phyCARD mounted on the carrier board as well as whether an optional
extension board is connected to the carrier board. An adapter with a minimum supply of
2.0 A is recommended.
Polarity:
+9 V - +36 V DC
≥ 2000 mA
-- +
Center Hole
2.5 mm
5.0 mm
GND
Figure 18:
Power Connector corresponding to Wall Adapter Input X28
No jumper configuration is required in order to supply power to the phyCARD module!
66
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
The phyBASE is assembled with a few power LEDs whose functions are described in the
following table:
LEDs
D37
D38
D39
D40
D41
Table 32:
Color
green
green
green
green
green
Description
VCC5V VCC_PHYCARD VCC3V3 VCC3V3STBY VSTBY -
5V supply voltage for peripherals on the phyBASE
supply voltage of the phyCARD
3V3 supply voltage for peripherals on the phyBASE
3V3 standby voltage of the phyBASE
standby voltage of the phyCARD
LEDs Assembled on the Carrier Board
ry
Note:
For powering up the phyCARD the following actions have to be done:
in
a
1. Plug in the power supply connector
» All power LEDs should light up and the phyCARD puts serial output to serial line 0
at P1.
2. For powering down the phyCARD-i.MX 6 button S2 should be pressed for a minimum
time of 2000 ms.
el
im
3. Press button S2 for a maximum time of 1000 ms.
» All power LEDs should light up and the phyCARD puts serial output to serial line 0
at P1.
Three different power states are possible RUN, OFF and SUSPEND.
•
Pr
•
During RUN all supply voltages except VSTBY are on. This means that the phyCARDi.MX 6 is supplied by VCC_PHYCARD.
In OFF state all supply voltages are turned off. Only the standby voltage (VCC3V3STBY)
of the phyBASE itself is still available to supply the PLD, the RTC and to provide a highlevel voltage for the Reset and Power switch.
In SUSPEND mode only the standby voltage VSTBY for the phyCARD-i.MX 6 and the
standby voltage (VCC3V3STBY) of the phyBASE itself are generated. This means the
phyCARD-i.MX 6 is supplied only by VSTBY.
•
The RUN and OFF state can be entered using the power button S2 as described in the gray
box above. It is also possible to enter OFF state with the help of the phyCARD's
X_nPOWER_OFF signal (GPIO1_25 of the i.MX 6). To enter OFF state signal X_nPOWER_OFF
must be active (low) for at least 100 ms.
SUSPEND state can be entered using signal X_nSUSPEND_RAM at pin X27B26 of the
phyCARD Connector (GPIO1_24 of the i.MX 6). X_nSUSPEND_RAM must be active (low) for
at least 100 ms.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
67
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.3 RS-232 Connectivity (P1)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
ON / OFF
X27
1
D46
S2
Reset
U4
BAT1
U29
U19
X34
U21
D37
D40
U23
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 19:
J4
50
U25
phyCARD XL cooling area
MMC / SD card
D39
B
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
in
a
S1
D50
D30
ry
U17
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
RS-232 Interface Connector P1
Pr
Connector P1 is a DB9 sub-connector and provides a connection interface to UART3 of the
i.MX 6. The TTL level signals from the phyCARD-i.MX 6 are converted to RS-232 level
signals. As defined in the specification of the X-Arc bus the serial interface allows for a 5wire connection including the signals RTS and CTS for hardware flow control. Figure 20
below shows the signal mapping of the RS-232 level signals at connector P1.
The RS-232 interface is hard-wired and no jumpers must be configured for proper
operation.
1
6
2
7
3
8
4
9
5
Figure 20:
68
Pin 2:
Pin 7:
Pin 3:
Pin 8:
TxD-RS232
RTS-RS232
RxD-RS232
CTS-RS232
Pin 5:
GND
RS-232 Connector P1 Signal Mapping
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
17.3.4 Ethernet Connectivity (X10)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
ON / OFF
X27
1
D46
S2
Reset
U4
BAT1
U29
D37
D40
U21
U23
U24
50
U25
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 21:
D39
B
X34
phyCARD XL cooling area
MMC / SD card
J4
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
in
a
S1
D50
D30
ry
U17
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Ethernet Interface at Connector X10
Pr
The Ethernet interface of the phyCARD is accessible at an RJ45 connector (X10) on the
carrier board. Due to its characteristics this interface is hard-wired and can not be
configured via jumpers. The LEDs for LINK (green) and SPEED (yellow) indication are
integrated in the connector.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
69
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.5 USB Host Connectivity (X6, X7, X8, X9, X33)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
ON / OFF
X27
1
D46
S2
Reset
U4
BAT1
U29
D37
D40
50
U25
U21
U23
U30
U33
J2
U43
D48
X32
X6
JP2 JP1
el
im
U7
Figure 22:
D39
B
U24
X34
phyCARD XL cooling area
MMC / SD card
J4
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
in
a
S1
D50
D30
ry
U17
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Components supporting the USB Host Interface
Pr
The USB host interface of the phyCARD is accessible via the USB hub controller U4 on the
carrier board. The controller supports control of input USB devices such as keyboard,
mouse or USB key. The USB hub has 7 downstream facing ports. Two ports extend to
standard USB connectors at X7 (dual USB A). Two more ports connect to 9 pin header row
X33. These interfaces are compliant with USB revision 2.0. The remaining ports are
accessible at the display data connector X6 and the extension connectors X8A and X9A.
These three interfaces provide only the data lines D+ and D-. They do not feature a supply
line Vbus.
70
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
LEDs D16 to D29 as well as D30 and D50 signal use of the USB host interfaces. Table 30
shows the assignment of the LEDs to the different USB ports.
Table 33 shows the distribution of the seven downstream facing ports to the different
connectors, whereas Table 34 shows the pinout of USB host connector X33.
USB hub Connector
port #
USB1 /
X33
USB 5
X6
USB3
X8
USB4
X9
USB6
USB7
X7A (bottom)
X7B (top)
D16, D23
D20, D27
Table 34:
D17, D24
D18, D25
in
a
D19, D26
D21, D28
D22, D29
Distribution of the USB Hub's (U4) Ports
Signal name
USB5_VBUS
USB5_DUSB5_D+
USB1_VBUS
USB1_DUSB1_D+
GND
NC
Pr
Pin #
1
3
5
2
4
6
7, 8
9,10
9 pin header row (see table
below)
40 pin FCC (pins 16 (D+)
and 17 (D-))
20 pin header row (pins 19
(D-) and 20 (D+))
20 pin header row (pins 19
(D-) and 20 (D+))
USB A
USB A
el
im
Table 33:
LEDs
ry
USB2
Connector Type
Description
USB5 Power Supply
USB5 Data USB5 Data +
USB1 Power Supply
USB1 Data USB1 Data +
Ground
Not connected
Universal USB Pin Header X33 Signal Description
© PHYTEC Messtechnik GmbH 2014
L-800e_0
71
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.6 USB OTG Connectivity (X29)
Front
9.4mm
P1
MIC
OUT
IN
RS232
AUDIO
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
U17
ON / OFF
X27
1
S2
U4
BAT1
U29
U21
U23
U30
U33
J2
U43
D48
X32
X6
JP2 JP1
el
im
U7
Figure 23:
D37
D40
50
U25
phyCARD XL cooling area
MMC / SD card
J4
U24
X34
D39
B
in
a
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
Reset
S1
D50
D30
phyCARD Connector
U32
U16
U8
U12
U22
D45
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
USB Host
U20
X28
X29
LVDS
X3 X2 X1
X7
USB OTG Interface at Connector X29
Pr
The USB OTG interface of the phyCARD is accessible at connector X29 (USB Mini AB) on the
carrier board. The phyCARD-i.MX 6 supports the On-The-Go feature. The Universal Serial
Bus On-The-Go is a device capable to initiate the session, control the connection and
exchange Host/Peripheral roles between each other. This interface is compliant with USB
revision 2.0.
Jumper JP3 configures the OTG operating mode. By default this jumper is open, which
leaves the USB_OTG_ID pin floating, and thus configuring the OTG interface as slave.
Alternatively this jumper can be closed, connecting the signal X_UID to GND, and
configuring the OTG interface as host. Typically the configuration of a connecting device as
host or slave is done automatically via a USB OTG cable. However, given the limited number
of OTG enabled devices in the embedded market this jumper is provided to either simulate
an OTG cable, or force the OTG interface into host mode when OTG operation is not
required.
LED D49 signals VBUS power supply, which is generated via a power distribution switch
TPS2042 (U29) of the carrier board. The power distribution switch is controlled via the
signals X_USB_HS_nPSW and X_USB_HS_FAULT which extend directly from the phyCARD
connector.
72
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
17.3.7 Display / Touch Connectivity (X6, X32)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
X27
1
D46
S2
Reset
U4
BAT1
D37
D40
U21
U23
U24
50
U25
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 24:
J4
X34
phyCARD XL cooling area
MMC / SD card
D39
B
in
a
U29
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
J3
D50
D30
phyCARD Connector
U32
U17
ON / OFF
S1
U8
U12
U22
U16
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Universal LVDS Interface at Connector X6
Pr
The various performance classes of the phyCARD family allow to attach a large number of
different displays varying in resolution, signal level, type of the backlight, pinout, etc. In
order not to limit the range of displays connectable to the phyCARD, the phyBASE has no
special display connector suitable only for a small number of displays. The new concept
intends the use of an adapter board (e.g. PHYTEC's LCD display adapters LCD-014 and LCD017) to attach a special display, or display family to the phyCARD. A new PHYTEC DisplayInterface (PDI) was defined to connect the adapter board to the phyBASE. It consists of
two universal connectors which provide the connectivity for the display adapter. They allow
easy adaption also to any customer display. One connector (40 pin FCC connector 0.5 mm
pitch) at X6 is intend for connecting all data signals to the display adapter. It combines
various interface signals like LVDS, USB, I2C, etc. required to hook up a display. The second
connector of the PDI (AMP microMatch 8-338069-2) at X32 provides all supply voltages
needed to supply the display and a backlight, and the brightness control.
The following sections contain specific information on each connector.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
73
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.7.1 PDI Data Connector (X6)
PDI data connector X6 provides display data which originates from the parallel display
interface of the i.MX 6 (LIDD). The display signals are converted into LVDS on the
phyCARD-i.MX 6 and are available at the X-Arc bus (phyCARD-Connector). Hence, no
additional signal conversion is necessary on the phyBASE. The LVDS signals extend directly
from the phyCARD-Connector to the PDI Data Connector (X6).
Signal name
SPI1_SCLK
I/O
SL
Description
O
3.3 V
SPI 1 clock
I/O
O/I
3.3 V
3.3 V
SPI 1 master data in; slave data out
SPI 1 master data out; slave data in
4
SPI_MISO
SPI1_MOSI
SP1I_SS_DISP
O
3.3 V
5
DISP_IRQ
I
3.3 V
6
7
8
9
10
11
12
13
VCC3V3
I2C_SCL
I2C_SDA
GND
LS_BRIGHT 1
VCC3V3
nPWR_KEY
nDISP_ENA
O
I/O
I/O
O
O
I
O
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
1
SPI 1 chip select display
Display interrupt input
Power supply display
I2C clock signal
I2C data signal
Ground
PWM brightness output
Logic supply voltage 2
Power on/off button
Display enable signal
Pr
el
im
2
3
in
a
Pin #
ry
Along with the display and touch screen interface signals other useful interfaces such as
USB, I2C, etc. are available at PDI data connector X6. Table 36 lists all miscellaneous
signals and gives detailed explanations. The following table shows the pin-out of the PDI's
display data connectors at X6.
Hardware Introspection Interface
14
PHYWIRE
I/O
3.3 V
15
GND
-
-
for internal use only
Ground
16
USB2_D+
I/O
3.3 V
USB2 data + 3
17
18
19
USB2_DGND
TXOUT0-
I/O
O
3.3 V
3.3 V
USB2 data -2
Ground
LVDS data channel 0 negative output
20
TXOUT0+
O
3.3 V
LVDS data channel 0 positive output
21
22
GND
TXOUT1-
O
3.3 V
Ground
LVDS data channel 1 negative output
Table 35:
1
:
:
3
:
2
74
Display Data Connector X6 Signal Description
This signal is also available at the display power connector X32 (refer to section 17.3.7.2 for more information)
Provided to supply any logic on the display adapter. Max. draw 100 mA
LEDs D17 and D24 signal use of the USB interface
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
Table 35:
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
LVDS data channel 1 positive output
Ground
LVDS data channel 2 negative output
LVDS data channel 2 positive output
Ground
LVDS data channel 3 negative output
LVDS data channel 3 positive output
Ground
LVDS clock channel negative output
LVDS clock channel positive output
Ground
Touch
Touch
Touch
Touch
Touch
Ground
Light sensor analog input
ry
TXOUT1+
GND
TXOUT2TXOUT2+
GND
TXOUT3TXOUT3+
GND
TXCLKOUTTXCLKOUT+
GND
TP_X+
TP_XTP_Y+
TP_YTP_WP
GND
LS_ANA
in
a
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Display Data Connector X6 Signal Description (continued)
Signal
USB2_D
I2C
Description
USB host interface derived from downstream port 2 of the USB hub at U4.
Suitable for optional features e.g. front USB (refer to section 17.3.5 for
more information about the USB host interfaces)
I2C interface for an optional EEPROM, or other I2C devices (additional
information on the I2C interfaces can be found in section 17.3.9)
SPI interface to connect optional SPI slave
Hardware Introspection Interface
for internal use only
Power on/off signal to allow for an ON/OFF switch on a front panel. It
connects to the nPWR_KEY input of the PLD at U25 (parallel to the ON/OFF
switch S2)
Can be used to enable, or disable the display, or to shutdown the backlight.
nDISP_ENA is connected to the corresponding input of the PLD at U25 x
PWM output to control the brightness of a display's backlight (0% = dark,
100% = bright). The signal is derived from the first output LED0 of the LCD
dimmer at U21 1.
Analog light sensor input.
The analog light sensor input at pin 40 extends to an 8-bit A/D converter
which is connected to the I2C bus at address 0x64. To get the maximum
adjustment range the output voltage of an applicable light sensor should
range from 0 V to VRef (VCC_3V3AD).
Pr
SPI1
el
im
The table below shows the auxiliary interfaces at display data connector X6.
PHYWIRE
nPWR_KEY
nDISP_ENA
LS_BRIGHT
LS_ANA
Table 36:
1
:
Auxiliary Interfaces at PDI Data Connector X12
This signal is also available at the display power connector X32 (refer to section 17.3.7.2 for more information)
© PHYTEC Messtechnik GmbH 2014
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75
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
The connection of the SPI interface and the display interrupt input to the X-Arc bus is
shared with the SPI interfaces and the interrupt inputs on the extension connectors X8A
and X9A. Because of that these signals have to be mapped to the display data connector by
configuring switches 7 and 8 of DIP-Switch S3. Table 37 shows the required settings.
The default setting does not connect the SPI interface and the GPIO/Interrupt pin of the
X-Arc bus to the display data connector.
Table 37:
in
a
1/x
Description
SS0/GPIO0_IRQ 1 -> extension 0 (X8A),
SS1/GPIO1_IRQ1 -> extension 1 (X9A)
SS0/GPIO0_IRQ1 -> extension 0 (X8A),
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> extension 1 (X9A),
SS1/GPIO1_IRQ1 -> display data connector (X6)
ry
Settin
Button g
S3_7/ 0/0
S3_8
0/1
SPI and GPIO Connector Selection
17.3.7.2 Display Power Connector (X32)
Pin #
1
2
Signal name
GND
VCC3V3
I/O
O
GND
VCC5V
GND
VCC5V
GND
VCC5V
GND
LS_BRIGHT
VCC12V_BL
VCC12V_BL
O
O
O
O
O
O
SL
3.3 V
Pr
3
4
5
6
7
8
9
10
11
12
el
im
The display power connector X32 (AMP microMatch 8-188275-2) provides all supply
voltages needed to supply the display and a backlight, as well as one PWM signal for
brightness control.
Table 38:
5V
5V
5V
3.3 V
+9 V - +38 V
+9 V - +38 V
Description
Ground
3.3 V
power
supply
display
Ground
5V power supply display
Ground
5 V power supply display
Ground
5 V power supply display
Ground
PWM brightness output
Backlight power supply
Backlight power supply
LVDS Power Connector X32 Signal Description
To make VCC12V_BL available at X32 jumper JP2 must be closed.
1
:
76
GPIO0_IRQ0 ≙ GPIO2_24 (at J23) and GPIO1_IRQ1 ≙ GPIO1_6 (at T3) of the i.MX 6
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
Caution!
The backlight voltage VCC12V_BL corresponds to the input voltage at power jack X28.
There is no protective circuitry for the backlight. Close jumper JP2 only if a 12 V power
supply is connected to X28 as primary supply for the phyBASE.
The PWM signal at pin 10 can be used to control the brightness of a display's backlight. It
is generated by an LED dimmer (U21). The LED dimmer is connected to the I2C bus at
address 1 0x60 (7 MSB).
17.3.7.3 Touch Screen Connectivity
in
a
ry
As many smaller applications need a touch screen as user interface, provisions are made to
connect 4- or 5- wire resistive touch screens to the display data connector X6 (pins 34 - 38,
refer to Table 35). Two touch screen controllers are available on the phyCARD Carrier
Board. The audio/touch codec at U1 allows connecting 4- and 5-wire touch panels,
whereas a separate touch panel controller at U28 is suitable for 4-wire touch panels only.
Because of the dual functionality of the audio / touch controller the choice which
controller is used to handle the signals from the touch screen is pegged to the audio
standard supported by the phyCARD. For phyCARDs supporting the AC'97 standard the
audio/touch controller at U1 processes the touch panel signals. For phyCARDs delivering
I2S compliant audio signals the dedicated touch panel controller at U28 must be selected.
el
im
Switches 1 and 2 of DIP-Switch S3 select which controller is used to process the touch
panel signals. The different configurations are shown in Table 39.
Description
Depending on the audio standard supported by the phyCARD the audio and touch
panel signals are either processed by the Wolfson audio/touch contrl. at U1
(AC'97), or the TI Audio CODEC at U17 (I2S) and a dedicated touch contrl. at U28.
Switches 1 and 2 of DIP-Switch S3 select which device processes the audio and
touch panel signals.
Pr
Button Setting
S3_1/
S3_2
0/0
1/0
Table 39:
Auto Detection: based on the low level of the HDA_SEL/AC_INT signal
generated on the phyCARD-i.MX 6 the dedicated touch contrl. at U28 handles
the signals from a touch screen.
The dedicated touch contrl. at U28 handles the signals from a touch screen,
regardless of the signal HDA_SEL/AC_INT.
Selection of the Touch Screen Controller
As the phyCARD-i.MX 6 features an I2S compliant audio interface the dedicated touch
controller at U28 (STMPE811) must be chosen to process the touch screen signals. It is
connected to the X-Arc bus's I2C interface. The I2C address can be configured with jumper
J3. The default setting is 0x44 (7 MSB)1.
The touch controller provides an interrupt output which extends directly to the interrupt
input pin GPIO2_IRQ (X1A47) at the phyCARD Connector.
1
:
Please refer to Table 31 for information on alternativ I2C address configurations.
© PHYTEC Messtechnik GmbH 2014
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77
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.8
Audio Interface (X1, X2, X3)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
J3
D50
D30
X27
1
S2
Reset
U4
BAT1
U29
U21
U23
U30
U33
J2
U43
D48
X32
X6
JP2 JP1
el
im
U7
Figure 25:
D37
D40
50
U25
phyCARD XL cooling area
MMC / SD card
J4
U24
X34
D39
B
in
a
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
phyCARD Connector
U32
U17
ON / OFF
S1
U8
U12
U22
U16
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Audio Interface at Connectors X1, X2, X3
The audio interface provides a method of exploring the i.MX 6's I2S capabilities.
Pr
Depending on the audio standard supported by the phyCARD the audio interface on the XArc bus connects either to a Wolfson WM9712L audio / touch controller (U1) or a TI
TLV320AIC3007 (U17) Audio CODEC on the carrier board. The audio / touch controller at U1
processes AC'97 compliant signals, while signals according to the I2S standard are handled
by the Audio CODEC at U17.
Switches 1 and 2 of DIP-Switch S3 select which codec is used to process the audio signals.
Table 40 shows the different options.
78
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
Button Setting
S3_1/
S3_2
0/0
1/0
Table 40:
Description
Depending on the audio standard supported by the phyCARD the audio and touch
panel signals are either processed by the Wolfson audio/touch contrl. at U1
(AC'97) or the TI Audio CODEC at U17 (I2S) and a dedicated touch contrl. at U28.
Switches 1 and 2 of DIP-Switch S3 select which device processes the audio and
touch panel signals.
Auto Detection: based on the low level of the HDA_SEL/AC_INT signal
generated on the phyCARD-i.MX 6 the TI audio CODEC (U17) is selected to
process the I2S compliant audio signals.
The TI audio CODEC (U17) is selected to process the I2S compliant audio signals,
regardless of the signal HDA_SEL/AC_INT.
Selection of the Audio Codec
ry
As the phyCARD-i.MX 6 features an I2S compliant audio interface the Audio CODEC at U17
must be chosen to process the audio signals.
in
a
LEDs D45 (AC'97) and D46 (I2S) indicate which audio interface is active. For the phyCARDi.MX 6 LED D46 should be on.
el
im
To reset the audio ICs at U1 and U17 two different reset sources can be selected with
jumper J4. The source of the reset can be either the peripheral reset signal X_nRES_OUT
(X27B7), or the dedicated audio device reset SSI_RESET (X27B44) from the
phyCARD-i.MX 6. The default setting of jumper J4 selects the peripheral reset signal
X_nRES_OUT (X27B7) from the phyCARD-i.MX 6 1.
Audio devices can be connected to 3.5 mm audio jacks at X1, X2, and X3.
Pr
Audio outputs:
X2 – Line output - Line_OUTL/Line_OUTR
Audio Inputs:
X1 - Microphone Inputs - MIC1/MIC2
X3 - Line Input - Line_INL/Line_INR
Please refer to the audio codec’s reference manual for additional information regarding
the special interface specification.
1
:
Please refer to Table for information on alternative settings.
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.9 I2C Connectivity
The I2C interface 1 of the X-Arc bus is available at different connectors on the phyBASE. The
following table provides a list of the connectors and pins with I2C connectivity.
Connector
Camera interface X5
Display data connector X6
Extension connector 1 X8A
Extension connector 2 X9A
I2C Connectivity
ry
Table 41:
Location
pin 4 (I2C_SDA); pin 5 (I2C_SCL)
pin 8 (I2C_SDA); pin 7 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
pin 7 (I2C_SDA); pin 8 (I2C_SCL)
Jumper
J2
J3
0x40
S3_3, S3_4
I2C Addresses in Use
Pr
Table 42:
Address used (7 MSB)
0x60
0x51
0x64
0x44
el
im
Device
LED dimmer (U21)
RTC (U3)
A/D converter (U22)
Touch screen controller
(U28)
CPLD (U25)
in
a
To avoid any conflicts when connecting external I2C devices to the phyBASE the addresses
of the on-board I2C devices must be considered. Some of the addresses can be configured
by jumper. Table 42 lists the addresses already in use. The table shows only the default
address. Please refer to section 17.2.4 for alternative address settings.
1
:
80
The interface of the i.MX 6's third I2C module (I2C3) is used for I2C connectivity on the carrier board (refer also to
section 9.5).
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Pr
el
im
in
a
ry
The phyCARD®-i.MX 6 on the phyBASE
© PHYTEC Messtechnik GmbH 2014
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81
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.10 SPI Connectivity
The SPI interface of the X-Arc bus is available at the extension connectors X8A and X9A as
well as at the display data connector X6 (refer to sections 17.3.7.1 and 17.3.12 to see the
pinout). Due to the X-Arc bus specification only two slave select signals are available.
Because of that the CPLD maps the SPI interface to two of the connectors depending on the
configuration of switches 7 and 8 of DIP-Switch S3. The table below shows the possible
configurations.
Table 43:
SPI Connector Selection
17.3.11 User programmable GPIOs
in
a
ry
Button Setting Description
S3_7/ 0/0
SS0/GPIO0_IRQ 1 -> extension 0 (X8A),
SS1/GPIO1_IRQ1 -> extension 1 (X9A)
S3_8
SS0/GPIO0_IRQ1 -> extension 0 (X8A),
0/1
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> extension 1 (X9A),
1/x
SS1/GPIO1_IRQ1 -> display data connector (X6)
Pr
el
im
Two (GPIO0_IRQ and GPIO1_IRQ) of the three GPIO / Interrupt signals available at the XArc bus are freely available. They are mapped to the extension connectors X8A and X9A
(pin 16), or to the display data connector X6 (pin 5) depending in the configuration at DIPSwitch S3 (see Table 43). The third GPIO / Interrupt signal (GPIO2_IRQ 2) is used to connect
the interrupt output of the touch screen controller at U28 to the phyCARD-i.MX 6.
1
:
2
:
82
GPIO0_IRQ0 ≙ GPIO2_24 (at J23) and GPIO1_IRQ1 ≙ GPIO1_6 (at T3) of the i.MX 6 (refer to section 10))
GPIO2_IRQ ≙ GPIO4_29(at R22) of the i.MX 6 (refer to section 10))
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
17.3.12 Extension connectors (X8A, X9A)
Front
9.4mm
P1
X7
USB Host
U2
X33
U13
D49
U27
U14
USB Host
D45
U10
X9
Expansion 1
U11
Expansion 2
X8
U26
U31
D41
U9
U32
U17
J3
ON / OFF
D50
D30
X27
1
S2
U4
BAT1
U29
in
a
D37
D40
50
U25
U21
U23
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 26:
D39
B
U24
X34
phyCARD XL cooling area
MMC / SD card
J4
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
Reset
S1
U8
U12
U22
U16
D38
Ethernet
U6
U1
PWR
JP3
LVDS
MIC
OUT
IN
RS232
J1 CAM
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
phyCARD Connector
X3 X2 X1
Extension Connector X8A, X9A
The extension connectors X8A and X9A provide an easy way to add other functions and
features to the phyBASE 1. Standard interfaces such as USB, SPI and I2C as well as different
supply voltages and one GPIO are available at the pin header rows. The pinout of the
extension connectors is shown in Table 45.
Pr
As can be seen in Figure 26 the location of the connectors allows to expand the
functionality without expanding the physical dimensions. Mounting wholes can be used to
screw the additional PCBs to the phyBASE.
The extension connectors share the SPI interface and the GPIOs of the X-Arc bus with the
display data connector X6. Therefore switches 7 and 8 of DIP-Switch S3 must be configured
to map the signals to the desired connector.
The following table shows the possible configurations.
1
:
PHYTEC offers a variety of extension boards (PEBs) to add new features, such as CAN, additional GPIOs or Ethernet, etc.
Please visit our web side or contact our sales team.
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83
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Button Setting Description
S3_7/ 0/0
SS0/GPIO0_IRQ 1 -> extension 0 (X8A),
SS1/GPIO1_IRQ1 -> extension 1 (X9A)
S3_8
SS0/GPIO0_IRQ1 -> extension 0 (X8A),
0/1
SS1/GPIO1_IRQ1 -> display data connector (X6)
SS0/GPIO0_IRQ1 -> extension 1 (X9A),
1/x
SS1/GPIO1_IRQ1 -> display data connector (X6)
SPI and GPIO Connector Selection
9
PHYWIRE
10
GND
SPI_SS_SLOT0
SPI_SS_SLOT1
SPI1_MOSI
SPI1_SCLK
SPI1_MISO
/SPI1_RDY
SLOT0_IRQ
SLOT1_IRQ
GND
GND
USB3_DUSB4_DUSB3_D+
USB4_D+
Description
5 V power supply
5 V power supply
3.3 V power supply
3.3 V power supply
Ground
Ground
I2C Data
I2C Clock
Hardware Introspection Interface.
For internal use only
Ground
X8A: SPI chip select extension port 0
X9A: SPI chip select extension port 1
SPI master output/slave input
SPI clock output
SPI master input/slave output
SPI data ready input master mode only
X8A: Interrupt input extension port 0
X9A: Interrupt input extension port 1
Ground
Ground
X8A: USB3 Data D- 2
X9A: USB4 Data D- 3
X8A: USB3 Data D+1
X9A: USB4 Data D+2
ry
Signal Name
VCC5V
VCC5V
VCC3V3
VCC3V3
GND
GND
I2C_SDA
I2C_SCL
el
im
Pin #
1
2
3
4
5
6
7
8
in
a
Table 44:
11
Pr
12
13
14
15
16
17
18
19
20
Table 45:
1
:
:
3
:
2
84
PHYTEC Extension Connectors X8A, X9A
GPIO0_IRQ0 ≙ GPIO2_24 (at J23) and GPIO1_IRQ1 ≙ GPIO1_6 (at T3) of the i.MX 6 (refer to section 10))
LEDs D18 and D25 signal use of the USB3 interface (X8A)
LEDs D19 and D26 signal use of the USB4 interface (X9A)
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
17.3.13 Secure Digital Memory Card/ MultiMedia Card (X26)
Front
9.4mm
P1
MIC
OUT
IN
RS232
AUDIO
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
U17
ON / OFF
X27
1
S2
U4
BAT1
U21
U30
U33
J2
U23
U24
in
a
D37
D40
50
U25
U43
U7
D48
X32
X6
JP2 JP1
el
im
Figure 27:
D39
B
X34
phyCARD XL cooling area
MMC / SD card
J4
U29
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
Reset
S1
D50
D30
phyCARD Connector
U32
U16
U8
U12
U22
D45
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
USB Host
U20
X28
X29
LVDS
X3 X2 X1
X7
SD / MM Card interface at connector X26
Pr
The phyCARD Carrier Board provides a standard SDHC card slot at X26 for connection to
SD/MMC interface cards. It allows easy and convenient connection to peripheral devices
like SD- and MMC cards in 1-bit, or 4-bit bus mode. Power to the SD interface is supplied by
sticking the appropriate card into the SD/MMC slot. The card slot X26 connects to the
phyCARD-i.MX 6 via a level shifter to ensure the correct voltage for the SD/MMC cards.
© PHYTEC Messtechnik GmbH 2014
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85
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.14 Boot Mode Selection (JP1)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
U17
ON / OFF
X27
1
S2
U4
BAT1
U29
U21
U23
U30
U33
J2
U43
D48
X32
X6
JP2 JP1
1 2
3 4
el
im
U7
Figure 28:
D37
D40
50
U25
phyCARD XL cooling area
MMC / SD card
J4
U24
X34
D39
B
in
a
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
Reset
S1
D50
D30
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
Boot Mode Selection Jumper JP1
The boot mode jumper JP1 is provided to configure the boot mode of the phyCARD-i.MX 6
after a reset.
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By default the boot mode jumper is open, configuring the phyCARD-i.MX 6 for booting from
the NAND device. Table 46 shows the different boot options for the phyCARD-i.MX 6. Please
refer to section 6 as well as the i.MX 6 Reference Manual for more information about
possible configurations.
86
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
Jumper Setting
JP1
open
1+2
3+4
1+2,
3+4
Description
Jumper JP1 selects the boot device of the
phyCARD-i.MX 6
NAND 1
SD0 external 1
Serial USB OTG (USB0) 1
Bootconfig from eFUSE 1
Boot Options for the phyCARD-i.MX 6
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Table 46:
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other settings must not be used with the
phyCARD-i.MX 6
1
:
please see section 6 for more information on the different boot modes
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.15 System Reset Button (S1)
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
ON / OFF
X27
1
D46
S2
Reset
U4
BAT1
U29
U19
X34
U21
D37
D40
U23
U30
U33
J2
U43
D48
X32
X6
JP2 JP1
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U7
Figure 29:
J4
50
U25
phyCARD XL cooling area
MMC / SD card
D39
B
U24
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
in
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S1
D50
D30
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U17
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
System Reset Button S1
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The phyCARD Carrier Board is equipped with a system reset button at S1. Pressing this
button will toggle the X_nRESET_IN pin (X1A7) of the phyCARD SOM low, causing the
module to reset. Additionally, a peripheral reset is generated by the PLD (U25) on the CB
to reset peripherals such as the USB Hub, etc.
88
© PHYTEC Messtechnik GmbH 2014
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The phyCARD®-i.MX 6 on the phyBASE
17.3.16 RTC at U3
Front
9.4mm
P1
X7
MIC
OUT
IN
RS232
USB Host
X33
U2
J1 CAM
PWR
JP3
U13
D49
U27
U14
USB Host
D45
U11
U10
X9
X8
Expansion 2
U26
Expansion 1
U31
D41
U9
U17
ON / OFF
X27
1
U4
BAT1
U29
in
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D37
D40
50
U25
U21
U23
U30
U33
J2
U43
U7
D48
X32
X6
JP2 JP1
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Figure 30:
D39
B
U24
X34
phyCARD XL cooling area
MMC / SD card
J4
U19
S3
X26
U3
D29
D22
D28
D21
D27
D20
D26
D19
D25
D18
D24
D17
D23
D16
U15
U5
A
ry
D46
S2
Reset
S1
D50
D30
phyCARD Connector
U32
U16
U8
U12
U22
J3
D38
Ethernet
U6
U1
U28
X10
USB OTG
X5
AUDIO
U20
X28
X29
LVDS
X3 X2 X1
RTC with Battery Buffer
For real-time or time-driven applications, the phyBASE is equipped with an RTC-8564 RealTime Clock at U3. This RTC device provides the following features:
Pr
• Serial input/output bus (I2C), address 0x51 (7 MSB)
• Power consumption
Bus active (400 kHz):
< 1 mA
Bus inactive, CLKOUT inactive:
= 275 nA
• Clock function with four year calendar
• Century bit for year 2000-compliance
• Universal timer with alarm and overflow indication
• 24-hour format
• Automatic word address incrementing
• Programmable alarm, timer and interrupt functions
The Real-Time Clock is programmed via the I2C bus (address 0x51). Since the
phyCARD-i.MX 6 is equipped with an internal I2C controller, the I2C protocol is processed
very effectively without extensive processor action (refer also to section 9.5)
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
The Real-Time Clock also provides an interrupt output that extends to the Wakeup input of
the PLD at U25 and is used within the PLD's state machine. Additionally the interrupt is
inverted and brought out as low active signal X_nWakeUp at pin X27A48 1 on the phyCARD
Connctor An interrupt occurs in the event of a clock alarm, timer alarm, timer overflow and
event counter alarm. It has to be cleared by software. With the interrupt function, the
Real-Time Clock can be utilized in various applications.
The RTC_CLK signal, which is also connected to the PLD at U25, can be programmed to
various frequencies e.g. 1 Hz.
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Caution!
As the RTC_CLK signal is used for the timing of the PLD's internal processes great care must
be taken to ensure that the timing doesn't get corrupted by changing the frequency.
in
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Note:
After connection of the supply voltage the Real-Time Clock generates no interrupt. The RTC
must be first initialized (see RTC Data Sheet for more information).
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Use of a coin cell at BAT1 allows to buffer the RTC.
1
:
90
extending on the phyCARD-i.MX 6 to the input port PWRON of the PMIC (U29) and port P3.2 of the CMIC (U13)
© PHYTEC Messtechnik GmbH 2014
L-800e_0
The phyCARD®-i.MX 6 on the phyBASE
17.3.17 PLD at U25
The phyBASE is equipped with a Lattice LC4256V PLD at U25. This PLD device provides the
following features:
• Power management function (section 17.3.2)
• Signal mapping and configuration of the sound devices at U1 (for AC'97) and at U17
(for I2S) (section 17.3.8)
• Signal mapping SPI chip select and interrupt to the extension or display connectors
(sections 17.3.10 and 17.3.11)
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• Touch Signal mapping to the discrete touch controller at U28, or to the touch controller
integrated in the audio codec at U1 (section 17.3.7.3)
© PHYTEC Messtechnik GmbH 2014
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3mm
X26
BAT1
D29
D22
D28
D21
D27
D20
D19
D25
D18
D24
D17
D23
D26
D16
D30
U10
U4
X8
S3
172mm
185mm
U25
U3
U29
Expansion 1
J2
in
a
USB Host
U14
USB Host
U12
D41
U43
U30
USB OTG
X29
U33
X32
X27
U26
D40
D37
X10
Ethernet
ry
D46
U21
U19
X34
XT1
U6
U27
X33
X7
U18
MMC / SD card
U5
S1
Reset
S2
U22
RS232
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U31
D45
U32
ON / OFF
J3
U17
U2
U16
Expansion 2
X9
X4
CAM
X5
9.4mm
U28
U20
U1
Pr
J1
AUDIO
X3 X2 X1
P1
Front
U15
6.5mm
3mm
Figure 31:
phyCARD Connector
MIC
OUT
IN
PWR
JP2 JP1
X28
X6
LVDS
92
U23
D39
U9
U8
D38
D3.2mm
124mm
130mm
6.5mm
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
17.3.18 Carrier Board Physical Dimensions
U24
U11
U13
U7
Carrier Board Physical Dimensions
Please contact us if a more detailed dimensioned drawing is needed to integrate the
phyBASE into a customer application.
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Revision History
18 Revision History
Version #
Manual
L-800e_0
Changes in this manual
Preliminary edition.
Describes the phyCARD-i.MX 6 SOM (PCB 1371.2) with
phyBASE- Carrier Board (PCB 1360.2).
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Date
21.08.2014
© PHYTEC Messtechnik GmbH 2014
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phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
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© PHYTEC Messtechnik GmbH 2014
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Index
Index
1
I
100Base-T.......................................... 35
10Base-T ........................................... 35
I²C EEPROM ........................................ 28
I2C Interface ....................................... 36
I2C Memory......................................... 16
I2S.................................................... 37
9
9 .................................................... 46
A
J
B
L
Backup Voltage ................................... 18
Block Diagram....................................... 3
Boot Configuration .............................. 26
Booting ............................................. 25
LAN .................................................. 36
LED
SOM D1 .......................................... 40
SOM D2 .......................................... 40
LINK LED............................................ 70
LVDS
Camera Signals........................... 16, 46
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Camera Interface ................................. 46
Control Management IC......................... 18
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Audio CODEC....................................... 79
Audio Interface ................................... 37
J3 ............................................... 16, 28
J31.............................................. 16, 46
JTAG Interface .................................... 41
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DDR3 SDRAM ...................................... 27
DDR3_1V5.......................................... 19
DDR3_VREF ........................................ 19
DDR3_VTT .......................................... 19
Debug Interface .................................. 41
Dimensions ........................................ 48
Display Interface ................................. 44
E
EEPROM ........................................ 27, 28
EEPROM Write Protection....................... 28
EMC ................................................... xi
Ethernet ............................................ 35
F
Features ......................................... 2, 55
G
General Purpose I/Os............................ 39
GND Connection .................................. 53
H
Humidity............................................ 48
© PHYTEC Messtechnik GmbH 2014
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M
MAC .................................................. 36
MAC Address....................................... 36
N
NAND Flash ........................................ 27
O
Operating Temperature......................... 48
Operating Voltage................................ 48
P
PDI ................................................... 74
phyBASE
Connectors ..................................... 58
P1 69
Peripherals ..................................... 57
Pin Header ..................................... 58
Switches ........................................ 59
X10 ............................................... 70
X27 ............................................... 66
X28 ............................................... 67
X29 ............................................... 73
X32 ............................................... 74
X33 ............................................... 71
95
phyCARD®-i.MX 6 [PCA-A-XL3-xxx]
Technical Specifications ........................ 47
U
U10 .................................................. 28
U11 .................................................. 35
U13 .................................................. 27
U17 .................................................. 18
U27 ............................................. 16, 46
U29 .................................................. 18
U2-U9 ............................................... 27
UART ................................................. 32
USB
OTG Interface .................................. 32
USB 2.0 ........................................ 71, 73
USB Device ......................................... 33
USB Host ...................................... 32, 33
USB OTG............................................. 32
User LEDs ........................................... 40
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X6 ............................................ 71, 74
X7 ................................................. 71
X8 ................................................. 71
X9 ................................................. 71
phyCARD-Connector ............................7, 8
Physical Dimensions ............................. 47
PHYTEC Display-Interface ...................... 74
Pin Description...................................... 7
Pinout ..................................... 10, 11, 12
PLD ................................................... 92
PMIC ................................................. 18
Power Consumption.............................. 48
Power Domains.................................... 19
Power Management.............................. 23
Power Management IC .......................... 18
Power Supply ........................................ 6
RS-232 Level....................................... 32
RTC ................................................... 90
V
S
VDD_3V3....................................... 17, 19
Voltage Output.................................... 21
VSTBY ................................................ 18
VSTBY_IN ........................................... 19
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SD / MMC Card Interfaces....................... 29
SDRAM............................................... 27
Serial Interfaces .................................. 31
SMT Connector ...................................... 7
SPEED LED .......................................... 70
SPI Interface....................................... 37
Storage Temperature ............................ 48
Supply Voltage .................................... 17
System Configuration ........................... 25
System Memory ................................... 27
System Power...................................... 17
96
W
Weight............................................... 48
WM9712L ........................................... 79
X
X29................................................... 73
X3 .................................................... 41
© PHYTEC Messtechnik GmbH 2014
L-800e_0
Suggestions for Improvement
Document:
Document number:
phyCARD®-i.MX 6
L-800e_0, August 2014
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Postfach 100403
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Fax : +49 (6131) 9221-33
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Printed in Germany
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