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User’s Manual
User’s Manual
EMMA Mobile Family
SEMC-EM1
EMMA MobileTM1
Document No.
190445001 (1.4 Edition)
Date Published Feb. 2010
© Shimafuji Electronics Inc.
Printed in Japan
z
Development Kit Board
[MEMO]
2
User’s Manual
The names of other companies and products are the registered trademarks or trademarks of the
respective company.
These commodities, technology or software, must be exported in accordance with the export
administration regulations of the exporting country. Diversion contrary to the low of that country
is prohibited.
NOTES FOR CMOS DEVICES
1. Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS
device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take
care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition
period when the input level passes through the area between VIL (MAX) and VIH (MIN).
2.HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that
an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using
pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a
possibility that it will be an output pin. All handling related to unused pins must be judged separately for each
device and according to related specifications governing the device.
3.PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a
humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or
conductive material. All test and measurement tools including work benches and floors should be grounded.
The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.
4.STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is
turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee
output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received.
A reset operation must be executed immediately after power-on for devices with reset functions.
5.POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external interface, as a
rule, switch on the external power supply after switching on the internal power supply. When switching the
power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the
reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the
device, causing malfunction and degradation of internal elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or
an I/O pull-up power supply while the device is not powered. The current injection that results from input of
such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the
device at this time may cause degradation of internal elements. Input of signals during the power off state must
be
z
・The names of other companies and products are the registered trademarks or trademarks of the respective
company. The information in this document is current as of August, 2008. The information is subject to change
without notice. For actual design-in, refer to the latest publications of Shimafuji specification, etc., for the most
up-to-date specifications of Shimafuji products. Not all products and/or types are available in every country. Please
check with a Shimafuji sales representative for availability and additional information.
・No part of this document may be copied or reproduced in any form or by any means without the prior
consent of Shimafuji. Shimafuji assumes no responsibility for any errors that may appear in this document.
written
・Shimafuji does not assume any liability for infringement of patents, Copyrights or other intellectual property rights of
third parties by or arising from the use of Shimafuji products listed in this document or any other liability arising from
the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of Shimafuji or others.
・Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer.
Shimafuji assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
・While Shimafuji endeavors to enhance the quality, reliability and safety of Shimafuji products, customers agree and
acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to
property or injury (including death) to persons arising from defects in Shimafuji products, customers must incorporate
sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.
・If customers wish to use Shimafuji products in applications not intended by Shimafuji, they must contact an
Shimafuji sales representative in advance to determine Shimafuji' willingness to support a given application.
(Note)
(1)"Shimafuji" as used in this statement means SHIMAFUJI Electric Incorporated. and also includes its
majority-owned subsidiaries.
(2)"Shimafuji products" means any product developed or manufactured by or for Shimafuji (as defined above).
4
User’s Manual
PREFACE
(1) Readers
This manual is intended for hardware/software application system designers who wish to understand and use board
functions of EMMA Mobile1 (EM1), a multimedia processor for mobile applications.
(2) Purpose
This manual is intended to explain to users the hardware and software functions of the board of EM1, and be used as
a reference material for developing hardware and software for systems that use EM1.
(3) Organization
This manual consists of the following chapters.
•
Chapter 1
Introduction
•
Chapter 2
Functions
•
Chapter 3
System Control
•
Chapter 4
Connecters
•
Chapter 5
Others
(4) How to read this manual
It is assumed that the readers of this manual have general knowledge of electricity, logic circuits, and microcontrollers.
To understand the functions of the board of EM1 in detail, read this manual according to the CONTENTS.
To understand the LSI functions of EM1, refer to the user’s manual of the respective module.
To understand the electrical specifications of EM1, refer to the Data Sheet.
(5) Conventions
Data significance:
Note:
Caution:
Remark:
Higher digits on the left and lower digits on the right
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Numeric representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Data type:
Word
… 32 bits
Half word … 16 bits
Byte
… 8 bits
(6) Major revised point
The revised points can be easily searched by using an "<R>" in the PDF file and specifying it in the “Find what:” field.
DISCLAIMER
This user's manual and development kit board is intended for the evaluation of the Emma mobile 1 and is not intended
to be included as part of any final product. The designs contained in this document are for reference and example
purposes only.
The information in this document is subject to change without notice. No part of this document may be copied or
reproduced in any form or by any means without the prior written consent of RENESAS Electronics Corporation.
RENESAS Electronics Corporation assumes no responsibility for any errors which may appear in this document.
RENESAS Electronics Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties by or arising from use of a device described herein or any other liability
arising from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of RENESAS Electronics Corporation or others.
User’s Manual
5
Related Documents
Document Name
Data sheet
Audio/Voice and PWM Interfaces
DDR SDRAM Interface
DMA Controller
I2C Interface
ITU-R BT.656 Interface
LCD Controller
MICROWIRE
NAND Flash Interface
User’s
SPI
Manual
UART Interface
Image Composer
Image Processor Unit
System Control/General-Purpose I/O Interface
Timer
Terrestrial Digital TV Interface
Camera Interface
USB Interface
Power Supply Chip
SD Memory Card Interface
PDMA
One Chip
Document No.
S19269E
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Caution: The related documents listed above are subject to change without notice. The related documents indicated in this
publication may include preliminary versions. However, preliminary versions are not marked as such. Be sure to use the
latest version of each document when designing.
6
User’s Manual
CONTENTS
CHAPTER 1.
1.1.
1.2.
1.3.
1.4.
CHAPTER 2.
2.1.
2.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
FUNCTIONS .................................................................................................................. 24
BOARD FUNCTION SUMMARY ........................................................................................................................... 24
PARTS DETAIL DESCRIPTIONS .......................................................................................................................... 25
2.2.1.
EMMA Mobile1-S (CPU LSI) ......................................................................................................... 25
2.2.2.
Power LSI (DA9052) ....................................................................................................................... 25
2.2.3.
DDR-SDRAM (MT46H32M32LFCM-6)......................................................................................... 25
2.2.4.
EMMC NAND Memory (MTFC4GDKDI-ET or KMCEG0000A) ................................................. 26
2.2.5.
NOR Flash Memory (PC28F256P30B85) ...................................................................................... 26
2.2.6.
Ether (LAN9221) ............................................................................................................................ 26
2.2.7.
USB-PHY (ISP1504 or USB3329) ................................................................................................. 27
2.2.8.
COM-Port (FT232RQ) .................................................................................................................... 27
2.2.9.
TV-OUT (ADV7179KCPZ) .............................................................................................................. 27
2.2.10. Audio LSI (AK4648EC) .................................................................................................................. 28
2.2.11. NAND Flash Memory (K9F1G08U0A)
NOT MOUNTED on the board. ................................. 28
CHAPTER 3.
3.1.
3.2.
INTRODUCTION ............................................................................................................ 15
OVERVIEW ....................................................................................................................................................... 15
1.1.1.
CPU Board ...................................................................................................................................... 15
1.1.2.
IO board .......................................................................................................................................... 15
1.1.3.
LCD Panel ...................................................................................................................................... 16
CONNECTORS .................................................................................................................................................. 17
1.2.1.
CPU Board Image........................................................................................................................... 17
1.2.2.
IO Board Image .............................................................................................................................. 19
POWER SUPPLY ............................................................................................................................................... 21
DEVELOPMENT TOOLS CONNECTION ............................................................................................................... 22
1.4.1.
CPU Board ICE Interface [CN1] ................................................................................................... 22
1.4.2.
IO board Debug Interface [CN6], [CN9] ........................................................................................ 23
SYSTEM CONTROL ...................................................................................................... 29
SYSTEM BLOCK DIAGRAM ................................................................................................................................ 29
MEMORY MAP ................................................................................................................................................. 30
3.2.1.
All Memory Bank ........................................................................................................................... 30
3.2.2.
BANK 0/1/2 ..................................................................................................................................... 31
3.2.3.
BANK3 DRAM AREA .................................................................................................................... 32
POWER SYSTEM ............................................................................................................................................... 33
3.3.1.
Power System Configuration ......................................................................................................... 34
3.3.2.
EM1-DA9052 Connection ............................................................................................................... 35
3.3.3.
Power down Control for Board device. .......................................................................................... 36
3.3.4.
Power Supply Source...................................................................................................................... 37
3.3.5.
RTC Backup Battery ...................................................................................................................... 38
CLOCK SYSTEM ............................................................................................................................................... 39
3.4.1.
CPU Board Clock Tree Structure .................................................................................................. 39
3.4.2.
IO Board Clock Tree Structure ...................................................................................................... 40
RESET SYSTEM ................................................................................................................................................ 41
3.5.1.
Reset System Architecture ............................................................................................................. 41
ON BOARD INTERRUPTS .................................................................................................................................. 42
GPIO .............................................................................................................................................................. 43
3.7.1.
EMMA Mobile1 ............................................................................................................................... 43
3.7.2.
DA9052 ........................................................................................................................................... 50
3.7.3.
MAX7324 ........................................................................................................................................ 54
PIN SETTING .................................................................................................................................................... 56
3.8.1.
AB0.................................................................................................................................................. 56
3.8.2.
PM0 ................................................................................................................................................. 58
3.8.3.
NTS,SP1.......................................................................................................................................... 59
3.8.4.
DTV,SP2 .......................................................................................................................................... 60
3.8.5.
SP0,MMI ......................................................................................................................................... 61
3.8.6.
LCDC .............................................................................................................................................. 62
3.8.7.
IIC ................................................................................................................................................... 64
3.8.8.
URT0, URT1 ................................................................................................................................... 65
3.8.9.
SD0 .................................................................................................................................................. 66
3.8.10. SD1 .................................................................................................................................................. 68
3.8.11. NAND, URT2, SD2, IIC ................................................................................................................. 70
3.8.12. PWM ............................................................................................................................................... 73
3.8.13. USB ................................................................................................................................................. 74
3.8.14. OSC, PLL2 ...................................................................................................................................... 76
User’s Manual
7
3.9.
3.10.
3.11.
3.12.
3.13.
3.14.
3.15.
3.16.
3.17.
CHIP SELECT ................................................................................................................................................... 77
3.9.1.
EM1-S System Connection Architecture ....................................................................................... 77
3.9.2.
External Bus Chip Select (CSB0 to CSB3).................................................................................... 78
3.9.3.
SPI Chip Selects ............................................................................................................................. 78
IIC CONNECTION ............................................................................................................................................ 79
DIP SWITCHES, KEYS, LED SPECS .................................................................................................................. 80
3.11.1. Button switches and LEDs on CPU Board .................................................................................... 80
3.11.2. Key-buttons, Side Switches, LEDs on IO Board ........................................................................... 81
3.11.3. IO Board Switches and LEDs ........................................................................................................ 82
3.11.4. Boot Mode Switch (DSW1) on CPU Board .................................................................................... 84
3.11.5. General Purpose Key Buttons and LEDs System Architecture ................................................... 85
AUDIO LSI CONNECTION ................................................................................................................................. 87
LAN9221 CONNECTION WITH EM1 .................................................................................................................. 88
TOUCH SCREEN I/F ......................................................................................................................................... 89
DDR SETTING ................................................................................................................................................. 90
SPI INTERFACE ............................................................................................................................................... 91
USB INTERFACE ............................................................................................................................................. 91
3.17.1. USB Switch for Host Mode ............................................................................................................ 91
3.17.2. USB Charger Detection.................................................................................................................. 92
CHAPTER 4.
4.1.
4.2.
4.3.
CHAPTER 5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
8
CONNECTORS .............................................................................................................. 93
CPU BOARD CONNECTORS .............................................................................................................................. 93
4.1.1.
CCPU JTAG Connector [CN1] ....................................................................................................... 93
4.1.2.
SD Interface Connector [CN2] ....................................................................................................... 93
4.1.3.
LCD Interface Connector [CN4] .................................................................................................... 94
4.1.4.
USB Interface Connector [CN5] .................................................................................................... 95
4.1.5.
USB Interface (from UART) Connectors [CN6] ............................................................................ 95
4.1.6.
Peripheral Connector [CN7] [CN8]................................................................................................ 96
4.1.7.
Power LSI (D9052) Monitor [CN9] ................................................................................................ 98
4.1.8.
JUMPER [JP1] ............................................................................................................................... 98
IO BOARD CONNECTORS .................................................................................................................................. 99
4.2.1.
CPU Daughter Board Connectors [CN1, CN2] ............................................................................. 99
4.2.2.
AB0 external [CN3] ...................................................................................................................... 101
4.2.3.
Enhanced Connector [CN4] ......................................................................................................... 102
4.2.4.
Enhanced Connector [CN5] ......................................................................................................... 102
4.2.5.
Debugger [CN6] [CN9] ................................................................................................................. 103
4.2.6.
Battery Connector [CN10] ........................................................................................................... 104
4.2.7.
JTAG Connector [CN11] ............................................................................................................... 105
4.2.8.
NTSC/PAL Connector [J1] ........................................................................................................... 106
4.2.9.
AUDIO Connector [J2, J3] ........................................................................................................... 106
4.2.10. AC Adapter Connector [J4 ] ......................................................................................................... 106
LCD.............................................................................................................................................................. 107
4.3.1.
LCD Panel Interface Connector [CN7] ........................................................................................ 107
OTHERS ...................................................................................................................... 108
USB CONNECTION ........................................................................................................................................ 108
5.1.1.
USB Mini B Connector by using serial COM port of EM1 ......................................................... 108
5.1.2.
USB Mini AB ................................................................................................................................ 108
BOARD INSTALLATION TO THE CASE ............................................................................................................... 109
MAC ADDRESS .............................................................................................................................................. 110
SERIAL NUMBER ........................................................................................................................................... 110
BOARD REVISION........................................................................................................................................... 110
BOARD INFORMATION IN EEPROM (FACTORY SETTING) ................................................................................ 111
MONITOR POINT AND TEST PAD ..................................................................................................................... 112
MODIFICATION FOR SIGNALS IN EXTERNAL CONNECTOR [CN4/CN5] .............................................................. 113
CONNECTION OF CPU BOARD AND IO BOARD ................................................................................................. 114
User’s Manual
LIST OF FIGURES
Figure No
Figure 1-1
Title
Page
LCD Image .................................................................................................................................................... 16
Figure 1-2 CPU Board Image ......................................................................................................................................... 17
Figure 1-3 IO board Image(Front) .............................................................................................................................. 19
Figure 1-4 IO board Key Image(Front) ....................................................................................................................... 19
Figure 1-5 IO board Image (back) .................................................................................................................................. 20
Figure 1-6 AC/DC Adapter Image ................................................................................................................................... 21
Figure 1-7 CPU Board ICE Interface .............................................................................................................................. 22
Figure 1-8 Debug Interface [CN6], [CN9]........................................................................................................................ 23
Figure 3-1 System Block Diagram .................................................................................................................................. 29
Figure 3-2 EMMA Mobile1 ALL Memory Bank ................................................................................................................ 30
Figure 3-3 EMMA Mobile1 NOR and Asynchronous Bus0 (No.0) Memory Map ............................................................. 31
Figure 3-4
EMMA Mobile1 DRAM Memory Map ............................................................................................................. 32
Figure 3-5
Power System Architecture ........................................................................................................................... 33
Figure 3-6 DA9052 – EM1 Connection ........................................................................................................................... 35
Figure 3-7
CPU Board .................................................................................................................................................... 37
Figure 3-8 CPU Board and I/O Board ............................................................................................................................. 37
Figure 3-9 Position of ML414.......................................................................................................................................... 38
Figure 3-10
Clock Source on CPU Board ....................................................................................................................... 39
Figure 3-11 Clock Source on IO Board ........................................................................................................................... 40
Figure 3-12
Reset System Architecture .......................................................................................................................... 41
Figure 3-13
GPIO Base Reset System for IO Board ...................................................................................................... 41
Figure 3-14 IRQ Tree of EM1 Development Kit Board .................................................................................................... 42
Figure 3-15 IIC Connection tree ..................................................................................................................................... 79
Figure 3-16 Top View of Key Matrix Switches and LEDs ................................................................................................ 81
Figure 3-17
DSW1 Photo and Top view Image ............................................................................................................... 84
Figure 3-18
Key Buttons and Side Switch System ......................................................................................................... 85
Figure 3-19
Key Buttons and Side Switch System ......................................................................................................... 86
Figure 3-20 Audio IF Circuit Block Diagram.................................................................................................................... 87
Figure 3-21 LAN9221- AB0 Connection ......................................................................................................................... 88
Figure 3-22 Touch Screen Control System ..................................................................................................................... 89
Figure 5-1
Case ............................................................................................................................................................ 109
User’s Manual
9
LIST OF TABLE
Table No
Title
Page
Table 2-1 Board Function................................................................................................................................................ 24
Table 3-1
Power System Configuration........................................................................................................................... 34
Table 3-2 Power down control for board devices ............................................................................................................ 36
Table 3-3 CPU Board JUMPER [JP1] ............................................................................................................................. 37
Table 3-4 EM1 GPIO Settings......................................................................................................................................... 43
Table 3-5 DA9052 GPIO ................................................................................................................................................. 50
Table 3-6 MAX7324 GPIO .............................................................................................................................................. 54
Table 3-7 EM1-S System Connection Architecture ......................................................................................................... 77
Table 3-8
External Bus Chip Select (CSB0 to CSB3) ..................................................................................................... 78
Table 3-9 SPI Chip Selects ............................................................................................................................................. 78
Table 3-10 IIC Read / Write Address............................................................................................................................... 79
Table 3-11
CPU Board Button Switches ......................................................................................................................... 80
Table 3-12 IO Board Switches and LEDs (1) .................................................................................................................. 82
Table 3-13 IO Board Switches and LEDs (2) .................................................................................................................. 83
Table 3-14
DSW1 Boot Mode Switch Description (1) ..................................................................................................... 84
Table 3-15
DSW1 Boot Mode Switch Description (2) ..................................................................................................... 84
Table 3-16
DA9052 Register USB Charger Detection Setting ........................................................................................ 92
Table 4-1 SICA20C20Y-GA102....................................................................................................................................... 93
Table 4-2 DM3AT-SF-PEJ............................................................................................................................................... 93
Table 4-3 FH23-51S-0.3SHW(06) ................................................................................................................................... 94
Table 4-4 56579-0579 ..................................................................................................................................................... 95
Table 4-5 UX60SA-MB-5ST ............................................................................................................................................ 95
Table 4-6 SO DIMM[CN7] ............................................................................................................................................ 96
Table 4-7 SO DIMM[CN8] ............................................................................................................................................ 97
Table 4-8 BM07B-SRSS-TB ........................................................................................................................................... 98
Table 4-9
XJ3B-0311 ...................................................................................................................................................... 98
Table 4-10 SO DIMM[CN1] .......................................................................................................................................... 99
Table 4-11 SO DIMM[CN2] ......................................................................................................................................... 100
Table 4-12
DF17(4.0)-60DS-0.5V(57) ........................................................................................................................... 101
Table 4-13
DF17(4.0)-40DS-0.5V(57) ........................................................................................................................... 102
Table 4-14
DF17(4.0)-40DS-0.5V(57) ........................................................................................................................... 102
Table 4-15
2-5767004-2................................................................................................................................................ 103
Table 4-16 Through Hole .............................................................................................................................................. 104
Table 4-17 FFC-12BMEP1............................................................................................................................................ 105
Table 4-18 MR-551L ..................................................................................................................................................... 106
Table 4-19 M03-772A0 [J2]........................................................................................................................................... 106
Table 4-20 M03-772A0 [J3]........................................................................................................................................... 106
Table 4-21
HEC3600-010520 ....................................................................................................................................... 106
Table 4-22 FH23-51S-0.3SHW(06) ............................................................................................................................... 107
Table 5-1 LAN9221 EEPROM Address: 0x10 ................................................................................................................ 111
Table 5-2 LAN9221 EEPROM Address: 0x11 ................................................................................................................ 111
Table 5-3 LAN9221 EEPROM Address: 0x12 ................................................................................................................ 111
Table 5-4 Monitor Point and Test Pad ............................................................................................................................112
Table 5-5 Modification signal in external connector .......................................................................................................113
10
User’s Manual
User’s Manual
11
To use this Product safety
In this paragraph, it explains notes to use this product safety. Please read before using the product.
・Please defend the content of the description of this document and use the product.
・Please keep this document near the main body of the product to refer at once when it is necessary.
・The content that has been described is the one in this document at the time of making. The inquired window, address,
telephone number, and the content and the address, etc. on the homepage might have been changed. Please
acknowledge it beforehand.
To mean mark
In this document, the item to use the product safety has been described as follows.
■When you cannot defend the content of the description.
You damage to personal to harm and the property.
DANGER
It is assumed that the user owes the death or the serious
illness (note 1) and shows the content with high risk.
WARNING
The content that the user owes the death or the serious illness
is shown.
CAUTION
The people receive injury (note 2), Receive the property
damage (note 3).
(note1)Definition of serious illness. Losing sight, injury, Burn (high temperature and low temperature), Electric
shock, Fracture, The one that squealed remains because of poisoning etc and the one to require going to hospital
regularly that hospitalizes and is long-term to treat.
(note 2 )Definition of injury. The one to require hospitalization and a long-term going to hospital regularly to treat
is said.
(note 3)Definition of property damage. It is damage to the building and equipment.
Alarm display in board products use
■The demand in the handling of the product is classified as follows.
・It is a mark that prohibits the act.
General prohibition
Example: Contact prohibition
The described act is prohibited.
The possibility of owing injury by touching
the specific location is shown.
・It is a mark of attention.
Example: High temperature attention.
General attention
The possibility of injury by the high
The general attention not specified is
temperature is shown.
shown.
・It is a mark that compels the act based on the instruction.
General instruction
The example: Pull out the power plug.
It is the one to compel the act based on
It is the one directed to pull out the plug of the
AC adapter.
the instruction.
12
User’s Manual
DANGER
DANGER
There is no danger marking in this product.
Warning
Warning
The hot section is in a part of the substrate when the AC power supply is connected.
Please note the high temperature burn.
The power supply and the plug use the one of ratings 2A that suited the safety standard of the product
according to law in country that uses it.
The use of the unacceptable products causes the breakdown, generation of heat, a fire, and the
electric shock.
Please detach the AC plug from the outlet when you generate smoke, a nasty smell, an abnormal
sound, and abnormal generation of heat, etc. by any chance. Using Products as it is. It causes a fire,
the burn, and the electric shock.
This product Shouldn’t dismantle and remodel by the customer.
It causes the breakdown, smoking, a fire, and the electric shock.
The product is not dropped, and the strong shock is given.
It causes a fire and the electric shock damaging it.
The AC adapter cable is not t pull out of supply entered. So connecter is not pull out of supply entered.
Exception: Cable can pull out of power supply. Pulling out the connector is not done with the power
supply entered.
It causes a fire and the electric shock damaging it.
The connection of the cable and the interface cable is insufficient and the power supply is not turned
on.
It causes the breakdown, generation of heat, a fire, and the explosion.
When moving products, cables and power supply are removed.
The cable etc. is damaged, and it causes the breakdown, generation of heat, a fire, and the electric
shock.
Caution
Caution
The power supply turning on and cutting each system follow the procedure described in the manual.
It causes the breakdown of generation of heat and the equipment to occur.
User’s Manual
13
General Precautions for Handling This Product
1.Circumstances not covered by product guarantee
Does not use over voltage, and use outside guaranteed temperature range.
Do not add power to the USB cable, and do not add power to the USB interface.
Do not remove or break S/N (Serial Number) sticker. These stickers are required for warranty validation.
2. Safety precautions
If used for a long time, the product may become hot (50°C to 60°C). Be careful of low temperature burns and
other dangers due to the product becoming hot.
It is explained by the previous item. “1. Circumstances not covered by product guarantee”.
3. Warning
The board is selling “AS IS” .If board has Faults. You and your company acknowledge and agree risk.
Anytime, you examine New Information of this Board and Devices.
Shimafuji don’t pay the ransom that exceeds the price of the product is not paid.
14
User’s Manual
CHAPTER 1.
INTRODUCTION
Development Kit Board is a reference design board which is mounted a EMMA Mobile 1. This document is information for
a software development, the demonstration and hardware evaluation. The Development Kit Board on EMMA Mobile 1 is
embedded low power SOC. The board is including components, debug I/F, Function, system control, Connecter,
Restriction and more.
1.1.
Overview
The major components of the boards are described below.
CPU Board, IO board, LCD
1.1.1.
CPU Board
PCB: 8 layers
Main LSI: EMMA mobile-S (μPD77630A)
Mobile DDR SDRAM: 1Gbit (8 Meg x 32 x 4 Banks)
FLASH-ROM
eMMC NAND-FLASH: 4Gbyte
IO board Interface
LCD Interface
JTAG ICE IF (Special Header; TET SICA20C20Y-GA102)
Micro SD Card IF
USB Mini AB Interface
Com Port Interface (USB mini B)
General purpose switch (2)
General purpose LED (2)
Sound interface: LINE OUT
1.1.2.
IO board
PCB: 6 layers
CPU Board Interface
LCD Interface
NTSC interface: RCA Jacks
Sound interface: LINE OUT, MIC 1 Channel
Ethernet interface: RJ-45
General purpose switch matrix (14)
General purpose LED (4)
JTAG ICE IF (Mictor)
Expansion interface
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CHAPTER
1.1.3.
1
0BINTRODUCTION
LCD Panel
Manufacture: NEC LCD Technologies, Ltd.
Product Name: NL8048HL11-01B
Type: TFT Active matrices LCD
Size: 99.6(H) × 69.5(V) × 5.0(D) mm (typ)
Interface: FH23-51S-0.3SHW (HRS)
Touch Panel Control: SPI
Color: 16777216(8-bit digital RGB)
Pixel: 800(H) × 480(V)
5 (mm)
99.6 (mm)
69.5 (mm)
Figure 1-1
LCD Image
CAUTION:
LCD board has bonded on PCB through Acrylic fiber board. LCD must not detach on PCB.
That would cause the breakdown which cannot recover.
16
User’s Manual
CHAPTER
1.2.
1.2.1.
1
0BINTRODUCTION
Connectors
CPU Board Image
【CN1】Debug IF
【DSW1】Boot mode switch
【J1】AUDIO Line OUT
【SW2】
Debug enable
Switch
【CN4】
LCD IF
【SW4】
Multi purpose
Switch
【LED1】
General
LED
【SW1】
Reset Switch
【LED2】
General
LED
【SW5】
Multi purpose
Switch
【CN9】
EVB I/F
【CN2】
MicroSD
Card IF
【JP1】Jumper
【LED3】
PowerLED
【CN5】Mini USB AB
【CN8】SO DIMM
(Back)
【CN7】SO DIMM
(Back)
【CN6】COM Port (USB MIniB)
Figure 1-2
CPU Board Image
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17
CHAPTER
1
0BINTRODUCTION
【CN1】Debug IF: Special Connecter that attached SICA20C20Y-GA102
【CN2】Micro SD Card IF
【CN4】LCD Interface
【CN5】Mini USB AB
【CN6】COM Port (USB Mini B)
【CN7】,【CN8】SO DIMM(Back)
【CN9】EVB IF
【JP1】Jumper (VBUS line switch to HOST mode/DEVICE mode)
【J1】AUDIO JACK (LINE OUT)
【DSW1】DIP Switch (Boot mode Select)
【SW1】Reset Switch (Board system reset)
【SW2】Debug Switch (Debug enable)
【SW4】【SW5】Two general purpose push Switches.
18
User’s Manual
CHAPTER
1.2.2.
1
0BINTRODUCTION
IO Board Image
(1) Front View
[LED1-4] General purpose
[SW2-4, SW6-14]
General purpose Switches
【CN9】Debug IF(MICTOR)
Figure 1-3
IO board Image(Front)
【CN9】Debug IF(Mictor)
【SW2-4, SW6-14】general purpose Switches
【LED1-4】general purpose LEDs
SW2
SW6
SW9
SW12
SW3
SW7
SW 10
SW13
LED1
LED2
LED3
SW4
SW8
Figure 1-4
SW 11
SW14
LED4
IO board Key Image(Front)
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19
CHAPTER
1
0BINTRODUCTION
(2) Back View
【CN5】Expansion Connecter
【CN3】AB0 expansion
【J2】Audio
MIC IN
【CN10】
BATTERY
【J3】Audio
LINE OUT
【SW19】
NTS/PM1 Clock Select
【CN1】
SO DIMM
【SW17】
NTS LSI Reset SW
【SW5】
Side Switch
【SW1】
Side Switch
【CN2】
SO DIMM
【CN6】
Debug
IF(Mictor)
【J1】
NTSC/Pal
【T1】
Ether
【J4】
+5V Jack
【CN4】Expansion Connecter
【SW16】Debug Target Control Switch
Figure 1-5
<R>
【CN7】
LCD Interface
【SW15】
Power SW
IO board Image (back)
【CN1】【CN2】CARD edge
【CN3】AB0 expansion
【CN4】【CN5】Expansion Connecter
【CN6】Debug IF(Mictor)
【CN7】LCD Interface
【CN10】BATTERY Connecter
【SW1】【SW5】Side Switch(x2)
【SW15】Power Switch
【SW16】Debug target Control switch (CPU or DSP)
【SW17】NTS LSI Reset SW
【SW19】NTS/PM1 Clock Select
【SW20】use for USB mode switch connected to EM1-GIO_P01.
【J1】NTSC/Pal Output
【J2】AUDIO JACK (MIC IN)
【J3】AUDIO JACK (LINE OUT)
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User’s Manual
【SW20】
USB mode
CHAPTER
1.3.
1
0BINTRODUCTION
Power Supply
CAUTION:
The travel adapter is not recommended for AC/DC adapter use.
And should isolate from water and dust.
Switching AC/DC Adapter
Manufacture: UNIFIVE
Product Name: US300520
INPUT:AC100V-120V, AC100V-240V, 50/60Hz
OUTPUT:5V,2A
SAFETY:PSE-MARK,UL/CUL,CE,CB,BSMI
DIMENSION: L×W×H: 60×44×26.5 [mm]
Plug Type: 2 pin, IEC Technical Report 60083, JIS C 8303
(1) Input Side
26.5
17
60
44
Dimension is [mm].
(2) Output Side
Figure 1-6
AC/DC Adapter Image
CAUTION:
If you need to prepare other AC/DC adapter for un-match AC plug, your domestic regulation and so on,
please must buy same mechanical specification and feeder specification regarding DC side. Those are
EIAJ2 and OUTPUT: 5V-2A.
User’s Manual
21
CHAPTER
1.4.
1.4.1.
1
0BINTRODUCTION
Development Tools Connection
CPU Board ICE Interface [CN1]
Special Header; TET SICA20C20Y-GA102
Header; ARM 20Pin
ARM 20pin Header
Special Header
CPU board
ICE
SICA20C20Y-GA102
Figure 1-7
CPU Board ICE Interface
TETC
Tokyo Eletech Corporation
3-10 Akihabara, Taito-ku, Tokyo, 110-0006, Japan
Mail [email protected]
TEL +81-(0)3-5295-1661
FAX +81-(0)3-5295-1775
Web http://www.tetc.co.jp/e_enquete.htm
On Apr.2009
You can get information of "TETC SICA20C20Y-GA102" on TETC web page.
Please confirm that when you need a interface connector cable of "TETC SICA20C20Y-GA102" to ICE.
22
User’s Manual
CHAPTER
1.4.2.
1
0BINTRODUCTION
IO board Debug Interface [CN6], [CN9]
Debug interface is used 38 Mictor connector.
The interface is not included ETM trace signal as below pin assignment.
Header: Mictor connector
Figure 1-8
Debug Interface [CN6], [CN9]
User’s Manual
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CHAPTER
2.1.
1
0BINTRODUCTION
CHAPTER 2.
FUNCTIONS
Board Function Summary
Table 2-1
Board Function
Items
Contents
Board Structure
CPU Board + IO Board 、CPU Board works independently
CPU
EM1-S
Power LSI
Dialog DA9052
Memory
CPU Board
MobileDDR 1Gbit(128Mbyte)
eMMC NAND 4GByte
IO
Board
NOR Flash 256Mbit(32Mbyte)
Nand Flash (not mounted) 4Gbyte
CPU Board
LCD Direct Connect IF
Audio IF : Audio mini Jack - Line Out x1
USB IF: miniAB Connector x1.
MicroSD Card Slot x1
Debug I/F : mini JTAG IF(Special) - for ARM Only
USB IF for Console: miniB Connector x1 – Console IF (COM-Port)
IO Board
LCD (WVGA Size, Supports Touch Screen、Back light),
Audio IF: Audio mini Jack – MIC In x1, Line Out x1
TV Out(NTSC/PAL), LAN I/F(RJ45),
Debug I/F mictor type connector x1
General purpose Connector (for WLAN/BT/DTV/Camera Module),
ASYNC Expansion Connector x1、
CPU Board – IO Board Connector (EM Connector)
CPU Board
Switch x2, LEDs x 2 (for General purpose), Power LEDx1,
Dip Switch(Boot mode select, Debug enable ) ,
USB VBUS route select (Jumper)
IO
Board
Key switch(3x4 LCD side、side switch x2)
LEDs for General purpose x4、
Dip SW(ARM/DSP ICE selection)
Power
Source
DC Power supply +5V-2A (EIAJ2)
Li-Ion Battery (Connector Only)
USB VBUS power supply
Charge
function
Supports Li-Ion battery Charge by DC Power supply or USB VBUS
Interfaces
Button SW
LED etc.
Power
Case:
CPU Board PCB:
IO Board PCB:
<R>
Size
Quality Specs
24
Standards
Support
154 x 88 x 32mm approx.
55.6 x 70.0 mm typ.
140.0 x 70.0 mm typ.
RoHS(EU) Support
AC adapter: Electrical Appliance and Material Safety Law Support
(PSE-MARK,UL/CUL,CE,CB,BSMI)
User’s Manual
CHAPTER
2.2.
2.2.1.
2
1BFUNCTIONS
Parts Detail Descriptions
EMMA Mobile1-S (CPU LSI)
The EMMA Mobile1 is a multimedia processor for mobile applications and low power applications that integrates
a logic chip incorporating a CPU and DSP in one package.
・CPU: ARM1176JZF-S (Max. 500 MHz, I-cache: 32 KB, D-cache: 32 KB)
・DSP: SPXK701 (Max. 500 MHz, I-cache: 32 KB, D-cache: 32 KB)
・DMA controller
・Image processing
Image processor (resizing, filtering, etc.)
Image rotator (0 , 90 , 180 , 270)
Graphics DMA (ROP and FILL)
Image composer (LCD output image synthesis)
・H.264/MPEG-4 AVC accelerator
・Peripheral interfaces
Memory interface: External bus interface (16 bits: Flash memory, etc.), NAND interface
Serial interfaces: UART, I2C, audio/voice, SPI, IrDA
SD card interface (with SDIO)
Image-related interfaces: LCD interface, terrestrial digital TV interface (DTV)
ITU-R.BT656 interface (NTS)
General-purpose I/O interface
ULPI interface
・Package( 481-pin fine-pitch BGA package (12.7x12.7 mm))
2.2.2.
Power LSI (DA9052)
The DA9052 is a highly integrated PMIC subsystem with supply domain flexibility to support a wide range of
application processors, associated peripherals and user interface functions
・Switched DC/USB Charger with power path management
・4 Buck Converters ( 3 have DVS) 0.5V – 3.6V up to 1Amp
・10 Programmable LDO’s High PSRR, 1% accuracy
・Low power Backup Charger 1.1 – 3.1V up to 6mA
・32kHz RTC Oscillator
・General Purpose ADC with touch screen interface
・High voltage white LED driver 24V / 50mA Boost, 3 strings
・16bit GPIO bus for enhanced
・Wake up and peripheral control
・Dual serial control interfaces
・Unique USB supply detection and charge current selection
・Unique ID code capability via OTP memory
・Package(86LD UFNBA-QFN (7x7 mm))
2.2.3.
DDR-SDRAM (MT46H32M32LFCM-6)
The MTH32M32LFCM-6 Mobile is a Low-Power DDR SDRAM
・Cycle time ( 6 ns )
・32 Meg x 32 (8 Meg x 32 x 4 banks)
・Package(90-Ball VFBGA 10 x 13mm)
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CHAPTER
2.2.4.
2
1BFUNCTIONS
EMMC NAND Memory (MTFC4GDKDI-ET or KMCEG0000A)
EMMC NAND Memory is used as next two options on the board. And that is different by board revision.
The board information can be confirmed by 5.5 Board Revision and 5.6 Board Information in EEPROM. Please
refer to eMMC bit of EEPROM Address’s 0x10 for the revision recognizing of software view point.
The KMCEG0000A is a NAND Flash Memory and MMC in one package.
・Simple read/write memory using industry-standard MMC protocol 4.2 interface
・Common solution for embedded and external flash memory
・4G Byte Flash Memory
・Package(153-Ball FBGA 11.5x13mm)
・Low-cost embedded solution with MLC NAND
・Performance increase costs less
・Dual power supply
3.0V (2.7V ~ 3.3V) for MLC NAND Flash
1.8V/3.0V for I/O
・MMC4.1 or 4.2 interface
x1, x4, x8 bus & 26MHz, 52MHz
The MTFC4GDKDI is a NAND Flash Memory and MMC in one package.
・Isolated Multimedia Card (MMC) interface
・4G Byte Flash Memory
・Package(169-Ball FBGA 12 x 16mm)
(MMC Specification)
・MMC system specification version 4.2 MMC-mode-protocol-compliant
・Advanced 10-signal interface
・ x1, x4, and x8 I/Os, selectable by host
・MMC mode operation
・Command classes
Class0 (basic) Class 2 (block read) Class 4 (block write) Class 5 (erase) Class 6 (WRITE protection)
Class 7 (lock card)
・MMCplus™ and MMCmobile™ protocols
・Password protection
・Permanent and temporary write protect
・Supports basic file formats
・52 MHz clock speed (MAX)
・416 Mb/s data rate (MAX)
・Fully backward-compatible with previous MMC modes
・ECC and block management implemented
2.2.5.
NOR Flash Memory (PC28F256P30B85)
The PC28F256P30B85 is NumonyxTM StrataFlash® Embedded Memory(256MBit)
・100 ns initial access
・25 ns 16-word asynchronous-page read mode
・52 MHz with zero WAIT states
・Buffered Enhanced Factory Programming (BEFP) at 2.0 MByte/s (Typ) using 512-word buffer
1.8 V buffered programming at 1.5MByte/s
・Package(64-Ball Easy BGA 10 x 13mm)
2.2.6.
Ether (LAN9221)
The LAN9221 is a Highly-performance 16bit Non-PCI 10/100 Ethernet Controller
・Host bus interface (16bit data bus)
・1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling
・Integrated PHY with HP Auto-MDIX support
・Integrated checksum offload engine helps reduce CPU load
・Package(56-QFN 8 x 8mm)
・EEPROM interface for MAC address storage. LAN9221 can load the MAC address automatically after reset.
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CHAPTER
2.2.7.
2
1BFUNCTIONS
USB-PHY (ISP1504 or USB3329)
USB PHY is used as next two options on the board. And the USB phy is different by board revision.
The board information can be confirmed by 6.3 Board Revision and 6.4 Board Information in EEPROM. Please
refer to USB-PHY bit of EEPROM Address’s 0x10 for the revision recognizing of software view point.
The ISP1504 is USB 2.0 Transceiver as below:
・Universal Serial Bus Specification Rev. 2.0
・On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2
・UTMI+ Low Pin Interface (ULPI) Specification Rev 1.1
・Interfaces to host, peripheral and OTG device cores; optimized for portable devices or system ASICs with
built-in USB OTG device core
・Complete Hi-Speed USB physical front-end solution that supports high-speed(480 Mbit/s), full-speed (12 M
bit/s) and low-speed (1.5 M bit/s)
・Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP) and Session Request
Protocol (SRP)
・Highly optimized ULPI-compliant interface
(60 MHz, 8-bit interface between the core and the transceiver)
・Package(36balls TFBGA 3.5 x 3.5mm)
The USB3329 is USB 2.0 Transceiver as below:
・Highly integrated, Hi-Speed USB 2.0 transceivers
・Integrated VBus over-voltage protection (up to +30V)
・Integrated USB switch
・Internal ESD protection circuits
No external ESD protection circuits required
・Integrated 3.3V LDO regulator
・Ability to use the USB connector as single port of connection
・Switch Hi-Speed data, battery charging, and stereo/mono audio accessories
・UART mode
・Variable I/O voltage capability
・Low power and standby modes of operation to minimize power consumption
・Low jitter PLL makes it possible to accept "noisy" clock sources
・Supports commercial (0° to 70°C) and industrial (-40° to 85°C) temperature ranges
2.2.8.
COM-Port (FT232RQ)
The FT232RQ is a USB to serial UART interface
・Single chip USB to asynchronous serial data transfer interface.
・Entire USB protocol handled on the chip. No USB specific firmware programming required.
・Fully integrated 1024 bit EEPROM storing device descriptors and CBUS I/O configuration.
・Supports bus powered, self powered and high-power
・bus powered USB configurations.
・UART signal inversion option.
・UHCI/OHCI/EHCI host controller compatible.
・USB 2.0 Full Speed compatible.
・Package(32pin QFN 5 x 5mm)
2.2.9.
TV-OUT (ADV7179KCPZ)
The ADV7179 is a Video Encoder transfer to PAL/NTSC from ITU-R1 BT601/BT656 YCrCb
・10bit video DAC
・Multi standard video output (CVBS Y/C)
・Video input data port(CCIR-656 4:2:2、8bit parallel format)
・Composite, S video simultaneous output or RGB (SCART)/YUV video output can be set.
・2-wire MPU serial interface(I2C® interchangeability and Fast I2C)
・Package(40 pin LFCSP 6x 6mm)
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CHAPTER
2.2.10.
2
1BFUNCTIONS
Audio LSI (AK4648EC)
The AK4648 is a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and
Speaker-Amplifier.
・Recording Function
(4 Stereo Inputs Selector, Stereo MIC Input (Full-differential or Single-ended), Stereo Line Input,
MIC Amplifier, Digital ALC (Automatic Level Control), Wind-noise Reduction Filter,
Stereo Separation Emphasis, Programmable EQ)
・Playback Function
(Digital De-emphasis Filter, 5-Band Equalizer, Soft Mute, Digital Volume,
Digital ALC (Automatic Level Control), Stereo Separation Emphasis, Programmable EQ,
Stereo Line Output, Stereo Headphone-Amp, Stereo Speaker-Amp, Analog Mixing: 4 Stereo Input)
・μP I/F: I2C Bus (Ver. 1.0, 400 kHz Fast-Mode)
・Master/Slave mode
・ Audio Interface Format: MSB First, 2’s complement
(ADC: 16bit MSB justified, I2S, DSP Mode,
DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, DSP Mode)
・Package: (CSP 3.7mm x 3.8mm)
2.2.11.
NAND Flash Memory (K9F1G08U0A)
NOT MOUNTED on the board.
The K9F1G08U0A is a 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
・Memory Cell Array : (128M + 4,096K)bit x 8bit
Data Register: (2K + 64) bit x8bit Cache Register: (2K + 64) bit x8bit
・Automatic Program and Erase
Page Program : (2K + 64)Byte Block Erase : (128K + 4K)Byte
・Page Read Operation
Page Size: 2K-Byte Random Read: 25μs (Max.)
Serial Access: 30ns (Min.) -3.3v device 50ns (Min.) -1.8v device
・Fast Write Cycle Time Program time : 200μs(Typ.) Block Erase Time : 2ms(Typ.)
・Command/Address/Data Multiplexed I/O Port
・Package(48-pin TSOP 12x20mm)System Control
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User’s Manual
J4
J4
Figure 3-1
User’s Manual
J1
J1
MIC In
Line Out
Async
LCD
CN6
CN6
JTAG IF
Mictor Conn CN9
CN9
General CN5
Conn #1 CN5
U5
U5
NTSC Enc
Enc
NTSC
ADV7179
ADV7179
U9
U9
UART IF
IF
UART
ADM3202
ADM3202
U2
U2
Ether
Ether
Lan9221
Lan9221
(Pad Only)
128Mbyte
U10
U10
NAND Flash
Flash
NAND
K9F1G08U0A
K9F1G08U0A
3.7V
U4
U4
NOR Flash
Flash
NOR
PC28256P
PC28256P
NAND
IIC
NTSC
URT0
CS1
CS3
CS0
GPIOs
U11
U11
GPIO Expdr
Expdr
GPIO
MAX7324
MAX7324
AB0
ASYNC
Bus
Touch Panel & Back light Control
RGB
Control(SP0_CS1, GPIO)
SW16
4 LEDs
CPU/DSP 4 LEDs
Debug Sel.
3x4+2
To
3x4+2
DA9052
Buttons
Buttons
Camera IF, DTV IF, SP1, IIC, SD1,
URT2, PM1,GPIOs,
REFCLKO, 32.768KHz
Power SW x1
Side Switch x2
Power LED x1
General
CN4
Conn #0 CN4
Video Out
RCA Jack
J2
J2
J3
J3
CN3
CN3
T1
T1
SW15
5V
DSW1 SW2
Bootsel Debug
EN
IIC
IIC
Audio In/Out
U10
AB0
U10
Address
Address
Latch
Latch
CPU
Board
U1
U1
EM1-S
EM1-S
U22
U22
USB Phy
Phy
USB
USB3329
USB3329
U6
U6
Codec
Codec
AK4648EC
AK4648EC
U2
U2
PMIC
PMIC
D9052
D9052
U9
U9
eMMC
eMMC
4GByte
4GByte
U7
U7
M-DDR
M-DDR
1GBit
1GBit
LCD Out
GPIOs
JTAG
SD0
2
Audio mini Jack
Line Out
5V
Reset SW
General SW x2
General LED x2
SW
SW SW
SW
CN6
CN6
CN5
CN5
CN4
LCD Direct
Connector
CN1
Mini JTAG
(ARM Only)
CN2
Micro SD
Slot
USB Socket
Mini B
USB Socket
Mini AB
5V
U17
U17
USB SW
SW
JP1
USB
MAX1946
Host/Device Sel.
MAX1946
J1
J1
5V AC Adapter
3.7V Battery
5V USB
Button Switch x2
U18 SerialSerialU18
USB Conv.
Conv.
USB
FT232RQ
FT232RQ
URT0
USB
PM0
IIC
Pwr
Supply
SP0_
CS0
SD2
MEMIF
<R>
Audio
Mini Jack
RS232_URT0
(Pad only)
Ether IF
RJ45 Conn
Async IF
Conn
Battery IF
CN10
(Thru hole) CN10
DC Power IN
3.1.
IO Board
CHAPTER 3.
SYSTEM CONTROL
System Block Diagram
System Block Diagram
29
CHAPTER
3.2.
3
2BSYSTEM CONTROL
Memory Map
3.2.1.
All Memory Bank
0000_0000H
BANK
Description
BANK 0
NOR FLASH
BANK 1
NOR FLASH
EXTERNAL Device
BANK 2
EXTERNAL Device
BANK 3
DRAM
MEMC
BANK 4
APB Bus #0
PB0
BANK 5
Async Bus #1
AB1
BANK 6
AHB Slave
SWL 1
BANK 7
Reserved
BANK 8
Reserved
BANK 9
Reserved
BANK 10
Intern al SRAM
BANK 11
Reserved
BANK 12
APB1
BANK 13
Reserved
BANK 14
Reserved
BANK 15
Boot ROM
0FFF_FFFFH
1000_0000H
1FFF_FFFFH
2000_0000H
Target Module
AB0
2FFF_FFFFH
3000_0000H
3FFF_FFFFH
4000_0000H
4FFF_FFFFH
5000_0000H
5FFF_FFFFH
6000_0000H
6FFF_FFFFH
7000_0000H
7FFF_FFFFH
8000_0000H
8FFF_FFFFH
9000_0000H
9FFF_FFFFH
A000_0000H
AFFF_FFFFH
B000_0000H
SRC
BFFF_FFFFH
C000_0000H
PB1
(PMU)
CFFF_FFFFH
D000_0000H
DFFF_FFFFH
E000_0000H
EFFF_FFFFH
F000_0000H
AXL1
FFFF_FFFFH
Figure 3-2
30
EMMA Mobile1 ALL Memory Bank
User’s Manual
CHAPTER
3.2.2.
3
2BSYSTEM CONTROL
BANK 0/1/2
BANK 0/1/2: AB0 (NOR FLASH/External Device)
NOR (0000_0000H - 01FF_FFFFH)
Ether (2000_0000H - 20FF_FFFFH) example mapping
2 5 6 M b it
000 0_0000H
01F F_FFFFH
C S0
NOR
0FF F_FFFFH
100 0_0000H
1FF F_FFFFH
200 0_0000H
C S3
20F F_FFFFH
E th e r ( L A N 9 2 2 1 )
e x am p l e m a p p i n g
y o u c a n c h o o s e o th e r a d d r e s s
2FF F_FFFFH
Figure 3-3
EMMA Mobile1 NOR and Asynchronous Bus0 (No.0) Memory Map
User’s Manual
31
CHAPTER
3.2.3.
3
2BSYSTEM CONTROL
BANK3 DRAM AREA
BANK 3: MEMC(DRAM)
(3000_0000H - 37FF_FFFFH)
1Gbit
3000_0000H
CS0
37FF_FFFFH
3800_0000H
Reserved
3FFF_FFFFH
Figure 3-4
32
EMMA Mobile1 DRAM Memory Map
User’s Manual
User’s Manual
CN4
HOST
DEVICE
HOST
USB VBUS
CN55V
(+5V)
CN7
BT1
BT1
CN9
3.7V
VBAT
VLDO6
VDDOUT
VLDO10
VLDO9
VLDO8
VLDO7
OUT
IN
JP1 U17
USB Power SW
JP1 U17 USB Power SW
MAX1946
MAX1946
VDDCORE
ANODE1,2
CATHODE1,2
VBBAT
VBUS
VDD_LDO
VDD_LDO
1,3_4,5,7_8,
1-10,
9_10, etc
etc.
VLDO5
VLDO4
VLDO3
VLDO2
VLDO1
VBUCKPRO
VBUCKCORE
VBUCKMEM
VDD_LDO2,6
VBUS
VBAT
DCIN
VBUCKPERI
VA12
VA12
1.2V
1.2V
2.5V
1.8V
3.6V
3.3V
2.5V
2.5V
2.85V
3.1V
1.5V
2.85V
3.10V
2.85V
2.85V
V12
V12
1.2V
2.85V
VIO3
VDDOUT
LCD_3V
EXT_V12
EXT_V15
EXT_V285
EXT_V18
AUDIO_V3
EXT V12
EXT_V12
VIO18
VIO18
1.8V
2.0V
3.3V
m-DDR
U7
U1
Serial
Serial-USB
IF
U18
USB Phy
U16
Audio Codec
U6
LAN9221
3.3V
Other
Circuit
JTAG IF
U10
NAND Flash
(Not used)
RS232C IF
U9
NOR Flash
U4
Video Enc
U5
LAN Ctrl
U2
GPIO
Expander
U11
IF
CN4 Expansion
CN3 AB0 IF
CN2 LCD IF
CN7
2.85V CN6/9
CN6/9
1.8V
3.3V
K9F1GD8
3.3V
ADM3202
3.3V
1.8V
PC28F256
3.3V
ADV7179
1.8V(VDDVARIO )
NTS_VIO3
1.2V
1.5V
2.85V
1.8V
VDDOUT
CN4 LCD IF
Slot
CN2 SD
2.85V CN2 SD Slot
CN4
3.10V
1.8V Other
1.8V Circuit
2.85V
Other
2.5V
2.85V
2.5V Circuit
AK4648
AK4648
2.85V
2.85V
MTFC4GDK U9
eMMC
2.85V
MT46H32
1.8V
VIO3
VA1/2/3
V
EM1-S
VIO18
VCC
3.3V
FT232RQ
1.8V
ISP1504C
MAX7324
3.3V
Power System
Coin Battery
for RTC
PMIC
MON
CN10
J4
5V DC IN
NTS_V3
USB
VBUS
EXT_VIO3
NAND_V3
3
LCD
Back Light
Power
Battery
Power Input
From AC Adaptor
Power Input
U2
Power
U2 Power
Dialog
DA9052
CPU Board
IO Board
NAND_V3
EXT_VIO3
VIO18
3.3.
CPU Board
CHAPTER
2BSYSTEM CONTROL
Figure 3-5 Power System Architecture
33
34
250mA
-
VDDOUT
DC IN or
VBAT or
VBUS
TSREF
EXT_V18
VDDOUT
VDDCORE
VBUCKPRO
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
LDO9
LDO10
VDDOUT
VDDCORE
4
5
6
7
8
9
User’s Manual
10
11
12
13
14
15
16
EXT_V285
-
VDDOUT
VDDOUT
VDDOUT
VBUCKMEM
EXT_V15
NAND_V3
VDDOUT
VDDOUT
AUDIO_V3
LCD_3V
VDDOUT
2.85V
2.5V
200mA
100mA
-
2.85V
200mA
2.5V
3.6V
1.8V
1.5V
2.85V
3.1V
2.85V
1.2V
1.2V
1.2V
1.8V
150mA
150mA
100mA
200mA
100mA
700mA
40mA
700mA
Expansion Connector VDDOUT – CN4
NC
DA9052-ERR_RST_REQB
OTP IF – CN9
Expansion Connector 2.85V –CN4
AB0 Connector – CN3
ICE Connector – CN6, CN9
NC
Expansion Connector 1.8V –CN4
AB0 Connector – CN3
LCD(3.10V) :70mA – CN7
Expansion Connector 1.5V –CN4
AB0 Connector – CN3
K9F1G08 (NAND Flash)
NC
NC
NC
Expansion Connector 1.2V –CN4
AB0 Connector – CN3
LAN9221-IO(1.8V+/-10%)
LAN92217mA
PC28F256: NOR Flash
Other Circuits
NC
LAN9221-VDD33(3.3V +/- 300mV) 133mA
ADV7179 :NTSC(3.0-3.6V) 155mA
ADM3202: RS232C
Other Circuits (Key, LED, LAN IF Circuit )
Other LSI
of IO Board
DA9052 Power Circuits
FT232RQ(USB) :
Vcc: 4.0-5.25V, 15mA typ
NC
NC
NC
NC
NC
eMMC(2.7-3.6V) 85mA typ
SD Slot VDD
EM1S / VIO3 :100mA
Other Circuits
AK4648(2.6-3.6V) 25mA
LCD(3.10V) 70mA – CN4
NC
DA9052 Return
EM1S / VIO18
MDDR(1.7V) :70mA
ISP1504C:
Vcc:3.0~4.0V, 48mA typ
Other Circuits
EM1S / V :700mA
EM1S / V1, V2, V3
ISP1504:PSW_N line
Connected to:
Other LSI
CPU Board /
of CPU Board
Current value
3
VIO3
VBUCKMEM
VDDOUT
VBUCKMEM
VDDOUT
2.0V
3.3V
Set
Voltage
Table 3-1
EXT_V12
V12
VA12
VIO18
500mA
VBUCKCORE
VDDOUT
3
VBUCKMEM
500mA
VBUCKMEM
VDDOUT
Max
Current
2
EXT_VIO3
Input
Source
VBUCKPERI
Power LSI Power line
Source
Symbol
3.3.1.
1
No
CHAPTER
2BSYSTEM CONTROL
Power System Configuration
Power System Configuration
CHAPTER
3.3.2.
3
2BSYSTEM CONTROL
EM1-DA9052 Connection
U1
U2
DA9052
nIRQ
Y1
32KHz
Xtal
GPIO_2
XOUT/IN
OUT_32K
CN5
Interrupt nIRQ
USB_WAKEUP
32KHz Clock
EM1-S
GIO_P0
USB_WAKEUP/
USB_PWR_FAULT/
GIO_P1
C32K
Reset
ID
USB_ID
ACC_ID_DET/
GPIO_11
SYS_UP
DET1
nRESET
RESETB
USB
Connector
Control
SP0_CS0
IO Board
GPIO_1
SW20
USB_MODE_
SELECT
SI
SP0_SO
SO
SP0_SI
SK
SP0_CLK
nCS
SP0_CS0
VBUCKCORE
VBUCKMEM
VBUCKPRO
VDDOUT
VLDO1
VDD_LDO2,6
VDD_LDO1,3_4,5,
7_8,9_10
VLDO3
VIO18 1.8V
V12 1.2V
VA12 1.2V
VIO3 2.85V
VLDO2-10
VDDCORE
VBUCKPERI
Figure 3-6
VIO18
V
V1, V2, V3
V1O3
Other
Circuit
DA9052 – EM1 Connection
User’s Manual
35
CHAPTER
3.3.3.
2BSYSTEM CONTROL
Power down Control for Board device.
Table 3-2
36
3
Power down control for board devices
Device
Type
Name
Explanation
CPU &
Power LSI
EM1-S
Mobile DDR
MT46H32M32LF
eMMC
Audio Codec
MTFC4GDKDI
AK4648EC
USB Phy
ISP1504C
USB-Serial
Converter
NOR Flash
Video Encoder
FT232RQ
Combination of EM1-S and DA9052 is able to realize various power
down modes. For detail Information: EMMA Mobile1-S Data Sheet and
User’s Manual and DA9052 Data Sheet.
This device has DPD (Deep-Power down) mode. When EM1-S send
DPD command to MT46H32M32LF by way of memory interface, the
device enters to DPD mode. For detail information, Please see
MT46H32M32LF data sheet.
(No power down mode)
- Power source for AK4648 is separated from other power source
(Audio_V3). This power source line is controllable independently.
- Users can set AK4648 to power down mode by GPIO control
Set GIO_P9 to low : PDN pin of AK4648 will be activated and AK4648
will be set into power down mode.
- For detail information, Please see AK4648 Data Sheet.
Users can set AK4648 to power down mode by GPIO control:
-Set GIO_P47 to High: CS_N/PWRDN pin of AK4648 will be activated
and ISP1504C will be set into power down mode.
For detail information, Please see ISP1504C Data Sheet.
(No power down mode)
PC28F256P30B85
ADV7179
LAN Controller
LAN9221
NAND Flash
Other Devices
K9F1G08U0A
-
(No power down mode)
Users can reset ADV7179 when this device does not be used,
- Set SW17 “off” of IO Board Off
- Set SW17 “on” of IO Board and GIO_P8 set to reset (Low).
For Detail Information, Please see ADV7179 Data Sheet.
Users can reset LAN9221 by GPIO control
- Set GIO_P44 set to reset(Low)
For Detail Information, Please see LAN9221 Data Sheet.
(No power down mode)
User’s Manual
CHAPTER
3.3.4.
3
2BSYSTEM CONTROL
Power Supply Source
Design Kit Board has two options about power supply source.
The supply source is selected by JP1 physically. And SW20 on IO Board should set to find the status for software point of
view. Please also refer to 4.1.8 JUMPER [JP1] about JP1 and Table 3-15 IO Board Switches and LEDs (2) about SW20.
[JP1]
Table 3-3 CPU Board JUMPER [JP1]
SET
Setting
1-2
USB(HOST MODE)
2-3
USB(DEVICE MODE)
1: USB_SW (from MAX1946)
2: USB con. (from/to Mini-AB)
3: VBUS (to DA9052)
(1) USE CASE1: VBUS power supply
USB VBUS power supply can drive CPU board only.
(USB VBUS power cannot drive CPU board and IO board configuration.)
JP1 2-3 must be shorted.
[CN5] USB Mini AB
USB Power Supply 5V-500mA DC
Figure 3-7
CPU Board
(2) USE CASE2: AC adapter power supply
CPU Board and I/O Board configuration is supplied by AC adapter.
[J4] +5V IN
+5V AC adapter
DC 5V 2A (MAX)
Figure 3-8
CPU Board and I/O Board
User’s Manual
37
CHAPTER
3.3.5.
3
2BSYSTEM CONTROL
RTC Backup Battery
<R>
One coin battery is mounted on the board for power source of the RTC in DA9052. This coin battery is ML414, capacity is
1.2mAh. When the AC adapter or the Lithium ion battery is connected to this board, coin battery charge starts
automatically.
ML414 is Rechargeable Li-ion battery. The battery must avoid using till fully low voltage. When the Development Kit Board
is not used during long time, please detach the coin battery.
Please remove the battery when the coin battery performance has deteriorated.
ML414
Figure 3-9
38
Position of ML414
User’s Manual
Figure 3-10
User’s Manual
XTAL2
XTAL1
ISP1504C
DTV
IF
JTAG
IF
DTV_BCLK-SP2_CLK (Slave)
JT0_TCK
USBIF
NTSC
IF
USB_CLK
26.0MHz
32.768KHz
PLL1
PLL3
NTS_CLK-PM1_CLK(Slave)
SO DIMM[In]
CN7/8
27MHz
26.00
MHz
Y4
U16 USB Phy
OSCO
OSCI
FT232RQ
U18 Serial IF
EXT_OUT_32K
C32K
32.768KHz
PLL2
OSC
Div.
Div.
LCD_LCLK
Div.
Div.
Div.
EMMA Mobile1
Logic
Logic
SO DIMM
[Out]
CN7/8
CLK
MicroSD
Slot
CN2
AB0_CLK /
GIO_P11
EXT_OUT_32K
LCD_PXCLK
CAM_SCLK
REFCLKO
GIO_P11-WIFI2
DTV_BCLK-SP2_CLK
SP1_CLK
DTV_BCLK / SP2_CLK
SP1_CLK
NTS_CLK-PM1_CLK
JT0_RTCK
MTFC4G
DKDI
CLK
U9 eMMC
CK#
CK
MT46H32
M32
SP0_CLK(CS1)
DDR_CKM
DDR_CKP
JTAG
CN1
JT0_TCK/RTCK
U7 M-DDR
AUD_CLK MCKI
AK4648
U6 Codec
SK
SP0_CLK
NTS_CLK / PM1_CLK
JT0_RTCK
SD2_CKI
SD2_CKO
SD0_CKI
SD0_CKO
DDR_MCLKB
DDR_MCLK
LCD_PXCLK
CAM_SCLK
REFCLKO
SP0_CLK(CS0)
DA9052
3
12.00
MHz
OUT_32K
XOUT
XIN
OSC_12M_CKO
OSC_12M_CKI
U1
CPU Board Clock Tree Structure
Y3
32.768
KHz
Y2
DA9052
U2A Power
12.0MHz
12.0
MHz
3.4.1.
Y1
3.4.
U2B Power
CHAPTER
2BSYSTEM CONTROL
Clock System
Clock Source on CPU Board
39
CHAPTER
3.4.2.
3
2BSYSTEM CONTROL
IO Board Clock Tree Structure
JTAG
CN6
JT0_RTCK
SO DIMM
CN1/2[In/Out]
JT0_TCK
JT0_RTCK
JTAG
CN9
JT0_RTCK
JT0_TCK
JT0_TCK
NTS_CLK / PM1_CLK
NTS_CLK-PM1_CLK
SP0_CLK(CS0)
SP1_CLK
SP1_CLK
DTV_BCLK (SP2_CLK)
EXT_OUT_32K
GIO_P11-WIFI2 (AB0_CLK)
GIO_P11-WIFI2 (AB0_CLK)
REFCLKO
REFCLKO
CAM_SCLK
WiFi#1
CN4
CAM_SCLK
LCD_PXCLK
DTV_BCLK(SP2_CLK)
EXT_OUT_32K
LCD_PXCLK
SP0_CLK(CS0)
U5 Video Enc.
ADV7179
NTS_CLK -PM1_CLK
Y1
25.00
MHz
CLOCK
Y2
27.00
MHz
SW19
U2 Lan Ctrl.
LAN9221
XTAL1/CLKIN
XTAL2
27MHz
Figure 3-11
Clock Source on IO Board
・Nand Flash: Clock Signal Source corresponds to WE/RE Signal.
・NOR Flash: Clock Signal Source corresponds to AB WR/RD Signal.
40
WiFi#2
CN5
User’s Manual
LCD IF
CN7
CHAPTER
3.5.
3.5.1.
<R>
3
2BSYSTEM CONTROL
Reset System
Reset System Architecture
CPU Board
IO Board
VDDCORE
2.5V
U1
U2
Reset
Control
DA9052
EM1S
U21 Level Shifter
2.85V→1.8V
SN74AVC
1.8V
SP0_CS0
(NC)
ERR_RESET_
REQB
DET1
SYS_UP
U4 NOR Flash
PC28F256
RST
nShutdown
58
2.85V
A_RESETB
nRESET
RESET
Button
SW1
07
CN6/CN9
JTAG Connector
9 nSRESET
ICE_RESET
CN1
JTAG Connector
15
Figure 3-12
SW17
U5 Video Encoder
ADV7179
CN7 LCD IF
nRESET
GIO_P8-NTS_RESET
GIO_P49
nSRESET
IO Board
EM1-S
GIO_P46
ICE_RESET
Reset System Architecture
CPU Board
GIO_P44
nRESET_18
(NC)
nRESET
07
GIO_P8
CN3
AB0 Connector
nRESET_18
U2 Lan Ctrl
LAN9221
nRE SET
GIO_P46-LCD_RESET
GIO_P49-CAM_R ESETZ
Figure 3-13
6 LCD_RESET
CN4 Exp.Connector
18 CA M_RESETZ
GPIO Base Reset System for IO Board
User’s Manual
41
CHAPTER
3.6.
3
2BSYSTEM CONTROL
On Board Interrupts
U2
U1
EM1S
IO Board
DA9052
GIO_P0
USB_WAKEUP/
USB_PWR_FAULT/
GIO_P1
nIRQ
nIRQ
Key_Matrix,
Side Switch
GPIO_1
GIO_P1
KEY_IN0,
KEY_IN1,
KEY_IN2,
KEY_IN3
GPIO_8,9,10,12
CN2
GIO_P3
GIO_P3SD0_CD
A
SD Card
Slot
U2
LAN9221
GIO_P41
IRQ
GIO_P41-LAN_INT
CPU Board
GIO_P2-SD1_CD
GIO_P95
GIO_P11
GIO_P94
GIO_P37
GIO_P10
Figure 3-14
42
CN5
GIO_P2-SD1_CD
9
GIO_P95-WIFI1
20
GIO_P11-WIFI2
22
GIO_P94-WIFI3
24
GIO_P37-WIFI4
26
GIO_P10-WIFI5
28
IRQ Tree of EM1 Development Kit Board
User’s Manual
Expansion
Connector
CHAPTER
3.7.
3
2BSYSTEM CONTROL
GPIO
EM1, DA9052, and MAX7324 have GPIO. Each GPIO is described blow.
3.7.1.
EMMA Mobile1
Table 3-4 EM1 GPIO Settings
<R>
GIO_P0
Voltage[V]
(Note 2)
VIO3
in
Alternative
function
dedicated
GIO_P2
GIO_P3
VIO3
in
dedicated
Card Detect for SD1
VIO3
in
dedicated
Card Detect for SD0
GIO_P4
VIO3
out
NAND_RB1
CAMSTANDBY
GIO_P5
VIO3
out
NAND_RB2
CAM_SCLK
CAM_SCLK
GIO_P6
VIO3
out
NAND_RB3
NAND /WP
GIO_P8
VIO3
out
NAND_CE1
NTSC ADC7179 /RESET
GIO_P9
VIO3
out
NAND_CE2
Audio AK4648 PDN
GIO of EM1
I/O
Connected to
Board Revision
(Note 1)
D9052_nIRQ
GIO_P10
VIO3
in
NAND_CE3
WIFI5(SPI_INT to EM1)
GIO_P11
VIO18
out
AB0_CLK
WIFI2(BT_Wakeup)
GIO_P36
VIO18
in
AB0_A25
PushSW1
GIO_P37
VIO18
out
AB0_A26
WIFI4(WL_Wakeup)
GIO_P41
VIO18
in
AB0_WAIT
LAN 9221 IRQ
GIO_P44
VIO18
out
AB0_CSB2
LAN9221 RESET
GIO_P46
VIO18
out
AB0_BEN0
LCD_RESET
GIO_P47
VIO18
out
AB0_BEN1
GIO_P49
VIO3
out
SP0_CS2
CAM_RESETZ
GIO_P71
VIO18
in
LCD_ENABLE
PushSW2
GIO_P94
VIO3
out
PWM0
WIFI3(WL_RESET)
GIO_P95
VIO3
out
PWM1
WIFI1(BT_RESET)
ISP1507 CS_N/PWRDN
Revision 1
USB3329 RESETB
Revision 2
Note:
(1) Regarding Board revision, please refer to 5.5 Board Revision and 5.6 Board Information in EEPROM.
(2) VIO3 and VIO18 are depended on DA9052 programming. The concrete voltage can refer to 3.3.2 EM1-DA9052
Connection
GIO_P0
EM1
D9052 (Power IC)
VIO3
Active Low
nIRQ
GIO_P0
GIO_P0 is connected to DA9052 nIRQ which is open drain interface.
EM1 must receive the signal with an internal pull-up resistor and must set GIO_P0 as interrupt input.
User’s Manual
43
CHAPTER
44
3
2BSYSTEM CONTROL
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
User’s Manual
45
CHAPTER
46
3
2BSYSTEM CONTROL
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
User’s Manual
47
CHAPTER
3
2BSYSTEM CONTROL
GIO_P47 for Board revision 1 (*)
EM1
USB PHY (ISP1504)
GIO_P47
Low: Chip Select Active
High: Power Down mode
CS_N/
PWRDN
GIO_P47 for Board revision 2 (*)
EM1
GIO_P47
USB PHY (USB3329)
Active Low
RESETB
Note) Regarding Board revision, please refer to 5.5 Board Revision and 5.6 Board Information in EEPROM.
48
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
User’s Manual
49
CHAPTER
3.7.2.
3
2BSYSTEM CONTROL
DA9052
Table 3-5
50
Alternative function
DA9052 GPIO
DA9052
I/O
Selected function
Connected to
GPIO_0
out
ADCIN4
PAD
GPIO_1
in
ADCIN5
USB-mode DIPSW
GPIO_2
in
ADCIN6
GPIO_3
in
TSIYN
TSIYN
GPIO_4
in
TSIYP
TSIYP
LCD CN4-46 YU
GPIO_5
in
TSIXN
TSIXN
LCD CN4-43 XL
Board revision
USB_WAKEUP
LCD CN4-44 YD
GPIO_6
in
TSIXP
TSIXP
LCD CN4-45 XR
GPIO_7
in
TSREF
TSREF
DA9052 VLDO9
GPIO_8
in
SYS_EN
key_in0
GPIO_9
in
PWR_EN
key_in1
GPIO_10
in
PWR1_EN
GPIO_11
in
ACC_ID_DET
GPIO_12
in
GP_FB1
key_in2
ACC_ID_DET
USB ID for CN5
nVDD_FAULT
CN9-1pin
Revision 1
MAX1946 ON/OFF
Revision 2
key_in3
GPIO_13
out
nVDD_FAULT
GPIO_14
out
DATA
LED1
GPIO_15
out
CLK
LED2
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
User’s Manual
51
CHAPTER
52
3
2BSYSTEM CONTROL
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
GPIO13 for Board Revision 1 (*)
nVDD_FAULT (GPIO13)
D9052
CN9 for PMIC Mon
nVDD_FAULT/ 79
GPIO_13
1 pin
GPIO13 for Board Revision 2 (*)
GPIO13 (nVDD_FAULT)
D9052
CN9 for PMIC Mon
nVDD_FAULT/ 79
1 pin
GPIO_13
EXT_VIO3
R53
10k
MAX1946 USB SW
7
ON
Note) Regarding Board revision, please refer to 5.5 Board Revision and 5.6 Board Information in EEPROM.
User’s Manual
53
CHAPTER
3.7.3.
3
2BSYSTEM CONTROL
MAX7324
Table 3-6
MAX7324 GPIO
MAX7324 GPIO
I/O
connect to
initial condition
O8
out
key matrix
key_out0
High
O9
out
key matrix
key_out1
High
O10
out
key matrix
key_out2
High
O11
out
key matrix
key_out3
High
O12
out
LED1
High
O13
out
LED2
High
O14
out
LED3
High
O15
out
LED4
High
I0
in
TP16
internal 40k pull-up anytime
I1
in
TP17
internal 40k pull-up anytime
I2
in
TP18
internal 40k pull-up anytime
I3
in
TP19
internal 40k pull-up anytime
I4
in
TP20
internal 40k pull-up anytime
I5
in
TP21
internal 40k pull-up anytime
I6
in
TP22
internal 40k pull-up anytime
I7
in
TP23
internal 40k pull-up anytime
54
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
User’s Manual
55
CHAPTER
3.8.
3
2BSYSTEM CONTROL
Pin setting
3.8.1.
AB0
Register
CHG_PINSEL_G00
C014_0200H
bit
00b
01b
[31:30]
GIO_P15
AB0_AD3
01b
[29:28]
GIO_P14
AB0_AD2
01b
[27:26]
GIO_P13
AB0_AD1
01b
[25:24]
GIO_P12
AB0_AD0
[23:22]
GIO_P11
AB0_CLK
11b
set value
[21:20]
[19:18]
01b
NTS_CLK
00b
GIO_P10
NAND_CE3
00b
GIO_P9
NAND_CE2
00b
[17:16]
GIO_P8
NAND_CE1
00b
[15:14]
GIO_P7
NAND_CE0
10b
[13:12]
GIO_P6
NAND_RB3
00b
[11:10]
GIO_P5
NAND_RB2
00b
[9:8]
GIO_P4
NAND_RB1
00b
[7:6]
GIO_P3
[5:4]
GIO_P2
[3:2]
GIO_P1
[1:0]
GIO_P0
00b
00b
USB_WAKEUP
USB_PWR_FAULT
01b
00b
alternative pins
56
10b
User’s Manual
CHAPTER
Register
CHG_PINSEL_G16
C014_0204H
3
2BSYSTEM CONTROL
bit
00b
01b
10b
set value
[31:30]
GIO_P31
AB0_A20
[29:28]
GIO_P30
AB0_A19
NTS_DATA2
01b
01b
[27:26]
GIO_P29
AB0_A18
NTS_DATA1
01b
[25:24]
GIO_P28
AB0_A17
NTS_DATA0
01b
[23:22]
GIO_P27
AB0_AD15
01b
[21:20]
GIO_P26
AB0_AD14
01b
[19:18]
GIO_P25
AB0_AD13
01b
[17:16]
GIO_P24
AB0_AD12
01b
[15:14]
GIO_P23
AB0_AD11
01b
[13:12]
GIO_P22
AB0_AD10
01b
[11:10]
GIO_P21
AB0_AD9
01b
[9:8]
GIO_P20
AB0_AD8
01b
[7:6]
GIO_P19
AB0_AD7
01b
[5:4]
GIO_P18
AB0_AD6
01b
[3:2]
GIO_P17
AB0_AD5
01b
[1:0]
GIO_P16
AB0_AD4
01b
alternative pins list
Register
CHG_PINSEL_G32
C014_0208
bit
00b
01b
[31:30]
GIO_P47
AB0_BEN1
[29:28]
GIO_P46
AB0_BEN0
[27:26]
GIO_P45
AB0_CSB3
NTS_HS
[25:24]
GIO_P44
AB0_CSB2
NTS_VS
00b
[23:22]
GIO_P43
AB0_CSB1
NTS_DATA7
00b
[21:20]
GIO_P42
AB0_CSB0
NTS_DATA6
01b
[19:18]
GIO_P41
AB0_WAIT
NTS_DATA5
00b
[17:16]
GIO_P40
AB0_WRB
NTS_DATA4
01b
[15:14]
GIO_P39
AB0_RDB
NTS_DATA3
01b
[13:12]
GIO_P38
AB0_ADV
01b
[11:10]
GIO_P37
AB0_A26
00b
[9:8]
GIO_P36
AB0_A25
00b
[7:6]
GIO_P35
AB0_A24
01b
[5:4]
GIO_P34
AB0_A23
01b
[3:2]
GIO_P33
AB0_A22
01b
[1:0]
GIO_P32
AB0_A21
01b
User’s Manual
10b
set value
00b
00b
00b
57
CHAPTER
3.8.2.
3
2BSYSTEM CONTROL
PM0
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
58
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P95
PWM1
00b
[29:28]
GIO_P94
PWM0
00b
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
[7:6]
GIO_P83
IIC_SCL
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
01b
01b
01b
CHAPTER
3.8.3.
3
2BSYSTEM CONTROL
NTS,SP1
alternative pins list
Register
CHG_PINSEL_G64
C014_0210
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P79
NTS_DATA4
SP1_CS3
CAM_YUV4
01b
[29:28]
GIO_P78
NTS_DATA3
SP1_CS2
CAM_YUV3
01b
[27:26]
GIO_P77
NTS_DATA2
SP1_CS1
CAM_YUV2
01b
[25:24]
GIO_P76
NTS_DATA1
SP1_CS0
CAM_YUV1
01b
[23:22]
GIO_P75
NTS_DATA0
SP1_SO
CAM_YUV0
01b
[21:20]
GIO_P74
NTS_HS
SP1_SI
01b
[19:18]
GIO_P73
NTS_VS
SP1_CLK
01b
[17:16]
GIO_P72
NTS_CLK
[15:14]
GIO_P71
LCD_ENABLE
01b
[13:12]
GIO_P70
LCD_VSYNC
01b
[11:10]
GIO_P69
LCD_HSYNC
01b
[9:8]
GIO_P68
LCD_B5
01b
[7:6]
GIO_P67
LCD_B4
01b
[5:4]
GIO_P66
LCD_B3
01b
[3:2]
GIO_P65
LCD_B2
01b
[1:0]
GIO_P64
LCD_B1
01b
User’s Manual
PM1_CLK
01b
59
CHAPTER
3.8.4.
3
2BSYSTEM CONTROL
DTV,SP2
alternative pins list
Register
bit
00b
01b
DTV
SP2
10b
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_DTV
C014_0284
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
60
User’s Manual
00b
CHAPTER
3.8.5.
3
2BSYSTEM CONTROL
SP0,MMI
alternative pins list
Register
bit
00b
01b
SP0, GIO
MWI, CS
10b
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_SP0
C014_0280
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
User’s Manual
00b
61
CHAPTER
3.8.6.
3
2BSYSTEM CONTROL
LCDC
alternative pins list
Register
CHG_PINSEL_G48
C014_020C
62
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P63
LCD_B0
01b
[29:28]
GIO_P62
LCD_G5
01b
[27:26]
GIO_P61
LCD_G4
01b
[25:24]
GIO_P60
LCD_G3
01b
[23:22]
GIO_P59
LCD_G2
01b
[21:20]
GIO_P58
LCD_G1
01b
[19:18]
GIO_P57
LCD_G0
01b
[17:16]
GIO_P56
LCD_R5
01b
[15:14]
GIO_P55
LCD_R4
01b
[13:12]
GIO_P54
LCD_R3
01b
[11:10]
GIO_P53
LCD_R2
01b
[9:8]
GIO_P52
LCD_R1
01b
[7:6]
GIO_P51
LCD_R0
01b
[5:4]
GIO_P50
LCD_PXCLK
01b
[3:2]
GIO_P49
SP0_CS2
00b
[1:0]
GIO_P48
SP0_CS1
01b
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
CHG_PINSEL_G64
C014_0210
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P79
NTS_DATA4
SP1_CS3
CAM_YUV4
01b
[29:28]
GIO_P78
NTS_DATA3
SP1_CS2
CAM_YUV3
01b
[27:26]
GIO_P77
NTS_DATA2
SP1_CS1
CAM_YUV2
01b
[25:24]
GIO_P76
NTS_DATA1
SP1_CS0
CAM_YUV1
01b
[23:22]
GIO_P75
NTS_DATA0
SP1_SO
CAM_YUV0
01b
[21:20]
GIO_P74
NTS_HS
SP1_SI
[19:18]
GIO_P73
NTS_VS
SP1_CLK
[17:16]
GIO_P72
NTS_CLK
[15:14]
GIO_P71
LCD_ENABLE
01b
[13:12]
GIO_P70
LCD_VSYNC
01b
[11:10]
GIO_P69
LCD_HSYNC
01b
[9:8]
GIO_P68
LCD_B5
01b
[7:6]
GIO_P67
LCD_B4
01b
[5:4]
GIO_P66
LCD_B3
01b
[3:2]
GIO_P65
LCD_B2
01b
[1:0]
GIO_P64
LCD_B1
01b
User’s Manual
01b
01b
PM1_CLK
01b
63
CHAPTER
3.8.7.
3
2BSYSTEM CONTROL
IIC
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
64
bit
00b
01b
[31:30]
GIO_P95
PWM1
[29:28]
GIO_P94
PWM0
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
01b
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
01b
[7:6]
GIO_P83
IIC_SCL
01b
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
10b
11b
set value
00b
00b
CHAPTER
3.8.8.
3
2BSYSTEM CONTROL
URT0, URT1
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P95
PWM1
00b
[29:28]
GIO_P94
PWM0
00b
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
[7:6]
GIO_P83
IIC_SCL
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
01b
01b
01b
65
CHAPTER
3.8.9.
3
2BSYSTEM CONTROL
SD0
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
66
bit
00b
01b
[31:30]
GIO_P95
PWM1
[29:28]
GIO_P94
PWM0
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
01b
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
01b
[7:6]
GIO_P83
IIC_SCL
01b
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
10b
11b
set value
00b
00b
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
bit
00b
01b
SD0, GIO
SD0
10b
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_SD0
C014_0288
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
User’s Manual
00b
67
CHAPTER
3
2BSYSTEM CONTROL
3.8.10. SD1
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
68
bit
00b
01b
[31:30]
GIO_P95
PWM1
[29:28]
GIO_P94
PWM0
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
01b
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
01b
[7:6]
GIO_P83
IIC_SCL
01b
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
10b
11b
set value
00b
00b
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
bit
00b
01b
10b
SD1, GIO
SD1
CAM
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_SD1
C014_028C
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
User’s Manual
00b
69
CHAPTER
3
2BSYSTEM CONTROL
3.8.11. NAND, URT2, SD2, IIC
alternative pins list
Register
CHG_PINSEL_G00
C014_0200H
70
bit
00b
01b
[31:30]
GIO_P15
AB0_AD3
10b
11b
01b
set value
[29:28]
GIO_P14
AB0_AD2
01b
[27:26]
GIO_P13
AB0_AD1
01b
[25:24]
GIO_P12
AB0_AD0
[23:22]
GIO_P11
AB0_CLK
[21:20]
[19:18]
01b
NTS_CLK
00b
GIO_P10
NAND_CE3
00b
GIO_P9
NAND_CE2
00b
[17:16]
GIO_P8
NAND_CE1
00b
[15:14]
GIO_P7
NAND_CE0
10b
[13:12]
GIO_P6
NAND_RB3
00b
[11:10]
GIO_P5
NAND_RB2
00b
[9:8]
GIO_P4
NAND_RB1
00b
[7:6]
GIO_P3
[5:4]
GIO_P2
[3:2]
GIO_P1
[1:0]
GIO_P0
00b
00b
USB_WAKEUP
USB_PWR_FAULT
01b
00b
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
CHG_PINSEL_G96
C014_0218
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P111
URT2_RTSB
NAND_D1
10b
[29:28]
GIO_P110
URT2_CTSB
NAND_D0
10b
[27:26]
GIO_P109
URT2_SOUT
NAND_CLE
10b
[25:24]
GIO_P108
URT2_SRIN
NAND_ALE
10b
[23:22]
GIO_P107
USB_NXT
01b
[21:20]
GIO_P106
USB_STP
01b
[19:18]
GIO_P105
USB_DIR
01b
[17:16]
GIO_P104
USB_DATA7
01b
[15:14]
GIO_P103
USB_DATA6
01b
[13:12]
GIO_P102
USB_DATA5
01b
[11:10]
GIO_P101
USB_DATA4
01b
[9:8]
GIO_P100
USB_DATA3
01b
[7:6]
GIO_P99
USB_DATA2
01b
[5:4]
GIO_P98
USB_DATA1
01b
[3:2]
GIO_P97
USB_DATA0
01b
[1:0]
GIO_P96
USB_CLK
01b
alternative pins list
bit
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_G112 [17:16]
C014_021C
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
Register
00b
GIO_P119
GIO_P118
GIO_P117
GIO_P116
GIO_P115
GIO_P114
GIO_P113
GIO_P112
01b
SD2_DATA3
SD2_DATA2
SD2_DATA1
SD2_DATA0
SD2_CMD
SD2_CKO
User’s Manual
10b
NAND_D7
NAND_D6
NAND_D5
NAND_D4
NAND_D3
NAND_D2
11b
set value
00b
00b
00b
00b
00b
00b
00b
00b
00b
00b
01b
01b
01b
01b
01b
01b
71
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
bit
00b
01b
10b
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_IIC2
C014_0290
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
72
IIC2
NAND
User’s Manual
10b
CHAPTER
3
2BSYSTEM CONTROL
3.8.12. PWM
alternative pins list
Register
CHG_PINSEL_G80
C014_0214
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P95
PWM1
00b
[29:28]
GIO_P94
PWM0
00b
[27:26]
GIO_P93
SD2_CKI
NAND_OE
01b
[25:24]
GIO_P92
SD1_CKI
CAM_CLKI
01b
[23:22]
GIO_P91
SD0_CKI
01b
[21:20]
GIO_P90
SD0_DATA3
01b
[19:18]
GIO_P89
SD0_DATA2
01b
[17:16]
GIO_P88
SD0_DATA1
01b
[15:14]
GIO_P87
PM0_SI
[13:12]
GIO_P86
URT0_RTSB
URT1_SOUT
10b
[11:10]
GIO_P85
URT0_CTSB
URT1_SRIN
10b
[9:8]
GIO_P84
IIC_SDA
[7:6]
GIO_P83
IIC_SCL
[5:4]
GIO_P82
NTS_DATA7
PM1_SO
PM1_SO
01b
[3:2]
GIO_P81
NTS_DATA6
SP1_CS5
PM1_SI
01b
[1:0]
GIO_P80
NTS_DATA5
SP1_CS4
PM1_SEN
01b
User’s Manual
01b
01b
01b
73
CHAPTER
3
2BSYSTEM CONTROL
3.8.13. USB
alternative pins list
Register
CHG_PINSEL_G96
C014_0218
74
bit
00b
01b
10b
[31:30]
GIO_P111
URT2_RTSB
NAND_D1
10b
[29:28]
GIO_P110
URT2_CTSB
NAND_D0
10b
[27:26]
GIO_P109
URT2_SOUT
NAND_CLE
10b
[25:24]
GIO_P108
URT2_SRIN
NAND_ALE
10b
[23:22]
GIO_P107
USB_NXT
01b
[21:20]
GIO_P106
USB_STP
01b
[19:18]
GIO_P105
USB_DIR
01b
[17:16]
GIO_P104
USB_DATA7
01b
[15:14]
GIO_P103
USB_DATA6
01b
[13:12]
GIO_P102
USB_DATA5
01b
[11:10]
GIO_P101
USB_DATA4
01b
[9:8]
GIO_P100
USB_DATA3
01b
[7:6]
GIO_P99
USB_DATA2
01b
[5:4]
GIO_P98
USB_DATA1
01b
[3:2]
GIO_P97
USB_DATA0
01b
[1:0]
GIO_P96
USB_CLK
01b
User’s Manual
11b
set value
CHAPTER
3
2BSYSTEM CONTROL
alternative pins list
Register
CHG_PINSEL_G00
C014_0200H
bit
00b
01b
10b
11b
set value
[31:30]
GIO_P15
AB0_AD3
01b
[29:28]
GIO_P14
AB0_AD2
01b
[27:26]
GIO_P13
AB0_AD1
01b
[25:24]
GIO_P12
AB0_AD0
01b
[23:22]
GIO_P11
AB0_CLK
NTS_CLK
00b
[21:20]
GIO_P10
NAND_CE3
00b
[19:18]
GIO_P9
NAND_CE2
00b
[17:16]
GIO_P8
NAND_CE1
00b
[15:14]
GIO_P7
NAND_CE0
10b
[13:12]
GIO_P6
NAND_RB3
00b
[11:10]
GIO_P5
NAND_RB2
00b
[9:8]
GIO_P4
NAND_RB1
00b
[7:6]
GIO_P3
00b
[5:4]
GIO_P2
00b
[3:2]
GIO_P1
[1:0]
GIO_P0
USB_WAKEUP
USB_PWR_FAULT
01b
00b
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3.8.14. OSC, PLL2
alternative pins list
Register
bit
00b
01b
OSC12M_OUT
PLL2OUT
10b
11b
set value
[31:30]
[29:28]
[27:26]
[25:24]
[23:22]
[21:20]
[19:18]
CHG_PINSEL_REFCLKO
C014_0294
[17:16]
[15:14]
[13:12]
[11:10]
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
76
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00b
CHAPTER
3.9.
3
2BSYSTEM CONTROL
Chip Select
3.9.1.
EM1-S System Connection Architecture
<R>
Table 3-7
EM1 I/F
IO
Voltage
Board
EM1-S System Connection Architecture
Connected to:
PCM
PM0
PM1
VIO3
VIO3
CPU
IO
Codec LSI (AK4648)
Expansion Co nnector CN4/5 (NTSC IF Pin Multiplexed)
SPI
SP0(CS0)
VIO3
CPU
DA 9052 (For Control)
SP0(CS1)
SP0(CS2)
VIO3
-
IO
-
LCD (For LCD Panel Control)
Not Used
SP1
VIO3
IO
Expansion Co nnector CN4/5 (NTSC IF Pin Multiplexed)
SP2
VIO3
IO
Expansion Co nnector CN4/5 (DTV IF Pin Multiplexed)
DTV/DTV2
BT656
A B0
CS0
VIO3
VIO3
VIO18
IO
IO
IO
Expansion Co nnector CN4/5
NTSC Encoder → NTSC Out
NOR Flash
CS1
CS2
CS3
SD0
VIO18
VIO18
VIO18
VIO3
IO
IO
CPU
SD1
SD2
VIO3
VIO3
VIO18/VI
O3
VIO18
IO
CPU/IO
IO
CPU, IO
Expansion Co nnector CN4/5
eMMC / NAND PAD
NAND PAD
Mini-JTAG port o n CPU Board, JTAG port (Mictor type) on IO Board
CPU, IO
LCD Connector - Direct Connector on CPU Board,
LCD Panel connection on IO Board
SD
NAND
JTAG
LCD
IIC
USB
IIC
VIO18
VIO3
CPU
CPU
UART
IIC2
URT0
VIO3
VIO3
IO
CPU, IO
URT1
URT2
VIO3
VIO3
VIO3
VIO3
IO
-
VIO18
VIO18/VI
O3
IO
CPU, IO
PWM
uWire
Camera
GPIO
-
Not Used
AB0 Connector
Ether IF
microSD Card IF
USB Phy → USB mini A B Connector
Codec LSI(A K4648) on CPU Board, Expansion Co nnector CN4/5 on IO Board,
GPIO Expander on IO Board
NAND PAD
FT232(USB⇔Serial)Adaptation LSI on CPU Board, RS232_URT0 (IO Board)
Expansion Co nnector CN4/5 on IO Board
Not Used
NAND PAD
Not Used
Not Used
Expansion Co nnector CN4/5
(Please GPIO Spec Section)
Note: VIO3 and VIO18 are depended on DA9052 programming. The concrete voltage can refer to 3.3.2 EM1-DA9052
Connection
User’s Manual
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CHAPTER
3.9.2.
3
2BSYSTEM CONTROL
External Bus Chip Select (CSB0 to CSB3)
<R>
Table 3-8
CS
Number
CSB0
Voltage[V]
(Note 3)
VIO18
External Bus Chip Select (CSB0 to CSB3)
Board
Connected to
IO
NOR Flash
Wait Register
Address
AB0_CS0_WAITCTRL
AB0_CS0_WAITCTRLW
CSB1
VIO18
IO
CSB2
VIO18
IO
CSB3
VIO18
IO
Wait Value
0x02000502
(CSint=2, T2=0, T1=5, T0=2)
0x00010302
(T2_W=1, T1_W=3, T0_W=2)
(Not used, CN3)
Note1
(LAN9921 as
GIO_P44 ) Note2
Ether IF
(LAN9921)
AB0_CS3WAITCTRL
AB0_CS3WAITCTRL_W
0x01000300
(CSint=1, T2=0, T1=3, T0=0)
0x00000300
(T2_W=0, T1_W=3, T0_W=0)
Note:
(1) CSB1 is not used in Design Kit Board but is connected to CN3 of IO board for external board.
(2) CSB2 of chip select signal is not used but it is connected to LAN9921-nRESET as GIO_P44 of alternating pin function
(3) VIO18 is depended on DA9052 programming. The concrete voltage can refer to 3.3.2 EM1-DA9052 Connection
3.9.3.
SPI Chip Selects
<R>
Table 3-9
SPx Number
SP0(CS0)
SP0(CS1)
SP0(CS2)
SP1
SP2
Voltage [V]
(Note)
VIO3
VIO3
VIO3
VIO3
VIO3
Board
CPU
IO
IO
IO
SPI Chip Selects
Connection
DA9052 (For Control)
LCD(For LCD Panel Control)
(Not Used)
Expansion Connector CN5 (IO Board)
Expansion Connector CN4
(IO Board - Pin Multiplexed w/ DTVIF)
Note: VIO3 is depended on DA9052 programming. The concrete voltage can refer to 3.3.2 EM1-DA9052 Connection
78
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3.10. IIC Connection
Table 3-10
Device
AK4648
ADV7179
MAX7324
IIC Read / Write Address
Write Address (7bit*)
0x13 (0010011b)
0x2B (0101011b)
0x5D (1011101b)
Read Address (7bit*)
0x13 (0010011b)
0x2B (0101011b)
0x6D (1101101b)
Note) Write and Read address do not include R/W bit of 8bit's LSB.
U1
U4
EM1S
Audio Codec
AK4648
IIC_SCL
IIC_SDA
IIC_SCL
IIC_SDA
IIC2_SDL
IIC2_SDA
SCL
IO Board
IIC Address:
W=13h R=12h
R=13h
U10
SDA
NAND Flash (NMT)
K9F1A08U0A
IIC_SCL-NAND_WE
WE
IIC_SDA-NAND_RB0
R/B
U5 Video Encoder
IIC Address
ADV7179
W=56h R=57h
W=2Bh
R=2Bh
SCLOCK
IIC_SCL
IIC_SDA
SDATA
U11
CPU Board
GPIO Expander
MAX7324
SCL
IIC Address
W=5Dh
BAh R=6Dh
DBh
SDA
GPIOs
CN4
24
26
Figure 3-15
SCL
SDA
Expansion
Connector
Key Matrix,
Side SW,
LEDs
IIC Connection tree
User’s Manual
79
CHAPTER
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2BSYSTEM CONTROL
3.11. Dip Switches, Keys, LED Specs
This section describes Power switches, Reset button, Push switches, General Purpose Matrix Key-buttons, Side Switches,
and General Purpose LEDs. For DIP Switches, Please see Section x.x.
3.11.1. Button switches and LEDs on CPU Board
(1) Location
Please see 1.2.1: CPU Board Image.
(2) Specification
Table 3-11
Switch
&
LED
SW1
SW2
CPU Board Button Switches
Title
Type
GPIO
Assign
Board Reset
Button
Debug Switch
Push Type
-
Slide Type
-
Explanation
Push Down: Reset Activated.
For Details: Please See Reset System Section.
Changes Debug Mode
On: Debug Mode
Off: Normal Mode
ON
OFF 2
1
SW3
SW4
-
Multi Purpose
Switch
-
Push Type
-
EM1
GIO_P36
SW5
Multi Purpose
Switch
Push
Type
EM1
GIO_P71
LED1
Multi Purpose
LED
Multi Purpose
LED
Power
LED
Color:
Green
Color:
Green
Color:
Green
DA9052
GPIO_14
DA9052
GPIO_15
-
LED2
LED3
80
SW2
3
Fig. TOP View of SW2 (Debug On/OFF)
You Should set SW2 to “ON” when you connect debugger
ICE and use it.
(Not Used)
Free Push Button for users
Push Down: Activated.
For Detail Architecture: Please see 3.9.3
Free Push Button for uses
Push Down: Activated.
For Detail Architecture: Please see 3.9.3
Free LED for users
For Detail Architecture: Please see 3.9.3
Free LED for users
For Detail Architecture: Please see 3.9.3
Power Indicator – VDDOUT line
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
3.11.2. Key-buttons, Side Switches, LEDs on IO Board
(1) Location – Key Matrix switch & General Purpose LEDs
SW2
SW6
SW9
SW12
SW3
SW7
SW 10
SW13
LED1
LED2
LED3
SW4
Figure 3-16
SW8
SW 11
SW14
LED4
Top View of Key Matrix Switches and LEDs
(2) Location – Side Switches, other Switches
Please see 1.3.2 IO Board Image.
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3.11.3. IO Board Switches and LEDs
Table 3-12
Switch &
LEDs
SW1,5
IO Board Switches and LEDs (1)
Title
Type
Side
Switches
Push Type
SW2,3,4,
6,7,8,
9,,10,11,
12,13,14
SW15
Key Matrix
Switches
Push
Type
(MAX7324)
Power
Switch
-
-
DC IN (AC Adapter ) Power Switch
ON
OFF
SW16
Debug Target
Control
Switch
Slide Type
(DPDT)
-
Debug target switch: CPU or DSP
SW17
NTS LSI
Reset Switch
GPIO
Assign
(MAX7324)
Explanation
Free Push Button Switches for users
Push Down: Activated.
Detail Architecture: Please see 3.9.3
Free Push Button Switches for users
Push Down: Activated.
Detail Architecture: Please see 3.9.3
←
DSP
Debug
Slide Type
(SPDT)
EM1
GIO_8
→
CPU
Debug
This switch can change JTAG Signal assign to DSP or
CPU.
This switch can reset Video Encoder LSI ADV7179.
ON
1
2
OFF
3
ON: ADV7179 Reset is connected to EM1 GIO_P8
OFF: ADV7179 Reset is connected to GND
It can reduce useless current when NTSC/PAL function
does not be used.
SW18
-
-
-
(Not Used)
(Continues to next Page)
82
User’s Manual
CHAPTER
Table 3-13
Switch &
LEDs
SW19
Title
Type
NTS/PM1 Clock
Select
Slide Type
(SPDT)
3
2BSYSTEM CONTROL
IO Board Switches and LEDs (2)
GPIO
Assign
-
Explanation
This Switch set NTSC 27MHz Clock supply to EM1 or not.
ON
2
1
OFF
3
On: 27MHz Clock supply to EM1
OFF: 27MHz Clock not supply to EM1
This signal line is duplicated with PM1 Clock line
(NTS_CLK-PM1_CLK). So SW19 should set to OFF when
PM1 function is used.
For Detail architecture, Please see 3.4.2.
SW20
USB Mode
Select Switch
Slide Type
(SPDT)
DA9052
GIO_1
This switch sets USB Mode.
ON
1
2
OFF
3
On: USB IF is defined as DEVICE
OFF: USB IF is defined as HOST
LED
1,2, 3,4
LED5
Multi Purpose
LED
Power LED
Color:
Green
Color:
Green
(MAX7324)
Free LED for users
Detail Architecture: Please see 3.9.3
Power Indicator – VDDOUT line
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3.11.4. Boot Mode Switch (DSW1) on CPU Board
ON
1
ON
2
3
4
OFF
Example: SD Boot setting (ON/ON/OFF/ON)
Figure 3-17
Table 3-14
No
DSW1-2
DSW1-3
DSW1-4
1
2
3
4
5
6
7
8
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Table 3-15
No
DSW1-1
1
2
OFF
ON
BOOT_SEL3
Bit Setting
1
0
DSW1 Photo and Top view Image
DSW1 Boot Mode Switch Description (1)
BOOT_SEL[2:0]
Bit Setting
000b
001b
010b
011b
100b
101b
110b
111b
Description
NOR Boot
eMMC Boot
SD Boot
(Reserved)
NAND Boot
AB0 boot (ADSP JTAG)
eMMC Boot (ADSP JTAG)
SD Boot (ADSP JTAG)
DSW1 Boot Mode Switch Description (2)
Description
L_SPEED mode ON
L_SPEED mode OFF
For Detail Information for Change Boot mode register and its BOOT_SEL bit description: Please see EM1 1Chip Usert’s
Manual.
84
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3.11.5. General Purpose Key Buttons and LEDs System Architecture
(1) General Purpose Key Buttons System Architecture
EM1S
CPU Board
SW4
GIO_P36
SW5
GIO_P71
SP0_CS0 line
DA9052
SP0_CS0
GPIO_0 / ADCIN_4
GIO_0
IO Board
MAX7324
O11
O10
IIC
IIC
line
O9
O8
KEY_OUT3
KEY_OUT2
KEY_OUT1
KEY_OUT0
GPIO Expander
SW4
SW3
SW2
TP7
KEY_IN0
SW8
SW7
SW6
GPIO_8 / SYS_EN
TP8
KEY_IN1
SW11
SW10
SW9
GPIO_9 / PWR_EN
SW1
TP9
KEY_IN2
SW14
SW13
SW12
GPIO_10 / PWR1_EN
SW5
TP10
KEY_IN3
Key Matrix Switch
Figure 3-18
GPIO_12 / GP_FB1
Side Switch
Key Buttons and Side Switch System
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(2) General Purpose LEDs System Architecture
CPU Board
3.3V
DA9052
EM1S
SP0_CS0
line
DATA /
GPIO_14
LED1
CLK /
GPIO_15
LED2
IO Board
MAX7324
O15
IIC
IIC line
O14
O13
O12
3.3V
LED1 LED2
LED3
LED4
LED5
LED6
GPIO Expander
Figure 3-19
86
Key Buttons and Side Switch System
User’s Manual
LED3
LED4
CHAPTER
3
2BSYSTEM CONTROL
3.12. Audio LSI Connection
U6
U1
AK4648EC
AUDIO_V3
MIC_IN
EM1-S
IO Board
MPWR
CAD0
RIN1/IN1+
LIN_R
SDA
LIN1/IN1-
LIN_L
SCL
RIN2/IN2+
LINEOUT_R
LIN2/IN2-
LINEOUT_L
IIC
IIC_SDA
IIC_SCL
PM0
PM0_SO
SDTI
PM0_SI
SDTO
PM0_SEN
LRCK
PM0_CLK
BICK
GIO_P9
GIO_P9-AUDIO_PDN#
PDN
RIN3/VCOC
LIN3/MIN
IO Board
Audio IF
LOUT/LOP
LINEOUT_R
LINE_OUT
MCLKO
REFCLKO
REFCLKO
U2
LINEOUT_L
ROUT/LON
PAD
MUTET
CPU Board
Audio IF
MCLKI
AVDD
DA9052
VLDO4
2.85V 150mA
Audio_V3
Figure 3-20
TVDD
HVDD
DVDD
Audio IF Circuit Block Diagram
PDN: Power down mode: -H: Power Up, L: Power down. Reset and initialize the control register.
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3.13. Lan9221 Connection with EM1
Lan9221 connection with EM1 is as follows: FIFO_SEL pin on LAN9221 is connected to AB0_11.
U2
T1
LAN9221
AB_AD[0:15]
D[0:15]
AB_A[11], AB_A[1:24]
AB_A7
A7
AB_A6
A6
AB_A5
A4
AB_A3
A3
AB_A2
A2
AB_A1
A1
AB_A11
nCS
AB_RD
nRD
AB_WR
nWR
nRESET
IRQ
VIO18
AMDIX_EN
Figure 3-21
88
U3
FIFO_SEL
LAN_AB_CS3
GIO_P41-LAN_INT
line
A5
AB_A4
GIO_P44-LAN9221_RESET
LAN IF
RJ45
LAN I/F
Connector
LAN9221- AB0 Connection
User’s Manual
EEPROM
IF line
EEPROM
93AA46-I/MS
CHAPTER
3
2BSYSTEM CONTROL
3.14. Touch Screen I/F
CPU Board
U1
EM1S
U2
DA9052
CN5
TSIYN/GPIO_3
44
TSIYP/GPIO_4
SP0_CS0
line
46 YU
XL
43
XR
45
TSIXN/GPIO_5
TSIXP/GPIO_6
TSREF/GPIO_7
YD
LCD
Connector
TSREF
IO Board
CN7
44
YD
46 YU
XL
43
XR
45
Figure 3-22
LCD
Connector
LCD
Panel
Touch Screen Control System
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3.15. DDR Setting
BA0/BA1 signal connections are different by the board revision. The connections are two types as below.
Please refer to 5.5 Board Revision about how to recognize. And these connections also can recognize by DDR-BA01 bit
of EEPROM Address’s 0x10 of LAN IC on software point of view. Please refer to 5.6 Board Information in EEPROM.
EM1
Board Rev 1
EEPROM 0x10 DDR-BA01 bit 5: 0
DDR
BA0
BA0
BA1
BA1
BA0
BA0
BA1
BA1
EM1
Board Rev 2
EEPROM 0x10 DDR-BA01 bit 5: 1
DDR
MEMC registers in next table is recommendation setting value. Regarding MEMC_DDR_CONFIGC1, it is different
number related to Board revision. The EEPROM information can be confirmed by 5.6 Board Information in EEPROM.
MEMC_DDR_CONFIGT2
MEMC_CLK270_SEL
MEMC_DDR_CONFIGT1
MEMC_DDR_CONFIGF
MEMC_DDR_CONFIGA1
MEMC_DDR_CONFIGA2
MEMC_DDR_CONFIGC2
Address
0xC00A2024
0xC01101FC
0xC00A2020
0xC00A2000
0xC00A2004
0xC00A2008
0xC00A2010
MEMC_DDR_CONFIGC1
0xC00A200C
MEMC_DDR_CONFIGC2
MEMC_REQSCH
MEMC_DDR_CONFIGC2
MEMC_DDR_CONFIGR1
0xC00A2010
0xC00A1000
0xC00A2010
0xC00A2014
MEMC_DDR_CONFIGR2
0xC00A2018
MEMC_DDR_CONFIGR3
MEMC_CACHE_MODE
0xC00A201C
0xC00A0000
Data
0x14141414
0x00000000
0x000F0A03
0x0000000F
0x54443203
0x20DA1042
0x0000001D
0x40200033 (EEPROM 0x10 DDR-BA01 bit 5: 0)
0x80200033 (EEPROM 0x10 DDR-BA01 bit 5: 1)
0x00000018
0x0000001F
0x00000090
0x00690069
0x37771F1F(EEPROM 0x10 DDR bit3: 1)
0x37770101(EEPROM 0x10 DDR bit3: 0)
0x00001415
0x00000100
Next table shows a recommendation number about related CHG register with MEMC.
CHG_DRIVE0
90
Address
0xC0140400
Data
0xAAA002AA
User’s Manual
CHAPTER
3
2BSYSTEM CONTROL
3.16. SPI Interface
Development Kit board has SPI interface. The Chip select state can be confirmed at 3.9.3 SPI Chip Selects.
This section is described two notes as below.
- Maximum clock speed
Clock frequency of SPI interface is 14.28MHz maximum which is depend of a limit of DA9052 specification.
- PMIC DA9052 command order
DA9052 has two different of initial start-up by silicon revision. For common software, you need below.
Before SPI transmission between LCD panel and EM1, DA9052 shall supply LCD PS which is LDO5.
The register number is R54 and the value is 0x66. By the command, DA9052 LDO5 outputs 3.1V to LCD.
3.17. USB Interface
3.17.1. USB Switch for Host Mode
When you use USB Host mode, following switch and jumper switch must be set:
Board
Circuit Name
CPU
JP1
Setting
Note, refer to
USB Device: 2-3 short
4.1.8 JUMPER[JP1]
USB Host: 1-2 short
IO
SW20
USB Device: ON (1-2 short)
Table 3-13 IO Board
USB Host: : OFF (2-3 short)
Switches and LEDs (2)
The Development Kit Board has a switch of VBUS voltage output for Host mode. The switch is controlled from two LSI
depended on the board revision as below.
(1) Board revision: Rev1 (*)
The MAX1946 USB SW is controlled through ISP1504 USB PHY
ISP1504 USB PHY
PSW_N
D4
EXT_VIO3
R53
10k
MAX1946 USB SW
7
ON
(2) Board revision: Rev2 (*)
The MAX1946 USB SW is controlled through D9052 GPIO_13
GPIO13 (nVDD_FAULT)
D9052
CN9 for PMIC Mon
nVDD_FAULT/ 79
1 pin
GPIO_13
EXT_VIO3
R53
10k
MAX1946 USB SW
7
ON
Note) Regarding Board revision, please refer to 5.5 Board Revision and 5.6 Board Information in EEPROM.
User’s Manual
91
CHAPTER
3
2BSYSTEM CONTROL
3.17.2. USB Charger Detection
Development Kit Board can detect USB Charger connection at DA9052 from board revision 2 as below. Regarding
board revision, please refer to 5.5 Board Revision and 5.6 Board Information in EEPROM.
(1) Board revision 1
CN5
USB mini-AB Connector
U2
PMIC (DA9052)
U16
USB PHY (ISP1504)
D+
DP
NC
D+
D-
DM
NC
D-
(2) Board revision 2
CN5
USB mini-AB Connector
U16
USB PHY (USB3329)
U2
PMIC (DA9052)
D+
DP
SPK_R
D+
D-
DM
SPK_L
D-
Table 3-16
DA9052 Register USB Charger Detection Setting
DA9052
Bit
Type
LABEL
OTP Rev. and Value
Board revision
R62
6
R/W
CHG_USB_ILIM
0 (r0.4/r0.4 modified)
Revision 1
R62
6
R/W
CHG_USB_ILIM
1 (r0.9)
Revision 2
CHG_USB_ILIM is automatic USB charger type detection. This function enables to detect by hardware before EM1
software working. When EM1 software starts after USB charger detection by hardware, EM1 software is suggested
to set CHG_USB_ILIM=0 because the hardware detection of DA9052 is not needed on software working condition
.
92
User’s Manual
CHAPTER 4.
4.1.
4.1.1.
CPU Board Connectors
CCPU JTAG Connector [CN1]
Table 4-1
PIN
4.1.2.
CONNECTORS
SICA20C20Y-GA102
Signal
PIN
Signal
1
VIO3
11
JT0_RTCK
2
VIO3
12
N.C.
3
JT0_TRSRZ
13
JTO_TDO
4
GND
14
GND
5
JT0_TDI
15
ICE_RESET
6
GND
16
GND
7
JT0_TMS
17
N.C.
8
GND
18
GND
9
JT0_TCK
19
N.C.
10
GND
20
GND
SD Interface Connector [CN2]
Table 4-2
PIN
Signal
DM3AT-SF-PEJ
PIN
Signal
1
DAT2
8
DAT1
2
CD/DAT3
9
A
3
CMD
10
B
4
VDD
11
N.C.
5
CLK
12
N.C.
6
VSS
13
N.C.
7
DAT0
14
N.C.
User’s Manual
93
CHAPTER
4.1.3.
3BCONNECTORS
LCD Interface Connector [CN4]
Table 4-3
PIN
94
4
Signal
FH23-51S-0.3SHW(06)
PIN
Signal
1
GND
27
D20_R(GND)
2
VCC
28
D21_R(GND)
3
VCC
29
D22_R
4
VCC
30
D23_R
5
GND
31
D24_R
6
/RESET
32
D25_R
7
HSYNC
33
D26_R
8
VSYNC
34
D27_R
9
CLK
35
GND
10
GND
36
SCL
11
D00_B(GND)
37
SI
12
D01_B(GND)
38
SO
13
D02_B
39
/CS3
14
D03_B
40
VCOMIN
15
D04_B
41
VCCIO
16
D05_B
42
GND
17
D06_B
43
XL
18
D07_B
44
YD
19
D10_G(GND)
45
XR
20
D11_G(GND)
46
YU
21
D12_G
47
GND
22
D13_G
48
ANODE1
23
D14_G
49
CATHODE1
24
D15_G
50
ANODE2
25
D16_G
51
CATHODE2
26
D17_G
User’s Manual
CHAPTER
4.1.4.
4
USB Interface Connector [CN5]
Table 4-4
PIN
4.1.5.
3BCONNECTORS
Signal
56579-0579
PIN
Signal
1
VBUS
6
SHIELD
2
D-
7
SHIELD
3
D+
8
SHIELD
4
ID
9
SHIELD
5
GND
USB Interface (from UART) Connectors [CN6]
Table 4-5
PIN
Signal
UX60SA-MB-5ST
PIN
Signal
1
VBUS(N.C.)
6
SHIELD
2
D-
7
SHIELD
3
D+
8
SHIELD
4
ID(N.C.)
9
SHIELD
5
GND
User’s Manual
95
CHAPTER
4.1.6.
4
Peripheral Connector [CN7] [CN8]
Table 4-6
PIN
3BCONNECTORS
Signal
PIN
Signal
SO DIMM[CN7]
PIN
Signal
URT2 CTSB-NAND D0
PIN
121
Signal
1
VBAT
41
GND
81
EXT V12
2
VBAT
42
GND
82
URT2 RTSB-NAND D1
122
EXT V12
3
VBAT
43
GND
83
NAND D2
123
EXT V12
4
VBAT
44
GND
84
NAND D3
124
EXT V12
5
VBAT
45
AB AD0
85
NAND D4
125
EXT V15
6
VBAT
46
AB AD1
86
NAND D5
126
EXT V15
7
N.C.
47
AB AD2
87
NAND D6
127
EXT V15
8
N.C.
48
AB AD3
88
NAND D7
128
EXT V15
9
AB A1
49
AB AD4
89
GND
129
EXT V18
10
AB A2
50
AB AD5
90
GND
130
EXT V18
11
AB A3
51
AB AD6
91
NAND OE
131
EXT V18
12
AB A4
52
AB AD7
92
IIC2 SCL-NAND WE
132
EXT V18
13
AB A5
53
GND
93
IIC2 SCL-NAND RB0
133
EXT V285
14
AB A6
54
GND
94
GIO P7-NAND CE0#
134
EXT V285
15
AB A7
55
GND
95
URT2 SRIN-NAND ALE
135
EXT V285
16
AB A8
56
GND
96
URT2 SOUT-NAND CLE
136
EXT V285
17
GND
57
AB AD8
97
GIO P6-NAND WP#
137
VDDOUT
18
GND
58
AB AD9
98
GND
138
VDDOUT
19
GND
59
AB AD10
99
GND
139
VDDOUT
20
GND
60
AB AD11
100
GND
140
VDDOUT
21
AB A9
61
AB AD12
101
KEY IN0
141
LCD 3V
22
AB A10
62
AB AD13
102
KEY IN1
142
LCD 3V
23
AB A11
63
AB AD14
103
KEY IN2
143
LCD 3V
24
AB A12
64
AB AD15
104
KEY IN3
144
LCD 3V
25
AB A13
65
GND
105
GND
145
+5V
26
AB A14
66
GND
106
GND
146
+5V
27
AB A15
67
GND
107
GND
147
+5V
28
AB A16
68
GND
108
GND
148
+5V
29
GND
69
NOR AB CS0
109
EXT VIO3
149
+5V
30
GND
70
LAN AB CS3
110
EXT VIO3
150
+5V
31
GND
71
EXT AB CS1
111
EXT VIO3
32
GND
72
AB WR
112
EXT VIO3
33
AB A17
73
AB RD
113
VIO18
34
AB A18
74
AB ADV
114
VIO18
35
AB A19
75
GND
115
VIO18
36
AB A20
76
GND
116
VIO18
37
AB A21
77
nRESET
117
NAND V3
38
AB A22
78
nRESET 18
118
NAND V3
39
AB A23
79
GND
119
NAND V3
40
AB A24
80
GND
120
NAND V3
96
User’s Manual
CHAPTER
4
Table 4-7
PIN
1
Signal
GND
PIN
41
Signal
LCD G5
PIN
81
3BCONNECTORS
SO DIMM[CN8]
Signal
EXT URT0 SRIN
PIN
121
Signal
GIO P4-CAM STBY
2
GND
42
LCD G4
82
URT0 SOUT
122
GIO P49-CAM RESETZ
3
GND
43
GND
83
URT1 SRIN
123
CAM SCLK
4
GND
44
GND
84
URT1 SOUT
124
SD1 CKI CAM CLKI
5
YD
45
LCD R1
85
GND
125
SD1 DATA3-CAM HS
6
YU
46
LCD R0
86
GND
126
SD1 DATA2-CAM VS
7
XL
47
LCD R3
87
GIO P44-LAN9221 R
127
GND
8
XR
48
LCD R2
88
GIO P41-LAN INT
128
GND
9
GND
49
LCD R5
89
GND
129
SD1 DATA1-CAM YUV7
10
GND
50
LCD R4
90
GND
130
SD1 DATA0-CAM YUV6
11
LED CATHODE1
51
GND
91
NTS DATA5-PM1 SE
131
SD1 CMD-CAM YUV5
12
LED CATHODE2
52
GND
92
NTS DATA6-PM1 SI
132
SD1 DATA4-CAM YUV4
13
GIO P71-SW2
53
GND
93
NTS DATA7-PM1 SO
133
NTS DATA3-CAM YUV3
14
LED ANODE
54
GND
94
NTS CLK-PM1 CLK
134
NTS DATA2-SP1 CS1-
15
GND
55
GND
95
GND
135
NTS DATA1-CAM YUV1
16
GND
56
GND
96
GND
136
NTS DATA0-SP1 SO-C
17
SP0 SI 18
57
N.C.
97
GND
137
AGND
18
SP0 CS1 18
58
N.C.
98
GIO P10-WFI5
138
AGND
19
SP0 CLK 18
59
IIC SDA
99
GIO P10-WFI4
139
AGND
20
SP0 SO 18
60
IIC SCL
100
GIO P10-WFI3
140
MPWR
21
GND
61
GND
101
GIO P10-WFI2
141
LIN1
22
GND
62
GND
102
GIO P10-WFI1
142
RIN1
23
LCD HSYNC
63
GND
103
GND
143
LINEOUT L
24
LCD VSYNC
64
ICE RESET
104
GND
144
LINEOUT R
25
GIO P46-LCD R
65
GND
105
GIO P2-SD1 CD
145
AGND
26
LCD PXCLK2
66
GND
106
SD1 CKO
146
AGND
27
GND
67
JT0 RTCK
107
NTS VS-SP1 CLK
147
GND
28
GND
68
JT0 TRSTZ
108
NTS HS-SP1 SI
148
TBAT
29
LCD B1
69
JT0 TMS
109
GND
149
GND
30
LCD B0
70
JT0 TDI
110
GND
150
GND
31
LCD B3
71
JT0 TDO
111
EXT-OUT 32K
32
LCD B2
72
JT0 TCK
112
REFCLKO
33
LCD B5
73
GND
113
GND
34
LCD B4
74
GND
114
GND
35
GND
75
USB MODE-
115
DTV DATA
36
GND
76
D9052 GPIO
116
DTV BCLK
37
LCD G1
77
GND
117
DTV VLD
38
LCD G0
78
GND
118
DTV PSYNC
39
LCD G3
79
GND
119
GND
40
LCD G2
80
GIO P8-NTS
120
GND
User’s Manual
97
CHAPTER
4.1.7.
4
3BCONNECTORS
Power LSI (D9052) Monitor [CN9]
Pin 1 signal is different by the board revision. The connection is two types as below. Regarding Board Revision, please
refer to 5.5 Board Revision.
Table 4-8
PIN
1
4.1.8.
BM07B-SRSS-TB
Signal
Board revision
nVDD Fault
Rev 1
PSW_N
Rev 2
2
VBAT
3
VDDCORE
4
D9052_DATA
5
D9052_CLK
6
TP
7
GND
JUMPER [JP1]
Table 4-9
XJ3B-0311
SET
Setting
1-2
USB(HOST MODE)
2-3
USB(DEVICE MODE)
[JP1]
1: USB_SW (from MAX1946)
2: USB con. (from/to Mini-AB)
3: VBUS (to DA9052)
A photo of DEVICE Mode (2-3 set)
98
User’s Manual
CHAPTER
4.2.
4.2.1.
4
IO board Connectors
CPU Daughter Board Connectors [CN1, CN2]
Table 4-10
PIN
1
3BCONNECTORS
Signal
PIN
Signal
SO DIMM[CN1]
PIN
Signal
PIN
Signal
GND
41
LCD G5
81
EXT URT0 SRIN
121
GIO P4-CAM STBY
2
GND
42
LCD G4
82
URT0 SOUT
122
GIO P49-CAM RESETZ
3
GND
43
GND
83
URT1 SRIN
123
CAM SCLK
4
GND
44
GND
84
URT1 SOUT
124
SD1 CKI CAM CLKI
5
YD
45
LCD R1
85
GND
125
SD1 DATA3-CAM HS
6
YU
46
LCD R0
86
GND
126
SD1 DATA2-CAM VS
7
XL
47
LCD R3
87
GIO P44-LAN9221 R
127
GND
8
XR
48
LCD R2
88
GIO P41-LAN INT
128
GND
9
GND
49
LCD R5
89
GND
129
SD1 DATA1-CAM YUV7
10
GND
50
LCD R4
90
GND
130
SD1 DATA0-CAM YUV6
11
LED CATHODE1
51
GND
91
NTS DATA5-PM1 SE
131
SD1 CMD-CAM YUV5
12
LED CATHODE2
52
GND
92
NTS DATA6-PM1 SI
132
SD1 DATA4-CAM YUV4
13
GIO P71-SW2
53
GND
93
NTS DATA7-PM1 SO
133
NTS DATA3-CAM YUV3
14
LED ANODE
54
GND
94
NTS CLK-PM1 CLK
134
NTS DATA2-SP1 CS1-CA
15
GND
55
GND
95
GND
135
NTS DATA1-CAM YUV1
16
GND
56
GND
96
GND
136
NTS DATA0-SP1 SO-CA
17
SP0 SI 18
57
N.C.
97
GND
137
AGND
18
SP0 CS1 18
58
N.C.
98
GIO P10-WFI5
138
AGND
19
SP0 CLK 18
59
IIC SDA
99
GIO P10-WFI4
139
AGND
20
SP0 SO 18
60
IIC SCL
100
GIO P10-WFI3
140
MPWR
21
GND
61
GND
101
GIO P10-WFI2
141
LIN1
22
GND
62
GND
102
GIO P10-WFI1
142
RIN1
23
LCD HSYNC
63
GND
103
GND
143
LINEOUT L
24
LCD VSYNC
64
ICE RESET
104
GND
144
LINEOUT R
25
GIO P46-LCD R
65
GND
105
GIO P2-SD1 CD
145
AGND
26
LCD PXCLK2
66
GND
106
SD1 CKO
146
AGND
27
GND
67
JT0 RTCK
107
NTS VS-SP1 CLK
147
GND
28
GND
68
JT0 TRSTZ
108
NTS HS-SP1 SI
148
TBAT
29
LCD B1
69
JT0 TMS
109
GND
149
GND
30
LCD B0
70
JT0 TDI
110
GND
150
GND
31
LCD B3
71
JT0 TDO
111
EXT-OUT 32K
32
LCD B2
72
JT0 TCK
112
REFCLKO
33
LCD B5
73
GND
113
GND
34
LCD B4
74
GND
114
GND
35
GND
75
USB MODE-
115
DTV DATA
36
GND
76
D9052 GPIO
116
DTV BCLK
37
LCD G1
77
GND
117
DTV VLD
38
LCD G0
78
GND
118
DTV PSYNC
39
LCD G3
79
GND
119
GND
40
LCD G2
80
GIO P8-NTS
120
GND
User’s Manual
99
CHAPTER
4
Table 4-11
PIN
Signal
PIN
Signal
3BCONNECTORS
SO DIMM[CN2]
PIN
Signal
PIN
Signal
1
VBAT
41
GND
81
URT2 CTSB-NAND D0
121
EXT V12
2
VBAT
42
GND
82
URT2 RTSB-NAND D1
122
EXT V12
3
VBAT
43
GND
83
NAND D2
123
EXT V12
4
VBAT
44
GND
84
NAND D3
124
EXT V12
5
VBAT
45
AB AD0
85
NAND D4
125
EXT V15
6
VBAT
46
AB AD1
86
NAND D5
126
EXT V15
7
N.C.
47
AB AD2
87
NAND D6
127
EXT V15
8
N.C.
48
AB AD3
88
NAND D7
128
EXT V15
9
AB A1
49
AB AD4
89
GND
129
EXT V18
10
AB A2
50
AB AD5
90
GND
130
EXT V18
11
AB A3
51
AB AD6
91
NAND OE
131
EXT V18
12
AB A4
52
AB AD7
92
IIC2 SCL-NAND WE
132
EXT V18
13
AB A5
53
GND
93
IIC2 SCL-NAND RB0
133
EXT V285
14
AB A6
54
GND
94
GIO P7-NAND CE0#
134
EXT V285
15
AB A7
55
GND
95
URT2 SRIN-NAND ALE
135
EXT V285
16
AB A8
56
GND
96
URT2 SOUT-NAND CLE
136
EXT V285
17
GND
57
AB AD8
97
GIO P6-NAND WP#
137
VDDOUT
18
GND
58
AB AD9
98
GND
138
VDDOUT
19
GND
59
AB AD10
99
GND
139
VDDOUT
20
GND
60
AB AD11
100
GND
140
VDDOUT
21
AB A9
61
AB AD12
101
KEY IN0
141
LCD 3V
22
AB A10
62
AB AD13
102
KEY IN1
142
LCD 3V
23
AB A11
63
AB AD14
103
KEY IN2
143
LCD 3V
24
AB A12
64
AB AD15
104
KEY IN3
144
LCD 3V
25
AB A13
65
GND
105
GND
145
+5V
26
AB A14
66
GND
106
GND
146
+5V
27
AB A15
67
GND
107
GND
147
+5V
28
AB A16
68
GND
108
GND
148
+5V
29
GND
69
NOR AB CS0
109
EXT VIO3
149
+5V
30
GND
70
LAN AB CS3
110
EXT VIO3
150
+5V
31
GND
71
EXT AB CS1
111
EXT VIO3
32
GND
72
AB WR
112
EXT VIO3
33
AB A17
73
AB RD
113
VIO18
34
AB A18
74
AB ADV
114
VIO18
35
AB A19
75
GND
115
VIO18
36
AB A20
76
GND
116
VIO18
37
AB A21
77
nRESET
117
NAND V3
38
AB A22
78
nRESET 18
118
NAND V3
39
AB A23
79
GND
119
NAND V3
40
AB A24
80
GND
120
NAND V3
100
User’s Manual
CHAPTER
4.2.2.
4
3BCONNECTORS
AB0 external [CN3]
Table 4-12
DF17(4.0)-60DS-0.5V(57)
PIN
Signal
PIN
Signal
PIN
Signal
1
EXT_V18
21
AB_A15
41
AB_AD6
2
EXT_V18
22
AB_A16
42
AB_AD7
3
EXT_V285
23
GND
43
GND
4
EXT_V285
24
GND
44
GND
5
AB_A1
25
AB_A17
45
AB_AD8
6
AB_A2
26
AB_A18
46
AB_AD9
7
AB_A3
27
AB_A19
47
AB_AD10
8
AB_A4
28
AB_A20
48
AB_AD11
9
AB_A5
29
AB_A21
49
AB_AD12
10
AB_A6
30
AB_A22
50
AB_AD13
11
AB_A7
31
AB_A23
51
AB_AD14
12
AB_A8
32
AB_A24
52
AB_AD15
13
GND
33
GND
53
NOR_AB_CS0
14
GND
34
GND
54
GND
15
AB_A9
35
AB_AD0
55
EXT_AB_CS1
16
AB_A10
36
AB_AD1
56
AB_RD
17
AB_A11
37
AB_AD2
57
AB_WR
18
AB_A12
38
AB_AD3
58
nRESET_18
19
AB_A13
39
AB_AD4
59
GND
20
AB_A14
40
AB_AD5
60
GND
User’s Manual
101
CHAPTER
4.2.3.
4
3BCONNECTORS
Enhanced Connector [CN4]
Table 4-13
PIN
Signal
1
GND
2
CAM_YUV1
3
GND
4
CAM_YUV3
5
CAM_YUV4
6
PIN
DF17(4.0)-40DS-0.5V(57)
Signal
PIN
Signal
PIN
Signal
11
GND
21
DTV_VLD
31
EXT_V285
12
GND
22
GND
32
GND
13
CAM_SCLK
23
DTV_PSYNC
33
EXT_V18
(Note)
14
GND
24
IIC_SDA
34
EXT_V15
(Note)
15
GND
25
GND
35
EXT_V18
GND
16
GND
26
IIC_SCL
36
VDDOUT
7
GND
17
DTV_DATA
27
DTV_BCLK
37
EXT_V12
8
GND
18
GIO_P49-CAM_RESETZ
28
GND
38
VDDOUT
9
GND
19
GND
29
GND
39
EXT_V12
10
GND
20
GIO_P4-CAM_STBY
30
REFCLKO
40
GND
(Note)
<R>
Note) these signals are not connected to CN4 on default state IO board because the signal is alternate pin with NTS signal.
For connection you need resistor mount to IO board. Regarding the modification, please refer to Modification for signals in
external connector [CN4/CN5].
4.2.4.
Enhanced Connector [CN5]
Table 4-14
PIN
Signal
PIN
DF17(4.0)-40DS-0.5V(57)
Signal
PIN
Signal
PIN
Signal
1
EXT-OUT_32K
11
SD1_DATA0-CAM_YUV6
21
UART2_SRIN
31
GND
2
GND
12
SP1_CS1-CAM_YUV2
22
GIO_P11_WIFI2
32
NTS_CLK-PM1_CLK
(Note)
3
SD1_CKI-CAM_CLKI
13
SD1_DATA1-CAM_YUV7
23
GND
33
UART2_RTSB
4
SP1_SI (Note)
14
GND
24
GIO_P94_WIFI3
34
GND
5
SD1_CKO
15
SD1_DATA2-CAM_VS
25
UART2_SOUT
35
GND
6
GND
16
SP1_CLK (Note)
26
GIO_P37_WIFI4
36
PM1_SI
7
SD1_CMD-CAM_YUV5
17
SD1_DATA3-CAM_HS
27
GND
37
PM1_SEN (Note)
8
SP1_SO-CAM_YUV0
18
GND
28
GIO_P10_WIFI5
38
GND
(Note)
(Note)
9
GIO_P2-SD1_CD
19
GND
29
UART2_CTSB
39
GND
10
GND
20
GIO_P95_WIFI1
30
GND
40
PM1_SO
(Note)
<R>
Note) these signals are not connected to CN5 on default state IO board because the signal is alternate pin with NTSC
signal. For connection you need resistor mount to IO board. Regarding the modification, please refer to Modification for
signals in external connector [CN4/CN5]
102
User’s Manual
CHAPTER
4.2.5.
4
Debugger [CN6] [CN9]
Table 4-15
PIN
3BCONNECTORS
Signal
PIN
Signal
2-5767004-2
PIN
Signal
PIN
Signal
1
(N.C.)
11
TDO
21
nTRST
31
GND
2
(N.C.)
12
Vref
22
GND
32
GND
3
(N.C.)
13
RTCK
23
GND
33
GND
4
(N.C.)
14
Vcc
24
GND
34
GND
5
GND
15
TCK
25
GND
35
GND
6
GND
16
GND
26
GND
36
GND
7
(N.C.)
17
TMS
27
GND
37
GND
8
GND
18
GND
28
GND
38
GND
9
ICE_RESET
19
TDI
29
GND
CG1
GND
10
pull up
20
GND
30
GND
CG2
GND
CG3
GND
CG4
GND
CG5
GND
User’s Manual
103
CHAPTER
4.2.6.
4
3BCONNECTORS
Battery Connector [CN10]
Table 4-16
Through Hole
PIN
Signal
1
VBAT
2
TBAT
3
GND
†For Using battery; Please contact “battery suppler or battery consultants” and DIALOG Semiconductor.
‡Europe
Dialog Semiconductor GmbH
Neue Strasse 95
D-73230 Kirchheim/Teck-Nabern
Germany
Phone: (+49) 7021 805-0
Fax: (+49) 7021 805-100
Email: [email protected]
Web: http://www.diasemi.com
‡Japan
Dialog Semiconductor K.K.
Mita Kokusai Bldg 16F
1-4-28, Mita, Minato-ku,
Tokyo, 108-0073
Japan
Phone: (+81) 3 3769-8123
Fax: (+81) 3 3769-8124
Email: [email protected]
104
‡North America
Dialog North America
440 Oakmead Parkway
Sunnyvale, CA 94085
USA
Phone: (+1) 888-809-3816
Fax: (+1) 408-328-9275
Email: [email protected]
‡Taiwan
Dialog Semiconductor GmbH
Taiwan Branch
Chu-Nan 3rd Factory No. 118
Chung-Hua Road
Chu-Nan, Miao-Li 350
Taiwan R.O.C.
Phone: +886 37 598 166
Fax: +886 37 595 026
Email: [email protected]
User’s Manual
CHAPTER
4.2.7.
4
3BCONNECTORS
JTAG Connector [CN11]
Table 4-17
PIN
FFC-12BMEP1
Signal
1
TRST
2
GND
3
JT0_TMS
4
GND
5
JT0_TDI
6
GND
7
TCK
8
GND
9
GND
10
N.C.
11
TDO
12
GND
User’s Manual
105
CHAPTER
4.2.8.
4
3BCONNECTORS
NTSC/PAL Connector [J1]
Table 4-18
MR-551L
PIN
Signal
1
NTS_GND
2
DAC output
4.2.9.
AUDIO Connector [J2, J3]
Table 4-19
1: NTS_GND
2: DAC output
M03-772A0 [J2]
PIN
1
2
3
Signal
1
RIN1
2
LIN1
3
AGND
Table 4-20
MIC IN
M03-772A0 [J3]
PIN
1
2
3
Signal
1
LINE_OUT_R
2
LINE_OUT_L
3
AGND
LINE OUT
4.2.10. AC Adapter Connector [J4 ]
Table 4-21
PIN
HEC3600-010520
Signal
1
+5V
2
-
3
GND
1
2
3
Type: EIAJ 2
Input: 5V-2A
106
User’s Manual
CHAPTER
4.3.
4.3.1.
4
3BCONNECTORS
LCD
LCD Panel Interface Connector [CN7]
Table 4-22
PIN
Signal
FH23-51S-0.3SHW(06)
PIN
Signal
PIN
Signal
1
GND
21
D12_G
41
VCCIO
2
VCC
22
D13_G
42
GND
3
VCC
23
D14_G
43
XL
4
VCC
24
D15_G
44
YD
5
GND
25
D16_G
45
XR
6
/RESET
26
D17_G
46
YU
7
HSYNC
27
D20_R
47
GND
8
VSYNC
28
D21_R
48
ANODE1
9
CLK
29
D22_R
49
CATHODE1
10
GND
30
D23_R
50
ANODE2
11
D00_B
31
D24_R
51
CATHODE2
12
D01_B
32
D25_R
52
13
D02_B
33
D26_R
53
14
D03_B
34
D27_R
54
15
D04_B
35
GND
55
16
D05_B
36
SCL
56
17
D06_B
37
SI
57
18
D07_B
38
SO
58
19
D10_G
39
/CS
59
20
D11_G
40
VCOMIN
60
User’s Manual
107
CHAPTER
4
CHAPTER 5.
5.1.
5.1.1.
3BCONNECTORS
OTHERS
USB Connection
USB Mini B Connector by using serial COM port of EM1
USB Mini B connector is USB interface by using EM1 serial COM Port. EM1 URT0 is connected via FT232R
(FTDI's USB-Serial Converter). PC connection is as follows;
5.1.1.1 Installation for “Virtual COM port driver” and “USB driver”
5.1.1.1.1 Download and extract above drivers from FTDI’s support site;
http://www.ftdichip.com/Drivers/D2XX.htm (At the time of May, 2009)
Click the version-number from “Driver Version” portion
5.1.1.1.2 Power-ON CPU and I/O boards
5.1.1.1.3 Connect USB mini B of CPU board to USB-A of PC by USB cable
5.1.1.1.4 If the PC detects “Unknown USB device”, you can set-up these drivers by PC’s instruction.
5.1.1.2 Connect PC and CPU and I/O boards via COM port
5.1.1.2.1 Power-ON CPU and I/O boards
5.1.1.2.2 Connect USB mini B of CPU board to USB-A of PC by USB cable
5.1.1.2.3 Start “Terminal Software” (ex. Hyper Terminal, Tera-Term)
5.1.1.3. An example of PC terminal software settings
Serial COM port:
Depend on “Virtual COM port driver” installation
Serial COM port Settings for Board Test Program:
Baud Rate: 115.2k, Data: 8bit, Parity: none, Stop bit: 1 bit
Flow Control: none (Fixed, CTS/RTS lines are short-circuited)
Note) above terminal-software settings are depend on board-software settings.
“Virtual COM port driver” and “USB driver” are maintained / supported by FTDI (Future Technology
Devices International Limited). If you have any trouble for above settings, please ask to FTDI directly.
Future Technology Devices International Limited (On May ’09)
Unit 1, 2 Seaward Place
Centurion Business Park
Glasgow
G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-Mail (Support): [email protected]
E-Mail (General Enquiries): [email protected]
Web Site URL: http://www.ftdichip.com
5.1.2.
USB Mini AB
The Development Kit Board can receive a power supply voltage from USB Mini AB Connecter. This function
needs a Jumper Switch set. But a supply current from USB Host is not enough for the Development Kit Board as
CPU board, IO board and LCD panel.
108
User’s Manual
5.2.
Board installation to the Case
Approx. 32mm
Step 2: Upper case
installation to Base
case with PCB
Step 1: PCB installation
to Base case by three
screw
Approx. 153mm
Approx. 87mm
Figure 5-1
Case
User’s Manual
109
5.3.
MAC Address
MAC(MAC Address) sticker is on board.
Do not remove a MAC Address sticker.
Image:TBD
5.4.
Serial Number
S/N (Serial Number) sticker is on board.
Do not remove a S/N (Serial Number) sticker.
Image:TBD
5.5.
Board Revision
Board revision can be confirmed a character on PCB as below:
Information of Board revision
190441002: Rev 1
190441002A: Rev 2
There is a case that some mounting components are different by a revision of the board. Please refer to BOM of the board
about the detail information. And recognition way for software of board revision can be confirmed in 5.6 Board Information
in EEPROM.
110
User’s Manual
5.6.
Board Information in EEPROM (Factory setting)
Development Kit board has information for clarification of board revision on software point of view. And the information is
related on Board Revision.
The information is in EEPROM of Ether IC (LAN9221) in IO board as below.
Do not overwrite any data in Board information. These data are needed for software to work normally.
<R>
Table 5-1
7
EM1-S/D
LAN9221 EEPROM Address: 0x10
6
USB-PHY
5
DDR-BA01
Name
EM1-S/D
R*
R
Bits
7
USB-PHY
R
6
DDR-BA01
R
5
eMMC
R
4
DDR
R
3
Reserved
R
2-0
Table 5-2
7
6
PMIC rev
5
Name
PMIC rev
R*
R
Bits
7-5
PMIC OTP
R
4-2
Reserved
R
2-0
Table 5-3
7
NAND
6
5
BD1
Name
NAND
R*
R
Bits
7
BD1
R
6-4
BD2
R
3-0
4
eMMC
3
2
1
0
Reserved
Contents
EM1 device name on board
0: EM1-S
1: EM1-D
USB-PHY device name on board
0: NXP ISP1504
1: SMSC USB3329
Two connection between EM1 and DDR
0: BA0-BA1 and BA1-BA0
1: BA0-BA0 and BA1-BA1
eMMC device name on board
0: Micron MTFC4GDKDI
1: Samsung KMCEG0000A
DDR device name on board
0: Micron MT46H32M32LF without Auto Self Refresh function
1:TBD with Auto Self Refresh function
Reserved.
LAN9221 EEPROM Address: 0x11
4
3
PMIC OTP
2
1
0
Reserved
Contents
PMIC device revision on board
000:DA9052 ES
001: DA9052 A silicon
010: DA9052 B silicon
OTP data of PMIC device for initial setting at factory.
000: DA9052 r0.4
001: DA9052 r0.4 modified
010: DA9052 r0.9
Reserved.
LAN9221 EEPROM Address: 0x12
4
3
2
1
0
BD2
Contents
With/Without of NAND memory on IO board
0: Without NAND Flash memory
1: With NAND Flash memory
Board information Data 1
000: IO board revision 1
001: IO board revision 2
010-111: reserved
Board information Data 2, still not used
0000-1111: reserved
Note) Do not overwrite any data in Board information.
User’s Manual
111
5.7.
Monitor Point and Test Pad
Below table is shown points of monitor, test input or current measurement use which you can use, if it is
necessary for you.
A current measurement point in table can be used for the current consumption measurement by using ampere
meter. Signal monitor points in table can monitor by using oscilloscope or equivalent equipment.
Test input points are for use of functionality expansion.
<R>
Table 5-4
Board
Name
CPU
Purpose of
Use
Current
measurem
ent
IO
Current
measurem
ent
CPU
Signal
Monitor
IO
Signal
Monitor
GND
Signal
Monitor
Input for
Test
GND
112
Monitor Point and Test Pad
Name
R128
R139
R131
R133
R129
R41
R42
R92
R96
R93
R97
TP1
TP2
TP3
TP4
TP5
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
Contents
These resistors are 0 ohm and are mounted on 1.2v line for EM1.
The resistor is 0 ohm and is mounted on 1.8v line for EM1 VIO18.
The resistor is 0 ohm and is mounted on 2.85v line for EM1 VIO3.
The resistor is 0 ohm and is mounted on 1.2V line for EM1 PLL
circuit.
These resistors are 0 ohm and are mounted on VBUS line from
USB Mini-AB connector.
These resistors are 0 ohm and are mounted on 5.0v line from AC
adapter.
These resistors are 0 ohm and are mounted on VBAT line to/from
CN10 which is NMT and for a battery connection.
AK4648 MCKO
D9052 VPERI_SW
D9052 VMEM_SW
D9052 PWR_UP
D9052 GPIO_0
URT0_SRIN_R (ADM3202)
URT0_SOUT_R (ADM3202)
GND Pad
KEY_IN0 (DA9052 GPIO_8)
KEY_IN1 (DA9052 GPIO_9)
KEY_IN2 (DA9052 GPIO_10)
KEY_IN3 (DA9052 GPIO_12)
URT1_SOUT (EM1)
URT1_SRIN (EM1)
D9052_GPIO_0
CPU Board SW5 (EM1 GIO_P71)
IIC Expander input 0 (MAX7324)
IIC Expander input 1 (MAX7324)
IIC Expander input 2 (MAX7324)
IIC Expander input 3 (MAX7324)
IIC Expander input 4 (MAX7324)
IIC Expander input 5 (MAX7324)
IIC Expander input 6 (MAX7324)
IIC Expander input 7 (MAX7324)
GND Terminal
User’s Manual
<R>
5.8.
Modification for signals in external connector [CN4/CN5]
Following table shows modification point for connection to external connector. Alternate signals of NTSC signal is
not connected on default state's IO board. So when any signal of the table is used through external connector
[CN4/CN5], it needs modification to use it. And after the modification, please refer to Connection of CPU board
and IO board for connection of CPU and IO board.
Table 5-5
Board
IO
Connec
tor
CN4
CN5
Modification signal in external connector
Signal
CAM_YUV1
CAM_YUV3
CAM_YUV4
SP1_SO-CAM_YUV0
SP1_CS1-CAM_YUV2
SP1_SI
SP1_CLK
PM1_SO
PM1_SI
PM1_SEN
Resist
or
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
Default
(Note 1)
NMT
NMT
NMT
NMT
NMT
NMT
NMT
NMT
NMT
NMT
Modification for
use case
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
0 ohm
Alternate signal
(Note 2)
NTS_DATA1
NTS_DATA3
NTS_DATA4
NTS_DATA0
NTS_DATA2
NTS_HS
NTS_VS
NTS_DATA7
NTS_DATA6
NTS_DATA5
Note1. NMT means “not mounted component”.
Note2. After the modification, please take care about output signal's wired-or. Alternate signal cannot use at the
same time. For the example, CAM_YUV1 from camera component and NTS_DATA1 from EM1 is output signal.
You should not use camera interface and NTSC interface after the modification.
Regarding place of R78-R87, please refer to following photo.
R84
R85
R86
R83
R87
R78
R80
User’s Manual
R79
R81
R82
113
<R>
5.9.
Connection of CPU board and IO board
CPU board and IO board is connected by two couple of 150 pin connectors. If you detach the connectors for a
reason, please carefully refer to a following procedure for attaching the connectors.
Step 1: Start
Step 2: Put CPU board on IO board. Be careful
about the aspect of IO CPU board.
Step 3: Push the connector toward inside and
downward with holding the metal parts.
Step 4: Confirm whether metal parts fold a plastic
part about four-portion in the side view
This plastic portion
should be .inside this
metal part.
Step 5: Insert fully metal parts to be parallel line
against the connector.
Step 6: Same as step 5 about other side connector.
Step 7: Final Confirmation 1: confirm whether
following distance 'D1' is same about four-portion.
The concrete distance of this photo is subject to
change without notice.
Step 8: Final Confirmation 2: when the connectors are
inserted correctly, following distance ‘D2’ must be
61.11mm approx about any distance between metal
part of connectors.
D2
D1
114
User’s Manual
PDF 時は、この頁を削除
Revision history
Date
Revi
Comments
sion
28th Oct. 2009
1.0
First edition
4th Feb 2010
1.1
NEC Revision 2.3 を反映
Writer
Arase
NEC Revision 2.4 を反映
th
16 Feb 2010
1.2
Urano
表に以下を追加しました。
010: DA9052 B silicon
th
17 , Mar. 2010 1.3
5.8 Modification for signals in external connector [CN4/CN5]
を新規追加
Arase
5.9 Connection of CPU board and IO board
を新規追加
4.2.3Enhanced Connector [CN4]
テーブル内に Note を追加
4.2.4Enhanced Connector [CN4]
テーブル内に Note を追加
5.2.Board installation to the Case
ケース寸法と外形図、取り付け方法を見直し
5.6 Board Information in EEPROM (Factory setting)
TTable 番号を取得(内容に変更なし)
5.7 Monitor Point and Test Pad
Table 番号を取得(内容に変更なし)
Revision History, Rev2.4
Revision History 2.4 版の位置を前の頁に移動
各頁
02nd, Apr. 2010
社名変更(NEC→Renesas)
Table 5-2 LAN9221 EEPROM Address: 0x11
PMIC rev ビットに B silicon を追加
Table 5-3 LAN9221 EEPROM Address: 0x12
NAND ビット誤記訂正
( 旧:0: With NAND memory 1: Without NAND memory )
User’s Manual
115
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