Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

STM8S003K3 STM8S003F3

Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C

LQFP32 7x7

Features

TSSOP20

UFQFPN20 3x3

Core

16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline

Extended instruction set

Memories

Program memory: 8 Kbytes Flash; data retention

20 years at 55 °C after 100 cycles

RAM: 1 Kbytes

Data memory: 128 bytes of true data EEPROM; endurance up to 100 000 write/erase cycles

Clock, reset and supply management

2.95 to 5.5 V operating voltage

Flexible clock control, 4 master clock sources:

-

Low power crystal resonator oscillator

-

External clock input

-

Internal, user-trimmable 16 MHz RC

-

Internal low power 128 kHz RC

Clock security system with clock monitor

Power management:

-

Low power modes (wait, active-halt, halt)

-

Switch-off peripheral clocks individually

Permanently active, low consumption power-on and power-down reset

Interrupt management

Nested interrupt controller with 32 interrupts

Up to 27 external interrupts on 6 vectors

Timers

Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)

8-bit basic timer with 8-bit prescaler

Auto wake-up timer

Window watchdog and independent watchdog timers

Communications interfaces

UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode

SPI interface up to 8 Mbit/s

I

2

C interface up to 400 Kbit/s

Analog to digital converter (ADC)

10-bit, ±1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog

I/Os

Up to 28 I/Os on a 32-pin package including 21 high sink outputs

Highly robust I/O design, immune against current injection

Development support

Embedded single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging

January 2012

DocID018576 Rev 2

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www.st.com

Contents STM8S003K3 STM8S003F3

Contents

1 Introduction ..............................................................................................................7

2 Description ...............................................................................................................8

3 Block diagram ..........................................................................................................9

4 Product overview ...................................................................................................10

4.1 Central processing unit STM8 .....................................................................................10

4.2 Single wire interface module (SWIM) and debug module (DM) ..................................10

4.3 Interrupt controller .......................................................................................................11

4.4 Flash program memory and data EEPROM ................................................................11

4.5 Clock controller ............................................................................................................12

4.6 Power management ....................................................................................................13

4.7 Watchdog timers ..........................................................................................................13

4.8 Auto wakeup counter ...................................................................................................14

4.9 Beeper ........................................................................................................................14

4.10 TIM1 - 16-bit advanced control timer .........................................................................14

4.11 TIM2 - 16-bit general purpose timer ..........................................................................15

4.12 TIM4 - 8-bit basic timer ..............................................................................................15

4.13 Analog-to-digital converter (ADC1) ............................................................................15

4.14 Communication interfaces .........................................................................................16

4.14.1 UART1 ...............................................................................................16

4.14.2 SPI .....................................................................................................17

4.14.3 I²C ......................................................................................................17

5 Pinout and pin description ...................................................................................18

5.1 STM8S003K3 LQFP32 pinout and pin description ......................................................18

5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description ...............................21

5.2.1 STM8S003F3 TSSOP20 pinout and pin description ............................21

5.2.2 STM8S003F3 UFQFPN20 pinout ........................................................22

5.2.3 STM8S003F3 TSSOP20/UFQFPN20 pin description ..........................22

5.3 Alternate function remapping .......................................................................................24

6 Memory and register map .....................................................................................25

6.1 Memory map ................................................................................................................25

6.2 Register map ...............................................................................................................26

6.2.1 I/O port hardware register map ............................................................26

6.2.2 General hardware register map ..........................................................27

6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................36

7 Interrupt vector mapping ......................................................................................39

8 Option bytes ...........................................................................................................41

8.1 Alternate function remapping bits ................................................................................43

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STM8S003K3 STM8S003F3 Contents

9 Electrical characteristics ......................................................................................46

9.1 Parameter conditions ...................................................................................................46

9.1.1 Minimum and maximum values ...........................................................46

9.1.2 Typical values .......................................................................................46

9.1.3 Typical curves ......................................................................................46

9.1.4 Loading capacitor .................................................................................46

9.1.5 Pin input voltage ...................................................................................46

9.2 Absolute maximum ratings ..........................................................................................47

9.3 Operating conditions ....................................................................................................49

9.3.1 VCAP external capacitor ......................................................................50

9.3.2 Supply current characteristics ..............................................................51

9.3.3 External clock sources and timing characteristics ...............................60

9.3.4 Internal clock sources and timing characteristics .................................62

9.3.5 Memory characteristics ........................................................................64

9.3.6 I/O port pin characteristics ...................................................................66

9.3.7 Reset pin characteristics ......................................................................74

9.3.8 SPI serial peripheral interface ..............................................................77

9.3.9 I

2

C interface characteristics .................................................................80

9.3.10 10-bit ADC characteristics ..................................................................81

9.3.11 EMC characteristics ...........................................................................85

10 Package information ...........................................................................................89

10.1 32-pin LQFP package mechanical data ....................................................................89

10.2 20-pin TSSOP package mechanical data ..................................................................90

10.3 20-lead UFQFPN package mechanical data .............................................................92

11 Thermal characteristics .......................................................................................93

11.1 Reference document .................................................................................................93

11.2 Selecting the product temperature range ..................................................................93

12 Ordering information ...........................................................................................95

13 STM8 development tools ....................................................................................96

13.1 Emulation and in-circuit debugging tools ...................................................................96

13.2 Software tools ............................................................................................................96

13.2.1 STM8 toolset ......................................................................................97

13.2.2 C and assembly toolchains ................................................................97

13.3 Programming tools ....................................................................................................97

14 Revision history ...................................................................................................98

DocID018576 Rev 2 3/99

List of tables STM8S003K3 STM8S003F3

List of tables

Table 1. STM8S003xx value line features ................................................................................................8

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................13

Table 3. TIM timer features ....................................................................................................................15

Table 4. Legend/abbreviations for pinout tables ...................................................................................18

Table 5. LQFP32 pin description ............................................................................................................19

Table 6. STM8S003F3 pin description ...................................................................................................22

Table 7. I/O port hardware register map ................................................................................................26

Table 8. General hardware register map ...............................................................................................27

Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................36

Table 10. Interrupt mapping ...................................................................................................................39

Table 11. Option bytes ...........................................................................................................................98

Table 12. Option byte description ...........................................................................................................41

Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices ......................................43

Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices ......................................44

Table 15. Voltage characteristics ...........................................................................................................47

Table 16. Current characteristics ...........................................................................................................47

Table 17. Thermal characteristics ..........................................................................................................48

Table 18. General operating conditions .................................................................................................49

Table 19. Operating conditions at power-up/power-down ......................................................................50

Table 20. Total current consumption with code execution in run mode at V

DD

Table 21. Total current consumption with code execution in run mode at V

DD

Table 22. Total current consumption in wait mode at V

DD

Table 23. Total current consumption in wait mode at V

DD

= 5 V .............................51

= 3.3 V ..........................52

= 5 V ............................................................53

= 3.3 V .........................................................53

Table 24. Total current consumption in active halt mode at V

DD

Table 25. Total current consumption in active halt mode at V

DD

= 5 V ..................................................54

= 3.3 V ...............................................54

= 5 V .............................................................55

Table 26. Total current consumption in halt mode at V

DD

Table 27. Total current consumption in halt mode at V

DD

= 3.3 V ..........................................................55

Table 28. Wakeup times .........................................................................................................................56

Table 29. Total current consumption and timing in forced reset state ....................................................57

Table 30. Peripheral current consumption .............................................................................................57

Table 31. HSE user external clock characteristics .................................................................................60

Table 32. HSE oscillator characteristics .................................................................................................61

Table 33. HSI oscillator characteristics ..................................................................................................62

Table 34. LSI oscillator characteristics ...................................................................................................64

Table 35. RAM and hardware registers ..................................................................................................64

Table 36. Flash program memory and data EEPROM ...........................................................................65

Table 37. I/O static characteristics .........................................................................................................66

Table 38. Output driving current (standard ports) ..................................................................................68

Table 39. Output driving current (true open drain ports) ........................................................................68

Table 40. Output driving current (high sink ports) ..................................................................................69

Table 41. NRST pin characteristics ........................................................................................................74

Table 42. SPI characteristics ..................................................................................................................78

Table 43. I

2

C characteristics ..................................................................................................................80

Table 44. ADC characteristics ................................................................................................................82

Table 45. ADC accuracy with R

AIN

Table 46. ADC accuracy with R

AIN

< 10 kΩ , V

DD

= 5 V

< 10 kΩ R

AIN

, V

DD

.........................................................................82

= 3.3 V ..............................................................83

Table 47. EMS data ................................................................................................................................86

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STM8S003K3 STM8S003F3 List of tables

Table 48. EMI data .................................................................................................................................86

Table 49. ESD absolute maximum ratings .............................................................................................87

Table 50. Electrical sensitivities .............................................................................................................88

Table 51. 32-pin low profile quad flat package mechanical data ............................................................89

Table 52. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .........................................................91

Table 53. 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data ......................92

Table 54. Thermal characteristics ..........................................................................................................93

Table 55. Document revision history ......................................................................................................98

DocID018576 Rev 2 5/99

List of figures STM8S003K3 STM8S003F3

List of figures

Figure 1. Block diagram ...........................................................................................................................9

Figure 2. Flash memory organization ....................................................................................................12

Figure 3. STM8S003K3 LQFP32 pinout ................................................................................................18

Figure 4. STM8S003F3 TSSOP20 pinout ..............................................................................................21

Figure 5. STM8S003F3 UFQFPN20-pin pinout .....................................................................................22

Figure 6. Memory map ...........................................................................................................................25

Figure 7. Pin loading conditions .............................................................................................................46

Figure 8. Pin input voltage .....................................................................................................................47

Figure 9. f

CPUmax versus V

DD

................................................................................................................50

Figure 10. External capacitor C

EXT

.......................................................................................................50

Figure 11. Typ I

DD(RUN)

Figure 12. Typ I

DD(RUN)

Figure 13. Typ I

DD(RUN)

Figure 14. Typ I

DD(WFI)

Figure 15. Typ I

Figure 16. Typ I

DD(WFI)

DD(WFI)

vs. V vs. f

vs. V

DD

CPU

DD vs. V

DD

vs. f

CPU vs. V

DD

HSE user external clock, f

CPU

HSE user external clock, V

DD

HSI RC osc, f

CPU

= 16 MHz .................................................................59

HSE user external clock, f

CPU

HSE user external clock, V

HSI RC osc, f

CPU

DD

= 16 MHz .............................................58

= 5 V ....................................................58

= 16 MHz ..............................................59

= 5 V .....................................................60

= 16 MHz .................................................................60

Figure 17. HSE external clock source ....................................................................................................61

Figure 18. HSE oscillator circuit diagram ...............................................................................................62

Figure 19. Typical HSI frequency variation vs V

DD

Figure 20. Typical LSI frequency variation vs V

DD

Figure 21. Typical V

IL and V

IH vs V

DD

@ 4 temperatures ......................................................................67

Figure 22. Typical pull-up resistance vs V

DD

Figure 23. Typical pull-up current vs V

Figure 24. Typ. V

OL

Figure 25. Typ. V

OL

Figure 26. Typ. V

OL

Figure 27. Typ. V

OL

Figure 28. Typ. V

OL

Figure 29. Typ. V

OL

Figure 30. Typ. V

DD

Figure 31. Typ. V

DD

Figure 32. Typ. V

DD

Figure 33. Typ. V

DD

@ V

@ V

DD

DD

@ V

DD

@ V

DD

DD

@ 4 temperatures ..................................................63

@ 4 temperatures ...................................................64

@ 4 temperatures ............................................................67

@ 4 temperatures .................................................................68

= 5 V (standard ports) ................................................................................70

= 3.3 V (standard ports) .............................................................................70

= 5 V (true open drain ports) ......................................................................71

@ V

DD

@ V

DD

= 5 V (high sink ports) ................................................................................72

= 3.3 V (high sink ports) .............................................................................72

- V

OH

@ V

DD

= 5 V (standard ports) .......................................................................73

- V

OH

- V

OH

- V

OH

@ V

@ V

DD

@ V

DD

Figure 34. Typical NRST V

IL

= 3.3 V (true open drain ports) ...................................................................71

DD

and V

= 3.3 V (standard ports) ...................................................................73

= 5 V (high sink ports) .......................................................................74

= 3.3 V (high sink ports) ....................................................................74

IH vs V

DD

@ 4 temperatures ...........................................................76

Figure 35. Typical NRST pull-up resistance vs V

Figure 36. Typical NRST pull-up current vs V

DD

DD

@ 4 temperatures .................................................76

@ 4 temperatures ......................................................77

Figure 37. Recommended reset pin protection ......................................................................................77

Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................79

Figure 39. SPI timing diagram - slave mode and CPHA = 1 ..................................................................79

Figure 40. SPI timing diagram - master mode

(1)

...................................................................................80

Figure 41. Typical application with I

2

C bus and timing diagram ............................................................84

Figure 42. ADC accuracy characteristics ...............................................................................................84

Figure 43. Typical application with ADC ................................................................................................85

Figure 44. 32-pin low profile quad flat package (7 x 7) ..........................................................................89

Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................90

Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ....................................92

Figure 47. STM8S003x value line ordering information scheme ...........................................................95

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STM8S003K3 STM8S003F3

1 Introduction

Introduction

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).

For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the STM8

SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, please refer to the STM8 CPU programming manual

(PM0044).

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Description

2

STM8S003K3 STM8S003F3

Description

The STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual

(RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.

Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.

The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Device

Pin count

Maximum number of GPIOs (I/Os)

Ext. interrupt pins

Table 1: STM8S003xx value line features

STM8S003K3

32

STM8S003F3

20

28

27

16

16

Timer CAPCOM channels

Timer complementary outputs

A/D converter channels

High sink I/Os

7

3

4

21

7

2

5

12

Low density Flash program memory (bytes)

RAM (bytes)

True data EEPROM (bytes)

Peripheral set

8K 8K

1K

128

(1)

1K

128

(1)

Multipurpose timer (TIM1), SPI, I

2

C, UART window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)

(1)

Without read-while-write capability.

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STM8S003K3 STM8S003F3

3 Block diagram

Figure 1: Block diagram

Block diagram

Reset

Single wire debug interf.

400 Kbit/s

8 Mbit/s

LIN master

SPI emul.

Up to 5 channels

1/2/4 kHz beep

Reset block

POR

Reset

BOR

Clock controller

Detector

XTAL 1-16 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART1

ADC1

Beeper

Clock to peripherals and core

Window WDG

Independent WDG

8-Kbyte program

Flash

128-byte data EEPROM

1-Kbyte

RAM

16-bit advanced control timer (TIM1)

16-bit general purpose timer (TIM2)

8-bit basic timer

(TIM4)

AWU timer

Up to

4 CAPCOM channels +3 complementary outputs

Up to

3 CAPCOM channels

DocID018576 Rev 2 9/99

Product overview

4

4.1

4.2

Product overview

STM8S003K3 STM8S003F3

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual

(RM0016).

Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching for most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

8-bit accumulator

24-bit program counter - 16-Mbyte linear memory space

16-bit stack pointer - access to a 64 K-level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address space

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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4.3

4.4

Product overview

SWIM

Single wire interface module for direct access to the debug module and memory programming.

The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator.

Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

R/W access to all resources by stalling the CPU

Breakpoints on all program-memory instructions (software breakpoints)

Two advanced breakpoints, 23 predefined configurations

Interrupt controller

Nested interrupts with three software priority levels

32 interrupt vectors with hardware priority

Up to 27 external interrupts on 6 vectors including TLI

Up to 37 external interrupts on 6 vectors including TLI

Trap and reset interrupts

Flash program memory and data EEPROM

8 Kbytes of Flash program single voltage Flash memory

128 bytes of true data EEPROM

User option byte area

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, the data EEPROM, and the option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of the main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page

(64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: 8 Kbytes minus UBC

User-specific boot code (UBC): Configurable up to 8 Kbytes

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Product overview STM8S003K3 STM8S003F3

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the

IAP and communication routines.

Figure 2: Flash memory organization

Option bytes

Data EEPROM (128 bytes)

UBC area

Remains write protected during IAP

Programmable area from 64 bytes(1 page) up to 8 Kbytes

(in 1 page steps)

Low density

Flash program

 

(8 Kbytes)

Program memory area

Write access possible for IAP

4.5

12/99

Read-out protection (ROP)

The read-out protection blocks reading and writing from/to the Flash program memory and the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller

The clock controller distributes the system clock (f

MASTER

) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master clock:

-

1-16 MHz high-speed external crystal (HSE)

-

Up to 16 MHz high-speed user-external clock (HSE user-ext)

-

16 MHz high-speed internal RC oscillator (HSI)

-

128 kHz low-speed internal RC (LSI)

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STM8S003K3 STM8S003F3 Product overview

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the application.

Bit

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral clock

Bit Peripheral clock

Bit Peripheral clock

Bit Peripheral clock

PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC

PCKEN16

PCKEN15

PCKEN14

Reserved

TIM2

TIM4

PCKEN12

PCKEN11

PCKEN10

Reserved

SPI

I

2

C

PCKEN26

PCKEN25

PCKEN24

Reserved

Reserved

Reserved

PCKEN22

PCKEN21

PCKEN20

AWU

Reserved

Reserved

4.6

4.7

Power management

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

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Product overview

4.8

4.9

4.10

STM8S003K3 STM8S003F3

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to

64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter

Used for auto wakeup from active halt mode

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

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STM8S003K3 STM8S003F3 Product overview

Encoder mode

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11

TIM2 - 16-bit general purpose timer

16-bit autoreload (AR) up-counter

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

3 individually configurable capture/compare channels

PWM mode

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

4.12

Timer

TIM1

TIM2

TIM4 8

TIM4 - 8-bit basic timer

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

Clock source: CPU clock

Interrupt source: 1 x overflow/update

Table 3: TIM timer features

Counter size (bits)

Prescaler

Counting mode

CAPCOM channels

Complem.

outputs

Ext.

trigger

Timer synchronization/ chaining

16

Any integer from 1 to

65536

Up/down 4 3 Yes

16

Any power of

2 from 1 to

32768

Up 3 0 No No

Any power of

2 from 1 to

128

Up 0 0 No

4.13

Analog-to-digital converter (ADC1)

The STM8S003xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed inputs channels and the following features:

The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features:

Input voltage range: 0 to V

DD

Input voltage range: 0 to V

DDA

Conversion time: 14 clock cycles

Single and continuous and buffered continuous conversion modes

Buffer size (n x 10 bits) where n = number of input channels

DocID018576 Rev 2 15/99

Product overview STM8S003K3 STM8S003F3

Scan mode for single and continuous conversion of a sequence of channels

Analog watchdog capability with programmable upper and lower thresholds

Analog watchdog interrupt

External trigger input

Trigger from TIM1 TRGO

End of conversion (EOC) interrupt

Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

4.14

4.14.1

Communication interfaces

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

I²C: Up to 400 Kbit/s

UART1

Main features

One Mbit/s full duplex SCI

SPI emulation

High precision baud rate generator

Smartcard emulation

IrDA SIR encoder decoder

LIN master mode

Single wire half duplex mode

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

Programmable transmit and receive baud rates up to 1 Mbit/s (f

CPU

/16) and capable of following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

Two receiver wakeup modes:

-

Address bit (MSB)

-

Idle line (interrupt)

Transmission error detection with interrupt generation

Parity control

Synchronous communication

Full duplex synchronous transfers

16/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

SPI master operation

8-bit data communication

Maximum speed: 1 Mbit/s at 16 MHz (f

CPU

/16)

LIN master mode

Emission: Generates 13-bit synch break frame

Reception: Detects 11-bit break frame

4.14.2

4.14.3

Product overview

SPI

Maximum speed: 8 Mbit/s (f

MASTER

/2) both for master and slave

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave/master selection input pin

I²C

I²C master features:

-

Clock generation

-

Start and stop generation

I²C slave features:

-

Programmable I2C address detection

-

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

-

Standard speed (up to 100 kHz)

-

Fast speed (up to 400 kHz)

DocID018576 Rev 2 17/99

Pinout and pin description

5 Pinout and pin description

Type

Level

Output speed

Port and control configuration

Reset state

STM8S003K3 STM8S003F3

Table 4: Legend/abbreviations for pinout tables

I= Input, O = Output, S = Power supply

Input

CM = CMOS

Output HS = High sink

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset

O4 = Fast/slow programmability with fast as default state after reset

Input

Output float = floating, wpu = weak pull-up

T = True open drain, OD = Open drain, PP =

Push pull

Bold X (pin state after internal reset release).

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

5.1

STM8S003K3 LQFP32 pinout and pin description

Figure 3: STM8S003K3 LQFP32 pinout

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

VCAP

VDD

[SPI_NSS] TIM2_CH3/(HS)PA3

PF4

6

7

4

5

2

3

1

32 31 30 29 28 27 26 25

24

23

22

21

20

19

8

18

9 10 11 12 13 14 15 16

17

PC7 (HS)/SPI_MISO

PC6 (HS)/SPI_MOSI

PC5 (HS)/SPI_SCK

PC4 (HS)/TIM1_CH4/CLK_CCO

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1/ UART1_CK

PE5

(HS)

/SPI_NSS

18/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Pinout and pin description

Pin no.

Pin name

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to V

DD not implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

Table 5: LQFP32 pin description

Input Output

Type floating wpu

Ext.

interrupt

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

Alternate function after remap

[option bit]

1

2

NRST I/O

PA1/ OSCI

(2)

I/O

X

X

X X O1 X X

Reset

Port A1 Resonator/ crystal in

3 PA2/ OSCOUT I/O

X

X X

4

5

VSS

VCAP

6

7

VDD

PA3/

TIM2_CH3

[SPI_NSS]

8 PF4

S

S

S

I/O

X

13 PB3/AIN3/

TIM1_ETR

I/O

X

9 PB7 I/O

X

10 PB6 I/O

X

11 PB5/ I

2

C_SDA I/O

X

12 PB4/ I

2

C_SCL I/O

X

I/O

X

14 PB2/AIN2/

TIM1_CH3N

I/O

X

X X

X

X X

X X

X

X

X X

X X

O1 X X Port A2 Resonator/ crystal out

Digital ground

1.8 V regulator capacitor

HS O3 X X

Digital power supply

Port A3 Timer 2 channel 3

O1 X X Port F4

O1 X X Port B7

O1

O1

O1

X

T

(3)

T

(3)

X Port B6

Port B5

Port B4

HS O3 X X Port B3

HS O3 X X Port B2

I

2

C data

I

2

C clock

Analog input 3/

Timer 1 external trigger

Analog input 2/

Timer 1 inverted channel 3

SPI master/ slave select

[AFR1]

DocID018576 Rev 2 19/99

Pinout and pin description STM8S003K3 STM8S003F3

Pin no.

Pin name

15 PB1/AIN1/

TIM1_CH2N

Input Output

Type floating wpu

Ext.

interrupt

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

I/O

X

X X HS O3 X X Port B1 Analog input 1/

Timer 1 inverted channel 2

Alternate function after remap

[option bit]

16 PB0/AIN0/

TIM1_CH1N

I/O

X

X X HS O3 X X Port B0 Analog input 0/

Timer 1 inverted channel 1

17 PE5/

SPI_NSS

18 PC1/

TIM1_CH1/

UART1_CK

I/O

X

I/O

X

X X

X X

HS O3 X X Port E5

HS O3 X X Port C1

SPI master/slave select

Timer 1 channel 1

UART1 clock

19

20

PC2/

TIM1_CH2

PC3/

TIM1_CH3

21 PC4/

TIM1_CH4/

CLK_CCO

I/O

X

I/O

I/O

X

X

X X

X

X

X

X

HS O3 X X Port C2

HS

HS

O3

O3

X

X

X

X

Port C3

Port C4

Timer 1 channel 2

Timer 1 channel 3

22

23

24

25

26

PC5/ SPI_SCK I/O

PC6/ PI_MOSI I/O

PC7/ PI_MISO I/O

PD0/

TIM1_BKIN

[CLK_CCO]

PD1/ SWIM

(4)

I/O

I/O

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

HS

HS

HS

HS

O3

HS O3

O3

O3

O4

X

X

X

X

X

X X

X

X

X

Port C5

Port C6

Port C7

Port D0

Port D1

Timer 1 channel 4

/configurable clock output

SPI clock

SPI master out/slave in

SPI master in/ slave out

Timer 1 - break input

Configurable clock output

[AFR5]

SWIM data interface

27 PD2

[TIM2_CH3]

I/O

X

X X HS O3 X X Port D2 Timer 2 channel

3[AFR1]

20/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Pinout and pin description

Pin no.

Pin name

28 PD3/

TIM2_CH2/

ADC_ETR

29 PD4/BEEP/

TIM2_CH1

Input Output

Type floating wpu

Ext.

interrupt

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

I/O

X

X X HS O3 X X Port D3 Timer 2 channel 2/ADC external trigger

Alternate function after remap

[option bit]

I/O

X

X X HS O3 X X Port D4

30 PD5/

UART1_TX

31 PD6/

UART1_RX

I/O

I/O

X

X

32 PD7/ TLI

[TIM1_CH4]

I/O

X

X

X

X

X

X

X

HS

HS

HS

O3

O3

O3

X

X

X

X

X

X

Port D5

Port D6

Port D7

Timer 2 channel

1/BEEP output

UART1 data transmit

UART1 data receive

Top level interrupt

Timer 1 channel 4

[AFR6]

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings (see

Electrical characteristics

).

(2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.

(3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).

(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

5.2

5.2.1

STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description

STM8S003F3 TSSOP20 pinout and pin description

Figure 4: STM8S003F3 TSSOP20 pinout

UART1_CK/TIM2_CH1/BEEP/(HS)PD4

UART1_TX/AIN5/(HS) PD5

UART1_RX/AIN6/(HS) PD6

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

VCAP

VDD

[SPI_NSS] TIM2_CH3/(HS) PA3

7

8

9

10

3

4

1

2

5

6

16

15

14

20

19

18

17

13

12

11

PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR

PD2 (HS)/AIN3/[TIM2_CH3]

PD1(HS)/SWIM

PC7 (HS) /SPI_MISO [TIM1_CH2]

PC6 (HS)/SPI_MOSI [TIM1_CH1]

PC5 (HS)/SPI_SCK [TIM2_CH1]

PC4

(HS)

/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]

PB4 (T)/I

2

C_SCL [ADC_ETR]

PB5 (T)/I

2

C_SDA [TIM1_BKIN]

1. HS high sink capability.

DocID018576 Rev 2 21/99

Pinout and pin description STM8S003K3 STM8S003F3

2. (T) True open drain (P-buffer and protection diode to V

DD not implemented).

3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

5.2.2

STM8S003F3 UFQFPN20 pinout

Figure 5: STM8S003F3 UFQFPN20-pin pinout

NRST

OSCIN/PA1

OSCOUT/PA2

VSS

VCAP

1

2

3

4

5

20 19 18 17 16

15

14

13

12

11

6 7 8

9 10

PD1(HS)/SWIM

PC7(HS)/SPI_MISO[TIM1_CH2]

PC6(HS)/SPI_MOSI [TIM1_CH1]

PC5 (HS)/SPI_SCK [TIM2_CH1]

PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]

1. HS high sink capability.

2. (T) True open drain (P-buffer and protection diode to V

DD not implemented).

3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).

5.2.3

STM8S003F3 TSSOP20/UFQFPN20 pin description

Pin no.

TSSOP20 UFQFPN20

Pin name

1 18 PD4/ BEEP/

TIM2_ CH1/

UART1 _CK

Table 6: STM8S003F3 pin description

Input Output

Type floating wpu

Ext.

interr.

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

I/O

X

X X HS O3 X X Port

D4

Timer 2 channel

1/BEEP output/

Alternate function after remap [option bit]

22/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Pinout and pin description

7

8

4

5

Pin no.

TSSOP20

2

3

UFQFPN20

19

20

Pin name

PD5/ AIN5/

UART1 _TX

PD6/ AIN6/

UART1 _RX

Input Output

Type floating wpu

Ext.

interr.

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

I/O

I/O

X

X

X

X

X

X

HS

HS

O3

O3

X

X

X

X

Port

D5

Port

D6

UART1 clock

Analog input 5/

UART1 data transmit

Analog input 6/

UART1 data receive

1

2

NRST

PA1/ OSCIN

(2)

I/O

I/O

X

X

X X O1 X X

6

9

10

11

12

13

14

15

3

4

5

6

7

8

9

10

11

12

PA2/

OSCOUT

VSS

VCAP

VDD

PA3/ TIM2_

CH3 [SPI_

NSS]

PB5/ I

2

C_

SDA [TIM1_

BKIN]

PB4/ I

2

C_

SCL

PC3/

TIM1_CH3

[TLI] [TIM1_

CH1N]

PC4/

CLK_CCO/

TIM1_

CH4/AIN2/[TIM1_

CH2N]

PC5/

SPI_SCK

[TIM2_ CH1]

I/O

S

S

S

I/O

I/O

I/O

I/O

I/O

I/O

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

HS

HS

HS

HS

O1

O3

O1

O1

O3

O3

O3

X

X

T

(3)

T

X

X

X

(3)

X

X

X

X

X

Alternate function after remap [option bit]

Reset

Port

A1

Resonator/ crystal in

Port

A2

Resonator/ crystal out

Digital ground

1.8 V regulator capacitor

Digital power supply

Port

A3

Timer 2 channel 3

Port

B5

Port

B4

Port

C3

I

I

2

2

C data

C clock

SPI master/ slave select

[AFR1]

Timer 1 break input

[AFR4]

ADC external trigger [AFR4]

Port

C4

Port

C5

Timer 1 channel 3

Top level interrupt

[AFR3] Timer

1 - inverted channel 1

[AFR7]

Configurable clock output/Timer

1 - channel

4/Analog input 2

Timer 1 inverted channel 2

[AFR7]

SPI clock Timer 2 channel 1

[AFR0]

DocID018576 Rev 2 23/99

Pinout and pin description STM8S003K3 STM8S003F3

Pin no.

TSSOP20

16

UFQFPN20

13

Pin name

PC6/

SPI_MOSI

[TIM1_ CH1]

Input Output

Type floating wpu

Ext.

interr.

High sink

(1)

Speed OD PP

Main function

(after reset)

Default alternate function

I/O

X

X X HS O3 X X Port

C6

SPI master out/slave in

Alternate function after remap [option bit]

Timer 1 channel 1

[AFR0]

17 14

X

X X HS O3 X X Port

C7

18

19

20

15

16

17

PC7/

SPI_MISO

[TIM1_ CH2]

PD1/

SWIM

(4)

I/O

I/O

PD2/AIN3/[TIM2_

CH3]

I/O

PD3/ AIN4/

TIM2_ CH2/

ADC_ ETR

I/O

X

X

X

X

X

X

X

X

X

HS

HS

HS

O4

O3

O3

X

X

X

X

X

X

Port

D1

Port

D2

Port

D3

SPI master in/ slave out

Timer 1 channel 2

[AFR0]

SWIM data interface

Analog input 3

Timer 2 channel 3

[AFR1]

Analog input 4/

Timer 2 channel

2/ADC external trigger

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings.

(2)

When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.

(3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented).

(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

5.3

Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

24/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

6

6.1

Memory and register map

Memory map

Figure 6: Memory map

Memory and register map

0x00 0000

0x00 03FF

0x00 0800

RAM

(1 Kbyte)

513 bytes stack

Reserved

0x00 4000

0x00 407F

0x00 47FF

0x00 4800

0x00 480A

0x00 480B

Data EEPROM

Reserved

Option bytes

Reserved

0x00 4FFF

0x00 5000

0x00 57FF

0x00 5800

GPIO and periph. reg.

Reserved

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F

0x00 8080

0x00 9FFF

0x00 A000

CPU/SWIM/debug/ITC registers

32 interrupt vectors

Flash program memory

(8 Kbytes)

Reserved

0x02 7FFF

DocID018576 Rev 2 25/99

Memory and register map STM8S003K3 STM8S003F3

6.2

Register map

6.2.1

Address

I/O port hardware register map

Block

Table 7: I/O port hardware register map

Register label Register name

0x00 5010

0x00 5011

0x00 5012

0x00 5013

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

0x00 500F

Port A

Port B

Port C

Port D

Port E

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

PD_ODR

PA_ODR

PA_IDR

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PE_ODR

PE_IDR

PE_DDR

PE_CR1

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C control register 2

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

Port D control register 2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

0x00

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

Reset status

0x00

0xXX

(1)

0x00

0x00

0x00

0x00

0xXX

(1)

0x00

0x02

0x00

0x00

0xXX

(1)

0x00

0x00

26/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

Address

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

Block

Port E

Port F

Register label

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

(1)

Depends on the external circuitry.

Register name

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Memory and register map

Reset status

0x00

0x00

0xXX

(1)

0x00

0x00

0x00

6.2.2

Address

General hardware register map

Block

Table 8: General hardware register map

Register label Register name Reset status

0x00 501E to

0x00 5059

0x00 505A

0x00 505B

0x00 505C

0x00 505D

0x00 505E

0x00 505F

Reserved area (60 bytes)

Flash

FLASH_CR1 Flash control register 1 0x00

FLASH_CR2 Flash control register 2 0x00

FLASH_NCR2 Flash complementary control register 2 0xFF

FLASH _FPR Flash protection register 0x00

FLASH _NFPR Flash complementary protection register 0xFF

FLASH _IAPSR Flash in-application programming status register

0x00

Reserved area (2 bytes) 0x00 5060 to

0x00 5061

0x00 5062 Flash FLASH _PUKR Flash program memory unprotection register

0x00

DocID018576 Rev 2 27/99

Memory and register map STM8S003K3 STM8S003F3

Address Block Register label Register name Reset status

0x00 5063

0x00 5064

0x00 5065 to

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2 to

0x00 50B2

0x00 50B3

0x00 50B4 to

0x00 50BF

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

Reserved area (1 byte)

Flash FLASH_DUKR

Reserved area (59 bytes)

Data EEPROM unprotection register

ITC EXTI_CR1

EXTI_CR2

Reserved area (17 bytes)

RST RST_SR

Reserved area (12 bytes)

External interrupt control register 1

External interrupt control register 2

Reset status register

CLK CLK_ICKR

CLK_ECKR

Internal clock control register

External clock control register

Reserved area (1 byte)

CLK CLK_CMSR Clock master status register

Clock master switch register CLK_SWR

CLK_SWCR Clock switch control register

Clock divider register CLK_CKDIVR

CLK_PCKENR1 Peripheral clock gating register 1

CLK_CSSR

CLK_CCOR

Clock security system register

Configurable clock control register

CLK_PCKENR2 Peripheral clock gating register 2

0x00

0x00

0x00

0xXX

(1)

0x01

0x00

0xFF

0x00

0x00

0xFF

0xE1

0xE1

0xXX

0x18

28/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Memory and register map

Address

0x00 50CC

0x00 50CD

0x00 50F2

0x00 50F3

0x00 50F4 to

0x00 50FF

0x00 5200

0x00 5201

Block

BEEP

SPI

Register label Register name Reset status

CLK_HSITRIMR HSI clock calibration trimming register 0x00

CLK_SWIMCCR SWIM clock control register 0bXXXX

XXX0

0x00 50CE to

0x00 50D0

0x00 50D1

0x00 50D2

0x00 50D3 to 00

50DF

Reserved area (13 bytes)

IWDG 0x00 50E0

0x00 50E1

IWDG_KR

IWDG_PR

0x00 50E2

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1

ReservLK ed area (3 bytes)

WWDG

IWDG_RLR

Reserved area (13 bytes)

AWU

WWDG_CR

WWDG_WR

AWU_CSR1

AWU_APR

AWU_TBR

BEEP_CSR

Reserved area (12 bytes)

SPI_CR1

SPI_CR2

WWDG control register

WWDR window register

IWDG key register

IWDG prescaler register

IWDG reload register

AWU control/status register 1

AWU asynchronous prescaler buffer register

AWU timebase selection register

BEEP control/status register

SPI control register 1

SPI control register 2

0x7F

0x7F

0xXX

0x00

0xFF

0x00

0x3F

0x00

0x1F

0x00

0x00

(2)

DocID018576 Rev 2 29/99

Memory and register map

Address Block Register label Register name

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

0x00 5208 to

0x00 520F

0x00 5218

0x00 5219

0x00 521A

0x00 521B

SPI_ICR

SPI_SR

SPI_DR

SPI_CRCPR

SPI interrupt control register

SPI status register

SPI data register

SPI CRC polynomial register

SPI_RXCRCR SPI Rx CRC register

SPI Tx CRC register SPI_TXCRCR

Reserved area (8 bytes)

I

2

C I2C_CR1

I2C_CR2

I2C_FREQR

I2C_OARL

I2C_OARH

Reserved

I2C_DR

I2C_SR1

I2C_SR2

I2C_SR3

I2C_ITR

I2C_CCRL I

I

I

I

I

I

I

I

I

I

I

2

2

2

2

2

2

2

2

2

2

2

C control register 1

C control register 2

C frequency register

C Own address register low

C Own address register high

C data register

C status register 1

C status register 2

C status register 3

C interrupt control register

C Clock control register low

STM8S003K3 STM8S003F3

Reset status

0x00

0x02

0x00

0x07

0xFF

0xFF

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x0X

0x00

0x00

30/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

Address Block Register label Register name

0x00 521C

0x00 521D

0x00 521E

0x00 521F to

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

0x00 523B to

0x00 523F

0x00 5250

0x00 5251

I2C_CCRH

I2C_TRISER

I2C_PECR

Reserved area (17 bytes)

UART1

TIM1 TIM1_CR1

TIM1_CR2

I

I

I

2

2

2

C Clock control register high

C TRISE register

C packet error checking register

UART1_SR

UART1_DR

UART1 status register

UART1 data register

UART1_BRR1 UART1 baud rate register 1

UART1_BRR2 UART1 baud rate register 2

UART1_CR1

UART1_CR2

UART1_CR3

UART1_CR4

UART1 control register 1

UART1 control register 2

UART1 control register 3

UART1 control register 4

UART1_CR5

UART1_GTR

UART1 control register 5

UART1 guard time register

UART1_PSCR UART1 prescaler register

Reserved area (21 bytes)

TIM1 control register 1

TIM1 control register 2

Memory and register map

Reset status

0x00

0x02

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xC0

0xXX

0x00

0x00

0x00

0x00

0x00

DocID018576 Rev 2 31/99

Memory and register map

Block Address

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 5262

0x00 5263

0x00 5264

STM8S003K3 STM8S003F3

Register label

TIM1_SMCR

TIM1_ETR

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1_EGR

Register name Reset status

0x00 TIM1 slave mode control register

TIM1 external trigger register 0x00

0x00 TIM1 interrupt enable register

TIM1 status register 1 0x00

0x00 TIM1 status register 2

TIM1 event generation register 0x00

TIM1 capture/compare mode register 1 0x00 TIM1_CCMR1

TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00

TIM1_CCMR3

TIM1_CCMR4

TIM1_CCER1

TIM1_CCER2

TIM1 capture/compare mode register 3 0x00

TIM1 capture/compare mode register 4 0x00

TIM1 capture/compare enable register 1 0x00

TIM1 capture/compare enable register 2 0x00

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1 counter high

TIM1 counter low

TIM1 prescaler register high

TIM1 prescaler register low

TIM1 auto-reload register high

TIM1 auto-reload register low

TIM1 repetition counter register

0x00

0x00

0x00

0x00

0xFF

0xFF

0x00

32/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Memory and register map

Address

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5265

0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C

0x00 526D

0x00 526E

0x00 526F

0x00 5270 to

0x00 52FF

Block Register label

TIM1_CCR1H

Register name

TIM1 capture/compare register 1 high

Reset status

0x00

TIM1_CCR1L

TIM1_CCR2H

TIM1 capture/compare register 1 low

TIM1 capture/compare register 2 low

0x00

TIM1 capture/compare register 2 high 0x00

0x00 TIM1_CCR2L

TIM1_CCR3H TIM1 capture/compare register 3 high 0x00

TIM1 capture/compare register 3 low 0x00 TIM1_CCR3L

TIM1_CCR4H TIM1 capture/compare register 4 high 0x00

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1_OISR

Reserved area (147 bytes)

TIM1 capture/compare register 4 low

TIM1 break register

TIM1 dead-time register

TIM1 output idle state register

0x00

0x00

0x00

0x00

TIM2 TIM2_CR1

Reserved

Reserved

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2_EGR

TIM2 control register 1

TIM2 Interrupt enable register

TIM2 status register 1

TIM2 status register 2

TIM2 event generation register

0x00

0x00

0x00

0x00

0x00

DocID018576 Rev 2 33/99

Memory and register map STM8S003K3 STM8S003F3

Address

0x00 530F

0x00 5310

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315

0x00 5316

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

0x00 530C

0x00 530D

0x00 530E

Block Register label

TIM2_CCMR1

Register name Reset status

TIM2 capture/compare mode register 1 0x00

TIM2_CCMR2

TIM2_CCMR3

TIM2 capture/compare mode register 2

TIM2 capture/compare mode register 3

0x00

0x00

TIM2_CCER1

TIM2_CCER2

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_CCR3H

TIM2 capture/compare enable register 1 0x00

TIM2 capture/compare enable register 2 0x00

TIM2 counter high

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare reg. 2 high

TIM2 capture/compare register 2 low

TIM2 capture/compare register 3 low

0x00

0x00

0x00

0xFF

0xFF

0x00

0x00

0x00

0x00

TIM2 capture/compare register 3 high 0x00

0x00 TIM2_CCR3L

Reserved area (43 bytes)

TIM4 TIM4_CR1

Reserved

TIM4 control register 1 0x00

34/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Memory and register map

Address Block Register label Register name Reset status

0x00 53E0 to

0x00 53F3

0x00 53F4 to

0x00 53FF

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349 to

0x00 53DF

Reserved

TIM4_IER

TIM4_SR

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

Reserved area (153 bytes)

ADC1 ADC _DBxR

Reserved area (12 bytes)

ADC1 ADC _CSR

ADC_CR1

ADC_CR2

ADC_CR3

ADC_DRH

ADC_DRL

ADC_TDRH

ADC_TDRL

TIM4 interrupt enable register

TIM4 status register

TIM4 event generation register

TIM4 counter

TIM4 prescaler register

TIM4 auto-reload register

ADC data buffer registers 0x00

ADC control/status register

ADC configuration register 1

ADC configuration register 2

ADC configuration register 3

ADC data register high

ADC data register low

0xXX

0xXX

ADC Schmitt trigger disable register high 0x00

ADC Schmitt trigger disable register low 0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xFF

DocID018576 Rev 2 35/99

Memory and register map STM8S003K3 STM8S003F3

Address

0x00 5408

0x00 5409

0x00 540A

0x00 540B

0x00 540C

0x00 540D

0x00 540E

0x00 540F

Block Register label

ADC_HTRH

ADC_HTRL

ADC_LTRH

ADC_LTRL

ADC_AWSRH

ADC_AWSRL

Register name Reset status

0x03 ADC high threshold register high

ADC high threshold register low 0xFF

0x00 ADC low threshold register high

ADC low threshold register low 0x00

0x00 ADC analog watchdog status register high

ADC analog watchdog status register low 0x00

ADC _AWCRH ADC analog watchdog control register high

0x00

ADC_AWCRL ADC analog watchdog control register low

0x00

Reserved area (1008 bytes) 0x00 5410 to

0x00 57FF

(1)

Depends on the previous reset source.

(2)

Write only register.

6.2.3

Address

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

CPU/SWIM/debug module/interrupt controller registers

Table 9: CPU/SWIM/debug module/interrupt controller registers

Block Register label Register name

A Accumulator

PCE Program counter extended

CPU

(1)

PCH

PCL

XH

XL

Program counter high

Program counter low

X index register high

X index register low

Reset status

0x00

0x00

0x00

0x00

0x00

0x00

36/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Memory and register map

Address

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

0x00 7F0B to

0x00 7F5F

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

0x00 7F78 to

0x00 7F79

0x00 7F80

0x00 7F81 to

0x00 7F8F

0x00 7F90

Block

CPU

ITC

SWIM

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

DM

Register label

YH

YL

SPH

SPL

CCR

Register name

Y index register high

Y index register low

Stack pointer high

Stack pointer low

Condition code register

Reserved area (85 bytes)

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Global configuration register

Interrupt software priority register 1

Interrupt software priority register 2

Interrupt software priority register 3

Interrupt software priority register 4

Interrupt software priority register 5

Interrupt software priority register 6

Interrupt software priority register 7

Interrupt software priority register 8

Reserved area (2 bytes)

0x00

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

Reset status

0x00

0x00

0x03

0xFF

0x28

SWIM_CSR SWIM control status register

Reserved area (15 bytes)

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM_CR2

0x00

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

0xFF

0xFF

0xFF

0xFF

0xFF

0xFF

DM debug module control register 1 0x00

DM debug module control register 2 0x00

DocID018576 Rev 2 37/99

Memory and register map STM8S003K3 STM8S003F3

Address

0x00 7F98

0x00 7F99

Block

0x00 7F9A

0x00 7F9B to

0x00 7F9F

(1)

Accessible by debug module only

Register label

DM_CSR1

DM_CSR2

Register name

DM debug module control/status register 1

DM debug module control/status register 2

DM_ENFCTR DM enable function register

Reserved area (5 bytes)

Reset status

0x10

0x00

0xFF

38/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Interrupt vector mapping

7 Interrupt vector mapping

19

20

21

22

15

16

17

18

12

13

14

9

10

11

7

8

5

6

3

4

1

2

IRQ no.

Source block

RESET

0

TRAP

TLI

Description

Reset

Software interrupt

Table 10: Interrupt mapping

Wakeup from halt mode

Wakeup from active-halt mode

Vector address

Yes Yes 0x00 8000

External top level interrupt

-

-

-

-

0x00 8004

0x00 8008

AWU

CLK

EXTI0

EXTI1

Auto wake up from halt

Clock controller

Port A external interrupts

Port B external interrupts

-

-

Yes

(1)

Yes

Yes

-

Yes

(1)

Yes

0x00 800C

0x00 8010

0x00 8014

0x00 8018

EXTI2

EXTI3

EXTI4

SPI

TIM1

Port C external interrupts

Port D external interrupts

Port E external interrupts

Reserved

Reserved

End of transfer

TIM1 update/ overflow/ underflow/ trigger/ break

-

TIM1 capture/ compare -

-

-

Yes

Yes

Yes

Yes

Yes

Yes

-

Yes

-

-

Yes

0x00 801C

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

TIM1

TIM2

TIM2

UART1

UART1

I

2

C

-

-

-

-

-

-

-

-

-

Yes

-

-

-

Yes

-

-

-

-

-

-

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

0x00 804C

0x00 8050

0x00 8054

0x00 8058

0x00 805C

0x00 8060

ADC1

TIM2 update/ overflow

TIM2 capture/ compare

Reserved

Reserved

Tx complete

Receive register DATA FULL

I

2

C interrupt

Reserved

Reserved

ADC1 end of conversion/ analog watchdog interrupt

DocID018576 Rev 2 39/99

Interrupt vector mapping

IRQ no.

Source block

23 TIM4

24 Flash

Description

TIM4 update/ overflow

EOP/WR_PG_DIS

Reserved

(1)

Except PA1

STM8S003K3 STM8S003F3

Wakeup from halt mode

Wakeup from active-halt mode

Vector address

0x00 8064

0x00 8068

0x00 806C to

0x00 807C

40/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Option bytes

8 Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 11: Option bytes

Addr.

Option name

Option byte no.

Option bits

7 6 5

0x4800 Read-out protection

(ROP)

OPT0 ROP [7:0]

0x4801

0x4802

0x4803

User boot code(UBC)

OPT1

NOPT1

UBC [7:0]

NUBC [7:0]

Alternate function

0x4804 remapping

(AFR)

OPT2

NOPT2

AFR7

NAFR7

AFR6

AFR5

NAFR6 NAFR5

OPT3 Reserved 0x4805h Miscell.

option

0x4806 NOPT3 Reserved

4

AFR4

NAFR4

HSI

TRIM

NHSI

TRIM

0x4807 Clock option

0x4808

OPT4

NOPT4

Reserved

Reserved

3

AFR3

NAFR3

2

AFR2

NAFR2

1

AFR1

NAFR1

0

AFR0

NAFR0

LSI_ EN

NLSI_

EN

IWDG

_HW

NIWDG

_HW

WWDG

_HW

NWWDG

_HW

WWDG

_HALT

NWW

G_HALT

EXT CLK CKAWU

SEL

PRS C1 PRS C0

NEXT

CLK

NCKA

WUSEL

NPRSC1 NPR

SC0

Factory default setting

0x00

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x4809

0x480A

HSE clock startup

OPT5 HSECNT [7:0]

NOPT5 NHSECNT [7:0]

0x00

0xFF

Option byte no.

OPT0

Table 12: Option byte description

Description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)

DocID018576 Rev 2 41/99

Option bytes STM8S003K3 STM8S003F3

Option byte no.

OPT1

OPT2

OPT3

Description

Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM memory readout protection for details.

UBC[7:0] User boot code area

0x00: no UBC, no write-protection

0x01: Page 0 defined as UBC, memory write-protected

0x02: Pages 0 to 1 defined as UBC, memory write-protected.

Page 0 and 1 contain the interrupt vectors.

...

0x7F: Pages 0 to 126 defined as UBC, memory write-protected

Other values: Pages 0 to 127 defined as UBC, memory write-protected

Note: Refer to the family reference manual (RM0016) section on

Flash write protection for more details.

AFR[7:0]

Refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively.

HSITRIM:High speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register

1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

42/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Option bytes

Option byte no.

OPT4

OPT5

Description

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL:Auto wake-up unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]:HSE crystal oscillator stabilization time

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

8.1

Alternate function remapping bits

Table 13: STM8S003K3 alternate function remapping bits for 32-pin devices

Option byte no.

Description

(1)

OPT2

AFR7 Alternate function remapping option 7

Reserved.

AFR6 Alternate function remapping option 6

0: AFR6 remapping option inactive: Default alternate function

(2)

.

1: Port D7 alternate function = TIM1_CH4.

AFR5 Alternate function remapping option 5

0: AFR5 remapping option inactive: Default alternate function

(2)

.

DocID018576 Rev 2 43/99

Option bytes STM8S003K3 STM8S003F3

Option byte no.

Description

(1)

1: Port D0 alternate function = CLK_CCO.

AFR[4:2] Alternate function remapping options 4:2

Reserved.

AFR1 Alternate function remapping option 1

0: AFR1 remapping option inactive: Default alternate functions

(2)

.

1: Port A3 alternate function = SPI_NSS; port D2 alternate function

= TIM2_CH3.

AFR0 Alternate function remapping option 0

Reserved.

(1)

Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0.

(2)

Refer to pinout description.

Table 14: STM8S003F3 alternate function remapping bits for 20-pin devices

Option byte no.

Description

OPT2

AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactive: Default alternate functions

(1)

.

1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N.

AFR6 Alternate function remapping option 6

Reserved.

AFR5 Alternate function remapping option 5

Reserved.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: Default alternate functions

(1)

.

1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactive: Default alternate function

(1)

.

1: Port C3 alternate function = TLI.

AFR2 Alternate function remapping option 2

44/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Option bytes

Option byte no.

Description

Reserved

AFR1 Alternate function remapping option 1

(2)

0: AFR1 remapping option inactive: Default alternate functions

(1)

.

1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3.

AFR0 Alternate function remapping option 0

(2)

0: AFR0 remapping option inactive: Default alternate functions

(1)

.

1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1; port C7 alternate function = TIM1_CH2.

(1)

Refer to pinout description.

(2)

Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and AFR0.

DocID018576 Rev 2 45/99

Electrical characteristics

9

9.1

9.1.1

9.1.2

9.1.3

9.1.4

Electrical characteristics

STM8S003K3 STM8S003F3

Parameter conditions

Unless otherwise specified, all voltages are referred to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100 % of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

Amax

(given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ).

Typical values

Unless otherwise specified, typical data are based on T

A only as design guidelines and are not tested.

= 25 °C, V

DD

= 5 V. They are given

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in the following figure.

Figure 7: Pin loading conditions

STM8 pin

50 pF

9.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in the following figure.

46/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

Figure 8: Pin input voltage

STM8 pin

VIN

Electrical characteristics

9.2

Absolute maximum ratings

Symbol

V

DDx

- V

SS

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Ratings

Table 15: Voltage characteristics

Min

Supply voltage

(1)

-0.3

Max

6.5

Unit

V

IN

Input voltage on true open drain pins

(2)

V

SS

- 0.3

6.5

V

Input voltage on any other pin

(2)

V

SS

- 0.3

V

DD

+ 0.3

|V

DDx

- V

DD

|

Variations between different power pins

50 mV

|V

SSx

- V

SS

|

Variations between all the different ground pins

50

V

ESD

Electrostatic discharge voltage

See "Absolute maximum ratings

(electrical sensitivity)"

(1)

All power (V

DD

) and ground (V

SS

) pins must always be connected to the external power supply

(2)

I

INJ(PIN) must never be exceeded. This is implicitly insured if V

IN maximum is respected. If V cannot be respected, the injection current must be limited externally to the I

INJ(PIN) injection is induced by V

IN

>V

DD while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V

IN

IN

<V

SS

IN maximum value. A positive

. For true open-drain maximum must always be respected

Symbol

I

VDD

Ratings

Table 16: Current characteristics

Total current into V

DD power lines (source)

(2)

Max

(1)

100

Unit

mA

DocID018576 Rev 2 47/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

I

I

I

VSS

IO

INJ(PIN)

ΣI

(3) (4)

INJ(PIN)

(3)

Ratings

Total current out of V

SS ground lines (sink)

(2)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

Injected current on OSCIN pin

Injected current on any other pin

(5)

Total injected current (sum of all I/O and control pins)

(5)

Max

80

20

- 20

± 4

± 4

± 4

± 20

(1)

Unit

(1)

Data based on characterization results, not tested in production.

(2)

All power (V

DD

) and ground (V

SS

) pins must always be connected to the external supply.

(3)

I

INJ(PIN) must never be exceeded. This is implicitly insured if V

IN maximum is respected. If V

IN cannot be respected, the injection current must be limited externally to the I

INJ(PIN) maximum value. A positive injection is induced by V

IN

>V

DD while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V

IN

IN

<V

SS

. For true open-drain maximum must always be respected

(4)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins

I which may potentially inject negative current. Any positive injection current within the limits specified for

INJ(PIN) and ΣI

INJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.

(5)

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI

INJ(PIN) maximum current injection on four I/O port pins of the device.

Symbol

T

STG

T

J

Table 17: Thermal characteristics

Ratings

Storage temperature range

Value

-65 to +150

Maximum junction temperature 150

Unit

°C

48/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3

Symbol

f

CPU

V

DD

VCAP

(1)

P

D

(3)

T

A

T

J

Operating conditions

Table 18: General operating conditions

Parameter

Internal CPU clock frequency

Conditions

Standard operating voltage

C

EXT

: capacitance of external capacitor

ESR of external capacitor at 1 MHz

(2)

ESL of external capacitor

TSSOP20

Power dissipation at T

A

= 85 °C for suffix 6

UFQFPN20

LQFP32

Ambient temperature for 6 suffix Maximum power dissipation version

Junction temperature range for suffix 6

Min

0

2.95

Max

16

5.5

Unit

MHz

V

470

-

-

-

-

-

-40

-40

3300

0.3

15

238

220

330

85

105 nF

Ω nH mW

°C

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

(2)

This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

(3)

To calculate P value for T

Jmax

Dmax

(T

A

), use the formula P

Dmax

=(T

Jmax

- T

A

)/Θ given in the previous table and the value for Θ

JA

JA

(see

Thermal characteristics

) with the given in

Thermal characteristics

.

DocID018576 Rev 2 49/99

Electrical characteristics STM8S003K3 STM8S003F3

f

CPU (MHz)

Functionality not guaranteed in this area

16

12

8

4

0

Figure 9: f

CPUmax versus V

DD

Functionality guaranteed

@TA-40 to 85 °C

2.95

4.0

5.0

Supply voltage

5.5

Symbol

t

VDD t

TEMP

V

IT+

V

IT-

V

HYS(BOR)

Table 19: Operating conditions at power-up/power-down

Parameter Conditions Min Typ

2 V

DD rise time rate

V

DD fall time rate

(1)

Reset release delay V

DD rising

2

Power-on reset threshold 2.6

2.7

Brown-out reset threshold

Brown-out reset hysteresis

2.5

2.65

70

Max

1.7

2.85

2.8

Unit

μs/V ms

V mV

(1)

Reset is always generated after a t

TEMP minimum ooperating voltage (V

DD delay. The application must ensure that V

DD min) when the t

TEMP delay has elapsed.

is still above the

9.3.1

VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

EXT

V

CAP pin. C

EXT to the is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH.

Figure 10: External capacitor C

EXT

C

ESR ESL

Rleak

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

50/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3.2

Supply current characteristics

The current consumption is measured as described in

Pin input voltage

.

9.3.2.1

Total current consumption in run mode

The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at V

DD or V

SS

(no load)

All peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned.

Subject to general operating conditions for V

DD and T

A

.

Symbol

Table 20: Total current consumption with code execution in run mode at V

DD

= 5 V

Parameter Conditions Typ

Max

(1)

Unit

f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz) 2.3

HSE user ext. clock (16 MHz) 2

HSI RC osc. (16 MHz) 1.7

I

DD(RUN)

Supply current in run mode, code executed from RAM f

CPU

= f

MASTER

/128 =

125 kHz f

CPU

= f

MASTER

/128 =

15.625 kHz

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

0.86

0.7

0.46

2.35

2

0.87

0.58

mA f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.41

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

=

16 MHz f

CPU

= f

MASTER

=

2 MHz

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

I

DD(RUN)

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

/128 =

125 kHz f

CPU

= f

MASTER

/128 =

15.625 kHz

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8) f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz)

(2)

4.5

4.3

3.7

0.84

0.72

0.46

0.42

0.55

4.75

4.5

1.05

0.9

0.58

0.57

mA

DocID018576 Rev 2 51/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 21: Total current consumption with code execution in run mode at V

DD

= 3.3 V

Symbol Parameter Conditions Typ

Max

(1)

Unit

f

CPU

= f

MASTER

=

16 MHz

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

Supply current in run mode, code executed from RAM f

CPU

= f

MASTER

/

128 = 125 kHz f

CPU

= f

MASTER

/

128 = 15.625 kHz

HSI RC osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

1.8

2

1.5

0.81

0.7

0.46

2.3

2

0.87

0.58

f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.41

0.55

I

DD(RUN) f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz) f

CPU

= f

MASTER

=

2 MHz

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

/

128 = 125 kHz f

CPU

= f

MASTER

/

128 = 15.625 kHz

HSI RC osc. (16 MHz/8) f

CPU

= f

MASTER

=

128 kHz

HSI RC osc. (16 MHz/8)

HSI RC osc. (16 MHz)

LSI RC osc. (128 kHz)

(2)

4

3.9

3.7

0.84

0.72

0.46

0.42

4.7

4.5

1.05

0.9

0.58

0.57

mA

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

52/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3.2.2

Total current consumption in wait mode

Symbol

Table 22: Total current consumption in wait mode at V

DD

= 5 V

Parameter Conditions Typ

f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

I

DD(WFI)

Supply current in wait mode f

CPU

= f

MASTER

/128 =

125 kHz

HSI RC osc. (16 MHz) f

CPU

= f

MASTER

/128 =

15.625 kHz

HSI RC osc. (16 MHz/8)

(2)

Max

(1)

Unit

1.6

1.1

0.89

1.3

1.1

0.7

0.88

0.45

0.57

mA f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.4

0.54

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Symbol

Table 23: Total current consumption in wait mode at V

DD

= 3.3 V

Parameter Conditions Typ

Max

(1)

HSE crystal osc.

(16 MHz)

1.1

Unit

I

DD(WFI) f

CPU

= f

MASTER

=

16 MHz

HSE user ext. clock

(16 MHz)

HSI RC osc.

(16 MHz)

Supply current in wait mode f

CPU

= f

MASTER

/ 128 =

125 kHz

HSI RC osc.

(16 MHz) f

CPU

= f

MASTER

/ 128 =

15.625 kHz

HSI RC osc.

(16 MHz/8)

(2)

f

CPU

= f

MASTER

=

128 kHz

LSI RC osc.

(128 kHz)

1.1

0.89

0.7

0.45

0.4

1.3

1.1

0.88

0.57

0.54

mA

DocID018576 Rev 2 53/99

Electrical characteristics

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

STM8S003K3 STM8S003F3

9.3.2.3

Total current consumption in active halt mode

Symbol

Table 24: Total current consumption in active halt mode at V

DD

= 5 V

Conditions

Parameter

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Typ

I

DD(AH)

Supply current in active halt mode

On Operating mode

HSE crystal osc.

(16 MHz)

1030

Max at 85

°C

(1)

Unit

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

Off

I

DD(AH)

Supply current in active halt mode

Operating mode

Power-down mode

Power-down mode

Operating mode

Power-down mode

LSI RC osc.

(128 kHz)

200

HSE crystal osc.

(16 MHz)

970

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

150

66

10

260

200

85

20

μA

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Symbol

Table 25: Total current consumption in active halt mode at V

DD

= 3.3 V

Conditions

Parameter

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Typ

Max at

85 °C

(1)

I

DD(AH)

Supply current in active halt mode

On Operating mode

HSE crystal osc.

(16 MHz)

550

Unit

μA

54/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

I

I

DD(AH)

Supply current in active halt mode

I

DD(AH)

DD(AH)

Parameter

I

DD(AH)

Supply current in active halt mode

Conditions

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Operating mode

LSI RC osc.

(128 kHz)

On

Off

Power-down mode

Operating mode

HSE crystal osc.

(16 MHz)

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

I

DD(AH)

Power-down mode

Typ

200

970

150

66

10

Max at

85 °C

(1)

260

200

80

18

Unit

μA

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

9.3.2.4

Symbol

I

DD(H)

Total current consumption in halt mode

Table 26: Total current consumption in halt mode at V

DD

= 5 V

Parameter Conditions Typ

Max at 85

°C

(1)

Unit

Supply current in halt mode

Flash in operating mode, HSI clock after wakeup

Flash in power-down mode, HSI clock after wakeup

63

6.0

75

20

μA

(1)

Data based on characterization results, not tested in production

Symbol

I

DD(H)

Table 27: Total current consumption in halt mode at V

DD

= 3.3 V

Parameter Conditions Typ

Max at 85

°C

(1)

Unit

Supply current in halt mode

Flash in operating mode, HSI clock after wakeup

60 75 μA

DocID018576 Rev 2 55/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter Conditions Typ

Max at 85

°C

(1)

Unit

17

Flash in power-down mode, HSI clock after wakeup

(1)

Data based on characterization results, not tested in production

4.5

9.3.2.5

Low power mode wakeup times

Table 28: Wakeup times

Symbol Parameter Conditions

t

WU(WFI)

Wakeup time from wait mode to run mode

(3)

0 to 16 MHz

Wakeup time active halt mode to run mode

(3)

Typ

Max

(1)

Unit

See note

(2)

f

CPU

= f

MASTER

= 16 MHz 0.56

MVR voltage regulator on

(4)

Flash in operating mode

(5)

HSI

(after wakeup)

1

(6)

2

(6)

Wakeup time active halt mode to run mode

(3)

t

WU(AH)

Wakeup time active halt mode to run mode

(3)

t

WU(H)

Wakeup time active halt mode to run mode

(3)

Wakeup time from halt mode to run mode

(3)

MVR voltage regulator on

(4)

Flash in power-down mode

(5)

MVR voltage regulator off

(4)

Flash in operating mode

(5)

HSI

(after wakeup)

48

(6)

MVR voltage Flash in regulator off

(4)

power-down mode

(5)

Flash in operating mode

(5)

Flash in power-down mode

(5)

HSI

(after wakeup)

3

(6)

HSI

(after wakeup)

50

52

54

(6)

μs

(1)

Data guaranteed by design, not tested in production.

(2) t

WU(WFI)

= 2 x 1/f master

+ x 1/f

CPU.

56/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

(3)

Measured from interrupt event to interrupt vector fetch.

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

(6)

Plus 1 LSI clock depending on synchronization.

Electrical characteristics

9.3.2.6

Symbol

I

DD(R) t

RESETBL

Total current consumption and timing in forced reset state

Table 29: Total current consumption and timing in forced reset state

Parameter Conditions Typ

Max

(1)

Supply current in reset state

(2)

V

V

DD

DD

= 5 V

= 3.3 V

400

300

Reset pin release to vector fetch

150

Unit

μA

μs

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to V

SS

.

9.3.2.7

Symbol

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM4)

I

DD(UART1)

Current consumption of on-chip peripherals

Subject to general operating conditions for V

DD and T

A

.

HSI internal RC/f

CPU

= f

MASTER

= 16 MHz, V

DD

= 5 V

Table 30: Peripheral current consumption

Parameter Typ.

210

TIM1 supply current

(1)

TIM2 supply current

(1)

130

TIM4 timer supply current

(1)

50

UART1 supply current

(2)

120

I

DD(SPI)

SPI supply current

(2)

45

I

DD(I

2

C)

I

2

C supply current

(2)

65

I

DD(ADC1)

ADC1 supply current when converting

(3)

1000

DocID018576 Rev 2

Unit

μA

57/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on a differential I

DD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

(2)

Data based on a differential I

DD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.

Not tested in production.

(3)

Data based on a differential I

DD measurement between reset configuration and continuous A/D conversions. Not tested in production.

9.3.2.8

Current consumption curves

The following figures show typical current consumption measured with code executing in

RAM.

Figure 11: Typ I

DD(RUN) vs. V

DD

HSE user external clock, f

CPU

= 16 MHz

Figure 12: Typ I

DD(RUN) vs. f

CPU

HSE user external clock, V

DD

= 5 V

58/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 13: Typ I

DD(RUN) vs. V

DD

HSI RC osc, f

CPU

= 16 MHz

Figure 14: Typ I

DD(WFI) vs. V

DD

HSE user external clock, f

CPU

= 16 MHz

DocID018576 Rev 2 59/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 15: Typ I

DD(WFI) vs. f

CPU

HSE user external clock, V

DD

= 5 V

Figure 16: Typ I

DD(WFI) vs. V

DD

HSI RC osc, f

CPU

= 16 MHz

9.3.3

External clock sources and timing characteristics

Symbol

f

HSE_ext

V

HSEH

(1)

V

HSEL

(1)

I

LEAK_HSE

HSE user external clock

Subject to general operating conditions for V

DD and T

A

.

Parameter

Table 31: HSE user external clock characteristics

Conditions Min

User external clock source frequency

0

OSCIN input pin high level voltage

OSCIN input pin low level voltage

0.7 x V

DD

V

SS

OSCIN input leakage current V

SS

V

DD

< V

IN

<

-1

Max

16

V

DD

+ 0.3 V

0.3 x V

DD

+1

Unit

M z

V

μA

60/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

(1)

Data based on characterization results, not tested in production.

Figure 17: HSE external clock source

V

HSEH

V HSEL

External clock source

OSCIN fHSE

STM8

Symbol

f

I

HSE

R

C

F

(1)

DD(HSE)

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Parameter

Table 32: HSE oscillator characteristics

Conditions Min Typ Max

External high speed oscillator frequency

1 16

Unit

MHz

Feedback resistor

Recommended load capacitance

(2)

220

20 kΩ pF

HSE oscillator power consumption

C = 20 pF, f

OSC

= 16 MHz

6 (startup)

1.6 (stabilized)

(3)

mA

C = 10 pF, f

OSC

=16 MHz

6 (startup)

1.2 (stabilized)

(3)

g m

Oscillator transconductance t

SU(HSE)

(4)

Startup time V

DD is stabilized

5

1 mA/V ms

DocID018576 Rev 2 61/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

C is approximately equivalent to 2 x crystal Cload.

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R m value. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4) t

SU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16

MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 18: HSE oscillator circuit diagram

Rm

Lm

CO

Cm

Resonator

CL1

OSCIN

CL2

Resonator

OSCOUT f HSE to core

RF gm

Consumption control

STM8

9.3.4

Symbol

f

HSI

HSE oscillator critical g

g mcrit

= (2 × Π × f

HSE

)

2 m

equation

× R m

(2Co + C)

2

R m

: Notional resistance (see crystal specification)

L m

: Notional inductance (see crystal specification)

C m

: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

C

L1

= C

L2

= C: Grounded external capacitance g m

>> g mcrit

Internal clock sources and timing characteristics

Subject to general operating conditions for V

DD and T

A

.

High speed internal RC oscillator (HSI)

Parameter

Frequency

Table 33: HSI oscillator characteristics

Conditions Min Typ

16

Max Unit

MHz

62/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

I t

ACC

HSI su(HSI)

DD(HSI)

Parameter

Accuracy of HSI oscillator

Conditions

User-trimmed with

CLK_HSITRIMR register for given V

DD and T

A conditions

(1)

Min

Accuracy of HSI oscillator (factory calibrated)

V

DD

= 5 V,

25 °C ≤ T

A

≤ 85 °C

HSI oscillator wakeup time including calibration

HSI oscillator power consumption

-5

(1)

Refer to application note.

(2)

Data based on characterization results, not tested in production.

(3)

Guaranteed by design, not tested in production.

Typ

170

Max

5

1.0

1.0

250

(3)

(3)

(2)

Figure 19: Typical HSI frequency variation vs V

DD

@ 4 temperatures

Unit

%

μs

μA

DocID018576 Rev 2 63/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

f

LSI t su(LSI)

I

DD(LSI)

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for V

DD and T

A

.

Parameter

Frequency

Table 34: LSI oscillator characteristics

Typ Max

128

LSI oscillator wake-up time

7

LSI oscillator power consumption

5

Unit

kHz

μs

μA

Figure 20: Typical LSI frequency variation vs V

DD

@ 4 temperatures

9.3.5

Memory characteristics

RAM and hardware registers

Symbol Parameter

Table 35: RAM and hardware registers

Conditions

V

RM

Data retention mode

(1)

Halt mode (or reset)

Min

V

IT-max

(2)

Unit

V

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.

(2)

Refer to the Operating conditions section for the value of V

IT-max

64/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Flash program memory and data EEPROM

Symbol

Table 36: Flash program memory and data EEPROM

Parameter Conditions Typ

Min

(1)

Max

V

DD

I t t t prog erase

N

RW

RET

DD

Operating voltage (all modes, execution/ write/erase)

Standard programming time

(including erase) for byte/word/block (1 byte/

4 bytes/64 bytes)

Fast programming time for

1 block (64 bytes) f

CPU

≤ 16 MHz

Erase time for 1 block

(64 bytes)

Erase/write cycles

(2)

(program memory)

Erase/write cycles

(2)

(data memory)

Data retention (program memory) after 100 erase/write cycles at T

A

85 °C

=

Data retention (data memory) after 10 k erase/write cycles at T

A

85 °C

=

Data retention (data memory) after 100 k erase/write cycles at T

A

85 °C

=

Supply current (Flash programming or erasing for 1 to 128 bytes)

T

T

T

A

= 85 °C

RET

RET

= 55°C

= 85°C

2.95

100

100 k

20

20

1

6

3

3

2

5.5

6.6

3.33

3.33

Unit

V ms cycles years mA

DocID018576 Rev 2 65/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

9.3.6

Symbol

V

IL

V

IH

V hys

R pu t

R

, t

F

I lkg

I lkg ana

I lkg(inj)

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

DD and T

A unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Parameter

Table 37: I/O static characteristics

Conditions Min

Input low level voltage

V

DD

= 5 V

-0.3 V

Typ

Input high level voltage

0.7 x

V

DD

Max

0.3 x

V

DD

V

DD

+

0.3

Unit

V

Hysteresis

(1)

Pull-up resistor

V

DD

= 5 V, V

IN

= V

SS

Rise and fall time

(10 % - 90 %)

Fast I/Os

Load = 50 pF

Standard and high sink

I/Os

Load = 50 pF

Digital input leakage current

V

SS

≤ V

IN

≤V

DD

Analog input leakage current

V

SS

≤ V

IN

≤ V

DD

Leakage current in adjacent

I/O

Injection current ±4 mA

30

700

55 80

20

(2)

125

(2)

±1

(2)

μA

±250

(2)

nA

±1

(2)

mV kΩ ns

μA

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

(2)

Data based on characterisation results, not tested in production.

66/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 21: Typical V

IL and V

IH vs V

DD

@ 4 temperatures

Figure 22: Typical pull-up resistance vs V

DD

@ 4 temperatures

DocID018576 Rev 2 67/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 23: Typical pull-up current vs V

DD

@ 4 temperatures

68/99

Symbol

Table 38: Output driving current (standard ports)

Parameter Conditions Min

Output low level with 8 pins sunk I

IO

= 10 mA,

V

DD

= 5 V

V

OL

Output low level with 4 pins sunk I

IO

= 4 mA,

V

DD

= 3.3 V

Output high level with 8 pins sourced

V

OH

Output high level with 4 pins sourced

I

IO

= 10 mA,

V

DD

= 5 V

I

IO

= 4 mA,

V

DD

= 3.3 V

2.8

2.1

(1)

Max Unit

2.0

1.0

(1)

V

(1)

Data based on characterization results, not tested in production

Symbol

V

OL

Table 39: Output driving current (true open drain ports)

Parameter Conditions Max

Output low level with 2 pins sunk

I

IO

= 10 mA, V

DD

5 V

= 1 .0

V

OL

Output low level with 2 pins sunk

I

IO

= 10 mA, V

DD

3.3 V

= 1.5

(1)

Unit

V

DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

V

OL

Parameter

Output low level with 2 pins sunk

Conditions Max

I

IO

= 20 mA, V

DD

5 V

=

2.0

(1)

Unit

(1)

Data based on characterization results, not tested in production

Symbol

V

V

V

OL

OL

OH

Table 40: Output driving current (high sink ports)

Parameter Conditions Min

Output low level with 8 pins sunk

I

IO

= 10 mA,

V

DD

= 5 V

Output low level with 4 pins sunk

Output low level with 4 pins sunk

I

IO

= 10 mA,

V

DD

= 3.3 V

I

IO

= 20 mA,

V

DD

= 5 V

Output high level with 8 pins sourced

Output high level with 4 pins sourced

Output high level with 4 pins sourced

I

IO

= 10 mA,

V

DD

= 5 V

I

IO

= 10 mA,

V

DD

= 3.3 V

I

IO

= 20 mA,

V

DD

= 5 V

4.0

2.1

3.3

(1)

(1)

Max

0.8

1.0

1.5

(1)

(1)

Unit

V

V

(1)

Data based on characterization results, not tested in production

DocID018576 Rev 2 69/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 24: Typ. V

OL

@ V

DD

= 5 V (standard ports)

Figure 25: Typ. V

OL

@ V

DD

= 3.3 V (standard ports)

70/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 26: Typ. V

OL

@ V

DD

= 5 V (true open drain ports)

Figure 27: Typ. V

OL

@ V

DD

= 3.3 V (true open drain ports)

DocID018576 Rev 2 71/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 28: Typ. V

OL

@ V

DD

= 5 V (high sink ports)

Figure 29: Typ. V

OL

@ V

DD

= 3.3 V (high sink ports)

72/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 30: Typ. V

DD

- V

OH

@ V

DD

= 5 V (standard ports)

Figure 31: Typ. V

DD

- V

OH

@ V

DD

= 3.3 V (standard ports)

DocID018576 Rev 2 73/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 32: Typ. V

DD

- V

OH

@ V

DD

= 5 V (high sink ports)

Figure 33: Typ. V

DD

- V

OH

@ V

DD

= 3.3 V (high sink ports)

9.3.7

Symbol

V

IL(NRST)

Reset pin characteristics

Subject to general operating conditions for V

DD and T

A unless otherwise specified.

Parameter

Table 41: NRST pin characteristics

Conditions Min Typ Max Unit

NRST input low

-0.3 V 0.3 x V

DD

V

74/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Unit Symbol

t t

V

V

R

IH(NRST)

OL(NRST)

PU(NRST)

I FP(NRST) t

IN FP(NRST)

OP(NRST)

Parameter

level voltage

(1)

Conditions

NRST input high level voltage

(1)

I

OL

=2 mA

NRST output low level voltage

(1)

NRST pull-up resistor

(2)

NRST input filtered pulse

(3)

NRST input not filtered pulse

(3)

NRST output pulse

(3)

Min

0.7 x V

30

500

20

DD

Typ

55

(1)

Data based on characterization results, not tested in production.

(2)

The R

PU pull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

Max

V

DD

0.5

80

75

+ 0.3

kΩ ns

μs

DocID018576 Rev 2 75/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 34: Typical NRST V

IL and V

IH vs V

DD

@ 4 temperatures

Figure 35: Typical NRST pull-up resistance vs V

DD

@ 4 temperatures

76/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 36: Typical NRST pull-up current vs V

DD

@ 4 temperatures

The reset network shown in the following figure protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below V

IL

(NRST) max. (see

#unique_55/CD662

), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

Figure 37: Recommended reset pin protection

External reset circuit

(optional)

0.1 µF

NRST

VDD

RPU

Filter

Internal reset

STM8

9.3.8

SPI serial peripheral interface

Unless otherwise specified, the parameters given in the following table are derived from tests t performed under ambient temperature, f

MASTER

MASTER

= 1/f

MASTER

.

frequency and V

DD supply voltage conditions.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

DocID018576 Rev 2 77/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter

SPI clock frequency f

SCK

1/ t c(SCK)

Table 42: SPI characteristics

Conditions

(1)

Min

Master mode

0

Max Unit

t t t f

SCK

1/ t c(SCK) f

SCK

1/ t c(SCK) r(SCK) f(SCK) su(NSS) t h(SO)

(3)

t h(MO)

(3)

(3)

Data output hold time

Data output hold time

SPI clock frequency

SPI clock rise and Capacitive load: C = 30 pF fall time

NSS setup time Slave mode t h(NSS)

(3)

t w(SCKH)

(3)

t w(SCKL)

(3)

t su(MI)

(3)

t su(SI)

(3)

t h(MI)

(3)

t h(SI)

(3)

t a(SO)

(3) (4)

NSS hold time Slave mode

SCK high and low Master mode time t dis(SO)

(3) (5)

Data output disable time t v(SO)

(3)

Data input setup time

Data input hold time

Data output access time

Data output valid time

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

Slave mode

(after enable edge) t v(MO)

(3)

Data output valid time

Master mode

(after enable edge)

Slave mode

(after enable edge)

Master mode

(after enable edge)

0 7

(2)

4 x t

MASTER

70 t

SCK

/

2 - 15 t

SCK

/

2 +15

5

5

7

10

25

27

11

(2)

(2)

t

8

25

3 x

MASTER

65

30

(2)

ns

MHz

MHz

78/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

(1)

Parameters are given by selecting 10 MHz I/O output frequency.

(2)

Data characterization in progress.

(3)

Values based on design simulation and/or characterization results, and not tested in production.

(4)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

(5)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 38: SPI timing diagram - slave mode and CPHA = 0

NSS input tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL)

MISO ta(SO)

OUT P UT tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN th(NSS) tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN

Figure 39: SPI timing diagram - slave mode and CPHA = 1

ai14134

NSS input tSU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 tw(SCKH) tw(SCKL)

MISO

OUT P UT ta(SO) tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT th(SI)

M SB IN B I T1 IN th(SO)

BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)

LSB OUT

LSB IN ai14135

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

DocID018576 Rev 2 79/99

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

STM8S003K3 STM8S003F3

Figure 40: SPI timing diagram - master mode

(1)

tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTUT tsu(MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

9.3.9

I

2

C interface characteristics

Symbol Parameter

Table 43: I

2

C characteristics

Standard mode I

2

C

t w(SCLL) t w(SCLH)

SCL clock low time

SCL clock high time

SDA setup time t su(SDA) t h(SDA)

SDA data hold time t r(SDA) t r(SCL)

SDA and SCL rise time t f(SDA) t f(SCL) t h(STA) t su(STA)

SDA and SCL fall time

START condition hold time 4.0

Repeated START condition setup time 4.7

Min

(2)

4.7

4.0

250

0

(3)

Max

(2)

Fast mode I

2

C

(1)

Unit

Min

1.3

0.6

100

0

(4)

(2)

Max

(2)

900

(3)

μs

1000

300

0.6

0.6

300

300 ns

μs

80/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol Parameter

Standard mode I

Min

4.0

(2)

2

C

Max

(2)

Fast mode I

2

C

(1)

Unit

Min

0.6

(2)

Max

(2)

t su(STO)

STOP condition setup time t w(STO:STA)

STOP to START condition time

(bus free)

C b

Capacitive load for each bus line

4.7

400

1.3

400

μs pF

(1) f

MASTER

, must be at least 8 MHz to achieve max fast I

2

C speed (400kHz)

(2)

Data based on standard I

2

C protocol requirement, not tested in production

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL

Figure 41: Typical application with I

2

C bus and timing diagram

I

2

C bus

4.7k

V

DD

4.7k

V

DD

100

100

SDA

SCL

STM8S

START

SDA t f(SDA)

SCL t r(SDA) t h(STA) t w(SCLH) t w(SCLL) t su(SDA) t h(SDA) t r(SCL) t f(SCL) t su(STA)

REPEATED

START t w(STO:STA)

START t su(STO)

STOP ai17490

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.

9.3.10

10-bit ADC characteristics

Subject to general operating conditions for V

DD

, f

MASTER

, and T

A unless otherwise specified.

DocID018576 Rev 2 81/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter

f

ADC

ADC clock frequency

Table 44: ADC characteristics

Conditions Min Typ Max Unit

1 4 V

DD

=2.95 to 5.5 V

V

DD

=4.5 to 5.5 V 1 6

MHz

V

AIN

Conversion voltage range

(1)

V

SS

V

DD

V

C

ADC

Internal sample and hold capacitor t

S

(1)

Minimum sampling time f

ADC

= 4 MHz f

ADC

= 6 MHz t

STAB

Wake-up time from standby t

CONV

Minimum total conversion time

(including sampling time,

10-bit resolution) f

ADC

= 4 MHz f

ADC

= 6 MHz

3.5

2.33

3

0.75

0.5

7 pF

μs

μs

μs

μs

14 1/f

ADC

(1)

During the sample time the input capacitance C

AIN

(3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

S.

After the end of the sample time t

S

, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t

S depend on programming.

Symbol

|E

T

|

Table 45: ADC accuracy with R

AIN

< 10 kΩ , V

DD

= 5 V

Parameter Conditions Typ Max

(1)

Unit

Total unadjusted error

(2)

f

ADC

= 2 MHz 1.6

3.5

2.2

4 f

ADC

= 4 MHz f

ADC

= 6 MHz 2.4

4.5

LSB

|E

O

| Offset error

(2)

f

ADC

= 2 MHz 1.1

2.5

82/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

|E

|E

|E

G

D

L

|

|

|

Parameter

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2)

Conditions

f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz

Typ

1.5

1.8

1.5

2.1

2.2

0.7

0.7

0.7

0.6

0.8

0.8

Max

(1)

3

3

3

3

4

1.5

1.5

1.5

1.5

2

2

Unit

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I

INJ(PIN) port pin characteristics section does not affect the ADC accuracy.

and ΣI

INJ(PIN) in the I/O

Symbol

Table 46: ADC accuracy with R

AIN

< 10 kΩ R

AIN

, V

DD

= 3.3 V

Parameter Conditions Typ Max

(1)

Unit

|E

T

| Total unadjusted error

(2)

f

ADC

= 2 MHz 1.6

3.5

1.9

4 LSB

|E

O

| Offset error

(2)

f

ADC

= 4 MHz f

ADC

= 2 MHz 1 2.5

DocID018576 Rev 2 83/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

|E

|E

|E

G

D

L

|

|

|

Parameter

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2)

Conditions

f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz

Typ

1.5

1.3

2

0.7

0.7

0.6

0.8

Max

2.5

3

3

1

1.5

1.5

2

(1)

Unit

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I

pin characteristics

does not affect the ADC accuracy.

INJ(PIN) and ΣI

INJ(PIN) in

I/O port

Figure 42: ADC accuracy characteristics

84/99

1. Example of an actual transfer curve.

2. The ideal transfer curve

DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

3. End point correlation line

E

T

= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

E

O

= Offset error: deviation between the first actual transition and the first ideal one.

E

G

= Gain error: deviation between the last ideal transition and the last actual one.

E

D

= Differential linearity error: maximum deviation between actual steps and the ideal one.

E

L

= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

Figure 43: Typical application with ADC

VAIN

RAIN

CAIN

AINx

VDD

VT

0.6 V

VT

0.6 V

IL

± 1 µA

10-bit A/D conversion

STM8

CADC

9.3.11

EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

9.3.11.1

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to V

DD and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers).

9.3.11.2

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

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Electrical characteristics STM8S003K3 STM8S003F3

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance).

Symbol

V

FESD

Parameter

Table 47: EMS data

Conditions Level/ class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

V

DD

= 3.3 V, T

A

= 25 °C, f

MASTER

= 16 MHz

(HSI clock), conforming to IEC 61000-4-2

2/B

(1)

V

EFTB

Fast transient voltage burst limits to be applied through 100 pF on V

DD and V

SS pins to induce a functional disturbance

V

DD

= 3.3 V, T

A

= 25 °C ,f

MASTER

= 16 MHz

(HSI clock),conforming to IEC 61000-4-4

4/A

(1)

(1)

Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers).

9.3.11.3

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE

IEC 61967-2 which specifies the board and the loading of each pin.

Table 48: EMI data

Conditions

Symbol Parameter

General conditions

Max f

HSE

/f

CPU

(1)

Monitored frequency band

16 MHz/ 16 MHz/

8 MHz 16 MHz

Unit

S

EMI

Peak level V

DD

= 5 V

T

A

= 25 °C

LQFP32 package

0.1 MHz to

30 MHz

30 MHz to

5

4

5

5 dBμV

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STM8S003K3 STM8S003F3 Electrical characteristics

Conditions

Symbol Parameter

General conditions

Max f

HSE

/f

CPU

(1)

Monitored frequency band

16 MHz/ 16 MHz/

8 MHz 16 MHz

Conforming to

SAE IEC

61967-2

130 MHz

130 MHz to

1 GHz

5 5

SAE EMI level

SAE EMI level

2.5

2.5

(1)

Data based on characterisation results, not tested in production.

Unit

9.3.11.4

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

9.3.11.5

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:

Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.

Table 49: ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value

(1)

Unit

V

ESD(HBM)

Electrostatic discharge voltage

(Human body model)

V

ESD(CDM)

Electrostatic discharge voltage

(Charge device model)

T

A

= 25°C, conforming to

JESD22-A114

A

T

A

LQFP32 package =

25°C, conforming to

SD22-C101

IV

4000

1000

V

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Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on characterization results, not tested in production

9.3.11.6

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance:

A supply overvoltage (applied to each power supply pin)

A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter

Table 50: Electrical sensitivities

Conditions

LU Static latch-up class

T

A

= 25 °C

T

A

= 85 °C

Class

(1)

A

A

(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

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10

10.1

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

® packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com. ECOPACK

® is an ST trademark.

32-pin LQFP package mechanical data

Figure 44: 32-pin low profile quad flat package (7 x 7)

ccc C

24 b

25

32

Pin 1 identification

1

D

D1

D3

17

16

8

9

E3 E1 E c

A

A2

A1

L1

L

K

5V_ME c

D

D1

A

A1

A2 b

Dim.

Table 51: 32-pin low profile quad flat package mechanical data mm inches

(1)

Min Typ Min Typ

0.050

1.350

0.300

0.090

8.800

6.800

1.400

0.370

9.000

7.000

Max

1.600

0.150

1.450

0.450

0.200

9.200

7.200

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.0551

0.0146

0.3543

0.2756

Max

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

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Package information STM8S003K3 STM8S003F3

Dim.

mm

Min inches

(1)

Min

E3 e

L

L1

D3

E

E1 k ccc

8.800

6.800

0.450

Typ

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

Max

9.200

7.200

0.750

0.3465

0.2677

0.0177

Typ

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5° 0.0° 7.0°

0.100

0.0°

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

Max

0.3622

0.2835

0.0295

7.0°

0.0039

10.2

20-pin TSSOP package mechanical data

Figure 45: 20-pin, 4.40 mm body, 0.65 mm pitch

D

20 11

E1 E

1 10 aaa

CP

A b e

A2

A1

L1

L

YA_ME k c

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STM8S003K3 STM8S003F3 Package information

Dim.

c

D

E

E1

A

A1

A2 b e

L

L1 k aaa

Table 52: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data mm inches

(1)

Min Typ Min Typ

0.050

0.800

0.190

0.090

6.400

6.200

4.300

0.450

0.0°

1.000

6.500

6.400

4.400

0.650

0.600

1.000

Max

1.200

0.150

1.050

0.300

0.200

6.600

6.600

4.500

0.750

8.0°

0.100

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

0.0177

0.0°

0.0394

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

Max

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.2598

0.1772

0.0295

8.0°

0.0039

DocID018576 Rev 2 91/99

Package information STM8S003K3 STM8S003F3

10.3

20-lead UFQFPN package mechanical data

Figure 46: 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3)

L4 b

5

1

20

L3

D e

10

11

L1 e

L2

E

15

16

A3 ddd

A1

A

103_A0A5_ME

1. Drawing is not to scale.

e

L1

L2

L3

Table 53: 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data

Dim.

mm inches

(1)

Min Typ Max Min Typ Max

D 3.000

0.1181

E

A

A1

A3

0.500

0.000

3.000

0.550

0.020

0.152

0.600

0.050

0.0197

0.0000

0.1181

0.0217

0.0008

0.0060

0.0236

0.0020

L4 b ddd

0.500

0.300

0.180

0.050

0.500

0.550

0.350

0.150

0.200

0.250

0.600

0.400

0.300

0.0197

0.0118

0.0071

0.0020

0.0197

0.0217

0.0138

0.0059

0.0079

0.0098

0.0236

0.0157

0.0118

(1)

Values in inches are converted from mm and rounded to 4 decimal digits.

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11 Thermal characteristics

Thermal characteristics

The maximum chip junction temperature (T

J max

) must never exceed the values given in

Operating conditions

.

The maximum chip-junction temperature, T

Jmax

, in degrees Celsius, may be calculated using the following equation:

T

Jmax

= T

Amax

+ (P

Dmax x Θ

JA

)

Where:

T

Amax is the maximum ambient temperature in °C

Θ

JA is the package junction-to-ambient thermal resistance in °C/W

P

Dmax is the sum of P

INTmax and P

I/Omax

(PDmax = P

INTmax

+ P

I/Omax

)

P

INTmax is the product of I

DD andV

DD

, expressed in Watts. This is the maximum chip internal power.

P

I/Omax represents the maximum power dissipation on output pins

Where: P

I/Omax

V

OH

/I

OH

=Σ (V

OL

*I

OL

) + Σ((V

DD

-V

OH

)*I

OH

), taking into account the actual V of the I/Os at low and high level in the application.

OL

/I

OL and

Symbol

Θ

JA

Θ

JA

Θ

JA

Table 54: Thermal characteristics

Parameter

(1)

Value

Thermal resistance junction-ambient

TSSOP20 - 4.4 mm

Thermal resistance junction-ambient

UFQFPN20 - 3 x 3 mm

Thermal resistance junction-ambient

LQFP32 - 7 x 7 mm

84

90

60

Unit

°C/W

(1)

Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

11.1

11.2

Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural convection

(still air). Available from www.jedec.org.

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code.

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Thermal characteristics STM8S003K3 STM8S003F3

The following example shows how to calculate the temperature range needed for a given application.

Assuming the following application conditions:

Maximum ambient temperature T

Amax

= 75 °C (measured according to JESD51-2)

I

DDmax

= 8 mA, V

DD

= 5 V

Maximum 20 I/Os used at the same time in output at low level with

I

OL

= 8 mA, V

OL

= 0.4 V

P

INTmax =

8 mA x 5 V = 400 mW

Amax

P

Dmax =

400 mW +

64 mW

Thus: P

Dmax

= 464 mW

T

Jmax for LQFP32 can be calculated as follows, using the thermal resistance Θ

JA

:

T

Jmax

= 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C

This is within the range of the suffix 6 version parts (-40 < T

J

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6.

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STM8S003K3 STM8S003F3

12 Ordering information

Ordering information

Figure 47: STM8S003x value line ordering information scheme

Example:

Product class

STM8 microcontroller

Family type

S = Standard

Sub-family type

00x = Value line

003 sub-family

Pin count

K = 32 pins

F = 20 pins

Program memory size

3 = 8 Kbytes

Package type 1

T = LQFP

P = TSSOP

U = UFQFPN

Temperature range

6 = -40 °C to 85 °C

Package pitch

Blank = 0.5 or 0.65 mm(1)

C = 0.8 mm(2)

Packing

No character = Tray or tube

TR = Tape and reel

STM8 S 003 K 3 T 6 TR

1. TSSOP and UFQFPN package.

2. LQFP package.

For a list of available options (e.g. package, packing) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales

Office nearest to you.

DocID018576 Rev 2 95/99

STM8 development tools

13

13.1

STM8S003K3 STM8S003F3

STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the

STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.

STice key features

Occurrence and time profiling and code coverage (new features)

Advanced breakpoints with up to 4 levels of conditions

Data breakpoints

Program and data trace recording up to 128 KB records

Read/write on the fly of memory during emulation

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements

Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8.

13.2

Software tools

STM8 development tools are supported by a complete, free software package from

STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual

Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code.

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STM8S003K3 STM8S003F3 STM8 development tools

13.2.1

13.2.2

STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

Seamless integration of C and ASM toolsets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface.

Available toolchains include:

Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com.

Raisonance C compiler for STM8 – Available in a free version that outputs up to

16 Kbytes of code. For more information, see www.raisonance.com.

STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code.

13.3

Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

DocID018576 Rev 2 97/99

Revision history

14 Revision history

Date

12-Jul-2011

09-Jan-2012

STM8S003K3 STM8S003F3

Table 55: Document revision history

Revision

1

2

Changes

Initial revision.

Added N

RW and t

RET for data EEPROM in

Table 36:

Flash program memory and data EEPROM

.

Updated R

PU in

Table 41: NRST pin characteristics

Table 37: I/O static characteristics

.

and

Updated notes related to V

CAP

operating conditions

.

in

Table 18: General

98/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

Please Read Carefully

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(“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

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