Renesas R5F1026AASP#V0 datasheet: pdf

Renesas R5F1026AASP#V0 datasheet: pdf
Datasheet
RL78/G12
R01DS0193EJ0100
Rev.1.00
Dec 10, 2012
RENESAS MCU
True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation,
2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.8V to 5.5V operation from a single supply
• Stop (RAM retained): 0.23µA, (LVD enabled): 0.31µA
• Snooze: 0.7mA (UART), 1.20mA (ADC)
• Operating: 63 µA /MHz
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Main Flash Memory
• Density: 2 KB to 16 KB
• Block size: 1KB
• On-chip single voltage flash memory with protection
from block erase/writing
Data Flash Memory
• Data Flash with background operation
• Data flash size: 2 KB size options
• Erase Cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 256 B to 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed Oscillator Oscillator
• 24MHz with +/- 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (-40°C to 85°C)
• Pre-configured settings: 24MHz, 16MHz, 12MHz,
8MHz, 4MHz & 1MHz
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
• Up to 3 x I2C master
• Up to 1 x I2C multi-master
• Up to 3 x CSI/SPI (7-, 8-bit)
• Up to 3 x UART (7-, 8-, 9-bit)
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer : 1 channel (window function)
Rich Analog
• ADC: Up to 11 channels, 10-bit resolution, 2.1µs
conversion time
• Supports 1.8V
• Internal voltage reference (1.45V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/ frequency detection
• ADC self-test
General Purpose I/O
• 5V tolerant, high-current (up to 20mA per pin)
• Open-Drain, Internal Pull-up support
Operating Ambient Temperature
• Standard: –40°C to +85°C
Package Type and Pin Count
• QFN: 24
• SSOP: 20, 30
* There is difference in specifications between every product.
Please refer to specification for details.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 1 of 61
RL78/G12
CHAPTER 1 OUTLINE
 ROM, RAM capacities
Flash ROM
Data flash
RAM
20 pins
24 pins
30 pins
16 KB
2 KB
2 KB
−
−
R5F102AA
−
−
−
2 KB
1.5 KB
−
12 KB
2KB
1 KB
−
8 KB
2 KB
2KB
768B
2 KB
512B
256B
−
Note
Note
R5F103AA
R5F1027A
Note
−
R5F1037A
Note
−
Note
R5F102A9
Note
R5F103A9
Note
R5F102A8
Note
R5F103A8
Note
R5F10279
Note
R5F10379
Note
R5F10278
Note
R5F10378
R5F10269
R5F10268
R5F10368
−
2 KB
R5F1036A
R5F10369
−
4 KB
R5F1026A
Note
R5F10267
R5F10277
R5F102A7
R5F10367
R5F10377
R5F103A7
R5F10266
−
−
R5F10366
−
−
This is about 639 byte when the self-programing function and data flash function are used (For detail, see
CHAPTER 3 CPU ARCHITECTURE in the RL78/G12 User’s Manual).
1.2 Ordering Information
Pin
count
Package
20 pins
20-pin plastic
SSOP
(4.4 × 6.5)
24 pins
30 pins
Note
24-pin plastic
WQFN
(4 × 4)
30-pin plastic
SSOP
(7.62 mm
(300) )
Fields
of
Applica
tion
Part Number
Mounted
A
R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP
R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP
Not mounted
D
R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP
R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP
Mounted
A
R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA
R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA
Not mounted
D
R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA
R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA
Mounted
A
R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP
R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP
Not mounted
D
R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP
R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP
Data flash
For fields of application, see Figure 1-1. Part Number, Memory Size, and Package of RL78/G12.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 2 of 61
RL78/G12
CHAPTER 1 OUTLINE
Figure 1-1. Part Number, Memory Size, and Package of RL78/G12
Part No. R 5 F 1 0 2 A A A x x x S P
Package type:
SP : SSOP, 0.65 mm pitch
NA : WQFN, 0.50 mm pitch
ROM number (Omitted with blank products)
Classification:
A : Consumer applications, operating ambient temperature : -40˚C to 85˚C
D : Industrial applications, operating ambient temperature : -40˚C to 85˚C
ROM capacity:
6 :
7:
8:
9 :
A :
2 KB
4 KB
8 KB
12 KB
16 KB
Pin count:
6 : 20-pin
7 : 24-pin
A : 30-pin
RL78/G12 group
102 : Data flash is povided
103 : Data flash is not provided
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 3 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.3 Differences between R5F102 and R5F103
The following are differences between the R5F102 and R5F103.
 Whether the data flash memory is mounted or not
 High-speed on-chip oscillator oscillation frequency accuracy
 Number of channels in serial interface
 Whether the DMA function is mounted or not
 Whether the safety function is mounted or not
1.3.1 Data Flash
The data flash memory of 2 KB is mounted on the R5F102 but not on the R5F103.
Product
R5F102
Data Flash
2KB
R5F1026A, R5F1027A, R5F102AA,
R5F10269, R5F10279, R5F102A9,
R5F10268, R5F10278, R5F102A8,
R5F10267, R5F10277, R5F102A7,
R5F10266 Note
R5F103
Not mounted
R5F1036A, R5F1037A, R5F103AA,
R5F10369, R5F10379, R5F103A9,
R5F10368, R5F10378 R5F103A8,
R5F10367, R5F10377, R5F103A7,
R5F10366
Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer’s program
specification, the stack area to execute the data flash library may not be kept and data may not be written to or
erased from the data flash memory.
Caution When the flash memory is rewritten via a user program, the flash ROM area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming
Library Type01 User’s Manual and RL78 Family Data Flash Library Type04 User’s Manual.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 4 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.3.2 On-chip oscillator characteristics
(1) High-speed on-chip oscillator oscillation frequency of the R5F102
Oscillator
Condition
MIN
High-speed on-chip
TA = -20 to +85 °C
oscillator oscillation
TA = -40 to -20 °C
MAX
Unit
-1
+1
%
-1.5
+1.5
frequency accuracy
(2) High-speed on-chip oscillator oscillation frequency of the R5F103
Oscillator
Condition
MIN
MAX
Unit
High-speed on-chip
TA = -40 to + 85 °C
-5
+5
%
oscillator oscillation
frequency accuracy
1.3.3 Peripheral Functions
R5F102
RL78/G12
20, 24 pin
30 pin product
product
Serial interface
UART
CSI
2
Simplified I C
DMA function
Safety function
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
R5F103
20, 24 pin
30 pin product
product
1 channel
3 channels
1 channel
2 channels
3 channels
1 channel
2 channels
3 channels
None
2 channels
None
CRC operation
Yes
None
RAM guard
Yes
None
SFR guard
Yes
None
Page 5 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.4 Pin Configuration (Top View)
1.4.1 20-pin products
• 20-pin plastic SSOP (4.4 × 6.5)
P20/ANI0/AVREFP
P42/ANI21/SCK01Note/SCL01Note /TI03/TO03
P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1
P40/KR0/TOOL0
P125/KR1/SI01Note/RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P21/ANI1/AV REFM
P22/ANI2
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00Note
P11/ANI17/SI00/RxD0/SDA00 Note/TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
P61/KR5/SDAA0/(RxD0)
P60/KR4/SCLA0/(TxD0)
Note Provided in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 6 of 61
RL78/G12
CHAPTER 1 OUTLINE
• 24-pin plastic WQFN (4 × 4)
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00Note
P11/ANI17/SI00/RxD0/SDA00Note/TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
1.4.2 24-pin products
exposed die pad
18 17 16 15 14 13
12
19
11
20
10
21
9
22
23
8
7
24
1 2 3 4 5 6
P61/KR5/SDAA00/(RxD0)
P60/KR4/SCLA0/(TxD0)
P03/KR9
P02/KR8/(SCK01/SCL01)Note
P01/KR7/(SO01/SDA01)Note
P00/KR6/(SI01)Note
P125/KR1/SI01Note/RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P42/ANI21/SCK01Note/SCL01Note/TI03/TO03
P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1
P40/KR0/TOOL0
Note Provided in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 7 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.4.3 30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P147/ANI18
P10/SCK00/SCL00Note/(TI07/TO07)
P11/SI00/RxD0/TOOLRxD/SDA00Note/(TI06/TO06)
P12/SO00/TxD0/TOOLTxD/(TI05/TO05)
P13/TxD2Note/SO20Note/(SDAA0)/(TI04/TO04)
P14/RxD2Note/SI20Note/SDA20Note/(SCLA0) /(TI03/TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02/TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
Note Provided in the R5F102 products.
Caution Connect the REGC pin to VSS via capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 8 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.5 Pin Identification
ANI0 to ANI3,
ANI16 to ANI22:
REGC:
Regulator Capacitance
Analog input
RESET:
Reset
Receive Data
AVREFM:
Analog Reference Voltage Minus
RxD0 to RxD2:
AVREFP:
Analog reference voltage plus
SCK00, SCK01, SCK11,
EXCLK:
External Clock Input
SCK20:
(Main System Clock)
SCL00, SCL01, SCL11,
INTP0 to INTP5
Interrupt Request From Peripheral
SCL20, SCLA0:
KR0 to KR9
Key Return
SDA00, SDA01, SDA11,
P00 to P03:
Port 0
SDA20, SDAA0:
Serial Data Input/Output
P10 to P17:
Port 1
SI00, SI01, SI11, SI20:
Serial Data Input
Serial Clock Input/Output
Serial Clock Input/Output
P20 to P23:
Port 2
SO00, SO01, SO11,
P30 to P31:
Port 3
SO20:
Serial Data Output
P40 to P42:
Port 4
TI00 to TI07:
Timer Input
P50, P51:
Port 5
TO00 to TO07:
Timer Output
P60, P61:
Port 6
TOOL0:
Data Input/Output for Tool
P120 to P122, P125:
Port 12
TOOLRxD, TOOLTxD:
Data Input/Output for External
P137:
Port 13
P147:
Port 14
TxD0 to TxD2:
Transmit Data
PCLBUZ0, PCLBUZ1:
Programmable Clock Output/
VDD:
Power supply
Buzzer Output
VSS:
Ground
X1, X2:
Crystal Oscillator (Main System
Device
Clock)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 9 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.6 Block Diagram
1.6.1 20-pin products
TAU0 (4 ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
Port 1
5
P10 to P14
Port 2
4
P20 to P23
Port 4
3
P40 to P42
Port 6
2
P60, P61
Port 12
3
P121, P122, P125
SAU0 (2 ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01 Note
SCL00
SDA00
IIC00 Note
SCL01
SDA01
IIC01 Note
Code flash: 16 KB
Data flash: 2 KB
Port 13
Note
P137
Buzzer/clock
output control
Key return
6 ch
6
KR0 to KR5
Interrupt control
4 ch
4
INTP0 to INTP3
9
ANI2, ANI3, ANI16 to ANI22
ANI0/AVREFP
ANI1/AVREFM
Note
DMA
2 ch
RL78 CPU core
RAM
1.5 KB
TOOL0
PCLBUZ0
Interrupt control
TOOL TOOL
TxD
RxD
Window watchdog
timer
CRC
Note
12-bit Interval timer
On-chip debugger
RESET
Clock Generator
+
Reset Generator
BCD
adjustment
Multiplier &
divider/
multiply
accumulator
SCLA0
SDAA0
IICA0
Main OSC
1 to 20 MHz
X1 X2/EXCLK
Power-on
reset/low
voltage
detector
Low-speed
on-chip
oscillator
15 kHz
VDD
10-bit A/D converter
11 ch
High-Speed
on-chip
oscillator
1 to 24 MHz
VSS
Note Provided for the R5F102 products.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 10 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.6.2 24-pin products
TAU0 (4 ch)
TI00/TO00
ch00
TI01/TO01
ch01
TI02/TO02
ch02
TI03/TO03
ch03
Port 0
4
P00 to P03
Port 1
5
P10 to P14
Port 2
4
P20 to P23
Port 4
3
P40 to P42
Port 6
2
P60, P61
Port 12
3
P121, P122, P125
SAU0 (2 ch)
RxD0
TxD0
UART0
SCK00
SI00
SO00
CSI00
SCK01
SI01
SO01
CSI01Note
SCL00
SDA00
IIC00Note
SCL01
SDA01
Note
Code flash: 16 KB
Data flash: 2 KBNote
Port 13
P137
Buzzer/clock
output control
PCLBUZ0
Interrupt control
Key return
10 ch
6
KR0 to KR9
Interrupt control
4 ch
4
INTP0 to INTP3
9
ANI2, ANI3, ANI16 to ANI22
ANI0/AVREFP
ANI1/AVREFM
Note
DMA
2 ch
RL78 CPU core
IIC01
RAM
1.5KB
TOOL TOOL
TOOL0 TxD
RxD
Window watchdog
timer
CRCNote
12-bit Interval timer
On-chip debugger
RESET
Clock Generator
+
Reset Generator
BCD
adjustment
Multiplier &
divider/
multiply
accumulator
SCLA0
SDAA0
IICA0
Main OSC
1 to 20 MHz
X1 X2/EXCLK
Power-on
reset/low
voltage
detector
Low-speed
on-chip
oscillator
15 kHz
V DD
10-bit A/D converter
11 ch
High-Speed
on-chip
oscillator
1 to 24 MHz
V SS
Note Provided for the R5F102 products.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 11 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.6.3 30-pin products
TAU (8ch)
TI00
TO00
ch0
TI01/TO01
ch1
TI02/TO02
ch2
PORT 0
2
P00, P01
TI03/TO03
ch3
PORT 1
8
P10 to P17
(TI04/TO04)
ch4
PORT 2
4
P20 to P23
(TI05/TO05)
ch5
PORT 3
2
P30, P31
(TI06/TO06)
ch6
(TI07/TO07)
ch7
PORT 4
CODE FLASH :16KB
DATA FLASH:2KBNote
SAU0 (4ch)
RxD0
TxD0
RxD1
TxD1
SCK00
SI00
SO00
SCK11
SI11
SO11
SCL00
SDA00
SCL11
SDA11
PORT 5
2
P50, P51
PORT 6
2
P60, P61
UART0
PORT 12
Note
UART1
INTERRUPT
CONTROL
CSI00
CSI11
RL78
CPU
CORE
DMA Note
2ch
P120
2
P121, P122
PORT 13
P137
PORT 14
P147
Note
IIC00
Note
IIC11
Note
RAM
2KB
RESET
Clock Generator
+
Reset Generator
UART2
SCK20
SI20
SO20
CSI20
SCL20
SDA20
IIC20
BUZZER/CLOCK
OUTPUT CONTROL
INTERRUPT
CONTROL
6ch
SAU1 (2ch) Note
RxD2
TxD2
P40
Main OSC
1 to 20 MHz
X1 X2/EXCLK
POWERON
RESET/
VOLTAGE
DETECTOR
TOOL TOOL
TOOL0 TxD RxD
ON-CHIP DEBUG
Low Speed
ON-CHIP
OSCILLATOR
15 kHz
VDD
VSS
2
PCLBUZ0, PCLBUZ1
6
INTP0 to INTP5
6
ANI2, ANI3,
ANI16 to ANI19
ANI0/AVREFP
ANI1/AVREFM
WINDOW
WATCHDOG
TIMER
CRCNote
12-bit INTERVAL
TIMER
High Speed
ON-CHIP
OSCILLATOR
1 to 24 MHz
10-bit
A/D CONVERTER
8ch
VOLTAGE
REGULATOR
REGC
BCD
ADJUSTMENT
MULTIPLIER&
DIVIDER
MULITIPLYACCUMULATOR
SCLA0
SDAA0
IICA0
Note Provided for the R5F102 products.
Remark
Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 12 of 61
RL78/G12
CHAPTER 1 OUTLINE
1.7 Outline of Functions
This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H (except
timer output of R5F102Ax)
(1/2)
Item
20-pin
R5F1026x
Code flash memory
Data flash memory
RAM
24-pin
R5F1036x
2 to 16 KB
R5F1027x
R5F103Ax
−
2 KB
512 B to 1.5 KB
512 B to 2KB
1 MB
X1, X2 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 5.5 V
system
clock
−
2 KB
Address space
High-speed system clock
R5F102Ax
4 to 16 KB
256 B to 1.5 KB
Main
R5F1037x
Note 1
−
2 KB
30-pin
High-speed on-chip
HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V),
oscillator clock
LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)
Low-speed on-chip oscillator clock
15 kHz (TYP)
General-purpose register
(8-bit register × 8) × 4 banks
Minimum instruction execution time
0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
Instruction set
• Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
I/O port
Total
18
22
26
CMOS I/O
12
16
21
CMOS input
4
4
3
N-ch open-drain I/O
2
(6 V tolerance)
Timer
16-bit timer
4 channels
Watchdog timer
1 channel
12-bit Interval timer
Timer output
Notes 1.
8 channels
1 channel
4/8
Note 2
(PWM Output
Note 3
: 3/7
Note 2
)
The self-programming function cannot be used in the R5F10266 and R5F10366.
2.
When PIOR0 is set to 1 in R5F102Az.
3.
The number of PWM outputs varies depending on the setting of channels in use (the number of masters and
slaves). (see 6.8.3 Operation as multiple PWM output function in the RL78/G12 User’s Manual).
Caution When the flash memory is rewritten via a user program, the flash ROM area and RAM area are used because
each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01
User’s Manual and RL78 Family Data Flash Library Type04 User’s Manual.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 13 of 61
RL78/G12
CHAPTER 1 OUTLINE
(2/2)
Item
20-pin
R5F1026x
24-pin
R5F1036x
R5F1027x
30-pin
R5F1037x
Clock output/buzzer output
R5F102Ax
R5F103Ax
1
2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation)
8/10-bit resolution A/D converter
11 channels
8 channels
2
Serial interface
2
CSI/UART/Simplified I C + CSI/Simplified I C
[Product with data flash memory (30-pin)]
2
CSI/UART/Simplified I C x 3
CSI + UART
2
I C bus
1 channel
Multiplier and divider/multiply-
• 16 bits × 16 bits = 32 bits (unsigned or signed)
accumulator
• 32 bits ÷ 32 bits = 32 bits (unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (unsigned or signed)
DMA controller
Vectored interrupt
Internal
sources
External
2 channels
−
2 channels
−
2 channels
−
18
16
18
16
26
19
5
Key interrupt
6
6
10
−
• Reset by RESET pin
Reset
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
• Power-on-reset:
1.51 ± 0.03 V
• Power-down-reset:
1.50 ± 0.03 V
• Rising edge : 1.88 to 4.06 V (12 stages)
• Falling edge : 1.84 to 3.98 V (12 stages)
On-chip debug function
Provided
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = −40 to +85°C
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 14 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2. ELECTRICAL SPECIFICATIONS
Cautions 1. The RL78/G12 has an on-chip debug function, which is provided for development and evaluation.
Do not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions for each
product in the RL78/G12 User’s Manual.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 15 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply Voltage
REGC terminal input
Note 1
voltage
Input Voltage
Symbols
Ratings
Unit
VDD
−0.5 to + 6.5
V
VSS
−0.5 to + 0.3
V
−0.3 to +2.8
V
VIREGC
Conditions
REGC
and −0.3 to VDD + 0.3
Note 2
VI1
Other than P60, P61
VI2
P60, P61 (N-ch open drain)
Output Voltage
VO
Analog input voltage
VAI
−0.3 to VDD + 0.3
Note 3
−0.3 to 6.5
ANI0 to ANI22
V
V
−0.3 to VDD + 0.3
Note 3
V
−0.3 to VDD + 0.3
Note 3
V
and −0.3 to
Note 3
AVREF(+)+0.3
Output current, high
IOH1
Per pin
Other than P20 to P23
−40
mA
Total of
all pins
All the terminals other than P20 to P23
−170
mA
20-, 24-pin products: P40 to P42
−70
mA
−100
mA
30-pin products: P00, P01, P40, P120
20-, 24-pin products: P00 to P03
P10 to P14
Note 4
,
30-pin products: P10 to P17, P30,
P31, P50, P51, P147
IOH2
Per pin
P20 to P23
Total of
all pins
Output current, low
IOL1
−0.5
mA
−2
mA
Per pin
Other than P20 to P23
40
mA
Total of
all pins
All the terminals other than P20 to P23
170
mA
20-, 24-pin products: P40 to P42
70
mA
100
mA
1
mA
5
mA
30-pin products: P00, P01, P40, P120
20-, 24-pin products: P00 to P03,
P10 to P14, P60, P61
30-pin products: P10 to P17, P30,
P31, P50, P51, P60, P61, P147
IOL2
Per pin
Total of
all pins
P20 to P23
Operating ambient
temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−65 to +150
°C
Notes 1. 30-pin product only.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). This value determines the absolute maximum
rating of the REGC pin. Do not use it with voltage applied.
3. Must be 6.5 V or lower.
4. 24-pin product only.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
2. AVREF (+) : + side reference voltage of the A/D converter.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 16 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.2 Oscillator Characteristics
2.2.1 X1 clock oscillator characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Resonator
X1 clock oscillation
Ceramic resonator
Note
frequency (fX)
Recommended Circuit
VSS X1
/ crystal oscillator
C1
X2
Rd
Conditions
MIN.
TYP.
MAX.
Unit
MHz
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
1.8 V ≤ VDD < 2.7 V
1.0
8.0
C2
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register
(OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the
oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
2.2.2 On-chip oscillator characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Oscillators
Parameters
High-speed on-chip oscillator
oscillation frequency
Conditions
MAX.
Unit
1
24
MHz
TA = -20 to +85°C
-1
+1
%
TA = -40 to -20°C
-1.5
+1.5
%
-5
+5
%
fIH
TYP.
Note 1
High-speed on-chip oscillator
R5F102
oscillation frequency
accuracy
MIN.
Note 2
R5F103
Low-speed on-chip oscillator
15
fIL
kHz
oscillation frequency
Low-speed on-chip oscillator
-15
+15
%
oscillation frequency
accuracy
Notes 1.
High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits
0 to 2 of HOCODIV register.
2.
This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 17 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Note 1
Output current, high
IOH1
(1/4)
Conditions
Per pin
MIN.
TYP.
20-, 24-pin products:
P00 to P03
MAX.
Unit
−10.0
mA
Note 3
,
P10 to P14,
P40 to P42
30-pin products: P00,
P01,
P10 to P17, P30,
P31, P40, P50, P51,
P120, P147
Total of all
Note 2
pins
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
−30.0
mA
P40 to P42
2.7 V ≤ VDD < 4.0 V
−6.0
mA
30-pin products: P00,
1.8 V ≤ VDD < 2.7 V
−4.5
mA
4.0 V ≤ VDD ≤ 5.5 V
−80.0
mA
2.7 V ≤ VDD < 4.0 V
−18.0
mA
1.8 V ≤ VDD < 2.7 V
−10.0
mA
All the terminals
−100
mA
P20 to P23
−0.1
mA
−0.4
mA
P01, P40, P120
20-, 24-pin products:
P00 to P03
Note 3
,
P10 to P14
30-pin products: P10
to P17, P30, P31,
P50, P51, P147
IOH2
Per pin
Total of all
Note 2
pins
Notes 1.
value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an
output pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
3.
24-pin products only.
Caution P10 to P12, P41 for 20-pin products, P01, P10 to P12, P41 for 24-pin products, and P00, P10 to P15,
P17, P50 for 30-pin products, do not output high level in N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 18 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Output current, low
Symbol
Note 1
IOL1
(2/4)
Conditions
Per pin
MIN.
20-, 24-pin products:
TYP.
MAX.
Unit
20.0
mA
15.0
mA
Note 3
,
P00 to P03
P10 to P14,
P40 to P42
30-pin products: P00,
P01, P10 to P17,
P30, P31, P40, P50,
P51, P120, P147
P60, P61
Total of all
Note 2
pins
20-, 24-pin products:
4.0 V ≤ VDD ≤ 5.5 V
60.0
mA
P40 to P42
2.7 V ≤ VDD < 4.0 V
9.0
mA
30-pin products:
1.8 V ≤ VDD < 2.7 V
1.8
mA
4.0 V ≤ VDD ≤ 5.5 V
80.0
mA
2.7 V ≤ VDD < 4.0 V
27.0
mA
1.8 V ≤ VDD < 2.7 V
5.4
mA
All the terminals
140
mA
P20 to P23
0.4
mA
1.6
mA
P00, P01, P40, P120
20-, 24-pin products:
P00 to P03
Note 3
,
P10 to P14, P60, P61
30-pin products:
P10 to P17, P30,
P31, P50, P51, P60,
P61, P147
IOL2
Per pin
Total of all
Note 2
pins
Notes 1.
Value of current at which the device operation is guaranteed even if the current flows from an output pin to
the VSS pin.
2.
Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
3.
Remark
24-pin products only.
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 19 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Input voltage, high
Symbol
VIH1
(3/4)
Conditions
MIN.
Normal input buffer
20-, 24-pin products: P00 to P03
TYP.
MAX.
Unit
0.8VDD
VDD
V
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIH2
4.0 V ≤ VDD ≤ 5.5 V
TTL input buffer
2.2
VDD
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
2.0
VDD
V
1.8 V ≤ VDD < 3.3 V
1.50
VDD
V
30-pin products: P01, P10,
P11, P13 to P17
Input voltage, low
VIH3
P20 to P23
0.7VDD
VDD
V
VIH4
P60, P61
0.7VDD
6.0
V
VIH5
P121, P122, P125, P137, EXCLK, RESET
0.8VDD
VDD
V
VIL1
Normal input buffer
0
0.2VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.8
V
20-, 24-pin products: P10, P11 3.3 V ≤ VDD < 4.0 V
0
0.5
V
1.8 V ≤ VDD < 3.3 V
0
0.32
V
0
0.3VDD
V
0
0.3VDD
V
0
0.2VDD
V
20-, 24-pin products: P00 to P03
Note 2
, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P51, P120, P147
VIL2
TTL input buffer
30-pin products: P01, P10,
P11, P13 to P17
Output voltage, high
VIL3
P20 to P23
VIL4
P60, P61
Note 1
VIL5
P121, P122, P125
VOH1
20-, 24-pin products:
P00 to P03
, P137, EXCLK, RESET
Note 2
, P10 to P14,
4.0 V ≤ VDD ≤ 5.5 V,
P40 to P42
4.0 V ≤ VDD ≤ 5.5 V,
30-pin products:
IOH1 = −3.0 mA
P00, P01, P10 to P17, P30,
2.7 V ≤ VDD ≤ 5.5 V,
P31, P40, P50, P51, P120,
P147
VDD−1.5
V
VDD−0.7
V
VDD−0.6
V
VDD−0.5
V
VDD−0.5
V
IOH1 = −10.0 mA
IOH1 = −2.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.5 mA
VOH2
P20 to P23
IOH2 = −100 μA
Notes 1. 20, 24-pin products only.
2. 24-pin products only.
Caution The maximum value of VIH of pins P01, P10 to P12, P41, for 20-, 24-pin products and P00, P10 to P15,
P17, P50 for 30-pin products is VDD even in N-ch open-drain mode.
High level is not output in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 20 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Output voltage, low
Symbol
VOL1
(4/4)
Conditions
20-, 24-pin products:
P00 to P03
Note
, P10 to P14,
TYP.
4.0 V ≤ VDD ≤ 5.5 V,
MAX.
Unit
1.3
V
0.7
V
0.6
V
0.4
V
0.4
V
IOL1 = 20.0 mA
P40 to P42
4.0 V ≤ VDD ≤ 5.5 V,
30-pin products: P00, P01,
IOL1 = 8.5 mA
P10 to P17, P30, P31, P40,
2.7 V ≤ VDD ≤ 5.5 V,
P50, P51, P120, P147
MIN.
IOL1 = 3.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
VOL2
P20 to P23
IOL2 = 400 μA
0.4
V
VOL3
P60, P61
4.0 V ≤ VDD ≤ 5.5 V,
2.0
V
0.4
V
0.4
V
0.4
V
VI = VDD
1
μA
VI = VDD Input port or external
clock input
1
μA
10
μA
−1
μA
−1
μA
−10
μA
100
kΩ
IOL3 = 15.0 mA
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 5.0 mA
2.7 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA
1.8 V ≤ VDD ≤ 5.5 V,
IOL3 = 2.0 mA
Input leakage current,
ILIH1
Other than P121,
P122
high
ILIH2
P121, P122
(X1, X2/EXCLK)
When resonator
connected
Input leakage current,
ILIL1
Other than P121,
VI = VSS
P122
low
ILIL2
P121, P122
VI = VSS Input port or external
(X1, X2/EXCLK)
clock input
When resonator
connected
On-chip pull-up
RU
20-, 24-pin products:
P00 to P03
resistance
VI = VSS, input port
10
20
Note
, P10 to P14,
P40 to P42, P125, RESET
30-pin products: P00, P01,
P10 to P17, P30, P31, P40,
P50, P51, P120, P147,
RESET
Note
24-pin products only.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 21 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.3.2 Supply current characteristics
(1) 20-, 24-pin products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
current
Symbol
IDD1
Note 1
(1/2)
Conditions
Note 3
Operating HS(High-speed fIH = 24 MHz
Note 2
mode
main) mode
MIN.
Basic
VDD = 5.0 V
operation VDD = 3.0 V
1.5
Noramal
5.0
3.3
5.0
VDD = 5.0 V
2.5
3.7
VDD = 3.0 V
2.5
3.7
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
Square wave input
2.8
4.4
Resonator connection
3.0
4.6
Square wave input
2.8
4.4
Resonator connection
3.0
4.6
Square wave input
1.8
2.6
Resonator connection
1.8
2.6
Square wave input
1.8
2.6
Resonator connection
1.8
2.6
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
fIH = 8 MHz
HS(High-speed fMX = 20 MHz
Note 2
,
VDD = 5.0 V
Note 4
fMX = 20 MHz
,
VDD = 3.0 V
Note 4
fMX = 10 MHz
,
VDD = 5.0 V
Note 4
fMX = 10 MHz
,
VDD = 3.0 V
LS(Low-speed
main) mode
Note 2
Note 4
fMX = 8 MHz
,
VDD = 3.0 V
Note 4
fMX = 8 MHz
,
VDD = 2.0 V
Notes 1.
mA
mA
mA
Note 2
Note 4
main) mode
1.5
3.3
Note 3
Unit
mA
VDD = 5.0 V
Note 3
main) mode
MAX.
operation VDD = 3.0 V
fIH = 16 MHz
LS(Low-speed
TYP.
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
3.
When high-speed system clock is stopped
4.
When high-speed on-chip osicllator clock is stopped.
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 22 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
current
Symbol
(2/2)
Conditions
HALT
IDD2
Note 1
mode
HS(High-speed
Note 2
main) mode
MIN.
Note 4
fIH = 24 MHz
fIH = 16 MHz
LS(Low-speed
Unit
VDD = 5.0 V
440
1210
μA
VDD = 3.0 V
440
1210
VDD = 5.0 V
400
950
Note 4
VDD = 3.0 V
400
950
fIH = 8 MHz
VDD = 3.0 V
270
542
VDD = 2.0 V
270
542
Square wave input
280
1000
Resonator connection
450
1170
Square wave input
280
1000
Resonator connection
450
1170
Note 3
Note 5
fMX = 20 MHz
,
VDD = 5.0 V
Note 5
fMX = 20 MHz
,
VDD = 3.0 V
Note 5
fMX = 10 MHz
,
Square wave input
190
590
Resonator connection
260
660
Square wave input
190
590
Resonator connection
260
660
Square wave input
110
360
Resonator connection
150
416
Square wave input
110
360
Resonator connection
150
416
VDD = 5.0 V
Note 5
fMX = 10 MHz
,
VDD = 3.0 V
LS(Low-speed
main) mode
Note 3
Note 5
fMX = 8 MHz
,
VDD = 3.0 V
Note 5
fMX = 8 MHz
,
VDD = 2.0 V
STOP
IDD3
mode
Notes 1.
μA
μA
Note 3
HS(High-speed
main) mode
MAX.
Note 3
Note 4
main) mode
TYP.
μA
μA
μA
μA
μA
μA
μA
TA = −40°C
0.19
TA = +25°C
0.24
0.50
TA = +50°C
0.25
0.80
TA = +70°C
0.28
1.20
TA = +85°C
0.88
2.20
Note 6
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2.
During HALT instruction execution by flash memory.
3.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
4.
VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
When high-speed system clock is stopped.
5.
When high-speed on-chip oscillator clock is stopped.
6.
When high-speed on-chip oscillator clock, high-speed system clock, and watchdog timer are stopped.
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except temperature condition of the TYP. value is TA = 25°C, other than STOP mode
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 23 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(2) 30-pin products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
current
Symbol
IDD1
Note 1
(1/2)
Conditions
Note 3
Operating HS(High-speed fIH = 24 MHz
mode
main) mode
MIN.
Basic
Note 2
VDD = 5.0 V
1.5
operation VDD = 3.0 V
1.5
Noramal
3.7
5.5
3.7
5.5
VDD = 5.0 V
2.7
4.0
VDD = 3.0 V
2.7
4.0
VDD = 3.0 V
1.2
1.8
VDD = 2.0 V
1.2
1.8
Square wave input
3.0
4.6
Resonator connection
3.2
4.8
Square wave input
3.0
4.6
Resonator connection
3.2
4.8
Square wave input
1.9
2.7
Resonator connection
1.9
2.7
Square wave input
1.9
2.7
Resonator connection
1.9
2.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Square wave input
1.1
1.7
Resonator connection
1.1
1.7
Note 3
fIH = 8 MHz
HS(High-speed fMX = 20 MHz
Note 2
,
VDD = 5.0 V
Note 4
fMX = 20 MHz
,
VDD = 3.0 V
Note 4
fMX = 10 MHz
,
VDD = 5.0 V
Note 4
fMX = 10 MHz
,
VDD = 3.0 V
LS(Low-speed
main) mode
Note2
Note 4
fMX = 8 MHz
,
VDD = 3.0 V
Note 4
fMX = 8 MHz
,
VDD = 2.0 V
Notes 1.
mA
mA
mA
Note2
Note 4
main) mode
Unit
mA
VDD = 5.0 V
Note 3
main) mode
MAX.
operation VDD = 3.0 V
fIH = 16 MHz
LS(Low-speed
TYP.
mA
mA
mA
mA
mA
mA
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
3.
When high-speed system clock is stopped
4.
When high-speed on-chip osicllator clock is stopped.
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 24 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Supply
current
Symbol
IDD2
Note 1
(2/2)
Conditions
HALT
mode
HS(High-speed
Note 2
main) mode
MIN.
Note 4
fIH = 24 MHz
fIH = 16 MHz
LS(Low-speed
Note 4
fIH = 8 MHz
Note 3
Note 5
fMX = 20 MHz
,
VDD = 5.0 V
Note 5
fMX = 20 MHz
,
VDD = 3.0 V
Note 5
fMX = 10 MHz
,
VDD = 5.0 V
Note 5
fMX = 10 MHz
,
VDD = 3.0 V
LS(Low-speed
main) mode
Note 3
Note 5
fMX = 8 MHz
,
VDD = 3.0 V
Note 5
fMX = 8 MHz
,
VDD = 2.0 V
IDD3
STOP
mode
Notes 1.
Unit
VDD = 5.0 V
440
1280
μA
VDD = 3.0 V
440
1280
VDD = 5.0 V
400
1000
VDD = 3.0 V
400
1000
VDD = 3.0 V
260
530
VDD = 2.0 V
260
530
Square wave input
280
1000
Resonator connection
450
1170
Square wave input
280
1000
Resonator connection
450
1170
Square wave input
190
600
Resonator connection
260
670
Square wave input
190
600
Resonator connection
260
670
Square wave input
95
330
Resonator connection
145
380
Square wave input
95
330
Resonator connection
145
380
μA
μA
Note 3
HS(High-speed
main) mode
MAX.
Note 3
Note 4
main) mode
TYP.
μA
μA
μA
μA
μA
μA
μA
TA = −40°C
0.18
TA = +25°C
0.23
0.50
TA = +50°C
0.26
1.10
TA = +70°C
0.29
1.90
TA = +85°C
0.90
3.30
Note 6
Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors.
2.
During HALT instruction execution by flash memory.
3.
Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode:
4.
VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
When high-speed system clock is stopped.
5.
When high-speed on-chip oscillator clock is stopped.
6.
When high-speed on-chip oscillator clock, high-speed system clock, and watchdog timer are stopped. The
values below the MAX. column include the leakage current.
Remarks 1.
fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. fIH: high-speed on-chip oscillator clock frequency
3. Except STOP mode, temperature condition of the TYP. value is TA = 25°C.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 25 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(3) Common to RL78/G12 all products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Notes 1, 2
fIL = 15 kHz
0.22
μA
IWDT
Notes 1, 3
fIL = 15 kHz
0.22
μA
A/D converter
operating
current
IADC
Note 4
When
conversion at
maximum
speed
A/D converter
reference
voltage current
IADREF
Temperature
sensor
operating
current
ITMPS
LVD operating
ILVD
12-bit interval
ITMKA
timer operating
current
Watchdog timer
operating
current
Normal mode, AVREFP = VDD = 5.0 V
1.30
1.70
mA
Low voltage mode, AVREFP = VDD = 3.0 V
0.50
0.70
mA
Note 5
Note 5
Note 6
75.0
μA
75.0
μA
0.08
μA
current
BGO operating
IBGO
Note 7
2.50
12.20
mA
0.50
0.60
mA
1.20
1.44
mA
0.70
0.84
mA
current
SNOOZE
ISNOZ
Note 5
ADC operation
The mode is performed
Note 8
operating
The A/D conversion operations are
current
performed, Low voltage mode, AVREFP =
VDD = 3.0 V
CSI/UART operation
Notes 1. When high speed on-chip oscillator and high-speed system clock are stopped.
2. Current flowing only to the 12-bit interval timer (including the operating current of the low-speed on-chip
oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
fCLK = fSUB when the watchdog timer operates in STOP mode.
3. Current flowing only to the watchdog timer (including the operating current of the 15 KHz low-speed on-chip
oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
fCLK = fSUB when the watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter. The current value of the RL78/G12 microcontrollers is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing to the VDD.
6. Current flowing only to the LVD circuit. The current value of the RL78/G12 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and IVLD when the LVD circuit operates in the Operating, HALT or STOP mode.
7. Current flowing only to the BGO. The current value of the RL78/G12 microcontrollers is the sum of IDD1 or IDD2
and IBGO when the BGO operates in an operation mode.
8. Refer to shift time to the SNOOZE mode, see 17.2.3 SNOOZE mode in the RL78/G12 User’s Manual.
Remarks 1. fIL:
Low-speed on-chip oscillator clock frequency
2. fCLK: CPU/peripheral hardware clock frequency
3. Temperature condition of the TYP. value is TA = 25°C
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 26 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.4 AC Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Items
Instruction cycle (minimum
Symbol
TCY
Conditions
fEX
External main system clock
tEXH, tEXL
input high-level width, lowlevel width
TI00 to TI07 input high-level
MAX.
Unit
0.04167
1
μs
2.4 V ≤ VDD < 2.7 V
0.0625
1
μs
1.8 V ≤ VDD ≤ 5.5 V
0.125
1
μs
2.7 V ≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V ≤ VDD < 2.7 V
1.0
8.0
MHz
2.7 V ≤ VDD ≤ 5.5 V
24
ns
1.8 V ≤ VDD < 2.7 V
60
ns
1/fMCK + 10
ns
LS(Low-speed main) mode
frequency
TYP.
2.7 V ≤ VDD ≤ 5.5 V
HS(High-speed main) mode
instruction execution time)
External main system clock
MIN.
tTIH, tTIL
width, low-level width
TO00 to TO07 output
fTO
frequency
PCLBUZ0, or PCLBUZ1
fPCL
output frequency
INTP0 to INTP5 input high-
4.0 V ≤ VDD ≤ 5.5 V
12
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
1.8 V ≤ VDD < 2.7 V
4
MHz
4.0 V ≤ VDD ≤ 5.5 V
16
MHz
2.7 V ≤ VDD < 4.0 V
8
MHz
1.8 V ≤ VDD < 2.7 V
4
MHz
1
μs
tKR
250
ns
tRSL
10
μs
tINTH, tINTL
level width, low-level width
KR0 to KR9 input available
width
RESET low-level width
Remark
fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0
to 7))
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 27 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
AC Timing Test Point
VIH
VIL
VIH
Test points
VIL
External main system clock timing
1/fEX
tEXL
tEXH
0.8VDD (MIN.)
0.2VDD (MAX.)
EXCLK
TI timing
tTIH
tTIL
TI00 to TI07
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP5
Key Interrupt Input Timing
tKR
KR0 to KR9
RESET input timing
tRSL
RESET
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 28 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.5 Serial Communication Characteristics
2.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Transfer rate
Conditions
MIN.
Normal operation
TYP.
MAX.
Unit
fMCK/6
bps
4.0
Mbps
9600
bps
Theoretical value of the
maximum transfer rate
fCLK = fMCK = 24 MHz
SNOOZE mode
4800
UART mode connection diagram (during communication at same potential)
Rx
TxDq
User’s device
RL78/G12
Tx
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg)
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 29 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(2) During communication at same potential (CSI00 master mode (fMCK/2), SCK00... internal clock output)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCK00 cycle time
SCK00 high - /low-level width
SI00 setup time (to SCK00↑)
SI00 hold time (to SCK00↑)
Note 2
Note2
Delay time from SCK00↓ to SO00 output
Notes 1.
2.
MIN.
tKCY1
2.7 V ≤ VDD ≤ 5.5 V
83.3
TYP.
MAX.
Note 1
Unit
ns
tKH1,
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 7
ns
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 10
ns
tSIK1
4.0 V ≤ VDD ≤ 5.5 V
23
ns
2.7 V ≤ VDD ≤ 5.5 V
33
ns
2.7 V ≤ VDD ≤ 5.5 V
10
ns
tKSI1
Note 4
Conditions
tKSO1
Note 5
C = 20 pF
10
ns
The value must also be 2/fCLK or more.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
3.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
4.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes
“from SCK00↑” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
5.
C is the load capacitance of the SCK00 and SO0 output lines.
Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00
pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).
Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKS00 bit of serial mode register (SMR00).
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 30 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
MIN.
2.7 V ≤ VDD ≤ 5.5 V
2.4 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
SCKp high-/low-level width
Note 2
SIp setup time (to SCKp↑)
Note 3
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to
SOp output
TYP.
MAX.
Unit
167
Note 1
ns
250
Note 1
ns
500
Note 1
ns
tKH1,
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 12
ns
tKL1
2.7 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 18
ns
2.4 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 38
ns
1.8 V ≤ VDD ≤ 5.5 V
tKCY1/2 − 50
ns
tSIK1
4.0 V ≤ VDD ≤ 5.5 V
44
ns
2.7 V ≤ VDD ≤ 5.5 V
44
ns
2.4 V ≤ VDD ≤ 5.5 V
75
ns
1.8 V ≤ VDD ≤ 5.5 V
110
ns
19
ns
tKSI1
tKSO1
Note 5
C = 30 pF
25
ns
Note 4
Notes 1.
2.
The value must also be 4/fCLK or more.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
5.
C is the load capacitance of the SCKp and SOp output lines.
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0,
POM1).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unito number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
for the R5F102 products.)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (n = 0, 1, 3; “1, 3” is for the R5F102 products.)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 31 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY2
Conditions
MIN.
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
Unit
20 MHz < fMCK
8/fMCK
ns
fMCK ≤ 20 MHz
6/fMCK
ns
16 MHz < fMCK
8/fMCK
ns
fMCK ≤ 16 MHz
6/fMCK
ns
16 MHz < fMCK
8/fMCK
ns
fMCK ≤ 16 MHz
6/fMCK
ns
SNOOZE mode
tKH2,
MAX.
Normal operation
4.0 V ≤ VDD ≤ 5.5 V
SCKp high-/low-level width
TYP.
1
Mbps
1.8 V ≤ VDD ≤ 5.5 V
tKCY2/2
ns
2.7 V ≤ VDD ≤ 5.5 V
1/fMCK+20
ns
1.8 V ≤ VDD < 2.7 V
1/fMCK+30
ns
1/fMCK+31
ns
tKL2
SIp setup time (to SCKp↑)
Note 1
SIp hold time (from SCKp↑)
Note 2
Delay time from SCKp↓ to SOp
output
tSIK2
tKSI2
tKSO2
C = 30 pF
Note 3
Notes 1.
Note 4
2.7 V ≤ VDD ≤ 5.5 V
2/fMCK+44
ns
2.4 V ≤ VDD < 2.7 V
2/fMCK+75
ns
1.8 V ≤ VDD < 2.4 V
2/fMCK+110
ns
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4.
C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0,
POM1).
Remarks 1.
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3; “1, 3” is
for the R5F102 products.)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (n = 0, 1, 3; “1, 3” is for the R5F102 products.)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 32 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
CSI mode connection diagram (during communication at same potential)
SCK
SCKp
RL78/G12
SIp
SO
SOp
SI
User’s device
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1, 2
tKL1, 2
tKH1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Output data
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
SIp
tKSI1, 2
Input data
tKSO1, 2
SOp
Remarks 1.
2.
Output data
p: CSI number (p = 00, 01, 11, 20)
n: Channel number (0, 1, 3)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 33 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2
(5) During communication at same potential (simplified I C mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCLr clock frequency
fSCL
Conditions
MIN.
Typ.
1.8 V ≤ VDD ≤ 5.5 V,
MAX.
Unit
400
kHz
300
kHz
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
tLOW
1.8 V ≤ VDD ≤ 5.5 V,
1150
ns
1550
ns
1150
ns
1550
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “H”
tHIGH
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Data setup time (reception)
tSU:DAT
1.8 V ≤ VDD ≤ 5.5 V,
1/fMCK + 145
Note
ns
1/fMCK + 230
Note
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Data hold time (transmission)
tHD:DAT
1.8 V ≤ VDD ≤ 5.5 V,
0
355
ns
0
405
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
Remarks 1.
Rb [Ω]:Communication line (SDAr) pull-up resistance
Cb [F]: Communication line (SCLr, SDAr) load capacitance
2.
r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number (m = 0, 1), n: Channel number (0, 1, 3)
4.
2
Simplified I C mode is supported by the R5F102 products.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 34 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2
Simplified I C mode connection diagram (during communication at same potential)
VDD
Rb
SDA
SDAr
RL78/G12
User’s device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at same potential)
tLOW
tHIGH
SCLr
SDAr
tHD : DAT
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
tSU : DAT
Page 35 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
fMCK/6
bps
4.0
Mbps
4.0
Mbps
1.3
Mbps
Note 1
bps
Normal operation
Note 1
Reception
4.0 V ≤ VDD ≤ 5.5 V,
Theoretical maximum
2.7 V ≤ Vb ≤ 4.0 V
transfer rate
fCLK = fMCK = 24 MHz
2.7 V ≤ VDD < 4.0 V,
Theoretical maximum
2.3 V ≤ Vb ≤ 2.7 V
transfer rate
fCLK = fMCK = 24 MHz
1.8 V ≤ VDD < 3.3 V,
Theoretical maximum
1.6 V ≤ Vb ≤ 2.0 V
transfer rate
fCLK = fMCK = 8 MHz
Transmissio
4.0 V ≤ VDD ≤ 5.5 V,
n
2.7 V ≤ Vb ≤ 4.0 V
Theoretical maximum
2.8
Note 2
Mbps
transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb =
2.7 V
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Note 3
Theoretical maximum
1.2
Note 4
bps
Mbps
transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb =
2.3 V
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Note 5
Note 6
Theoretical maximum
0.43
bps
Mbps
transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb =
1.6 V
SNOOZE mode
Notes 1.
4800
9600
bps
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
2.2
)} × 3
Vb
[bps]
2.2
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
(
1
) × Number of transferred bits
Transfer rate
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 36 of 61
RL78/G12
3.
CHAPTER 2 ELECTRICAL SPECIFICATIONS
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
2.0
)} × 3
Vb
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
[bps]
2.0
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
1
) × Number of transferred bits
Transfer rate
(
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 −
Baud rate error (theoretical value) =
1.5
)} × 3
Vb
[bps]
1.5
1
− {−Cb × Rb × ln (1 −
)}
Vb
Transfer rate × 2
(
1
) × Number of transferred bits
Transfer rate
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6.
This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). (In
20- or 24-pin products, redirect to P6 is not supported.)
Remarks 1.
Rb [Ω]:Communication line (TxDq) pull-up resistance,
Cb [F]: Communication line (TxDq) load capacitance,
Vb [V]: Communication line voltage
2.
q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 37 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
UART mode connection diagram (during communication at different potential)
Vb
Rb
Rx
TxDq
RL78/G12
User’s device
Tx
RxDq
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1.
2.
Rb [Ω]: Communication line (TxD0) pull-up resistance, Vb [V]: Communication line voltage
q = UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 38 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(7) Communication at different potential (2.5 V, 3 V) (CSI00 mode) (CSI00 master mode (fMCK/2), SCK00...
internal clock output)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
SCK00 cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
200
Note 1
ns
300
Note 1
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCK00 high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKCY1/2 − 50
ns
tKCY1/2 − 120
ns
tKCY1/2 − 7
ns
tKCY1/2 − 10
ns
58
ns
121
ns
10
ns
10
ns
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SCK00 low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 setup time
(to SCK00↑)
tSIK1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 hold time
(from SCK00↑)
tKSI1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCK00↓ to
SO00 output
tKSO1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
60
ns
130
ns
Note 2
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 setup time
(to SCK00↓)
tSIK1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
23
ns
33
ns
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SI00 hold time
(from SCK00↓)
tKSI1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCK00↑ to
SO00 output
tKSO1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
10
ns
10
ns
Note 3
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Notes 1.
The value must also be 2/fCLK or more.
2.
When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1
3.
When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 39 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for
the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1) (Redirect to P0 is not supported in 24-pin products).
Remarks 1. Rb [Ω]:Communication line (SCK00, SOp) pull-up resistance, Cb [F]: Communication line (SCK00, SO00)
load capacitance, Vb [V]: Communication line voltage
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKS00 bit of serial mode register (SMR00).
CSI mode connection diagram (during communication at different potential)
Vb
<Master>
Rb
SCK00
RL78/G12
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Vb
Rb
SCK
SI00
SO
SO00
SI
User’s device
Page 40 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI00 mode) (master mode, SCKp... internal
clock output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCKp cycle time
tKCY1
Conditions
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
Note
ns
Note
ns
300
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
500
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
1150
Note
ns
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
tKCY1/2 −75
ns
tKCY1/2 −170
ns
tKCY1/2 −458
ns
tKCY1/2 −12
ns
tKCY1/2 −18
ns
tKCY1/2 −50
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Note The value must also be 4/fCLK or more.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different potential is not allowed in CSI01, CSI11.
Remarks 1.
Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2.
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 41 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal
clock output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
SIp setup time
(to SCKp↑)
Symbol
tSIK1
Note 1
Conditions
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MIN.
TYP.
MAX.
Unit
81
ns
177
ns
479
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↑)
tKSI1
Note 1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from
tKSO1
SCKp↓ to
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
100
ns
195
ns
483
ns
Cb = 30 pF, Rb = 1.4 kΩ
Note 1
SOp output
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
(to SCKp↓)
tSIK1
Note 2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
44
ns
44
ns
110
ns
19
ns
19
ns
19
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
(from SCKp↓)
tKSI1
Note 2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Delay time from
tKSO1
SCKp↑ to
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
25
ns
25
ns
25
ns
Cb = 30 pF, Rb = 1.4 kΩ
SOp output
Note 2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2.
When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution
Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different potential is not allowed in CSI01, CSI11.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 42 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
Remarks 1.
Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2.
p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
CSI mode connection diagram (during communication at different potential)
Vb
<Master>
Vb
Rb
Rb
SCK
SCKp
RL78/G12
SIp
SO
SOp
SI
User’s device
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Output data
Page 43 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Output data
Page 44 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
SCKp cycle time
Symbol
tKCY2
Conditions
MIN.
TYP.
MAX.
Unit
Noromal operation
4.0 V ≤ VDD ≤ 5.5 V,
20 MHz < fMCK ≤ 24 MHz
12/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
10/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
ns
2.7 V ≤ VDD < 4.0 V,
20 MHz < fMCK ≤ 24 MHz
16/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
14/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
12/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
8/fMCK
ns
fMCK ≤ 4 MHz
6/fMCK
ns
1.8 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
36/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
16 MHz < fMCK ≤ 20 MHz
32/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
26/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
10/fMCK
ns
SNOOZE mode
1
Mbps
SCKp high-/low-level
tKH2,
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
tKCY2/2 − 12
ns
width
tKL2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 − 18
ns
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2 − 50
ns
2.7 V ≤ VDD < 5.5 V
1/fMCK + 20
ns
1.8 V ≤ VDD < 3.3 V
1/fMCK + 30
ns
1/fMCK + 31
ns
SIp setup time
(to SCKp↑)
tSIK2
Note 1
SIp hold time
(from SCKp↑)
tKSI2
Note 2
Delay time from
tKSO2
SCKp↓ to SOp output
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
2/fMCK + 120
ns
2/fMCK + 214
ns
2/fMCK + 573
ns
Cb = 30 pF, Rb = 1.4 kΩ
Note 3
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
Notes 1.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp and SCKp pins by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different potential is not allowed in CSI01, CSI11.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 45 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
Remarks 1. Rb [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance,
Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn)
CSI mode connection diagram (during communication at different potential)
Vb
<Slave>
Rb
SCK
SCKp
RL78/G12
SIp
SO User’s device
SI
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
tKH1
SCKp
tSIK1
SIp
tKSI1
Input data
tKSO1
SOp
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Output data
Page 46 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2
tKH2
SCKp
tSIK2
tKSI2
Input data
SIp
tKSO2
SOp
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Output data
Page 47 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
SCLr clock frequency
fSCL
Conditions
MIN.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
MAX.
Unit
400
kHz
400
kHz
300
kHz
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “L”
tLOW
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
1150
ns
1150
ns
1550
ns
675
ns
600
ns
610
ns
1/fMCK
Note
ns
1/fMCK
Note
ns
1/fMCK
Note
ns
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Hold time when SCLr = “H”
tHIGH
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Data setup time (reception)
tSU:DAT
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
+190
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
+190
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
+190
Cb = 100 pF, Rb = 5.5 kΩ
Data hold time (transmission)
tHD:DAT
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
0
355
ns
0
355
ns
0
405
ns
Cb = 100 pF, Rb = 2.8 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
Note
Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution
Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1). Communication at
different potential is not allowed in IIC01, IIC11.
Remarks 1.
Rb [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communication line voltage
2.
r: IIC Number (r = 00, 20)
3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number (m = 0,1), n: Channel number (n = 0))
4.
2
Simplified I C mode is supported by the R5F102 products.
2
Simplified I C mode connection diagram (during communication at different potential)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 48 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
Vb
Rb
Vb
Rb
SDA
SDAr
RL78/G12
User’s device
SCL
SCLr
2
Simplified I C mode serial transfer timing (during communication at different potential)
1/f SCL
t LOW
t HIGH
SCLr
SDAr
t HD : DAT
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
t SU : DAT
Page 49 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.5.2 Serial interface IICA
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Standard Mode
MIN.
SCLA0 clock frequency
fSCL
Fast mode: fCLK ≥ 3.5 MHz
Normal mode: fCLK ≥ 1 MHz
Setup time of restart condition
Note 1
MAX.
0
tSU:STA
Fast Mode
Unit
MIN.
MAX.
0
400
kHz
100
kHz
4.7
0.6
μs
Hold time
tHD:STA
4.0
0.6
μs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
μs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
μs
tSU:DAT
250
100
ns
Data hold time (transmission)
tHD:DAT
0
Setup time of stop condition
tSU:STO
4.0
0.6
μs
Bus-free time
tBUF
4.7
1.3
μs
Data setup time (reception)
Note 2
Notes 1.
2.
3.45
0
μs
0.9
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
Remark
resistor) at that time in each mode are as follows.
Cb = 400 pF, Rb = 2.7 kΩ
Cb = 320 pF, Rb = 1.1 kΩ
Normal mode:
Fast mode:
IICA serial transfer timing
t LOW
tR
SCLA0
tHD:DAT
t HIGH
tF
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
tHD:STA
SDAA0
t BUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
2.5.3 On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Transfer rate
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Symbol
Conditions
MIN.
115.2 k
TYP.
MAX.
Unit
1M
bps
Page 50 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), (target
ANI pin : ANI2, ANI3)
(TA = −40 to +85°C, 1.8 V ≤VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
Conversion time
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
MIN.
TYP.
8
AINL
10-bit resolution
tCONV
AVREFP = VDD
1.2
MAX.
Unit
10
bit
±3.5
LSB
39
μs
3.6 V ≤ VDD ≤ 5.5 V
2.125
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
EZS
±0.25
%FSR
EFS
±0.25
%FSR
ILE
±2.5
LSB
DLE
±1.5
LSB
1.8
VDD
V
0
AVREFP
V
1.50
V
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
VBGR
Internal reference voltage is selected
1.38
1.45
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 51 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(2) When AVREF (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), (target
ANI pin : ANI16 to ANI22)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM =0 V)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
Conversion time
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
MIN.
TYP.
8
AINL
10-bit resolution
tCONV
AVREFP = VDD
1.2
MAX.
Unit
10
bit
±5.0
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
EZS
±0.35
%FSR
EFS
±0.35
%FSR
ILE
±3.5
LSB
DLE
±2.0
LSB
VDD
V
AVREFP
V
Reference voltage (+)
AVREFP
Analog input voltage
VAIN
1.8
0
and VDD
VBGR
Internal reference voltage is selected
1.38
1.45
1.5
V
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 52 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
(3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), (target ANI pin : ANI0 to
ANI3, ANI16 to ANI22)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter
Symbol
Resolution
Conditions
RES
Note 1
Overall error
AINL
Conversion time
tCONV
Notes 1, 2
Zero-scale error
Full-scale error
Notes 1, 2
Integral linearity error
Note 1
Differential linearity error
Note 1
Analog input voltage
MIN.
TYP.
8
10-bit resolution
1.2
MAX.
Unit
10
bit
±7.0
LSB
3.6 V ≤ VDD ≤ 5.5 V
2.125
39
μs
2.7 V ≤ VDD ≤ 5.5 V
3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
17
39
μs
EZS
±0.60
%FSR
EFS
±0.60
%FSR
ILE
±4.0
LSB
DLE
±2.0
LSB
VDD
V
1.50
V
VAIN
VBGR
0
Internal reference voltage is selected
1.38
1.45
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
(4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (−) = AVREFM (ADREFM = 1),
(target ANI pin : ANI0, ANI2, ANI3, ANI16 to ANI22)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR, Reference voltage (−) = AVREFM = 0 V,
HS (high-speed main) mode)
Parameter
Symbol
Resolution
Conditions
MIN.
RES
Conversion time
Notes 1, 2
Zero-scale error
Integral linearity error
Note 1
Differential linearity error
Note 1
TYP.
MAX.
8
Unit
bit
39
μs
±0.60
%FSR
ILE
±2.0
LSB
DLE
±1.0
LSB
1.5
V
VBGR
V
tCONV
8-bit resolution
EZS
AVREFM = 0 V, 2.4 V ≤ VDD ≤ 5.5 V
17
Reference voltage (+)
VBGR
1.38
Analog input voltage
VAIN
0
1.45
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 53 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode
Parameter
Temperature sensor output voltage
Symbol
VTMPS25
Conditions
MIN.
Setting ADS register = 80H,
TYP.
MAX.
1.05
Unit
V
TA = +25°C
Internal reference voltage
VCONST
Setting ADS register = 81H
Temperature coefficient
FVTMPS
Temperature sensor that
1.38
1.45
1.5
−3.6
V
mV/°C
depends on the temperature
Operation stabilization wait time
tAMP
5
μs
2.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Minimum pulse width
Detection delay time
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPOR
Power supply rise time
1.48
1.51
1.54
V
VPDR
Power supply fall time
1.47
1.50
1.53
V
TPW
μs
300
350
μs
Page 54 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Detection supply voltage
Symbol
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
Minimum pulse width
Detection delay time
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
tLW
Conditions
MIN.
TYP.
MAX.
Unit
Power supply rise time
3.98
4.06
4.14
V
Power supply fall time
3.90
3.98
4.06
V
Power supply rise time
3.68
3.75
3.82
V
Power supply fall time
3.60
3.67
3.74
V
Power supply rise time
3.07
3.13
3.19
V
Power supply fall time
3.00
3.06
3.12
V
Power supply rise time
2.96
3.02
3.08
V
Power supply fall time
2.90
2.96
3.02
V
Power supply rise time
2.86
2.92
2.97
V
Power supply fall time
2.80
2.86
2.91
V
Power supply rise time
2.76
2.81
2.87
V
Power supply fall time
2.70
2.75
2.81
V
Power supply rise time
2.66
2.71
2.76
V
Power supply fall time
2.60
2.65
2.70
V
Power supply rise time
2.56
2.61
2.66
V
Power supply fall time
2.50
2.55
2.60
V
Power supply rise time
2.45
2.50
2.55
V
Power supply fall time
2.40
2.45
2.50
V
Power supply rise time
2.05
2.09
2.13
V
Power supply fall time
2.00
2.04
2.08
V
Power supply rise time
1.94
1.98
2.02
V
Power supply fall time
1.90
1.94
1.98
V
Power supply rise time
1.84
1.88
1.91
V
Power supply fall time
1.80
1.84
1.87
V
μs
300
300
μs
Page 55 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
LVD detection voltage of interrupt & reset mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
LVD detection
VLVD11
voltage
VLVD10
VLVD9
VLVD2
VLVD8
VLVD7
VLVD6
VLVD1
VLVD5
VLVD4
VLVD3
VLVD0
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Conditions
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V
MIN.
TYP.
MAX.
Unit
1.80
1.84
1.87
V
LVIS1, LVIS0 = 1, 0
Rising reset release voltage
1.94
1.98
2.02
V
(+0.1 V)
Falling interrupt voltage
1.90
1.94
1.98
V
LVIS1, LVIS0 = 0, 1
Rising reset release voltage
2.05
2.09
2.13
V
(+0.2 V)
Falling interrupt voltage
2.00
2.04
2.08
V
LVIS1, LVIS0 = 0, 0
Rising reset release voltage
3.07
3.13
3.19
V
(+1.2 V)
Falling interrupt voltage
3.00
3.06
3.12
V
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V
2.40
2.45
2.50
V
LVIS1, LVIS0 = 1, 0
Rising reset release voltage
2.56
2.61
2.66
V
(+0.1 V)
Falling interrupt voltage
2.50
2.55
2.60
V
LVIS1, LVIS0 = 0, 1
Rising reset release voltage
2.66
2.71
2.76
V
(+0.2 V)
Falling interrupt voltage
2.60
2.65
2.70
V
LVIS1, LVIS0 = 0, 0
Rising reset release voltage
3.68
3.75
3.82
V
(+1.2 V)
Falling interrupt voltage
3.60
3.67
3.74
V
VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage: 2.7 V
2.70
2.75
2.81
V
LVIS1, LVIS0 = 1, 0
Rising reset release voltage
2.86
2.92
2.97
V
(+0.1 V)
Falling interrupt voltage
2.80
2.86
2.91
V
LVIS1, LVIS0 = 0, 1
Rising reset release voltage
2.96
3.02
3.08
V
(+0.2 V)
Falling interrupt voltage
2.90
2.96
3.02
V
LVIS1, LVIS0 = 0, 0
Rising reset release voltage
3.98
4.06
4.14
V
(+1.2 V)
Falling interrupt voltage
3.90
3.98
4.06
V
Page 56 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter
Data retention supply voltage
Symbol
Conditions
MIN.
VDDDR
1.47
TYP.
Note
MAX.
Unit
5.5
V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is affected, but data is not retained when a POR reset is affected.
Operation mode
STOP mode
Data retention mode
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.8 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
System clock frequency
Code flash memory rewritable times
Symbol
fCLK
Cerwr
Conditions
MIN.
1.8 V ≤ VDD ≤ 5.5 V
TYP.
1
Retained for 20 years
TA = 85°C
Note 3
Retained for 1 year
TA = 25°C
Note 3
Retained for 5 years
TA = 85°C
Note 3
100,000
Retained for 20 years
TA = 85°C
Note 3
10,000
MAX.
Unit
24
MHz
Times
1,000
Notes 1.2.3
Data flash memory rewritable times
Notes 1.2.3
1,000,000
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self program library.
3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas
Electronics Corporation.
Caution This specifications show target values, which may change after device evaluation.
Remark
When updating data multiple times, use the flash memory as one for updating data.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 57 of 61
RL78/G12
CHAPTER 2 ELECTRICAL SPECIFICATIONS
2.9 Timing Specs for Flash Memory Programming Switching Modes
Parameter
Symbol
Conditions
MIN.
TYP.
POR and LVD reset are
How long from when an external reset ends until tSUINIT
the initial communication settings are specified
MAX.
Unit
100
ms
released before external
reset release
How long from when the TOOL0 pin is placed at tsu
10
μs
1
ms
the low level until an external reset ends
How long the TOOL0 pin must be kept at the low tHD
level after a reset ends
(except soft processing time)
<1>
<2>
<4>
<3>
RESET
tHD+
software
processing
time
00H reception
(TOOLRxD, TOOLTxD mode)
TOOL0
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the pin reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark
tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
tSU:
How long from when the TOOL0 pin is placed at the low level until an external reset ends.
tHD:
How long to keep the TOOL0 pin at the low level from when the external and internal resets end.
(except soft processing time)
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 58 of 61
RL78/G12
CHAPTER 3 PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1 20-pin products
R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP
R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP
R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP
R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65
PLSP0020JB-A
P20MA-65-NAA-1
0.1
2
D
detail of lead end
11
20
E
1
c
10
1
L
3
bp
A
A2
A1
HE
e
y
(UNIT:mm)
NOTE
1.Dimensions “
2.Dimension “
1” and “
2”
” does not include tr
ITEM
DIMENSIONS
D
E
6.50 0.10
4.40 0.10
HE
6.40 0.20
A
1.45 MAX.
A1
0.10 0.10
A2
1.15
e
bp
c
L
y
0.65 0.12
0.22 0.10
0.05
0.15 0.05
0.02
0.50 0.20
0.10
0 to 10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 59 of 61
RL78/G12
CHAPTER 3 PACKAGE DRAWINGS
3.2 24-pin products
R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA
R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA
R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA
R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-1
0.04
D
DETAIL OF A PART
E
S
A
A
S
y
S
(UNIT:mm)
ITEM
D2
A
EXPOSED DIE PAD
1
6
D
4.00 0.05
E
4.00 0.05
A
0.75 0.05
b
0.25 0.05
0.07
e
7
24
Lp
B
DIMENSIONS
0.50
0.40 0.10
x
0.05
y
0.05
E2
ITEM
19
12
18
EXPOSED
DIE PAD
VARIATIONS
13
D2
E2
MIN NOM MAX MIN NOM MAX
A 2.45 2.50 2.55 2.45 2.50 2.55
e
Lp
b
x
M
S AB
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 60 of 61
RL78/G12
CHAPTER 3 PACKAGE DRAWINGS
3.3 30-pin products
R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP
R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP
R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP
R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-LSSOP30-0300-0.65
PLSP0030JB-B
S30MC-65-5A4-3
0.18
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
M
K
ITEM
A
MILLIMETERS
9.85 0.15
B
0.45 MAX.
C
0.65 (T.P.)
NOTE
D
0.24 0.08
0.07
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
E
0.1 0.05
F
1.3 0.1
G
1.2
H
8.1 0.2
I
6.1 0.2
J
1.0 0.2
K
0.17 0.03
L
0.5
M
0.13
N
0.10
P
3
T
0.25
U
0.6 0.15
5
3
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0193EJ0100 Rev.1.00
Dec 10, 2012
Page 61 of 61
Revision History
RL78/G12 Data Sheet
Rev.
Date
Page
1.00
Dec 10, 2012
-
Description
Summary
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C-1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
5.
Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 2.2
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement