phyCORE-AM3517 Hardware Manual

phyCORE-AM3517 Hardware Manual

phyCORE-AM3517

System on Module and Carrier Board

Hardware Manual

Document No:

Product No:

SOM PCB No:

L-761e_2

PCM-048/PCM-961

1335.1

CB PCB No:

1336.1

Edition: March 21, 2012

A product of a PHYTEC Technology Holding Company

phyCORE-AM3517 L-761e_2

In this manual are descriptions for copyrighted products that are not explicitly indicated as such. The absence of the trademark (™) and copyright (©) symbols does not imply that a product is not protected.

Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is believed to be entirely reliable.

However, PHYTEC America LLC assumes no responsibility for any inaccuracies. PHYTEC America LLC neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC America LLC reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

Additionally, PHYTEC America LLC offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC America LLC further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

© Copyright 2011 PHYTEC America LLC, Bainbridge Island, WA.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC America LLC.

EUROPE

Address:

PHYTEC Technologie Holding AG

Robert-Koch-Str. 39

D-55129 Mainz

GERMANY

Ordering Information:

+49 (800) 0749832

Technical Support:

+49 (6131) 9221-31

Fax:

+49 (6131) 9221-33

Website:

http://www.phytec.eu/europe

NORTH AMERICA

PHYTEC America LLC

203 Parfitt Way SW, Suite G100

Bainbridge Island, WA 98110

USA

1 (800) 278-9913

1 (800) 278-9913

1 (206) 780-9135 http://www.phytec.com

© PHYTEC America LLC 2012 L-761e_2

Table of Contents L-761e_2

Table of Contents

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Conventions, Abbreviations, and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Part I: PCM-048/phyCORE-AM3517 System on Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 View of the phyCORE-AM3517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Primary System Power (VIN & VIN_3V3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Secondary Battery Power (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 PMIC Supplies (U2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 RTC Supplies (U2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.5 Selecting Shunt Resistors for Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.6 Voltage Supervisor (U2, U21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 External RTC (U22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6 System Configuration and Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1 Boot Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 System Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 SDRAM (U8, U9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2 NAND Flash (U16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.3 EEPROM (U13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Serial Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1 RS-232 Transceiver (U15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.2 Ethernet PHY (U12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.3 USB OTG (U1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.4 USB1 Host (U1, U7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Debug Interface (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10 Touch Screen Controller (U25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 General Purpose Memory Controller (U2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12 LCD LVDS Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1 LVDS and SOM I/O Voltage (J23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

13 AM3517 IO and GPMC Bus Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

14 Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

15 Hints for Handling the phyCORE-AM3517 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Part II: PCM-961/phyCORE-AM3517 Carrier Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

17 Overview of Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

18 Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

19 phyCORE-AM3517 SOM Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

20 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

20.1 Wall Adapter Input (X9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

20.2 Power over Ethernet (PoE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

© PHYTEC America LLC 2012 i

Table of Contents L-761e_2

20.3 Lithium-Ion Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

20.4 3.3V Supply (U27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

20.5 1.8V Supply (U31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

20.6 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

21 JTAG Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

22 Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

23 Ethernet Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

24 USB Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

25 LCD and DVI Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

25.1 DVI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

25.2 LVDS Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

25.3 TTL LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

26 GPIO Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

27 RS-232 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

28 SD/SDIO/MMC Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

29 CAN (Controller Area Network) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

30 Wireless Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

31 TV Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

32 Camera Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

33 User Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

34 User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

35 Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

36 System Reset Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Part III: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Part III: PCM-988/GPIO Expansion Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

38 System Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

39 GPMC Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

40 UART Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

41 I²C Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

42 GPIO Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

43 USB Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

44 CAN Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

45 Ethernet Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

46 HDQ Signal Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

47 McBSP Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

48 SPI Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

49 Power Signal Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

© PHYTEC America LLC 2012 ii

List of Tables L-761e_2

List of Tables

Conventions, Abbreviations, and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Table i-1. Abbreviations and Acronyms Used in This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Part I: PCM-048/phyCORE-AM3517 System on Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2-1. Pin Descriptions, phyCORE-Connector X2, Row A . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2-2. Pin Descriptions, phyCORE-Connector X2, Row B . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2-3. Pin Descriptions, phyCORE-Connector X2, Row C . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2-4. Pin Descriptions, phyCORE-Connector X2, Row D . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3-1. Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4-1. Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 6-1. Peripheral Booting Configuration Pins after POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6-2. Booting Configuration Pins after a Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7-1. Valid SDRAM Memory Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7-2. LOCK Pin Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7-3. phyCORE-AM3517 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8-1. UART3 TTL and RS-232 Level Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 8-2. Applicable USB Operating Mode Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11-1. GPMC Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 14-1. Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 14-2. Static Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Part II: PCM-961/phyCORE-AM3517 Carrier Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 17-1. Connectors and Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 17-2. Description of the Buttons and Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 17-3. Description of LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 18-1. Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 20-1. Possible Ethernet PSE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 21-1. phyCORE-AM3517 JTAG Connector X13 Pin Descriptions . . . . . . . . . . . . . . . . . . 60

Table 21-2. Compatible JTAG Probes for the phyCORE-AM3517 Carrier Board . . . . . . . . . . . . 61

Table 25-1. 24-bit 8:8:8 mode (S1-1,S1-2, S1-3, S1-4 = O,O,O,O) . . . . . . . . . . . . . . . . . . . . . . 69

Table 25-2. 12-bit 4:4:4 mode (S1-1,S1-2, S1-3, S1-4 = C, C, C, O) . . . . . . . . . . . . . . . . . . . . . 69

Table 25-3. 16-bit 5:6:5 mode (S1-1,S1-2, S1-3, S1-4 = C, C, O, C) . . . . . . . . . . . . . . . . . . . . . 69

Table 25-4. 18-bit 6:6:6 mode (S1-1,S1-2, S1-3, S1-4 = C, C, O, O) . . . . . . . . . . . . . . . . . . . . . 69

Table 25-5. LCD Mode Jumper Summary (S1-1,S1-2, S1-3, S1-4) . . . . . . . . . . . . . . . . . . . . . . 70

Table 27-1. Connector P1 (UART3) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 27-2. Connector X29 (UART2) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 27-3. TTL UART Pin Header (X10) Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 28-1. SDIO Easy Access Header Connector Signal Descriptions . . . . . . . . . . . . . . . . . . . 78

Table 30-1. Wireless Connector (X7) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 32-1. Camera Interface (X4) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 35-1. Boot Selection Switches and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 35-2. Boot Order Switch Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Part III: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Part III: PCM-988/GPIO Expansion Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 37-1. GPIO Expansion Connector - Signals Removed . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 38-1. System Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 39-1. GPMC Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 40-1. UART Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 41-1. I²C Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

© PHYTEC America LLC 2012 iii

List of Tables L-761e_2

Table 42-1. GPIO Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 43-1. USB Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 44-1. CAN Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 45-1. Ethernet Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 46-1. HDQ Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 47-1. McBSP Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 48-1. SPI Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 49-1. Power Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 50-1. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

© PHYTEC America LLC 2012 iv

List of Figures L-761e_2

List of Figures

Part I: PCM-048/phyCORE-AM3517 System on Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Fig. 1-1. phyCORE-AM3517 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Fig. 1-2. Top View of the phyCORE-AM3517 (Controller Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Fig. 1-3. Bottom View of the phyCORE-AM3517 (Connector Side) . . . . . . . . . . . . . . . . . . . . . . . . 6

Fig. 2-1. Pin-out of the phyCORE-Connector

(Top View, with Cross Section Insert) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Fig. 3-1. Jumper Locations (Connector Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Fig. 3-2. Jumper Locations (Controller Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fig. 3-3. Default Jumper Settings (Connector Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Fig. 3-4. Default Jumper Settings (Controller Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Fig. 9-1. JTAG Interface X1 (Controller Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Fig. 12-1. LVDS Multiplexing Scheme

1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Fig. 14-1. phyCORE-AM3517 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Part II: PCM-961/phyCORE-AM3517 Carrier Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Fig. 16-1. phyCORE-AM3517 Carrier Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Fig. 17-1. Overview of Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Fig. 18-1. Jumper Locations and Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Fig. 18-2. Typical Jumper Pad Numbering Scheme (Removable Jumpers) . . . . . . . . . . . . . . . . 51

Fig. 19-1. phyCORE-AM3517 SOM Connectivity to the Carrier Board . . . . . . . . . . . . . . . . . . . . 55

Fig. 20-1. Powering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Fig. 21-1. JTAG Probe Connectivity to the phyCORE-AM3517 . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Fig. 22-1. Audio Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig. 23-1. Ethernet Interface Connector and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Fig. 24-1. USB Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Fig. 25-1. LCD/DVI Interface Connectors, Jumpers, and Switches . . . . . . . . . . . . . . . . . . . . . . . 67

Fig. 25-2. LCD Signal Mapping in 24-bit Mode with a 24-bit LCD . . . . . . . . . . . . . . . . . . . . . . . . 68

Fig. 25-3. LCD Signal Mapping in 16-bit Mode with an 16-Bit LCD . . . . . . . . . . . . . . . . . . . . . . . 68

Fig. 26-1. GPIO Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Fig. 27-1. RS-232 Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Fig. 27-2. DB9 RS-232 Connectors P1 (UART3) Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . . 73

Fig. 27-3. Connector X29 (UART2) Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Fig. 27-4. UART3/UART2 Header Connector X10 Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . 75

Fig. 28-1. SDIO Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig. 29-1. CAN Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Fig. 30-1. Wireless Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Fig. 31-1. TV Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Fig. 32-1. Camera Interface Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Fig. 33-1. User Buttons and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Fig. 34-1. User LEDs and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Fig. 35-1. Boot Mode Selection Connectors and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Fig. 35-2. Boot Switches - Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Fig. 36-1. System Reset Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Part III: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Part III: PCM-988/GPIO Expansion Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig. 37-1. PCM-988/GPIO Expansion Board and Patch Field . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

© PHYTEC America LLC 2012 v

L-761e_2

Conventions, Abbreviations, and Acronyms

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by a “/” character are designated as active low signals. Their active state is when they are driven low, or are driving low; for example: /RESET.

• Tables show the default setting or jumper position in

bold, teal text.

• Text in blue indicates a hyperlink, either internal or external to the document. Click these links to quickly jump to the applicable URL, part, chapter, table, or figure.

• References made to the phyCORE-Connector always refer to the high density molex connectors on the underside of the phyCORE-AM3517 System on Module.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms used in this document.

Table i-1. Abbreviations and Acronyms Used in This Manual

Abbreviation

BTN1

BTN2

BTN3

BTN4

CB

CPLD

EMI

GPI

GPIO

GPIOEBPF

GPMC

GPO

J

JP

PCB

PoE

POT

PMIC

PSE

Definition

User button 1; used in reference to one of the four available user buttons on the Carrier Board

User button 2; used in reference to one of the four available user buttons on the Carrier Board

User button 3; used in reference to one of the four available user buttons on the Carrier Board

User button 4; used in reference to one of the four available user buttons on the Carrier Board

Carrier Board; used in reference to the PCM-961/phyCORE-AM3517 Carrier Board

Complex Programmable Logic Device

Electromagnetic Interference

General purpose input

General purpose input and output

GPIO Expansion Board Patch Field; used in reference with the PCM-988/GPIO

Expansion Board and its associated patch field

General Purpose Memory Controller

General purpose output

Solder jumper; these types of jumpers require solder equipment to remove and place

Solderless jumper; these types of jumpers can be removed and placed by hand with no special tools

Printed circuit board

Power over Ethernet

Potentiometer

Power Management Integrated Circuit

Power sourcing equipment; the device in a PoE network that provides power to connected devices - usually a switch, router, or stand alone power injector

© PHYTEC America LLC 2012 vi

L-761e_2

Table i-1. Abbreviations and Acronyms Used in This Manual

Abbreviation

RTC

SMT

SOM

TRM

VBAT

VFP

Definition

Real-time clock

Surface mount technology

System on Module; used in reference to the PCM-048/phyCORE-AM3517 System on Module

Technical Reference Manual

SOM battery supply input

Vector Floating Point

© PHYTEC America LLC 2012 vii

L-761e_2

Preface

This phyCORE-AM3517 Hardware Manual describes the System on Module's design and functions.

Precise specifications for the Texas Instruments AM3517 processor can be found in the processor datasheet and/or user's manual.

In this hardware manual and in the schematics, active low signals are denoted by a "/" preceding the signal name, for example: /RD. A "0" represents a logic-zero or low-level signal, while a "1" represents a logicone or high-level signal.

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE-AM3517

PHYTEC System on Modules (SOMs) are designed for installation in electrical appliances or, combined with the PHYTEC Carrier Board, can be used as dedicated Evaluation Boards (for use as a test and prototype platform for hardware/software development) in laboratory environments.

CAUTION:

PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only be unpacked, handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m.

PHYTEC products fulfill the norms of the European Union's Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector and serial interface to a host-PC).

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of

PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro

Magnetic Directives. Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems.

The phyCORE-AM3517 is one of a series of PHYTEC System on Modules that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports a variety of

8-/16- and 32-bit controllers in two ways:

1.

As the basis for Rapid Development Kits which serve as a reference and evaluation platform.

2.

As insert-ready, fully functional phyCORE OEM modules, which can be embedded directly into the user's peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware further reduce development time and expenses. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. For more information go to: http://www.phytec.com/services/design-services/index.html

© PHYTEC America LLC 2012 viii

PCM-048/phyCORE-AM3517 System on Module L-761e_2

Part I: PCM-048/phyCORE-AM3517 System on

Module

Part 1 of this three part manual provides detailed information on the phyCORE-AM3517 System on Module

(SOM) designed for custom integration into customer applications.

The information in the following chapters is applicable to the 1335.1 PCB revision of the phyCORE-

AM3517 SOM.

© PHYTEC America LLC 2012 1

Part I, Chapter 1: Introduction L-761e_2

1 Introduction

The phyCORE-AM3517 belongs to PHYTEC’s phyCORE System on Module (SOM) family. The phyCORE SOMs represent the continuous development of PHYTEC SOM technology. Like its mini-, micro-, and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

As independent research indicates that approximately 70% of all EMI (Electro Magnetic Interference) problems stem from insufficient supply voltage grounding of electronic components in high frequency environments, the phyCORE board design features an increased pin package. The increased pin package allows dedication of approximately 20% of all connector pins on the phyCORE boards to ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments.

phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled

Microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE-AM3517 is a sub-miniature (72 x 58 mm) insert-ready SOM populated with Texas

Instruments AM3517 ARM Cortex-A8 core processor. Its universal design enables its insertion into a wide range of embedded applications. All processor signals and ports extend from the processor to high-density pitch (0.635 mm) connectors aligning two sides of the board. This allows the SOM to be plugged like a "big chip" into a target application.

Precise specifications for the processor populating the board can be found in the applicable processor user's manual and datasheet. The descriptions in this manual are based on the Texas Instruments ARM

Cortex A8/AM3517 processor. No description of compatible processor derivative functions is included, as such functions are not relevant for the basic functioning of the phyCORE-AM3517.

The phyCORE-AM3517 offers the following features:

• Insert-ready, sub-miniature (72 x 58 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology

• Populated with the Texas Instruments AM3517 processor (491-ball BGA packaging)

• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• Controller signals and ports extend to two 160-pin high-density (0.635 mm) Molex connectors aligning two sides of the board, enabling it to be plugged like a "big chip" into target application

• Maximum 600 MHz core clock frequency

• NEON (TM) SIMD co-processor and Vector Floating Point (VFP) co-processor

• 16KB instruction cache (4-way set-associative)

• 16KB data cache (4-way set-associative)

• 256KB L2 cache

• System direct memory access (sDMA) controller (32 logical channels with configurable priority)

• Memory Management Unit (MMU)

• 32-bit DDR2-333MHz, 256 or 512MByte SDRAM running at 1.8V

• General Purpose Memory Controller supporting 16-bit wide multiplexed address/data bus

• 12 32-bit General Purpose Timers

• 64 KB SRAM

• 128, 256, or 512 MB of on-board NAND flash at 1.8V (bootable)

• HD resolution display subsystem:

Parallel Digital Output

Up to 24-Bit RGB

© PHYTEC America LLC 2012 2

Part I, Chapter 1: Introduction L-761e_2

Supports up to two LCD Panels

Support for Remote Frame Buffer Interface (RFBI) LCD Panels supporting

Two 10-bit Digital-to-Analog Converters (DACs) supporting Composite NTSC/PAL Video and

Luma/Chroma Separate Video (S-Video)

Rotation 90, 180, and 270 degrees; image resizing from 1/4x to 8x

Color Space Converter

8-bit Alpha Blending

• Video Processing Front End (VPFE) 16-bit video input port:

RAW data interface

75-MHz maximum pixel clock

Supports REC656/CCIR656 standard chip

Supports YCbCr422 format (8-bit or 16-bit with discrete horizontal and vertical sync signals)

Generates optical black clamping signals

Built-in digital clamping and black level compensation

10-bit to 8-bit A-law compression hardware

Up to 16K Pixels (Image Size) in horizontal and vertical directions

• 10/100 Mbit Ethernet (MAC and PHY)

• Multiport USB Host Subsystem [HS/FS/LS] DP/DM interface

• USB OTG transceiver for embedded USB host/peripheral functionality

• High-End CAN Controller (HECC)

• Six rail voltage supervision PMIC with programmable processor core voltage support and RTC priority voltage switch

• One 32-bit Watchdog Timer (internal to AM3517)

• Support for RealView ICE debug through standard JTAG interface

• Four Master/Slave Multichannel Serial Port Interface (McSPI) ports

• Five Multichannel Buffered Serial Ports: one 5K-Byte Transmit/Receive Buffer (McBSP2) and four

512-Byte transmit/receive buffers (McBSP1/3/4/5)

• Three Master/Slave high-speed Inter-Integrated circuit (I²C) controllers

• Two I²C ports

• 10/100 Ethernet with HP Auto MDIX support

• 24-bit LCD controller supporting STN and TFT panels at up to 1024x768 display resolution at

60Hz and 2048x2048 resolution at lower frame rates (PCLK max 75MHz).

• Touch screen controller

• Three removable media interfaces [MMC/SD/SDIO]

• Real-time clock (RTC) with dedicated interrupt (alarm clock function) and processor independent

RTC consuming less than 275nA at 3.0V typical

• Boot from NAND, USB, MMC/SDIO, Ethernet, and more

• JTAG interface for debugging and download of user code

• Up to 186 General-Purpose I/O (GPIO) pins

• Configurable IO voltage of 1.8V or 3.3V

• Single input supply voltage of 3.3 to 5.0V

• Industrial temperature range (-40C to +85C)

© PHYTEC America LLC 2012 3

Part I, Chapter 1: Introduction

1.1 Block Diagram

L-761e_2

Fig. 1-1. phyCORE-AM3517 Block Diagram

© PHYTEC America LLC 2012 4

Part I, Chapter 1: Introduction

1.2 View of the phyCORE-AM3517

L-761e_2

Fig. 1-2. Top View of the phyCORE-AM3517 (Controller Side)

© PHYTEC America LLC 2012 5

Part I, Chapter 1: Introduction L-761e_2

Fig. 1-3. Bottom View of the phyCORE-AM3517 (Connector Side)

© PHYTEC America LLC 2012 6

Part I, Chapter 2: Pin Description L-761e_2

2 Pin Description

Please note that all module connections are not to exceed their expressed maximum voltage or current.

Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

All controller signals extend to surface mount technology (SMT) connectors (0.635 mm) lining two sides of the module (referred to as the phyCORE-Connector). This allows the phyCORE-AM3517 to be plugged into any target application like a "big chip."

The numbering scheme for the phyCORE-Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number. Pin 1A, for example, is always located in the upper left hand corner of the matrix. The pin numbering values increase moving down on the board. Lettering of the pin connector rows progresses alphabetically from left to right (refer to

Figure 2-1

).

The numbered matrix can be aligned with the phyCORE-AM3517 (viewed from above; phyCORE-

Connector pointing down) or with the socket of the corresponding phyCORE Carrier Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-AM3517 marked with a number 1. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

The numbering scheme is thus consistent for both the module’s phyCORE-Connector as well as mating connectors on the phyCORE Carrier Board or target hardware, thereby considerably reducing the risk of pin identification errors.

Since the pins are exactly defined according to the numbered matrix previously described, the phyCORE-

Connector is usually assigned a single designator for its position (X2 for example). In this manner the phyCORE-Connector comprises a single, logical unit regardless of the fact that it could consist of more than one physical socketed connector. The location of row 1 on the board is marked by a number 1 on the

PCB to allow easy identification.

Figure 2-1

illustrates the numbered matrix system. It shows a phyCORE-AM3517 with SMT phyCORE-

Connectors on its underside (defined as dotted lines) mounted on a Carrier Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a cross-view of the phyCORE module showing these phyCORE-Connectors mounted on the underside of the module’s PCB.

© PHYTEC America LLC 2012 7

Part I, Chapter 2: Pin Description L-761e_2

Fig. 2-1. Pin-out of the phyCORE-Connector

(Top View, with Cross Section Insert)

9A

10A

11A

12A

13A

14A

15A

16A

5A

6A

7A

8A

1A

2A

3A

4A

17A

18A

19A

20A

21A

22A

Table 2-1. Pin Descriptions, phyCORE-Connector X2, Row A

Pin Signal

GPMC_NCS7

GND

GPMC_NCS3

GPMC_NCS2

GPMC_NCS1 xGPMC_NWE

GND

GPMC_NBE0_CLE

GPMC_NBE1

GPMC_WAIT0

GPMC_WAIT2

GND

GPMC_A9

GPMC_A8

GPMC_A7

GPMC_A4

GND

GPMC_A1

GPMC_D15

GPMC_D14

GPMC_D11

GND

I/O

Signal

Level

Description

O VDDSHV GPMC interface - control (active low chip select 7)

Ground

O VDDSHV GPMC interface - control (active low chip select 3)

O VDDSHV GPMC interface - control (active low chip select 2)

O VDDSHV GPMC interface - control (active low chip select 1)

O VDDSHV GPMC interface - control (active low write enable)

Ground

O VDDSHV GPMC interface - control (active low bus enable 0)

-

I

O VDDSHV GPMC interface - control (active low bus enable 1)

I VDDSHV GPMC interface - control (active low wait signal)

VDDSHV

-

GPMC interface - control (active low wait signal)

Ground

O VDDSHV GPMC interface - address

O VDDSHV GPMC interface - address

O VDDSHV GPMC interface - address

O VDDSHV GPMC interface - address

-

I

I

I

Ground

O VDDSHV GPMC interface - address

VDDSHV

VDDSHV

GPMC interface - data

GPMC interface - data

VDDSHV GPMC interface - data

Ground

© PHYTEC America LLC 2012 8

Part I, Chapter 2: Pin Description L-761e_2

Table 2-1. Pin Descriptions, phyCORE-Connector X2, Row A (Continued)

Pin

32A

33A

34A

35A

36A

37A

38A

39A

40A

41A

42A

43A

23A

24A

25A

26A

27A

28A

29A

30A

31A

44A

45A

46A

47A

48A

49A

50A

51A

52A

53A

54A

55A

56A

Signal

GPMC_D8

GPMC_D7

GPMC_D6

GPMC_D3

GND

GPMC_D0

CCDC_WEN

CCDC_VD

CCDC_FIELD

GND

CCDC_DATA5

CCDC_DATA4

CCDC_DATA3

CCDC_DATA0

GND

RMII_MDIO_CLK

RMII_MDIO_DATA

RMII_RXD1

RMII_RXER

GND

ETK_D15

ETK_D14

ETK_D13

ETK_D10

GND

HSUSB1_DATA3

HSUSB1_DATA6

HSUSB1_DATA5

HSUSB1_DATA2

GND

HSUSB1_STP xHSUSB1_CLK

MMC2_DAT7

MMC2_DAT4

I/O

Signal

Level

Description

I

I

I

I VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

-

I

Ground

VDDSHV GPMC interface - data

I VDDSHV CCD Camera interface - control (write enable)

IO VDDSHV CCD Camera interface - control (vertical sync)

IO VDDSHV CCD Camera interface - control (field identification)

I

I

-

I

Ground

VDDSHV CCD Camera interface - data

VDDSHV CCD Camera interface - data

VDDSHV CCD Camera interface - data

-

I VDDSHV CCD Camera interface - data

Ground

O VDDSHV Ethernet - MDIO interface clock

IO VDDSHV Ethernet - MDIO interface data

I

I VDDSHV Ethernet MAC - RMII data RX data

VDDSHV Ethernet MAC - RMII data RX error

Ground

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

Ground

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

Ground

O VDDSHV High Speed USB digital interface - control

O VDDSHV High speed USB digital interface 1 - clock

IO VDDSHV MMC / SDIO 2 interface - data

IO VDDSHV MMC / SDIO 2 interface - data

© PHYTEC America LLC 2012 9

Part I, Chapter 2: Pin Description L-761e_2

Table 2-1. Pin Descriptions, phyCORE-Connector X2, Row A (Continued)

Pin

57A

58A

59A

60A

61A

62A

63A

64A

65A

75A

76A

77A

78A

79A

80A

66A

67A

68A

69A

70A

71A

72A

73A

74A

Signal

GND

MMC2_DAT1

MMC2_DAT0

MMC2_CMD

MCSPI2_CS1

GND

MCSPI2_CS0

MCSPI2_SIMO

MCSPI2_SOMI xMCSPI2_CLK

GND

TV_OUT1

TV_OUT2

MCBSP4_CLKX

MCBSP4_DR

GND

MCBSP4_DX

MCBSP4_FSX

N/C

JTAG_EMU0

GND

JTAG_NTRST

JTAG_TDI xJTAG_TDO

I/O

Signal

Level

Description

Ground

IO VDDSHV MMC / SDIO 2 interface - data

IO VDDSHV MMC / SDIO 2 interface - data

O VDDSHV MMC / SDIO 2 interface - command

O VDDSHV Multichannel Serial Peripheral Interface 2 - chip select 1

Ground

IO VDDSHV Multichannel Serial Peripheral Interface 2 - chip select 0

IO VDDSHV Multichannel Serial Peripheral Interface 2 - slave data in, master data out

IO VDDSHV Multichannel Serial Peripheral Interface 2 - slave data out, master data in

IO VDDSHV Multichannel Buffered Serial Port 2 - clock

Ground

O

O

Analog TV Out signal 1

Analog TV Out signal 2

IO VDDSHV Multichannel Buffered Serial Port 4 - TX clock

I VDDSHV Multichannel Buffered Serial Port 4 - data receive

Ground

IO VDDSHV Multichannel Buffered Serial Port 4 - data transmit

IO VDDSHV Multichannel Buffered Serial Port 4 - frame sync transmit

-

I

No connect

IO VDDSHV JTAG - test emulation

-

VDDSHV

Ground

JTAG - test reset

I VDDSHV JTAG - test data in

O VDDSHV JTAG - test data out

Table 2-2. Pin Descriptions, phyCORE-Connector X2, Row B

Pin

1B

2B

3B

4B

5B

Signal

GPMC_NCS6

GPMC_NCS5

GPMC_NCS4

GND

N/C

I/O

Signal

Level

Description

O VDDSHV GPMC interface - control

O VDDSHV GPMC interface - control

O VDDSHV GPMC interface - control

Ground

No connect

© PHYTEC America LLC 2012 10

Part I, Chapter 2: Pin Description L-761e_2

30B

31B

32B

33B

34B

35B

36B

37B

22B

23B

24B

25B

26B

27B

28B

29B

38B

39B

40B

41B

42B

43B

14B

15B

16B

17B

18B

19B

20B

21B

6B

7B

8B

9B

10B

11B

12B

13B

Table 2-2. Pin Descriptions, phyCORE-Connector X2, Row B (Continued)

Pin Signal I/O

Signal

Level

Description

GPMC_NWP

GPMC_NOE

O VDDSHV GPMC interface - control (active low write protect)

O VDDSHV GPMC interface - control (active low output enable) xGPMC_NADV_ALE O VDDSHV GPMC interface - control

GND Ground

GPMC_WAIT1

GPMC_WAIT3 xGPMC_CLK

GPMC_A10

I

I

O

O

VDDSHV

VDDSHV

VDDSHV

VDDSHV

GPMC interface - control (active low wait)

GPMC interface - control (active low wait)

GPMC interface - clock

GPMC interface - address

GND

GPMC_A6

GPMC_A5

GPMC_A3

GPMC_A2

GND

GPMC_D13

GPMC_D12

-

O VDDSHV GPMC interface - address

-

I

I

-

O VDDSHV GPMC interface - address

O VDDSHV GPMC interface - address

O VDDSHV GPMC interface - address

-

VDDSHV

VDDSHV

Ground

Ground

GPMC interface - data

GPMC interface - data

GPMC_D10

GPMC_D9

GND

GPMC_D5

GPMC_D4

GPMC_D2

GPMC_D1

GND

CCDC_PCLK

CCDC_HD

CCDC_DATA7

CCDC_DATA6

GND

CCDC_DATA2

CCDC_DATA1

RMII_50MHZ_CLK

RMII_CRS_DV

GND

RMII_RXD0

RMII_TXD1

RMII_TXD0

RMII_TXEN

-

I

-

I

I

-

I

I

I

I

I

-

I

I

I

I

I

O

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

Ground

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

VDDSHV GPMC interface - data

Ground

IO VDDSHV CCD Camera interface - control (pixel clock)

IO VDDSHV CCD Camera interface - control (horizontal sync)

VDDSHV

VDDSHV

-

VDDSHV

VDDSHV

VDDSHV

VDDSHV

-

CCD Camera interface - data

CCD Camera interface - data

Ground

CCD Camera interface - data

CCD Camera interface - data

Ethernet MAC - RMII clock

Ethernet MAC - RMII data valid

Ground

VDDSHV Ethernet MAC - RMII data RX data

O VDDSHV Ethernet MAC - RMII data TX data

O VDDSHV

VDDSHV

Ethernet MAC - RMII data TX data

Ethernet MAC - RMII data TX enable

© PHYTEC America LLC 2012 11

Part I, Chapter 2: Pin Description L-761e_2

63B

64B

65B

66B

67B

68B

69B

70B

71B

72B

73B

55B

56B

57B

58B

59B

60B

61B

62B

47B

48B

49B

50B

51B

52B

53B

54B

HSUSB1_NXT

HSUSB1_DIR

GND

HSUSB1_DATA4

HSUSB1_DATA7

HSUSB1_DATA1

HSUSB1_DATA0

GND

MMC2_DAT6

MMC2_DAT5

MMC2_DAT3

MMC2_DAT2

GND xMMC2_CLK

I2C3_SCL

I2C3_SDA

UART1_RTS

GND

UART1_CTS

N/C

N/C

N/C

GND

MCBSP3_CLKX

MCBSP3_DR

MCBSP3_DX

MCBSP3_FSX

Table 2-2. Pin Descriptions, phyCORE-Connector X2, Row B (Continued)

Pin

44B

45B

46B

74B

75B

76B

77B

Signal

GND

ETK_D12

ETK_D11

GND

N/C

JTAG_EMU1 xJTAG_RTCK

I/O

Signal

Level

Description

Ground

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

I

I

O VDDSHV ARM Embedded Toolkit debug interface (other signal on HSUSB interface)

VDDSHV

VDDSHV

High Speed USB digital interface - control

High Speed USB digital interface - control

Ground

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

IO VDDSHV High Speed USB digital interface - data

Ground

IO VDDSHV MMC / SDIO 2 interface - data

IO VDDSHV MMC / SDIO 2 interface - data

IO VDDSHV MMC / SDIO 2 interface - data

IO VDDSHV MMC / SDIO 2 interface - data

Ground

O VDDSHV MMC / SDIO 2 interface - clock

O VDDSHV I²C bus 3 clock

IO VDDSHV I²C bus 3 data

O VDDSHV UART 1 ready to send

Ground

-

-

-

I VDDSHV UART 1 clear to send

No connect

-

-

No connect

No connect

Ground

IO VDDSHV Multichannel Buffered Serial Port 3 - TX clock

I VDDSHV Multichannel Buffered Serial Port 3 - data receive

IO VDDSHV Multichannel Buffered Serial Port 3 - data transmit

IO VDDSHV Multichannel Buffered Serial Port 3 - frame sync transmit

-

-

-

-

Ground

No connect

IO VDDSHV JTAG - test emulation

O VDDSHV JTAG - test clock - ARM clock emulation

© PHYTEC America LLC 2012 12

Part I, Chapter 2: Pin Description

Table 2-2. Pin Descriptions, phyCORE-Connector X2, Row B (Continued)

Pin

78B

79B

80B

Signal

JTAG_TCK

GND

JTAG_TMS

I/O

Signal

Level

Description

-

I VDDSHV

-

JTAG - test clock

Ground

IO VDDSHV JTAG - test mode select

L-761e_2

Table 2-3. Pin Descriptions, phyCORE-Connector X2, Row C

Pin Signal I/O

Signal

Level

Description

1C

2C

3C

4C

5C

6C

VIN

VIN

GND

VIN_3V3

VIN_3V3

VBAT

-

I

I

I

I

I

VIN

VIN

3.3V-5.0 power input

3.3V-5.0 power input

Ground

VIN_3V3 3.3V power input

VIN_3V3 3.3V power input

Power Battery connection to PMIC switch supplying power to the VRTC

7C

8C

9C

GND

/RESET

-

OD xSYS_NRESWARM IO

D

10C xSYS_CLKOUT1

11C SYS_BOOT6

O

I

-

VIN

VDDSHV

VDDSHV

VDDSHV

Ground

Active low reset out (open drain), normally connected to other open drain reset control inputs; this signal indicates all power supplies on the SOM are within regulation

Active low processor warm reset (input / open drain output)

System clock out 1

Boot configuration (sampled at reset)

12C GND

13C SYS_BOOT4

14C SYS_BOOT3

15C UART1_RX

-

I

I

I

-

VDDSHV

VDDSHV

VDDSHV

Ground

Boot configuration (sampled at reset)

Boot configuration (sampled at reset)

UART 1 receive data into SOM

16C UART1_TX

17C GND

18C ENET_TXP

19C ENET_TXN

20C ENET_RXP

21C ENET_RXN

22C GND

23C MMC1_DAT7

24C MMC1_DAT6

25C MMC1_DAT4

26C MMC1_DAT3

O VDDSHV UART 1 transmit data from SOM

-

O

O

I

I

-

Analog

Analog

Ground

Ethernet Differential (transmit positive)

Ethernet Differential (transmit negative)

Analog Ethernet Differential (receive positive)

Analog Ethernet Differential (receive negative)

Ground

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

© PHYTEC America LLC 2012 13

Part I, Chapter 2: Pin Description L-761e_2

Table 2-3. Pin Descriptions, phyCORE-Connector X2, Row C (Continued)

Pin Signal I/O

Signal

Level

Description

27C

28C

29C

GND xMCSPI1_CLK

MCSPI1_SOMI

30C MCSPI1_CS3

31C MCSPI1_CS2

32C GND

33C MCBSP2_DX

34C

35C

36C

37C

MCBSP2_DR

MCBSP2_CLKX

MCBSP1_FSR

GND

Ground

IO VDDSHV Multichannel Buffered Serial Port 1 - clock

IO VDDSHV Multichannel Serial Peripheral Interface 1 - Slave data out, Master data in

O

O

-

IO

VDDSHV

VDDSHV

-

VDDSHV

Multichannel Serial Peripheral Interface 1 - chip select 0

Multichannel Serial Peripheral Interface 1 - chip select 2

Ground

Multichannel Buffered Serial Port 2 - data transmit

I VDDSHV Multichannel Buffered Serial Port 2 - data receive

IO VDDSHV Multichannel Buffered Serial Port 2 - TX clock

IO VDDSHV Multichannel Buffered Serial Port 1 - frame sync receive

Ground

38C MCBSP1_CLKR

39C MCBSP_CLKS

IO

IO

40C UART3_TX_RS232 O

VDDSHV

VDDSHV

Multichannel Buffered Serial Port 1 - RX clock

Multichannel Buffered Serial Port - clock

UART 3 transmit at RS-232 levels

41C UART3_RX_RS232 I

RS232/

VDDSHV a

RS232/

VDDSHV

a

UART 3 receive at RS-232 levels

42C GND

43C UART2_CTS

44C UART2_RTS

45C UART2_TX

46C UART2_RX

47C GND

48C HECC1_TXD

49C HECC1_RXD

-

-

I

O

O

I

-

VDDSHV

VDDSHV

VDDSHV

VDDSHV

-

Ground

UART 2 clear to send

UART 2 ready to send

UART 2 transmit

UART 2 receive

Ground

O VDDSHV High-end CAN transmit

I VDDSHV High-end CAN receive

50C I2C2_SDA

51C I2C2_SCL

52C GND

53C I2C1_SDA

54C I2C1_SCL

55C DSS_VSYNC

56C DSS_HSYNC

57C GND

58C DSS_DATA21

59C DSS_DATA20

60C DSS_DATA18

61C DSS_DATA17

IO

O

-

IO

O

O

O

-

O

O

O

O

VDDSHV

VDDSHV

-

VDDSHV

VDDSHV

VDDSHV

VDDSHV

-

VDDSHV

VDDSHV

VDDSHV

VDDSHV

I²C bus 2 data

I²C bus 2 clock

Ground

I²C bus 1 data

I²C bus 1 clock

Display Sub-System - control

Display Sub-System - control

Ground

Display Sub-System - data

Display Sub-System - data

Display Sub-System - data

Display Sub-System - data

© PHYTEC America LLC 2012 14

Part I, Chapter 2: Pin Description L-761e_2

Table 2-3. Pin Descriptions, phyCORE-Connector X2, Row C (Continued)

Pin Signal I/O

Signal

Level

Description

62C GND

63C DSS_DATA13

64C DSS_DATA12

65C DSS_DATA10

66C DSS_DATA9

67C GND

68C DSS_DATA5

69C DSS_DATA4

70C DSS_DATA2

71C DSS_DATA1

72C GND

73C LCD_LVDS_Y3P

74C LCD_LVDS_Y3M

75C LCD_LVDS_Y2P

76C LCD_LVDS_Y2M

77C GND

78C TOUCH_X+

79C TOUCH_X-

80C TOUCH_Y+

Ground

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

Ground

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

-

O

O

O

O

-

I

I

I

-

Analog

Analog

Analog

Analog

-

Ground

LCD LVDS - data

LCD LVDS - data

LCD LVDS - data

LCD LVDS - data

Ground

Analog Touch panel X direction positive

Analog Touch panel X direction negative

Analog Touch panel Y direction positive a. The default level for these signals is consistent with the RS-232 standard, but can be optionally configured to VDDSHV voltage levels of 3.3V or 1.8V

Table 2-4. Pin Descriptions, phyCORE-Connector X2, Row D

Pin

5D

6D

7D

8D

1D

2D

3D

4D

VIN

VIN

GND

VCC_1V8

VCC_1V8

VDDSHV

VDDSHV

SYS_NIRQ

9D GND

10D /RESIN

11D

Signal

SYS_CLKREQ

I/O

Signal

Level

Description

-

I

I

I VIN

VIN

3.3V-5.0 power input

3.3V-5.0 power input

Ground

O VCC_1V8 1.8V output voltage

O VCC_1V8 1.8V output voltage

O VDDSHV IO voltage output

O VDDSHV IO voltage output

I VDDSHV Interrupt to AM3517 (dedicated interrupt)

I

-

VIN

Ground

System reset input; connect this pin to an open drain output and momentarily pull low to initiate a system reset. Do not connect this pin to a push-pull output or any other pull-up/pull-down circuitry.

Do not use

© PHYTEC America LLC 2012 15

Part I, Chapter 2: Pin Description L-761e_2

Table 2-4. Pin Descriptions, phyCORE-Connector X2, Row D (Continued)

Pin

12D

13D

14D

15D

16D

17D

18D

19D

20D

21D

22D

23D

24D

25D

26D

27D

28D

29D

30D

31D

32D

33D

34D

35D

36D

37D

38D

39D

40D

41D

42D

43D

Signal xSYS_CLKOUT2

SYS_BOOT5

GND

SYS_BOOT2

SYS_BOOT1

SYS_BOOT0

HDQ_SIO

GND

ENET_LINK

ENET_SPEED xMMC1_CLK

MMC1_CMD

GND

MMC1_DAT5

MMC1_DAT2

MMC1_DAT1

MMC1_DAT0

GND

MCSPI1_SIMO

MCSPI1_CS1

MCSPI1_CS0

MCBSP2_FSX

GND

MCBSP1_FSX

MCBSP1_DX

MCBSP1_DR

MCBSP1_CLKX

GND

/RS232_EN

UART3_RTS

UART3_CTS

USB0_DRVVBUS

I/O

Signal

Level

Description

-

I

O VDDSHV System clock out 1

I VDDSHV Boot configuration (sampled at reset)

-

VDDSHV

Ground

Boot configuration (sampled at reset)

I

I VDDSHV Boot configuration (sampled at reset)

VDDSHV Boot configuration (sampled at reset)

IO VDDSHV HDQ / single wire interface (Bi-directional control and data interface, open drain output)

-

O

-

3.3V

Ground

Ethernet Link status output; typically connected to an

LED on the carrier board to indicate Ethernet link status

O 3.3V

Ethernet activity status output; typically connected to an

LED on the Carrier Board to indicate Ethernet activity status

O VDDSHV MMC / SDIO 1 interface - clock

O VDDSHV MMC / SDIO 1 interface - command

Ground

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

IO VDDSHV MMC / SDIO 1 interface - data

Ground

IO VDDSHV Multichannel Serial Peripheral Interface 1 - Slave data in, Master data out

O VDDSHV Multichannel Serial Peripheral Interface 1 - chip select 1

IO VDDSHV Multichannel Serial Peripheral Interface 1 - chip select 0

IO VDDSHV Multichannel Buffered Serial Port 2 - frame sync transmit

Ground

IO VDDSHV Multichannel Buffered Serial Port 1 - frame sync transmit

IO VDDSHV Multichannel Buffered Serial Port 1 - data transmit

I VDDSHV Multichannel Buffered Serial Port 1 - data receive

IO VDDSHV Multichannel Buffered Serial Port 1 - TX clock

Ground

I 3.3V

Active low UART 3 transceiver disable; ground this signal to conserve power

O VDDSHV UART 3 ready to send

I VDDSHV UART 3 clear to send

O VDDSHV USB 0 VBUS enable to USB VBUS power supply

© PHYTEC America LLC 2012 16

Part I, Chapter 2: Pin Description

Table 2-4. Pin Descriptions, phyCORE-Connector X2, Row D (Continued)

Pin Signal

44D GND

45D USB0_ID

46D USB0_VBUS

47D USB0_DM

48D USB0_DP

49D GND

50D USB1_CPEN

51D USB1_DM

52D USB1_DP

53D xUSB1_VBUS

54D GND

55D xDSS_PCLK

56D DSS_ACBIAS

57D DSS_DATA23

58D DSS_DATA22

59D GND

60D DSS_DATA19

61D DSS_DATA16

62D DSS_DATA15

63D DSS_DATA14

64D GND

65D DSS_DATA11

66D DSS_DATA8

67D DSS_DATA7

68D DSS_DATA6

69D GND

70D DSS_DATA3

71D DSS_DATA0

72D LCD_LVDS_Y4P

73D LCD_LVDS_Y4M

74D GND

75D LCD_LVDS_Y1P

76D LCD_LVDS_Y1M

77D LCD_LVDS_CKLOU

TP

I/O

Signal

Level

Description

A

A

-

A

-

VBUS

Ground

USB 0 ID signal

VBUS USB 0 VBUS sense

Analog USB 0 communication channel minus

A

-

Analog USB 0 communication channel plus

Ground

O VDDSHV USB 1 VBUS enable

A Analog USB 1 communication channel minus

A

I

Analog USB 1 communication channel plus

VBUS USB 1 VBUS voltage sense

Ground

O VDDSHV Display Sub-System - clock

O VDDSHV Display Sub-System - AC Bias

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

Ground

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

Ground

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O

O

-

O

O VDDSHV Display Sub-System - data

Ground

O VDDSHV Display Sub-System - data

O VDDSHV Display Sub-System - data

O

O

Analog

Analog

-

Analog

Analog

Analog

LCD LVDS - data

LCD LVDS - data

Ground

LCD LVDS - data

LCD LVDS - data

LCD LVDS - clock plus

L-761e_2

© PHYTEC America LLC 2012 17

Part I, Chapter 2: Pin Description

Table 2-4. Pin Descriptions, phyCORE-Connector X2, Row D (Continued)

Pin Signal I/O

Signal

Level

Description

Analog LCD LVDS - clock minus 78D LCD_LVDS_CLKOU

TM

79D GND

80D TOUCH_Y-

O

-

I

-

Analog

Ground

Touch panel Y direction negative signal

L-761e_2

© PHYTEC America LLC 2012 18

Part I, Chapter 3: Jumpers L-761e_2

3 Jumpers

For configuration purposes the phyCORE-AM3517 has 23 solder jumpers, some of which have been installed prior to delivery.

Figure 3-2 and

Figure 3-1 indicate the location of the solder jumpers on the

board. There are 20 solder jumpers located on the top side of the module (opposite side of connectors) and 3 solder jumpers on the bottom side.

If manual jumper modification is required, pay special attention to the "TYPE" column in Table 3-1 ensuring

the use of the correct jumper type (0 Ohms, 10k Ohms, etc.). All jumpers are 0805 package with a 1/8W or better power rating.

Three and four position jumpers have pin 1 marked with a GREEN pad. Pin 1 can also be identified by the beveled edge on the silk-screen.

Fig. 3-1. Jumper Locations (Connector Side)

© PHYTEC America LLC 2012 19

Part I, Chapter 3: Jumpers L-761e_2

Fig. 3-2. Jumper Locations (Controller Side)

© PHYTEC America LLC 2012 20

Part I, Chapter 3: Jumpers L-761e_2

Fig. 3-3. Default Jumper Settings (Connector Side)

© PHYTEC America LLC 2012 21

Part I, Chapter 3: Jumpers L-761e_2

Fig. 3-4. Default Jumper Settings (Controller Side)

3.1 Jumper Settings

Table 3-1 below provides a functional summary of the solder jumpers, their default positions, and possible

alternative positions and functions.

A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

Table 3-1. Jumper Settings

J

J1

0R

J2

J3

J4

J5

Type Setting Description

0R

0R

0R

0R

1+2

2+3

1+2

2+3

1+2

2+3

1+2

2+3

1+2

2+3

Sets clock edge to negative edge on the LVDS encoder U3

Sets clock edge to positive edge on the LVDS encoder U3

Sets I²C lower address bit to 0; AD0 for U25 (touch controller)

Sets I²C lower address bit to 1; AD0 for U25 (touch controller) default address = 1001 001x

Sets I²C upper address bit to 0; AD1 for U25 (touch controller) default address = 1001 001x

Sets I²C upper address bit to 1; AD1 for U25 (touch controller)

Sets I²C address bit to 0; A2 for U13 (EEPROM) default address

= 1010 000x

Sets I²C address bit to 1; A2 for U13 (EEPROM)

Sets EEPROM to write protect off

Sets EEPROM to write protect on

Chapter

12

10

10

7.3

7.3

© PHYTEC America LLC 2012 22

Part I, Chapter 3: Jumpers L-761e_2

Table 3-1. Jumper Settings (Continued)

J Type

J6

0R

Setting Description

J7

J8

J9

10k

10k

10k

J10 0R

J11 0R

J12 0R

J13 0R

J14 0R

J15 0R

J16 0R

J17 0R

J18 0R

J19 0R

J20 0R

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

1+2

1+2

2+3

1+2

2+3

1+2 a

2+3

1+2

2+3

1+2

2+3

1+2

2+3

Open

Closed

Open

2+3

Open

Closed

1+2

2+3 b

Sets I²C address; A1 for U13 (EEPROM) default address = 1010

000x

Sets I²C address; A1 for U13 (EEPROM)

Sets I²C address; A0 for U13 (EEPROM) default address = 1010

000x

Sets I²C address lower; A0 for U13 (EEPROM)

Sets VDDSHV to 1.8V (1.8V SOM required)

Sets VDDSHV to 3.3V (Standard 3.3V SOM)

Reserved

Turns CLKOUT off

Sets USB1 PHY to slave

Sets USB1 PHY to host

Sets NAND Flash lock off

Sets NAND Flash lock on

No hardware reset is provided to U7 (USB1 PHY)

AM3517 GPIO_58 provides reset to U7 (USB1 PHY)

Disables processor access to /Shutdown (low power mode); frees signal for external use as GPIO

Provides SW controlled /Shutdown (low power mode) via GPIO

UART3 TX operates at RS232 specified transceiver levels

UART3 TX operates at TTL level signaling (U15 must be removed)

RS232 level bypass RX

Convert to TTL signal level (VDDSHV)

Disables processor visibility; frees signal for external use as GPIO

Interrupt from RTC to AM3517

Disables processor access to system reset

Provides SW controlled system reset via GPIO

Power to processor's integrated TV DAC supplied from U17

(external LDO regulator)

Power to processor's integrated TV DAC supplied from U2 (LDO regulator integrated into the PMIC)

Disables touch screen interrupt to processor; frees signal for external use as GPIO

Interrupt from touch screen controlled connect to AM3517

GPIO input

Selects the 26.000MHz crystal as the clock source to the processor

Selects the 26.000MHz oscillator as the clock source to the processor

Chapter

7.3

7.3

13

8.3

7.2

8.4

8.1

8.1

5

4.3

10

22

© PHYTEC America LLC 2012 23

Part I, Chapter 3: Jumpers L-761e_2

Table 3-1. Jumper Settings (Continued)

J Type

J21 0R

J22 0R

J23 0R

Setting Description

1+2

2+3

1+2

2+3

1+2

2+3

a

Defines PMIC rail 1 to be 1.2V

Reserved

Defines PMIC rail 3 to be 1.8V

Reserved

Setting determined by J8; Sets LVDS power scheme for use with SN65LVDS93 part

Setting determined by J8; Sets LVDS power scheme for use with

SN75LVDS83B part

Chapter

4.3

4.3

13

a. See

Chapter 13

for the requirements of this setting b. This jumper setting requires the addition of components not populated on the standard configuration of the phyCORE-

AM3517

© PHYTEC America LLC 2012 24

Part I, Chapter 4: Power L-761e_2

4 Power

The phyCORE-AM3517 operates by using three separate power supply input domains. For systems that do not require the RTC, VBAT is not required and should be tied to ground.

The following sections of this chapter discuss the primary power pins on the phyCORE-Connector X2 in detail.

4.1 Primary System Power (VIN & VIN_3V3)

The phyCORE-AM3517 operates from a primary voltage (VIN) supply with a nominal value of 3.3V - 5.0V

DC. On-board switching regulators generate the 1.8V, 1.2V, and adjustable IO voltage VDDSHV. However an additional power supply of 3.3V is required to power the board. These two power supplies then generate all the required voltages of the AM3517 MCU and other on-board components.

For proper operation the phyCORE-AM3517 must be supplied with a voltage source of 3.3V - 5.0V at the

VIN pins and 3.3V +/- 100mv on the VIN_3V3 pins. 3.0V - 5.0V DC must be supplied at the VBAT pin if the

RTC functionality is needed. See

Table 2-1 for VCC pin locations on phyCORE-Connector X2. See

Chapter 8.4

for current requirements.

It is possible to use a simplified power system to tie all supplies to a 3.3VDC source. VIN_3V3 powers several peripheral chips on the SOM, but if these features are not required, then VIN_3V3 can be connected to ground.

Connect all VIN and VIN_3V3 input pins to your power supply and at least the matching number of GND pins neighboring the + VIN and VIN_3V3 pins.

CAUTION:

As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry. For maximum EMI performance all GND pins should be connected to a solid ground plane.

4.2 Secondary Battery Power (VBAT)

For applications requiring a battery backed up RTC function, a battery supply with a nominal value of 3.0V

is required. The battery supply powers the RTC during a power off condition, allowing primary system power (VIN) and VCC_3V3 to be removed.

Applications not requiring a battery backed up RTC function can tie VBAT to ground.

4.3 PMIC Supplies (U2)

The PMIC located at U2 generates the 1.2V, 1.8V, VDDSHV (IO voltage), and two low power (1.8V and

3.3V) output supplies required by system components. This power is sourced from the primary VIN = 3.3V-

5.0V. Various jumpers have been provided as current measurement access points on these supply outputs.

Table 4-1

provides a summary of the jumpers and their operation. See

Chapter 4.5

for current measurement techniques with a precision shunt resistor.

© PHYTEC America LLC 2012 25

Part I, Chapter 4: Power L-761e_2

Table 4-1. Current Measurements

R Type Setting Description

R20 0R

R21 0R

R22 0R

R23 0R

R24 0R

R25 0R

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Reserved

VRTC to RTC IC (U22)

Reserved

1.8V power to AM3517 (LDO output, low noise)

Reserved

3.3V power to AM3517 (USB PHY)

Reserved

1.8V power for AM3517 (U1) and other peripheral (SDRAM, USB, touch,

NAND)

Reserved

VDDSHV, IO power for AM3517 (U1) and all other peripheral

Reserved

1.2V power to AM3517 (U1) and Ethernet PHY (U12)

4.4 RTC Supplies (U2)

The TPS65023 PMIC has incorporated a dual input, priority-switched power supply. This generates the

VCC_RTC power required by the RTC integrated circuit U2. The priority switch draws power from the

VIN_3V3 if it is available, otherwise the power is drawn from VBAT. Power to VBAT is supplied from a battery (Li-ION) connected to the VBAT pins on the phyCORE-Connector X2. The battery switch is responsible for connecting VIN_3V3 to the input of U2 during normal operating conditions (VIN_3V3 is present) and connecting VBAT to the input of U2 during a power off condition. The switchover between

VIN_3V3 and VBAT is automatic. An output jumper has been provided as a current measurement access point for VRTC.

Table 4-1

provides a summary of the jumpers and their operation. See

Chapter 4.5

for

current measurement techniques with a precision shunt resistor.

4.5 Selecting Shunt Resistors for Current Measurements

To make current measurements, the 0 Ohm resistors populating the regulator output jumpers should be replaced by precision shunt resistors, allowing the current draw to be calculated from the voltage measurement taken across the shunt resistor. When selecting a shunt resistor it is desirable to select a resistor large enough to give a voltage measurement that is not overtaken by noise. However, a larger shunt resistor means a larger voltage drop across the shunt, resulting in a smaller output voltage to powered devices. The output voltage after the shunt should be kept above the reset threshold. If the shunt resistor is too large, the voltage at the output could be below the supervisor reset threshold and force the system into reset. A good starting place is a 0.025 Ohm precision shunt in a 0805 package.

4.6 Voltage Supervisor (U2, U21)

The phyCORE-AM3517 is designed with two voltage supervision circuits which are intimately interconnected to provide a robust voltage supervision system. The purpose of this circuit is to ensure that power supplies to the various ICs on the SOM are provided correct voltages at all times.

The PMIC (U2) continuously monitors its integrated power supplies for any loss of regulation. If regulation is lost, the PMIC will pull the open drain output /INT of U2 low. See Texas Instrument TPS55023b datasheet (page 25) for details.

© PHYTEC America LLC 2012 26

Part I, Chapter 4: Power L-761e_2

The voltage supervision chip U21 has two functions:

1.

If the /INT signal is driven low then the voltage supervisor chip U21 will drive /RESET low

2.

If the input voltage to VIN is below 2.93V, the voltage supervisor will assert /RESET, driving it low

The reset signal /RESET (sys_nrespwron pin at the AM3517) is the main reset for the SOM. The possible causes of reset are:

• PMIC (TPS65023b) pin /RESPWRON: This output is an open drain, which can drive the /RESET signal low or hold it low at power up.

NOTE:

The PMIC will hold the signal low at power up for an additional second after the power supplies are stable. This additional second is provided by the system to ensure that the crystal oscillators are stable before the reset is released. In addition, the /HOT_RESET signal can also drive the /RESET signal low.

• The voltage supervisor U21: This has two possible causes as already mentioned in

Chapter 4.6

.

When these reset causes clear, the U21 voltage supervisor holds reset low for an additional

200ms. This difference in time can be used to narrow down the causes of a reset event should debugging in the general area be required.

• The Carrier Board can generate a reset from the /RESET signal connected to the phyCORE-

Connector X2. U21 senses this reset and adds a delay of 200ms.

• The /RESIN signal from the phyCORE-Connector X2 can cause the /RESET signal to be driven low as mentioned above. This signal is intended to be the standard method of issuing a reset to the SOM. U21 senses this reset and adds a delay of 200ms.

© PHYTEC America LLC 2012 27

Part I, Chapter 5: External RTC (U22) L-761e_2

5 External RTC (U22)

The external RTC (RTC-8564JE) is located at U22. It provides a time keeping source and an alarm output to the AM3517 and phyCORE-Connector X2 via the /RTC_INT signal (at GPMC_NCS5).

The RTC is interfaced to the processor via the I²C1 port. The default I²C address of the device is binary

1010 001x, where the 'x' bit is the read/write operation bit.

The RTC is automatically powered via the VBAT power input during a power down.

The open collector output signal /RTC_INT is provided to drive an external power wake circuit (not provided on the SOM) which would allow the system a signal to wake from sleep at some later time.

© PHYTEC America LLC 2012 28

Part I, Chapter 6: System Configuration and Booting L-761e_2

6 System Configuration and Booting

The phyCORE-AM3517 boots from an internal ROM which implements a boot order as described in section 24.2.3 - “Boot Configuration” of the AM3517 (TRM) Technical Reference Manual (page 2686; July

2010 revised edition). The phyCORE-AM3517 provides the SYS_BOOT[0-6] pins at phyCORE-Connector

X2 such that the users can hard configure the boot sequence. By default, the boot configuration is set to

0x01100 with SYS_BOOT[5] set low so the boot sequence is NAND - EMAC - USB - MMC1. This can be changed to any of the TRM described sequences by tying SYS_BOOT pins on the user’s application board or the PHYTEC carrier board.

The SYS_BOOT pins are sampled at system reset. Boot speed can be increased by ensuring that the normal boot device of a production system is configured for the first priority device. The ROM in the

AM3517 implements the boot sequence by accessing each peripheral at boot time and searching for a valid image. If a valid image exists, then the processor will boot to it. If an image is not valid, it will proceed to the next peripheral in the list.

0b000001

0b000011

0b000101

0b000110

0b000111

0b001000

0b001001

0b001010

0b001011

0b01100

0b001101

0b01110

0b001111

0b010001

0b010010

0b010011

0b010100

0b010101

0b010111

0b011000

0b011001

0b011010

0b011011

0b011100

Table 6-1. Peripheral Booting Configuration Pins after POR sys_boot [5:0]

Booting Sequence:

Peripheral Booting Preferred Order

Third

USB

USB

XIP

XDOC

NAND

MMC2

MMC1

XIP

XDOC

NAND

SPI

XIP

XDOC

NAND

XIP

XDOC

NAND

MMC2

MMC1

First

NAND

MMC2

MMC2

MMC1

XIP

XDOC

MMC2

EMAC

EMAC

EMAC

USB

USB

USB

USB

USB

Second

EMAC

EMAC

USB

USB

EMAC

EMAC

EMAC

UART

UART

UART

UART

UART

USB

USB

USB

UART

USB

USB

USB

USB

USB

USB

UART

UART

UART

UART

UART

Fourth

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

© PHYTEC America LLC 2012 29

Part I, Chapter 6: System Configuration and Booting

0b100001

0b100011

0b100101

0b100110

0b100111

0b101000

0b101001

0b101010

0b101011

0b11100

0b101101

0b111110

0b101111

0b110001

0b110010

0b110011

0b110100

0b110101

0b110111

0b111000

0b111001

0b111010

0b111011

0b111100

0b111111

Table 6-1. Peripheral Booting Configuration Pins after POR sys_boot [5:0]

0b011111

Booting Sequence:

Peripheral Booting Preferred Order

USB UART3

EMAC

EMAC

EMAC

EMAC

USB

USB

USB

USB

Fast XIP booting wait monitoring

EMAC

EMAC

USB

USB

EMAC

USB

USB

UART

UART

UART

UART

UART

USB

USB

USB

UART

Fast XIP booting wait monitoring

USB

USB

MMC2

MMC1

USB

XDOC

USB

USB

USB

USB

UART

UART

UART

UART

UART

XIP

XDOC

NAND

MMC2

MMC1

XIP

XDOC

NAND

SPI

USB

NAND

MMC1

XIP

MMC2

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

UART3

Table 6-2. Booting Configuration Pins after a Warm Reset sys_boot[5:0]

0b000001

0b000011

0b000101

0b000110

Booting Sequence:

Memory Booting Preferred Order

Second First

NAND

MMC2

MMC2

MMC1

© PHYTEC America LLC 2012

MMC2

XIP

XDOC

NAND

XIP

XDOC

NAND

MMC2

L-761e_2

30

Part I, Chapter 6: System Configuration and Booting

0b011001

0b011010

0b011011

0b011100

0b011111

0b100001

0b100011

0b100101

0b100110

0b100111

0b101000

0b101001

0b101010

0b101011

0b101100

0b101101

0b000111

0b001000

0b001001

0b001010

0b001011

0b001100

0b001101

0b001110

0b001111

0b010001

0b010010

0b010011

0b010100

0b010101

0b010111

0b011000

0b101110

0b101111

0b110001

0b110010

0b110011

0b110100

Table 6-2. Booting Configuration Pins after a Warm Reset sys_boot[5:0]

Booting Sequence:

Memory Booting Preferred Order

NAND

MMC2

MMC1

XIP

XIPwait

NAND

MMC2

MMC1

XIP

XIPwait

MMC2

XIP

XIPwait

NAND

XIP

XIPwait

MMC1

XIP

XIPwait

MMC2

XIP

XIPwait

NAND

USB

XIP

XIPwait

NAND

SPI

ROM code fast XIP booting

NAND

MMC2

MMC2

XIPwait

NAND

MMC2

MMC1

XIP

XIPwait

DOC

DOC

DOC

DOC

DOC

DOC

DOC

XIP

DOC

DOC

© PHYTEC America LLC 2012

L-761e_2

31

Part I, Chapter 6: System Configuration and Booting

Table 6-2. Booting Configuration Pins after a Warm Reset sys_boot[5:0]

0b110101

0b110111

0b111000

0b111001

0b111010

0b111011

0b111100

0b111111

Booting Sequence:

Memory Booting Preferred Order

NAND

MMC2

MMC1

XIP

XIPwait

NAND

SPI

ROM code fast XIP booting

DOC

L-761e_2

6.1 Boot Process

The AM3517's ROM code looks for X-loader as the first image to continue the boot process. X-loader is an open-source program, maintained by Texas Instruments. X-loader configures the SDRAM, loads the next boot image, and then runs it. Unlike boot ROM, X-loader does not have a complex algorithm to search for the next image and must be hard-coded in the software. In order to execute the next boot loader (U-Boot or

E-Boot), X-loader uses the SYS_BOOT settings to determine which image to load. If desired, increasingly complex boot sequences are possible with modifications to the X-loader source code. However, one must carefully consider the TRM boot sequence, boot time, and reliability before making such changes.

© PHYTEC America LLC 2012 32

Part I, Chapter 7: System Memory L-761e_2

7 System Memory

The phyCORE-AM3517 provides three types of on-board memory:

1.

2.

3.

4.

DDR2 SDRAM (U8/U9):

NAND Flash (U16):

EEPROM (U13): from 256MB to 512MB (2x 128MB or 2x 256MB ICs) from 128MB to 512MB from 256KB

The following sections of this chapter detail each memory type used on the phyCORE-AM3517 SOM.

7.1 SDRAM (U8, U9)

The phyCORE-AM3517 is populated with either 256MB or 512MB of 333MHz DDR2 SDRAM configured for 32-bit access using two 16-bit wide RAM chips at U8 and U9.

The AM3517 is capable of addressing 8 RAM banks located at memory address 0x8000 0000. Refer to

Table 7-1 for permissible SDRAM memory access ranges.

Table 7-1. Valid SDRAM Memory Address Ranges

SDRAM Size Lower Memory Address Upper Memory Address

256MB

512MB

0x8000 0000

0x8000 0000

0x8FFF FFFF

0x9FFF FFFF

7.2 NAND Flash (U16)

The NAND memory is comprised of a single 128MB, 256MB or 512MB chip located at U16 and is interfaced via the AM3517 GPMC memory bus.

Write protection control of the NAND device is configurable via jumper J11.

Table 7-2

lists the various

NAND Flash write protection control options, including the default setting on the standard version of the phyCORE-AM3517 SOM included in the Rapid Development Kits (RDK). See below for an overview from the Micron MT29F2G16 datasheet for "Block Lock" and the operation of the LOCK. Refer to this datasheet for information on unlock commands if the LOCK jumper is put in place to protect the NAND flash.

Additionally the "LOCK TIGHT" feature of the NAND flash may be useful in some applications.

The block lock feature protects either the entire device or ranges of blocks from being programmed and erased. Using the block lock feature is preferable to using WP# to prevent PROGRAM and ERASE operations.

Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if LOCK is LOW, all

BLOCK LOCK commands are disabled. However if LOCK is HIGH at power-on, the BLOCK LOCK commands are enabled. In addition to this, all the blocks on the device are protected or locked from

PROGRAM and ERASE operations, even if WP# is HIGH. Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device may be unlocked.

PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and

ERASE operations.

“Blocks that are locked can be protected further, or locked tight. When locked tight, the device's blocks can no longer be locked or unlocked until the device is power cycled."

1

© PHYTEC America LLC 2012 33

Part I, Chapter 7: System Memory L-761e_2

Refer to Table 7-2

for J11, LOCK pin jumper settings.

Table 7-2. LOCK Pin Jumper Settings

J Type

J11 0R

Setting Description

1+2

2+3

At power on, LOCK is low and all "BLOCK LOCK " commands are disabled.

"BLOCK LOCK" commands are enabled and all blocks are locked at power up. Block unlock commands are required to unlock blocks prior to writing.

7.3 EEPROM (U13)

The phyCORE-AM3517 is populated with one 256KB EEPROM device. The EEPROM is not preprogrammed, so it can be used to store manufacturing information, Ethernet MAC ID, and/or other data.

The EEPROM is an I²C device, connected to the I²C1 bus.

7.4 Memory Map

The phyCORE-AM3517 memory map is summarized in

Table 7-3

below. Make note of the memory addresses assigned to functions on the phyCORE-AM3517. A detailed memory map for the AM3517 can be found in the AM3517 TRM in section 2.2.

Table 7-3. phyCORE-AM3517 Memory Map

Start

Address

0x0000 0000

0x4000 0000

0x4800 0000

0x5000 0000

0x5400 0000

0x5800 0000

0x5C00 0000

0x6000 0000

0x6800 0000

0x6E00 0000

0x6F00 0000

0x7000 0000

0x8000 0000

0xA000 0000

0xE000 0000

End Address

0x3FFF FFFF

0x47FF FFFF

0x4FFF FFFF

0x53FF FFFF

0x57FF FFFF

0x5BFF FFFF

0x5FFF FFFF

0x67FF FFFF

0x6DFF FFFF

0x6EFF FFFF

0x6FFF FFFF

0x7FFF FFFF

0x9FFF FFFF

0xDFFF FFFF

0xFFFF FFFF

Function

General Purpose Memory Controller (GPMC 8/16 bit)

AM3517 internal memory

AM3517 L4 internal interconnect

AM3517 Graphics Accelerator

AM3517 L4 Emulation

Reserved

IPSS

Reserved

AM3517 L3 internal interconnect

GPMC configuration registers

Reserved

EMIF4-SMS virtual address space 0

DDR2 SDRAM (512MB)

Reserved

EMIF4-SMS virtual address space 1

1. Micron MT29F2G16 Datasheet. Rev. D; Sept. 2009, pg.63

© PHYTEC America LLC 2012 34

Part I, Chapter 8: Serial Interfaces L-761e_2

8 Serial Interfaces

The phyCORE-AM3517 provides on-board transceivers for four serial interfaces:

1.

A high speed RS-232 transceiver supporting 920kbps on UART3

2.

A high speed USB OTG transceiver internal to the AM3517 (USB0)

3.

An external high speed USB Host port transceiver supporting AM3517 host port 1

4.

An Auto-MDIX enabled 10/100 Ethernet PHY supporting the AM3517 Ethernet MAC

The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers.

8.1 RS-232 Transceiver (U15)

A TRSF3221E RS-232 transceiver supporting typical data rates of 115.2kbps populates the phyCORE-

AM3517 at U15. This device provides RS-232 level translation for UART3 of the AM3517.

Table 8-1

details

the TTL and RS-232 level signals for UART3. See the pin description listing in Chapter 2

,

Table 2-1

for the signal locations on the phyCORE-Connector X2.

For custom configurations which do not require RS-232 level translation, the RS-232 transceiver (U15) can be removed and 0 Ohm resistors J14 and J15 can be populated. In this configuration there is a direct short between the TTL level signal name and RS-232 level signal name, leaving the RS-232 level signal names operating at TTL levels.

Table 8-1. UART3 TTL and RS-232 Level Signals

UART

RS-232 Level

Signal name

UART3_TX_RS232

UART3_RX_RS232

UART3

TTL Level Signal

Name

UART3_TX

UART3_RX

UART3_CTS

UART3_RTS

8.2 Ethernet PHY (U12)

The phyCORE-AM3517 comes populated with an SMSC LAN8720I Ethernet PHY at U12 supporting 10/

100 Mbps Ethernet connectivity. The PHY uses an RMII interface to the Ethernet MAC integrated on the

AM3517.

The LAN8720I supports the HP Auto-MDIX function eliminating the need for consideration of a direct connect LAN cable, or a cross-over patch cable. The LAN8720I detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. Interfacing the

Ethernet port involves incorporating RJ45 and appropriate magnetic devices into your design. Please consult the phyCORE-AM3517 Carrier Board schematics as a reference. Impedance matching and careful layout practices are important for signal integrity, particularly where long cable lengths need to be supported in the target application.

8.3 USB OTG (U1)

The phyCORE AM3517 comes with a USB On-The-Go transceiver internal to AM3517 that supports both full speed and low speed data rates. This USB port can be configured as a dedicated host, dedicated peripheral, or OTG interface.

© PHYTEC America LLC 2012 35

Part I, Chapter 8: Serial Interfaces L-761e_2

When designing the USB interface, pay special attention to current requirements when operating as an embedded host. By default an embedded USB OTG host only needs to supply 8mA of current to a connecting peripheral. However, the AM3517 is not capable of supplying this current to a connecting peripheral, so a device on the carrier board is required to satisfy this requirement. To meet this higher current requirement the USB0_DRVVBUS pin can be used. This signal can drive an external power control switch capable of sourcing additional power. In this configuration the USB0_DRVVBUS signal is connected to the power supply enable input pin and the USB_VBUS signal is sourced from a 5V power supply output.

See the phyCORE-AM3517 Carrier Board schematics for reference circuitry that makes use of the

USB0_DRVVBUS pin to provide additional host current.

Termination for the USB0 signals are internal to the AM3517. A USB_VBUS capacitor of 4.7µF has been placed on the phyCORE-AM3517 Carrier Board. It should be noted that the maximum VBUS capacitance a USB OTG device can add to the bus is 6.5µF. Therefore, adding anything more than 1.7µF external to the phyCORE-AM3517 on USB_VBUS is not recommended when operating in OTG mode. This may be increased to the typical 120uF minimum required by the USB specifications for dedicated host devices if

OTG mode is not required.

In addition to optional power control circuitry via the USB_DRVVBUS signal, an external USB connector is all that is needed to interface the phyCORE-AM3517 USB functionality.

Table 8-2 details applicable

connectors for various end-application operating modes. The applicable interface signals (USB_DM/

USB_DP/USB_VBUS/USB_ID/USB_DRVVBUS) can be found in the phyCORE-Connector pin-out

Table

2-1

located in Chapter 2

.

Table 8-2. Applicable USB Operating Mode Connectors

Operating Mode Applicable Connectors

Host

Device/Peripheral

OTG

Standard-A

Mini-A

Standard-B

Mini-B

Mini-AB

8.4 USB1 Host (U1, U7)

In addition to the USB OTG signals, the phyCORE-AM3517 also provides a USB 3320 Host transceiver connected to the AM3517 Host controller. This USB interface supports high, full, and low speed data rates.

When designing the USB host interface, pay special attention to the necessary current requirements as an embedded host. The AM3517 is not capable of supplying this current to a connecting peripheral, so a device is required on the carrier board to satisfy this requirement. To meet this higher current requirement the USB1_CPEN pin can be used. This signal can drive an external power control switch capable of sourcing additional power. In this configuration, the USB1_CPEN signal is connected to the power supply enable input pin and the USB_VBUS signal is sourced from a 5V power supply output. See the phyCORE-

AM3517 Carrier Board schematics for reference circuitry that makes use of the USB1_CPEN pin to provide additional host current.

Termination for the USB1 signals are internal to the USB3320. A USB_VBUS capacitor of 150µF has been placed on the phyCORE-AM3517 Carrier Board. In addition to optional power control circuitry via the

USB1_CPEN signal, an external USB connector is all that is needed to interface the phyCORE-AM3517

USB functionality.

Table 8-2 details applicable connectors for various end application operating modes.

The applicable interface signals (USB_DM/USB_DP/USB_VBUS/USB_ID/USB_DRVVBUS) can be found in the phyCORE-Connector pin-out

Table 2-1

located in

Chapter 2 .

© PHYTEC America LLC 2012 36

Part I, Chapter 9: Debug Interface (X1) L-761e_2

9 Debug Interface (X1)

The phyCORE-AM3517 is equipped with a JTAG interface for downloading program code into the internal

RAM controller or for debugging programs currently executing. In addition to being made available at the phyCORE-Connector X2, the JTAG interface extends out to a 2.54 mm pitch pin header at X1 on the edge of the module.

Figure 9-1 shows the position of the debug interface (JTAG connector X1) on the

phyCORE-AM3517. Even numbered pins are on the top of the module, moving from pin 2 on the right to pin 20 on the left. Odd number pins are on the bottom, starting from (as viewed from the top) 1 on the right to 19 on the left.

Fig. 9-1. JTAG Interface X1 (Controller Side)

The JTAG edge card connector X1 provides an easy means of debugging the phyCORE-AM3517 in your target system via an external JTAG probe, such as RealView ICE.

NOTE:

The JTAG connector X1 only populates phyCORE-AM3517 modules with order code PCM-048-xxxxxD.

This version of the phyCORE module must be special ordered. The JTAG connector X1 is not populated on phyCORE modules included in the Rapid Development Kits. All JTAG signals are accessible from the

Carrier Board and at the phyCORE-Connector X2 on the SOM. Integration of a standard (2.54 mm pitch) pin header connector in the user target circuitry is recommended to allow easy program updates via the

JTAG interface. See Chapter 2 for details on the JTAG signal pin assignment.

© PHYTEC America LLC 2012 37

Part I, Chapter 10: Touch Screen Controller (U25) L-761e_2

10 Touch Screen Controller (U25)

The phyCORE-AM3517 SOM provides an on-board touch controller (TSC2004). The touch controller interfaces with a resistive touch panel typically integrated into an LCD. The touch screen controller communicates with the AM3517 over I²C1 at address 1001001x (by default). The touch sense signals (X+,

X-, Y+, Y) are routed to the phyCORE-Connector X2 for connection to an external resistive touch panel.

Care should be taken to route the touch panel sense signals to achieve low noise.

© PHYTEC America LLC 2012 38

Part I, Chapter 11: General Purpose Memory Controller (U2) L-761e_2

11 General Purpose Memory Controller (U2)

The phyCORE-AM3517 provides a configurable voltage GPMC interface for the connection of external memory mapped peripherals. Data bus direction is controlled by the processor’s output enable signal /OE.

Table 11-1 provides a detailed list of the memory bus signals available at the phyCORE-Connector X2.

Refer to the phyCORE-Connector pin-out Table 2-1

for signal locations.

Table 11-1. GPMC Signal Mapping

General Purpose Signal

Address line A0 - A10

Data lines D0 - D15

Chip Selects 1 - 7

External wait signal to GPMC interface

Upper byte enable / command latch enable

Lower byte enable

Write protect

Output enable (to slaves)

Clock

Write enable

Address valid / Address latch enable phyCORE Signal Name

GPMC_A0 - A10

GPMC_D0 - 15

GPMC_NCS1 - 7

GPMC_WAIT0 - 3

GPMC_NBE0_CLE

GPMC_NBE1

GPMC_NWP

GPMC_NOE xGPMC_CLK xGPMC_NWE xGPMC_NADV_ALE

See section 9.1.6.2.2 of the AM3517 TRM for GPMC interface and section 9.1.7.2.1 for GPMC interface configuration/register descriptions. The GPMC_NCS1-7 signals are programmable throughout the memory space 0x0000 0000 to 0x3FFF FFFF as noted in the memory maps with few limitations. This flexible controller should provide an easily configured interface to NOR Flash, FPGAs, and many other general purpose bus interface required ICs.

© PHYTEC America LLC 2012 39

Part I, Chapter 12: LCD LVDS Transmitter L-761e_2

12 LCD LVDS Transmitter

The phyCORE-AM3517 provides an LVDS transmitter for use in conjunction with a compatible LVDS LCD panel. The LVDS transmitter is connected to the processor’s display subsystem interface (DSS); providing

24-bits of color data in addition to control signals.

There are several advantages of the LVDS LCD interface over its TTL counterpart. Some of those advantages include:

• The differential nature of the signals decreases susceptibility to EMI

• The differential nature of the signals decreases the magnitude of radiated emissions

• Differential signals allow longer trace, and/or cable lengths

• I/O signal count is lower due to time division multiplexing of the signals at a high bit rate (28 signals are reduced to 10 signals)

It should be noted that not all LVDS transmitters and LVDS LCD panels are compatible. Ensure that the time division multiplexing (TDM) used by the LVDS transmitter on the phyCORE-AM3517 is compatible with the TDM scheme in the LVDS receiver used in the LCD panel of interest. To elaborate on this note, a basic theory of operation in conjunction with the phyCORE-AM3517 LVDS circuit is presented below.

The LVDS transmitter operates by serializing the parallel data from the display subsystem interface and transmitting this serialized data at a high frequency over a set of 5 differential pairs (one pair dedicated to differential clock). This technique is a form of time division multiplexing (TDM) where a large set of several control and color data signals are multiplexed in time over a smaller set of differential signals.

Figure 12-1

1 below shows the multiplexing scheme used by the LVDS transmitters used on the phyCORE-AM3517

(SN65LVDS93 and SN75LVDS83B depending on IO voltage configuration).

Fig. 12-1. LVDS Multiplexing Scheme

1

To illustrate an example, take the DSS_DATA23 signal from the processor. This signal is normally bit 7 of the red color channel when operating in 24-bit mode. DSS_DATA23 is connected to the LVDS transmitter

D6 input pin. From

Figure 12-1 above, that means the DSS_DATA23 signal shows up as the 6th bit in

differential data channel Y0 (signals LCD_LVDS_Y1P & LCD_LVDS_Y1M on the phyCORE-AM3517) in time. Thus, when determining if a particular LCD LVDS receiver is compatible with the phyCORE-AM3517, the red bit 7 of the LVDS receiver should be expected on differential channel 0 at bit position 6. This type of analysis should be done for all color and control bits connected to the LVDS transmitter on the phyCORE-

AM3517 to ensure compatibility.

1.

Texas Instruments SN64LVDS93 datasheet; figure 1

© PHYTEC America LLC 2012 40

Part I, Chapter 12: LCD LVDS Transmitter L-761e_2

12.1 LVDS and SOM I/O Voltage (J23)

The phyCORE-AM3517 was designed to support a configurable bus operating voltage of 1.8V or 3.3V (see chapter

Chapter 13

for details). To support this dual mode configuration, different LVDS transmitters must be used at different bus voltage levels. When running at 3.3V (the standard configuration) the

SN65LVDS93 is used. When running at 1.8V the SN75LVDS83B is used. Although the SN75LVDS83B can operate at both 1.8V and 3.3V while the SN65LVDS93 cannot (3.3V only), the SN75LVDS83B is limited to an operating temperature of -10C to +70C, while the SN65LVDS93 is capable of -40C to +85C. Thus the following becomes true:

• Designs requiring LVDS and industrial temperature (-40C to +85C) ratings must operate at 3.3V and use the SN65LVDS93

• Designs requiring LVDS and 1.8V operating voltage will not be rated for industrial temperature range and must use the SN75LVDS83B

To accommodate these two different LVDS transmitter parts with different power requirements, jumper J23 is provided. When the SN65LVDS93 is populating the board, jumper J23 should be set to 1+2. When the

SN75LVDS83B is populating the board, jumper J23 should be set to 2+3. If the SOM is being configured for 1.8V operation and one is attempting to replace the SN65LVDS93 with the SN75LVDS83B on the standard kit version of the SOM by hand, make sure all of the modifications listed in

Chapter 13 are

implemented to avoid damaging the SOM or Carrier Board before powering up the system.

CAUTION:

The SN75LVDS83B has its own unique data sheet and should not be confused with the similar part #

SN75LVDS83

© PHYTEC America LLC 2012 41

Part I, Chapter 13: AM3517 IO and GPMC Bus Voltage L-761e_2

13 AM3517 IO and GPMC Bus Voltage

The buffered memory bus operating voltage is configurable at 1.8V or 3.3V via jumper J8 to allow connection to a variety of devices. By default this jumper is set to the 2+3 position, selecting 3.3V. To interface 1.8V low power devices to the external memory bus, J8 should be set to the 1+2 position.

Switching to 1.8V IO will reduce the power consumption of the embedded system.

WARNING:

Normal operating voltage for the Carrier Board and SOM is 3.3V.

In 3.3V IO mode the following is required:

• Carrier Board X21 set to 3+5 and 4+6

• Carrier Board JP13 set to OPEN

• SOM J8 set to 2+3

• SOM U3 SN65LVDS93 optionally installed

• SOM J23 set to 1+2

In 1.8V IO mode the following is required:

• Carrier Board X21 set to 1+3 and 2+4

• Carrier Board JP13 set to CLOSED

• SOM J8 set to 1+2

• SOM U3 SN75LVDS83B optionally installed

• SOM J23 set to 2+3

Failure to follow these guidelines will result in damage to the SOM and Carrier Board circuitry.

© PHYTEC America LLC 2012 42

Part I, Chapter 14: Technical Specifications L-761e_2

14 Technical Specifications

The physical dimensions of the phyCORE-AM3517 are represented in

Figure 14-1

. The module's profile is approximately 6.7mm thick. The maximum component height is approximately 4.5mm on the bottom

(connector) side of the PCB and approximately 2.58mm on the top (microcontroller) side. The board itself is approximately 1.55mm thick. The distance from the Carrier board surface to the highest component on the top side of the board is approximately 8mm.

Fig. 14-1. phyCORE-AM3517 Physical Dimensions

Table 14-1. Technical Specifications

Dimensions 72 x 58 mm

Weight TBD

Storage Temperature -40C to +90C

Operating Temperature -40C to +85C

Humidity 95% r.F. not condensed

Power Consumption

~1.25W typical

Operating Conditions:

VIN = 3.3V

256MB SDRAM @ 333MHz, 256MB NAND, Linux booted

© PHYTEC America LLC 2012 43

Part I, Chapter 14: Technical Specifications L-761e_2

Table 14-2. Static Operating Characteristics

a

I

I

Symbol

VIN

VIN_3V3

VBAT

VIN

VIN_3V3

Description Conditions

Primary SOM input voltage

Peripheral device power

(USB, Enet, RTC, RS-232)

Battery backup for RTC

Primary SOM operating current

Peripheral device current

(USB, Enet, RTC, RS-232)

Core @ 600MHz, 256MB

SDRAM @ 333MHz,

256MB NAND, Linux

Booted, Ethernet Linked

Core @ 600MHz, 256MB

SDRAM @ 333MHz,

256MB NAND, Linux

Booted, Ethernet Linked

I

VBAT a. Tamb = -40C to +85C unless otherwise specified.

Min Type Max Unit

3.0

3.3

5.0

VDC

3.0

2.73

3.3

3.3

338.2

72.8

TBD

3.6

3.75

mA mA mA

These specifications describe the standard configuration of the phyCORE-AM3517 as of the printing of this manual.

© PHYTEC America LLC 2012 44

Part I, Chapter 15: Hints for Handling the phyCORE-AM3517 L-761e_2

15 Hints for Handling the phyCORE-AM3517

Removal of various components, such as the microcontroller and the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while de-soldering.

Overheating the board can cause the solder pads to loosen, rendering the module inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds.

© PHYTEC America LLC 2012 45

PCM-961/phyCORE-AM3517 Carrier Board L-761e_2

Part II: PCM-961/phyCORE-AM3517 Carrier

Board

Part 2 of this three part manual provides detailed information on the phyCORE-AM3517 Carrier Board and its usage with the phyCORE-AM3517 SOM.

The information in the following chapters is applicable to the 1336.1 PCB revision of the phyCORE-

AM3517 Carrier Board. All board images in this section of the manual refer to the 1336.1 PCB.

The Carrier Board can also serves as a reference design for development of custom target hardware in which the phyCORE SOM is deployed. Carrier Board schematics with BoM are available under a Non

Disclosure Agreement (NDA). Re-use of Carrier Board circuitry likewise enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

© PHYTEC America LLC 2012 46

Part II, Chapter 16: Introduction

16 Introduction

L-761e_2

Fig. 16-1. phyCORE-AM3517 Carrier Board

PHYTEC Carrier Boards are fully equipped with all mechanical and electrical components necessary for a speedy, secure start-up and subsequent communication to, and programming of, the applicable PHYTEC

System on Module (SOM). Carrier Boards are designed for evaluation, testing, and prototyping of

PHYTEC SOMs in laboratory environments prior to their use in customer designed applications.

The phyCORE-AM3517 Carrier Board provides a flexible development platform enabling quick and easy start-up and subsequent programming of the phyCORE-AM3517 System on Module. The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation.

© PHYTEC America LLC 2012 47

Part II, Chapter 17: Overview of Peripherals

17 Overview of Peripherals

L-761e_2

Fig. 17-1. Overview of Peripherals

The phyCORE-AM3517 Carrier Board is depicted in

Figure 17-1 and includes the following components

and peripherals listed in

Table 17-1

,

Table 17-2

, and

Table 17-3 . For a more detailed description of each

peripheral, refer to the appropriate chapter listed in the applicable table.

Table 17-1. Connectors and Headers

Ref. Des. Description

X9

X10

X11

X12

X13

X14

X5

X6

X7

X8

X1

X2

X3

X4

USB OTG Connector (AM3517 - USB1)

USB Host (AM3517 - USB0)

MMC1 easy access header

Camera easy access header (AM3517 - CCDC)

MMC / SDIO connector (AM3517-MMC1)

CAN connector

WIFI connector (AM3517 - MCBSP1 / UART1 / MMC2)

DVI video connector

Wall adapter input power jack to supply main board power

UART easy access connector (AM3517 - UART2 / UART3)

CPLD JTAG (video bit map programmable logic)

LCD LVDS connector

JTAG interface to AM3517

GPIO expansion connectors

Chapter

20

27

21

25

21

26

28

32

30

25

24

24

28

32

© PHYTEC America LLC 2012 48

Part II, Chapter 17: Overview of Peripherals

Table 17-1. Connectors and Headers (Continued)

Ref. Des. Description

X25

X26

X27

X28

X29

X30

P1

X15

X16

X17

X18

X19

X20

X23

X24 phyCORE-AM3517 connectors to SOM

TV Out

Ethernet connector (POE capable)

PHYTEC Camera interface (AM3517 - CCDC)

PHYTEC Camera easy access header (AM3517 - CCDC)

LVDS LCD power and backlight control connector

Loudspeaker connector

MIC in connector

Headphones connector

Line out

Ground test point

Ground test point

UART2 RS-232 connector

LCD TTL connector

UART3 RS-232 connector

Table 17-2. Description of the Buttons and Switches

Ref. Des. Description

S5

S6

S7

S8

S1

S2

S3

S4

S9

S10

LCD video color bit depth control

LCD orientation control

System Reset button

User button 4 (labeled BTN4)

User button 3 (labeled BTN3)

User button 2 (labeled BTN2)

User button 1 (labeled BTN1)

SYS_BOOT 4 & 5 switches

SYS_BOOT 3 & 2 switches

SYS_BOOT 1 & 0 switches

Table 17-3. Description of LEDs

Ref. Des. Description

D25

D26

D27

D28

PoE power available

Power connector power available

User controlled LED 2

Ethernet Link LED

© PHYTEC America LLC 2012

L-761e_2

Chapter

22

22

N/A

N/A

27

25

27

32

25

22

22

19

31

20

32

Chapter

33

33

33

35

25

25

36

33

35

35

Chapter

20

20

34

34

49

Part II, Chapter 17: Overview of Peripherals L-761e_2

Table 17-3. Description of LEDs (Continued)

Ref. Des. Description

D29

D30

D31

User controlled LED 1

User controlled LED 3

Ethernet Speed LED

Chapter

34

34

34

Please note that all module connections are not to exceed their expressed maximum voltage or current.

Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

© PHYTEC America LLC 2012 50

Part II, Chapter 18: Jumpers

18 Jumpers

L-761e_2

Fig. 18-1. Jumper Locations and Default Settings

The phyCORE-AM3517 Carrier Board comes pre-configured with 39 removable jumpers (JP). The jumpers allow the user flexibility in rerouting a limited number of signals for development constraint purposes.

Table 18-1

below lists the 39 removable jumpers, their default positions, and their functions in each position.

Figure 18-2

depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board. Note that pin 1 is always marked by a cut corner on the silk-screen on the PCB and with a green indicator in the jumper location diagrams that follow.

Figure 18-1

provides a detailed view of the phyCORE-AM3517 Carrier Board jumpers and their default settings.

Fig. 18-2. Typical Jumper

Table 18-1 provides a comprehensive list of all Carrier Board jumpers. The table only provides a concise

summary of jumper descriptions. For a detailed description of each jumper see the applicable chapter listing in the right hand column of the table.

The following conventions were used in the J/JP column of the jumper table:

• J = solder jumper

• JP = removable jumper

© PHYTEC America LLC 2012 51

Part II, Chapter 18: Jumpers L-761e_2

Table 18-1. Jumper Settings

J/JP Setting Description

X22

X21

JP1

JP2

JP3

JP4

JP5

JP6

JP7

JP8

JP9

JP10

JP11

JP12

JP13

JP14

JP15

1+3, 2+4

3+5, 4+6

1+3, 2+4

3+5, 4+6

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Selects the X9 power connector for main power input (3.3-5.0V)

Selects the PoE power supply

Selects the SOM IO voltage to be 1.8V (this requires a SOM with 1.8V IO configuration)

Selects the SOM IO voltage to be 3.3V (standard SOM)

JTAG_EMU1 - Normal operation

JTAG_EMU1 - See section 24.5.2 of the AM3517 TRM

Allows CAN_HECC1 signal to be used as GPIO_131 or UART3_RTS

CAN HECC1_RXD connected to CAN transceiver

Allows xMMC1_DAT6 to be used as GPIO_128

xMMC1_DAT6 connected to SDIO write protect

JTAG_EMU1 - Normal operation

JTAG_EMU1 - See section 24.5.2 of the AM3517 TRM

Allows ETK_D11 to be used as GPIO_25 at expansion connector or other functions, see AM3517 TRM

Button 2 drives ETK_D11 signal

Allows ETK_D12 to be used as GPIO_26 at expansion connector or other functions, see AM3517 TRM

Button 3 drives ETK_D12 signal

Allows ETK_D10 to be used as GPIO_24 at expansion connector or other functions, see AM3517 TRM

Button 1 drives ETK_D10 signal

Allows ETK_D13 to be used as GPIO_27 at expansion connector or other functions, see AM3517 TRM

Button 4 drives ETK_D13 signal

Allows MCSPI1_CS3 to be used as GPIO_177 at expansion connector or other functions, see AM3517 TRM

MCSPI1_CS3 connected to LCD_SPI_IRQ on X12

Allows MCSPI1_SOMI to be used as GPIO_173 at expansion connector or other functions, see AM3517 TRM

MCSPI1_SOMI connected to LCD_SPI_MISO on X12

Allows UART2_RXD to be used as GPIO_147 at expansion connector or other functions, see AM3517 TRM

UART2_RXD connected to xUART_RX

Allows MCBSP2_DR to be used as GPIO_118 at expansion connector or other functions, see AM3517 TRM

Connects MCBSP2_DR to audio codec

Sets the LCD LVDS transceiver IO reference for 3.3V

Sets the LCD LVDS transceiver IO reference for 1.8V

Configures the Carrier Board as an intermediate node on the CAN network.

Provides termination impedance at the carrier board

Allows MCBSP2_CLKX to be used as GPIO_117 at expansion connector

Connects MCBSP2_CLKX to audio codec

Chapter

20

20

21

29

28

21

33

33

33

33

25

25

27

22

25

29

22

© PHYTEC America LLC 2012 52

Part II, Chapter 18: Jumpers L-761e_2

Table 18-1. Jumper Settings (Continued)

J/JP

JP16

JP17

JP18

JP19

JP20

JP21

JP22

JP23

JP24

JP25

JP26

JP27

JP28

JP29

JP30

JP31

JP32

Setting Description

Closed

Open

Closed

Open

Closed

Open

Open

Open

Open

Open

Open

Closed

Open

Closed

Open

Closed

Open

Allows MCBSP2_FSX to be used as GPIO_116 at expansion connector

Connects MCBSP2_FSX to audio codec

Allows MCBSP2_DX to be used as GPIO_119 at expansion connector

Connects MCBSP2_DX to audio codec

Disconnects camera power

Connects camera power

Allows MCBSP4_FSX to be used as GPIO_155 or other functions, enable

DVI transcoder

Enables MCBSP4_FSX to control power down of DVI transcoder

Test point for GPIO from audio codec

Reserved

Allows xMMC1_DAT7 to be used as GPIO_129

xMMC1_DAT6 connected to SDIO card detect

See phyCAM-P interface manual for operation of this jumper

See phyCAM-P interface manual for operation of this jumper

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

1+2

2+3

1+2

2+3

Disconnects GPMC_NCS2 from LCD_PWM, disables LCD backlight intensity control, allows GPMC_NC2 to be used as GPIO_53 or other functions, see AM3517 TRM

Enables ETK_D14 (gpt9_pwm_evt) to control LCD backlight intensity

Disconnects ETK_D14 from LCD_BL_EN, enables LCD back light, allows ETK_D14 to used as GPIO_28 or other functions, see AM3517

TRM

Enables ETK_D14 (gpio_28) to control LCD backlight enable

Disconnects xMMC1_DAT5 from SDIO power enable, power enabled by card detect, SW can not turn power off to SDIO interface

Enables MMC1_DAT5 (gpio_127) to power off to SDIO interface; saving power

Allows UART2_CTS to be used as GPIO_144 at expansion connector or other functions, see AM3517 TRM

Connects UART2_CTS to xUART2_CTS

Allows GPMC_WAIT2 to be used as GPIO_64 at expansion connector or other functions, see AM3517 TRM

Connects GPMC_WAIT2 to USB1 over current indication

Allows GPMC_WAIT3 to be used as GPIO_65 at expansion connector or other functions, see AM3517 TRM

Connects GPMC_WAIT3 to USB0 over current indication

Sets USB0 capacitance on VBUS to 4uF for OTG mode

Sets USB0 capacitance on VBUS to 150uF for host mode

Grounds VBAT; RTC is not powered when main power is off

Sources VBAT from the BAT1 Li-Ion battery

SYS_CLKOUT1 drives audio MCLK (through JP35)

SYS_CLKOUT1 drives SYS_CLKOUT1B

Chapter

22

22

32

25

22

28

32

32

25

25

28

27

24

24

24

20

22

© PHYTEC America LLC 2012 53

Part II, Chapter 18: Jumpers L-761e_2

Table 18-1. Jumper Settings (Continued)

J/JP

JP33

JP34

JP35

JP36

JP37

JP38

JP39

Setting Description

1+2

2+3

1+2

2+3

1+2

2+3

1+2

2+3

1+2

2+3

1+2

2+3

Open

Closed

Sets the reference (SIGDISA) to the PoE power supply to VPORTN

Sets the reference (SIGDISA) to the PoE power supply to VPORTP

Enables SOM VIN power to be driven from X22 (3.3V - 5.0V)

Enables SOM VIN power to be driven from Carrier Board 3.3V power supply

Enables Audio MCLK to be driven from OZ1 crystal oscillator

Enables Audio MCLK to be driven from OZ1 AM3517 SYS_CLKOUT1

(through JP32)

Configures SYS_CLKOUT1 to drive CAM_MCLK

Configures SYS_CLKOUT1 to drive SYS_CLKOUT1B

Connects microphone bias to tip

Connects microphone bias to ring

Disables the Camera input

Enables camera input

USB0 OTG ID pin pulled high, normal for OTG

USB0 OTG ID pin grounded, port set to host mode

Chapter

20

20

22

32

22

32

24

© PHYTEC America LLC 2012 54

Part II, Chapter 19: phyCORE-AM3517 SOM Connectivity

19 phyCORE-AM3517 SOM Connectivity

L-761e_2

Fig. 19-1. phyCORE-AM3517 SOM Connectivity to the Carrier Board

Connector X15 on the Carrier Board provides the phyCORE-AM3517 System on Module connectivity. The connector is keyed for proper insertion of the SOM.

Figure 19-1

above shows the location of connector

X15, along with the pin numbering scheme.

© PHYTEC America LLC 2012 55

Part II, Chapter 20: Power

20 Power

L-761e_2

Fig. 20-1. Powering Scheme

The phyCORE-AM3517 Carrier Board powering scheme provides two possible power sources:

1.

Wall adapter power jack at X9

2.

Power over Ethernet (PoE) Ethernet jack at X17

In order to generate the VCC_5V0, primary input power is selected via jumper X22 and is supplied from either the wall adapter (via jack X9), or the Power over Ethernet circuit U14 (via Ethernet jack X17). All board power supplies ultimately generate power from VCC_5V0 except the VBAT which is supplied from

BAT1.

The VBAT terminals to the SOM are powered directly from the battery at BAT1. If this battery is installed and jumper JP31 is set to 2+3, then VBAT will always be present on an installed SOM and Carrier Board.

Therefore, care should be taken before performing any electrical work on the boards to prevent shorting out this battery.

CAUTION:

Remove the battery, remove JP31, or remove the SOM from X15 before performing any electrical work.

The following sections in this chapter describe each power block in detail.

20.1 Wall Adapter Input (X9)

Permissible input voltage: +3.3V to +5 VDC regulated.

© PHYTEC America LLC 2012 56

Part II, Chapter 20: Power L-761e_2

The primary input power to the phyCORE-AM3517 Carrier Board is located at connector X9. The required load current capacity of the power supply depends on the specific configuration of the phyCORE-AM3517 mounted on the Carrier Board, and the interfaces enabled while executing software. An adapter with a minimum supply of 2000mA is recommended.

A detailed list of applicable configuration jumpers is presented below.

X22 Configures primary input power source. By default this jumper is set to 1+3/2+4, sourcing board power from the wall adapter input. Alternatively this jumper can be set to 3+5/4+6, sourcing board power from the Power over Ethernet circuit.

D26 Shows the status of the input power supply (wall power or PoE). When illuminated the supply is active.

20.2 Power over Ethernet (PoE)

The Power over Ethernet (PoE) circuit provides a method of powering the board via the Ethernet interface.

In this configuration the phyCORE-AM3517 Carrier Board acts as the Powered Device (PD) while the connecting Ethernet interface acts as the Power Source Equipment (PSE). For applications that require

Ethernet connectivity, this is an extremely convenient method for simultaneously providing power. To make use of the PoE circuit you must have a PSE for connectivity. Typically a PoE enabled router or switch can be used.

Table 20-1 provides a list of possible Power Sourcing Equipment you can purchase to interface

the phyCORE-AM3517 PoE circuit if you do not already have a PSE.

Table 20-1. Possible Ethernet PSE Options

Device Description

FS108P Netgear 8-port Ethernet switch with 4-port PoE support.

TPE-101I TRENDnet single port PoE injector

The IEEE PoE standard restricts the maximum amount of power a PSE must provide and therefore a PD can consume. The phyCORE-AM3517 Carrier Board PoE circuit was designed to provide up to 8.5W of power to the board. Note that this is less than the wall adapter can supply and less than the SOM, Carrier

Board, and additional circuits can potentially consume. The base configuration of the SOM and Carrier

Board typically consume less than 2 watts. Be aware that this PoE limitation could cause board operation to fail if peak power capability is exceeded due to added peripherals. The phyCORE-AM3517 Carrier

Board Ethernet connector X17 supports both PSE power sourcing methods of power over the data wires, or power over the spare wires.

A detailed list of applicable configuration jumpers and LED indicators is presented below.

JP33 Controls the PoE signature resistor internal to the Linear Tech LTC4267 PoE IC. By default this jumper is set to the 2+3 position, enabling the 25k signature resistor. Alternatively this jumper can be set to the 1+2 position, disabling the 25k signature resistor. For normal operation this jumper should be set to the 2+3 position, but in some applications it may be necessary to disable the signature resistor.

X22 Configures primary input power source. By default this jumper is set to 1+3/2+4, sourcing board power from the wall adapter input. Alternatively this jumper can be set to 3+5/4+6, sourcing board power from the Power over Ethernet circuit.

© PHYTEC America LLC 2012 57

Part II, Chapter 20: Power L-761e_2

D25

D28

PoE 5V power indicator. When illuminated the PoE circuit is actively generating 5V.

Ethernet LINK status indicator. When illuminated the Ethernet interface has established a link to the network. This LED blinks when there is activity on the Ethernet interface.

D31 Ethernet ACTIVITY status indicator. When illuminated the Ethernet interface is linked in

100Mbps mode.

20.3 Lithium-Ion Battery

The phyCORE-AM3517 Carrier Board utilizes a Lithium-Ion Battery (at Bat1) to power the RTC when main power is off. The PMIC on the SOM switches from main power to the Lithium-Ion Battery when the main power is turned off. The battery used in the BAT1 position is a Panasonic CR2032 or equivalent. The battery may be replaced with the system running on main power, but care should be taken to ensure the battery and/or battery holder terminals are not shorted during this process. The RTC requires one source of continuous power in order to keep time.

The applicable configuration jumper is presented below.

JP31 Configures Carrier Board VBAT voltage supply. By default this jumper is set to 2+3, sourcing

VBAT power from the Lithium-Ion battery. Alternatively this jumper can be set to 1+2, to ground the VBAT supply. Note, with VBAT at ground, the VRTC power rail is supplied only when VIN power is on, hence the RTC will not preserve time when VIN power is off.

20.4 3.3V Supply (U27)

The Linear Technology LTC3612EFE switching regulator (U27) powers the VCC_3V3 power supply rail.

This power supply powers most of the accessory circuits on the Carrier Board. It can optionally power the phyCORE-AM3517 SOM by supplying power to VIN. It can also optionally power the VCC_IO power rail on the Carrier Board.

A detailed list of applicable configuration jumpers is presented below.

X21 Configures Carrier Board VCC_IO voltage level. By default this jumper is set to 3+5/4+6, sourcing VCC_IO power from the 3.3V supply U27. Alternatively this jumper can be set to

1+3/2+4, sourcing VCC_IO from the 1.8V regulator (U31).

JP34 Configures VIN to the phyCORE-AM3517 SOM to be powered from VCC_3V3 or VCC_5V0

(3.3V-5.0V). By default this jumper is set to 2+3, sourcing VIN power to the SOM from

VCC_3V3. Alternatively this jumper can be set to 1+2, sourcing VIN to the SOM from

VCC_5V0.

20.5 1.8V Supply (U31)

The Linear Technology LTC3411 switching regulator (U31) powers the VCC_1V8 power supply rail. This power supply powers a few accessory circuits on the Carrier Board. It can optionally power the VCC_IO power rail on the Carrier Board.

© PHYTEC America LLC 2012 58

Part II, Chapter 20: Power L-761e_2

The applicable configuration jumper is presented below.

X21 Configures Carrier Board VCC_IO voltage level. By default this jumper is set to 3+5/4+6, sourcing VCC_IO power from the 3.3V supply (U27). Alternatively this jumper can be set to

1+3/2+4, sourcing VCC_IO from the 1.8V regulator (U31).

20.6 Current Measurement

To facilitate current measurement, jumpers R121 - R126 are provided as current access measurement points. Replace these jumpers with 1206 packaged precision shunt resistors and measure the resulting voltage drop across the shunt resistor to calculate current draw. A good value to start with for your shunt resistor is 25mΩ. The shunt resistor should be small enough to have no effect on the output voltage (it will be reduced by the voltage drop across the shunt), but large enough to have a discernible measurement from supply noise.

© PHYTEC America LLC 2012 59

Part II, Chapter 21: JTAG Connectivity

21 JTAG Connectivity

L-761e_2

Fig. 21-1. JTAG Probe Connectivity to the phyCORE-AM3517

Connector X13 provides a convenient JTAG probe connection interface for ARM Cortex-A8 compatible

JTAG probes to the AM3517.

Table 21-1 provides a detailed list of the signals at the JTAG connector.

Cross reference this with a JTAG probe on the target application to ensure compatibility.

Table 21-1. phyCORE-AM3517 JTAG Connector X13 Pin Descriptions

Pin

7

8

5

6

3

4

1

2

9

10

11

12

13

Signal

VTREF

VSUPPLY

/TRST

GND

TDI

GND

TMS

GND

TCK

GND

RTCK

GND

TDO

Description

Ref voltage input - connected to VCC=3.15V

Supply input - connected to VCC=3.15V

Test controller reset input with internal 10k pull-up

Ground

Test data input with internal 10k pull-up

Ground

Test mode select input with internal 10k pull-up

Ground

Test clock input with internal 10k pull-down

Ground

Return test clock output with internal 10k pull-down

Ground

Test data output

© PHYTEC America LLC 2012 60

Part II, Chapter 21: JTAG Connectivity

Table 21-1. phyCORE-AM3517 JTAG Connector X13 Pin Descriptions

Pin

18

19

20

14

15

16

17

Signal

GND

/SRST

GND

N/C

GND

N/C

GND

Description

Ground

System reset input with internal 10k pull-up

Ground

No connect

Ground

No connect

Ground

L-761e_2

As of the printing of this manual,

Table 21-2

lists JTAG probes which are known to be compatible to the phyCORE-AM3517 Carrier Board JTAG interface.

Table 21-2. Compatible JTAG Probes for the phyCORE-AM3517 Carrier Board

JTAG Probe Name

ARM Realview ICE

A detailed list of the connector and applicable LED indicators is presented below.

X13 This connector provides a convenient interface for the AM3517's ARM Cortex-A8 processor to a compatible JTAG probe.

Table 21-1 provides a detailed list of the signals at the JTAG

connector. Cross reference this with a JTAG probe on the target application to ensure compatibility.

JP4

JP1

Reserved

Reserved

© PHYTEC America LLC 2012 61

Part II, Chapter 22: Audio Interface

22 Audio Interface

L-761e_2

Fig. 22-1. Audio Interface Connectors and Jumpers

The audio interface provides a method of exploring the AM3517's I²S capabilities. The phyCORE-AM3517

Carrier Board is populated with a Wolfson Microelectronics’ WM8974 mono audio codec.

This codec supports the following:

• Microphone input

• Line output

• Headphone output

• Loudspeaker

The WM8974 is interfaced to the phyCORE-AM3517 SOM via the I²S on McBSP2 port for audio data and the I²C port 2 for codec configuration. The codec is clocked from the processor SYS_CLKOUT1 (optional) or from a crystal oscillator on the Carrier Board (default). JP35 and JP32 configuration allows flexible

control over board audio clock source. See Table 18-1

for jumper configuration settings.

A detailed list of applicable connectors and configuration jumpers is presented below.

X23 Loud speaker out for connecting to a speaker (8 ohms).

X24

X25

MIC jack input for connecting to a compatible electret type microphone. The MIC is biased via a 10k pull-up to WM8974's MIC bias drive. Ensure that this does not exceed the biasing requirements of the MIC.

Stereo Headphone Output jack for connecting to a set of headphones. This output is capable of driving a 8 Ohm load.

© PHYTEC America LLC 2012 62

Part II, Chapter 22: Audio Interface L-761e_2

X26

X23

JP12

JP15

JP16

JP17

JP20

JP35

JP32

JP37

Line Output jack for connection to an applicable audio input source capable of receiving a

~0.945V RMS (typical) input signal (such as the LINE INPUT on a PC).

MIC bias configuration jumper is by default set to the 1+2 position, biasing a mono input microphone. This jumper may be useful for independently biasing and using either channel of a stereo MIC. Set this jumper to the 2+3 position to use and bias the right channel and

1+2 for the left channel.

Connects the MCBSP2_DR processor signal to the audio codec. By default this jumper is set to the closed position. Open this jumper to free this signal for external use.

Connects the MCBSP2_CLKX processor signal to the audio codec. By default this jumper is set to the closed position. Open this jumper to free this signal for external use.

Connects the MCBSP2_FSX processor signal to the audio codec. By default this jumper is set to the closed position. Open this jumper to free this signal for external use.

Connects the MCBSP2_DX processor signal to the audio codec. By default this jumper is set to the closed position. Open this jumper to free this signal for external use.

GPIO out of audio chip. This jumper is for test purposes only. Do not install this jumper.

Selects audio codec clock source. By default this jumper is set to the 1+2 position to use the external crystal oscillator OZ1. Set jumper to 2+3 to use SYS_CLKOUT1 clock signal from

AM3517 processor.

This jumper causes the SYS_CLKOUT1 from the SOM to be connected to nets xSYS_CLKOUT1A or xSYS_CLKOUT1B. Set this jumper in the 1+2 position to connect

SYS_CLKOUT1 to SYSCLKOUT1A net which connects to the audio section. Set this jumper in the 2+3 position to connect SYS_CLKOUT1 to SYSCLKOUT1B net which connects to the expansion connector.

This jumper is used to supply bias current to the microphone. Position 1+2 generates a bias current on the tip. Position 2+3 generates bias current on the ring. The correct setting for this jumper will depend on the wiring for the MIC. Refer to the microphone's documentation for correct bias wiring.

© PHYTEC America LLC 2012 63

Part II, Chapter 23: Ethernet Connectivity

23 Ethernet Connectivity

L-761e_2

Fig. 23-1. Ethernet Interface Connector and LEDs

The Ethernet interface provides a method of connecting to the phyCORE-AM3517 Ethernet functionality.

One RJ-45 connector is provided at X17. This connector provides both a connection to the Ethernet data signals and the Power over Ethernet power signals. A LINK/ACTIVITY and SPEED LED are provided on the Carrier Board at D31 and D26.

A detailed list of the connector and applicable LED indicators is presented below.

X17 This 10/100 Base-T Ethernet connect provides a standard Ethernet cable connection point for the AM3517 to a network. This interface supports PoE injection as well as Ethernet connectivity. In addition, this Ethernet interface supports straight and crossover cable wiring through the AUTOMDIX function of the 10/100 PHY.

D28 Ethernet LINK/ACTIVITY status indicator. When illuminated the Ethernet interface has established a link to the network. This LED blinks when there is activity on the Ethernet interface.

D31 Ethernet SPEED status indicator. When illuminated the Ethernet interface is linked in

100Mbps mode.

For information on using the Power over Ethernet circuit refer to

Chapter 20.2

.

© PHYTEC America LLC 2012 64

Part II, Chapter 24: USB Connectivity

24 USB Connectivity

L-761e_2

Fig. 24-1. USB Interface Connectors and Jumpers

The USB connectors provide connectivity to the phyCORE-AM3517's two USB interfaces. Peripheral connector X2 provides the dedicated host interface. This is connected to the USB1 interface on the

AM3517 thorough a USB PHY. Connector X1 provides a Mini-AB OTG interface, which is connected to the

USB0 (internal PHY) interface on the AM3517.

The host interface is provided with an additional 5V supply current for robust peripheral power.

The OTG interface has configuration jumpers, along with additional 5V supply current for non-OTG peripherals. A USB OTG compliant device is only required to source up to 8mA of current when operating as a host. Because very few devices are OTG compliant and most USB peripherals require more than

8mA to operate, a 5V power circuit and configuration jumper have been provided to facilitate these devices.

Both USB interface's VBUS power is current limited by U1 (TPS2052BD)

A detailed list of applicable configuration jumpers and connectors is presented below.

X2 USB Standard-A host connection interface. Connect a USB Standard-A mating cable to this connector when operating this USB interface in host mode.

X1 USB Mini-AB OTG connection interface. Connect a USB OTG cable to this connector when operating the USB interface in OTG mode. Connect a USB mini-B connector to this interface to use in peripheral mode.

© PHYTEC America LLC 2012 65

Part II, Chapter 24: USB Connectivity L-761e_2

JP39

JP30

JP28

JP29

This jumper grounds the ID pin on X1's OTG port. Use this jumper to make this port a host port.

This jumper adds additional capacitance to the OTG port's VBUS. With this jumper OPEN a capacitor of 4.7µF is connected to VBUS. When this jumper is CLOSED a 150µF capacitor is placed in parallel to the 4.7µF capacitor on VBUS.

This jumper connects the over-current indication for USB1 interface (X2) to the AM3517.

Removing this jumper makes the GPMC_WAIT2 signal available for external use.

This jumper connects the over-current indication for USB0 interface (X1) to the AM3517.

Removing this jumper makes the GPMC_WAIT3 signal available for external use.

© PHYTEC America LLC 2012 66

Part II, Chapter 25: LCD and DVI Connectivity

25 LCD and DVI Connectivity

L-761e_2

Fig. 25-1. LCD/DVI Interface Connectors, Jumpers, and Switches

The phyCORE-AM3517 Carrier Board provides flexible LCD and DVI connection interfaces to support various PHYTEC provided LCD boards. The universal LCD connector X30 provides power and buffered signals to connecting LCDs.

The universal LCD interface consists of the following components:

1.

CPLDs for buffered signals and color signal control

2.

Mode set jumpers for various LCD color bit encoding modes

3.

Buffered I²C interface

4.

PWM controlled backlight and LCD enable

The CPLDs come pre-programmed; supporting the 24bpp (8:8:8), 18bpp (6:6:6), 16bpp (5:6:5), and 12bpp

(4:4:4) modes allowed on the AM3517 LCD controller. Color signal control allows dynamic reconfiguration of the color signals to support various LCD bit widths.

As an example, consider only the blue color signals from a 24-bit LCD. In the case of a 24-bit LCD

Figure

25-2

shows the connection interface from the AM3517 DSS port all the way to the LCD. As can be seen

DSS23...16 from the processor map directly to LCD_RED7...0 via the CPLD U22.

© PHYTEC America LLC 2012 67

Part II, Chapter 25: LCD and DVI Connectivity L-761e_2

Fig. 25-2. LCD Signal Mapping in 24-bit Mode with a 24-bit LCD

In the case of an 16-bit LCD, Figure 25-3 shows the lower 3-bits of the RED signals to the connector X30

are held to 0 (low) by the CPLD when operating the AM3517 in 16-bit 5:6:5 mode. The result is that the upper 5 bits of the LCD blue interface are driven with the blue color data provided by the AM3517. The lower blue LCD bits 2...0 are driven to 0 by the CPLD (since this data bit is not provided by the 16-bit operating mode of the AM3517). The upper 8 bits of the AM3517 DSS interface (DSS23...16) are freed for use as their alternative functions when operating in this mode.

Fig. 25-3. LCD Signal Mapping in 16-bit Mode with an 16-Bit LCD

Figure 25-3

shows a detailed mapping of the AM3517 LCD port signals through the CPLD. In general the

CPLD is acting as a buffer, mapping LCD23...16 directly to LCD_BLUE7...0, LCD15...8 to

LCD_GREEN7...0, and LCD7...0 to LCD_RED7...0. The only time this is not true is for the lower LCD color bits for 16-bit and 12-bit mode. In the 16-bit modes (5:6:5 and 5:5:5) and 12-bit mode (4:4:4) the unused

LCD bits on the AM3517 LCD port are not buffered through the CPLD. Instead the CPLD holds these signals low for these operating modes.

© PHYTEC America LLC 2012 68

Part II, Chapter 25: LCD and DVI Connectivity L-761e_2

Table 25-1 , Table 25-2 , Table 25-3

, and

Table 25-4

show the signal mapping for the four LCD bit modes

(C=CLOSED; O=OPEN):

Table 25-1. 24-bit 8:8:8 mode (S1-1,S1-2, S1-3, S1-4 = O,O,O,O)

AM3517 Signal

DSS23...16

DSS15...8

DSS7...0

LCD Connector X30 Signal

→ LCD_RED7...0

→ LCD_GRN7...0

→ LCD_BLUE7...0

Table 25-2. 12-bit 4:4:4 mode (S1-1,S1-2, S1-3, S1-4 = C, C, C, O)

AM3517 Signal

DSS11...8

DSS7...4

DSS3...0

LCD Connector X30 Signal

LCD_RED7...4

→ LCD_GRN7...4

LCD_BLUE7...4

Table 25-3. 16-bit 5:6:5 mode (S1-1,S1-2, S1-3, S1-4 = C, C, O, C)

AM3517 Signal

DSS15...11

DSS10...5

DSS4...0

LCD Connector X30 Signal

→ LCD_RED7...3

LCD_GRN7...3

→ LCD_BLUE7...3

Table 25-4. 18-bit 6:6:6 mode (S1-1,S1-2, S1-3, S1-4 = C, C, O, O)

AM3517 Signal

DSS17...12

DSS11...6

DSS5...0

LCD Connector X30 Signal

LCD_RED7...2

→ LCD_GRN7...2

LCD_BLUE7...2

© PHYTEC America LLC 2012 69

Part II, Chapter 25: LCD and DVI Connectivity L-761e_2

Table 25-5 shows a summary of the required switch settings for each of the AM3517 LCD operating

modes.

Table 25-5. LCD Mode Jumper Summary (S1-1,S1-2, S1-3, S1-4)

LCD Mode

24-bit 8:8:8

18-bit 6:6:6

16-bit 5:6:5

12-bit 4:4:4

Switch Settings (S1-1, S1-2, S1-3, S1-4)

OPEN, OPEN, OPEN, OPEN

CLOSED, CLOSED, CLOSED, OPEN

CLOSED, CLOSED, OPEN, CLOSED

CLOSED, CLOSED, OPEN, OPEN

25.1 DVI Connector

A DVI connector is provided at X8, see

Figure 25-1

. The DVI encoder (U28) formats the DSS video signals in 24 bit mode appropriately for any DVI (digital) compatible monitor. The DVI output operates in parallel with the LCD outputs so the DVI, LVDS LCD and TTL LCD ports can simultaneously drive video to their respective connectors.

A detailed list of the connector and applicable configuration jumpers is presented below

JP19 This jumper is used to allow the AM3517 to put the DVI encoder into a power down mode.

CLOSE this jumper to allow AM3517 control of the power down. OPEN this jumper to allow

GPIO_155 to be used as a GPIO.

JP13 This jumper is used to set the DVI encoder IO voltage levels to 1.8V or 3.3V. CLOSE this jumper to operate SOM IOs at1.8V; OPEN to use 3.3V IOs.

X8 DVI (digital) interface connector. This can be connected to a digital DVI compatible monitor; resolution must be consistent with SOM BSP configuration.

25.2 LVDS Connectors

Two connectors are provided to support LVDS LCDs. The LVDS signaling connector is provided at X12 and the power connector is at X20. The LVDS output operates in parallel with the DVI and TTL LCD outputs so the DVI and TTL LCD ports can simultaneously drive video to their respective connectors.

A detailed list of applicable configuration jumpers, switches, and connectors is presented below.

JP25 LCD backlight control jumper. By default this jumper is CLOSED, selecting processor signal

ETK_D14 to control LCD backlight. OPEN this jumper to permanently turn on the LCD backlight. When this jumper is removed, the processor signal ETK_D14 becomes free for external use.

S2

JP24

Reserved

LCD PWM control jumper. By default this jumper is CLOSED, selecting processor signal

GPMC_NCS2 to control LCD backlight PWM (brightness). OPEN this jumper to permanently disable LCD backlight control. When this jumper is removed, the processor signal

GPMC_NCS2 becomes free for external use.

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Part II, Chapter 25: LCD and DVI Connectivity L-761e_2

X12

X20

JP9

LVDS LCD signaling connector. This can be used to connect an LUD supported LCD such as the PHYTEC LCD-014

LVDS LCD power connector. This can be used to power an LCD such as the PHYTEC LCD-

014

LCD SPI SOMI jumper. By default this jumper is CLOSED, selecting processor signal

MCSPI1_SOMI to interface to the LCD SPI EEPROM. OPEN this jumper to permanently disable LCD EEPROM access. When this jumper is removed, the processor signal

MCSPI1_SOMI becomes free for external use.

JP10 LCD SPI IRQ jumper. By default this jumper is CLOSED, selecting processor signal

MCSPI1_CS3 to interface to the LCD SPI interrupt. OPEN this jumper to permanently disable LCD SPI interrupt. When this jumper is removed, the processor signal MCSPI1_CS3 becomes free for external use.

25.3 TTL LCD Connector

Connector X30 and a level translator (U22) are provided to interface to a PHYTEC standard TTL LCD such as the LCD-011. This interface uses standard 3.3V TTL level signaling that can be used to interface to other standard TTL level LCDs with 12, 16, 18, or 24 bit interfaces. A CPLD is provided for convenience in switching between various bit modes and LCD bit depths during software development. In the target

application, the CPLD is not required. See Table 25-5 for detailed list of switch settings for these various bit

mode settings.

A detailed list of the applicable switch, and connectors is presented below.

S1 Configures the LCD operating mode. By default these switches are set to OPEN, OPEN,

OPEN, OPEN resulting in the 24-bit 8:8:8 operating mode. See

Table 25-5 for a detailed list

of switch settings and corresponding operating modes.

X30

X11

TTL LCD interface connector

CPLD JTAG connector, reserved

© PHYTEC America LLC 2012 71

Part II, Chapter 26: GPIO Expansion Connector

26 GPIO Expansion Connector

L-761e_2

Fig. 26-1. GPIO Expansion Connector

Figure 26-1

shows the location of the GPIO expansion port connector X14. This connector provides a 1:1 mapping of most of the phyCORE-AM3517 mating connector X15 signals. Additional signals generated on the Carrier Board are also routed to the GPIO expansion port connector X14. As an accessory, a GPIO

Expansion Board (part # PCM-988) is made available through PHYTEC to mate with the X14 connector on the phyCORE-AM3517 Carrier Board. This Expansion Board provides a patch field for easy access to all signals, plus additional board space for testing and prototyping. A summary of the signal mappings

between X14, X15, and the patch field on the GPIO Expansion Board is provided in Part III .

© PHYTEC America LLC 2012 72

Part II, Chapter 27: RS-232 Connectivity

27 RS-232 Connectivity

L-761e_2

Fig. 27-1. RS-232 Interface Connectors and Jumpers

Female DB9 connector P1, and a 10 pin 0.1"/2.54mm spaced header (X29) provide connectivity to the phyCORE-AM3517 UART3 and UART2 interfaces at RS-232 levels. Connector P1 is dedicated to UART3, while X29 is dedicated to UART2. In addition to these connectors, a 0.1"/2.54mm header at X10 is provided for easy access the UART2 and UART3 signals at TTL levels.

Figure 27-2 shows the pin numbering for the DB9 connectors, while

Table 27-1 and Table 27-2 give a

detailed description of the signals at P1 and X29.

Fig. 27-2. DB9 RS-232 Connectors P1 (UART3) Pin Numbering

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Part II, Chapter 27: RS-232 Connectivity L-761e_2

Table 27-1. Connector P1 (UART3) Pin Descriptions

Pin Signal

7

8

5

6

9

3

4

1

2

I/O Description

N/C Not connected

U3_TX_RS232 O UART3 transmit

U3_RX_RS232 I

N/C -

UART3 receive

Not connected

GND

N/C

N/C

N/C

N/C

-

-

-

-

-

Ground

Not connected

Not connected

Not connected

Not connected

Figure 27-3 shows a detail of the pin numbering at the UART2 header (X29) while Table 27-2

gives a description of signals. Pin number 1 can be found by looking for the beveled silk-screen around the header.

Fig. 27-3. Connector X29 (UART2) Pin Numbering

Table 27-2. Connector X29 (UART2) Pin Descriptions

Pin Signal

5

6

7

3

4

1

2

N/C

UART2_RX_RS232

UART2_TX_RS232

N/C

GND

N/C

I/O

I

-

O

-

-

-

UART2_RTS_RS232 O

Description

Not connected

UART 2 receive

UART 2 transmit

Not connected

Ground

Not connected

Ready to send

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Part II, Chapter 27: RS-232 Connectivity

Table 27-2. Connector X29 (UART2) Pin Descriptions

Pin Signal I/O Description

8

9

UART2_CTS_RS232

N/C

10 N/C

I

-

-

Clear to send

Not connected

Not connected

L-761e_2

Figure 27-4

shows a detail of the pin numbering at connector X10. Pin number 1 can be identified by the beveled silk-screen around the header.

Fig. 27-4. UART3/UART2 Header Connector X10 Pin Numbering

Table 27-3

gives detailed pin numbering descriptions at the TTL/RS-232 UART header (X10).

Table 27-3. TTL UART Pin Header (X10) Descriptions

6

7

8

9

10

Pin Signal

3

4

1

2

5

UART3_RTS

UART2_TXD

UART3_CTS

UART2_RTS

UART3_TX_R

S232

I

I/O

O

O

O

O

UART2_RXD I

UART3_RX_

RS232

I

UART2_CTS I

VCC_IO -

GND -

Description

UART3 ready to send, TTL levels

UART2 transmit data, TTL levels

UART3 clear to send, TTL levels

UART2 ready to send, TTL levels

UART3 transmit, RS-232 levels

UART2 receive data, TTL levels

UART3 receive, RS-232 levels

UART2 clear to send, TTL levels

IO power (1.8V or 3.3V)

Ground

In addition to the three access connectors, two configuration jumpers are provided to free up signals for alternative use. A detailed list of the applicable connectors and configuration jumpers is presented below.

P1 UART3 connection point. This connector supports RS-232 level signals.

X29 UART2 connection point. This connector supports RS-232 level signals.

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Part II, Chapter 27: RS-232 Connectivity L-761e_2

X10

JP11

JP27

This header provides access to the UART2 and UART3 TTL level signals for debug.

Connects UART2_RXD signal to the RS-232 transceiver, through a level translator. By default this jumper is in the CLOSED position, enabling RS-232 communication. OPEN this jumper to free up UART2_RXD for external use.

Connects UART2_CTS signal to the RS-232 transceiver, through a level translator. By default this jumper is in the CLOSED position, enabling RS-232 communication. OPEN this jumper to free up UART2_CTS for external use.

© PHYTEC America LLC 2012 76

Part II, Chapter 28: SD/SDIO/MMC Connectivity

28 SD/SDIO/MMC Connectivity

L-761e_2

Fig. 28-1. SDIO Interface Connectors and Jumpers

Connector X5 provides connectivity to the phyCORE-AM3517's SD/SSDIO/MMC1 card interface. In addition, header connector X3 has been provided for easy access to the SD/SDIO/MMC1 card signals for probing purposes. An instant-on 3.3V power supply capable of supplying 1.2A of current has been provided for dynamic power control to the connected SD/SDIO/MMC card. The power circuit is controlled via the card detect function of the SD card connector and the processor signal MMC1_DAT5. At initial card insertion, the power supply is turned on by a GPIO. After discovery, the processor can disable this power if desired. Set MMC1_DAT5 high to turn the SD/SDIO/MMC1 power ON and low to turn the SD/SDIO/MMC1 power off.

The phyCORE-AM3517 supports an additional SD/SDIO/MMC interface which is used in the wireless connector and is documented in

Chapter 30 .

Several configuration jumpers are provided for control of the SD/SDIO/MMC1 interface. A detailed list of applicable configuration jumpers and connectors is presented below.

JP26 Connects the buffered processor signal MMC1_DAT5 to the SD/SDIO/MMC power control circuit. By default this jumper is set to the CLOSED position, enabling processor control over the SD/SDIO/MMC power supply. Set this jumper to the OPEN position to free up

MMC1_DAT5 for external use.

JP21 Connects processor signal MMC1_DAT7 to the SD/SDIO/MMC card detect output. By default this jumper is set to the CLOSED position, enabling the processor to detect SD/

SDIO/MMC card presence. Set this jumper to the OPEN position to free up the MMC1_DAT7 signal for external use.

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Part II, Chapter 28: SD/SDIO/MMC Connectivity L-761e_2

JP3

X7

X5

X3

Connects the processor signal MMC1_DAT6 to the SD/SDIO/MMC card write protect output.

By default this jumper is set to the CLOSED position, enabling the processor to detect the

SD/SDIO/MMC card write protect state. Set this jumper to the OPEN position when using the

SD/SDIO/MMC card slot with SDIO devices. Remove this jumper to free up MMC1_DAT6 for external use

Connection point for a WIFI/Bluetooth module, such as the PHYTEC PCM-958

MMC1/SD Card/ SDIO card connector. This connector supports the MMC, SD Card or SDIO standard interface and is form factor compatible with these standards.

Provides a convenient access point to the signals on X5 to aid in debug.

Table 28-1

shows the signal locations and descriptions on the connector.

Table 28-1. SDIO Easy Access Header Connector Signal Descriptions

Pin Signal

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2 xMMC1_CLK xMMC1_CMD xMMC1_DAT0 xMMC1_DAT1 xMMC1_DAT2 xMMC1_DAT3 xMMC1_DAT4 xMMC1_DAT5 xMMC1_DAT6 xMMC1_DAT7

N/C

N/C

GND

VCC_MMC1

GND

VCC_MMC1

I/O

-

-

-

-

-

-

IO

IO

IO

IO

IO

IO

O

O

IO

IO

Description

SD/SDIO/MMC clock

SD/SDIO/MMC command

SD/SDIO/MMC data 0

SD/SDIO/MMC data 1

SD/SDIO/MMC data 2

SD/SDIO/MMC data 3

SD/SDIO/MMC data 4

SD/SDIO/MMC data 5

SD/SDIO/MMC data 6

SD/SDIO/MMC data 7

Not connected

Not connected

Ground

SD/SDIO/MMC power

Ground

SD/SDIO/MMC power

© PHYTEC America LLC 2012 78

Part II, Chapter 29: CAN (Controller Area Network) Interface

29 CAN (Controller Area Network) Interface

L-761e_2

Fig. 29-1. CAN Interface Connectors and Jumpers

The phyCORE-AM3517 Carrier Board provides all necessary circuitry to connect the AM3517 HECC (High

End CAN Controller) on the phyCORE SOM to a CAN bus via the DB9 style connector at X6. A 3.3V highspeed CAN transceiver (SN65HVD234) populates U11. This transceiver converts the single-ended CAN signals of the controller to the differential signals of the physical layer; supporting specifications within the

ISO 11898 standard. It is capable of supporting signal rates of up to 1 Mbps. Additional ESD protection and

EMI filtering is also integrated on the Carrier Board. CAN bus line termination can be enabled using a removable jumper (JP14). This interface is CAN version 2.0B compliant.

Below is a detailed list of the jumpers and connector associated with the CAN interface.

X6 Standard CAN 2.0B connection point in a DB9 connector.

JP14

JP2

In the CLOSED position, this jumper provides termination impedance at the Carrier Board.

This is used when the phyCORE-AM3517 Carrier Board is the end point of a CAN network.

Jumper position should be OPEN if the phyCORE-AM3517 Carrier Board is an intermediate node on the CAN network.

The CLOSED position connects the CAN transceiver (U11) to the HECC1_RXD signal on the SOM. Leave this CLOSED if the CAN interface is used; OPEN this jumper to free up the

HECC_RXD for external use.

© PHYTEC America LLC 2012 79

Part II, Chapter 30: Wireless Connector

30 Wireless Connector

L-761e_2

Fig. 30-1. Wireless Interface Connector

The wireless connector (X7) is a 0.1"/2.54mm 2x16 header. It houses a collection of SDIO, UART and I²S interfaces required to connect to a WIFI/Bluetooth module, such as the PHYTEC PCM-958.

Table 30-1

is a detailed list of the signals on this connector.

Table 30-1. Wireless Connector (X7) Signal Descriptions

Pin Signal

7

8

5

6

3

4

1

2

9

10

11

12

13

MCBSP1_FSX

GND

MCBSP1_DX

VCC_1V8

MCBSP1_CLKX

VCC_1V8

GND

GND

UART1_TX

VCC_IO

UART1_RTS

VCC_IO

MMC2_DAT5

I/O

-

-

O

-

I

-

O

-

O

-

O

-

IO

Description

I²S framing signal

Ground

I²S data transmit

Power (1.8V)

I²S clock

Power (1.8V)

Ground

Ground

UART 1 transmit data

IO Power (1.8V or 3.3V)

UART 1 ready to send

IO power (1.8V or 3.3V)

SDIO data 5

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Part II, Chapter 30: Wireless Connector

Table 30-1. Wireless Connector (X7) Signal Descriptions

Pin Signal

26

27

28

29

22

23

24

25

30

31

32

18

19

20

21

14

15

16

17

VCC_3V3

GND

VCC_3V3

MMC2_DAT4

GND

MMC2_DAT6

MCBSP1_DR

MMC2_DAT3

UART1_RX

GND

UART1_CTS

MMC2_DAT2

GND

MMC2_DAT1

MMC2_DAT7

MMC2_DAT0

MMC2_CMD

GND

MMC2_CLK

I/O

-

IO

IO

IO

I

-

I

IO

O

-

O

-

IO

I

IO

-

-

-

IO

Description

Power (3.3V)

Ground

Power (3.3V)

SDIO data 4

Ground

SDIO data 6

I²S data in

SDIO data 3

UART 1 receive data

Ground

UART 1 clear to send

SDIO data 2

Ground

SDIO data 1

SDIO data 7

SDIO data 0

SDIO command

Ground

SDIO clock

L-761e_2

© PHYTEC America LLC 2012 81

Part II, Chapter 31: TV Out

31 TV Out

L-761e_2

Fig. 31-1. TV Out Connector

The TV Out connector (X16) is driven by the Video DAC on the AM3517 processor. This interface supports

NTSC, PAL-B,D,G, H, I, and M. The connector is a standard S-Video connector type.

© PHYTEC America LLC 2012 82

Part II, Chapter 32: Camera Interface

32 Camera Interface

L-761e_2

Fig. 32-1. Camera Interface Connectors and Jumpers

The camera interface is provided to connect a CCD camera. The connectors X19 and X18 are PHYTEC standard connectors which can be used to connect a PHYTEC device. A 16 pin 0.1"/2.54mm spaced header (X4) is also provided to connect a camera or to easily probe camera signals.

Table 32-1. Camera Interface (X4) Signal Descriptions

Pin

7

8

5

6

3

4

1

2

9

10

11

12

13

Signal

CCDC_FIELD

CCDC_DATA3 I

I

CCDC_DATA7 I

CCDC_DATA2 I

CCDC_DATA6 I

I/O

CCDC_PCLK

VCC_IO

CCDC_VD

GND

CCDC_HD

GND

CCDC_WE

CCDC_DATA4 I

I

IO

-

IO

-

IO

-

Description

Camera CCD interface clock

IO Power (1.8V or 3.3V)

Camera CCD interface - vertical sync

Ground

Camera CCD interface - horizontal sync

Ground

Camera CCD interface - write enable

Camera CCD interface - data 4

Camera CCD interface - field ID signal

Camera CCD interface - data 3

Camera CCD interface - data 7

Camera CCD interface - data 2

Camera CCD interface - data 6

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Part II, Chapter 32: Camera Interface

Table 32-1. Camera Interface (X4) Signal Descriptions

Pin

14

15

16

Signal

CCDC_DATA1 I

CCDC_DATA5 I

CCDC_DATA0 I

I/O Description

Camera CCD interface - data 1

Camera CCD interface - data 5

Camera CCD interface - data 0

L-761e_2

Below is a detailed list of the connectors and configuration jumpers associated with the camera interface.

X18 This connector provides the connection point to a PHYTEC supported camera flex cable.

See PHYTEC camera offerings for specifics.

X19

X4

This connector provides a convenient access point to the signals on X18 to aid in debug.

This connector provides a convenient access point to the AM3517 CCDC signals to aid in debug.

JP36

JP23

JP22

JP38

This jumper causes the SYS_CLKOUT2 from the SOM to be connected to nets xSYS_CLKOUT2A or xSYS_CLKOUT2B. Install this jumper in the 1+2 setting to connect

SYS_CLKOUT2 to SYSCLKOUT2A net which connects to the Camera section. Install this jumper in the 2+3 setting to connect SYS_CLKOUT2 to SYSCLKOUT2B net which connects to the Expansion connector.

This jumper controls the Camera as described in phyCAM-P manual.

This jumper controls the Camera as described in phyCAM-P manual.

JP18

This jumper is provided to tristate all the outputs of all the Camera interface level translator

U13. Install this jumper in the 1+2 setting to allow the AM3517 to control the output enable of

U13. Install this jumper in the 2+3 to continuously enable the output from U13. Remove this jumper completely to disable the outputs of U13

This jumper is provided to disconnect power from the VCC_CAM rail.

© PHYTEC America LLC 2012 84

Part II, Chapter 33: User Buttons

33 User Buttons

L-761e_2

Fig. 33-1. User Buttons and Jumpers

Four user buttons are provided for development purposes.

Figure 33-1 shows the location of the user

buttons and associated configuration jumpers. The configuration jumpers allow disconnection of the button outputs from the processor GPIOs signals.

Below is a detailed list of the user buttons and configuration jumpers associated with them.

S4 User button 1 (BTN1). Pressing this button generates a debounced, active, low signal to the processor. Holding this button will keep the output to ETK_D10 held low. Releasing this button will keep the output to ETK_D10 held high.

S5

S6

User button 2 (BTN2). Pressing this button generates a debounced, active, low signal to the processor. Holding this button will keep the output to ETK_D11 held low. Releasing this button will keep the output to ETK_D11 held high.

User button 3 (BTN3). Pressing this button generates a debounced, active, low signal to the processor. Holding this button will keep the output to ETK_D12 held low. Releasing this button will keep the output to ETK_D12 held high.

S7 User button 4 (BTN4). Pressing this button generates a debounced, active, low signal to the processor. Holding this button will keep the output to ETK_D13 held low. Releasing this button will keep the output to ETK_D13 held high.

© PHYTEC America LLC 2012 85

Part II, Chapter 33: User Buttons

JP7

JP5

JP6

JP8

L-761e_2

Connects the output of BTN1 (S7) to processor signal ETK_D10. By default this jumper is

CLOSED, connecting BTN1 to ETK_D10. OPEN this jumper if ETK_D10 is needed for external use.

Connects the output of BTN2 (S6) to processor signal ETK_D11. By default this jumper is

CLOSED, connecting BTN1 to ETK_D11. OPEN this jumper if ETK_D11 is needed for external use.

Connects the output of BTN3 (S5) to processor signal ETK_D12. By default this jumper is

CLOSED, connecting BTN1 to ETK_D12. OPEN this jumper if ETK_D12 is needed for external use.

Connects the output of BTN4 (S4) to processor signal ETK_D13. By default this jumper is

CLOSED, connecting BTN1 to ETK_D13. OPEN this jumper if ETK_D13 is needed for external use.

© PHYTEC America LLC 2012 86

Part II, Chapter 34: User LEDs

34 User LEDs

L-761e_2

Fig. 34-1. User LEDs and Jumpers

Three user LEDs are provided for development purposes.

Figure 34-1

shows the location of the User

LEDs.

Below is a detailed list of the user LEDs.

D29

D27

D30

Green User LED 1. Drive processor signal MCBSP4_CLKX high to turn this LED on and low to turn this LED off.

Green User LED 2. Drive processor signal MCBSP4_DR high to turn this LED on and low to turn this LED off.

Green User LED 3. Drive processor signal MCBSP4_DX high to turn this LED on and low to turn this LED off.

© PHYTEC America LLC 2012 87

Part II, Chapter 35: Boot Mode Selection

35 Boot Mode Selection

L-761e_2

Fig. 35-1. Boot Mode Selection Connectors and Jumpers

The boot mode switches are provided to configure the boot mode after a reset. By default the boot mode switches are all open, configuring the phyCORE-AM3517 SOM for its default setting of 0b01100 (see

AM3517 TRM for definition). In the default mode, the following boot sequence NAND,EMAC,USB,MMC1 is followed by the AM3517. The AM3517 will boot from the first device which has a "valid" image to boot from.

Alternatively S1, S2, and S3 can be set for other boot sequences. Two switches are provided for each

SYS_BOOT signal on the Carrier Board, one to pull the signal high and one to tie it low.

Fig. 35-2. Boot Switches - Default Settings

© PHYTEC America LLC 2012 88

Part II, Chapter 35: Boot Mode Selection L-761e_2

Table 35-1. Boot Selection Switches and Descriptions

Switch-

Position

S1-1 / S1-2

Condition Description

S1-3 / S1-4

S2-1 / S2-2

S2-3 / S2-4

S3-1 / S3-2

S3-3 / S3-4

Open/Open

Closed/Open

Open/Closed

Closed/Closed

Open/Open

Closed/Open

Open/Closed

Closed/Closed

Open/Open

Closed/Open

Open/Closed

Closed/Closed

Open/Open

Closed/Open

Open/Closed

Closed/Closed

Open/Open

Closed/Open

Open/Closed

Closed/Closed

Open/Open

Closed/Open

Open/Closed

Closed/Closed

SYS_BOOT5 setting determined by SOM default

SYS_BOOT5 is pulled high

SYS_BOOT5 is held low

SYS_BOOT5 is held low

SYS_BOOT4 setting determined by SOM default

SYS_BOOT4 is pulled high

SYS_BOOT4 is held low

SYS_BOOT4 is held low

SYS_BOOT3 setting determined by SOM default

SYS_BOOT3 is pulled high

SYS_BOOT3 is held low

SYS_BOOT3 is held low

SYS_BOOT2 setting determined by SOM default

SYS_BOOT2 is pulled high

SYS_BOOT2 is held low

SYS_BOOT2 is held low

SYS_BOOT1 setting determined by SOM default

SYS_BOOT1 is pulled high

SYS_BOOT1 is held low

SYS_BOOT1 is held low

SYS_BOOT0 setting determined by SOM default

SYS_BOOT0 is pulled high

SYS_BOOT0 is held low

SYS_BOOT0 is held low

Refer to Table 35-2

for each of the possible boot configurations supported by the phyCORE-AM3517 SOM and Carrier Board switches.

Table 35-2. Boot Order Switch Configurations

Boot Order Switch Configuration

First

NAND

MMC2

Second Third

EMAC

EMAC

MMC2 USB

MMC1 USB

USB

USB

Forth

MMC1

S8 1-4

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

S9 1-4 S10 1-4

(off,on,off,on) (off,on,on,off)

(off,on,off,on) (on,off,on,off)

(off,on,on,off) (off,on,on,off)

(off,on,on,off) (on,off,off,on)

© PHYTEC America LLC 2012 89

Part II, Chapter 35: Boot Mode Selection L-761e_2

Table 35-2. Boot Order Switch Configurations

Boot Order Switch Configuration

First

XIP USB

XDOC USB

NAND USB

SPI UART

EMAC USB

EMAC USB

USB

USB

MMC2

MMC1

EMAC USB

EMAC USB

EMAC USB

EMAC USB

EMAC USB

EMAC USB

USB

USB

UART

UART

USB

USB

UART

UART

USB UART

UART XIP

XIP EMAC

XDOC EMAC

MMC2 EMAC

XIP EMAC

XDOC EMAC

NAND EMAC

XIP USB

XDOC USB

NAND USB

MMC2 USB

MMC1 USB

XIP UART

XDOC UART

NAND UART

MMC2 UART

MMC1 UART

Second Third

USB

USB

USB

USB

USB

USB

UART

UART

UART

UART

UART

NAND

MMC1

XIP

XDOC

MMC2

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

Forth

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC1

MMC2

XIP

XDOC

NAND

XIP

XDOC

NAND

MMC2

S8 1-4

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,off,on)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,off,on)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

(off,on,on,off)

S9 1-4 S10 1-4

(off,on,on,off) (on,off,on,off)

(on,off,off,on) (off,on,off,on)

(on,off,off,on) (off,on,on,off)

(on,off,off,on) (on,off,off,on)

(on,off,off,on) (on,off,on,off)

(on,off,on,off) (off,on,off,on)

(on,off,on,off) (off,on,on,off)

(on,off,on,off) (on,off,off,on)

(on,off,on,off) (on,off,on,off)

(off,on,off,on) (off,on,on,off)

(off,on,off,on) (on,off,off,on)

(off,on,off,on) (on,off,on,off)

(off,on,on,off) (off,on,off,on)

(off,on,on,off) (off,on,on,off)

(off,on,on,off) (on,off,on,off)

(on,off,off,on) (off,on,off,on)

(on,off,off,on) (off,on,on,off)

(on,off,off,on) (on,off,off,on)

(on,off,off,on) (on,off,on,off)

(on,off,on,off) (off,on,off,on)

(off,on,off,on) (off,on,on,off)

(off,on,off,on) (on,off,on,off)

(off,on,on,off) (off,on,on,off)

(off,on,on,off) (on,off,off,on)

(off,on,on,off) (on,off,on,off)

(on,off,off,on) (off,on,off,on)

(on,off,off,on) (off,on,on,off)

(on,off,off,on) (on,off,off,on)

(on,off,off,on) (on,off,on,off)

(on,off,on,off) (off,on,off,on)

(on,off,on,off) (off,on,on,off)

(on,off,on,off) (on,off,off,on)

(on,off,on,off) (on,off,on,off)

(off,on,off,on) (off,on,on,off)

(off,on,off,on) (on,off,off,on)

(off,on,off,on) (on,off,on,off)

© PHYTEC America LLC 2012 90

Part II, Chapter 35: Boot Mode Selection L-761e_2

Table 35-2. Boot Order Switch Configurations

Boot Order Switch Configuration

First Second Third

UART XDOC

UART NAND

UART MMC2

UART MMC1

USB

USB

XIP

XDOC

USB NAND

UART SPI

Forth S8 1-4

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

(on,off,on,off)

S9 1-4 S10 1-4

(off,on,on,off) (off,on,off,on)

(off,on,on,off) (off,on,on,off)

(off,on,on,off) (on,off,on,off)

(on,off,off,on) (off,on,off,on)

(on,off,off,on) (off,on,on,off)

(on,off,off,on) (on,off,off,on)

(on,off,off,on) (on,off,on,off)

(on,off,on,off) (off,on,off,on)

© PHYTEC America LLC 2012 91

Part II, Chapter 36: System Reset Button

36 System Reset Button

L-761e_2

Fig. 36-1. System Reset Button

A system reset button is provided to reset the processor and its peripherals.

Figure 36-1

shows the position of the reset button on the Carrier Board.

Momentarily pressing button S3 will generate a system reset.

Refer to Table 35-2

for each of the possible boot configurations supported by the phyCORE-AM3517 SOM and Carrier Board switches.

© PHYTEC America LLC 2012 92

L-761e_2

Part III:

Part III: PCM-988/GPIO Expansion Board

Part 3 of this three part manual provides detailed information on the GPIO Expansion Board and how it enables easy access to most phyCORE-AM3517 SOM signals.

The information in the following chapters is applicable to the 1190.2 PCB revision of the GPIO Expansion

Board.

© PHYTEC America LLC 2012 93

Part III, Chapter 37: Introduction

37 Introduction

L-761e_2

Fig. 37-1. PCM-988/GPIO Expansion Board and Patch Field

The optional PCM-988/GPIO Expansion Board add-on provides an easy means of accessing the phyCORE-AM3517 SOM signals in addition to Carrier Board generated signals via a 2.54mm/0.1in spaced patch field. The Expansion Board also provides an empty prototyping area for soldering additional test circuits to interface the phyCORE-AM3517 SOM.

The Expansion Board interfaces the SOM and Carrier Board via the Carrier Board expansion bus connector X14. Nearly all signals from the phyCORE-AM3517 extend in a strict 1:1 assignment to the

Expansion Bus connector. These signals, in turn, are routed in a similar manner to the patch field on the

Expansion Board.

A two-dimensional numbering matrix, similar to the one used for the pin layout of the phyCORE-Connector, is provided to identify signals on the Carrier Board Expansion Bus connector X14 and the Expansion

Board patch field. See

Figure 26-1 for the pin numbering on the Carrier Board expansion bus connector

© PHYTEC America LLC 2012 94

Part III, Chapter 37: Introduction L-714e_1

X14. See

Figure 37-1 for the pin numbering on the Expansion Board patch field (

red box ). The patch field pin numbering is composed of a row number and a column letter: e.g. 24C. Patch field rows extend from 1 to 54 while columns extend from A to F.

Select phyCORE-AM3517 signals have been removed from the GPIO expansion connector for signal integrity reasons.

Table 37-1 lists the signal groups which have not been routed from the phyCORE-

AM3517 Molex connector to the GPIO expansion connector and also provides a reference to where the signals can be located on the Carrier Board.

Table 37-1. GPIO Expansion Connector - Signals Removed

Signal Group

CCDC

MMC2

TV OUT

JTAG

ENET

MMC1

MCBSP2

DSS

LVDS LCD

USB 0 & 1

MCBSP1

Routed To

X4, X19, X18

X7

X16

X13

None (highly encoded)

X3

JP12, JP15, JP16, JP17

Resistor networks at the output of CPLD

X12 (highly encoded)

X1, X2 (highly encoded)

X7

Chapter

23

28

28

25

32

28

31

21

25

24

28

The following chapters and tables arranged in functional groups, show the relationship between the phyCORE-AM3517 signal, the location on the GPIO expansion bus connector, and where to find the associated signal on the Expansion Board patch field. Please note that because there are a number of multiplexed pins on the AM3517 processor, a particular pin may fall in multiple groups, and hence will be repeated in several tables.

© PHYTEC America LLC 2012 95

Part III, Chapter 38: System Signal Mapping L-761e_2

38 System Signal Mapping

Table 38-1

provides signal mapping for the SOM system signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 38-1. System Signal Mapping

Signal

/RESET xSYS_NRESWARM xSYS_CLKOUT1

SYS_BOOT6

SYS_BOOT4

SYS_BOOT3

SYS_NIRQ

/RESIN

SYS_CLKREQ xSYS_CLKOUT2

SYS_BOOT5

SYS_BOOT2

SYS_BOOT1

SYS_BOOT0

SOM

11D

12D

13D

15D

16D

17D

8C

9C

10C

11C

13C

14C

8D

10D

Expansion Bus Patch Field

11D

12D

13D

15D

16D

17D

8C

9C

10C

11C

13C

14C

8D

10D

4A

12D

13D

5B

6A

6C

4F

5C

3A

3F

3E

3B

3D

4E

© PHYTEC America LLC 2012 96

Part III, Chapter 39: GPMC Signal Mapping L-761e_2

39 GPMC Signal Mapping

Table 39-1 provides signal mapping for the SOM memory bus signals for connection of external memory

mapped devices.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 39-1. GPMC Signal Mapping

Signal

GPMC_NCS7

GPMC_NCS3

GPMC_NCS2

GPMC_NCS1

GPMC_NWE

GPMC_NBE0_CLE

GPMC_NBE1

GPMC_WAIT0

GPMC_WAIT2

GPMC_A9

GPMC_A8

GPMC_A7

GPMC_A4

GPMC_A1

GPMC_D15

GPMC_D14

GPMC_D11

GPMC_D8

GPMC_D7

GPMC_D6

GPMC_D3

GPMC_D0

GPMC_NCS6

GPMC_NCS5

GPMC_NCS4

GPMC_NWP

GPMC_NOE xGPMC_NADV_ALE

GPMC_WAIT1

SOM

21A

23A

24A

25A

26A

28A

1B

2B

3B

6B

7B

8B

10B

11A

13A

14A

15A

16A

18A

19A

20A

1A

3A

4A

5A

6A

8A

9A

10A

Expansion Bus Patch Field

21A

23A

24A

25A

26A

28A

1B

2B

3B

6B

7B

8B

10B

11A

13A

14A

15A

16A

18A

19A

20A

1A

3A

4A

5A

6A

8A

9A

10A

34D

35E

35D

35F

36E

37A

28C

28E

28F

29F

30A

30B

31A

31E

32A

32E

32B

33A

33B

34B

34E

28A

28B

29A

29E

29D

30E

30D

30F

© PHYTEC America LLC 2012 97

Part III, Chapter 39: GPMC Signal Mapping

Table 39-1. GPMC Signal Mapping

Signal

GPMC_WAIT3 xGPMC_CLK

GPMC_A10

GPMC_A6

GPMC_A5

GPMC_A3

GPMC_A2

GPMC_D13

GPMC_D12

GPMC_D10

GPMC_D9

GPMC_D5

GPMC_D4

GPMC_D2

GPMC_D1

SOM

21B

22B

23B

25B

26B

27B

28B

11B

12B

13B

15B

16B

17B

18B

20B

Expansion Bus Patch Field

21B

22B

23B

25B

26B

27B

28B

11B

12B

13B

15B

16B

17B

18B

20B

34F

35A

35B

36A

36B

36F

37C

31B

31F

32C

32F

33C

33E

33F

34B

L-761e_2

© PHYTEC America LLC 2012 98

Part III, Chapter 40: UART Signal Mapping L-761e_2

40 UART Signal Mapping

Table 40-1

provides signal mapping for the SOM UART signals. All signals that end in “RS232” are at RS-

232 levels. All signals that do not end in “RS232” are at TTL levels.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 40-1. UART Signal Mapping

Signal

UART1_RTS

UART1_CTS

UART1_RX

UART1_TX

UART3_TX_RS232

UART3_RX_RS232

UART2_CTS

UART2_RTS

UART2_TX

UART2_RX

SOM

63B

65B

15C

16C

40C

41C

43C

44C

45C

46C

Expansion Bus

63B

65B

15C

16C

40C

41C

43C

44C

45C

46C

Patch Field

48F

49B

5E

5F

13D

14A

14F

15C

15E

15F

© PHYTEC America LLC 2012 99

Part III, Chapter 41: I²C Signal Mapping L-761e_2

41 I²C Signal Mapping

Table 41-1

provides signal mapping for the SOM I²C signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 41-1. I²C Signal Mapping

Signal

I2C2_SDA

I2C2_SCL

I2C1_SDA

I2C1_SCL

I2C3_SCL

I2C3_SDA

SOM

50C

51C

53C

54C

61B

62B

Expansion

Bus

50C

51C

53C

54C

61B

62B

Patch Field

17A

17B

18A

18B

48C

48E

© PHYTEC America LLC 2012 100

Part III, Chapter 42: GPIO Signal Mapping L-761e_2

42 GPIO Signal Mapping

Table 42-1

provides signal mapping for the SOM GPI, GPO, and GPIO signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 42-1. GPIO Signal Mapping

Signal

ETK_D15

ETK_D14

ETK_D13

ETK_D10

ETK_D12

ETK_D11

SOM

43A

44A

45A

46A

45B

46B

Expansion

Bus

43A

44A

45A

46A

45B

46B

Patch Field

42A

42E

42B

43A

42F

43C

© PHYTEC America LLC 2012 101

Part III, Chapter 43: USB Signal Mapping L-761e_2

43 USB Signal Mapping

Table 43-1

provides signal mapping for the SOM USB signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 43-1. USB Signal Mapping

Signal

HSUSB1_DATA3

HSUSB1_DATA6

HSUSB1_DATA5

HSUSB1_DATA2

HSUSB1_STP xHSUSB1_CLK

HSUSB1_NXT

HSUSB1_DIR

HSUSB1_DATA4

HSUSB1_DATA7

HSUSB1_DATA1

HSUSB1_DATA0

SOM

48A

49A

50A

51A

53A

54A

47B

48B

50B

51B

52B

53B

Expansion

Bus

48A

49A

50A

51A

53A

54A

47B

48B

50B

51B

52B

53B

Patch Field

43B

44A

44E

44D

45E

45D

43E

43F

44B

44F

45A

45B

© PHYTEC America LLC 2012 102

Part III, Chapter 44: CAN Signal Mapping L-761e_2

44 CAN Signal Mapping

Table 44-1

provides signal mapping for the SOM CAN signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 44-1. CAN Signal Mapping

Signal

HECC1_TXD

HECC1_RXD

SOM

48C

49C

Expansion

Bus

48C

49C

Patch Field

16E

16F

© PHYTEC America LLC 2012 103

Part III, Chapter 45: Ethernet Signal Mapping L-761e_2

45 Ethernet Signal Mapping

Table 45-1

provides signal mapping for the SOM Ethernet signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 45-1. Ethernet Signal Mapping

Signal

RMII_MDIO_CLK

SOM

RMII_MDIO_DATA 39A

RMII_RXD1

RMII_RXER

RMII_TXD0

RMII_TXEN

38A

40A

41A

RMII_50MHZ_CLK 37B

RMII_CRS_DV 38B

RMII_RXD0

RMII_TXD1

40B

41B

42B

43B

Expansion

Bus

38A

39A

40A

41A

37B

38B

40B

41B

42B

43B

Patch Field

40E

40D

40F

41E

40A

40B

41A

41B

41F

42C

© PHYTEC America LLC 2012 104

Part III, Chapter 46: HDQ Signal Mapping L-761e_2

46 HDQ Signal Mapping

Table 46-1

provides signal mapping for the SOM HDQ/1-wire signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 46-1. HDQ Signal Mapping

Signal

HDQ_SIO

SOM

18D

Expansion

Bus

18D

Patch Field

6B

© PHYTEC America LLC 2012 105

Part III, Chapter 47: McBSP Signal Mapping L-761e_2

47 McBSP Signal Mapping

Table 47-1

provides signal mapping for the SOM McBSP (Multichannel Buffered Serial Port) signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 47-1. McBSP Signal Mapping

Signal

MCBSP1_FSR

MCBSP1_CLKR

MCBSP_CLKS

MCBSP3_CLKX

MCBSP3_DR

MCBSP3_DX

MCBSP3_FSX

MCBSP4_CLKX

MCBSP4_DR

MCBSP4_DX

MCBSP4_FSX

SOM

36C

38C

39C

70B

71B

72B

73B

70A

71A

73A

74A

Expansion

Bus

36C

38C

39C

70B

71B

72B

73B

70A

71A

73A

74A

Patch Field

12B

13A

13B

51A

51B

51F

52C

50F

51E

52A

52E

© PHYTEC America LLC 2012 106

Part III, Chapter 48: SPI Signal Mapping L-761e_2

48 SPI Signal Mapping

Table 48-1

provides signal mapping for the SOM SPI signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 48-1. SPI Signal Mapping

Signal

MCSPI1_SIMO

MCSPI1_CS1

MCSPI1_CS0 xMCSPI1_CLK

MCSPI1_SOMI

MCSPI1_CS3

MCSPI1_CS2

MCSPI2_CS1

MCSPI2_CS0

MCSPI2_SIMO

MCSPI2_SOMI xMCSPI2_CLK

SOM

30D

31D

32D

28C

29C

30C

31C

61A

63A

64A

65A

66A

Expansion

Bus

30D

31D

32D

28C

29C

30C

31C

61A

63A

64A

65A

66A

Patch Field

10B

11A

11C

9F

10C

10E

10F

48A

48B

49A

49E

49D

© PHYTEC America LLC 2012 107

Part III, Chapter 49: Power Signal Mapping L-761e_2

49 Power Signal Mapping

Table 49-1

provides signal mapping for the SOM power signals.

The Signal column specifies the signal name used on the phyCORE-Connector and throughout the phyCORE-AM3517 schematics. The SOM column specifies the pin number on the phyCORE-Connector on the SOM (see

Chapter 2

). The Expansion Bus column specifies the pin number on the GPIO expansion bus connector (see

Chapter 26 ) on the Carrier Board. The Patch Field column specifies the location of the

signal on the GPIO Expansion Board patch field.

Table 49-1. Power Signal Mapping

Signal

VIN

VIN

VCC_1V8

VCC_1V8

VDDSHV

VDDSHV

GND

SOM

1D

2D

4D

5D

6D

7D

2A, 7A, 12A, 17A, 22A,

27A, 32A, 37A, 42A, 47A,

52A, 57A, 62A, 67A, 72A,

77A, 4B, 9B, 14B, 19B,

24B, 29B, 34B, 39B, 44B,

49B, 54B, 59B, 64B, 69B,

74B, 79B, 7C, 12C, 17C,

22C, 27C, 32C, 37C, 42C,

47C, 52C, 57C, 62C, 67C,

72C, 77C, 3D, 9D, 14D,

19D, 24D, 29D, 34D, 39D,

44D, 49D, 54D, 59D, 64D,

9D, 74D, 79D

Expansion Bus

1D

2D

4D

5D

6D

7D

2A, 7A, 12A, 17A, 22A,

27A, 32A, 37A, 42A, 47A,

52A, 57A, 62A, 67A, 72A,

77A, 4B, 9B, 14B, 19B,

24B, 29B, 34B, 39B, 44B,

49B, 54B, 59B, 64B, 69B,

74B, 79B, 7C, 12C, 17C,

22C, 27C, 32C, 37C, 42C,

47C, 52C, 57C, 62C, 67C,

72C, 77C, 3D, 9D, 14D,

19D, 24D, 29D, 34D, 39D,

44D, 49D, 54D, 59D, 64D,

9D, 74D, 79D

Patch Field

1A, 2C

1A, 2C

2C, 1D

2C, 1D

2D

2F

3C, 4C, 7C, 8C, 9C, 12C,

13C, 14C, 17C, 18C, 19C,

22C, 23C, 24C, 27C, 29C,

30C, 31C, 34C, 35C, 36C,

39C, 40C, 41C, 44C, 45C,

46C, 48C, 49C, 50C, 51C,

54C, 4D, 5D, 6D, 9D, 10D,

11D, 14D, 15D, 16D, 19D,

20D, 21D, 24D, 25D, 26D,

28D, 31D, 32D, 33D, 36D,

37D, 38D, 41D, 42D, 43D,

46D, 47D, 48D, 51D, 52D,

54D

© PHYTEC America LLC 2012 108

Revision History

Revision History

Table 50-1. Revision History

Date

06/06/11

03/20/12

Version Number Changes in this Manual

L-761e_1

L-761e_2

Preliminary release

Figure 2-1 updated

L-761e_2

© PHYTEC America LLC 2012 109

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