Curtiss-Wright / Synergy Microsystems VSS4 Manual

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VMEbus Quad G3/G4
PowerPC Single Board Computer for DSP
USER GUIDE
Revision 4.0
9605 Scranton Road
Suite 700
San Diego, CA 92121-1773
April 29, 2003
3895 N. Business Center Drive
Suite 100
Tucson, AZ 85705-6909
(858) 452-0020 • (858) 452-0060 (FAX)
Web: www.synergymicro.com
99-0062/UG-VSS4-04
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User Guide
Copyright © 1999-2003 Synergy Microsystems, Inc.
This manual is copyrighted under Title 17 US Code of the United States Copyright Law. All rights are reserved by
Synergy Microsystems, Inc. This document may not, in whole or in part, be copied, photocopied, reproduced,
translated, scanned, or reduced to any electronic medium or readable form without the express written consent of
Synergy Microsystems, Inc.
This document contains material of a proprietary nature to Synergy Microsystems, Inc. All manufacturing, use, and
sales rights pertaining to this product are expressly reserved. Distribution of this material does not convey any
license or title under any patent or copyright. It is submitted in strict confidence to provide technical information for
purchasers of this product or for those considering the purchase of the product. Each recipient, by accepting this
document, agrees that its contents will not be disclosed in any manner or any person except to serve this purpose.
Synergy Microsystems, Inc. reserves the right to make changes to the specifications and contents in this document
without prior notification. If in doubt, users are urged to consult Synergy to determine whether any such changes
have been made.
Synergy products are not intended for use in life support systems or other applications where a failure of the
product could result in injury or loss of life. Customers using or selling this product in systems or applications
serving such a function do so at their own risk and agree to fully indemnify Synergy Microsystems, Inc. for any and
all damages arising from improper use.
This product and associated manuals are sold “AS IS” without implied warranty as to their merchantability or
fitness for any particular use. In no event shall Synergy Microsystems, Inc. or anyone involved in the creation,
production, or delivery of this product be liable for any direct, incidental, or consequential damages, such as, but
not limited to, loss of anticipated profits, benefits, use, or to data resulting from the use of this product or
associated manuals or arising out of any breach of warranty. In states that do not allow the exclusion or limitation
of direct, incidental, or consequential damages, this limitation may not apply.
Synergy™, VSS4™, VSS Series™, V4xx Series™, V30 Series™, V20 Series™, EZ-bus™ and P0•PCI™ are
trademarks of Synergy Microsystems, Inc. VMEbus Technology logo is a trademark of VITA.
Synergy wishes to acknowledge that the names of products and companies mentioned in this manual are
trademarks of their respective manufacturers.
PRINTED IN THE USA
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Table of contents
Manual revision summary ............................................................................................... viii
Section 1.
Overview ..................................................................................................... 1
VSS4 features..................................................................................................................................................................................3
Optional PEX3 expansion module..........................................................................................................................4
VSS4 physical configuration .....................................................................................................................................5
Functional block diagram..........................................................................................................................................6
Feature summary .........................................................................................................................................................7
Manual conventions .....................................................................................................................................................................9
Typographical conventions.......................................................................................................................................9
Notes chapter...............................................................................................................................................................9
Bit numbering conventions.................................................................................................................................... 10
Web address/URL .................................................................................................................................................... 10
Manual comments.................................................................................................................................................... 10
Section 2.
Getting Started ............................................................................................11
Minimum system requirements .............................................................................................................................................. 13
Front panel.................................................................................................................................................................................... 17
8-bit user switch ........................................................................................................................................................ 18
Toggle switch............................................................................................................................................................. 19
LEDs.............................................................................................................................................................................. 20
Lamp test feature.................................................................................................................................... 22
Setting up the VSS4 hardware ................................................................................................................................................ 23
Default configuration............................................................................................................................................... 23
Installing jumpers...................................................................................................................................................... 24
Setting the slot number manually (Rev. C or higher).................................................................... 26
Installing a monitor PROM ...................................................................................................................................................... 29
Installing the RGS3 memory module.................................................................................................................................... 33
Installing/upgrading the RGS3 memory module............................................................................................. 35
Memory module securing screws........................................................................................................................ 37
Installing PMC cards .................................................................................................................................................................. 39
VSS4 PMC connectors............................................................................................................................................ 40
Adding additional PMC cards with the PEX3 expansion board ................................................ 40
PMC card securing screws................................................................................................................... 41
Installing a PMC card............................................................................................................................................... 41
Installing the P0 overlay............................................................................................................................................................ 45
Installation notes......................................................................................................................................................................... 51
Slot installation recommendations....................................................................................................................... 51
Bus grant signal problems with Hybricon VME64x backplanes.................................................................. 52
Section 3.
Basic Bus Descriptions..................................................................................53
PowerPC bus ............................................................................................................................................................................... 55
VME64 bus................................................................................................................................................................................... 57
Overview..................................................................................................................................................................... 57
VSS4 VMEbus implementation............................................................................................................................. 58
PCI bus........................................................................................................................................................................................... 61
Introduction................................................................................................................................................................ 61
PMC cards .................................................................................................................................................................. 62
PCI implementation details.................................................................................................................................... 62
PCI configuration.................................................................................................................................... 63
Endian issues, byte swapping.............................................................................................................. 65
PCI standards organization.................................................................................................................................... 66
SCSI bus ........................................................................................................................................................................................ 67
Overview..................................................................................................................................................................... 67
History.......................................................................................................................................................................... 67
SCSI specifications and publications................................................................................................................... 69
Device connections ................................................................................................................................................. 69
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iii
Table of contents
Electrical connections ..............................................................................................................................................72
Physical topology ....................................................................................................................................73
Bus terminations......................................................................................................................................74
Bus communication control...................................................................................................................................74
Data transfer options................................................................................................................................................75
Fast Ethernet interface................................................................................................................................................................77
Ethernet network connections...............................................................................................................................78
Data transmission......................................................................................................................................................79
Ethernet ID or physical address...........................................................................................................80
Avoiding bus contention — CSMA/CD.............................................................................................80
Interchange signals ...................................................................................................................................................81
LED indicators ............................................................................................................................................................82
Section 4.
Programming the PowerPC .......................................................................... 83
PowerPC architecture................................................................................................................................................................85
Introduction ................................................................................................................................................................85
Architecture models .................................................................................................................................................86
Register set..................................................................................................................................................................88
Instruction set overview ..........................................................................................................................................89
PowerPC G4 processor...........................................................................................................................................90
Summary of differences, 750 vs. 7400 Processor..........................................................................91
7410 G4 Processor.................................................................................................................................92
MPC106 PCI bridge/memory controller..............................................................................................................................93
General description..................................................................................................................................................93
PowerPC processor interface ..............................................................................................................94
Secondary (L2) cache interface...........................................................................................................94
Memory interface....................................................................................................................................94
PCI bus interface .....................................................................................................................................94
Power management functions.............................................................................................................95
Programming the MPC106 ....................................................................................................................................95
MPC106 registers......................................................................................................................................................96
Address maps...........................................................................................................................................96
Configuration registers...........................................................................................................................96
Power management configuration registers....................................................................................97
Error handling registers..........................................................................................................................98
Memory interface registers...................................................................................................................98
Processor interface configuration registers......................................................................................99
Alternate OS–Visible parameters registers ......................................................................................99
Emulation support configuration registers........................................................................................99
External configuration registers ...........................................................................................................99
Programming notes, MPC106.............................................................................................................................................. 101
Setting PCI device base address........................................................................................................................ 101
Write posting to ROM Space............................................................................................................................. 102
Address map.............................................................................................................................................................................. 105
CHRP address map................................................................................................................................................ 105
PCI configuration and address ........................................................................................................................... 108
VSS4 address map ................................................................................................................................................. 109
Onboard registers .................................................................................................................................................................... 113
Board information registers................................................................................................................................. 114
Board type and revision register, 0xFFEF_FE00 (RO)................................................................. 114
Special mod and ECO level register, 0xFFEF_FE08 (RO).......................................................... 115
Board family and feature register, 0xFFEF_FE10 (RO)............................................................... 115
L2 cache register, 0xFFEF_FE30 (RO)............................................................................................. 116
Memory register, 0xFFEF_FE38 (RO)..............................................................................................116
Secondary PCI Slot register, 0xFFEF_FE48 (RO).......................................................................... 117
VME64 Slot register, 0xFFEF_FF30 (RO)........................................................................................ 117
Status registers ........................................................................................................................................................ 118
Eight-bit user switch register, 0xFFEF_FD00 (RO)....................................................................... 118
Board status register, 0xFFEF_FE18 (RO)....................................................................................... 119
CPU status register, 0xFFEF_FE20 (RO)......................................................................................... 119
iv
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Table of contents
Control/Mode registers.........................................................................................................................................120
CPU Timebase register, 0xFFEF_FE28 (RW)..................................................................................120
Flash ROM register, 0xFFEF_FE40 (RW).........................................................................................121
Flash Window register, 0xFFEF_FE50 (WO)..................................................................................122
PCI error register, 0xFFEF_FE70 (RO) .............................................................................................123
P0•PCI interrupt assert/pending register, 0xFFEF_FE68 (RW).................................................123
P0•PCI interrupt mask register, 0xFFEF_FE60 (RW)...................................................................124
User LED registers, 0xFFEF_FE80, 0xFFEF_FE88, 0xFFEF_FE90, 0xFFEF_FE98, 0xFFEF_FEA0,
0xFFEF_FEA8, 0xFFEF_FEB0, 0xFFEF_FEB8 (RW).........................................................................124
VME64 SysReset register, 0xFFEF_FF38 (RW)..............................................................................125
Watchdog enable register, 0xFFEF_FF40 (WO)...........................................................................125
Watchdog pet register, 0xFFEF_FF48 (WO) .................................................................................126
Backside L2 cache controller.................................................................................................................................................127
How to use the backside L2 cache ...................................................................................................................128
Mailboxes....................................................................................................................................................................................129
Asynchronous serial interface ...............................................................................................................................................131
Registers ....................................................................................................................................................................131
Serial I/O address map..........................................................................................................................................133
Programmable baud rate generator..................................................................................................................134
Serial interface interrupts......................................................................................................................................135
Serial interface connector ....................................................................................................................................136
Clock calendar...........................................................................................................................................................................137
Non-volatile 128K x 8 SRAM ................................................................................................................................................143
NVRAM space allocation.....................................................................................................................................144
Boot Flash ROM/DIP EPROM..............................................................................................................................................145
Boot options.............................................................................................................................................................146
DIP EPROM use......................................................................................................................................................147
EPROM type configuration................................................................................................................147
Boot Flash use..........................................................................................................................................................148
Block organization................................................................................................................................149
Writing and erasing..............................................................................................................................149
Additional write protection of Boot Flash......................................................................................150
Additional Flash memory information.............................................................................................151
User Flash memory ..................................................................................................................................................................153
Introduction..............................................................................................................................................................153
Block organization..................................................................................................................................................154
Bank selection..........................................................................................................................................................154
Writing and erasing................................................................................................................................................156
Additional Flash memory information...............................................................................................................156
Section 5.
Reset ........................................................................................................157
Reset information......................................................................................................................................................................159
General description................................................................................................................................................159
PCI reset..................................................................................................................................................160
Hard reset sources .................................................................................................................................................160
Power monitor.......................................................................................................................................161
Front panel reset switch......................................................................................................................161
External VME SysReset........................................................................................................................161
Watchdog timer....................................................................................................................................162
Universe II software reset...................................................................................................................163
Soft reset ...................................................................................................................................................................163
Section 6.
MPIC Interrupt Controller ..........................................................................165
General description..................................................................................................................................................................167
MPIC registers ...........................................................................................................................................................................169
MPIC base address.................................................................................................................................................169
Global registers .......................................................................................................................................................170
Feature reporting register...................................................................................................................171
Global configuration registers...........................................................................................................171
Vendor identification register............................................................................................................172
Processor init register ..........................................................................................................................172
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v
Table of contents
IPI vector/priority registers ................................................................................................................ 173
Spurious vector register...................................................................................................................... 174
Global Timer registers......................................................................................................................... 174
Interrupt source configuration registers........................................................................................................... 177
Interrupt Source Vector/Priority registers .....................................................................................178
Interrupt Source Destination register ............................................................................................. 179
Per processor registers.......................................................................................................................................... 179
Interprocessor Interrupt Dispatch registers................................................................................... 180
Current Task Priority register ............................................................................................................ 181
Interrupt Acknowlege registers ........................................................................................................ 181
End-of-interrupt registers..................................................................................................................... 182
Section 7.
PCI-VME64 Bridge (Universe II).................................................................. 183
Introduction to Universe II .................................................................................................................................................... 185
Universe II register reference................................................................................................................................................ 189
Overview.................................................................................................................................................................. 189
Register access........................................................................................................................................................ 189
Universe II base address .................................................................................................................... 189
Register map............................................................................................................................................................ 190
Improving VME performance ............................................................................................................................................... 195
Universe II specific (U2SPEC) register.............................................................................................................. 195
U2SPEC adjustable VME timing parameters .................................................................................................. 196
U2SPEC register bit assignments..................................................................................................... 197
Programming notes, Universe II........................................................................................................................................... 199
Writing to non-existent VME locations ............................................................................................................ 199
Slave image programming................................................................................................................................... 199
Section 8.
SCSI/Ethernet Controller............................................................................ 201
General description................................................................................................................................................................. 203
SYM53C885 registers ............................................................................................................................................................. 205
SCSI registers........................................................................................................................................................... 206
PCI configuration.................................................................................................................................. 206
Operating registers .............................................................................................................................. 207
Ethernet registers.................................................................................................................................................... 209
PCI configuration.................................................................................................................................. 209
Operating registers .............................................................................................................................. 210
Programming notes, SYM53C885....................................................................................................................................... 213
SCSI prematurely surrendering PCI bus........................................................................................................... 213
Section 9.
PCI-PCI Bridge Interface ............................................................................ 215
General description................................................................................................................................................................. 217
Registers...................................................................................................................................................................................... 219
Configuration............................................................................................................................................................................. 221
Introduction ............................................................................................................................................................. 221
PCI configuration.................................................................................................................................................... 222
P0•PCI™ configuration........................................................................................................................................ 222
Software support, P0•PCI™.................................................................................................................................................. 223
Section 10. Warranties & Service ................................................................................. 225
Warranty terms & options ..................................................................................................................................................... 227
Customer service...................................................................................................................................................................... 229
vi
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Table of contents
Appendix A, Connectors & Cables...................................................................................231
VMEbus connectors (P1 & P2) .............................................................................................................................................233
PMC connectors (P11–P15)..................................................................................................................................................237
P0•PCI bus connector (P0)...................................................................................................................................................245
Memory module connectors (PM1 & PM2).....................................................................................................................249
Wide Ultra SCSI connector (P264)......................................................................................................................................253
Fast Ethernet connector (P240)............................................................................................................................................255
Asynchronous serial connector (P346) ..............................................................................................................................257
Serial I/O cabling......................................................................................................................................................................259
Appendix B, Specifications .............................................................................................263
Board layout.............................................................................................................................................................264
Appendix C, Board revision summary..............................................................................267
Appendix D, PEX3 PMC expansion option .......................................................................269
Features .....................................................................................................................................................................269
Block diagram........................................................................................................................................270
Board layout...........................................................................................................................................271
Front panel layout.................................................................................................................................272
Configuration...........................................................................................................................................................273
Flash write protect................................................................................................................................273
Installation.................................................................................................................................................................274
Installing PMC cards ............................................................................................................................274
PSTK/PSTR adapters ............................................................................................................................274
PMC stacking and P2 I/O routing....................................................................................................278
PMC P2 I/O restriction.......................................................................................................................278
Operation..................................................................................................................................................................280
Address map ..........................................................................................................................................280
PMC PCI interrupts ..............................................................................................................................280
PCI Type 0 configuration and address............................................................................................281
PCI configuration..................................................................................................................................281
PCI 9080 basic set up .........................................................................................................................282
Registers ..................................................................................................................................................283
Board type register, 0xC000_0000 (RO).......................................................................................284
Revision and ECO level register, 0xC000_0004 (RO) ...............................................................284
Flash configuration register, 0xC000_0008 (RO)........................................................................285
DRAM configuration register, 0xC000_000C (RO)....................................................................285
Using PEX3 memory ............................................................................................................................286
PEX3 connector pinouts .......................................................................................................................................287
VMEbus connectors (P1 & P2) .........................................................................................................288
PMC connectors...................................................................................................................................290
Glossary........................................................................................................................295
Index ............................................................................................................................305
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vii
Manual revision summary
Manual revision summary
Revision level
1.0a
Revision date
3/16/99
Section
1.0b
5/28/99
2nd Preliminary Release
1.0c
11/10/99
Pre-GA Release
1.0
3/28/00
GA Release
2.0
2/27/01
All
Section 1
Section 4
Section 7
Appendix C
Appendix D
3.0
6/18/01
All
Section 2/App. B
Section 2
Section 3
Section 4
4.0
4/29/03
All
Section 2/App. B
Section 4
Appendix C
Appendix D
viii
Affected chapter/description
1st Preliminary Release
Cleaned up various items as required.
VSS4 features/Updated User Flash capacity.
User Flash Memory/Updated User Flash capacity.
Added Slave image programming caveat.
Added VSS4 Rev. D and E to revision summary.
Deleted P0•PCI references.
Cleaned up various items as required.
Updated ±12V specification.
Installation notes/Added slot installation recommendations.
PCI bus/Revised PCI bus discussion (configuration).
SCSI bus/Added SCSI-3 info, expanded SCSI types table.
Address Map/Revised address map information.
Cleaned up various items as required.
Added typical power consumption data for 7410/500 MHz
board.
Installing PMC cards/All PEX3 info moved to Appendix D.
Installing a monitor PROM/Revised J902 configuration
jumper diagram to include Boot Flash Write Protect jumper
function (see next item below).
Boot Flash ROM/DIP EPROM/Added info describing J902
jumper settings for Boot Flash Write Enable/Disable
(applicable only to boards that incorporate ECO specifying
this change).
User Flash Memory/Corrected bank address ranges in User
Flash bank selection table.
Added VSS4 Rev. F to revision summary.
Revised PCI 9080 basic setup info. Added info on VxWorks
BSP PEX3 driver. Revised PMC connector pin
assignments. Added info previously in Section 2.
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Overview
1
This section introduces the VSS4 single board computer.
•
VSS4 features
•
Manual conventions
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2
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Section 1: Overview
VSS4 features
VSS4 features
Synergy Microsystems’ VSS4 is a 6U VMEbus Single Board Computer
(SBC) designed for digital signal processing (DSP) applications. The
VSS4 comes bundled with Synergy’s library of 450+ scientific
subroutines (SSSL, Synergy Scientific Subroutine Library) that are handcoded for optimum performance specifically for running on the VSS4.
The SSSL library is compatible with MATLAB® and provided in VxWorks
and PowerPC Linux (with realtime extensions) versions.
The VSS4 SBC is based on quad G3/G4 (750/7400/7410) PowerPC
microprocessors running at up to 533 MHz (7410). (A dual CPU
version of the board is also available.) Each processor is provided with a
performance-boosting 2 MB (or 1 MB for G3) backside L2 cache as
standard. An upgradeable DRAM module provides 32–512 MB of high
performance SDRAM memory. SCSI, Ethernet, a PMC slot, up to 64 MB
of 8-bit User Flash and 128 KB NVRAM give the VSS4 the flexibility to
meet almost any requirement.
Multiprocessing support includes: quad CPUs with shared high
bandwidth DRAM memory, a private mailbox for each CPU, and the
OpenPIC™ interrupt controller.
Onboard peripherals include a Wide Ultra SCSI (8/16-bit wide)
interface, Fast Ethernet (10Base-T/100Base-TX) RJ-45 interface, four RS232D serial ports, and a real time, clock/calendar with four digits for the
year.
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Section 1: Overview
VSS4 features
Quad
PowerPC
CPU Status G3/G4
LEDs
Rear
stiffener
Status LEDs
User LEDs
8-bit
Readable
CPU
Switch SMI/Reset
Switch
Wide Ultra
SCSI
Connector
PMC
Connectors
Mid-board
stiffener
Serial
DIP EPROM
Interface Ethernet
Connector Connector PMC Module Socket
Cutout
VSS4 single board computer for DSP
An industry-standard PMC slot provides optional daughterboard I/O
connection to the PCI bus. The VSS4 also provides Synergy
Microsystems’ P0•PCI™ interface which is a secondary PCI bus
accessed through the P0 connector. P0•PCI™ provides support for
additional PCI I/O expansion and board-to-board communications.
A full line of system monitor, kernel, and operating system software/
firmware is also available from Synergy and leading developers.
Optional PEX3 expansion module
The expansion module option provides the VSS4 with additional singlewidth PMC slots and additional Flash and SDRAM memory. Refer to
Appendix D (page 269) for details on the PEX3 PMC expansion option.
4
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Section 1: Overview
VSS4 features
VSS4 physical configuration
VSS4 has onboard connectors for:
•
Modular memory card
•
PMC I/O card and/or PMC carrier board expansion
•
Secondary PCI (P0•PCI™ interface) via P0 connector
VSS4’s front panel includes:
•
Modular RJ-45 jack for Fast Ethernet
•
Modular RJ-50/RJ-69 jack for quad serial ports (A, B, C and D)
•
Processor SMI & reset switch
•
8 user LEDs
•
8 status LEDs
•
Software-readable 8-bit DIP switch
•
For SCSI option, 68-pin Wide Ultra SCSI connector (singleended)
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6
VSS4 functional block diagram
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PCI–PCI
Bridge
GRACKLE
PowerPC
to
PCI Bridge/
Mem. Ctrlr.
PPC G3/G4
Y
L2 Backside Cache
1MB/2MB
P0•PCI Interface (P0)
OpenPIC
Interrupt
Controller
PPC G3/G4
X
L2 Backside Cache
1MB/2MB
PMC
Slot
PPC G3/G4
Z
L2 Backside Cache
1MB/2MB
PMC
Slot
PMC
Slot
Optional PMC Expander
Memory
1MB
1MB
PMC Slot
DIP
EPROM
Mailboxes
Boot
Flash ROM
32–512MB
PCI-PCI
Bridge
PCI Bus
PowerPC Bus
PPC G3/G4
W
L2 Backside Cache
1MB/2MB
4/8/16/
32/64MB
8-bit User
Flash
Switches/
LEDs
Serial
Ports
(4)
PCI-VME
Bridge
SCSI/
Ethernet
Controller
VMEBus (P1 & P2)
VME Transceivers
128KB
Clk/Cal/
NVRAM
Front Panel
Section 1: Overview
VSS4 features
Functional block diagram
Section 1: Overview
VSS4 features
Feature summary
The VSS4 provides the following list of powerful features and functions:
•
SMP compliant
•
PCI to VME64 bridge (with auto-system controller) rated at
50MB/sec
•
OpenPIC™ compliant — any interrupt source can be routed to
any CPU at any priority
•
Four 32-bit counters can be read at any time as well as generate
interrupts
•
Quad G3 750 PowerPC processors or Quad G4 7410 PowerPC
processors (Rev. C or higher assy.). Dual versions available.
•
2 MB backside L2 cache (1 MB backside L2 cache, Rev. B or
lower assy.)
•
32-512 MB of high performance SDRAM supporting parity
•
1 MB of system boot Flash loadable via a 32-pin JEDEC socket
•
Four RS-232D serial ports up to 115.2Kbps
•
Four 8-bit CPU mailboxes
•
Real time clock/calendar (4-digit year)
•
128 KB of NVRAM
•
4–64 MB 8-bit User Flash memory
•
Fast-20 SCSI (8/16-bit wide)
•
Fast Ethernet 10Base-T/100Base-TX
•
64-bit PMC compliant slot with front panel and rear VME P2 I/O
access
•
Optional 6U expansion board provides up to 3 additional PMC
slots
•
Geographical addressing support (Rev. C or higher assy.)
•
Eight status LEDs, eight user-programmable LEDs, an 8-bit
software-readable switch, one CPU reset/interrupt switch
•
P0•PCI ™ sub-bus interface goes beyond VMEbus bandwidth
limitations by providing an aggregate 266 MB/sec (theoretical
maximum) transfer rate for up to 8 boards (4 pair) in a system
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Section 1: Overview
VSS4 features
8
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Section 1: Overview
Manual conventions
Manual conventions
Typographical conventions
This manual observes the following typographical conventions:
➊
➋
The term PowerPC Series is used in conjunction with information that applies to ALL models of Synergy’s PowerPC-based
SBCs. When differences among models exist, specific model
numbers are used to describe any special features.
In diagrams and descriptions in this manual, signal names followed by a backslash (\) are active low.
Notes chapter
Within this manual, a notes chapter is provided in select sections. Some
or all of the following notes chapters may be found in this manual:
•
Programming notes — deals with programming issues
•
Installation notes — deals with installation issues
•
Operating notes — deals with operating/usage issues
Refer to this special information for any notes or caveats for the device
or topic under discussion.
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9
Section 1: Overview
Manual conventions
Bit numbering conventions
To avoid confusion, be aware that there are two bit numbering
conventions.
The PowerPC architecture was invented by IBM, who number their bits
with 0 on the left (most-significant bit or MSB) and 31 on the right
(least-significant bit or LSB). This zero-on-the-left numbering convention
is reflected in the IBM PowerPC documentation.
PCI bus and VMEbus both number the bits with 0 on the right (LSB)
and 31 on the left (MSB). This zero-on-the-right numbering convention
is used in the bit descriptions contained in this manual.
Bit numbering conventions
Binary bits of data
Zero-on-the-right
Zero-on-the-left
1
7
0
0
6
1
1
5
2
1
4
3
0
3
4
0
2
5
1
1
6
0
0
7
Web address/URL
Note that any web page address (URL) is subject to change without
notice. If the listed web page address in the manual doesn’t work, do a
site search or use your favorite search engine to find the information
you need. Over time, some information may no longer be posted
online. In this case, contact the manufacturer directly using the contact
information usually provided in the home page.
Manual comments
Synergy invites your comments or corrections to this manual. Email
comments/corrections to:
[email protected]
10
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Getting Started
2
This section provides configuration, setup and general information for
the VSS4 SBC.
•
Minimum system requirements
•
Front panel
•
Setting up the VSS4 hardware
•
Installing a monitor PROM
•
Installing the RGS3 memory module
•
Installing PMC cards
•
Installing the P0 overlay
•
Installation notes
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12
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Section 2: Getting Started
Minimum system requirements
Minimum system requirements
The following system components are required to install and test VSS4
boards:
•
6U VMEbus-compatible card cage with VME64x-compatible P1
and P2 backplanes installed (with P0 connector) — A card cage
with forced air cooling is required:
• minimum, 400 LFM
• recommended, 600 LFM
e
Not
Note the recommended airflow rating in
linear ft./min. This is the rate of air
flowing over the component side of the
SBC in its chassis and not the air moved
through the chassis (CFM rating). LFM
can be measured using a hand-held
anemometer such as the Kestrel 1000
Pocket Wind Meter by NielsenKellerman (www.nkelectronics.com).
VSS4 boards feature state-of-the-art,
high-speed, transfers across the VME-bus
that in some cases may approach the
maximum VME specifications for transfer
speeds. To support these transfers, the
underlying connectors, circuitry, and
printed circuit boards used in the VME
card cage must be constructed of highquality materials that are fully compliant
with VME specifications.
For example, VME card cages containing
10-layer, PCB boards are normally re-
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13
Section 2: Getting Started
Minimum system requirements
quired to support high-speed VME transfers. Older style card cages containing
6-layer boards may have some difficulty
conducting these signals without generating excessive noise.
Pin row B of the P2 backplane is
defined by VMEbus specifications and
is bussed across the entire backplane.
Pin rows A and C are user configured
and, if connected at all, are normally
connected to adjacent slots via
wirewrap or special cables.
Because the P2 and P0 pinout may vary
between backplanes or even slots in the
same backplane, DO NOT INSTALL the
VSS4 into a system
slot whose
backplane is not compatible with the
VSS4’s P2 and P0 pinout. Failure to
observe this warning can cause the
complete destruction of many on-board
components and also voids the product
warranty.
The VSS4 pinout meets standard VME
specifications for row B, but rows A and
C (and for 5-row boards, the majority of
pins on row D and half the pins on row
Z) will vary according to the PMC card
installed. Synergy PMC card pinouts are
shown in the associated manual. If no
PMC card is present, P2 backplane rows
A and C (and D & Z) are defined as noconnects.
For a complete list of the VSS4 P2
assignments, see VMEbus connectors in
Appendix A, page 233.
14
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Section 2: Getting Started
Minimum system requirements
•
Power supply — VSS4 boards typically require the following
power supply voltage levels (with no PMC installed):
G4 7400/466 MHz
G4 7400/433 MHz
G4 7400/366 MHz
G4 7410/500 MHz
+5.0V +/-5%, 15.7 A typical @ 5.00V (78.5 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
+5.0V +/-5%, 11.0 A typical @ 5.00V (55 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
+5.0V +/-5%, 9.5 A typical @ 5.00V (47.5 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
+5.0V +/-5%, 8.37 A typical @ 5.00V (41.9 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
Ensure that the power supply is capable
of meeting the above requirements plus
the requirements of any additional
boards in the system. An extra 20%
margin of current capacity should be
factored in for safety.
•
One modular quad serial I/O port adapter cable/assembly —
The VSS4 serial ports share a 10-pin modular RJ-50/RJ-69 front
panel connector. The CRJ4 serial interface adapter, available
from Synergy, allows access to all four serial ports. Refer to
Serial I/O cabling in Appendix A, page 259, for more
information.
•
RS-232 compatible video display terminal or a PC with a COM
port and terminal emulator software
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Section 2: Getting Started
Minimum system requirements
16
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Section 2: Getting Started
Front panel
Front panel
The drawing below shows the layout of the connectors, controls, and
indicators on the VSS4 front panel.
IL
E
I
A C M C
Sts F S V P
Status LEDs
Usr
User LEDs (0-7)
Usr
7 6 5 4
3 2 1 0
X
0
8-bit User
Switch
CPU
Y
CPU Halt/Run LEDs
Z
W
7
Rst
CPU SMI/Reset Switch
SCSI
Wide Ultra SCSI
Front Panel Connector
SMI
Serial I/O A, B, C & D,
RJ-50/RJ-69 Jack
Serial
A
/
B
/
C
/
D
Fast Ethernet, RJ-45 Jack
Ethernet
PMC
PMC Module Front Panel
Cutout (Filler Panel)
microsystems
99-0149
VSS4 front panel
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Section 2: Getting Started
Front panel
8-bit user switch
The eight position switch on the front panel of the VSS4 provides an 8bit software-readable switch.
Readable switches can be very useful in target applications where
applications programs can read the switch to discover what their
function should be, the nature of their peripherals, etc.
The CPU reads the switch setting by performing a byte-wide read from
the 8-bit User Switch register at memory location 0xFFEF_FD00. The
figure below shows the register bits corresponding to each of the eight
switch positions.
UP
(with board
in card cage)
☞
Push left
for Logic 0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Position switch
as required
☞
Push right
for Logic 1
91-0011
8-bit user switch polarity
Numbering may appear on the switch
component itself that conflicts with the
numbering shown above. Ignore all
numbering schemes except what is
shown above and on the Quick
Reference Card.
18
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Section 2: Getting Started
Front panel
Toggle switch
The VSS4 is provided with a toggle switch for RESET and SMI interrupt:
RESET
Pushing the switch to the right asserts a boardlevel RESET that:
•
•
•
SMI
Resets the CPUs.
Resets all on-board components that have
such a function and clears all on-board
control registers.
Asserts a VME RESET if the board is serving as the System Controller.
Pushing the toggle switch to the left asserts an
SMI interrupt to all CPUs on the board.
5 4
7 6
1 0
Usr
3 2
Usr
X
Y
0
CPU
Z
W
SMI
7
FT
h LE
for
set
r Re
Rst
I
hR
Pus
fo
GHT
SMI
Pus
Close-up of RESET and SMI switch
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Section 2: Getting Started
Front panel
LEDs
Shown below are the VSS4 front panel and onboard LEDs that provide
a quick indication of board activity. The following describes the
function of these LEDs.
Usr
User LEDs (0-7)
Yellow
Usr
I
PC
Sts
VM
E
FA
IL
SC
VSS4
Status LEDs
Fail: Red = Fail
SC: Green = System Controller mode
VME: Green = Master, Red = Slave
PCI: Green = PCI, Yellow = PCI Expansion
7 6 5 4
3 2 1 0
X
0
CPU
Y
Z
W
7
SMI
Rst
CPU
Run/Halt LEDs
Red = Halt
Green = Run
Front panel, lower
Fast Ethernet Jack
Ethernet, Link Status LED
Green = Link OK
Ethernet, Link Activity LED
Yellow = Activity
Ethernet, Speed LED
Orange = 100Base-TX
Not Lit = 10Base-T
99-0026
VSS4 LEDs
20
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Section 2: Getting Started
Front panel
The eight User LEDs indicate application events:
0-7
Software-programmable LEDs are controlled by
the User LED registers. They indicate the current
operating mode of the board as defined by the
software currently running.
For more information on the registers that control
these LEDs, refer to the Onboard registers
chapter in Section 4.
The Status LEDs indicate various status items:
LED Label
FAIL
SC
VME
PCI
Indication
Red
When on, indicates a condition that caused the CPU to reset (VMEbus
SysRst\ line or the front panel RESET toggle).
During normal operation, the system boot software clears this condition
shortly after RESET.
Green
When on, indicates System Controller function assumed by board.
Dual-color LED, VMEbus Activity
Green (VME Master)
Red (VME Slave)
Flickers green in response to VME
Flickers red in response to VME
Master activity. When the VMEbus
Slave activity.
interface is idle, the VME LED lights
up green on the last release-onrequest (ROR) VMEbus master to
have used the bus.
Dual-color LED, PCI Bus Activity
Green (PCI Bus)
Yellow (PCI Expansion)
Flickers green in response to PCI
Flickers yellow in response to PCI
bus activity.
expansion (PMC) activity.
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Section 2: Getting Started
Front panel
The CPU LEDs indicate the run status of the CPUs:
LED Label
CPU X
CPU Y
CPU Z
CPU W
Indication
Dual-color LED, CPU-X/Y/Z/W Run Status
Green (Run)
Red (Halt)
Flickers green in response to
Lights red when CPU has halted.
PowerPC bus activity by CPUX/Y/Z/W. If not on, indicates CPU is
not executing bus cycles as it
executes instructions in cache or
waits for an interrupt.
The three LEDs on the VSS4 motherboard indicate Ethernet port status
as follows:
Green
Link OK – lit when 10Base-T/100Base-TX cable is
properly plugged into a functioning Ethernet
network and onboard software has initialized the
Ethernet interface.
Yellow
Link Activity – flickers whenever data is being
received or transmitted. If the VSS4 is connected
to a repeater-type hub instead of a switch-type
hub, this LED may still flicker even when the VSS4
is not transferring data since packets sent over the
network to other nodes will also be sent to the
VSS4.
Orange
Link Speed – lit when operating as 100Base-TX.
LED is OFF when operating as 10Base-T.
Lamp test feature
During board level reset, all LEDs are illuminated to provide a lamp test.
You can confirm proper operation of the LED indicators as you do a
board level reset by observing the LEDs and pushing the CPU reset
switch to the right. Hold switch in this position and wait 2 seconds for
LED illumination.
22
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Section 2: Getting Started
Setting up the VSS4 hardware
Setting up the VSS4 hardware
This chapter describes the general hardware configuration of VSS4
boards. This configuration is done via jumper block J02L.
Additional jumpers are provided on jumper block J902 for EPROM
configuration. Refer to the next chapter on Installing a monitor PROM
for details on EPROM configuration.
Default configuration
The table shown below lists VSS4’s default hardware configuration
before the installation of any jumpers on J02L.
Default hardware conditions
Jumpers (presumes no jumper installed)
J02L
— Boot ROM Enable
— SCSI Termination
— Force VME System Controller
— VME64 Auto System Controller
— User Defined Slot Number *
— Flash Write Protect
* For Rev. C or higher boards only.
Default
Disabled
Enabled
Disabled
Enabled
None
Disabled
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Section 2: Getting Started
Setting up the VSS4 hardware
Installing jumpers
No jumpers need to be set for most applications. However, the J02L
user configuration jumpers let you change the default conditions listed
in the table above if necessary. Note that the jumper shunts used are of
the smaller 2 mm size and not the larger .100" size commonly found on
older SBCs. The jumpers are summarized below.
e
Not
•
•
•
•
•
•
•
•
VSS4 Rev. C or higher boards have
additional jumpers for manual slot
number/geographical address select.
Verify that the board has a monitor EPROM and memory module installed.
Verify/install shunt at J02L 1 & 2 to boot from DIP EPROM.
Install a shunt at J02L 3 & 4 to unterminate the SCSI bus.
Install a shunt at J02L 5 & 6 to force VME System Controller.
Install shunt at J02L 7 & 8 to disable Auto System Controller
function.
Rev. B or lower boards: Install a shunt at J02L 9 & 10 for global
Flash write protection.
Rev. C or higher boards: Install a shunt at J02L 9–20 for manual
slot number configuration.
Rev. C or higher boards: Install a shunt at J02L 21 & 22 for
global Flash write protection.
e
Not
Some boards have an ECO
modification to provide extra write
protection of Boot Flash. See page 150
for more information
The drawing below shows the location and pinout of jumper block
J02L.
24
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Section 2: Getting Started
Setting up the VSS4 hardware
Rev. B or lower
Rev. C or higher
Boot ROM Enable
(Boot Source)
SCSI Termination Disable
System Controller, Manual
System Controller, Auto
Flash Write Protect
1
3
5
7
9
Boot ROM Enable
(Boot Source)
SCSI Termination Disable
System Controller, Manual
System Controller, Auto
Slot ID Jumper Enable
2
4
6
8
10
Geographical Addressing
Jumper Fields
GA4
GA3
GA2
GA1
GA0
Flash Write Protect
1
3
5
7
9
11
13
15
17
19
21
2
4
6
8
10
12
14
16
18
20
22
Configuration
Jumpers, J02L
99-0047a
Configuration jumpers, J02L
Jumper J02L functions
Jumper Pins
1&2
3&4
5&6
7&8
9 & 10 †
Function
For more info, see Section,
Chapter
Section 4, Boot Flash ROM/DIP
EPROM
Boot ROM Enable: When installed, the
board will boot from the DIP EPROM
instead of Boot Flash ROM.
SCSI Termination Disable: When
Section 3, SCSI bus
installed, the on-board SCSI termination is
disabled
VME System Controller: When installed,
Section 3, VME64 bus
the on-board VME system controller
function is active regardless of the VME64
auto-system controller function or the
actual VME slot in which the board is
installed.
VME64 Auto-System Controller Disable:
When installed, the on-board auto-system
controller function is disabled.
Flash Write Protect: When installed, all
Section 4, Onboard registers;
Flash (Boot Flash, User Flash, DIP Flash Section 4, Boot Flash ROM/DIP
EPROM) is protected from writes.
EPROM; Section 4, User Flash
memory
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Section 2: Getting Started
Setting up the VSS4 hardware
Jumper J02L functions (continued)
9 & 10 ††
11 & 12 ††
13 & 14 ††
15 & 16 ††
17 & 18 ††
19 & 20 ††
21 & 22 ††
User Defined Slot Number: When
installed, indicates that the slot number
has been set by the user installing
jumpers in positions 6-10. When not
installed, the slot number is determined
from the geographical address pins on
VME64x P1.
Jumper for GA4, slot number
Jumper for GA3, slot number
Jumper for GA2, slot number
Jumper for GA1, slot number
Jumper for GA0, slot number
Flash Write Protect: When installed, all
Flash (Boot Flash, User Flash, DIP Flash
EPROM) is protected from writes.
See text below.
See Table Below
For Jumper Settings
Section 4, Onboard registers;
Section 4, Boot Flash ROM/DIP
EPROM; Section 4, User Flash
memory
Notes:
† This jumper present on Rev. B or lower boards.
†† This jumper present on Rev. C or higher boards.
Setting the slot number manually (Rev. C or higher)
On a VME64x backplane (5-row connectors), a board can automatically
sense which slot it is plugged into by reading special pins on P1. These
geographical address pins are encoded on the backplane. Boards that
can read these pins present the geographical address in the VME64 Slot
register. These boards also check the geographically addressing parity
and signal its validity in the same register.
In some cases the VSS4 will not be able to read these pins because the
board is configured with 3-row VME connectors or it may be plugged
into an old VME64 backplane (3-row connectors). For these situations,
jumpers on J02L (pins 9–20) are provided to set the board’s slot
number manually.
To set a slot number, install jumpers over the appropriate pair of pins as
shown with a bullet ( ) in the table below. Pins with no jumper installed
are shown with a dash (—). This is a binary encoded scheme with pins
11 & 12 MSB and pins 19 & 20 LSB.
Install the User Defined Slot Number jumper (pins 9 & 10) to let
hardware/software read the user defined slot number from the VME64
Slot register. The value in this register is set by the 5 slot number
jumpers.
Note that user defined slot number jumpers must not be used if both
the board and backplane have 5-row connectors.
26
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Section 2: Getting Started
Setting up the VSS4 hardware
J02L jumper settings for slot number selection
Slot No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pins 11 &12
(GA4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pins 13 & 14
(GA3)
—
—
—
—
—
—
—
Pins 15 & 16
(GA2)
—
—
—
Pins 17 & 18
(GA1)
—
Pins 19 & 20
(GA0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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Section 2: Getting Started
Setting up the VSS4 hardware
28
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Section 2: Getting Started
Installing a monitor PROM
Installing a monitor PROM
The VSS4 comes with one, 32-pin, 8-bit monitor DIP EPROM socket
that accepts any of the following devices†:
•
•
•
•
•
27C010
27C020
27C040
28F020
29C040
1 Mbit (128 KB) DIP EPROM
2 Mbit (256 KB) DIP EPROM
4 Mbit (512 KB) DIP EPROM
2 Mbit (256 KB) Flash DIP EPROM
4 Mbit (512 KB) Flash DIP EPROM
Some boards ship from the factory with the appropriate monitor PROM
already installed. However, a new or updated PROM is easily added or
changed in the field.
The paragraphs below describe a field installation of a new DIP EPROM
and all of the potential configuration changes you may need to make to
the VSS4 CPU board as a result.
e
Not
If the desired monitor PROM is already
present on the VSS4 board or if the
monitor ROM is programmed into Boot
Flash (e.g. VxWorks), proceed to the
next chapter in this section.
† TI brand EPROMs cannot be used. Their requirement for Vcc on unused pins prevents a TI PROM from being used in a general
purpose socket. EPROMs from other manufacturers such as Intel, AMD, etc. work without problem.
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Section 2: Getting Started
Installing a monitor PROM
Materials
To complete this procedure, you will need the following materials:
•
•
•
The desired monitor firmware PROM
A 32-pin, 0.6" wide DIP extractor tool to remove the current
PROM (if necessary)
The manual for the software product on the new EPROM.
Procedural steps
To install a monitor EPROM, complete the following procedure:
➊
Verify proper operation of the motherboard (if replacing an existing monitor PROM) — Before attempting to install a new
EPROM on an existing board, ensure that the motherboard (and
any attached mezzanine cards) are operating properly.
Pin 1
32-pin DIP JEDEC
standard EPROM
VSS4 DIP EPROM socket location
30
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Section 2: Getting Started
Installing a monitor PROM
➋
Power-down and remove the CPU motherboard from the card
cage (if necessary) — Power-down the system and remove the
VSS4 CPU board from the card cage.
Synergy SBCs contain static-sensitive
devices. Make sure you are properly
grounded (by putting on a ground-strap,
touching a system ground such as a
metallic chassis or case, etc.) before
removing and handling the board. Use
an ESD-protected workstation for
module removal and installation work.
➌
Locate the current monitor PROM or DIP socket on the CPU
board and remove the current monitor PROM (if necessary) —
The figure on the previous page shows the location of the DIP
EPROM socket on the VSS4 board.
Use a chip extraction tool to remove
the DIP EPROM from the socket to
avoid damaging parts underneath.
➍
Install the DIP EPROM — Install the DIP EPROM in the socket.
The VSS4 EPROM socket accepts 32-pin DIP EPROM devices.
The figure above shows the orientation of the DIP EPROM after
proper installation (note orientation of notch end).
❺
Install DIP EPROM configuration jumpers (J902) — Place a pair
of jumpers at J902 to configure the board for the device used in
the DIP EPROM socket as shown in the drawing below.
e
Not
Some VSS4 boards include an ECO that
adds a Boot Flash write protect function
to the J902 jumper block, pins 1 and 2.
Refer to the Additional write
protection of Boot Flash discussion in
Section 4 (page 150) for more
information on this jumper.
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Section 2: Getting Started
Installing a monitor PROM
Boot Flash
DIP EPROM/Flash
Device
1
3
5
7
Jumpers Installed on Pins:
27Cxxx EPROM
3 & 5,
4&6
1
3
5
7
2
4
6
8
28F020 Flash (write enabled)
1 & 3,
6&8
1
3
5
7
2
4
6
8
28F020 Flash (write prot.)
6&8
1
3
5
7
2
4
6
8
29C040 Flash
3 & 4,
6&8
1
3
5
7
2
4
6
8
Boot Flash
(write enabled)
1&2
1
3
5
7
2
4
6
8
Boot Flash
(write protected)
None
(1 & 2)
1
3
5
7
2
4
6
8
2
4
6
8
DIP EPROM/Boot Flash
Configuration
Jumpers, J902
99-0047b
DIP EPROM/Boot Flash configuration jumpers, J902
32
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Section 2: Getting Started
Installing the RGS3 memory module
Installing the RGS3 memory
module
VSS4 boards provide on-board SDRAM with the RGS3 memory
module. RGS3 is available in the following sizes:
•
•
•
•
•
32 MB
64 MB
128 MB
256 MB
512 MB
Normally, all VSS4 boards ship from the factory with a memory module
installed. The modular design of the VSS4 DRAM interface, however,
allows for easy DRAM upgrades in the field.
The drawing below shows the location of the RGS3 memory module on
the motherboard.
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Section 2: Getting Started
Installing the RGS3 memory module
RGS3 Memory Module
99-0027
RGS3 memory module location (top view)
This chapter describes field installation of an RGS3 memory module.
e
Not
34
If the desired RGS3 module is already
present on the VSS4 board, proceed to
the next chapter in this section.
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Section 2: Getting Started
Installing the RGS3 memory module
Installing/upgrading the RGS3 memory
module
Perform the following steps to install or upgrade an RGS3 memory
module.
➊
Verify proper operation of motherboard (if replacing an existing
RGS3 memory module) — Before attempting to install a new
RGS3 memory module on a working CPU motherboard,
consider checking that the motherboard (and any attached PMC
cards) are operating properly.
➋
Power-down and remove CPU motherboard from card cage (if
necessary) — Power-down the system and remove the VSS4
CPU board from the card cage.
Synergy SBCs contain static-sensitive
devices. Make sure you are properly
grounded (by putting on a ground-strap,
touching a system ground such as a
metallic chassis or case, etc.) before
removing and handling the board. Use
an ESD-protected workstation for
module removal and installation work.
➌
Remove existing RGS3 memory module from CPU
motherboard (if you are replacing — refer to RGS3 module
installation drawing below for assembly details):
a. Place VSS4/RGS3 assembly face-down, that is with large
circuit board (motherboard) on top, on a flat surface of an
ESD-protected workstation.
b. Remove four M2.5 slot-head screws from rear (solder) side of
VSS4 motherboard. See Location, memory module securing
screws drawing below.
c. Turn VSS4/RGS3 assembly over.
d. Grasp RGS3 sides at connector end (toward SBC front panel)
and gently pull up until the connector comes loose (rocking
back and forth may help).
➍
Install RGS3 module on motherboard — Installation of RGS3
memory module is reverse of removal. Refer to RGS3 module
installation drawing below for assembly details.
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Section 2: Getting Started
Installing the RGS3 memory module
The SBC memory module connector is
fragile. To avoid connector damage,
make sure that module connector is
properly aligned with SBC connector
before fully seating module.
Module connector (below) engages
motherboard's PM1 and PM2 connector
Memory Module,
RGS3 (32-512 MB)
Standoff securing screws
(red paint on head)
DO NOT REMOVE
(4 places)
w
Vie
CPU MOTHERBOARD
A-A
PM2
PM1
4 ea. securing
screws engage
memory module
standoffs.
Memory Module, RGS3 (up to 512MB)
Top Eject
Knob
VME P1
conn.
CPU Motherboard
Screw, M2.5 thread,
6mm, pan head slot
(4 places)
PM1 and PM2
connectors
Top (Processor) End of Motherboard
VIEW A-A, Side View — Memory Module Installation
99-0028
RGS3 module installation
36
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Section 2: Getting Started
Installing the RGS3 memory module
Memory module securing screws
To aid in installation, the location of the memory module securing
screws on the VSS4 is shown in the drawing below.
SBC solder side
Memory module
securing screws
99-0029
Location, memory module securing screws
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Section 2: Getting Started
Installing the RGS3 memory module
38
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Section 2: Getting Started
Installing PMC cards
Installing PMC cards
VSS4’s I/O expansion is provided by PMC (PCI Mezzanine Card) cards.
This chapter describes PMC card installation.
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Section 2: Getting Started
Installing PMC cards
VSS4 PMC connectors
The VSS4 comes with PMC connectors for direct installation of one
PMC card. The drawing below shows the location of a PMC card on
the VSS4 board.
PMC card front panel
(component side)
PMC card
PMC card
Hex standoffs
(component
side)
99-0030
PMC location (top view)
Adding additional PMC cards with the PEX3 expansion
board
The PEX3 PMC expansion option provides VSS4 with up to three
additional PMC slots plus additional SDRAM and Flash memory. Refer
to Appendix D (page 269) for complete PEX3 information.
40
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Section 2: Getting Started
Installing PMC cards
PMC card securing screws
To aid in installation, the location of the PMC card securing screws on
the VSS4 is shown in the drawing below.
SBC solder side
PMC card
securing screws
99-0034
Location, PMC card securing screws
Installing a PMC card
Perform the following steps to install a PMC card.
e
Not
➊
The VSS4 PMC slot accepts 5V VI/O or
5V-tolerant PMCs only.
Power-down and remove SBC from card cage — Power-down
the system and remove the VSS4 from the card cage.
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Section 2: Getting Started
Installing PMC cards
Synergy SBCs contain static-sensitive
devices. Make sure you are properly
grounded (by putting on a ground-strap,
touching a system ground such as a
metallic chassis or case, etc.) before
removing and handling the board. Use
an ESD-protected workstation for
module removal and installation work
42
➋
Remove PMC filler panel from SBC front panel — The filler
panel will be one of two types. The first type simply snaps in
place — remove by pushing from the inside. The second type is
an actual blank PMC front panel — remove 2 ea. 6 mm M2.5 slot
head securing screws from solder side of board to remove (see
PMC card securing screws location drawing above).
➌
Install PMC card onto SBC (refer to drawing below for assembly
details):
a. Place VSS4 assembly face-up on a flat surface of an ESDprotected workstation.
b. If not already on, install PMC card’s front panel O-ring gasket
(included with PMC card) by slipping gasket into groove
around front panel.
c. Grasp PMC at sides: with card front panel towards SBC front
panel from rear, tilt PMC front panel into SBC front panel
cutout and engage front panel O-ring gasket with chamfer in
SBC panel cutout. With PMC front panel in place, place card
over SBC connectors. Ensure both PMC and SBC connectors
are aligned then press down over PMC connector area to
fully engage SBC connectors.
d. Turn VSS4 assembly over.
e. Install four 6 mm M2.5 slot-head screws (item 6, or whatever
screw fasteners are supplied with PMC card) from rear
(solder) side of VSS4 motherboard. Two screws engage the
standoffs on the PMC card. The other two screws engage the
threaded holes in the PMC card front panel. See Location,
PMC card securing screws drawing earlier in this chapter.
Removal is reverse of installation.
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Section 2: Getting Started
Installing PMC cards
Single PMC installation — Required hardware
Item
locator
Quantity
in assy
6
4
Synergy part
number
Item
description
Fas/SwM25FP6S
Screw, M2.5 thread, pan head, phillips, 6 mm long, steel (or use whatever
screw fastener is supplied in PMC card kit)
FR
ON
T
O-ring
Gasket
PMC card
front panel
Groove
Detail
Place o-ring gasket in front panel groove.
PMC CARD
Filler panel
SBC
Bolt-on type
Push-in type
6
BA
CK
Front panel
PMC cutout
Vi
e
w
A-
A
6
6
Screw, M2.5 6mm
panhd, 4 places
Rubber o-ring gasket in place
PMC Connectors
6
PMC Card
VMEbus
connectors
Tilt front
panel into
SBC cutout
SBC
PMC connectors
6 Screw, M2.5 thread, 6mm,
pan head slot (4 places)
Eject Knob
VIEW A-A, Side View — PMC Card Installation
01-0059
PMC card installation
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Section 2: Getting Started
Installing PMC cards
44
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Section 2: Getting Started
Installing the P0 overlay
Installing the P0 overlay
The P0 overlay is used to interconnect boards within the same
cardcage via Synergy’s P0•PCI™ interface. Refer to Section 9 (page
215) for a description of the interface.
The P0 overlay board comes in left, right, and center configurations of
varying slot capacities. Each overlay uses a small, plug-in arbiter board.
Some overlay models allow joining with another overlay section via a
bridge board. The table below lists the P0 overlay components for use
with the P0•PCI™ interface.
P0 overlay components
Model Number
BP08
BPM7
BPM6
BPM5
BPR4
BPL4
BP03
BP02
BBP0
DPPA
DPPB
Description
8-slot P0 overlay, non-bridgeable
7-slot P0 overlay, bridging to left or right
6-slot P0 overlay, bridging to left/right/both
5-slot P0 overlay, bridging to left/right/both
4-slot P0 overlay, bridging to left only
4-slot P0 overlay, bridging to right only
3-slot P0 overlay, non-bridgeable
2-slot P0 overlay, non-bridgeable
Bridge board
Arbiter board, standup type
Arbiter board, flat type
The drawing below shows the available P0 overlay boards.
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Section 2: Getting Started
Installing the P0 overlay
UP *
Arbiter Board connector (BP02 only)
95-pin socket
connector
(2 places)
(a) BP02, 2-slot P0 overlay, non-bridgeable
Bridge Board connector
95-pin socket
connector Arbiter Board
(4 places) connector
Arbiter Board connector (BP03 only)
95-pin socket
connector
(3 places)
(b) BP03, 3-slot P0 overlay, non-bridgeable
Bridge Board connector
Arbiter Board
connector
UP *
BPL4, Left
P0 Overlay
95-pin socket
connector
(4 places)
BPR4, Right
P0 Overlay
(c) BPL4/BPR4, 4 slot Left or Right P0 overlay, bridgeable
Bridge Board connector (left/right only, or both)
Arbiter Board
connector
95-pin socket
connector
(5 places)
Bridge Board connectors (left/right only, or both)
95-pin socket
connector
Arbiter Board
(6 places)
connector
UP *
(d) BPM5, 5-slot Center P0 overlay, bridgeable
(e) BPM6, 6-slot Center P0 overlay, bridgeable
* Note: View is from FRONT of card cage, looking towards back.
Farside components shown with dashed line.
P0 overlay board models
46
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99-0245
Section 2: Getting Started
Installing the P0 overlay
Bridge Board connectors (left or right only, not both)
UP *
Arbiter Board
connector
95-pin socket
connector
(7 places)
(f) BPM7, 7-slot Center P0 overlay, bridgeable
UP *
Arbiter Board
connector
95-pin socket
connector
(8 places)
(g) BP08, 8-slot Center P0 overlay, non-bridgeable
* Note: View is from FRONT of card cage, looking towards back.
Farside components shown with dashed line.
99-0246
P0 overlay board models (continued)
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Section 2: Getting Started
Installing the P0 overlay
The drawing below is provided as a guide to assembly of P0 overlay
components. The minimum installation is an overlay board (with its
arbiter plugged in) plugged into the VME backplane. Other installations
may have one or more overlay sections joined together with a bridge
board. Observe the following precautions when installing the P0
overlay boards.
First check to make sure that the P0
backplane pins are straight. With the
pins verified (or made) straight, carefully
align the overlay board onto the P0
backplane pins. Ensure that all
backplane P0 pins properly engage the
overlay board socket before fully
seating the board! If board doesn’t
begin to seat when pressed against the
pins, BACK OFF and try aligning the
board again.
To avoid accidental damage to the
arbiter board, always remove it from its
P0 overlay socket before handling the
P0 overlay board. This applies
especially to the standup type arbiter
(DPPA) used with the BP02 2-slot P0
overlay.
48
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Section 2: Getting Started
Installing the P0 overlay
Cardcage Front
VME64x Backplane w/P0
BPR4 Overlay Board
BPM7 Overlay Board
DPPB Arbiter Board
DPPB Arbiter Board
BPP0 Bridge Board
Assembly Side View, Looking From Above Cardcage
DPPB, Arbiter
Board, Flat **
Bridge Board (Model BBP0)
Orient board with label "Top" at
upper left.
DPPB, Arbiter
Board, Flat **
UP *
TOP
BPR4, 4-slot P0 overlay (right)
BPM7, 7-slot P0 overlay ('bridging to right' configuration)
Notes:
* View is from BACK of card cage, looking towards front.
Farside components shown with dashed line.
** A 'standup' arbiter board, DPPA, is used with BP02 2-slot overlay only.
99-0247
P0 overlay boards, typical component assembly
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Section 2: Getting Started
Installing the P0 overlay
50
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Section 2: Getting Started
Installation notes
Installation notes
Slot installation recommendations
The VSS4 and other quad processor boards place extra demands on the
chassis for cooling and ventilation. Two chassis issues affect this: slot
location and empty slots.
Slot location — Some slots in a VME or CompactPCI cardcage have
little or no airflow. End slots in wide (e.g., 21-slot) cardcages are often
prone to poor airflow, as well as slots located between fans. It is
recommended that these slots be avoided when installing the VSS4 (or
similar quad board). To ensure the suitability of a particular slot, its
airflow can be quickly checked (with adjacent boards installed as they
would be in the actual installation) by using a hand-held anemometer
such as the Kestrel 1000 Pocket Wind Meter by Nielsen-Kellerman
( www.nkelectronics.com). Note that a system controller board needs to be
the leftmost slot. Any slot to the left of the system controller board must
be empty.
Empty slots — Empty slots in a cardcage tend to rob airflow away from
populated slots. It is recommended that empty slots be avoided. If
empty slots cannot be avoided, it is recommended that empty slots be
installed with Slot Bypass or Air Management boards (www.apw.com) or
that empty slots be distributed in such a way that the VSS4 or any hotrunning board is adjacent to an empty slot.
By managing empty slot placement and avoiding slots with diminished
airflow, the cardcage should have no trouble cooling the VSS4 and
other high power boards.
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Section 2: Getting Started
Installation notes
Bus grant signal problems with Hybricon
VME64x backplanes
Problem
Installing a Universe II-equipped SBC in slot 1 of some early Hybricon
VME64x backplanes prevents the bus grant daisy chain signals from
being passed on to the next slot (slot 2).
Observation
Some early Hybricon VME64x backplanes use active logic to drive the
bus grant daisy chain signals to the next slot. The logic requires that the
signal be low (active) coming out of the slot AND low (active) going
into the slot in order to be driven to the next slot. This logic is also
included on the backplane for slot 1 even though there is no slot to the
left of slot 1. The backplane includes pull-down resistors (82K ohms) for
the BGnIn\s and BGnOut\s for slot 1. The Universe II VME interface
chip, however, has an internal pull-up (~10kΩ) on its BGnIn\s that is
stronger than those on the backplane. A board using the Universe II
chip in slot 1 causes the active logic on the backplane to not pass the
BGnOut\s to the next slot because the active logic sees a high
(inactive) signal going into slot 1. BG3Out\ from slot 1 works because
of the pull-down on BG3In\ for VME auto-system controller.
Solution
If the VSS4 board (or any SBC using the Universe II) is to be used in slot
1 of an early Hybricon VME64x backplane, connect the backplane’s
slot 1 BGnIn\s to ground. This can be accomplished by adding four (4)
short wires as listed in the table below:
Slot 1 wiring fix for some early Hybricon VME64x backplanes
From
P1 - Z4 (GND)
P1 - Z6 (GND)
P1 - Z8 (GND)
P1 - Z10 (GND)
52
To
P1 - B4 (BG0In\)
P1 - B6 (BG1In\)
P1 - B8 (BG2In\)
P1 - B10 (BG3In\)
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Basic Bus
Descriptions
3
This section provides basic background information about the various
buses/interfaces used in the VSS4 board.
•
PowerPC bus
•
VME64 bus
•
PCI bus
•
SCSI bus
•
Fast Ethernet interface
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Section 3: Basic Bus Descriptions
PowerPC bus
PowerPC bus
The system communicates with the PowerPC processor(s) through the
MPC106 (Grackle) PCI Bridge/Memory controller. The Grackle
connects all memory, front panel switches/LEDs, serial ports,
RTC/NVRAM, User Flash, and mailboxes to the PowerPC bus.
Moreover, the Grackle interfaces the PowerPC bus to the SBC's local
PCI bus.
The PowerPC processor uses separate address and data buses plus
various control and status signals for performing reads and writes. The
address bus is 32 bits wide and the data bus is 64 bits wide. For
memory accesses, the address and data buses are independent to
support pipelining and split transactions.
The bus interface is synchronous, with all inputs sampled and all
outputs driven from the rising edge of the bus clock. The bus runs at 66
MHz. The PowerPC chip’s internal multiplier boosts this frequency to its
rated speed. The multiplier ratio is configured at assembly time by
soldered-in jumpers on the board.
Access to the PowerPC bus interface is granted through an external
arbitration mechanism that allows devices to compete for bus
mastership. For the VSS4, these devices include the PowerPC to PCI
Bridge/Memory Controller (Grackle) chip and the PowerPC processors.
The Grackle chip handles PCI–PowerPC bus accesses.
For more details on PowerPC bus arbitration, refer to the Motorola/IBM
User’s Manual for the appropriate processor resident on your VSS4
board.
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Section 3: Basic Bus Descriptions
PowerPC Bus
56
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Section 3: Basic Bus Descriptions
VME64 bus
VME64 bus
Overview
The VMEbus (Versa Module Eurocard bus) is a microcomputer
architecture whose physical and electrical characteristics are defined in
the IEC 821 and IEEE 1014-1987 specifications. Standard VMEbus
supports separate address and data lines of up to 32 bits each. This bus
uses a backplane in which VMEbus modules are interconnected using
DIN-41612 connectors designated as P1/J1 and P2/J2
(module/backplane designations respectively).
Standard VMEbus modules come in two form factor types:
•
•
Single height (3U) for single backplane using P1/J1 connectors
Double height (6U) for two backplanes (or combined backplane)
using P1/J1 and P2/J2 connectors
The original VMEbus specification has been refined through several
revisions (A, B, C, C.1, IEC 821 and IEEE 1014-1987). On April 10,
1995, a new VME64 standard was approved for publication as
ANSI/VITA 1-1994. The VME64 standard was based on the VME
Revision C.1 specification and adds several features including 64-bit
address and data transfers. However, 64-bit addressing is not supported
by the VSS4 board since the PowerPC processor has only a 32-bit
address bus.
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Section 3: Basic Bus Descriptions
VME64 bus
The table below summarizes the VMEbus architecture and features
supported by the VSS4.
VSS4 VMEbus feature support
Standard VMEbus
32-bit address bus
address range
16-bit
24-bit
32-bit
(64-bit)
–
–
–
–
–
VME64, add:
64-bit data transfer
Locked cycles
Rescinding DTAck\
Autoslot ID
Auto Sys. Controller detection
32-bit data bus
data path width
8-bit
16-bit
24-bit
32-bit
(64-bit)
VME64 Extensions, add:
160-pin P1/P2 (wide P1/P2)1
User defined P0 conn.2
Slot geographical addressing
Mate first, break last
precharge pins on P1/P2 for
hot-swapping applications
– ETL bus transceivers
– EMI front panel
–
–
–
–
7 interrupt levels
Master/Slave architecture
Functional modules
Master
Slave
System Controller
Sub-busses
Data Transfer Bus
Data Transfer Arbitration Bus
Priority Interrupt Bus
Utility Bus
Notes:
1. For VSS4, P1 is 3-row for Rev. B or lower boards only.
2. Supported in select PowerPC Series models.
VSS4 VMEbus implementation
The VSS4 VMEbus functionality is provided by the Universe II PCI to
VME64 bridge interface.
The Universe II chip provides the VME interface. It can do most all VME
functions, including system controller, master and slave single and block
transfers, and interrupt generation and handling. It cannot do readmodify-write (RMW) cycles.
The VSS4 has two functional modules involved with bus ownership; the
system controller, and the Universe requester.
The system controller resides in the Universe II chip. It is enabled when
the VSS4 is installed in Slot 1. The system controller performs bus
arbitration and system reset tasks. It is not directly related to the VSS4’s
58
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Section 3: Basic Bus Descriptions
VME64 bus
bus requesters. All bus requesters in the system use the arbiter in this
system controller.
The Universe requester is used when the Universe VME master function
is used; i.e. when the CPU accesses the VMEbus through a Universe
VME master window.
The Universe VME requester has selectable bus request level, release
mode, fair mode, etc.
The block diagram below shows the functional blocks that make up the
VSS4 VMEbus interface.
Universe II VME Interface
System controller
Interrupt generation/handling
Master/Slave Single transfers
Master/Slave Block transfers (BLT32 & BLT64)
Data broadcast slave
PowerPC
CPUs
PowerPC Bus
PowerPC
to
PCI Bridge/
Mem. Ctrlr.
PCI Bus
PCI-VME
Bridge
VME Bus Transceivers
VMEBus
Block diagram, VSS4 VMEbus interface
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Section 3: Basic Bus Descriptions
VME64 bus
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Section 3: Basic Bus Descriptions
PCI bus
PCI bus
Introduction
PCI, or Peripheral Component Interconnect, is a computer industry
specification for interconnecting peripherals with both the system
memory and the CPU. Though often referred to as a “local bus” since it
accesses the CPU and system memory directly, PCI is actually a
separate bus isolated from the CPU. At the early stages of PCI bus use,
this processor independence was typically provided by a PCI bridge
chip with a 32-bit PCI bus running at 33 MHz for a maximum data
transfer rate of 132 MB/sec. With the PCI 2.1 specification, both data
width and clock speed doubled to 64-bits and 66 MHz respectively for
a maximum data transfer rate of 528 MB/sec (in the real world, actual
rate will be lower due to bus latency times). Various clarifications and
enhancements to PCI 2.1 were subsequently included in the PCI 2.2
specification. The PCI 2.3 specification migrated the PCI bus from the
original 5V signaling to a 3.3V signaling bus and included some
changes in the system board keyed connector support. PCI
performance received yet another boost with the PCI-X specification,
which provided a path for ever increasing bus speeds starting at 133
MHz (or 1 GB/s). The PCI bus’ processor independence has caused the
interface to gain in popularity as a solution to providing cost-effective,
high performance peripheral interconnections regardless of the
processor or platform used.
Key features of PCI:
•
Multiple busmasters on the same bus — with bus mastering, a
device can take control of the bus and provide main memory
I/O without CPU intervention.
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Section 3: Basic Bus Descriptions
PCI bus
•
•
•
Auto-configuring — all components plugged into the PCI bus can
be automatically detected and configured for use during the
system startup routine.
Interrupt (IRQ) sharing — the PCI bus is able to share a single
interrupt between cards/PCI devices.
High bus bandwidth — 132 MB/sec and 264 MB/sec for 32-bit
and 64-bit PCI respectively (@33 MHz).
The VSS4 PCI interface is provided by the MPC106 (Grackle chip). It
provides a 33 MHz PCI bus interface that is compliant with the PCI 2.1
specification which is backwards compatible with PCI 2.0. The
MPC106, however, supports only 32-bit PCI connections. Refer to the
Grackle chip discussion in Section 4, page 93, for more information.
PMC cards
The PCI Mezzanine Card (PMC) is an industry-standard design that
allows PCI based I/O cards to be used in VMEbus and CompactPCI
motherboard designs. The IEEE P1386 CMC (Common Mezzanine
Card) standard defined the available PMC card sizes. The table below
lists the PMC sizes typically used for VMEbus and CompactPCI systems.
Typical PMC card size designations and dimensions
Designation
Single
Double
Width in mm
74.0
149.0
Depth in mm
149.0
149.0
PMC cards come in 32- and 64-bit designs. With 64-bit designs,
additional connectors are required over the standard 32-bit design. The
VSS4 boards come with these extra connectors, allowing 64-bit PMC
cards to be used.
PCI implementation details
The following is a nuts and bolts description of how PCI is implemented
in a system from a software standpoint.
PCI address spaces
PCI devices are accessed by the CPU from three address spaces, PCI
I/O, PCI Memory and PCI Configuration space. The PCI I/O and PCI
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Section 3: Basic Bus Descriptions
PCI bus
Memory address spaces are used by the device drivers. The PCI
Configuration space is used by the PCI initialization code being run at
bootup.
All of these spaces are for PCI chips or devices. Exactly what registers
are used and their location depend on the assigned IDSel number
and/or its slot location (if PMC) and specific programming as set during
PCI configuration.
e
Not
The PCI I/O space is a relic of the IBM
PC's ISA bus, and is typically not used
by modern PCI configuration routines
for most PowerPC operating systems.
PCI configuration
Every PCI device in the system, including PCI-PCI bridges, has a data
structure located in PCI configuration address space called the PCI
Configuration header. This structure, which has a maximum length of
256 bytes, allows the system to identify and control the device during
configuration.
31
16 15
0
Device ID = 0x0701
Vendor ID = 0x1000
Status
Command 0x0000*
Class Code = 0x020000
Revision ID= 0x00
BIST
Header Type
Latency Timer
Cache Line Size
Base Address Zero (I/O), Ethernet Operating Registers
Base Address One (Memory), Ethernet Operating Registers
Not Supported
Not Supported
Not Supported
Not Supported
Reserved
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Reserved
Max_Lat
Max_Gnt
Interrupt Pin
Interrupt Line
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Shown above is a typical layout of a PCI configuration header (Symbios
Logic’s Ethernet interface). It contains the following fields:
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Section 3: Basic Bus Descriptions
PCI bus
•
•
•
•
•
•
•
•
Vendor Identification — A unique number describing the
originator of the PCI device. Symbios Logic’s PCI Vendor
Identification is 0x1000.
Device Identification — A unique number describing the device
itself. In the example above, Symbios Logic’s Fast Ethernet
device has a device identification of 0x0701.
Status — This field gives the status of the device with the
meaning of the bits of this field set by the PCI Local Bus
Specification
Command — By writing to this field the system controls the
device, for example allowing the device to access PCI I/O
memory.
Class Code — This identifies the device category. There are
standard classes for every sort of device; video, SCSI and so on.
The class code for SCSI is 0x0100.
Base Address Registers — These registers are used to determine
and allocate the type, amount and location of PCI I/O and PCI
memory space that the device can use.
Interrupt Pin — Four of the physical pins on the PCI card carry
interrupts from the card to the PCI bus. The standard labels
these as A, B, C and D. The Interrupt Pin field describes which of
these pins this PCI device uses. Generally it is hardwired for a
particular device. That is, every time the system boots, the
device uses the same interrupt pin. This information allows the
interrupt handling subsystem to manage interrupts from this
device.
Interrupt Line — The Interrupt Line field of the device’s PCI
Configuration header is used to pass an interrupt handle
between the PCI initialization code, the device’s driver and OS’s
interrupt handling subsystem. The number written there is
meaningless to the device driver but it allows the interrupt
handler to correctly route an interrupt from the PCI device to
the correct device driver’s interrupt handling code within the
operating system.
During system boot time, PCI devices are detected and configured
automatically via a software process called PCI Discovery. Other names
for this process include PCI Enumeration and PCI Auto Configuration.
The exact mechanism for PCI Discovery is system-specific. For Synergy
PowerPC SBCs, all PCI devices or slots in the system are hardwired with
an address line that functions as the device’s IDSEL number. IDSEL is
essentially a ‘chip select’ for a device during PCI configuration.
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Section 3: Basic Bus Descriptions
PCI bus
Devices are detected by reading the Vendor and Device IDs in all
possible device locations via IDSEL (reads from PCI Configuration Data
space). If a location is empty, the read returns all 1s (0xFFFFFFFF) and
the system goes on to read the next location. A valid Vendor and
Device ID results in the system narrowing down the capabilities by
reading additional device configuration data. If a device indicates a
multifunction device (such as the Symbios 53C885), a read of all
locations every 0x100 is done to tally up all the sub-functions. After all
functions are identified, the device base address registers (BARs) and
other miscellaneous configuration registers (if any) are set up per the
programming for that type device (writes to PCI Configuration Address
space).
To find out just how much of each address space a given BAR is
requesting, all 1s are written to the register and the result read back.
The device will return zeros in the don’t care address bits, effectively
specifying the address space required. This design implies that all
address spaces used are a power of two and are naturally aligned.
For example when you initialize the Symbios Logic Fast Ethernet device,
it tells you that it needs 0x100 bytes of space of either PCI I/O or PCI
Memory. The initialization code allocates it space. The moment that it
allocates space, the Fast Ethernet device’s control and status registers
can be seen at those addresses.
The above process repeats until all locations (maximum of 21 PCI
devices) are read.
Endian issues, byte swapping
The PCI bus is inherently little-endian where byte 0 is the LSB. The
PowerPC is big-endian where byte 0 is the MSB. This difference in
endianness requires byte swapping code for accesses between PCI and
PowerPC. The PowerPC instruction set includes a class of load and
store instructions that perform byte swapping based on the size of data
being transferred. The example in-line routines below show how this is
done for word and half-word data.
#define ASM volatile asm
// Read a longword from adr, little-endian
extern inline int lwbrx(void *adr)
{
int data;
ASM("lwbrx %0,0,%1": "=r"(data):"r"(adr));
return data;
}
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Section 3: Basic Bus Descriptions
PCI bus
// Store longword data to adr, little-endian
extern inline void stwbrx(int data, void *adr)
{
ASM("stwbrx %0,0,%1": :"r"(data), "r"(adr));
}
// Read a 16-bit word from adr, little-endian
extern inline int lhbrx(void *adr)
{
int data;
ASM("lhbrx %0,0,%1": "=r"(data):"r"(adr));
return data;
}
// Store 16-bit word data to adr, little-endian
extern inline void sthbrx(int data, void *adr)
{
ASM("sthbrx %0,0,%1": :"r"(data), "r"(adr));
}
PCI standards organization
PCI architecture specifications are maintained by the PCI Special
Interest Group (PCI-SIG), an industry standards organization formed in
1992 to develop and manage the PCI standard. PCI specification
documents are available for purchase from:
The PCI-SIG:
PCI SIG Specification Distribution
5440 SW Westgate Drive, Suite 217
Portland, OR 97221 USA
1-800-433-5177 (Domestic Only) 425-803-1191 (International)
WWW: http://www.pcisig.com/
Global Engineering Documents:
Global Engineering Documents
15 Inverness Way East
Englewood, CO, 80112
E-Mail:[email protected]
Phone:+1-800-854-7179 FAX:+1-303-397-2740
WWW: http://www.global.ihs.com/
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Section 3: Basic Bus Descriptions
SCSI bus
SCSI bus
Overview
The Small Computer Systems Interface (SCSI) is a parallel I/O bus that
lets a host computer access various peripheral devices without the need
for specialized hardware and software commands for each device. The
host’s SCSI interface acts as a translator between the host and a
particular type of peripheral which provides the host with device
independence. For example, one vendor's SCSI disk drive could be
replaced with another vendor's SCSI disk drive with no changes to the
existing driver code. In addition, because SCSI is a general-purpose
interface, tape drives, hard disks, CD-ROMs, and a variety of other
peripherals can quickly be added to the SCSI bus since they all speak
the same high level language when communicating with the host.
History
The SCSI interface started life as SASI (Shugart Associates Systems
Interface), a joint development between Shugart Associates and NCR.
In late 1981, SASI was submitted to the ANSI X3T9 standards
committee as a proposed interface standard. The standards committee
renamed the interface SCSI and in June 1986, SCSI was finally made an
ANSI standard with the publication of specification X3.131-1986. This
particular 8-bit SCSI was later referred to as SCSI-1.
A fast, wide SCSI interface, referred to as SCSI-2, was then designed
with increased throughput of up to 20 MB/S. The SCSI-2 interface was
finally approved by ANSI on January 31, 1994 and designated as
specification X3.131-1994.
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Section 3: Basic Bus Descriptions
SCSI bus
Even before the release of the SCSI-2 standard, work on SCSI-3 began
in 1993. It became apparent to the standards committee that a variety
of technology (i.e., new serial interfaces for desktop and high
performance environments) was vying for inclusion in the SCSI spec. As
a result, the SCSI-3 standard was turned into layers (similar to a
networking standard) so that parts which were fast changing could be
isolated and standardized on different schedules. Since the creation of
SCSI-3, the confusion surrounding SCSI standards has increased. SCSI-3
is defined in a collection of about 30 different standards.
e
Not
VSS4’s Wide Ultra (Fast-20) SCSI
interface is defined in ANSI standard
X3.277-1996 which is an addendum to
the SCSI-3 Parallel Interface (SPI)
standard.
Two organizations exist to maintain and promote the SCSI standard:
•
SCSI Trade Association (STA) — This industry trade organization
communicates the benefits of SCSI. For more information on this
organization, refer to the STA website:
•
T10, National Committee on Information Technology Standards
(NCITS) Technical Committee — This is a standards committee
that promulgates low-level interface standards. This group works
with industry members to gain consensus on the low-level
interface rules. These rules start out as draft standards that
eventually become ANSI standards. For more information on the
T10 committee, refer to the T10 home page on the web:
http://www.scsita.org/
http://www.t10.org
To keep pace with improvements in computer technology, SCSI
continues to evolve with wider data paths and increased transfer
speeds. The table below lists the current varieties of the SCSI interface
as given by the SCSI Trade Association.
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Section 3: Basic Bus Descriptions
SCSI bus
List of SCSI types (SCSI Trade Organization)
SCSI Type (per STA)
Bus Speed, MBytes/Sec,
Maximum
5
10
20
20
40
40
80
160
Bus Width, Bits
Device Support
(including Host)
8
8
16
8
16
8
16
16
SCSI-1†
8
Fast SCSI†
8
Fast Wide SCSI
16
Ultra SCSI†
8
Wide Ultra SCSI
16
Ultra2 SCSI †
8
Wide Ultra2 SCSI
16
Ultra3 SCSI or
16
Ultra160 SCSI
Ultra320 SCSI
320
16
Ultra640 SCSI
640
16
†Use of the word "narrow", preceding SCSI, Ultra SCSI, or Ultra2 SCSI is optional.
16
16
SCSI specifications and publications
For a complete list of SCSI-related specifications (draft and approved)
and other publications, refer to the T10 publications list on the web:
http://www.t10.org/pubs.htm
Device connections
The SCSI bus supports up to eight devices including the host(s). A SCSI
device is either an initiator (host) or target (device that responds to the
requests of an initiator to perform an operation). The bus protocol
accommodates four types of SCSI device configurations as shown in
the following figures:
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Section 3: Basic Bus Descriptions
SCSI bus
Host
Computer
SCSI Host Bus
Adapter
SCSI BUS
SCSI Hard Disk
Drive
Single Host (initiator)/Single Controller (target)
Host
Computer
SCSI Host Bus
Adapter
SCSI BUS
SCSI Tape
Drive
SCSI Hard Disk
Drive
SCSI CD-ROM
Drive
Single Host (initiator)/Multiple Controllers (targets)
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Section 3: Basic Bus Descriptions
SCSI bus
Host
Computer
Host
Computer
Host
Computer
SCSI Host Bus
Adapter
SCSI Host Bus
Adapter
SCSI Host Bus
Adapter
SCSI BUS
SCSI CD-ROM
Drive
Multiple Hosts (initiators)/Single Controller (target)
Host
Computer
Host
Computer
Host
Computer
SCSI Host Bus
Adapter
SCSI Host Bus
Adapter
SCSI Host Bus
Adapter
SCSI BUS
SCSI Tape
Drive
SCSI Hard Disk
Drive
SCSI CD-ROM
Drive
Multiple Hosts (initiators)/Multiple Controllers (targets)
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Section 3: Basic Bus Descriptions
SCSI bus
Electrical connections
Electrical connections on the SCSI bus are either single-ended or
differential. Single-ended SCSI connections use TTL level signals to drive
a cumulative cable length of up to 6 meters (20 feet) while differential
connections use either EIA-485 (high voltage differential or HVD) or
EIA-644 (low voltage differential signaling or LVD) to drive a maximum
cumulative cable length of up to 25 meters (82 feet).
For older SCSI interfaces, device connections to a particular SCSI bus
must be all single-ended or differential — they cannot be combined on
the same bus. To protect the differential driver circuits, the DIFFSENS
signal is provided. This signal is a single-ended signal that is used as an
active high enable for the differential drivers. If a single-ended device or
terminator is inadvertently connected, DIFFSENS is grounded, which
disables the differential drivers by placing them in high impedance state
(tristate).
Newer SCSI interfaces that use low voltage differential (LVD) signaling
can operate in “multimode” to allow a mix of low voltage differential
and single-ended devices on the bus. In multimode, the DIFFSENS line
is used to differentiate between SE (DIFFSENS ≤ 0.5 V), and LVD
(DIFFSENS = 0.7 V–1.9 V). When a single-ended device is connected to
the bus, the DIFFSENS line senses the voltage which causes all other
attached devices to automatically configure themselves for single-ended
operation (all “+” signal pins grounded). Since only SE or LVD buses
can accommodate multimode operation, HVD devices are not allowed
to be connected to an SE or LVD bus.
The VSS4 SCSI interface is fixed at single-ended. For connector
information, refer to Appendix A, Wide Ultra SCSI connector (page
253).
The SCSI signal lines are divided into two basic groups, data lines
(DB0–DB15, DBP0 and DBP1) and control signals (SEL, BSY, C/D, I/O,
MSG, REQ, ACK, ATN and RST). Altogether, the SCSI-2 interface uses
68 lines.
The following table summarizes the ANSI standard SCSI-2/SCSI-3 bus
signals supported by VSS4.
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Section 3: Basic Bus Descriptions
SCSI bus
SCSI-2/SCSI-3 bus signals
Pin No.
40
41
42
43
44
45
46
47
65
66
67
68
35
36
37
38
48
39
—
17, 18,
51, 52
55
57
58
59
60
61
62
63
64
19, 53
Note:
Mnemonic (see Note)
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DBP0
DBP1
DIFFSENS
TERMPWR
Signal
Data Bus Line 0
Data Bus Line 1
Data Bus Line 2
Data Bus Line 3
Data Bus Line 4
Data Bus Line 5
Data Bus Line 6
Data Bus Line 7
Data Bus Line 8
Data Bus Line 9
Data Bus Line 10
Data Bus Line 11
Data Bus Line 12
Data Bus Line 13
Data Bus Line 14
Data Bus Line 15
Data Bus Parity1
Data Bus Parity2
Differential Sense
Terminator Power
Driven By
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Initiator/Target
Any device
Any device
ATN
BSY
ACK
RST
MSG
SEL
C/D
REQ
I/O
No Connection
Attention
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
—
Initiator
Initiator/Target
Initiator
Any device
Target
Initiator/Target
Target
Target
Target
—
Signals in bold italic are provided as plus and minus signal pairs for differential SCSI.
For single-ended SCSI, each of these signals is provided as one negative polarity line
and the DIFFSENSE signal is unused.
Physical topology
SCSI devices are connected one after the other in daisy-chain fashion.
Up to seven devices can make up this chain. See E l e c t r i c a l
connections above for the maximum cumulative length of the chain.
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73
Section 3: Basic Bus Descriptions
SCSI bus
Bus terminations
All SCSI signals must be terminated at each end of the SCSI chain to
ensure clean signals and proper timing of bus operations. This is
achieved either by a voltage divider resistor network powered by the
TERMPWR pin on one of the SCSI device connectors or by active
circuitry that provides the same function.
The VSS4 SCSI interface has active termination circuitry that is
enabled/disabled with configuration jumper J02L (pins 3 & 4). See
Section 2 Setting up the VSS4 hardware for more information on the
SCSI termination jumper.
Bus communication control
The SCSI interface uses the following eight phases or bus states to
control communication over the bus:
❏
❏
❏
❏
❏
❏
❏
❏
Bus Free — indicates that no SCSI device is actively using the bus
and that it is free.
Arbitration — an optional phase in which SCSI devices arbitrate
for use of the bus.
Selection — lets an initiator select a target to perform a function
such as a Read or Write command.
Reselection — an optional phase in which a target reconnects to
an initiator to continue an operation that was previously started
but was suspended by the target.
Command — lets a target request command information from
the initiator.
Data — allows data transfer from target to initiator or from
initiator to target.
Status — allows status information to be sent from target to
initiator.
Message — allows sending of single or multi-byte messages from
target to initiator or from initiator to target.
The last four phases listed above are called information phases since
they transfer command, data, status or message information.
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Section 3: Basic Bus Descriptions
SCSI bus
Data transfer options
Asynchronous and synchronous protocols are used in the SCSI bus. The
asynchronous protocol requires a handshake for every byte transferred.
The synchronous protocol transfers a series of bytes before the
handshake occurs. This means a higher data transfer rate for
synchronous mode versus that for asynchronous mode.
The asynchronous data transfer mode is the default (normal) mode
since this mode does not need to be selected. All commands,
messages, and status are always transferred asynchronously.
A synchronous target, however, can ask the initiator for synchronous
transfer of data. The initiator responds to this request by either
maintaining asynchronous data transfers or establishing synchronous
data transfers by an exchange of messages containing the minimum
transfer period and maximum REQ/ACK offset for each device. When
synchronous data transfer is established, it is done using the greater of
the two minimum transfer periods and the lesser of the two maximum
REQ/ACK offsets.
The VSS4 SCSI interface supports 8-bit Ultra SCSI synchronous transfers
of up to 20 MB/s and 16-bit Wide Ultra SCSI synchronous transfers of
up to 40 MB/s.
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Section 3: Basic Bus Descriptions
SCSI bus
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Section 3: Basic Bus Descriptions
Fast Ethernet interface
Fast Ethernet interface
Ethernet is a LAN (local area network) architecture that provides the
means for computers and other peripherals located in a moderately
sized geographical area to communicate with each other at high speed.
The Ethernet prototype was developed by Xerox Corporation in 1975
and grew to a standard LAN specification 10 years later (IEEE 802.31985) with the collaborative efforts of Digital Equipment Corporation,
Intel Corporation, and Xerox Corporation. From the standard Ethernet
specification came the 10Base-T Ethernet standard that used
inexpensive unshielded twisted pair cable terminated in modular plugs.
The popularity of 10Base-T fueled the development of Fast Ethernet
100Base-T which incorporated new signaling schemes to provide a 100
Mbps data rate over a range of twisted pair (100Base-TX, 100Base-T4)
and fiber cabling (100Base-FX) types. 100Base-TX provides an easy
migration path to higher performance since it can use existing 10Base-T
cables and equipment for interim 10Base-T operation. Changing over to
Category 5 cable and Fast Ethernet hubs automatically switches the
network to Fast Ethernet operation.
Ethernet provides what is called a “link level” facility since it deals with
the lowest two layers of network architecture as defined by the ISO
Model for Open Systems Interconnection: the Physical Level and the
Data Link Layer.
With Ethernet, the type of data it transmits is immaterial since it does
not concern itself with data protocol and interpretation. As such,
Ethernet LANs are used for various types of computing platforms such
as mainframe computers, Macintoshes, IBM PC and compatibles,
SPARC workstations, UNIX systems, etc.
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77
Section 3: Basic Bus Descriptions
Fast Ethernet interface
Ethernet network connections
The VSS4 provides a 10Base/100Base-TX Ethernet (Fast Ethernet) port
at the front panel. This type of Ethernet uses a star topology in which
each DTE (data terminal equipment) is connected to a shared hub
through a single, 4-pair unshielded twisted pair (UTP) cable. The UTP
cable is similar to modular telephone cable. For network use, however,
a higher grade (or category) of cable is typically used. For 10Base-T,
Category 3 is the minimum, but Category 4 or 5 is more often
recommended. For 100Base-TX, no less than Category 5 cable is
recommended. Cable connections are made to an 8-pin RJ-45 modular
jack. The maximum distance between DTE and hub is 100 m (328 ft.)
for both 10Base-T and 100Base-TX.
The figure below shows a typical 10Base/100Base-TX Ethernet single
hub network.
DTEs
HUB
10Base/100Base-TX Ethernet single hub network
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Section 3: Basic Bus Descriptions
Fast Ethernet interface
Data transmission
Both clock and NRZ data information is Manchester-encoded in bitserial form and encapsulated in a basic unit called a frame packet.
The frame packet is made up of seven fields in which the data field is
bracketed by several bytes of information. The figure below shows the
format of an Ethernet frame.
Bits within byte transmitted LSB first (except FCS)
Preamble
62 bits
SFD
2 bits
Destination
6 Bytes
Source
6 Bytes
Length
2 Bytes
Data
46–1500 Bytes
FCS
4 Bytes
Ethernet Frame Packet Format
The packet fields are summarized below.
Preamble — is a series of alternating 1’s and 0’s that serve to
synchronize the clock and other circuitry on all the receivers and
repeaters on the network.
Start of Frame Delimiter (SFD) — consists of two consecutive 1’s to
signal the start of a frame.
Destination — six bytes to indicate the destination of the packet on the
network.
Source — six bytes to indicate the node that sent the packet.
Length — two bytes to indicate the number of bytes contained in the
data field.
Data — 46–1500 data bytes. Stations that need to send less than 46
bytes of data must pad the data to reach the minimum requirement.
Stations that need to send in excess of 1500 bytes of data must send
multiple frame packets.
Frame Check Sequence — CRC value of packet (not including
preamble and SFD fields) for error detection. Receiver rejects the frame
if the calculated CRC value of the received data does not match the
transmitted CRC value.
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Section 3: Basic Bus Descriptions
Fast Ethernet interface
Ethernet ID or physical address
An Ethernet board is typically designed with a unique Ethernet ID (also
called physical address) in ROM; by default any Ethernet packet sent to
this ID will be received by the board and passed to the host. Packets
addressed to other Ethernet IDs will be seen by the board, but ignored
(by default).
The Ethernet ID is a 12-digit number. This number is made up of three
bytes of manufacturer’s ID followed by another three bytes of a unique
identifier number. The Ethernet ID is what’s contained in the
Destination and Source fields of the Ethernet packet.
For Synergy boards, Synergy’s 3-byte manufacturer’s ID (00:80:F6) is
compiled into the Ethernet driver code as a macro. The second half of
the Ethernet ID is made up of the 7-digit SBC serial number that is
stored as 3 bytes of BCD (leading ‘1’ in board serial number ignored) in
these NVRAM locations:
•
•
NVRAM address 0xFFE9_E778: single processor, CPU-X
NVRAM address 0xFFE9_E774: dual processor, CPU-Y
Synergy’s 3-byte manufacturer’s ID is combined with the board serial
number to produce the Ethernet ID of the board’s Ethernet interface.
For example, for a board serial number of ‘1123456’, the Ethernet ID is
“00:80:F6:12:34:56”.
For more information on the VSS4 non-volatile SRAM, refer to the Nonvolatile 128K x 8 SRAM chapter in Section 4, page 143.
Avoiding bus contention — CSMA/CD
To avoid contention from two or more stations trying to talk at the
same time on the network, Ethernet uses a media access method called
CSMA/CD (Carrier Sense Multiple Access with Collision Detection).
With CSMA/CD, a station transmits a frame only when the network is
not busy. If a collision does occur after a transmission, the station
resolves it by retransmitting the frame.
❏
80
To avoid contention, stations monitor a carrier signal (an
encoded clock signal integrated with the data) that indicates
whether or not another station is transmitting. If a station has
data of its own to transmit and the network is not busy, it is sent
immediately. Otherwise, if the network is busy, the station waits
until it senses no activity plus an extra delay time padding for
channel recovery before transmitting its own data.
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Section 3: Basic Bus Descriptions
Fast Ethernet interface
❏
When a collision does occur, all stations are notified of the
occurrence by a signal applied to their Collision Detect input.
Any station that is currently transmitting must stop and wait a
certain amount of time before retransmitting the frame. The
station’s location on the network is factored into the time delay
to ensure that no overlap occurs with other stations that may
also be retransmitting their data. A packet less than the minimum
size (512 bits) is considered a collision remnant and is ignored
by the receiving station.
Interchange signals
Ethernet uses differential driver circuits for its interchange signals. For
the onboard 10/100Base-T interface, the transmit data and receive data
signals are transformer coupled internally on the SBC and routed to the
VSS4 front panel RJ-45 jack. The table below lists the interchange
signals and their pin assignments on the RJ-45 jack.
Ethernet interchange signals, RJ-45 pin assignments
P240, RJ-45 Pin
1
2
3
6
IEEE 802.3 Name
DO+ (Data Out +)
DO– (Data Out –)
DI+ (Data In +)
DI– (Data In –)
Function
Signal from:
Transmit Pair
VSS4
Receive Pair
External Device
2 4 6 8
1 3 5 7
Ethernet 10Base-T/100Base-TX connector pin numbering
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Section 3: Basic Bus Descriptions
Fast Ethernet interface
LED indicators
The VSS4 Ethernet interface is provided with three onboard LED
indicators for quick port status indication.
•
•
•
Link OK — lights up green when cable is connected to a
functioning 10Base-T/100Base-TX network.
Link Activity — flickers yellow whenever data is being received
or transmitted. If the VSS4 is connected to a repeater-type hub
instead of a switch-type hub, this LED may still flicker even when
the VSS4 is not transferring data since packets sent over the
network to other nodes will also be sent to the VSS4.
Link Speed — lights up orange if cable is connected to a
100Base-TX hub. LED is OFF if cable is connected to a 10Base-T
hub.
Refer to the LED discussion in Section 2 (page 20) for more
information.
82
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Programming the
PowerPC
4
This section provides programming and operation information for the
PowerPC processor and for other devices under its direct control.
•
PowerPC architecture
•
MPC106 PCI bridge/memory controller
•
Programming notes, MPC106
•
Address map
•
Onboard registers
•
L2 backside cache controller
•
Mailboxes
•
Asynchronous serial interface
•
Clock calendar
•
Non-volatile 128K x 8 SRAM
•
Boot Flash ROM/EPROM
•
User Flash memory
e
Not
The bit numbering of registers in this
section follows the zero-on-the-right
convention as opposed to the zero-onthe-left bit numbering convention used
by Motorola and IBM in their PowerPC
documentation.
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84
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Section 4: Programming the PowerPC
PowerPC architecture
PowerPC architecture
Introduction
The PowerPC processor is a RISC (Reduced Instruction Set Computer)
design of which development can be traced to IBM’s introduction of
the POWER (Performance Optimization With Enhanced RISC)
architecture of the RISC System/6000 in early 1990. The multi-chip
approach used by the microprocessor in this system lead to discussions
among IBM, Apple, and Motorola to collaborate on the design and
production of a more economical single chip solution. Thus was born
the PowerPC (“PC” stands for Performance Computing) family of RISC
processors starting with the 601 chip. The PowerPC architecture is
scalable so that it can take advantage of new technological
breakthroughs.
The PowerPC architecture defines the following features:
•
•
•
•
•
•
•
•
Separate registers for integer and floating point operations.
Integer data uses the general purpose registers (GPR) while
floating point data uses the floating point registers (FPR).
Instructions for moving integer and floating point data between
the registers (GPR and FPR) and memory.
Multiple execution units for parallel processing.
Uniform length instructions for easy instruction pipelining and
parallel processing.
Liberal use of registers (up to four) during arithmetic operations.
An exception handling mechanism.
IEEE-754 floating point support.
Single and double precision floating point operations.
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Section 4: Programming the PowerPC
PowerPC architecture
•
•
•
Separate L1 instruction and data caches.
Instructions for controlling L1 data cache coherency at the user
level.
Support for both big and little endian addressing.
Further information
For further PowerPC processor information, refer to the following
Motorola/IBM documentation:
•
•
The appropriate processor model User’s Manual
PowerPC Microprocessor Family: The Programmer's Reference
Guide (Document No. MPCPRG/D)
For these and other literature, contact:
Motorola Literature Distribution Center
P.O. Box 20912
Phoenix, AZ 85036
PowerPC information and documentation in PDF format is also
available at Motorola’s Semiconductor Products Sector website:
http://e-www.motorola.com/
Architecture models
There are three models within the PowerPC architecture:
1.
2.
3.
86
User model containing the user instruction set architecture
(UISA) registers. This model contains the GPR, FPR, condition,
floating point status and control, XER, link, and count registers.
These registers are accessible by all software all the time.
User model containing the virtual environment architecture
(VEA) registers. This model includes the UISA model and time
base facility registers. The time base facility registers are read
only in this model.
Supervisor model containing the operating environment
architecture registers. This model includes all the registers. In this
model the time base facility registers are read/write.
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Section 4: Programming the PowerPC
PowerPC architecture
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PowerPC programming model (7400)
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Section 4: Programming the PowerPC
PowerPC architecture
Register set
The PowerPC architecture defines register-to-register operations for
most computational instructions. For example, there are no instructions
that modify storage directly. For a storage operand to be used in a
computation that modifies the same or another location, the content of
storage must be loaded into a register, modified, and then stored back
to the target location.
The PowerPC programming model includes 32 general purpose
registers (GPRs), 32 floating point registers (FPRs), special purpose
registers (SPRs), and several miscellaneous registers. A PowerPC
processor also includes several processor-specific registers that are
excluded from the PowerPC programming model. These registers
provide functions unique to the processor and thus may not be
supported by other PowerPC processors.
The following paragraphs give a brief description of the PowerPC
register set. For more detailed register set information on a particular
processor, refer to that processor’s user’s manual.
General Purpose Registers (GPRs) — 32 user-level, general purpose
registers are defined in the PowerPC architecture. These registers are
either 32- or 64-bits wide in 32- and 64-bit wide PowerPC processors.
GPRs serve as the data source or destination for all integer instructions.
Floating Point Registers (FPRs) — 32 user-level, 64-bit wide floating point
registers are defined in the PowerPC architecture. These registers serve
as the data source or destination for floating-point instructions. FPRs
can contain either single- or double-precision floating-point data.
Condition Register (CR) — The CR is a 32-bit user-level register that is
used to show the results of certain operations such as move, integer
and floating-point compare, and provide a mechanism for testing and
branching.
Floating-point Status and Control Register (FPSCR) — The FPSCR
provides compliance to the IEEE 754 standard by containing all
exception signal bits, exception summary bits, exception enable bits,
and rounding control bits.
Machine State Register (MSR) — The MSR is a supervisor level register
that reflects the state of the processor. The contents of this register are
saved when an exception is taken and restored when the exception
handling routine completes. This is a 32- or 64-bit register depending on
the processor.
88
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Section 4: Programming the PowerPC
PowerPC architecture
Segment Registers (SRs) — SRs (16 ea. for 32-bit processors) are
provided for memory management.
Special Purpose Registers (SPRs) — Special purpose registers serve a
variety of functions. Some of these functions include control, status
indication, processor configuration, and other special operations. The
SPRs in PowerPC processors are 32-bits wide. A program accesses SPRs
according to its privilege level (user or supervisor).
Instruction set overview
All PowerPC instructions are encoded as single-word (32-bit) opcodes.
The PowerPC instructions are divided into the following categories:
•
•
•
•
•
Integer instructions — These include computational and logical
instructions.
− Integer arithmetic instructions
− Integer compare instructions
− Integer logical instructions
− Integer rotate and shift instructions
Floating-point instructions
− Floating-point arithmetic instructions
− Floating-point multiply/add instructions
− Floating-point rounding and conversion instructions
− Floating-point compare instructions
− Floating-point status and control instructions
Load/store instructions
− Integer load and store instructions
− Integer load and store multiple instructions
− Floating point load and store
− Integer load and store with byte reversal instructions
Flow control instructions
− Branch and trap instructions
− Condition register logical instructions
Processor control instructions
− Move to/from SPR instructions
− Move to/from MSR
− Synchronize
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Section 4: Programming the PowerPC
PowerPC architecture
•
− Instruction synchronize
− Order loads and saves
Memory control instructions
− Supervisor-level cache management instructions
− User-level cache instructions
− Segment register manipulation instructions
− Translation lookaside buffer management instructions
Detailed information on the PowerPC architecture can be found in the
“PowerPC™ Microprocessor Family: The Programming Environments”
manual available from IBM or Motorola.
PowerPC G4 processor
The PowerPC G4 (74xx) is a 4th generation PowerPC processor. This
processor is similar to the PowerPC G3 (750) with exception of the
G4’s 128-bit vector unit that operates concurrently with the 32-bit
integer and floating point units. The addition of the vector execution
unit is the basis for Motorola’s AltiVec™ technology.
With its AltiVec™ technology, the G4 provides for highly parallel
operations with the ability to execute up to 16 operations in a single
clock cycle. The G4 performs a type of parallel processing called SIMD
(single instruction, multiple data) which speeds high bandwidth
applications such as 3-D imaging/video processing, scientific array
processing, speech processing, etc.
The vector unit has 32 128-bit registers. Depending on data size, each
register can hold sixteen 8-bit elements, eight 16-bit elements, or four
32-bit elements. The vector unit’s ALU can operate on three source
vectors and produce a single result vector on each instruction (there are
162 AltiVec™ specific instructions). Hence, the smaller the data size,
the more data that can be processed in a single clock cycle.
Below is a simplified block diagram of PowerPC with AltiVec™
technology.
90
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Section 4: Programming the PowerPC
PowerPC architecture
Branch
Unit
INST INST INST
INST
INST
ADDR
Integer
Unit
Floating-Point
Unit
Vector
Unit
GPRs
FPRs
VRs
DATA
DATA
DATA
ADDR
DATA
Memory
Overview, PowerPC with AltiVec™ technology
Though there are numerous differences between G3 and G4 CPUs
(G4, for example, supports a 2 MB L2 cache), the G4 is still compatible
with the industry standard PowerPC architecture. For more detailed
information on the PowerPC 74xx and AltiVec™, refer to Motorola’s
SPS website:
http://e-www.motorola.com/
Summary of differences, 750 vs. 7400 Processor
•
•
•
•
•
Completion queue: 750 has 6-entry completion queue vs.
7400’s 8-entry completion queue. G4’s extra completion queue
entries reduce the opportunity for bottlenecks from the G4’s
additional execution units.
Floating point: 750 has 4-cycle latency for double-precision
floating-point multiply and 3-cycle latency for all other floating
point add and multiply. 7400 has 3-cycle latency for all floatingpoint add and multiply. As a result, the 7400 has equal latency
for double-precision and single-precision operations.
AltiVec™: 7400 has special vector execution units to implement
the AltiVec™ instruction set which speeds high bandwidth
applications via parallel processing (SIMD).
Memory subsystem: 7400 improves data flow with increased
queue sizes and queue additions.
L1 cache block allocation policy: 750 has allocate-on-miss policy.
7400 has allocate-on-reload policy. 7400’s block allocation
occurs in parallel with reload, which uses the cache more
efficiently (5 cycles for 7400 vs. 6 cycles for 750).
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Section 4: Programming the PowerPC
PowerPC architecture
•
•
L2 cache: 750 supports 1 MB max. L2 cache. 7400 supports 2
MB max. L2 cache. 7400 has fewer sectors per tag than the 750
allowing for more efficient caching. Moreover, the L2 cache
reload policy was changed in the 7400 to improve performance.
Processor bus: In addition to the 60x bus, the 7400 supports a
higher performance processor bus called the MPX bus (not
supported by VSS4).
7410 G4 Processor
Later revisions of the VSS4 SBC use the 7410, a 2nd generation G4
PowerPC processor. In comparison to the 7400, the 7410 has lower
power consumption and higher processor speeds. Other major
differences between the two G4 processors:
•
•
•
92
Private memory — can use L2 SRAM as direct-mapped private
memory.
L2 data bus width — can use either a 32- or 64-bit L2 data bus.
Processor version register — PVR data for 7410: 0x800C_1xxx.
PVR data for 7400: 0x000C_0xxx.
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
MPC106 PCI bridge/memory
controller
General description
The MPC106 PCI bridge/memory controller (aka Grackle) is an
integrated high-bandwidth, high-performance interface for:
•
•
•
•
PowerPC processor(s)
Secondary (L2) cache
Memory (EDO DRAM/SDRAM/ROM)
PCI bus
In addition to interface support, the MPC106 provides hardware
support for power management functions via register programming.
e
Not
For detailed information about the
MPC106, refer to the Motorola MPC106
User Manual MPC106UM/AD. This can
be obtained by contacting:
Motorola Literature Distribution Center
P.O. Box 20912
Phoenix, AZ 85036
Document descriptions and ordering
information can be found on Motorola’s
website on the WWW:
http://www.mot.com/SPS/
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
PowerPC processor interface
The MPC106 provides an interface to a variety of PowerPC processors
(up to 4) using a 32-bit address bus and a 64-bit data bus. The address
and data bus are decoupled for pipelining of 60x accesses. The
MPC106 processor interface supports full memory coherency and an
optional local bus slave.
Secondary (L2) cache interface
The MPC106 supports various combinations of L2 cache/60x
processors. For the VSS4, however, individual L2 backside cache is
provided for each processor, so the MPC106’s cache controller is not
used. This frees the MPC106 to support full arbitration and interface
functions for multiprocessor operation.
Memory interface
The MPC106 memory interface controls processor accesses to/from
main memory using a 64-bit data path. The memory configuration/size
and error checking scheme (normal parity, RMW parity, ECC) is
programmable.
ROM/Flash interfacing is also provided by the MPC106.
PCI access to/from main memory is provided by the PCI bus interface
(see next).
PCI bus interface
The MPC106 provides the PCI interface that connects to the processor
and memory buses. The MPC106 PCI interface is compliant with PCI
Local Bus Specification, Revision 2.1. The PCI bus is 32-bits wide and
runs at 33 MHz. Refer to the PCI bus description in Section 3 for more
information.
As a PCI interface, the MPC106 functions as both a master and target
device. As a PCI bus master, the MPC106 configures all PCI devices
using PCI configuration cycles in addition to supporting read/write
operations to PCI memory space and PCI I/O space. As a PCI target,
the MPC106 supports read/write operations to system memory.
94
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
Power management functions
The table below lists the power management functions supported by
the MPC106.
MPC106 power management functions
Mode
Full-On
Doze
Nap
Sleep
Suspend
Description
This is the normal operating mode.
All functions disabled except PCI address decoding, RAM refresh, CPU bus
requests, and NMI monitoring. The CPUs can continue to operate normally.
All functions disabled except PCI address decoding, RAM refresh, CPU bus
requests, and NMI monitoring. The CPUs are also in Nap mode. (603s will not
snoop, but 604s will. Flush 603 L1 caches before entering this mode.)
All functions disabled except RAM refresh, CPU bus requests, and NMI
monitoring. CPUs are also in sleep (or nap) mode.
All functions disabled except RAM refresh. (This mode not supported by VSS4
boards.)
Programming the MPC106
The Grackle must be programmed in order to:
•
Access RAM
•
Access PCI
•
Write to the serial ports
•
Write to the LEDs
•
Write to the board configuration registers
•
Enable CPU-Y, Z, and W
•
Enable and diagnose certain memory and PCI error conditions
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
MPC106 registers
The following is an overview of the MPC106 registers. For in-depth
register programming information, refer to the MPC106 User’s Manual
by Motorola.
Address maps
The MPC106 supports three address mapping configurations
designated address map A, address map B, and emulation mode
address map. Address map A conforms to the now-obsolete PowerPC
Reference Platform Specification (PREP). Address map B conforms to
the Common Hardware Reference Platform Architecture (CHRP). The
emulation mode address map, which is not used for VSS4 boards,
supports software emulation of x86 hardware. On reset, onboard
hardware selects address map B by default. After reset, the address map
can be changed by programming bit 16 in the MPC106’s Processor
Interface Configuration register 1 (PICR1). VSS4 boards default to
address map B for all models. Refer to the next chapter (Address map)
for more information on the address map structure.
Configuration registers
Using CHRP address map B, the base address of the Grackle chip is:
•
•
0xFEC0_0000, Address Register
0xFEE0_0000, Data Register
The OS initialization software sets up the MPC106 in the PCI
configuration space header. The PCI configuration space header format
is shown below. Note that Grackle operates in PCI memory space only
(write ‘2’ [0x0010] to command register to enable PCI memory access).
Access Grackle’s configuration registers 0x00–0xFC by writing
0x8000_00XX to 0xFEC0_0000 then reading or writing 32 bits only
to/from address 0xFEE0_0000. In both cases the data must be bytereversed as the PCI bus uses little-endian bit format whereas the
PowerPC bus uses big-endian bit format.
96
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
31
16 15
0
Device ID
0x0002
Status
Class Code
Subclass Code
Vendor ID
0x1057
Command 0x0000*
Standard
Revision ID
Programming
BIST Control
Header Type
Latency Timer
Cache Line Size
MAX GNT
MIN GNT
Interrupt Pin
Interrupt Line
—
Disconnect Cntr
Subordinate Bus No.
Bus Number
—
Special Cycle Address
—
PMCR2
Power Management Configuration
Memory Starting Address
Memory Starting Address
Extended Memory Starting Address
Extended Memory Starting Address
Memory Ending Address
Memory Ending Address
Extended Memory Ending Address
Extended Memory Ending Address
Pg. Mode Cntr/Timer
//// ////
Memory Enable
////////
Processor Interface Configuration 1
Processor Interface Configuration 2
Alternate OS Visible Alternate OS Visible
ECC Single Bit
ECC Single Bit
Params 2
Params 1
Trigger
Counter
60x Bus Error Status
////////
Error Detection 1
Error Enabling 1
PCI Bus Error Status
////////
Error Detection 2
Error Enabling 2
60x/PCI Error Address
Emulation Support Configuration 1
Modified Memory Status (No Clear)
Emulation Support Configuration 2
Modified Memory Status (Clear)
Memory Control Configuration 1
Memory Control Configuration 2
Memory Control Configuration 3
Memory Control Configuration 4
*Note:
0x00
0x04
0x08
0x0C
0x3C
0x40
0x44
0x70
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA4
0xA8
0xAC
0xB8
0xC0
0xC4
0xC8
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0xF8
0xFC
Bit 1 of the PCI command register, when set to a 1, enables MPC106 to respond to accesses to the
PCI Memory Address space.
Power management configuration registers
The power management configuration registers (PMCRs) control power
management functions of the MPC106.
Register Name
PMCR1
PMCR2
Size
half-word (16 bits)
byte
Address Offset
0x70
0x72
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
Error handling registers
The error handling registers control the MPC106’s error handling and
reporting.
Register Name
ECC single-bit error counter register
ECC single-bit error trigger register
ErrEnR1
ErrDR1
60x Bus error status register
ErrEnR2
ErrDR2
PCI bus error status register
60x/PCI error address register
Size
byte
byte
byte
byte
byte
byte
byte
byte
byte
Address Offset
0xB8
0xB9
0xC0
0xC1
0xC3
0xC4
0xC5
0xC7
0xC8
Memory interface registers
Memory boundaries (starting and ending addresses), memory bank
enables, memory timing, and external memory buffers are all controlled
by the memory interface configuration registers (MICRs).
Register Name
Memory starting address register 1
Memory starting address register 2
Ext. memory starting address register 1
Ext. memory starting address register 2
Memory ending address register 1
Memory ending address register 2
Ext. memory ending address register 1
Ext. memory ending address register 2
Memory bank enable register
Memory page mode register
MCCR1
MCCR2
MCCR3
MCCR4
98
Size
longword
longword
longword
longword
longword
longword
longword
longword
byte
byte
longword
longword
longword
longword
Address Offset
0x80
0x84
0x88
0x8C
0x90
0x94
0x98
0x9C
0xA0
0xA3
0xF0
0xF4
0xF8
0xFC
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
Processor interface configuration registers
The processor interface configuration registers (PICRs) control
programmable parameters of the PowerPC bus and L2 cache interface.
Register Name
PICR1
PICR2
Size
longword
longword
Address Offset
0xA8
0xAC
Alternate OS–Visible parameters registers
Operating systems have an alternate means to access some of the bits
of the PICR1 using the alternate OS-visible parameters registers.
Register Name
Alternate OS-visible parameters reg. 1
Alternate OS-visible parameters reg. 2
Size
byte
byte
Address Offset
0xBA
0xBB
Emulation support configuration registers
The emulation support configuration registers controls MPC106
operation in emulation mode. (Not used for VSS4 boards.)
External configuration registers
The external configuration registers allow access to certain
configuration bits when using Address map A (PREP).
Register Name
External configuration register 1
External configuration register 2
External configuration register 3
Size
byte
byte
byte
Address Offset
Port 0x092
Port 0x81C
Port 0x850
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Section 4: Programming the PowerPC
MPC106 PCI bridge/memory controller
100
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Section 4: Programming the PowerPC
Programming notes, MPC106
Programming notes, MPC106
Setting PCI device base address
Each PCI device has a standard set of configuration registers, accessed
with PCI configuration cycles using the Grackle’s CFG_ADDR @
0xFEC0_0000 and CFG_DATA @ 0xFEE0_0000 registers. Refer to the
‘type 0’ and ‘type 1’ configuration register tables from the PCI spec. The
standard Synergy Microsystems PowerPC SBC configuration addresses
for PCI devices are listed in the VxWorks svgm1.h header file.
Most OS's contain PCI configuration access routines. VxWorks, for
example, has readMPC and writeMPC:
readMPC(0x80006800);
returns a 32 bit value which is the VendorID and DeviceID registers of
the first PMC daughterboard, or 0xFFFF_FFFF if none exists. And...
writeMPC(0x80006810, 0xe00000000);
...writes the address 0xE000_0000 to a ‘type 0’ device’s configuration
register 0x10 (BAR0).
Each device defines some of its Base Address Registers to be the
address of a particular bank within it, usually additional registers or dualported memory. Bit 0 of the register specifies the PCI space in which it
is to be placed: 0 for PCI Memory and 1 for PCI I/O space. By first
writing 0xFFFF_FFFF to the register and reading it back, it is possible to
tell which bits are writable — those that aren’t won’t change. This tells
the size of the bank and whether it is fixed in a particular space.
On the PowerPC Series SBC, the allowed ranges for the PCI spaces are:
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Section 4: Programming the PowerPC
Programming notes, MPC106
Memory: base = 0xDFFF_0000 – 0xEFFF_FFFF
I/O: base = 0xFEB0_0000 - 0xFEBF_FFFF
You also need to enable the PCI device’s response to PCI Memory
space and/or PCI I/O space by setting the corresponding bits in the
device’s Command register; typically, bits 1 and 0 respectively.
The MPIC interrupt vector assigned to PCI Interrupt A is 13, and for B it
is 12.
Write posting to ROM Space
Problem
If you have a program that writes very frequently to that address region
which the Grackle considers to be “ROM space”, the Grackle services
those writes at the expense of other requests for memory access that
might happen at the same time. The ROM space includes everything at
high address range (any address that is 0xFFxx_xxxx). This includes the
ROMs that are meaningless to write to, but it also includes all the CPU
control registers, the LEDs being among them. So it is normal for the
CPU to make writes to this region even though it's considered ROM
space by the Grackle. This poses a problem as the Grackle gives priority
to write-posts writes to ROM space at the expense of other processes
waiting for Grackle’s services.
Observation
A program had a tight loop which was reading 8 bytes of data from a
file and then writing a number to the LEDs which caused 8 write
operations to ROM space. At the same time that was going on there
was lots of contention for the Grackle’s services: another CPU card
tried to make many accesses to the CPUs RAM through the VME
interface and onboard DMA transfers were occurring from the Ethernet
interface. The Grackle in effect gave priority to the writes to ROM
space (which it performed rather slowly, too) and serviced the DMA
and VMEbus requests in whatever time was left over. Occasionally, the
Grackle would make the Universe II chip wait longer than 16µs for the
memory access it requested. Since the VME timeout is set to the
standard value of 16µs, this longer than 16µs wait caused the VMEbus
system controller to generate a bus timeout — a bus error.
102
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Section 4: Programming the PowerPC
Programming notes, MPC106
Solution
Altering the LED writing routine solved the problem. After each write to
an LED, a read of that LED is performed. The LED read data itself is
ignored. The act of reading the LED register is what causes the Grackle
to resume paying attention to other pending Grackle accesses.
Bottom line: If frequent writes to ROM space are needed, intersperse
ROM space writes with ROM space reads whether or not you need the
data being read. It makes the Grackle give fairer access to the onboard
memory to the various competing sources of memory access requests.
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Section 4: Programming the PowerPC
Programming notes, MPC106
104
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Section 4: Programming the PowerPC
Address map
Address map
This chapter provides VSS4 address map information:
•
•
•
Overall CHRP address map, processor view and PCI master
(memory and I/O) view.
VSS4 address map as viewed by the PowerPC processor(s)
VSS4 address map as viewed by PCI devices
Additional information on the board’s memory spaces follows the
board address map listing.
CHRP address map
By default, the VSS4 uses a Common Hardware Reference Platform
(CHRP) compliant address map designated Address Map B.
Alternatively, the board can use Address Map A (PREP) by
programming the MPC106.
e
Not
For detailed information about the
MPC106, refer to the Motorola
MPC106
User’s
Manual
MPC106UM/AD. This can be obtained
by contacting:
Motorola Literature Distribution Center
P.O. Box 20912
Phoenix, AZ 85036
Document descriptions and ordering
information can be found on Motorola’s
website:
http://www.mot.com/SPS/
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Section 4: Programming the PowerPC
Address map
The tables below list Address Map B as viewed by the processor and as
viewed by PCI memory and I/O Masters. The figure following the tables
shows a graphical view of Address Map B. These tables are listed in
Motorola’s MPC106 User’s Manual with additional notes. Refer to the
MPC106 user’s manual for more information about Address Map B and
Address Map A (PREP).
Address map B — Processor view
PowerPC Processor Address Range
Hex
Decimal
0x0000_0000 0x0009_FFFF
0
640K–1
0x000A_0000 0x000B_FFFF
640K
768K–1
0x000C_0000 0x3FFF_FFFF
768K
1G–
0x4000_0000 0x7FFF_FFFF
1G
2G–1
0x8000_0000 0xFCFF_FFFF
2G
4G–48M–1
0xFD00_0000 0xFDFF_FFFF
4G–48M
4G–32M–1
0xFE00_0000 0xFE7F_FFFF
4G–32M
4G–24M–1
PCI
Address Range
No PCI cycle
0x000A_0000–0x000B_FFFF
No PCI cycle
No PCI cycle
0x8000_000–0xFCFF_FFFF
0x0000_0000–0x00FF_FFFF
0x0000_0000–0x0000_FFFF
0xFE80_0000
0xFEC0_0000
0xFEBF_FFFF
0xFEDF_FFFF
4G–24M
4G–20M
4G–20M–1
4G–18M–1
0x0080_0000–0x00BF_FFFF
CONFIG_ADDR
0xFEE0_0000
0xFEF0_0000
0xFF00_0000
0xFF80_0000
0xFEEF_FFFF
0xFEFF_FFFF
0xFF7F_FFFF
0xFFFF_FFFF
4G–18M
4G–17M
4G–16M
4G–8M
4G–17M–1
4G–16M–1
4G–8M–1
4G–1
CONFIG_DATA
0xFEFF_0000–0xFEFF_FFFF
0xFF00_0000–0xFF7F_FFFF
0xFF80_0000–0xFFFF_FFFF
Definition
System memory space
Compatibility hole
System memory space
Reserved
PCI memory space
PCI/ISA memory space 3
PCI/ISA I/O space (64Kbytes or
8 Mbytes)
PCI I/O space
PCI configuration address
register 1
PCI configuration data register 1
PCI interrupt acknowledge
64-bit system ROM space2
8- or 64-bit system ROM space3
Address map B — PCI memory master view
PCI Memory Transaction Address Range
Hex
Decimal
0x0000_0000 0x0009_FFFF
0
640K–1
0x000A_0000 0x000F_FFFF
640K
1M–1
0x0010_0000 0x3FFF_FFFF
1M
1G–1
0x4000_0000 0x7FFF_FFFF
1G
2G–1
0x8000_0000 0xFCFF_FFFF
2G
4G–48M–1
0xFD00_0000 0xFDFF_FFFF
4G–48M
4G–32M–1
0xFE00_0000 0xFEFF_FFFF
4G–32M
4G–16M–1
0xFF00_0000 0xFF7F_FFFF
4G–16M
4G–8M–1
0xFF80_0000 0xFFFF_FFFF
4G–8M
4G–1
PowerPC Processor
Address Range
0x0000_0000–0x0009_FFFF
0x000A_0000–0x000F_FFFF
0x0010_0000–0x3FFF_FFFF
0x4000_0000–0x7FFF_FFFF
No system memory cycle
0x0000_0000–0x00FF_FFFF
No system memory cycle
0xFF00_0000–0xFF7F_FFFF
0xFF80_0000–0xFFFF_FFFF
Definition
System memory space
Compatibility hole
System memory space
Reserved
PCI memory space
System memory space
Reserved
64-bit system ROM space2
8- or 64-bit system ROM space3
Notes: 1. Used for PCI configuration cycles.
2. Maps to unused space in VSS4.
3. Maps to VSS4’s onboard registers and all ROM/NVRAM.
4. Synergy does not use the compatibility hole, which needs to be explicitly enabled to be present. For the VSS4,
this space is part of the 1GB system memory (RAM) space allocation permitted by the CHRP address map.
106
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Section 4: Programming the PowerPC
Address map
Address map B — PCI I/O master view
PCI I/O Transaction Address Range
Hex
Decimal
0x0000_0000 0x0000_FFFF
0
0x0001_0000 0x007F_FFFF
64K
0x0080_0000 0x00BF_FFFF
8M
0x00C0_0000 0xFFFF_FFFF
12M
64K–1
8M–1
12G–1
4G–1
Processor View
0
PowerPC Processor
Address Range
No system memory cycle
No system memory cycle
No system memory cycle
No system memory cycle
PCI Master Memory View
0
System memory
640K
System memory
640K
Compatibility hole
768K
Definition
PCI/ISA I/O space
Reserved
PCI I/O space
Reserved
PCI Master I/O View
0
ISA bus ports
64K
Compatibility hole
1M
System memory
System memory
8M
PCI I/O space
12M
16M
16M
System memory
System memory
1G
BPM
1G
BPM
2G
TM
2G
TM
PCI memory
4G – 48M
PCI memory
4G – 48M
PCI/ISA memory
(0–16M)
TPM & BIO
4G – 32M
PCI/ISA bus port
64KB or 8MB space
4G – 24M
DIOT
4G – 32M
System memory1
(0-16M)
TPM & BIO
PCI I/O
4G – 20M
4G – 18M
4G – 17M
4G – 16M
4G
TIO
CONFIG_ADDR
TIO
4G – 20M
TIO
CONFIG_DATA
PCI Int Ack
System ROM space
(ROM or Flash)
4G – 16M
4G
System ROM space
(ROM or Flash)
Note: This view can be disabled.
4G
Reserved
Address map B
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Section 4: Programming the PowerPC
Address map
PCI configuration and address
To help in programming VSS4’s PCI devices, the table below lists each
PCI device with its Type 0 PCI configuration data and address.
Type 0 configuration for devices on VSS4
ID Sel
Vendor
Device ID
Manufacturer
Part No./Description
PCI Config. Address
0
0x1057
0x0002
Motorola
MPC106/PCI bridge, mem. ctrlr.
0x8000_0000
11
0x1014
0x0046
IBM
MPIC/multiproc. int. controller
0x8000_5800
12
0x1000
0x000D
Symbios
SYM53C885/SCSI controller
0x8000_6000
12.1
0x1000
0x0701
Symbios
SYM53C885/Ethernet controller
0x8000_6100
13
(Note 4)
(Note 4)
(Note 4)
PMC Slot1
0x8000_6800
14
(Note 4)
(Note 4)
(Note 4)
PMC Slot2 (Note 1)
0x8000_7000
15
0x1011
0x0026
DEC
21154/PCI-PCI bridge (Note 2)
0x8000_7800
17
0x10E3
0x0000
Tundra Semiconductor
Universe II/PCI–VME64 bridge
0x8000_8800
18
0x1011
0x0046
DEC
21554/PCI-PCI bridge (Note 3)
0x8000_9000
Notes:
108
1. PMC Slot2 present on select model Synergy SBCs.
2. This PCI-PCI bridge (21154) on PEX3 only.
3. This PCI-PCI bridge (21554) on SBC models VGM5 and VSS4 only.
4. Vendor and Device IDs set by PMC manufacturer.
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Section 4: Programming the PowerPC
Address map
VSS4 address map
The VSS4 address map as viewed by the PowerPC processor(s) and PCI
devices is shown in the tables below.
PowerPC Address Map
Address
0000_0000 - 01FF_FFFF
0000_0000 - 03FF_FFFF
0000_0000 - 07FF_FFFF
0000_0000 - 0FFF_FFFF
0000_0000 - 1FFF_FFFF
0000_0000 - 3FFF_FFFF
0000_0080
0000_00A0
0000_00C0
0000_00E0
4000_0000 - 7FFF_FFFF
8000_0000 - FCFF_FFFF
FD00_0000 - FDFF_FFFF
FE00_0000 - FE7F_FFFF
FE80_0000 - FEBF_FFFF
FEC0_0000 - FEDF_FFFF
FEE0_0000 - FEEF_FFFF
FEF0_0000 - FEFF_FFFF
FF00_0000 - FFDF_FFFF
FFE0_0000 - FFE7_FFFF
FFE0_0000 - FFE7_FFFF
FFE8_0000 - FFE9_FFEF
FFE9_FFF0 - FFE9_FFFF
FFEA_0000 - FFEF_FAFF
FFEF_FB00 - FFEF_FB07
FFEF_FB08 - FFEF_FB0F
FFEF_FB10 - FFEF_FB17
FFEF_FB18 - FFEF_FB1F
FFEF_FC00
FFEF_FC08
FFEF_FC10
FFEF_FC18
Device/address space description
RAM (32 MB)
RAM (64 MB)
RAM (128 MB)
RAM (256 MB)
RAM (512 MB)
RAM (1 GB)
Mailbox A Write
Mailbox B Write
Mailbox C Write
Mailbox D Write
Reserved (1 GB)
PCI Memory Space (2 GB-48 MB)
Reserved
PCI I/O Space (8 MB), 0-based
PCI I/O Space (4 MB), 0-based
PCI Configuration Address Reg (2 MB)
PCI Configuration Data Reg (1 MB)
PCI Interrupt Acknowledge (1 MB)
Reserved (14 MB)
Boot Flash ROM (lower 512 KB, ROMBoot)
EPROM (512 KB), FlashBoot
NVRAM (128 KB-16 bytes)
Real Time Clock/Calendar
Reserved
Serial Port B (8B)
Serial Port A (8B)
Serial Port D (8B)
Serial Port C (8B)
Mailbox A Read
Mailbox B Read
Mailbox C Read
Mailbox D Read
Access
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8 (WO) Note 2
D8 (WO) Note 2
D8 (WO) Note 2
D8 (WO) Note 2
—
D8, D16, D32 (RW)
—
D8, D16, D32 (RW)
D8, D16, D32 (RW)
D8, D16, D32 (RW)
D8, D16, D32 (RW)
D8, D16, D32 (RO)
D8 (RW), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 1
D8 (RW), D64 (RO)
D8 (RW), D64 (RO)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RO)
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109
Section 4: Programming the PowerPC
Address map
PowerPC Address Map (continued)
Address
FFEF_FD00
FFEF_FE00
FFEF_FE08
FFEF_FE10
FFEF_FE18
FFEF_FE20
FFEF_FE28
FFEF_FE30
FFEF_FE38
FFEF_FE40
FFEF_FE48
FFEF_FE50
FFEF_FE60
FFEF_FE68
FFEF_FE70
FFEF_FE80
FFEF_FE88
FFEF_FE90
FFEF_FE98
FFEF_FEA0
FFEF_FEA8
FFEF_FEB0
FFEF_FEB8
FFEF_FF30
FFEF_FF38
FFEF_FF40
FFEF_FF48
FFF0_0000 - FFF7_FFFF
FFF0_0000 - FFFF_FFFF
FFF8_0000 - FFFF_FFFF
FFF8_0000 - FFFF_FFFF
110
Device/address space description
8-bit User Switch Register
Board Type and Revision Reg
Special Mod and ECO Level Reg
Board Family and Feature Register
Board Status Register
CPU Status Register
CPU Timebase Register
L2 Cache Register
Memory Register
Flash ROM Register
P0•PCI Register
Flash Window Register
P0•PCI Interrupt Mask Register
P0•PCI Interrupt Assert/Pending Register
PCI Error Register
User LED 0 Register
User LED 1 Register
User LED 2 Register
User LED 3 Register
User LED 4 Register
User LED 5 Register
User LED 6 Register
User LED 7 Register
VME64 Slot Register
VME64 SysReset Register
Watchdog Enable Register
Watchdog Pet Register
EPROM (512 KB), ROMBoot
Boot Flash ROM (1 MB, FlashBoot)
Boot Flash ROM (upper 512 KB, ROMBoot)
User Flash Bank (512 KB)
Access
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RW)
D8 (RO)
D8 (RO)
D8 (RW)
D8 (RO)
D8 (WO)
D8 (RW)
D8 (RW)
D8 (RO)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RW)
D8 (RO)
D8 (RW)
D8 (WO)
D8 (WO)
D8 (RW), D64 (RO) Note 1
D8 (RW), D64 (RO) Note 1
D8 (RW), D64 (RO) Note 1
D8 (RW), D64 (RO) Note 3
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Section 4: Programming the PowerPC
Address map
PCI Memory Space Address Map
Address
0000_0000 - 00FF_FFFF
0000_0000 - 01FF_FFFF
0000_0000 - 03FF_FFFF
0000_0000 - 07FF_FFFF
0000_0000 - 0FFF_FFFF
0000_0000 - 1FFF_FFFF
0000_0000 - 3FFF_FFFF
0000_0080
0000_00A0
0000_00C0
0000_00E0
4000_0000 - 7FFF_FFFF
8000_0000 - FCFF_FFFF
FD00_0000 - FEFF_FFFF
FF00_0000 - FF7F_FFFF
FFE0_0000 - FFE7_FFFF
FFE0_0000 - FFE7_FFFF
FFE8_0000 - FFEF_FFFF
FFF0_0000 - FFF7_FFFF
FFF0_0000 - FFFF_FFFF
FFF8_0000 - FFFF_FFFF
FFF8_0000 - FFFF_FFFF
Device/address space description
RAM (16 MB)
RAM (32 MB)
RAM (64 MB)
RAM (128 MB)
RAM (256 MB)
RAM (512 MB)
RAM ( 1GB)
Mailbox A Write
Mailbox B Write
Mailbox C Write
Mailbox D Write
unused (1 GB)
PCI Memory Space (2 GB-48 MB)
Reserved (32 MB)
Reserved (8 MB)
Boot Flash ROM (lower 512 KB), ROMBoot
EPROM (512 KB), FlashBoot
Reserved
EPROM (512 KB), ROMBoot
Boot Flash ROM (1 MB), FlashBoot
Boot Flash ROM (upper 512 KB), ROMBoot
User Flash Bank (512 KB)
Access
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8–D64 (RW)
D8 (WO) Note 2
D8 (WO) Note 2
D8 (WO) Note 2
D8 (WO) Note 2
D8, D16, D32 (RW)
D8 (RO), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 1
D8 (RO), D64 (RO) Note 3
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Section 4: Programming the PowerPC
Address map
Address Map Table Notes:
Note 1:
The Boot Flash ROM and EPROM devices have specific locations and accesses depending on whether the board
is configured to boot from Flash (FlashBoot) or DIP EPROM (ROMBoot). This is summarized below:
FlashBoot mode (Boot ROM Enable jumper not installed): The system boots from Boot Flash ROM at location
FFF0_0100. The entire device is addressed at FFF0_0000 - FFFF_FFFF and is D8 read/write if Flash Write
Protect jumper (J02L pins 9 & 10 for Rev. B or lower boards, J02L pins 21 & 22 for Rev. C or higher boards) not
installed and if FlashWP bit is not on; otherwise, device is read-only. EPROM is addressed at FFE0_0000 FFE7_FFFF. The EPROM/Flash ROM address map for FlashBoot is shown below:
Address Map, FlashBoot
Address
FFE0_0000 - FFE7_FFFF
FFF0_0000 - FFFF_FFFF
Device/address space description
EPROM (512 KB)
Boot Flash ROM
Access
D8 (RW), D64 (RO)
D8 (RW), D64 (RO)
ROMBoot mode (Boot ROM Enable jumper installed): The system boots from EPROM at location FFF0_0100.
EPROM is addressed at FFF0_0000 - FFF7_FFFF. Boot Flash ROM is read/write and is split-addressed at
FFE0_0000 - FFE7_FFFF and FFF8_0000 - FFFF_FFFF. Flash ROM reading/programming code must deal with
the address discontinuity to properly access the device. The EPROM/Flash ROM address map for ROMBoot is
shown below:
Address Map, ROMBoot
Address
FFE0_0000 - FFE7_FFFF
FFF0_0000 - FFF7_FFFF
FFF8_0000 - FFFF_FFFF
Note 2:
Note 3:
112
Device/address space description
Boot Flash ROM (lower half)
EPROM (512 KB)
Boot Flash ROM (upper half)
Access
D8 (RW), D64 (RO)
D8 (RW), D64 (RO)
D8 (RW), D64 (RO)
Mailbox writes are done by writing an 8-bit value to memory. To ensure proper operation, disable cache for page 0
of memory.
User Flash is selected by setting bit 7 of the Flash Window Register (0xFFEF_FE50). This register also addresses
a particular 512 KB bank of User Flash. The number of available User Flash banks depends on the amount of
User Flash installed in the system. User Flash and the upper 512 KB of Boot Flash cannot be accessed at the
same time. Access routines in application programs must be mutually exclusive when both Boot Flash and User
Flash are used.
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Section 4: Programming the PowerPC
Onboard registers
Onboard registers
This chapter describes the contents and use of the onboard registers
that monitor and control the operation of various features and functions
on VSS4 boards. All registers described in this chapter are 8-bits wide
and limited to PowerPC bus accesses only. The onboard registers fall
into one of three categories:
•
•
•
Board information registers — are read-only registers that
provide the system with ID and configuration information.
Status registers — are read-only registers that indicate the status
or condition of on-board devices or processes. Using these
registers involves reading the register and interpreting the bit
pattern found there.
Control/Mode registers — are read/write registers that set up the
board to perform a given operation or function. Using a
Control/Mode register involves writing a particular hex value to
the register’s address location. A read of the control/mode
address location gives the current value of the register.
The following register descriptions include address location, access
mode (read/write [RW], write-only [WO] or read-only [RO]), bit
description, and a brief summary of what it does.
The register bit description uses the notation listed below in each bit
position to show the register’s value after a board reset (i.e., power
cycling or system reset).
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Section 4: Programming the PowerPC
Onboard registers
Register bit description notations for reset value
Notation
x
—
1
0
What it means
Unused bit; set to 0 for future compatibility
Read-only bit
Set to 1 upon reset
Set to 0 upon reset
Board information registers
VSS4 board information registers include:
•
Board type and revision register
•
Special mod and ECO level register
•
Board family and feature register
•
L2 cache register
•
Memory register
•
Secondary PCI slot register
•
VME64 slot register
Board type and revision register, 0xFFEF_FE00 (RO)
Bit 7
0
6
1
5
4
0
0
3
2
1
0
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7–b4
Function
Board Type
b3–b0
Revision Level
Values
0x1 = VGM1
0x2 = VGM2
0x4 = VSS4
0x5 = VGM5
0xC = VGMC
0xD = VGMD
0x0 = a
0x1 = b
0x2 = c
↓
0xF = p
:
A byte read of this register reveals the board type (higher order nibble)
and board revision level (lower order nibble).
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Section 4: Programming the PowerPC
Onboard registers
Special mod and ECO level register, 0xFFEF_FE08 (RO)
Bit 7
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7–b4
Function
Special Mod
b3–b0
ECO Level
Values
0x0 = none
0x1 = ________
0x2 = ________
0x4 = ________
0x5 = ________
0x6 = ________
0x0 = none
0x1 = 1
0x2 = 2
↓
:
0xF = 15
A byte read of this register reveals the special modification code (higher
order nibble) and ECO level of the board (lower order nibble). Space is
provided above to write in the special mod to the code that applies to
your board.
Board family and feature register, 0xFFEF_FE10 (RO)
Bit 7
0
6
0
5
4
0
1
3
2
1
0
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7–b4
Function
Board Family
b3–b0
Reserved
Values
0 = VGM Series
1 = VSS Series
2 = KGM Series
3 = VGR Series
—
A byte read of this register reveals the board’s special features, if any,
and the board family to which it belongs.
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Section 4: Programming the PowerPC
Onboard registers
L2 cache register, 0xFFEF_FE30 (RO)
Bit 7
0
6
0
5
4
0
0
3
0
2
0
1
0
0
0
Reset value
Bit assignments:
Bit(s)
b7-b2
b1-b0
Function
Reserved
L2 Clock Ratio (CPU core to L2 frequency
divider)
Values
—
0 = 1:1.0
1 = 1:1.5
2 = 1:2.0
3 = Reserved
This read-only register returns the CPU’s L2 clock ratio based on the
relative clock speed of the processor and L2 SRAM parts that are
installed on the board. This value must then be programmed into the
CPU’s L2 cache control registers for the L2 cache to function properly.
Memory register, 0xFFEF_FE38 (RO)
Bit 7
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7–b6
Function
Type of Memory
b5–b3
Memory per Bank
b2–b0
Number of Banks
Values
0 = SDRAM, 15nS, CL=2, Flow-Thru
1 = SDRAM, 15nS, CL=2, Registered
2 = reserved
3 = reserved
0 = 8 MB
1 = 16 MB
2 = 32 MB
3 = 64M B
4 = 128 MB
0 = no memory
1 = 1 bank
2 = 2 banks
3 = 4 banks
4 = 8 banks
A byte read of this register provides information on the board’s installed
memory. Information provided in this register includes number of
banks, capacity per bank, and type of memory used (SDRAM type,
etc.).
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Section 4: Programming the PowerPC
Onboard registers
Secondary PCI Slot register, 0xFFEF_FE48 (RO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
—
Reset value
Bit assignments:
Bit(s)
b7–b1
b0
Function
Reserved
Sec. PCI Bus Slot controller Indicator
Values
—
0 = Not System Controller
1 = System Controller
A byte read of this register informs which CPU board is responsible for
configuring the P0•PCI™ bus map. If b0 = 0, the SBC configures the
P0•PCI™ bus map. If b0 = 1, a CPU board on the secondary (external)
PCI bus configures the P0•PCI™ bus map.
VME64 Slot register, 0xFFEF_FF30 (RO)
Bit 7
x
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7
b6
Function
Reserved
Slot Number Source
b5
Valid/Invalid Geographical Address
b4–b0
Binary Encoded Slot Number
Values
—
0 = Manual, Slot Jumper Field (J02L)
1 = Auto, VME64x Geographical Address
0 = invalid
1 = valid
1 = slot 1
2 = slot 2
↓
:
21 = slot 21
A byte read of this register returns information on the board’s VME64x
slot number assignment. The five lower order bits make up the binary
encoded slot number. Additional bits show whether or not the VME64x
geographical address is valid, and the source of the slot number
assignment (board’s jumper field [J02L] or board’s geographical address
pins). (This register present on Rev. C or higher boards only.)
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Section 4: Programming the PowerPC
Onboard registers
Status registers
VSS4 status registers include:
•
Eight-bit user switch register
•
Board status register
•
CPU status register
Eight-bit user switch register, 0xFFEF_FD00 (RO)
Bit 7
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7
Function
Switch 7
b6
Switch 6
b5
Switch 5
b4
Switch 4
b3
Switch 3
b2
Switch 2
b1
Switch 1
b0
Switch 0
Values
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
0 = Off
1 = On
A read of this register shows the setting of the 8-position front panel
switch.
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Section 4: Programming the PowerPC
Onboard registers
Board status register, 0xFFEF_FE18 (RO)
Bit 7
x
6
x
5
4
x
x
3
2
1
0
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7-b4
b3-b2
Function
Reserved
PowerPC Bus Speed
Values
—
0 = 66MHz
1 = 83MHz
2 = 100MHz
3 = undefined
Board Ejector Handle Switches*
0 = Both eject handle switches are closed
1 = one/both eject handles switch(es) open
Fail LED
0 = OFF
1 = ON
This bit valid only for boards with locking ejector handle option.
b1
b0
NOTE:
A read of this register shows the status of the board’s FAIL LED (ON or
OFF) and the PowerPC bus speed.
CPU status register, 0xFFEF_FE20 (RO)
Bit 7
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7
b6
b5
b4
b3-b2
b1-b0
NOTE:
Function
CPU-W status
Values
0 = Halted
1 = Running
CPU-Z status
0 = Halted
1 = Running
CPU-Y status
0 = Halted
1 = Running
CPU-X status
0 = Halted
1 = Running
Number of CPUs
0=4
1=1
2=2
3=3
CPU ID*
0=W
1=Y
2=Z
3=W
This is a processor-dependent register. All CPUs access the same address, but the information in
b1-b0 identifies which CPU is performing the read.
A read of this register returns the status of the CPU(s) on the board.
Information in this register includes the CPU ID of the processor doing
the read, the total number of CPUs on the board, and the halt/run
status for all onboard CPUs.
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Section 4: Programming the PowerPC
Onboard registers
Control/Mode registers
VSS4 control/mode registers include:
CPU timebase register
Flash ROM register
Flash Window register
PCI error register
P0•PCI interrupt assert/pending register
P0•PCI interrupt mask register
User LED registers
VME64 SysReset register
Watchdog enable register
Watchdog pet register
•
•
•
•
•
•
•
•
•
•
Using Control/Mode register functions
Activating a Control/Mode register function involves writing the
appropriate hexadecimal data value to the appropriate register.
For example, turning on LED 0 would require writing 0x01 to the User
LED register at 0xFFEF_FE80 using the following PowerPC instructions:
lis
ori
li
stb
3,
3,
4,
4,
0xFFEF
3, 0xFE80
1
0 (3)
CPU Timebase register, 0xFFEF_FE28 (RW)
Bit 7
x
6
x
5
4
x
x
3
1
2
1
1
1
0
1
Reset value
Bit assignments:
120
Bit(s)
b7-b4
b3
Function
Reserved
CPU-W Timebase Enable
b2
CPU-Z Timebase Enable
b1
CPU-Y Timebase Enable
b0
CPU-X Timebase Enable
Values
—
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
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Section 4: Programming the PowerPC
Onboard registers
A write to this register enables (1) or disables (0) the CPU’s (X, Y, Z or
W) internal timebase generator. This internal timebase generator is a
free running counter that runs at the CPU’s core frequency. Software
can use this free running counter to determine the speed at which the
processor is running, or other timing functions as required. A read of
this register returns the status of the timebase enables/disables.
Flash ROM register, 0xFFEF_FE40 (RW)
Bit 7
—
6
—
5
4
x
x
3
x
2
x
1
x
0
1
Reset value
Bit assignments:
Bit(s)
b7
b6
b5-b1
b0
NOTE:
Function
Boot ROM Enable jumper, J02L 1 & 2 (RO)
Values
0 = Jumper OFF (Boot Source is Boot Flash)
1 = Jumper ON (Boot Source is DIP EPROM)
Flash ROM Write Protect Jumper,
0 = Jumper OFF (no write protect)
J02L, 9 & 10 or 21 & 22 (RO) [see text]
1 = Jumper ON (write protect)
Reserved
—
Software Flash ROM Write Protect (RW) *
0 = Flash ROM not write-protected
(jumper ON** overrides this)
1 = Flash ROM write-protected
(set bit overrides jumper OFF)
* When Flash ROM is not write-protected, only CPU-X has access to it.
** Jumper refers to J02L Flash Write Protect jumper.
This register addresses the board’s Flash ROM operation.
Bit 0 of this register is a software Flash write-protect bit. Setting this bit
protects Flash from writes even if the Flash write protect jumper (J02L)
is removed. Clearing this bit allows Flash to be written provided that the
J02L Flash write protect jumper is also removed and that the MPC106
ROM write protect bit has not been set since the last board reset.
A read of bit 6 indicates the state of the Flash write protect jumper
(J02L pins 9 & 10 for Rev. B or lower, J02L pins 21 & 22 for Rev. C or
higher). When 1, the Flash write protect jumper is ON for Flash write
protection. When 0, the Flash write protect jumper is OFF to enable
Flash writes. However, this is true only if the write-protect bit (b0) of this
register is cleared and if the MPC106 ROM write-protect bit has not
been set since the last board reset.
Flash write protection indicated or set by this register applies to Boot
Flash, User Flash, and Flash EPROM (if installed) in the DIP EPROM
socket.
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Section 4: Programming the PowerPC
Onboard registers
A read of bit 7 indicates the state of the Boot ROM enable jumper
(J02L pins 1 & 2) which selects between two possible boot sources.
When 0, the jumper is OFF and boot is from Boot Flash. When 1, the
jumper is ON and boot is from DIP EPROM.
Refer to the Setting up the VSS4 hardware chapter (page 23) for more
information on the Flash write protect jumper and the Boot ROM
enable jumper.
Flash Window register, 0xFFEF_FE50 (WO)
Bit 7
0
6
0
5
4
0
0
3
0
2
0
1
0
0
0
Reset value
Bit assignments:
Bit(s)
b7
Function
User Flash Select
b6-b0
User Flash 512K Bank Select
Values
0 = Boot Flash
1 = User Flash
4 MB = 0x00–0x87 (8 banks)
8 MB = 0x00–0x8F (16 banks)
16 MB = 0x00–0x9F (32 banks)
32 MB = 0x00–0xBF (64 banks)
64 MB = 0x00–0xEF (128 banks)
This write-only register selects which Flash memory, User Flash or Boot
Flash, appears at address range 0xFFF8_0000–0xFFFF_FFFF (512 KB).
When User Flash is selected (b7 = 1) a particular 512 KB bank or
window of that memory is addressed by bits b6-b0. As shown in the
diagram above, the total available 512 KB banks of Flash memory
depend on the amount of User Flash installed on the board.
With User Flash selected, only the lower 512 KB of Boot Flash is
accessible. With Boot Flash selected, the entire 1 MB of Boot Flash is
available for use.
This register returns an undefined value when read.
Refer to the User Flash memory chapter in this section (page 153) for
more information.
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Section 4: Programming the PowerPC
Onboard registers
PCI error register, 0xFFEF_FE70 (RO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
0
—
—
Reset value
Bit assignments:
Bit(s)
b7-b2
b1
Function
Reserved
System Error (SErr)
b0
Parity Error (PErr)
Values
—
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
To maximize the use of available MPIC interrupts, the local PCI parity
and system error signals are combined into one interrupt source (Int
#4). When this interrupt source is asserted, the PCI error register tells
the CPU the type of error, parity or system, originally generated by the
local PCI.
P0•PCI interrupt assert/pending register, 0xFFEF_FE68 (RW)
Bit 7
—
6
x
5
4
3
2
1
0
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7
Function
P0•PCI Bridge Interrupt (read only)
b6
b5
Reserved
P0•PCI System Error (read only)
b4
P0•PCI Parity Error (read only)
b3
P0•PCI Interrupt D
b2
P0•PCI Interrupt C
b1
P0•PCI Interrupt B
b0
P0•PCI Interrupt A
Values
0 = not asserted
1 = asserted
—
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
0 = not asserted
1 = asserted
Setting b3–b0 of the P0•PCI interrupt assert/pending register asserts a
PCI interrupt (Int A–D) on the P0 side of the PCI-PCI bridge. Clearing
b3–b0 deasserts the corresponding interrupt. A read of this register
returns the current state of the P0•PCI interrupt signals. If it is not
desired for the board to see any or all of these interrupts coming
elsewhere from the bus, use the P0•PCI interrupt mask register to
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Section 4: Programming the PowerPC
Onboard registers
prevent any of these interrupts from being passed on to the board. See
next.
P0•PCI interrupt mask register, 0xFFEF_FE60 (RW)
Bit 7
x
6
x
5
4
1
1
3
1
2
1
1
1
0
1
Reset value
Bit assignments:
Bit(s)
b7-b6
b5
Function
Reserved
P0•PCI System Error Mask
b4
P0•PCI Parity Error Mask
b3
P0•PCI Interrupt D Mask
b2
P0•PCI Interrupt C Mask
b1
P0•PCI Interrupt B Mask
b0
P0•PCI Interrupt A Mask
Values
—
0 = interrupt enabled
1 = interrupt disabled (masked)
0 = interrupt enabled
1 = interrupt disabled (masked)
0 = interrupt enabled
1 = interrupt disabled (masked)
0 = interrupt enabled
1 = interrupt disabled (masked)
0 = interrupt enabled
1 = interrupt disabled (masked)
0 = interrupt enabled
1 = interrupt disabled (masked)
The P0•PCI interrupt mask register enables/disables the board’s
processing of P0•PCI interrupts. This is necessary since the board is
sharing interrupts when other boards are connected to the P0•PCI
interface. Setting a bit masks the corresponding interrupt, which
prevents it from being seen by the board. Clearing a bit passes the
corresponding interrupt to the board, which enables it to act on the
interrupt.
User LED registers, 0xFFEF_FE80, 0xFFEF_FE88,
0xFFEF_FE90, 0xFFEF_FE98, 0xFFEF_FEA0,
0xFFEF_FEA8, 0xFFEF_FEB0, 0xFFEF_FEB8 (RW)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
1
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
User LED n
(n = 0, 1, 2, 3, 4, 5, 6, 7)
Values
—
0 = OFF
1 = ON
There are eight User LED registers, one for each user LED. A write to
one of these registers turns ON or OFF the appropriate user LED. A
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Section 4: Programming the PowerPC
Onboard registers
read of one of these registers returns the ON/OFF status of the
appropriate user LED.
VME64 SysReset register, 0xFFEF_FF38 (RW)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
1
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
VME64 SysReset
Values
—
0 = Board does not respond to its own
SysReset
1 = Board does respond to its own SysReset
A write to this register sets whether or not the board responds to its
own SysReset. A read of this register returns the value of the bits setting
this register. (This register present on Rev. C or higher boards only.)
Refer to External VME SysReset in Section 5 (page 161) for details on
the use of this register.
Watchdog enable register, 0xFFEF_FF40 (WO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
0
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
Watchdog Enable
Values
—
0 = Watchdog disabled. No need to service
watchdog.
1 = Watchdog enabled. Periodic writes to
Watchdog Pet register (see next register
description) is required to prevent board
reset.
Setting b0 of this write-only register to ‘1’ enables the watchdog timer
function. Once watchdog is enabled, the application code must
periodically write to the watchdog pet register (see next) to avoid reset.
An enabled watchdog can only be disabled by a board reset after
which b0 is automatically set to 0. Refer to Section 5 Reset (page 157)
for detailed reset information. (This register present on Rev. C or higher
boards only.)
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Section 4: Programming the PowerPC
Onboard registers
Watchdog pet register, 0xFFEF_FF48 (WO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
0
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
Watchdog Service
Values
—
Write alternating 0 and 1 to this bit within
250 ms to prevent board reset. This register
has no effect if watchdog is disabled.
The watchdog is held off from resetting the board by periodic writes
alternating between 0 and 1 to the watchdog pet register b0. A 0-to-1
transition at least once every 250 milliseconds is required. The code
may twiddle this bit as often as it likes as long as this maximum time is
not exceeded. This periodic writing to the watchdog pet register is
typically done in the main polling loop of the application program.
Should the program fail to write to the watchdog pet register, the
watchdog times out and the board/system is reset. Refer to Section 5
Reset (page 157) for detailed reset information. (This register present on
Rev. C or higher boards only.)
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Section 4: Programming the PowerPC
Backside L2 cache controller
Backside L2 cache controller
The 750/7400/7410 processor has an onboard L2 cache controller with
a dedicated port to the external synchronous SRAMs (1 MB for Rev. D
or lower boards, 1 MB or 2 MB for Rev. E or higher boards). The L2
backside cache maintains cache coherency through snooping and is
normally configured for copyback mode.
For the 750 G3 processor, the L2 cache is a two-way set associative tag
memory with 4096 tags per way. With 1 MB of SRAM, the L2 tags are
configured for four sectors (128 bytes) per L2 cache block.
For the 7400/7410 G4 processor, the L2 cache is a two-way set
associative tag memory with 8K tags per way. The tags are sectored
depending on L2 cache size. A 1 MB L2 cache supports 2 cache line
blocks per tag entry (2 sectors, 64 bytes. A 2 MB L2 cache supports 4
cache lines blocks per tag entry (4 sectors, 128 bytes).
Because the cache runs at or near the CPU core frequency and has its
own bus to the cache SRAMs, the 750/7400/7410’s performance is
noticeably improved over similar processors running at the same speed.
When a CPU read memory access is detected:
1.
2.
3.
It looks in its L1 cache to service the CPU request. If not in L1, it
looks in L2.
If what the CPU wants is in either L1 or L2, it’s a “hit” and the
CPU fetches the data without using a memory access cycle.
If the requested data is not in either L1 or L2 cache, it’s a “miss”
and the CPU accesses the main memory for the data using the
Grackle.
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Section 4: Programming the PowerPC
Backside L2 cache controller
For a memory write, the backside L2 cache will “copy-back” the write:
1.
The CPU, due to an L1 cache castout, writes data to memory (so
it thinks).
2.
The backside L2 cache captures the write and stores the data.
3.
If the L2 cache write caused an L2 castout because that cache
line was already used, then the L2 cache writes (copies back) the
previous data to memory.
How to use the backside L2 cache
The configuration of the backside L2 cache including the enable/disable
status is set by the processor’s L2 cache control register (L2CR). The
VSS4 is provided with an onboard register at 0xFFEF_FE30 to discover
the proper L2 clock ratio. Information on this register is found in this
section on page 116. Refer to the Motorola 750/7400/7410 User’s
Manual for more information about the backside L2 cache interface
operation.
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Section 4: Programming the PowerPC
Mailboxes
Mailboxes
The VSS4 provides four 8-bit wide mailboxes for interprocessor
communication. Each mailbox generates an interrupt while it contains
any data.
The mailbox write addresses are in RAM space, which is accessible by
all memory owners including either CPU, all PCI masters including PMC
cards and the Universe VME slave. The mailbox read registers are
located in ROM space, and are readable only by the CPUs.
Mailboxes A–D are typically used to interrupt CPU-X, CPU-Y, CPU-Z
and CPU-W respectively. This interrupt steering is programmed by the
user into the MPIC interrupt controller, and may be changed if needed.
Refer to Section 6 MPIC Interrupt Controller (page 165) for more
information on the MPIC.
Each mailbox contains a FIFO containing 256 storage locations, which
allows up to 256 pending messages in each mailbox. This provides
buffering for multiple near-simultaneous messages from many different
processes. Messages written to the mailbox will be read by the CPU in
the order they were received.
e
Not
For proper operation of the mailbox
write function, set memory page
0x0000_0000 to non-cacheable mode
in the MMU.
Any processor, but no other device (e.g., a PMC card), is allowed to
read a mailbox. This restriction is in place to prevent CPU interrupts
from being mishandled. Reading the mailbox will return the least
recently written value and will cause that entry to be removed from the
FIFO. When all pending mailbox data has been read, the interrupt will
be cleared. The ISR does not need to read all data from the FIFO; in
fact, it's best to have the interrupt routine read one entry from the
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129
Section 4: Programming the PowerPC
Mailboxes
mailbox and return to program execution. If additional data is in the
mailbox, the interrupt will still be active and the ISR will be entered
again automatically.
Mailbox addresses are listed below.
Mailbox read/write addresses
Mailbox
Mailbox A
Mailbox B
Mailbox C
Mailbox D
Write
0x0000_0080
0x0000_00A0
0x0000_00C0
0x0000_00E0
Read
0xFFEF_FC00
0xFFEF_FC08
0xFFEF_FC10
0xFFEF_FC18
The mailbox write may be any data size, but only the byte of data at
exactly the specified address (i.e., the most significant byte) will be
written to the FIFO.
130
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Section 4: Programming the PowerPC
Asynchronous serial interface
Asynchronous serial interface
The VSS4’s asynchronous serial ports are provided by Exar
Corporation’s ST16C654 quad UART chip. The four serial channels
(A–D) are brought out to a single RJ-69 jack on the front panel.
The ST16C654 features 64 bytes of transmit and 64 bytes of receive
FIFO per channel. This reduces overall UART interrupt servicing time,
which allows the CPU extra time to run other processes (multitask).
e
Not
For more information about
programming the ST16C654, refer to
the Exar ST16C654 datasheet. This can
be obtained by contacting:
EXAR Corporation,
48720 Kato Road
Fremont, CA 94538
(510) 668-7000
FAX (510) 668-7017
The datasheet is also available on Exar’s
website:
http://www.exar.com/products/st16c654.pdf
Registers
The ST16C654 provides 14 internal registers per channel for monitoring
and control. These registers are summarized in the table below.
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131
Section 4: Programming the PowerPC
Asynchronous serial interface
Asynchronous serial interface registers, ST16C654
Address
Offset
Register
[Default]1 R/W
General Register Set
0x0
RHR[XX]
R
0x0
THR[XX]
W
0x1
IER
W
[0x00]
b7
b6
b5
b4
b3
b2
b1
b0
bit-7
bit-7
CTS
bit-6
bit-6
RTS
interrupt
bit-5
bit-5
Xoff
interrupt
bit-4
bit-4
Sleep
mode
bit-3
bit-3
modem
status
interrupt
bit-1
bit-1
transmit
holding
interrupt
bit-0
bit-0
receive
holding
register
RCVR
trigger
(MSB)
FIFO’s
enabled
RCVR
trigger
(LSB)
FIFO’s
enabled
set
break
TX
trigger
(LSB)
INT
priority
bit-3
even
parity
DMA
mode
select
INT
priority
bit-2
parity
enable
IR
enable
Xon Any
loop
back
-OP1
FIFO
data
error
CD
trans.
empty
break
interrupt
parity
error
overrun
error
RI
trans.
holding
empty
DSR
-OP2/
INTx
enable
framing
error
RCVR
FIFO
reset
INT
priority
bit-0
word
length
bit-1
-RTS
FIFO
enable
divisor
latch
enable
Clock
select
TX
trigger
(MSB)
INT
priority
bit-4
set
parity
bit-2
bit-2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit-1
stop bits
CTS
delta CD
delta
-RI
delta DSR
receive
data
ready
delta CTS
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
bit-7
bit-15
bit-6
bit-14
bit-5
bit-13
bit-4
bit-12
bit-3
bit-11
bit-2
bit-10
bit-1
bit-9
bit-0
bit-8
Auto
CTS
Auto
RTS
Special
Char.
select
Enable
IER Bits
4-7, IAR,
FCR Bits
4-5, MCR
Bits 5-7
Cont-3
Tx/Rx
Control
Cont-2
Tx/Rx
Control
Cont-1
Tx/Rx
Control
Cont-0
Tx/Rx
Control
RW
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
RW
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
RW
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
RW
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
0x2
FCR
W
0x2
ISR
[0x01]
R
0x3
LCR
[0x00]
W
0x4
MCR
[0x00]
W
0x5
LSR
[0x60]
R
0x6
MSR
R
[0xX0]
0x7
SPR
RW
[0xFF]
Baud Rate Register Set 2
0x0
DLL[XX]
RW
0x1
DLM[XX]
RW
Enhanced Register Set 3
0x2
EFR
RW
[0x00]
0x4
0x5
0x6
0x7
132
Xon-1
[0x00]
Xon-2
[0x00]
Xoff-1
[0x00]
Xoff-2
[0x00]
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INT
status
word
length
bit-0
-DTR
Section 4: Programming the PowerPC
Asynchronous serial interface
Notes:
1. The value between the square brackets represents the register’s initialized HEX value.
2. The Baud Rate register set is accessible only when LCR bit-7 is set to “1”.
3. Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when LCR is set to 0xBF.
For detailed register descriptions, refer to the ST16C654 datasheet.
Serial I/O address map
Listed below are the base addresses of the four serial ports. To calculate
a serial port register address, add the serial port’s base address given
below to the Address Offset listed in the left-hand column of the table
on the previous page.
Serial port base addresses
Address
Port
0xFFEF_FB08
A
0xFFEF_FB00
B
0xFFEF_FB18
C
0xFFEF_FB10
D
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133
Section 4: Programming the PowerPC
Asynchronous serial interface
Programmable baud rate generator
A 24.0000 MHz clock oscillator provides input to the ST16C654 baud
rate generator. The ST16C654 divides the clock input by 16. The
resultant clock is divided down by a divisor which is programmed as a
Hex value into the DLM (MSB) and DLL (LSB) registers. Further division
of this clock provides two table rates to support low (clock divided by
4) and high (clock divided by 1) data rate applications in the same
system. The default baud rate is set in hardware to the baud table that is
derived from the clock divided by 1.
After the board is initialized, one of the two available baud tables must
be selected via Modem Control Register (MCR) bit 7:
•
•
MCR register b7 = 0, clock divided by 1
MCR register b7 = 1, clock divided by 4
The table below shows the DLM and DLL register program values and
the associated output baud rate.
Baud rate generator programming table
DLM value
DLL value
0x4E
0x27
0x13
0x09
0x04
0x02
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x20
0x10
0x88
0xC4
0xE2
0x71
0x39
0x9C
0x4E
0x27
0x1A
0x14
0x0D
Divisor
Hex [Decimal]
0x4E20 [20000]
0x2710 [10000]
0x1388 [5000]
0x09C4 [2500]
0x04E2 [1250]
0x0271 [625]
0x0139 [313]
0x009C [156]
0x004E [78]
0x0027 [39]
0x001A [26]
0x0014 [20]
0x000D [13]
Output Baud, bps
(clock ÷4)
—
—
75
150
300
600
1200
2400
4800
9600
14.4K
19.2K
28.8K
Output Baud, bps
(clock ÷1)
75
150
300
600
1200
2400
4800
9600
19.2K
38.4K
57.6K
76.8K
115.2K
Note that the table above is not exhaustive; it only contains the most
commonly used baud rates. The user can program a divisor value
(DLM, DLL registers) for any desired baud rate using the formulas:
•
•
134
For divide-by-one mode: 1,500,000 ÷ baudrate = divisor
For divide-by-two mode: 375,000 ÷ baudrate = divisor
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Section 4: Programming the PowerPC
Asynchronous serial interface
Serial interface interrupts
The ST16C654 provides six levels of prioritized interrupts. The status of
these interrupts is shown in the Interrupt Status Register (ISR). A read of
the ISR provides an indication of the highest pending interrupt to be
serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Reading the ISR clears the interrupt status of the
current pending interrupt only. Note that after an interrupt is cleared,
the ISR should be reread as another lower level interrupt may be
pending. The table below shows the interrupt sources, the priority level,
and associated status bits.
Interrupt source, ST16C654
Priority
Level
ISR Bits
Interrupt
Source
b5
b4
b3
b2
b1
b0
1
0
0
0
1
1
0
LSR (Receiver Line Status Reg.)
2
0
0
0
1
0
0
RXRDY (Rx Data Ready)
2
0
0
1
1
0
0
RXRDY (Rx Data timeout)
3
0
0
0
0
1
0
TXRDY (Tx Holding Reg. Empty)
4
0
0
0
0
0
0
MSR (Modem Status Register)
5
0
1
0
0
0
0
RXRDY (Rec’d Xoff signal)/
Special character
6
1
0
0
0
0
0
CTS, RTS change of state
Enabling/disabling the serial ports as interrupt sources
The Interrupt Enable Register (IER) masks the interrupts from receiver
read, transmitter empty, line status and modem status registers. These
interrupts are normally seen on the INT A-D output pins. Refer to the
ST16C654 datasheet for programming details.
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135
Section 4: Programming the PowerPC
Asynchronous serial interface
Serial interface connector
The figure and table identify the pinout numbers and signals for the
VSS4 front panel serial port RJ-50/RJ-69 connector.
2 4 6 8 10
1 3 5 7 9
Asynchronous serial connector pin numbering
Serial Ports A, B, C, & D (P346) pin assignments
Pin
Function
1
Transmit Data, Serial Port D
2
Transmit Data, Serial Port C
3
Transmit Data, Serial Port B
4
Transmit Data, Serial Port A
5
Ground – (Gnd) internally connected to ground; connect to Signal Ground.
6
Ground – (Gnd) internally connected to ground; connect to Signal Ground.
7
Receive Data, Serial Port A
8
Receive Data, Serial Port B
9
Receive Data, Serial Port C
10
Receive Data, Serial Port D
A serial connection option is available:
•
CRJ4 — VSS4 serial port adapter. The CRJ4 serial port adapter is
a PCB assembly that connects to the VSS4 front panel serial
connector via an RJ-69 cable. Four RJ-45 connectors on the CRJ4
provide the connection to/from the individual serial channels.
Refer to the serial port connector discussion in Appendix A, Cables &
Connectors (page 257) for more information on VSS4 serial port
connectivity.
136
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Section 4: Programming the PowerPC
Clock calendar
Clock calendar
The VSS4 provides clock/calendar data including the year, month, date,
day, hour, minutes, and seconds data in 24-hour BCD format from a
SGS-Thomson M48T201Y Timekeeper SRAM controller chip. The Y2Kcompliant clock calendar is backed-up by a lithium battery that should
last for 5–10 years.
For high-altitude applications (>10,000 ft.), a capacitor backup option is
available to back up the clock calendar in lieu of the regular lithium
battery which can leak in a high-altitude environment. The capacitor
backup option provides 12 days (typical) of backup and raises the
board’s maximum operating altitude to approximately 39,000 ft.
e
Not
For more information about this device,
see the M 4 8 T 2 0 1 Y
Timekeeper
Controller datasheet which is available
as a PDF file from the SGS-Thomson
website:
http://www.st.com/stonline/books/index.htm
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137
Section 4: Programming the PowerPC
Clock calendar
Clock address locations
The M48T201Y Clock/SRAM is an 8-bit peripheral. Each M48T201Y
memory location must be accessed on successive byte boundaries as
illustrated in the table below.
Clock/calendar registers
Register
address
Data bits 0-7
b7
b6
0
0
0
0
0
ST
W
10 Years
0
0
10M
0
10 Date
FT
0
0
0
10 Hours
10 Minutes
10 Seconds
R
S
b5
b4
FFE9_FFFF
FFE9_FFFE
FFE9_FFFD
FFE9_FFFC
FFE9_FFFB
FFE9_FFFA
FFE9_FFF9
FFE9_FFF8
FFE9_FFF7
WDS
BMB
4
BMB
3
BMB
2
FFE9_FFF6
AFE
SQWE
ABE
Al.
10M
FFE9_FFF5
FFE9_FFF4
FFE9_FFF3
FFE9_FFF2
FFE9_FFF1
FFE9_FFF0
RPT4
RPT5
Al. 10 Date
0
Al. 10 Hrs.
Key:
RPT3
RPT2
RPT1
WDF
b3
b2
b1
b0
Year
Month
Day of Month
0
Day of the Week
Hours (24-hr Format)
Minutes
Seconds
Calibration
Year
Month
Day of Month
Day of Week
Hour
Minutes
Seconds
Control
Watchdog
00-99
01-12
01-31
01-07
00-23
00-59
00-59
Alarm Month
Al. Month
01-12
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
100 Years
RS3 RS2 RS1 RS0
Al. Date
Al. Hours
Al. Minutes
Al. Seconds
Century
Flags
01-31
00-23
00-59
00-59
00-99
BMB
1
Alarm 10 Minutes
Alarm 10 Seconds
1000 Years
AF
0
BL
S= Sign bit
FT= Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to ‘0’
Z = ‘0’ and are read only
Range
BMB
0
RB1
RB0
WDS = Watchdog Steering Bit
AF = Alarm Flag
BL = Battery Low Flag
SQWE = Square Wave Enable Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
RS0-RS3 = SQW Frequency
Accessing clock data
Access to the clock is as simple as conventional byte-wide RAM access
because the RAM and the clock are combined on the same die. The
Timekeeper registers are located in the upper 16 locations of the RAM
as listed in the table above.
138
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Section 4: Programming the PowerPC
Clock calendar
These registers contain, beginning from the top: year, month, day of
month, day of week (Sunday = 1), hour, minutes, and seconds data in
24-hour BCD format. Corrections for leap year and the number of days
in the month are made automatically. These registers are not the actual
clock counters, but BiPort read/write static RAM memory locations. The
M48T201Y includes a clock control circuit that, once a second, dumps
the counters into the BiPort RAM.
Clock operations
Updates to the Timekeeper registers should be temporarily suspended
before clock data is read to prevent reading of data in transition.
Because the BiPort Timekeeper cells in the RAM array are only data
registers and not the actual counters, updating the registers can be
suspended without disturbing the clock itself.
Updating the data registers is suspended when a 1 is written into the
Read bit, the seventh most significant bit in the Control register. As long
as a 1 remains in that position, data register updates are suspended.
After the Read bit is set, the registers reflect the count, i.e., the day,
date, and time that were current at the moment the Read command
was issued. All of the Timekeeper registers are updated simultaneously.
The Read command will not interrupt an update in progress. Registers
are again updated in a normal fashion within a second after the Read
bit is reset to a 0.
Setting the clock — The eighth bit of the Control register is the Write
bit. Setting the Write bit to a 1, like the Read bit, suspends updates to
the Timekeeper registers. The user can then load them with the correct
day, date, and time data in 24-hour BCD format.
Resetting the Write bit to a 0 transfers those values into the actual
Timekeeper counters and allows normal operation to resume. The FT
bit, as well as the bits marked with zeros in the above table, must be
written with zeros to allow normal Timekeeper and RAM operation.
Stopping and starting the oscillator — The oscillator may be stopped at
any time. If the CPU board is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to minimize current
drain from the battery. The STOP bit is the MSB (b7) of the Seconds
register. Set this bit to “1” to stop the oscillator.
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139
Section 4: Programming the PowerPC
Clock calendar
To start the oscillator:
➊
➋
➌
➍
➎
➏
➐
Set the Write bit to "1".
Reset the Stop bit to "0".
Reset the Write bit to "0".
Wait two seconds.
Set the Write bit to "1".
Set the correct time and date.
Reset the Write bit to "0".
Calibrating the clock speed — The low-order 5 bits of the control register (‘Calibration’ in the table above) represent any value between 0 and
31 in binary form. The sixth bit is a sign bit (the s bit in the table above)
where:
•
•
S=1 indicates a positive calibration and speeds up the oscillator.
S=0 indicates a negative calibration and slows down the oscillator.
Calibration corrections are applied within a 64-minute cycle. The first
62 minutes in each 64-minute cycle may, once per minute, have one
second either shortened or lengthened by:
128/32768 seconds (3.906 ms)
If a binary 1 is loaded into the ccccc bits, only the first 2 minutes in the
64 minute cycle will be modified; if a binary 6 is loaded, the first 12
minutes of the 64-minute cycle will be affected, and so on. If the oscillator is running precisely at its nominal frequency (32768 Hz), each of the
31 increments in the calibration bits represents 5.35 seconds per
(average) month, or, more precisely, 175.78 ms per day. This affords a
total calibration range of about 5.4 seconds per day.
140
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Section 4: Programming the PowerPC
Clock calendar
The simplest and most accurate method to calibrate the clock is as
follows:
➊
➋
➌
Synchronize the clock to an accurate timing source such as a
GPS receiver or WWV radio transmissions from the National
Bureau of Standards in Fort Collins, Colorado (available at 5,000
kHz, 10,000 kHz, and 15,000 kHz on the AM band).
Accumulate an error for a few weeks or months if necessary.
Compare the clock to the original source.
This procedure yields an accurate correction. Even a manual comparison, which has an error of a second or more, is sufficient to adjust the
clock to within a single count of the calibration register.
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Section 4: Programming the PowerPC
Clock calendar
142
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Section 4: Programming the PowerPC
Non-volatile 128K x 8 SRAM
Non-volatile 128K x 8 SRAM
VSS4 boards provide 128K bytes of general use non-volatile SRAM. The
contents of this non-volatile SRAM are backed-up by a lithium battery
that has a service life of about 5-10 years.
For high-altitude applications (>10,000 ft.), a capacitor backup option is
available to back up the NVRAM in lieu of the regular lithium battery
which can leak in a high-altitude environment. The capacitor backup
option provides 12 days (typical) of backup and raises the board’s
maximum operating altitude to approximately 39,000 ft.
e
Not
Configuration data in NVRAM may be
lost in a capacitor backup-equipped
board that is stored unused or plugged
into an unpowered system in excess of
12 days. A reprogramming of the
NVRAM is required if this occurs.
Consult the factory if your capacitor
backup-equipped board requires
storage or inactivity prior to being
placed in service.
Each SRAM location must be accessed on successive byte-aligned
boundaries in the address range shown in the table below:
Non-volatile SRAM address location
Address
0xFFE8_0000 – 0xFFE9_FFF0
*Note:
Data width
D8*
Description
128K bytes of battery-backed SRAM
SRAM can be read with D8, D16, or D32 accesses. For write accesses, however, only
byte-wise writes are allowed. A D32 write to non-volatile SRAM results in a bus error.
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143
Section 4: Programming the PowerPC
Non-volatile 128K x 8 SRAM
NVRAM space allocation
The table below is a guide to the VSS4’s NVRAM space allocation for
various operating systems and factory test functions. Observe these
space allocations as required by your application. Note that you have
the option to use any unassigned or unused OS spaces in the listed
NVRAM allocations.
Non-volatile SRAM space allocations
Address
Size
Description
0xFFE8_0000 – 0xFFE9_CFFF
116KB
Free User Space
0xFFE9_D000 – 0xFFE9_D4FF
1.25KB
Reserved (factory testing)
0xFFE9_D500 – 0xFFE9_D5FF
256B
Reserved (Boot up write/verify Scratch Space)
0xFFE9_D600 – 0xFFE9_DAFF
1.25KB
OS9
0xFFE9_DB00 – 0xFFE9_DBFF
256B
unassigned
0xFFE9_DC00 – 0xFFE9_E0FF
1.25KB
LynxOS
0xFFE9_E100 – 0xFFE9_E2FF
512B
unassigned
0xFFE9_E300 – 0xFFE9_E6FF
1.0KB
VxWorks
0xFFE9_E700 – 0xFFE9_E8FF
512B
OS common (Boot config/Bd. Serial No.1)
0xFFE9_E900 – 0xFFE9_EDFF
1.25KB
Linux
0xFFE9_EE00 – 0xFFE9_EFFF
512B
unassigned
0xFFE9_F000 – 0xFFE9_F4FF
1.25KB
pSOS
0xFFE9_F500 – 0xFFE9_F7FF
768B
unassigned
0xFFE9_F800 – 0xFFE9_FCFF
1.25KB
SMon
0xFFE9_FD00 – 0xFFE9_FFCF
720B
unassigned
0xFFE9_FFD0 – 0xFFE9_FFEF
32B
Reserved (factory testing)
Note:
1. Board’s 7-digit serial no. is encoded as a three-byte value (leading ‘1’ in board serial
number ignored) 0xFFE9_E778 (single processor or CPU-X) and 0xFFE9_E774 (CPUY). These three bytes are part of the 6-byte (12-digit) Ethernet ID (also called ‘Physical
Address’) that uniquely identifies the board’s Ethernet node(s). Refer to the Ethernet ID
discussion in Section 3 (page 80) for more information about the Ethernet ID.
Battery
The VSS4’s NVRAM/Clock battery is a lithium button type that is
soldered onto the board. Should the battery need replacing, the board
must be returned to the factory for a new battery to be installed.
Contact Customer Service for details.
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
Boot Flash ROM/DIP EPROM
The VSS4 board can boot from DIP EPROM or Boot Flash ROM.
The VSS4 comes with one 32-pin socket (.6 inches wide) at UE10. This
socket accepts one of the following types of JEDEC-standard byte-wide
DIP EPROM/Flash memories† :
•
•
•
•
•
27C010
27C020
27C040
28F020
29C040
1 Mbit DIP EPROM (128 KB)
2 Mbit DIP EPROM (256 KB)
4 Mbit DIP EPROM (512 KB)
2 Mbit DIP Flash EPROM (256 KB)
4 Mbit DIP Flash EPROM (512 KB)
VSS4 boards also come with 1 MB of onboard boot Flash memory.
The figure below shows the location of the DIP EPROM socket on
VSS4 boards. The Boot Flash ROM itself is under this socket.
e
Not
DIP EPROM is limited to a maximum
size of 512 KB. If a larger ROM space is
desired, use the Boot Flash (1 MB).
Use a DIP extractor tool (OK Industries
model EX-2 or equivalent) to remove
the EPROM from its socket. This will
avoid damaging the parts underneath
and voiding the warranty.
† TI brand EPROMs cannot be used. Their requirement for Vcc on unused pins prevents a TI PROM from being used in a general
purpose socket. EPROMs from other manufacturers such as Intel, AMD, etc. work without problem.
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
Pin 1
32-pin DIP JEDEC
standard EPROM
VSS4 DIP EPROM socket location
Boot options
The Boot EPROM Enable jumper at J02L pins 1 & 2 selects the boot
device as follows:
•
Jumper ON = boot from DIP EPROM
•
Jumper OFF = boot from Boot Flash
Refer to the configuration discussion in Section 2 Getting Started, page
23, for a jumper diagram and detailed configuration information.
To boot from onboard Flash, boot from DIP EPROM and program the
Flash memory with the reset vector and boot code. Once this is done,
remove the Boot ROM Enable jumper from J02L pins 1 & 2. With this
jumper removed, a power cycle or local reset directs the CPU to look
for its reset vector at the base of Boot Flash (0xFFF0_0000) instead of
the EPROM.
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
DIP EPROM use
The PowerPC processor fetches its reset vector from the default
address 0xFFF0_0100. It is possible to use either the DIP EPROM or the
soldered-down Boot Flash to contain the reset code. Since the reset
address is fixed, the address mapping of the two boot devices must be
changed to change the boot device. Consequently, the DIP EPROM
appears in one of two address space locations depending on whether
the board is configured to boot from DIP EPROM or Boot Flash:
•
If the board is configured to boot from EPROM, the EPROM is
accessed in the range 0xFFF0_0000 – 0xFFF7_FFFF.
•
If the board is configured to boot from Boot Flash, the EPROM is
accessed in the range 0xFFE0_0000 – 0xFFE7_FFFF.
Refer to the Address Map chapter in this section.
EPROM type configuration
Jumper J902 is used to configure the type device used in the DIP
EPROM socket. Set the jumpers as required for your application as
shown in the drawing below. See also Installing a monitor PROM in
Section 2, page 29.
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147
Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
Boot Flash
DIP EPROM/Flash
Device
1
3
5
7
Jumpers Installed on Pins:
27Cxxx EPROM
3 & 5,
4&6
1
3
5
7
2
4
6
8
28F020 Flash (write enabled)
1 & 3,
6&8
1
3
5
7
2
4
6
8
28F020 Flash (write prot.)
6&8
1
3
5
7
2
4
6
8
29C040 Flash
3 & 4,
6&8
1
3
5
7
2
4
6
8
Boot Flash
(write enabled)
1&2
1
3
5
7
2
4
6
8
Boot Flash
(write protected)
None
(1 & 2)
1
3
5
7
2
4
6
8
2
4
6
8
DIP EPROM/Boot Flash
Configuration
Jumpers, J902
99-0130b
DIP EPROM/Boot Flash configuration jumpers, J902
Boot Flash use
Boot Flash memory is made up of 1 ea. 8-bit Flash memory chip with 1
MB total space.
Boot Flash device
Onboard Flash size
1 MB
Manufacturer1
Intel
Part Number
28F008SA
Organization
1 MB x 8
The 1 MB space provided by this device is split in half in two different
memory locations if the board is configured to boot from DIP EPROM.
If the board is configured to boot from Flash, the 1 MB space is
contiguous. See table below.
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
Boot Flash memory address location
Address
0xFFE0_0000 – 0xFFE7_FFFF
0xFFF8_0000 – 0xFFFF_FFFF
0xFFF0_0000 – 0xFFFF_FFFF
Data width
D8/D64
D8/D64
D8/D64
Description
Boot Flash (lower 512 KB, ROMBoot)
Boot Flash (upper 512 KB, ROMBoot)
Boot Flash (Flash Boot)
Block organization
For convenience in programming or erasing, the block information for
the Boot Flash memory is listed in the table below.
Boot Flash memory block information
Flash Memory Size
1 MB
Total Blocks
16
Block Size
64 KB
Block Numbers
0-15
Note that full Flash support is supplied in Synergy’s SMon Application
Developer and Debugger package. Example Flash driver code is also
available from Synergy. Contact Customer Service for details and
ordering information.
Writing and erasing
Write protection of all Flash (Boot Flash, User Flash, and DIP Flash
EPROM [if installed]) is set in either or both of two ways:
Jumper Flash Write Protect (J02L pins 9 & 10, Rev. B or lower; or pins
21 & 22, Rev. C or higher) — write protect if jumper ON; no write
protect if jumper OFF. Refer to the Setting up the VSS4 hardware
chapter in Section 2, page 23, for more information on the
configuration jumpers.
Software Flash Write Protect (Flash ROM register at 0xFFEF_FE40) —
bit 0 controls protect (1, default) and no protect (0) status. Refer to the
Flash ROM register discussion in Section 4, page 121, for more
information on the Flash ROM register.
To enable writing to Flash memory, remove the Flash Write Protect
jumper (J02L pins 9 & 10, Rev. B or lower; or pins 21 & 22, Rev. C or
higher) and clear bit 0 of the Flash ROM register at 0xFFEF_FE40.
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149
Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
To protect Flash from writes, install the Flash Write Protect jumper (J02L
pins 9 & 10, Rev. B or lower; or pins 21 & 22, Rev. C or higher) or set
bit 0 of the Flash ROM register at 0xFFEF_FE40, or take both actions if
desired.
Additional write protection of Boot Flash
Some VSS4 boards incorporate a retrofit of a Boot Flash Write Protect
jumper on J902 pins 1 and 2. Listed below are the affected board
revisions and the ECO level incorporating the change.
•
•
VSS4 Rev. E with ECO 6
VSS4 Rev. F with ECO 5
The new jumper function provides Boot Flash with additional write
protection for data security during board startup. Refer to the J902
jumper diagram on page 148.
•
•
To write protect Boot Flash, remove jumper from J902 pins 1 &
2. With this jumper removed, Boot Flash has unconditional write
protection regardless of the J02L jumper and/or Flash ROM
register (0xFFEF_FE40) Flash write enable configuration.
To write enable Boot Flash, install jumper J902 pins 1 & 2 and
remove jumper (if installed) from J02L pins 21 & 22.
e
Not
150
On other VSS4 revisions, this jumper
has no function other than to serve as a
place to store a jumper when the
28F020 DIP Flash is write protected.
However, future ECOs may be issued
to retrofit other VSS4 board revisions
for this jumper function. Contact
Customer Service for assistance in
determining whether or not your board
has this added jumper function.
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
Additional Flash memory information
The Flash memory chips have embedded byte write and block/sector
erase algorithms. For more information on the chip itself and on the
software aspects of writing/erasing Flash memory, refer to the Intel
Flash memory databook.
•
Intel Flash Memory Databook (Order no. 210830)
For ordering information, contact:
Intel Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
In U.S. and Canada, call toll free: (800) 548-4725
For general technical information via the Web:
Intel’s Developer site:
http://developer.intel.com/
•
Datasheets for the Flash parts are available in PDF (Adobe
Acrobat) from the Intel’s Developer site:
http://developer.intel.com/design/flash/datashts/index.htm
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Section 4: Programming the PowerPC
Boot Flash ROM/DIP EPROM
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Section 4: Programming the PowerPC
User Flash memory
User Flash memory
Introduction
VSS4 boards provide onboard User Flash memory as an option. For
Rev. B or lower boards, the size of User Flash is 2 or 4 MB. For Rev. C,
the size of User Flash is 4 or 16 MB. For Rev. D or higher, User Flash
options are 4/8/16/32 or 64 MB.
The memory chips have a byte write and block erase architecture with
data storage similar to that of a sectored hard disk. A typical use of User
Flash includes operation as a RAM disk for loading an operating system
kernel or accessing other files as needed by the system.
User Flash memory address location
Address
0xFFF8_0000 – 0xFFFF_FFFF
Data width
D8
Description
User Flash, 512 KB bank
User Flash memory is made up of 1, 2, or 4 ea. Flash memory chip(s)
used in byte-wide mode. The table below lists the devices used for the
VSS4’s User Flash memory.
User Flash device
Onboard Flash size
(no. of chips)
4/8 MB (1/2 ea.)
16/32/64 MB (1/2/4 ea.)
Manufacturer
Part Number
Organization
Intel
Intel
28F320J5
28F128J3A
4 MB x 8
16 MB x 8
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153
Section 4: Programming the PowerPC
User Flash memory
Block organization
For convenience in programming or erasing, the block information for
the onboard Flash memory is listed in the table below.
User Flash memory block information
Flash Memory Size
4 MB
8 MB
16 MB
32 MB
64 MB
Total Blocks
32
64
128
256
512
Block Size
64KB
64KB
64KB
64KB
64KB
Block Numbers
0-31
0-63
0-127
0-255
0-511
Note that full Flash support is supplied in Synergy’s SMon Application
Developer and Debugger package. Example Flash driver code is also
available from Synergy. Contact Customer Service for details and
ordering information.
Bank selection
The MPC106 provides only 2 Megabytes of address space for all 8-bit
ROM devices. Because of this limitation and the need to incorporate
three different ROM devices plus onboard control/status registers into
this space, the User Flash ROM must be accessed piecemeal.
User Flash is accessed in multiple 512 KB banks using the onboard
Flash Window register at 0xFFEF_FE50 (see page 122). The total
number of banks depends on the amount of User Flash installed on the
board. See table below.
With Boot Flash selected (reg. 0xFFEF_FE50, bit 7 = 0), User Flash is
inactive. With User Flash selected (reg. 0xFFEF_FE50, bit 7 = 1), User
Flash is active and a 512 KB window of User Flash space can be
selected. Note that accesses to User Flash and the upper 512 KB of
Boot Flash are not allowed to occur at the same time.
Only 512 KB of User Flash is visible at any time in the User Flash
window, and this 512 KB window is shared with the upper 512 KB of
the Boot Flash. The result of this limit is that code stored in the User
Flash must be read into RAM and executed from RAM instead of being
directly executed from Flash ROM.
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Section 4: Programming the PowerPC
User Flash memory
User Flash bank selection
Flash device
Boot
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
User
Address within device
Register
User Flash Amount
Value
0x0008_0000 – 0x000F_FFFF
0x00
0x0000_0000 – 0x0007_FFFF
0x80
0x0008_0000 – 0x000F_FFFF
0x81
0x0010_0000 – 0x0017_FFFF
0x82
2 MB
0x0018_0000 – 0x001F_FFFF
0x83
0x0020_0000 – 0x0027_FFFF
0x84
4 MB
0x0028_0000 – 0x002F_FFFF
0x85
0x0030_0000 – 0x0037_FFFF
0x86
0x0038_0000 – 0x003F_FFFF
0x87
0x0040_0000 – 0x0047_FFFF
0x88
8 MB
0x0048_0000 – 0x004F_FFFF
0x89
0x0050_0000 – 0x0057_FFFF
0x8A
0x0058_0000 – 0x005F_FFFF
0x8B
0x0060_0000 – 0x0067_FFFF
0x8C
0x0068_0000 – 0x006F_FFFF
0x8D
0x0070_0000 – 0x0077_FFFF
0x8E
0x0078_0000 – 0x007F_FFFF
0x8F
0x0080_0000 – 0x0087_FFFF
0x90
16 MB
0x0088_0000 – 0x008F_FFFF
0x91
0x0090_0000 – 0x0097_FFFF
0x92
0x0098_0000 – 0x009F_FFFF
0x93
0x00A0_0000 – 0x00A7_FFFF
0x94
0x00A8_0000 – 0x00AF_FFFF
0x95
0x00B0_0000 – 0x00B7_FFFF
0x96
0x00B8_0000 – 0x00BF_FFFF
0x97
0x00C0_0000 – 0x00C7_FFFF
0x98
0x00C8_0000 – 0x00CF_FFFF
0x99
0x00D0_0000 – 0x00D7_FFFF
0x9A
0x00D8_0000 – 0x00DF_FFFF
0x9B
0x00E0_0000 – 0x00E7_FFFF
0x9C
0x00E8_0000 – 0x00EF_FFFF
0x9D
0x00F0_0000 – 0x00F7_FFFF
0x9E
0x00F8_0000 – 0x00FF_FFFF
0x9F
...31 additional 512 KB windows....
0x01F8_0000 – 0x01FF_FFFF
0xBF
End of 32 MB User Flash
...63 additional 512 KB windows....
0x07F8_0000 – 0x07FF_FFFF
0xEF
End of 64 MB User Flash
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155
Section 4: Programming the PowerPC
User Flash memory
Writing and erasing
Write protection of all Flash (Boot Flash, User Flash, and DIP Flash
EPROM [if installed]) is set in either or both of two ways:
Jumper Flash Write Protect (J02L pins 9 & 10, Rev. B or lower; or pins
21 & 22, Rev. C or higher) — write protect if jumper ON; no write
protect if jumper OFF. Refer to the Setting up the VSS4 hardware
chapter in Section 2, page 23, for more information on the
configuration jumpers.
Software Flash Write Protect (Flash ROM register at 0xFFEF_FE40) —
bit 0 controls protect (1, default) and no protect (0) status. Refer to the
Refer to the Flash ROM register discussion in Section 4, page 121, for
more information on the Flash ROM register.
To enable writing to Flash memory, remove the Flash Write Protect
jumper (J02L pins 9 & 10, Rev. B or lower; or pins 21 & 22, Rev. C or
higher) and clear bit 0 of the Flash ROM register at 0xFFEF_FE40.
To protect Flash from writes, install the Flash Write Protect jumper (J02L
pins 9 & 10, Rev. B or lower; or pins 21 & 22, Rev. C or higher) or set
bit 0 of the Flash ROM register at 0xFFEF_FE40, or take both actions if
desired.
Additional Flash memory information
The Flash memory chips have embedded byte write and block/sector
erase algorithms. For more information on the chip itself and on the
software aspects of writing/erasing Flash memory, refer to the Intel
Flash memory databook.
•
Intel Flash Memory Databook (Order no. 210830)
For ordering information, contact:
Intel Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
In U.S. and Canada, call toll free: (800) 548-4725
For general technical information via the Web:
Intel’s Developer site:
http://developer.intel.com/
•
Datasheets for the Flash parts are available in PDF (Adobe
Acrobat) from the Intel’s Developer site:
http://developer.intel.com/design/flash/datashts/index.htm
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Reset
5
This section provides information about VSS4 reset.
•
General description
•
PCI reset
•
Hard reset sources
•
Soft reset
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Section 5: Reset
Reset information
Reset information
General description
A reset of the VSS4 causes the board to reset all processors, registers
and onboard peripheral devices such as I/O controllers and bridges. If
the board is the system controller, the VME SysReset is also asserted to
force a system-wide reset.
Once reset, the three CPUs Y, Z, and W are disabled since the
MP_ENABLE bit in the MPC106 is cleared by hardware reset.
CPU-X enters the boot state in which it will execute the code at address
0xFFF0_0100 in either DIP EPROM (512KB) or Boot Flash (1MB)
depending on the Boot ROM Enable jumper configuration (see Section
2, Setting up the VSS4 hardware, page 23). The code at this address is
typically a jump to the cold-start routine, which performs the
initialization tasks that ready the board facilities for use.
e
Not
For Linux, boot code must direct the
processor to go to 0x100 (RAM space)
from address 0xFFF0_0100. The
MSR_IP bit in the processor’s MSR
register must also be cleared so that
any subsequent soft resets would result
in the processor executing boot at
0x100.
The above describes a hard reset or cold-start.
The VSS4 is also capable of a warm start in which only the CPU(s)
is/are reset using the MPIC Processor Init register. Refer to the Soft
reset discussion below.
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Section 5: Reset
Reset information
PCI reset
The PCI reset (RST\) line is driven only by a board-level reset. It is not
allowed to be driven by any onboard PCI device. On the VSS4, the
Universe II PCI reset facility (SW_LRST bit in MISC_CTL register) is not
usable to reset the PCI bus.
Hard reset sources
There are five reset sources, each of which produces a hard reset:
•
•
•
•
•
Power monitors
Front panel switch
External VME SysReset signal
Watchdog timer
Universe II software SysReset
The functional block diagram below shows the VSS4 reset sources.
VMEbus
Hardware
Reset
VME
SysReset
(if SysCon)
Power Monitors
Fnt Pnl Switch
Ext. VME
SysReset
Reset Generator
Local Reset
CPU(s)
Peripheral
Chips
Watchdog Timer
Software Reset
Universe II
SW_SYSRST
(bit 22, MISC_CTL)
Registers
VSS4 hard reset sources
160
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Section 5: Reset
Reset information
Power monitor
The VSS4 power monitor is based on the Max924 low power
comparator. The following bus voltages are monitored:
•
•
•
+5V Vcc supply from backplane, threshold is +4.75V
3.3V DC-DC converter output, threshold is +3.15V
2.0V CPU core DC-DC converter output, threshold value is
dependent on core voltage used (set at factory).
For VSS4 Rev. C or higher, the +5V Vcc line has an additional power
monitor provided by the DS1232 micromonitor chip whose main
purpose in the VSS4 is to provide the watchdog timer function (see
below). The power monitor threshold for this chip is +4.5V which
provides a backup monitor for the primary Vcc power monitor with the
+4.75V threshold.
The power monitor ensures that all bus voltages are at a valid level for
reliable operation. When powering up, the power monitor holds all
devices at reset until all voltages rise past the threshold. If, during the
course of normal operation, a voltage level should dip below the
threshold, the power monitor triggers a reset. This action avoids the
unpredictable nature of operating in a twilight zone.
Front panel reset switch
The front panel reset switch (see Front panel in Section 2, page 17)
provides the user with a means to manually reset the board or system
(if board is system controller). Push the front panel reset switch handle
to the right to reset the board/system.
External VME SysReset
Assertion of the VMEbus SysReset\ signal (P1 pin C12) causes a
board/system reset.
Note that there is a bit called SysReset Enable that allows the board to
prevent itself from being reset by its own SysReset. This bit is in the
VME64 SysReset onboard register at address 0xFFEF_FF38 (see page
125). Its default value is 1 (board responds to its own SysReset). Use
this register to program the board to reset only the other VMEbus
boards in the system without resetting itself. To reset the VMEbus
without resetting the VSS4:
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Section 5: Reset
Reset information
1.
Temporarily disable board’s VMEbus reset from resetting CPU
by writing 0 to 0xFFEF_FF38, b0.
Start VMEbus reset by setting Universe SysReset bit (write 1).
Stop VMEbus reset by clearing Universe SysReset bit (write 0).
Re-enable board’s VMEbus reset to also reset the CPU by writing
1 to 0xFFEF_FF38, b0. This last step is needed to put the system
back into normal operating mode in case it is desired to have
other VME boards reset this CPU.
2.
3.
4.
Allow time for the reset signal to settle — add a 0.1 second delay
between each of the above operations.
The VME64 SysReset register is readable, which lets the system check
its status at anytime by a simple read of the register.
Watchdog timer
For Rev. C or higher boards, a watchdog timer circuit based on the
Dallas Semiconductor DS1232LP low power micromonitor chip
provides a means for the hardware to automatically reset the board
when it is no longer executing code properly. The watchdog timer is
disabled by default at reset, and must be enabled by software before it
is usable.
Once the watchdog is enabled, it cannot be disabled by software. It can
only be disabled by a board reset. This protects the watchdog from
being disabled by errant software.
Two write-only registers are used to control the watchdog.
Watchdog enable register, 0xFFEF_FF40 (WO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
0
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
Watchdog Enable
Values
—
0 = Watchdog disabled. No need to service
watchdog.
1 = Watchdog enabled. Periodic writes to
Watchdog Pet register (see next register
description) is required to prevent board
reset.
The watchdog timer function is enabled by setting b0 of this write-only
register to ‘1’. Once watchdog is enabled, the application code must
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Section 5: Reset
Reset information
periodically write to the watchdog pet register (see next) to avoid reset.
An enabled watchdog can only be disabled by a board reset after
which b0 is automatically set to 0.
Watchdog pet register, 0xFFEF_FF48 (WO)
Bit 7
x
6
x
5
4
x
x
3
x
2
x
1
x
0
0
Reset value
Bit assignments:
Bit(s)
b7-b1
b0
Function
Reserved
Watchdog Service
Values
—
Write alternating 0 and 1 to this bit within
250 ms to prevent board reset. This register
has no effect if watchdog is disabled.
The watchdog is held off from resetting the board by periodic writes
alternating between 0 and 1 to the watchdog pet register b0. A 0-to-1
transition at least once every 250 milliseconds is required. The code
may twiddle this bit as often as it likes as long as this maximum time is
not exceeded. This periodic writing to the watchdog pet register is
typically done in the main polling loop of the application program.
Should the program fail to write to the watchdog pet register, the
watchdog times out and the board/system is reset.
Universe II software reset
Sotware can initiate a board reset by setting bit 22 of the Universe II
PCI-VME64 bridge Miscellaneous Control register (MISC_CTL). If the
board is the system controller, the software reset will also reset the
system. Some OS board support packages from Synergy include a
facility for software reset via the Universe II. The VxWorks BSP, for
example, includes the sysReset() function.
Soft reset
Each of the four CPUs may be independently reset by means of the Soft
Reset feature. The MPIC interrupt controller generates a signal called
Init\ to each of the four CPUs. The four signals Init0\–Init3\ are wired to
the SReset\ inputs of CPUs X, Y, Z and W respectively.
The SReset\ function in the CPU is edge-triggered. This means that
when a CPU’s Init bit in the MPIC is changed from 0 to 1, the CPU will
be reset. The Init bit must be reset to 0 before another soft reset may
be performed.
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Section 5: Reset
Reset information
The Processor Init register is a 32-bit read/write register of which the
least 4 significant bits are defined. Bit 0 (on right) is CPU-X Init, bit 1 is
CPU-Y, etc.
Select Processors 3:0
3 2 1 0
31
C
P
U
W
Reserved
C
P
U
Z
C
P
U
Y
C
P
U
X
To soft reset a particular CPU the appropriate bit(s) in the Processor Init
register is/are cleared to 0 then set to 1. This is done by masking the
desired bit(s) off and writing the data word back to the register [bit(s)
cleared], then ORing the bit(s) with the data word and writing that back
to the register [bit(s) set]. This initiates a soft reset of the corresponding
processor(s) while the register bits of unselected processors remain
unchanged. A simplified form of this procedure in ‘C’ is shown below:
reg & = ~bit;
reg | = bit;
// Clear bit
// Set bit
Where reg is the MPIC Processor Init register and bit is the value
selecting one or more CPUs (1, 2, 4, 8 corresponds to CPU-X, CPU-Y,
CPU-Z & CPU-W).
e
Not
For Linux, boot up code must start at
0x100 (RAM space). For this to happen,
the processor MSR register must have
its MSR_IP bit cleared prior to initiating
a soft reset. This bit defaults to ON
which directs the processor to begin
executing code at 0xFFF0_0100. Setting
the MSR_IP bit OFF allows the
processor to execute code at 0x100.
Refer to Section 6 MPIC Interrupt Controller (page 165) for more on
the MPIC.
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MPIC Interrupt
Controller
6
This section provides information about the PowerPC multiprocessor
interrupt controller (MPIC).
•
General description
•
MPIC registers
e
Not
The bit numbering of registers in this
section follows the zero-on-the-right
convention as opposed to the zero-onthe-left bit numbering convention used
by Motorola and IBM in their PowerPC
documentation.
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Section 6: MPIC Interrupt Controller
General description
General description
Interrupt control on the VSS4 board is provided by IBM’s MPIC
(multiprocessor interrupt controller) chip which is specifically designed
for PowerPC systems. The chip provides interrupt management for
board devices and the processors themselves.
The MPIC chip supports:
•
16 I/O device interrupts
•
Up to 4 processors (0–3)
•
4 interprocessor interrupts
•
4 global timers
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Section 6: MPIC Interrupt Controller
General description
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Section 6: MPIC Interrupt Controller
MPIC registers
MPIC registers
MPIC base address
The operating system PCI discovery routines dynamically set up the
MPIC base address by writing to the appropriate registers in PCI
configuration address space. MPIC’s PCI configuration header is shown
below.
31
*Note:
16 15
0
Device ID
0x0046
Vendor ID
0x1014
0x00
Status 0x0200
Command 0x0000*
0x04
Reserved
0x08
Reserved
0x0C
Base Address Register 0x0000_0000
0x10
Set PCI command regis ter bit 1 to 1 to enable PCI Memory Address space access. MPIC
does not support I/O space access.
The MPIC chip operates only in PCI Memory Space (operation in PCI
I/O Space not supported).
For more information on PCI configuration, refer to the PCI
implementation details discussion in the PCI bus chapter in Section 3,
page 62, and the Setting PCI device base address discussion in Section
4, page 101. Also refer to the Type 0 configuration table on page 108.
The table below shows the overall address map of the MPIC registers
which are accessed through PCI memory cycles. All of these registers
are 32-bits wide located on 16-byte boundaries.
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Section 6: MPIC Interrupt Controller
MPIC registers
Overall Address map, MPIC
Address Offset*
Register
0x0_0000
Reserved
0x0_1000
Global Registers
0x1_0000
Interrupt Source Configuration Registers
0x2_0000
Processor 0 Per Processor Registers
0x2_1000
Processor 1 Per Processor Registers
0x2_2000
Processor 2 Per Processor Registers
0x2_3300
Processor 3 Per Processor Registers
0x3_F000
Reserved
* Note: Add to base address set during PCI configuration.
The following paragraphs describe the three major MPIC register
groups:
•
Global registers
•
Interrupt Source Configuration registers
•
Per Processor registers
Global registers
The table below lists the address map locations of the global registers.
Address map, global registers
Address Offset*
Register
0x0_1000
Feature Reporting register
0x0_1020
Global Configuration register
0x0_1080
Vendor Identification register
0x0_1090
Processor Init register
0x0_1000–0x0_10A0
IPI Vector/Priority registers
0x0_10E0
Spurious Vector register
0x0_10F0–0x0_11F0
Global Timer registers
* Note: Add to base address set during PCI configuration.
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RO
R/W
RO
R/W
R/W
R/W
—
Section 6: MPIC Interrupt Controller
MPIC registers
Feature reporting register
31
27 26
Reserved
16 15
Num IRQ Sources
13 12
Reserved
8
Num CPU
7
0
Version ID
Version ID: Version ID for this interrupt controller. This value reports
what level of the OpenPIC specification is supported by this
implementation, 1 = Spec. Revision 1.0; 2 = Spec. Revision 1.2
Num CPU: The number of the highest physical CPU supported. For a 4processor MPIC chip, this value is 3; for a 2-processor MPIC chip, this
value is 1; for a 1-processor EPIC chip, this value is 0.
Num IRQ: The number of the highest IRQ source supported. For
example, in a system with 16 I/O interrupt sources, this value is 15.
Global configuration registers
31 30 29 28
R
M
20 19
Reserved
0
Base (not used in PowerPC-based systems)
Base: Base Address Relocation field. This field is not used in Power PCbased systems.
M: Cascade mode. Set this bit to 1 to enable the MPIC. This bit is
provided to support an 8259 interrupt controller, which is not used on
the VSS4.
When set to 0 (reset default), the MPIC passes interrupt input 0 directly
through to CPU-X, which disables all other interrupt encoding and
steering operations. This effectively disables the MPIC.
When set to 1, the MPIC processes all interrupt inputs normally.
R: Reset controller. Writing a one to this bit forces the controller logic
to be reset. This bit is cleared automatically when the reset sequence is
complete. While this bit is set, the values of all other registers are
undefined.
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Section 6: MPIC Interrupt Controller
MPIC registers
Vendor identification register
31
24 23
Reserved
16 15
Stepping
8
Device ID
7
0
Vendor ID
Vendor ID: Specifies the manufacturer of this part. For this part, the
value is 0x14.
Device ID: Vendor specified identifier for this device. Value for MPIC2A part is 0x46.
Stepping: Stepping (silicon revision) for this device. Initially 0.
Processor init register
Select Processors 3:0
3 2 1 0
31
Reserved
C
P
U
W
C
P
U
Z
C
P
U
Y
C
P
U
X
Writing to this register (b3–b0) causes the INIT lines(s) to one or more
processors to be activated. Writing a one to a bit activates the
corresponding INIT line. Writing a zero to a bit deactivates the
corresponding INIT line. (The INIT lines(s) are connected to the Soft
Reset pin(s) on PowerPC processors. The Soft Reset input on a
PowerPC processor is normally edge triggered.)
The Processor Init register is used to perform a soft reset of any or all
CPUs on the VSS4. To issue a soft reset to a CPU, write a 0 to the bit
corresponding to the CPU to be reset, then write a 1 to that bit. An
eieio instruction between the two writes is recommended to enforce
proper sequencing of the hardware write cycles.
Beware that a soft reset performed inside an interrupt service routine
will leave the MPIC’s internal interrupt-under-service bit set for that
interrupt, which will prevent future interrupts from that source from
being serviced. This interrupt-under-service bit may be cleared by
writing a zero to the End Of Interrupt register for the processor
servicing the interrupt.
For more information on VSS4 reset, refer to Section 5, Reset (page
157).
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Section 6: MPIC Interrupt Controller
MPIC registers
IPI vector/priority registers
There are 4 IPI vector/priority registers, one for each IPI dispatch
register. The IPI vector/priority register bit assignments are described
below:
Address map, IPI vector/priority registers
Address Offset*
Register
0x010A0
IPI 0 Vector/Priority register
0x010B0
IPI 1 Vector/Priority register
0x010C0
IPI 2 Vector/Priority register
0x010D0
IPI 3 Vector/Priority register
* Note: Add to base address set during PCI configuration.
31
M
S
K
30 29
A
C
T
20 19
Reserved
16 15
Priority
8
Reserved for
Vector Expansion
Access
R/W
R/W
R/W
R/W
7
0
Vector
Vector: Interrupt vector. The vector value in this field is returned when
the Interrupt Acknowledge register is examined and the interrupt
associated with this vector is requested.
Priority: Interrupt priority. This field sets the interrupt priority. The
lowest priority is 0 and the highest is 15. Setting the priority level to 0
disables interrupts.
ACT: Activity bit, read only. The activity bit indicates that an interrupt
has been requested or that it is in-service. The ACT bit is set to 1 when
its associated bit in the Interrupt Pending or In-Service register is set.
Note that this bit is read only. The Vector, Priority, and Sense values
should not be changed while the ACT bit is 1.
MSK: Mask bit. Setting this bit to 1 disables any further interrupts from
this source. If the mask bit is cleared while the bit associated with this
interrupt is set in the IPR, the interrupt request will be generated. This
bit is always set to 1 following a reset.
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Section 6: MPIC Interrupt Controller
MPIC registers
Spurious vector register
31
16 15
8
7
Reserved for
Vector Expansion
Reserved
0
Vector
The MPIC will respond to a spurious interrupt by presenting the CPU
with the vector stored in this register when it is unable to determine the
vector for the interrupt under service. This will occur if the interrupt
request is negated by the source before the vector read cycle is
performed by that CPU.
Only one spurious interrupt register exists, so it will be used only for
interrupts directed to the CPU to which it is steered.
Reset sets this register to 0x0000_00FF.
Global Timer registers
MPIC contains four global timers (0–3) suitable for system timing and
periodic interrupt generation. The four timers share a Timer Frequency
Reporting register. Each timer has a set of 4 registers for configuration
and control and each is readable on-the-fly.
Address map, global timer registers
Address Offset*
0x010F0
0x01100
0x01110
0x01120
0x01130
0x01140
0x01150
0x01160
0x01170
0x01180
0x01190
0x011A0
0x011B0
0x011C0
0x011D0
0x011E0
Register
Timer Frequency Reporting register
Global Timer 0 Current Count
Global Timer 0 Base Count
Global Timer 0 Vector/Priority register
Global Timer 0 Destination register
Global Timer 1 Current Count
Global Timer 1 Base Count
Global Timer 1 Vector/Priority register
Global Timer 1 Destination register
Global Timer 2 Current Count
Global Timer 2 Base Count
Global Timer 2 Vector/Priority register
Global Timer 2 Destination register
Global Timer 3 Current Count
Global Timer 3 Base Count
Global Timer 3 Vector/Priority register
0x011F0
Global Timer 3 Destination register
* Note: Add to base address set during PCI configuration.
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Access
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
Section 6: MPIC Interrupt Controller
MPIC registers
Timer frequency reporting register
31
0
Timer Frequency
Timer Frequency: This register is used to report the frequency (in Hz) of
the clock source for the global timers. The global timers’ clock source is
the MPIC input clock frequency divided by 8.
This register contains zero after a Reset. System initialization code
should initialize this register to one-eighth the MPIC clock frequency
once the MPIC clock frequency (VSS4’s 33MHz PCI clock) has been
determined. A typical value for this register would be 0x003F_940B
indicating each timer is updated once every 240nS.
Global Timer Current Count register
31 30
0
Current Count
T
Current Count: The current count is loaded with the base count, and
the toggle bit is cleared, whenever the Base Count register is written
and the Count Inhibit bit in the Base Count register transitions from 1 to
0. The timer decrements while the Count Inhibit bit in the Base Count
register is zero. When the time counts down to zero, an interrupt is
generated, the toggle bit is inverted and the current count is reloaded
from the base count.
Following Reset, counting is disabled and the current count register
contains zero.
T: Toggle. This bit toggles whenever the current count decrements to
zero.
Global Timer Base Count register
31 30
0
Base Count
C
Base Count: This field contains the 31-bit base count for this timer. The
current count is loaded with the base count, and the toggle bit in the
Current Count register is cleared, whenever the Base Count register is
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Section 6: MPIC Interrupt Controller
MPIC registers
written and the Count Inhibit bit transitions from 1 to a 0. The timer
decrements while the Count Inhibit bit is zero. When the timer counts
down to zero, an interrupt is generated, the toggle bit in the Current
Count register is inverted and the current count is reloaded from the
base count.
C:Count Inhibit bit; 1 = inhibit counting for this timer, 0 = proceed with
counting. Reset sets this bit to one (inhibit counting).
Global Timer Vector/Priority register
31
M
S
K
30 29
A
C
T
20 19
Reserved
16 15
Priority
8
Reserved for
Vector Expansion
7
0
Vector
Vector: Interrupt Vector. The vector value in this field is returned when
the Interrupt Acknowledge register is examined and the interrupt
associated with this vector is requested.
Priority: Interrupt Priority. This field sets the interrupt priority. The
lowest priority is 0 and the highest is 15. Setting the priority level to 0
disables interrupts.
ACT: Activity bit, read only. The activity bit indicates that an interrupt
has been requested or that it is in-service. The ACT bit is set to 1 when
its associated bit in the Interrupt Pending or In-Service register is set.
Note that this bit is READ ONLY. The vector and priority values should
not be changed while the ACT bit is 1.
MSK: Mask bit. Setting this bit disables any further interrupts from this
source. Reset sets this bit to one.
Global Timer Destination register
Select Processors 3:0
3 2 1 0
31
Reserved
C
P
U
W
C
P
U
Z
C
P
U
Y
C
P
U
X
This register indicates the destination(s) for this timer’s interrupts. Timer
interrupts operate only in Directed Delivery mode. This register may
specify multiple destinations (multicast delivery).
CPU_: Setting the appropriate bit(s) (b3-b0) directs the timer interrupt
to the corresponding processor(s).
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Section 6: MPIC Interrupt Controller
MPIC registers
Interrupt source configuration registers
The table below lists the address map locations of the interrupt source
configuration registers.
Address map, interrupt source configuration registers
Address Offset*
Register
0x1_0000
Interrupt Source 0 Vector/Priority register
0x1_0010
Interrupt Source 0 Destination register
|
|
0x1_01E0
Interrupt Source 15 Vector/Priority register
0x1_01F0
Interrupt Source 15 Destination register
* Note: Add to base address set during PCI configuration.
Access
R/W
R/W
|
R/W
R/W
Each interrupt source has an associated vector/priority register and a
destination register. There are 16 sets of these. The vector/priority
register sets up how an interrupt source is detected, its priority, and its
vector address. The destination register routes (or steers) the interrupt
source to one or more onboard processors.
The table below lists the VSS4 interrupt sources (active low trigger
mode used for all).
VSS4 interrupt sources
Source
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Owner
PCI Int D
PCI–VME Bridge (Universe II) Int 4
PCI Int B
PCI Int A
PCI PErr/SErr
Mailbox D
P0•PCI Bridge/Interrupts
Mailbox C
PCI–VME Bridge (Universe II) Int 5
PCI Int C
Ethernet
SCSI
Mailbox B
Mailbox A
Serial Port B
Serial Port A
Notes
Note1
—
Note2
Note3
—
—
—
—
—
Note4
—
—
—
—
—
—
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Section 6: MPIC Interrupt Controller
MPIC registers
Notes:
1. PCI Int D can be driven by any of the following:
a. Universe Int 3
b. PMC Int D
c. PEX3 Int D
d. Serial Port D
2. PCI Int B can be driven by any of the following:
a. Universe Int 1
b. PMC Int B
c. PEX3 Int B
3. PCI Int A can be driven by any of the following:
a. Universe Int 0
b. PMC Int A
c. PEX3 Int A
4. PCI Int C can be driven by any of the following:
a. Universe Int 2
b. PMC Int C
c. PEX3 Int C
d. Serial Port C
Interrupt Source Vector/Priority registers
The vector/priority register bit assignments are described below.
31
M
S
K
30 29
A
C
T
Reserved
24 23 22 21
P S R
O
s
L
v
20 19
16 15
R
s
Priority
v
8
Reserved for
Vector Expansion
7
0
Vector
Vector: Interrupt Vector. The vector value in this field is returned when
the Interrupt Acknowledge register is examined and the interrupt
associated with this vector is requested.
Priority: Interrupt Priority. This field sets the interrupt priority. The
lowest priority is 0 and the highest is 15. Setting the priority level to 0
disables interrupts.
S: Sense. This bit sets the sense for external interrupts. Setting this bit to
0 enables edge sensitive interrupts. Setting this bit to 1 enables level
sensitive interrupts.
POL: Polarity. This bit sets the polarity for external interrupts. Setting
this bit to 0 enables active low or negative edge. Setting this bit to 1
enables active high or positive edge.
e
Not
178
For Synergy PowerPC series boards, all
I/O interrupt sources (0–15) are set up
for Active Low polarity and Level
Triggered sense.
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Section 6: MPIC Interrupt Controller
MPIC registers
ACT: Activity bit, read only. The activity bit indicates that an interrupt
has been requested or that it is in-service. The ACT bit is set to 1 when
its associated bit in the Interrupt Pending or In-Service register is set.
Note that this bit is READ ONLY. The vector and priority values should
not be changed while the ACT bit is 1.
MSK: Mask bit. Setting this bit disables any further interrupts from this
source. Reset sets this bit to one.
Unless otherwise specified, reset sets all bits in all program accessible
registers to zero.
Interrupt Source Destination register
The destination register bit assignments are described below.
Select Processors 3:0
3 2 1 0
31
Reserved
C
P
U
W
C
P
U
Z
C
P
U
Y
C
P
U
X
This register indicates the destination processors(s) for this interrupt
source.
CPU_: Setting the appropriate bit(s) (b3-b0) directs the interrupt source
to the corresponding processor(s).
If a single destination processor is selected (directed delivery mode)
then interrupts from this source are directed to that processor. If
multiple destination processors are selected (distributed delivery mode)
then interrupts from this source are distributed among the selected
destination processors using a fair, implementation specific algorithm.
Per processor registers
For each processor supported, MPIC provides the following registers:
•
•
•
•
Interprocessor interrupt dispatch register
Current task priority register
Interrupt request register (implementation-specific, non-program
accessible)
Interrupt acknowledge register
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Section 6: MPIC Interrupt Controller
MPIC registers
•
•
In-service registers (implementation-specific, non-program
accessible)
End-of-interrupt register
The following describes the bit assignments of the Per Processor
registers. Not included are the implementation-specific, non-program
accessible registers: interrupt request and in-service registers. For these
registers, refer to the MPIC data manual for more information.
Interprocessor Interrupt Dispatch registers
There are 4 interprocessor interrupt (IPI) dispatch registers 0-3 per
processor. Writing to an IPI dispatch register causes an interprocessor
interrupt request to be sent to one or more processors. A processor is
interrupted if the bit in the IPI dispatch register corresponding to that
processor is set during the write. Reading these registers returns zeros.
Select Processors 3:0
3 2 1 0
31
Reserved
C
P
U
W
C
P
U
Z
C
P
U
Y
C
P
U
X
Address map, interprocessor interrupt dispatch registers
Address Offset*
Register
0x2_0040
IPI 0 dispatch register, processor 0
0x2_0050
IPI 1 dispatch register, processor 0
0x2_0060
IPI 2 dispatch register, processor 0
0x2_0070
IPI 3 dispatch register, processor 0
0x2_1040
IPI 0 dispatch register, processor 1
0x2_1050
IPI 1 dispatch register, processor 1
0x2_1060
IPI 2 dispatch register, processor 1
0x2_1070
IPI 3 dispatch register, processor 1
0x2_2040
IPI 0 dispatch register, processor 2
0x2_2050
IPI 1 dispatch register, processor 2
0x2_2060
IPI 2 dispatch register, processor 2
0x2_2070
IPI 3 dispatch register, processor 2
0x2_3040
IPI 0 dispatch register, processor 3
0x2_3050
IPI 1 dispatch register, processor 3
0x2_3060
IPI 2 dispatch register, processor 3
0x2_3070
IPI 3 dispatch register, processor 3
* Note: Add to base address set during PCI configuration.
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section 6: MPIC Interrupt Controller
MPIC registers
Current Task Priority register
Each processor has a Current Task Priority register.
31
4
3
0
Priority
Reserved
Priority: Task Priority. Set from 0 (lowest) to 15 (highest). Setting the
Task Priority register to 15 masks all interrupts to this processor. At
reset, hardware sets the Task Priority registers to 0xF.
Do not use the Task Priority register to temporarily disable interrupts to
a processor. Doing so may result in a spurious interrupt being
generated if an interrupt is requested just as the Task Priority register is
set to disable interrupts.
Address map, current task priority registers
Address Offset*
Register
0x2_0080
Task Priority register, processor 0
0x2_1080
Task Priority register, processor 1
0x2_2080
Task Priority register, processor 2
0x2_3080
Task Priority register, processor 3
* Note: Add to base address set during PCI configuration.
Access
R/W
R/W
R/W
R/W
Interrupt Acknowlege registers
31
16 15
Reserved
8
Reserved for
Vector Expansion
7
0
Vector
On PowerPC based systems, Interrupt Acknowledge is implemented as
a read request to a memory-mapped Interrupt Acknowledge register.
There is one Interrupt Acknowledge register per processor. Interrupt
Acknowledge:
•
•
•
Returns the interrupt vector corresponding to the highest priority
pending interrupt in that processor’s Interrupt Request Register.
Transfers the highest priority pending interrupt from that
processor’s IRR to that processor’s In-Service register.
Clears the bit in the Interrupt Pending Register corresponding to
the highest priority pending interrupt in that processor’s IRR.
Note: This is effective only for edge triggered interrupts. Level
triggered interrupts normally cause the bit in the IPR to be set to
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Section 6: MPIC Interrupt Controller
MPIC registers
1 every cycle until the device driver’s interrupt service routine
has cleared the interrupt at the source.
In some implementations, Interrupt Acknowlege also flushes data
buffers between the device and system memory.
Address map, interrupt acknowlege registers
Address Offset*
Register
0x2_00A0
Int. Acknowledge register, processor 0
0x2_10A0
Int. Acknowledge register, processor 1
0x2_20A0
Int. Acknowledge register, processor 2
0x2_30A0
Int. Acknowledge register, processor 3
* Note: Add to base address set during PCI configuration.
Access
RO
RO
RO
RO
End-of-interrupt registers
There is one End-of-interrupt (EOI) register per processor. Writing a zero
to this register signals the end of processing for the highest priority
interrupt currently in service by the associated processor. EOI Code
values other than 0 are currently undefined and should not be used.
Reading this register returns the last value written.
MPIC Implementation Note: When the EOI register is written, the
highest priority interrupt in the In-Service Priority register is reset along
with the corresponding bit in the Interrupt Source In-Service register.
MPIC-2A requires the EOI code be written as zero to signal the end of
processing for the highest priority interrupt currently in service by the
associated processor; EOI code values other than zero are ignored. The
MPIC-2A returns zero on reads.
31
0
EOI Code
Address map, end-of-interrupt registers
Address Offset*
Register
0x2_00B0
End-of-interrupt register, processor 0
0x2_10B0
End-of-interrupt register, processor 1
0x2_20B0
End-of-interrupt register, processor 2
0x2_30B0
End-of-interrupt register, processor 3
* Note: Add to base address set during PCI configuration.
182
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Access
RO
RO
RO
RO
PCI-VME64
Bridge (Universe II)
7
This section provides general information about the Universe II PCIVME64 bridge interface.
•
Introduction to Universe II
•
Universe II register reference
•
Improving BLT performance
•
Programming notes, Universe II
e
Not
The bit numbering of registers in this
section follows the zero-on-the-right
convention as opposed to the zero-onthe-left bit numbering convention used
by Motorola and IBM in their PowerPC
documentation.
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184
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Section 7: PCI–VME64 Bridge
Introduction to Universe II
Introduction to Universe II
The Universe II PCI–VME64 bridge chip from Tundra Semiconductor
provides the VSS4 VMEbus interface. Universe II’s address translation
provides VME access to PCI and PCI access to VME. The VME
functions provided by this chip include:
•
•
•
•
System controller
Block transfers, master and slave
Single data transfers, master and slave
Interrupt generation and handling
For general information about the VSS4 VMEbus interface, refer to the
VME64 bus chapter in Section 3.
The PCI interface side of the Universe II provides the following
functions:
•
PCI Target — PCI masters address the Universe II. Read
transactions are coupled. Write transactions are either coupled
or posted depending on the PCI bus target image. PCI masters
can also perform RMW and ADOH cycles via the Universe II’s
Special Cycle generator. For details on the mechanisms of these
transfers, refer to the Universe II User Manual.
•
PCI Master — An internal request of the Universe II’s PCI Master
interface by the VMEbus Slave channel or DMA channel causes
the Universe II to operate as a PCI master. The user can set the
relative priority of the VMEbus Slave channel and the DMA
channel. For details on how this is set up, refer to the Universe II
User Manual.
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Section 7: PCI–VME64 Bridge
Introduction to Universe II
As an Interrupter and Interrupt Handler, the Universe II provides flexible
mapping of interrupts to the PCI bus or VMEbus interface. PCI
interrupts can be routed and processed and VMEbus interrupts can be
input to generate a VMEbus IAck cycle and to generate the specified
interrupt signal. Software interrupts are ROAK while hardware and
internal interrupts are RORA.
Universe II’s DMA controller provides high performance data transfer
between the PCI and VMEbus. Universe II is provided with a set of
DMA registers to set up DMA transfer parameters.
The diagram below shows the general architecture of the Universe II
chip.
DMA Channel
PCI Bus
Interface
DMA bidirectional FIFO
VMEbus
Interface
VMEbus Slave Channel
posted writes FIFO
prefetch read FIFO
coupled read
VME
Slave
PCI Bus Slave Channel
PCI
Slave
posted writes FIFO
PCI
Interrupts
Interrupt Handler
Interrupter
coupled read logic
VME
Master
VMEbus
PCI bus
PCI
Master
Interrupt Channel
VME
Interrupts
Register Channel
Mailbox Registers
Semaphores
Universe II architecture
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Section 7: PCI–VME64 Bridge
Introduction to Universe II
A register overview is given in the next chapter of this section (Universe
II register reference ).
e
Not
For detailed information on the
Universe II chip, refer to the Universe II
User Manual and other supporting
documentation available on Tundra
Semiconductor Corporation’s website
on the WWW:
http://www.tundra.com
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Section 7: PCI–VME64 Bridge
Introduction to Universe II
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Section 7: PCI–VME64 Bridge
Universe II register reference
Universe II register reference
Overview
The Universe II registers are collectively known as the Universe II
Control and Status Registers (UCSR). These registers occupy 4KBytes of
internal memory. This space is divided into three logical groups:
•
•
•
PCI Configuration Space (PCICS)
Universe II Device Specific Registers (UDSR)
VMEbus Control and Status Registers (VCSR)
The register access mechanism depends on whether the register space
is accessed from the PCI bus or the VMEbus.
This chapter provides a reference overview of the Universe II registers.
Refer to Tundra Semiconductor’s Universe II User Manual and/or other
supporting documentation for detailed information.
Register access
Below is a brief description of Universe II register access.
Universe II base address
The operating system PCI discovery routines dynamically set up the
Universe II base address by writing to the appropriate registers in PCI
configuration address space.
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189
Section 7: PCI–VME64 Bridge
Universe II register reference
For more information on PCI configuration, refer to the PCI
implementation details discussion in the PCI bus chapter in Section 3,
page 62, and the Setting PCI device base address discussion in Section
4, page 101. Also refer to the Type 0 configuration table on page 108.
Register access from PCI
There are two PCI access mechanisms for the Universe II registers:
•
•
PCI Configuration space — only the lower 256 bytes of the
UCSR can be accessed as Configuration space. These bytes
make up the Universe II’s PCI configuration header.
PCI Memory or I/O space — As specified in the Space bit of the
PCI_BSx registers, the Universe II registers are accessed in either
the PCI Memory or I/O space.
Register access from VMEbus
There are two VMEbus access mechanisms for the Universe II registers.
This mode is typically not used on the VSS4, since the VSS4 has
onboard intelligence. However, it may be useful in certain applications.
•
VMEbus Register Access Image (VRAI) — this mechanism allows
the user to map the Universe II registers in A16, A24, or A32
address space.
•
CS/CSR Space — this mechanism uses the VME64 scheme in
which each slot in the VMEbus system is assigned 512KBytes of
CS/CSR space.
Register map
The table below lists the Universe II registers by offset address.
e
Not
190
For CS/CSR access, add 508 KBytes
(0x7_F000) to offsets listed below.
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Section 7: PCI–VME64 Bridge
Universe II register reference
Universe II register map
Offset (Hex)
000
004
008
00C
010
014
018-024
028
02C
030
034
038
03C
040-0FF
100
104
108
10C
110
114
118
11C
120
124
128
12C
130
134
138
13C
140
144
148
14C-16C
170
174
Register
PCI Configuration Space ID register
PCI Configuration Space Ctl & Status reg.
PCI Configuration Class register
PCI Configuration Misc. 0 register
PCI Configuration Base Address register
PCI Configuration Base Address 1 register
PCI Unimplemented
PCI Reserved
PCI Reserved
PCI Unimplemented
PCI Reserved
PCI Reserved
PCI Configuration Misc. 1 register
PCI Unimplemented
PCI Target Image 0 Control register
PCI Target Image 0 Base Address register
PCI Target Image 0 Bound Address register
PCI Target Image 0 Translation Offset register
Reserved
PCI Target Image 1 Control register
PCI Target Image 1 Base Address register
PCI Target Image 1 Bound Address register
PCI Target Image 1 Translation Offset register
Reserved
PCI Target Image 2 Control register
PCI Target Image 2 Base Address register
PCI Target Image 2 Bound Address register
PCI Target Image 2 Translation Offset register
Reserved
PCI Target Image 3 Control register
PCI Target Image 3 Base Address register
PCI Target Image 3 Bound Address register
PCI Target Image 3 Translation Offset register
Reserved
Special Cycle Control register
Special Cycle PCI Bus Address register
Name
PCI_ID
PCI_CSR
PCI_Class
PCI_MISC0
PCI_BS0
PCI_BS1
PCI_MISC1
LSI0_CTL
LSI0_BS
LSI0_BD
LSI0_TO
LSI1_CTL
LSI1_BS
LSI1_BD
LSI1_TO
LSI2_CTL
LSI2_BS
LSI2_BD
LSI2_TO
LSI3_CTL
LSI3_BS
LSI3_BD
LSI3_TO
SCYC_CTL
SCYC_ADDR
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191
Section 7: PCI–VME64 Bridge
Universe II register reference
Universe II register map (continued)
192
Offset (Hex)
Register
Name
178
17C
180
184
188
18C
190
194-19C
1A0
1A4
1A8
1AC
1B0
1B4
1B8
1BC
1C0
1C4
1C8
1CC
1D0
1D4
1D8
1DC
1E0
1E4
1E8
1EC-1FC
200
204
208
20C
210
214
218
21C
220
224
228-2FC
300
304
Special Cycle Swap/Compare Enable register
Special Cycle Compare Data register
Special Cycle Swap Data register
PCI Misc. register
Special PCI Target Image register
PCI Command Error Log register
PCI Address Error Log register
Reserved
PCI Target Image 4 Control register
PCI Target Image 4 Base Address register
PCI Target Image 4 Bound Address register
PCI Target Image 4 Translation Offset register
Reserved
PCI Target Image 5 Control register
PCI Target Image 5 Base Address register
PCI Target Image 5 Bound Address register
PCI Target Image 5 Translation Offset register
Reserved
PCI Target Image 6 Control register
PCI Target Image 6 Base Address register
PCI Target Image 6 Bound Address register
PCI Target Image 6 Translation Offset register
Reserved
PCI Target Image 7 Control register
PCI Target Image 7 Base Address register
PCI Target Image 7 Bound Address register
PCI Target Image 7 Translation Offset register
Reserved
DMA Transfer Control register
DMA Transfer Byte Count register
DMA PCI Bus Address register
Reserved
DMA VMEbus Address register
Reserved
DMA Command Packet Pointer register
Reserved
DMA General Control and Status register
DMA Linked List Update Enable register
Reserved
PCI Interrupt Enable register
PCI Interrupt Status register
SCYC_EN
SCYC_CMP
SCYC_SWP
LMISC
SLSI
L_CMDERR
LAERR
LSI4_CTL
LSI4_BS
LSI4_BD
LSI4_TO
LSI5_CTL
LSI5_BS
LSI5_BD
LSI5_TO
LSI6_CTL
LSI6_BS
LSI6_BD
LSI6_TO
LSI7_CTL
LSI7_BS
LSI7_BD
LSI7_TO
DCTL
DTBC
DLA
DVA
DCPP
DGCS
D_LLUE
LINT_EN
LINT_STAT
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Section 7: PCI–VME64 Bridge
Universe II register reference
Universe II register map (continued)
Offset (Hex)
308
30C
310
314
318
31C
320
324
328
32C
330
334
338
33C
340
344
348
34C
350
354
358
35C
360-3FC
400
404
408
40C
410-EFC
F00
F04
F08
F0C
F10
F14
F18
F1C
F20
F24
F28
F2C
F30
F34
Note:
Register
Name
PCI Interrupt Map 0 register
PCI Interrupt Map 1 register
VMEbus Interrupt Enable register
VMEbus Interrupt Status register
VMEbus Interrupt Map 0 register
VMEbus Interrupt Map 1 register
Interrupt Status/ID Out register
VIRQ1 Status/ID register
VIRQ2 Status/ID register
VIRQ3 Status/ID register
VIRQ4 Status/ID register
VIRQ5 Status/ID register
VIRQ6 Status/ID register
VIRQ7 Status/ID register
PCI Interrupt Map 2 register
VME Interrupt Map 1 register
Mailbox 0 register
Mailbox 1 register
Mailbox 2 register
Mailbox 3 register
Semaphore 0 register
Semaphore 1 register
LINT_MAP0
LINT_MAP1
VINT_EN
VINT_STAT
VINT_MAP0
VINT_MAP1
STATID
V1_STATID
V2_STATID
V3_STATID
V4_STATID
V5_STATID
V6_STATID
V7_STATID
LINT_MAP2
VINT_MAP2
MBOX0
MBOX1
MBOX2
MBOX3
SEMA0
SEMA1
Reserved
Master Control register
Misc. Control register
Misc. Status register
User AM Codes register
Reserved
VMEbus Slave Image 0 Control register 1
VMEbus Slave Image 0 Base Address register1
VMEbus Slave Image 0 Bound Address reg. 1
VMEbus Slave Image 0 Translation Offset reg. 1
Reserved
VMEbus Slave Image 1 Control register 1
VMEbus Slave Image 1 Base Address register1
VMEbus Slave Image 1 Bound Address reg. 1
VMEbus Slave Image 1 Translation Offset reg. 1
Reserved
VMEbus Slave Image 2 Control register 1
VMEbus Slave Image 2 Base Address register1
VMEbus Slave Image 2 Bound Address reg. 1
VMEbus Slave Image 2 Translation Offset reg. 1
MAST_CTL
MISC_CTL
MISC_STAT
USER_AM
VSIO_CTL
VSIO_BS
VSIO_BD
VSIO_TO
VSI1_CTL
VSI1_BS
VSI1_BD
VSI1_TO
VSI2_CTL
VSI2_BS
VSI2_BD
VSI2_TO
1. Avoid updating slave image registers while VME traffic is using the slave window.
Doing so results in VME data errors. See Programming notes, Universe II on page 199
for more information.
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193
Section 7: PCI–VME64 Bridge
Universe II register reference
Universe II register map (continued)
Offset (Hex)
F38
F3C
F40
F44
F48
F4C-F60
F64
F68
F6C
F70
F74
F78
F7C
F80
F84
F88
F8C
F90
F94
F98
F9C
FA0
FA4
FA8
FAC
FB0
FB4
FB8
FBC
FC0
FC4
FC8
FCC
FD0
FD4
FD8
FDC-FEC
FF0
FF4
FF8
FFC
Note:
194
Register
Reserved
VMEbus Slave Image 3 Control register 1
VMEbus Slave Image 3 Base Address register1
VMEbus Slave Image 3 Bound Address reg. 1
VMEbus Slave Image 3 Translation Offset reg. 1
Reserved
Location Monitor Control register
Location Monitor Base Address register
Reserved
VMEbus Register Access Image Control reg.
VMEbus Register Access Image Base Addr. reg.
Reserved
Reserved
VMEbus CSR Control register
VMEbus CSR Translation Offset register
VMEbus AM Code Error Log register
VMEbus Address Error Log register
VMEbus Slave Image 4 Control register 1
VMEbus Slave Image 4 Base Address register1
VMEbus Slave Image 4 Bound Address reg. 1
VMEbus Slave Image 4 Translation Offset reg. 1
Reserved
VMEbus Slave Image 5 Control register 1
VMEbus Slave Image 5 Base Address register1
VMEbus Slave Image 5 Bound Address reg. 1
VMEbus Slave Image 5 Translation Offset reg. 1
Reserved
VMEbus Slave Image 6 Control register 1
VMEbus Slave Image 6 Base Address register1
VMEbus Slave Image 6 Bound Address reg. 1
VMEbus Slave Image 6 Translation Offset reg. 1
Reserved
VMEbus Slave Image 7 Control register 1
VMEbus Slave Image 7 Base Address register1
VMEbus Slave Image 7 Bound Address reg. 1
VMEbus Slave Image 7 Translation Offset reg. 1
Reserved
VME CR/CSR Reserved
VMEbus CSR Bit Clear register
VMEbus CSR Bit Set register
VMEbus CSR Base Address register
Name
VSI3_CTL
VSI3_BS
VSI3_BD
VSI3_TO
LM_CTL
LM_BS
VRAI_CTL
VRAI_BS
VCSR_CTL
VCSR_TO
V_AMERR
VAERR
VSI4_CTL
VSI4_BS
VSI4_BD
VSI4_TO
VSI5_CTL
VSI5_BS
VSI5_BD
VSI5_TO
VSI6_CTL
VSI6_BS
VSI6_BD
VSI6_TO
VSI7_CTL
VSI7_BS
VSI7_BD
VSI7_TO
VCSR_CKR
VCSR_SET
VCSR_BS
1. Avoid updating slave image registers while VME traffic is using the slave window.
Doing so results in VME data errors. See Programming notes, Universe II on page 199
for more information.
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Section 7: PCI–VME64 Bridge
Improving VME performance
Improving VME performance
Universe II specific (U2SPEC) register
The Universe II chip (Revision ID = 01 or 02) comes with a register
called “Specific Register” (U2SPEC, offset 0x4FC) which is used to
improve the performance of the Universe II by reducing the latency of
key VMEbus timing elements. The timing adjustment provided by the
U2SPEC register is intended to compensate for VME master and slave
latencies introduced by buffers, transceivers, and the backplane itself.
Using the U2SPEC register may result in violation of the VME
specification.
The U2SPEC register is an unsupported
feature of Universe II. Its design may
not be as robust as other areas of the
Universe II design, and may not be
included in future revisions of the
device. Improper use of the U2SPEC
register may result in undesirable
system
behavior.
Tundra
Semiconductor Corp. and Synergy
Microsystems, Inc. do not recommend
the manipulation of this register by
users who are unfamiliar with the
timing characteristics of their VME
systems.
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195
Section 7: PCI–VME64 Bridge
Improving VME performance
U2SPEC adjustable VME timing parameters
VME DTAck\ Inactive Filter (DTKFLTR), bit 12 — In order to overcome
the DTAck\ noise typical of most VME systems, the Universe II
quadruple samples this signal with the 64MHz clock. While “safer”, the
extra sampling results in decreased performance. User who believe
their systems to have little noise on their DTAck\ lines can elect to filter
this signal less and thus increase their Universe II response time.
VME Master Parameter t11 Control (MASt11), bit 10 — According to
the VME64 Specification, a VMEbus master must not drive DS0\ low
until both it and DS1\ have been simultaneously high for a minimum of
40ns. The MASt11 parameter in the U2SPEC register, however, allows
DS0\ to be driven low in less than 40ns.
VME Master Parameter t27 Control (READt27), bits 8 & 9 — During
read cycles, the VMEbus master must guarantee that the data lines will
be valid within 25ns after DTAck\ is asserted. That is to say, the master
must not latch the data and terminate the cycle for a minimum of 25ns
after the falling edge of DTAck\. The READt27 parameter in the
U2SPEC register allows for faster cycle termination in one of two ways.
One setting allows for the data to be latched and the cycle terminated
with an associated delay that is less than 25ns. The other setting results
in no delay whatsoever in latching and termination.
VME Slave Parameter t28 Control (POSt28), bit 2 — According to the
VME64 Specification, VMEbus slaves must wait at least 30ns after the
assertion of DS\ before driving DTAck\ low. The POSt28 parameter in
the U2SPEC register, however, allows DTAck\ to be asserted in less
than 30ns when executing posted writes.
VME Slave Parameter t28 Control (PREt28), bit 0 — VMEbus slaves
must wait at least 30ns after the assertion of DS\ before driving DTAck\
low. The PREt28 parameter in the U2SPEC register, however, allows
DTAck\ to be asserted in less than 30ns when executing prefetched
reads.
196
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Section 7: PCI–VME64 Bridge
Improving VME performance
U2SPEC register bit assignments
The U2SPEC bit assignments and descriptions are listed below.
U2SPEC register, offset 0x4FC – bit assignments
Bits
31-24
23-16
15-08
07-00
Function
Universe Reserved
Universe Reserved
Universe Reserved
DTKFLTR Reserved
Universe Reserved
MASt11
POSt28
READt27
Reserved
PREt28
U2SPEC bit descriptions
Name
DTKFLTR
Type
R/W
Reset By
All
MASt11
R/W
All
READt27
R/W
All
POSt28
R/W
All
PREt28
R/W
All
e
Not
Reset State
Function
0
VME DTAck\ Inactive Filter
0 = Slower but better filter, 1 = Faster but poorer filter
0
VME Master Parameter t11 Control (DS\ high time
during BLT’s and MBLT’s)
0 = Default, 1 = Faster
00
VME Master Parameter t27 Control (Delay of DS\
negation after read)
00 = Default, 01 = Faster, 10 = No Delay
0
VME Slave Parameter t28 Control (Time of DS\ to
DTAck\ for posted-write)
0 = Default, 1 = Faster
0
VME Slave Parameter t28 Control (Time of DS\ to
DTAck\ for prefetch read)
0 = Default, 1 = Faster
Bits marked as “Universe Reserved”
must be set to zero (0).
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197
Section 7: PCI–VME64 Bridge
Improving VME performance
198
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Section 7: PCI–VME64 Bridge
Programming notes, Universe II
Programming notes, Universe II
Writing to non-existent VME locations
Problem
The Universe II chip has a problem dealing with non-existent VME
locations. The problem is that the Grackle will not return a machine
check exception to the CPU when a VME write fails with a Bus Error.
Solutions
Workaround #1: First perform a read of the location to verify its
existence.
Workaround #2: Program the Universe II to generate an interrupt upon
VME Bus Error and have this interrupt report a fatal error.
Slave image programming
Problem
Updating a Universe II slave window while VME traffic is using that
window results in data errors even if the register contents are the
same.
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Section 7: PCI–VME64 Bridge
Programming notes, Universe II
Solution
Avoid programming a slave’s image registers while VME is accessing
that slave’s window.
200
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SCSI/Ethernet
Controller
8
This section provides information about the SYM53C885 SCSI/Ethernet
controller interface.
•
General description
•
SYM53C885 registers
•
Programming notes, SYM53C885
e
Not
The bit numbering of registers in this
section follows the zero-on-the-right
convention as opposed to the zero-onthe-left bit numbering convention used
by Motorola and IBM in their PowerPC
documentation.
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201
202
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Section 8: SCSI/Ethernet controller
General description
General description
The VSS4 SCSI and Fast Ethernet interface is provided by a single
multifunction device, the Symbios Logic SYM53C885 PCI-SCSI/Fast
Ethernet Multifunction Controller. On the SCSI side, the SYM53C885
provides a Wide Ultra SCSI interface using a PCI bus master DMA core
and Symbios Logic SCSI SCRIPTS processor. On the Ethernet side, the
SYM53C885 provides a 10/100Base-T Ethernet interface with
independent DMA engines for the transmit and receive channels for
access to the motherboard bus and memory with little or no CPU
intervention.
The Ethernet connection is available at the VSS4 front panel. The SCSI
option is provided with a front panel connector. Refer to Appendix A
for connector information.
Listed below are some of the features of the SYM53C885.
•
•
•
•
•
Fully PCI 2.1 compliant
Full 32-bit PCI DMA bus master
High performance SCSI and Ethernet cores, both highly
programmable
Up to 40MB/s synchronous Wide, Ultra SCSI transfers
10/100 Mb/s Ethernet operation
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203
Section 8: SCSI/Ethernet controller
General description
e
Not
For detailed SYM53C885 programming
information, refer to the Symbios Logic
Data Manual no. T89962I 1296 15MH.
This document (and other supporting
documents) can be obtained by
contacting:
LSI Logic Corporation
1551 McCarthy Blvd
Milpitas CA 95035
United States
Tel: 408.433.8000
FAX: 408.433.8989
Web: http://www.lsilogic.com
A datasheet in PDF format is available
from the LSI Logic website in their Tech
Library:
Document: (P01964I) SYM53C885 Data Sheet (3/98)
204
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
SYM53C885 registers
The operating system PCI discovery routines dynamically set up the
SYM53C885 base address by writing to the appropriate registers in PCI
configuration address space. Note that the SYM53C885 is a
multifunction PCI device. Thus, SCSI and Ethernet functions are
programmed as separate entities by the PCI auto-configuration.
For more information on PCI configuration, refer to the PCI
implementation details discussion in the PCI bus chapter in Section 3,
page 62, and the Setting PCI device base address discussion in Section
4, page 101. Also refer to the Type 0 configuration table on page 108.
The following is an overview of the registers in each interface.
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205
Section 8: SCSI/Ethernet controller
SYM53C885 registers
SCSI registers
PCI configuration
The PCI configuration registers for the SCSI interface are shown below.
Addresses 0x40 through 0xFF are unused.
31
16 15
0
Device ID
0x000D
Vendor ID
0x1000
0x00
Status
Command 0x0000*
0x04
Class Code = 0x010000
BIST
Header Type
Latency Timer
*Note:
206
0x08
Cache Line Size
0x0C
Base Address Register 1
0x10
Base Address Register 2
0x14
Base Address Register 3
0x18
Not Supported
0x1C
Not Supported
0x20
Not Supported
0x24
Reserved
0x28
Subsystem ID
Max_Lat
Revision ID= 0x00
Subsystem Vendor ID
0x2C
Expansion ROM Base Address
0x30
Reserved
0x34
Reserved
0x38
Max_Gnt
Interrupt Pin
Interrupt Line
0x3C
Setting bit0 or bit 1 of the PCI command register enables the SCSI interface to respond
to accesses to the PCI Memory or I/O Address space respectively.
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
Operating registers
The table below lists the SYM53C885 SCSI registers which are accessed
through PCI memory or I/O cycles depending on operation.
SYM53C885 SCSI registers address and descriptions
Addr. Offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10-0x13
0x14
0x18
0x19
0x1A
0x1B
0x1C-1F
0x20
0x21
0x22
0x23
0x24-0x26
0x27
0x28-0x2B
0x2C-0x2F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Label
SCNTL0
SCNTL1
SCNTL2
SCNTL3
SCID
SXFER
SDID
GPREG
SFBR
SOCL
SSID
SBCL
DSTAT
SSTAT0
SSTAT1
SSTAT2
DSA
ISTAT
CTEST0
CTEST1
CTEST2
CTEST3
TEMP
DFIFO
CTEST4
CTEST5
CTEST6
DBC
DCMD
DNAD
DSP
Description
SCSI Control 0
SCSI Control 1
SCSI Control 2
SCSI Control 3
SCSI Chip ID
SCSI Transfer
SCSI Destination ID
General Purpose Bits
SCSI First Byte Received
SCSI Output Control Latch
SCSI Selector ID
SCSI Bus Control Lines
DMA Status
SCSI Status 0
SCSI Status 1
SCSI Status 2
Data Structure Address
Interrupt Status
Reserved
Chip Test 1
Chip Test 2
Chip Test 3
Temporary Register
DMA FIFO
Chip Test 4
Chip Test 5
Chip Test 6
DMA Byte Counter
DMA Command
DMA Next Address For Data
DMA Scripts Pointer
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
SYM53C885 SCSI registers address and descriptions (cont.)
Addr. Offset
0x30-0x33
0x34-0x37
0x38
0x39
0x3A
0x3B
0x3C-0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50-0x51
0x52-0x53
0x54-0x55
0x56-0x57
0x58-0x59
0x5A-0x5B
0x5C-0x5F
0x60-0x7F
208
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R
—
R/W
—
R
—
R/W
R/W
Label
DSPS
SCRATCHA
DMODE
DIEN
SBR
DCNTL
ADDER
SIEN0
SIEN1
SIST0
SIST1
SLPAR
SWIDE
MACNTL
GPCNTL
STIME0
STIME1
RESPID0
RESPID1
STEST0
STEST1
STEST2
STEST3
SIDL
—
SODL
—
SBDL
—
SCRATCHB
ScratchC-J
Description
DMA Scripts Pointer Save
General Purpose Scratch Pad A
DMA Mode
DMA Interrupt Enable
Scratch Byte Register
DMA Control
Sum Output of Internal Adder
SCSI Interrupt Enable 0
SCSI Interrupt Enable 1
SCSI Interrupt Status 0
SCSI Interrupt Status 1
SCSI Longitudinal Parity
SCSI Wide Residue Data
Memory Access Control
General Purpose Control
SCSI Timer 0
SCSI Timer 1
Response ID 0
Response ID 1
SCSI Test
SCSI Test
SCSI Test
SCSI Test
SCSI Input Data Latch
Reserved
SCSI Output Data Latch
Reserved
SCSI Bus Data Lines
Reserved
General Purpose Scratch Pad B
General Purpose Scratch Pad C-J
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
Ethernet registers
PCI configuration
The PCI configuration registers for the Ethernet interface are shown
below. Addresses 0x40 through 0xFF are unused.
31
16 15
0
Device ID
0x0701
Vendor ID
0x1000
0x00
Status
Command 0x0000*
0x04
Class Code = 0x020000
BIST
Header Type
Latency Timer
0x08
Cache Line Size
0x0C
Base Address Zero (I/O), Ethernet Operating Registers
0x10
Base Address One (Memory), Ethernet Operating Registers
0x14
Not Supported
0x18
Not Supported
0x1C
Not Supported
0x20
Not Supported
0x24
Reserved
0x28
Subsystem ID
Max_Lat
*Note:
Revision ID= 0x00
Subsystem Vendor ID
0x2C
Expansion ROM Base Address
0x30
Reserved
0x34
Reserved
0x38
Max_Gnt
Interrupt Pin
Interrupt Line
0x3C
Setting bit0 or bit 1 of the PCI command register enables the Ethernet interface to
respond to accesses to the PCI Memory or I/O Address space respectively.
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
Operating registers
The table below lists the SYM53C885 Ethernet registers which are
accessed through PCI memory or I/O cycles depending on operation.
SYM53C885 Ethernet registers address and descriptions
Addr. Offset
0x00-0x03
0x04-0x05
0x06-0x07
0x08-0x0B
0x0C-0x0F
0x10-0x13
0x14-0x17
0x18-0x1B
0x1C-3F
0x40-0x43
0x44-0x45
0x46-0x47
0x48-0x4B
0x4C-0x4F
0x50-0x53
0x54-0x57
0x58-0x5B
0x5C-0x7F
0x80-0x81
0x82-0x83
0x84-0x85
0x86-0x87
0x88-0x8B
0x8C-0x8F
0x90-0x93
0x0x94
0x95-0x97
0x98-0x9B
0x9C-0x9D
0x9E
0x9F
0xA0-0xA1
0xA2-0xA3
0xA4-0xA5
0xA6-0xA7
210
R/W
R/W
R/W
—
—
R/W
R/W
R/W
R/W
—
R/W
R
—
—
R
R
R
R/W
—
R/W
R/W
R
—
—
—
—
R
R/W
R/W
R/W
Description
Transmit Channel Control
Transmit Channel Status
Reserved
Reserved
Transmit CommandPtrLo
Transmit InterruptSelect
Transmit BranchSelect
Transmit WaitSelect
Reserved
Receive ChannelControl
Receive ChannelStatus
Reserved
Reserved
Receive CommandPtrLo
Receive InterruptSelect
Receive BranchSelect
Receive WaitSelect
Reserved
EventStatus
InterruptEnable
InterruptClear
InterruptStatus
Reserved
Chip Revision
DBDMA Control
TxThreshold
Reserved
Reserved
Reserved
General Purpose
General Purpose Control
Configuration
Back-to-Back Interpacket Gap
Non Back-to-Back Interpacket Gap
MIIM Command
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
SYM53C885 Ethernet registers address and descriptions (cont.)
Addr. Offset
0xA8-0xA9
0xAA-0xAB
0xAC-0xAD
0xAE-0xAF
0xB0-0xCF
0xD0-0xD1
0xD2-0xD3
0xD4-0xD5
0xD6-0xD7
0xD8-0xD9
0xDA-0xDB
0xDC-0sDD
0xDE-0xDF
0xE0-0xE3
0xE4-0xE5
0xE6-0xE7
0xE8-0xEB
0xEC-0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6-0xF7
0xF8-0xFB
0xFC-0xFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
Description
MII Address or TP_PMD Control
MII Write Data
MII Read Data
MII Indicators
Reserved
Address Filter
Station Address 0
Station Address 1
Station Address 2
Hash Table 0
Hash Table 1
Hash Table 2
Hash Table 3
Reserved
PHY Identifier 0
PHY Identifier 1
Reserved
Reserved
EE Status
EE Control
EE Word Address
EE Read Data
EE Write Data
EE Feature Enable
Reserved
Reserved
Reserved
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Section 8: SCSI/Ethernet controller
SYM53C885 registers
212
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Section 8: SCSI/Ethernet controller
Programming notes, SYM53C885
Programming notes, SYM53C885
SCSI prematurely surrendering PCI bus
Problem
Slow SCSI transfers to SCSI drive when VME BLT’s were occurring.
Observation
The SYM53C885 SCSI chip was surrendering the PCI bus in the middle
of a burst read transfer when the Universe II PCI-VME bridge needed to
write data. This was slowing down the SCSI transfers in the face of VME
traffic.
Solution
The solution is to write a value of 20 decimal or greater to the SCSI
chip’s PCI Latency register (0x0D; or 0x0E if big-endian). The C code to
do this in pSOS or VxWorks is below.
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Section 8: SCSI/Ethernet controller
Programming notes, SYM53C885
SetLatency( int value )
{
int temp
value = value & 0xFF; /* Mask value to range of 0-255 */
temp = readMPC( 0x8000600C);
temp = temp &~0xff00;
writeMPC( 0x8000600C, temp | (value <<8) );
/* numbering bytes from right to left, byte 0 is
* the Cache Line length byte at offset 0xC,
* and byte 1 is the Latency timer byte at offset 0xD,
* which is defined as number of PCI clocks of latency.
*/
}
Note that this register should always be set with this value. There is no
downside to setting the PCI Latency register to 20, since that’s the
length of one burst transfer. This means that it’s the optimal setting for
use with the Grackle.
214
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PCI-PCI Bridge
Interface
9
This section provides information about the PCI-PCI bridge chip that
provides the P0•PCI™ bridge interface.
•
General description
•
Registers
•
Configuration
•
Software support, P0•PCI™
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216
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Section 9: PCI-PCI Bridge Interface
General description
General description
Synergy’s P0•PCI™ bus interface provides the VSS4 with a sub-bus for
board-to-board data transfers that are speedier than the VMEbus. The
P0•PCI ™ bus is 64-bits wide and operates at 33 MHz, for a theoretical
maximum aggregate bandwidth of 266 MB/sec. Up to 4 pair of SBCs (8
slots) are allowed on the P0•PCI bus. A single VSS4 can write data to
another VSS4 at about 72 MB/sec over the P0•PCI ™ bus. However,
the rest of the P0•PCI™ bandwidth is not consumed, so other transfers
can occur concurrently up to the maximum bandwidth. The P0•PCI™
bus interface is based on Intel’s (formerly Digital Semiconductor’s)
21554 64-bit PCI-to-PCI bridge chip.
The 21554 chip has two PCI ports, primary and secondary. The primary
port is connected to P0 and the secondary port is connected to the
VSS4’s onboard PCI bus. This connection scheme allows the PCI-PCI
bridge to be used for peer-to-peer communication between multiple
VSS4 boards. Up to 8 boards can be connected together using the
P0•PCI ™ bus.
The P0•PCI™ interface uses the VME64x P0 connector which is inbetween the VME P1 and P2 connectors. Note that the VSS4’s P0
connector may interfere with board insertion in non-VME64x
compatible backplanes. The VSS4 P0•PCI™ interface works in
conjunction with a P0•PCI™ overlay board. See the Installing the P0
overlay chapter in Section 2, page 45, for model descriptions and
installation information. (For ordering information of these components,
contact Synergy Microsystems' Customer Service.)
The external P0•PCI™ overlay board connects P0•PCI™ slots together
from the back side of the VME64x backplane. The overlay board (with
the exception of passive models) includes a plug-in arbiter board which
provides clock generation and round-robin PCI bus arbitration for all
interconnected boards on the P0•PCI™ bus. The arbiter board also
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217
Section 9: PCI-PCI Bridge Interface
General description
provides power-on reset to all devices on the primary side of P0•PCI™
interface.
The diagram below shows the VSS4 PCI-PCI bridge interface in relation
to the other major busses in the system.
PowerPC
CPU(s)
PowerPC Bus
PowerPC
to
PCI Bridge/
Mem. Ctrlr.
Local PCI Bus
PCI
to
PCI Bridge
PCI-PCI Bridge Interface
Additional P0-PCI slots
Sec. Side
Pri. Side
P0•PCI (P0)
P0•PCI Overlay
External to
SBC
Arbiter
Board
Block diagram VSS4 PCI-PCI bridge
218
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Section 9: PCI-PCI Bridge Interface
Registers
Registers
The 21554 contains the following register groups:
Primary and Secondary interface PCI configuration header
registers
• Device-specific configuration registers
• Memory and I/O mapped control and status registers
•
For detailed information on the 21554 PCI-to-PCI bridge, refer to the
“21554 PCI-to-PCI Bridge for Embedded Applications, Hardware
Reference Manual” available from Intel. This document is available as a
PDF file from Intel’s developer website:
http://developer.intel.com/design/bridge/
Application notes, datasheets, and manuals for Intel’s PCI bridges can
be found at this site.
The table below lists recommended related documents available as PDF
files from the Intel developer website (online availability subject to
change without notice).
Related 21554 documents available for download
Document
Specification Update
Product Preview Datasheet
Bridge Performance Optimization, AppNote
Getting Started..., AppNote
Issues w/ Host Processor Card..., AppNote
Embedded Applications...Hardware Reference, Manual
Date
Aug 1998
Sep 1998
Sep 1998
Oct 1998
Sep 1998
Size
88 Kbytes
797 Kbytes
72 Kbytes
94 Kbytes
68 Kbytes
1075 Kbytes
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219
Section 9: PCI-PCI Bridge Interface
Registers
The block diagram below shows the microarchitecture of the 21554
PCI-PCI bridge.
21554
Downstream Delayed Buffer
Downstream Posted Write Buffer
Upstream Read Data Buffer
Downstream Read Data Buffer
Upstream Posted Write Buffer
Secondary
PCI
Bus
Upstream Delayed Buffer
Primary
PCI
Bus
Primary
Target
Control
Primary
Config
Registers
DeviceSpecific
Config
Registers
CSR
Registers
Secondary
Master
Control
Primary
Master
Control
ROM
Interface
Control
JTAG
JTAG Signals
ROM Interface
Signals
Secondary
Config
Registers
Secondary
Target
Control
Secondary
Bus
Arbiter
Interrupt
Signals
Secondary Arbiter
Signals
FM-06188.AI4
Microarchitecture, 21554 PCI-PCI bridge chip
220
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Section 9: PCI-PCI Bridge Interface
Configuration
Configuration
Introduction
The 21554 configuration space is divided into three parts:
•
Primary interface configuration registers
•
Secondary interface configuration registers
•
Device-specific configuration registers
Both the primary and secondary interface configuration headers contain
the 64-byte Type 0 configuration header corresponding to that
interface. The device-specific configuration registers are specific to the
21554, some of which apply to the primary interface, others to the
secondary interface, and some to other 21554 functions.
Access to the 21554 configuration registers is supported from both the
primary (P0•PCI) and secondary (onboard PCI) interfaces. Normally,
however, access to the 21554 configuration space is allowed from the
secondary interface only. In this case, the 21554 returns target retry to
all accesses initiated on the primary bus, with the exception of accesses
to the Reset Control register at Dword 0xD8. Clearing the Primary
Lockout Bit in the Chip Control 0 register allows access to 21554
configuration space from the primary side.
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221
Section 9: PCI-PCI Bridge Interface
Configuration
PCI configuration
The operating system PCI discovery routines dynamically set up the
21554 base address by writing to the appropriate registers in PCI
configuration address space.
The host accesses devices behind the bridge (i.e., devices outside the
local PCI bus) with Type 1 PCI configuration accesses which contain
extra data for bus number and device number. Type 1 accesses are
intended for PCI-PCI bridges only. If a bridge detects that the bus
number is not to the secondary bus of the bridge, the access is passed
through unchanged. If the bus number matches the secondary bus
number, the bridge converts the access to a Type 0 PCI configuration
access. The device number is then decoded and the proper IDSel
asserted to configure the device on the secondary bus.
For more information on PCI configuration, refer to the PCI
implementation details discussion in the PCI bus chapter in Section 3,
page 62, and the Setting PCI device base address discussion in Section
4, page 101. Also refer to the Type 0 configuration table on page 108.
P0•PCI™ configuration
The implementation of configuring the P0•PCI™ bus for each board
connected to the bus, the address ranges and any address translation,
are application-specific. It is recommended that each board be
allocated at least one 256KB window into the onboard memory.
222
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Section 9: PCI-PCI Bridge Interface
Software support, P0•PCI™
Software support, P0•PCI™
Synergy Microsystems provides optional software to support board-toboard communications using the VSS4’s P0•PCI™ interface.
•
•
Global Buffer Manager (GBM) Software Package — The GBM
software package allows sharing of data among processors on
Synergy PPC CPU boards connected via the P0•PCI™ bus
backplane. GBM is available for Linux and VxWorks (contact
factory for availability).
Board Support Package (BSP), Linux and VxWorks — Synergy
Microsystems’ Linux and VxWorks BSP distribution includes
sample software for P0•PCI™.
Contact Synergy Customer Service for more information about these
software options.
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Section 9: PCI-PCI Bridge Interface
Software support, P0•PCI™
224
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Warranties &
Service
10
This section provides information on product warranty and support.
•
Warranty terms and options
•
Customer service
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226
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Section 10: Warranties & Service
Warranty terms & options
Warranty terms & options
This chapter describes the warranty terms and options provided for the
VSS4 SBC.
Warranty terms
Synergy Microsystems, Inc. warrants all standard (off-the-shelf) and nonstandard (custom) products to be free of defects in materials and
workmanship under normal use for the applicable warranty period (as
described below). This limited warranty is void if the failure has resulted
from accident, abuse, alteration, or misapplication by the customer.
Product returns
The following guidelines describe warranty terms for product returns.
•
•
Initial product acceptance — Synergy presumes that customers
will inspect products within 14 days of receipt for conformance
to the specifications stated in this manual (for standard, off-theshelf units) and/or purchasing documentation (for custom units).
Products not rejected within this period are considered by
Synergy to be accepted by the customer.
Delivery rejection — Products that do not conform to the specifications and standards in this manual or purchase documents
can be returned to Synergy for replacement/repair. Before
returning products, notify Synergy of the problem and get a
Return Material Authorization (RMA) number. Board rejection
will not be valid unless boards are returned in the original shipping cartons within 10 days of the receipt of the RMA number.
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Section 10: Warranties & Service
Warranty terms & options
•
•
For more information about returning products, see the next
chapter on Customer service.
If the customer adheres to these requirements, Synergy agrees to
pay shipping charges, otherwise shipment costs must be paid by
the customer.
Delivery turnaround after rejection — Synergy’s service goal is
to return new or refurbished products within 14 days of the
receipt of properly rejected boards that were returned in
accordance with the requirements stated above and in next
chapter.
Product returns under warranty — Once products have been
either accepted or the initial product accept/reject period has
passed, products are warranted for the applicable warranty
period as described below:
For information about returning products under warranty, see
the next chapter on Customer service.
Warranty periods
Synergy Microsystems, Inc. offers the following warranty periods:
•
•
•
228
90-day guarantee and limited warranty — All standard (off-theshelf) and non-standard (custom) products are automatically
guaranteed for 90 days from the day of delivery.
1-year standard limited warranty — Customers who complete
payment for the product to Synergy within 30 days of delivery
receive a free warranty extension for a full year on all products
covered by the payment.
3-year extended limited warranty — If desired, Synergy offers an
extended 3-year warranty for an additional charge. The terms for
the extended warranty are identical to those listed above.
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Section 10: Warranties & Service
Customer service
Customer service
Please contact Synergy Microsystems, Inc. if you have any questions,
comments, or suggestions. You can contact our customer service
department by writing or calling:
Synergy Microsystems, Inc.
9605 Scranton Rd., Suite 700
San Diego, CA 92121-1773
(858) 452-0020
(858) 452-0060 (FAX)
Web: http://www.synergymicro.com
E-mail: [email protected]
Reporting problems
If you encounter any difficulty with your VSS4 board, call Synergy
customer service. If possible, please have the following information
available to assist our staff in assessing your problem:
•
VSS4 model number (silk-screened on solder side of board)
•
Serial number marked on solder side of board
•
VSS4 revision level (silk-screened on the solder side of board)
•
ECO level (marked on solder side of board)
•
Revision level of the Monitor PROM.
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Section 10: Warranties & Service
Customer service
Return policies and procedures
Should it become necessary to return a board to Synergy for repair,
please take the following steps.
❶
❷
❸
❹
❺
Call Synergy Microsystems, Inc. customer service for a Return
Merchandise Authorization (RMA) number. Use this number in
all communications regarding the problem boards.
Provide the following information with all returned items:
• VSS4 model number (solder side of the board)
• Serial number (solder side of board)
• VSS4 revision level (solder side of board)
• ECO level (solder side of board)
• Operating system and Revision level of the Monitor
PROM (or other PROM/EPROM) if used on your board.
The revision level is normally printed on the label of the
DIP EPROM (if so equipped).
• Purchase order number and billing address if the board is
out of warranty.
• Customer contact name, address, and telephone number
• Complete description of the problem.
Carefully package the board to protect it during shipment; be
sure that it is enclosed in an anti-static bag.
Mark the RMA number on the shipping container.
Send the board and the requested information prepaid to
Synergy at the following address:
Synergy Microsystems, Inc.
9605 Scranton Rd., Suite 700
San Diego, CA 92121-1773
An inspection and test charge will be applicable to all units returned for
repair, unless the unit is found to be defective and under warranty. If
the repair charge exceeds the inspection and test charge, we will notify
you of the repair charge. The test and inspection charge will be applied
to your repair charge. No repair (other than test and inspection) will be
performed on products that are out of warranty until we have received
your approval for the charges.
We appreciate your cooperation with these procedures. They help us
give you the best possible service.
230
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Appendix A,
Connectors & Cables
This appendix contains descriptions and diagrams of the VSS4
connectors and specialized cabling:
•
VMEbus connectors (P1 & P2)
•
PMC connectors (P11– P15)
•
P0•PCI bus connector (P0)
•
Memory module connectors (PM1 & PM2)
•
Wide Ultra SCSI connector (P264)
•
Fast Ethernet connector (P240)
•
Asynchronous serial connector (P346)
•
Serial I/O cabling
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231
232
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Appendix A: Cables & Connectors
VMEbus connectors (P1 & P2)
VMEbus connectors (P1 & P2)
The VSS4’s P1 and P2 connectors provide the standard I/O interface to
the VMEbus as listed in the tables below.
e
Not
The P1 connector is the standard 3-row
type for board revision B or lower. For
board revision C or higher, the VME64x
5-row connector is optionally available
for P1.
The P2 connector shows the signals
Synergy has assigned to the user-defined pins for rows A and C (and Z and
D for 5-row option) on the standard
VMEbus. These rows are connected to
the PMC I/O (P14 & P15) connectors
listed later in this chapter.
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233
Appendix A: Cables & Connectors
VMEbus connectors (P1 & P2)
VMEbus P1 connector pinouts
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Notes:
234
Row Z 1
Row A
Row B
Row C
Row D 1
—
D0
BBsy\
D8
+5VPrecharge
Gnd
D1
BClr\
D9
Gnd
—
D2
ACFail\
D10
—
Gnd
D3
BG0In\
D11
—
—
D4
BG0Out\
D12
—
Gnd
D5
BG1In\
D13
—
—
D6
BG1Out\
D14
—
Gnd
D7
BG2In\
D15
—
—
Gnd
BG2Out\
Gnd
GAP\
Gnd
SysClk
BG3In\
SysFail\
GA0\
—
Gnd
BG3Out\
BErr\
GA1\
Gnd
DS1\
BR0\
SysReset\
+3.3V
—
DS0\
BR1\
LWord\
GA2\
Gnd
Write\
BR2\
AM5
+3.3V
—
Gnd
BR3\
A23
GA3\
Gnd
DTAck\
AM0
A22
+3.3V
—
Gnd
AM1
A21
GA4\
Gnd
AS\
AM2
A20
+3.3V
—
Gnd
AM3
A19
—
Gnd
IAck\
Gnd
A18
+3.3V
—
IAckIn\
—
A17
—
Gnd
IAckOut\
—
A16
+3.3V
—
AM4
Gnd
A15
—
Gnd
A7
IRq7\
A14
+3.3V
—
A6
IRq6\
A13
—
Gnd
A5
IRq5\
A12
+3.3V
—
A4
IRq4\
A11
LII\
Gnd
A3
IRq3\
A10
+3.3V
—
A2
IRq2\
A9
LIO\
Gnd
A1
IRq1\
A8
+3.3V
—
-12V
—
+12V
Gnd
Gnd
+5V
+5V
+5V
+5VPrecharge
1. This row present only with optional wide (160-pin) VMEbus P1 & P2 connectors (not
available for VSS4 assembly Revision B or lower).
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Appendix A: Cables & Connectors
VMEbus connectors (P1 & P2)
VMEbus P2 connector pinouts
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Notes:
Row Z 1
(UsrIO66)
Gnd
(UsrIO69)
Gnd
(UsrIO72)
Gnd
(UsrIO75)
Gnd
(UsrIO78)
Gnd
(UsrIO81)
Gnd
(UsrIO84)
Gnd
(UsrIO87)
Gnd
(UsrIO90)
Gnd
(UsrIO93)
Gnd
(UsrIO96)
Gnd
(UsrIO99)
Row A 1
Row B
Row C 1
Row D 1
(UsrIO2)
+5V
(UsrIO1)
(UsrIO65)
(UsrIO4)
Gnd
(UsrIO3)
(UsrIO67)
(UsrIO6)
Retry\
(UsrIO5)
(UsrIO68)
(UsrIO8)
A24
(UsrIO7)
(UsrIO70)
(UsrIO10)
A25
(UsrIO9)
(UsrIO71)
(UsrIO12)
A26
(UsrIO11)
(UsrIO73)
(UsrIO14)
A27
(UsrIO13)
(UsrIO74)
(UsrIO16)
A28
(UsrIO15)
(UsrIO76)
(UsrIO18)
A29
(UsrIO17)
(UsrIO77)
(UsrIO20)
A30
(UsrIO19)
(UsrIO79)
(UsrIO22)
A31
(UsrIO21)
(UsrIO80)
(UsrIO24)
Gnd
(UsrIO23)
(UsrIO82)
(UsrIO26)
+5V
(UsrIO25)
(UsrIO83)
(UsrIO28)
D16
(UsrIO27)
(UsrIO85)
(UsrIO30)
D17
(UsrIO29)
(UsrIO86)
(UsrIO32)
D18
(UsrIO31)
(UsrIO88)
(UsrIO34)
D19
(UsrIO33)
(UsrIO89)
(UsrIO36)
D20
(UsrIO35)
(UsrIO91)
(UsrIO38)
D21
(UsrIO37)
(UsrIO92)
(UsrIO40)
D22
(UsrIO39)
(UsrIO94)
(UsrIO42)
D23
(UsrIO41)
(UsrIO95)
(UsrIO44)
Gnd
(UsrIO43)
(UsrIO97)
(UsrIO46)
D24
(UsrIO45)
(UsrIO98)
Gnd
(UsrIO48)
D25
(UsrIO47)
(UsrIO100)
(UsrIO102)
(UsrIO50)
D26
(UsrIO49)
(UsrIO101)
Gnd
(UsrIO52)
D27
(UsrIO51)
(UsrIO103)
(UsrIO105)
(UsrIO54)
D28
(UsrIO53)
(UsrIO104)
Gnd
(UsrIO56)
D29
(UsrIO55)
(UsrIO106)
(UsrIO108)
(UsrIO58)
D30
(UsrIO57)
(UsrIO107)
Gnd
(UsrIO60)
D31
(UsrIO59)
(UsrIO109)
(UsrIO62)
Gnd
(UsrIO61)
Gnd
(UsrIO64)
+5V
(UsrIO63)
+5VPrecharge
(UsrIO110
Gnd
1. Pins in this row connect to the P14 or P15 PMC connector pin indicated in
parentheses. Space is provided in these columns to write in the assigned signals, if
desired. Refer to the applicable PMC module documentation for P2 pin assignments.
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235
Appendix A: Cables & Connectors
VMEbus connectors (P1 & P2)
236
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Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connectors (P11–P15)
The PMC connectors provide the connection of an add-on PMC (PCI
mezzanine card) card or PMC expansion board for various types of I/O
options. These connectors have the following functions:
•
•
•
•
P11, P12 — 32-/64-bit PCI
P13 — 64-bit PCI (provided as an option)
P14 — standard PCI I/O
P15 — Synergy-proprietary stacking and I/O (provided as an
option)
Synergy Microsystems has made a few minor changes to the standard
PMC connector pinout to support the PEX3 PMC Expansion card.
These changes are:
•
•
•
The JTAG test port is not supported. These pins are used for the
bus request, grant, and clock connections to the PEX3.
The IDSel pin is wired to AD13 on the PMC connector.
VI/O is connected to 5V. This means that all PMC signals are at
5V logic levels.
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237
Appendix A: Cables & Connectors
PMC connectors (P11–P15)
The drawing below shows the locations of the VSS4 PMC connectors.
The tables that follow list the pin assignments of these connectors.
(Refer to Section 2 for PMC card installation instructions.)
P13
P15
P11
P12
P14
PMC connector (P11–P15) locations
238
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Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connector, P11 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Function
PEX3_Gnt\ (TCK)
Gnd
IntB\
—
IntD\
Gnd
Clk2b
Gnd
Req\
VI/O (5V)
AD28
AD25
Gnd
AD22
AD19
VI/O (5V)
Frame\
Gnd
DevSel\
Gnd
— (SDONE)
Par
VI/O (5V)
AD12
AD9
Gnd
AD6
AD4
VI/O (5V)
AD2
AD0
Gnd
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Function
-12V
IntA\
IntC\
+5V
Reserved
Reserved
Gnd
Gnt\
+5V
AD31
AD27
Gnd
CBE3\
AD21
+5V
AD17
Gnd
IRdy\
+5V
Lock\
— (SBO\)
Gnd
AD15
AD11
+5V
CBE0\
AD5
Gnd
AD3
AD1
+5V
Req64B\
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239
Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connector, P12 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
240
Function
+12V
PEX3_Req\ (TMS)
PEX3_Clk (TDI)
Gnd
Reserved
—
Rst\
+3.3V
Reserved
AD30
Gnd
AD24
AD13 (IDSel)
+3.3V
AD18
AD16
Gnd
TRdy\
Gnd
PErr\
+3.3V
CBE1\
AD14
Gnd
AD8
AD7
+3.3V
Reserved
Reserved
Gnd
Ack64B\
Gnd
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Function
Gnd (TRst\)
— (TDO)
Gnd
Reserved
Reserved
+3.3V
—
—
Gnd
AD29
AD26
+3.3V
AD23
AD20
Gnd
CBE2\
Reserved
+3.3V
Stop\
Gnd
SErr\
Gnd
AD13
AD10
+3.3V
Reserved
Reserved
Gnd
Reserved
Reserved
+3.3V
Reserved
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Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connector, P13 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Function
Reserved
Gnd
CBE6\
CBE4\
VI/O (5V)
AD63
AD61
Gnd
AD59
AD57
VI/O (5V)
AD55
AD53
Gnd
AD51
AD49
Gnd
AD47
AD45
VI/O (5V)
AD43
AD41
Gnd
AD39
AD37
Gnd
AD35
AD33
VI/O (5V)
Reserved
Reserved
Gnd
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Function
Gnd
CBE7\
CBE5\
Gnd
Par64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
Gnd
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
Gnd
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
Reserved
Gnd
Reserved
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241
Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connector, P14 pinouts
Pin
Function 1
Pin
Function 1
1
UsrIO1
2
UsrIO2
3
UsrIO3
4
UsrIO4
5
UsrIO5
6
UsrIO6
7
UsrIO7
8
UsrIO8
9
UsrIO9
10
UsrIO10
11
UsrIO11
12
UsrIO12
13
UsrIO13
14
UsrIO14
15
UsrIO15
16
UsrIO16
17
UsrIO17
18
UsrIO18
19
UsrIO19
20
UsrIO20
21
UsrIO21
22
UsrIO22
23
UsrIO23
24
UsrIO24
25
UsrIO25
26
UsrIO26
27
UsrIO27
28
UsrIO28
29
UsrIO29
30
UsrIO30
31
UsrIO31
32
UsrIO32
33
UsrIO33
34
UsrIO34
35
UsrIO35
36
UsrIO36
37
UsrIO37
38
UsrIO38
39
UsrIO39
40
UsrIO40
41
UsrIO41
42
UsrIO42
43
UsrIO43
44
UsrIO44
45
UsrIO45
46
UsrIO46
47
UsrIO47
48
UsrIO48
49
UsrIO49
50
UsrIO50
51
UsrIO51
52
UsrIO52
53
UsrIO53
54
UsrIO54
55
UsrIO55
56
UsrIO56
57
UsrIO57
58
UsrIO58
59
UsrIO59
60
UsrIO60
61
UsrIO61
62
UsrIO62
63
UsrIO63
64
UsrIO64
Note: 1. The function of pins labeled ‘UsrIOxxx’ depends on the add-on card installed on the
board. Space is provided in these columns to write the assigned signals if desired.
242
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Appendix A: Cables & Connectors
PMC connectors (P11–P15)
PMC connector, P15 pinouts
Pin
Function 1
Pin
Function 1
1
UsrIO65
2
UsrIO66
3
UsrIO67
4
Gnd
5
UsrIO68
6
UsrIO69
7
UsrIO70
8
—
9
UsrIO71
10
UsrIO72
11
UsrIO73
12
Gnd
13
UsrIO74
14
UsrIO75
15
UsrIO76
16
—
17
UsrIO77
18
UsrIO78
19
UsrIO79
20
Gnd
21
UsrIO80
22
UsrIO81
23
UsrIO82
24
—
25
UsrIO83
26
UsrIO84
27
UsrIO85
28
Gnd
29
UsrIO86
30
UsrIO87
31
UsrIO88
32
—
33
UsrIO89
34
UsrIO90
35
UsrIO91
36
Gnd
37
UsrIO92
38
UsrIO93
39
UsrIO94
40
—
41
UsrIO95
42
UsrIO96
43
UsrIO97
44
Gnd
45
UsrIO98
46
UsrIO99
47
UsrIO100
48
—
49
UsrIO101
50
UsrIO102
51
UsrIO103
52
Gnd
53
UsrIO104
54
UsrIO105
55
UsrIO106
56
—
57
UsrIO107
58
UsrIO108
59
UsrIO109
60
Gnd
61
Gnd
62
UsrIO110
63
+5V
64
—
Note: 1. The function of pins labeled ‘UsrIOxxx’ depends on the add-on card installed on the
board. Space is provided in these columns to write the assigned signals if desired.
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243
Appendix A: Cables & Connectors
PMC connectors (P11–P15)
244
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Appendix A: Cables & Connectors
P0•PCI bus connector (P0)
P0•PCI bus connector (P0)
The VSS4’s P0•PCI™ connector provides an additional PCI bus
connection to the VSS4’s PCI bus for board-to-board communications
and additional expansion of PCI devices. Boards with the P0•PCI™
interface option require installation in a VME64x compatible backplane
that includes the P0 backplane connector.
Because the VME64x P0 connector has
user-defined pins, make sure that your
backplane’s P0 connections are
compatible with the VSS4’s secondary
PCI bus connector before plugging the
board in. Failure to observe this
warning can cause the complete
destruction of many on-board
components and also voids the
product warranty.
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245
Section A: Cables & Connectors
P0•PCI bus connector (P0)
The drawing below shows the location and pin orientation of the
VSS4’s P0•PCI™ connector. The table that follows lists the pin
assignments of this connector.
P2
Component Side
19
E
D
C
B
A
P0
P1
1
Rear edge of SBC (side view)
P0•PCI bus connector, P0
246
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Appendix A: Cables & Connectors
P0•PCI bus connector (P0)
P0•PCI bus connector (P0) pinouts
Pin Number
A
B
C
D
E
F
1
IntA
AD44
IntB/Gt
IntC/Rq
IntD/Ck
Gnd
2
AD45
AD39
AD37
AD32
AD34
Gnd
3
AD47
AD46
AD42
AD33
AD36
Gnd
4
AD50
AD51
AD48
AD38
AD41
Gnd
5
AD52
AD54
AD53
AD35
AD40
Gnd
6
AD56
AD55
Vcc5V
AD43
Par64
Gnd
7
AD59
AD63
AD60
AD49
AD57
Gnd
8
AD61
CBE6\
CBE4\
AD58
AD62
Gnd
9
CBE5\
AD1
AD0
Req64\
CBE7\
Gnd
10
Ack64\
AD2
AD6
AD5
AD4
Gnd
11
AD3
AD7
AD8
CBE0\
AD9
Gnd
12
AD11
AD12
AD10
Par
AD13
Gnd
13
AD14
SErr\
AD15
AD28
Lock
Gnd
14
Req\
Stop\
SysCon
CBE2\
IRdy\
Gnd
15
CBE1\
PErr\
TRdy\
AD23
AD20
Gnd
16
DevSel\
AD19
AD17
AD24
AD29
Gnd
17
Frame\
CBE3\
AD22
AD27
AD26
Gnd
18
AD16
AD21
IDSel
AD30
AD31
Gnd
19
Gnt\
AD18
AD25
Rst\
Clk
Gnd
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Section A: Cables & Connectors
P0•PCI bus connector (P0)
248
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Appendix A: Cables & Connectors
Memory module connectors (PM1 & PM2)
Memory module connectors (PM1
& PM2)
The field-replaceable RGS3 memory module plugs into the VSS4 board
via connectors PM1 and PM2. The drawing below shows the locations
of these connectors. The table that follows lists the PM1 and PM2 pin
assignments.
e
Not
This connector accepts the following
memory module board(s):
RGS3: 32, 64, 128, 256 or 512MB of
SDRAM
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249
Appendix A: Cables & Connectors
Memory module connectors (PM1 & PM2)
PM1
PM2
2
100
2
100
1
99
1
99
Memory module connector (PM1 & PM2) locations
250
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Appendix A: Cables & Connectors
Memory module connectors (PM1 & PM2)
Memory module connector, PM1 pinouts
Odd Row
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Function
Gnd
PpcDP1
PpcDP2
Gnd
PpcDP5
PpcDP6
Gnd
PpcDH1
PpcDH2
Gnd
PpcDH5
PpcDH6
Gnd
PpcDH9
PpcDH10
Gnd
RamClk3
PpcDH12
Gnd
PpcDH15
PpcDH16
Gnd
PpcDH19
PpcDH20
Gnd
PpcDH23
PpcDH24
Gnd
PpcDH27
PpcDH28
Gnd
PpcDH31
RamClk6
Gnd
PpcDL1
PpcDL2
Gnd
PpcDL5
PpcDL6
Gnd
PpcDL9
PpcDL10
Gnd
PpcDL13
PpcDL14
Gnd
PpcDL17
PpcDL18
Gnd
PpcDL21
Even Row
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Function
PpcDP0
Vcc3V
PpcDP3
PpcDP4
Vcc3V
PpcDP7
PpcDH0
Vcc3V
PpcDH3
PpcDH4
Vcc3V
PpcDH7
PpcDH8
Vcc3V
PpcDH11
RamClk7
Vcc3V
PpcDH13
PpcDH14
Vcc3V
PpcDH17
PpcDH18
Vcc3V
PpcDH21
PpcDH22
Vcc3V
PpcDH25
PpcDH26
Vcc3V
PpcDH29
PpcDH30
Vcc3V
RamClk2
PpcDL0
Vcc3V
PpcDL3
PpcDL4
Vcc3V
PpcDL7
PpcDL8
Vcc3V
PpcDL11
PpcDL12
Vcc3V
PpcDL15
PpcDL16
Vcc3V
PpcDL19
PpcDL20
Vcc3V
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Appendix A: Cables & Connectors
Memory module connectors (PM1 & PM2)
Memory module connector, PM2 pinouts
Odd Row
Pin No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
252
Function
PpcDL22
Gnd
PpcDL25
PpcDL26
Gnd
PpcDL29
PpcDL30
Gnd
RamWrClk
MemRamRE\
Gnd
MemSDCAS\
MemSDRAS\
Gnd
MemCS3\
RamClk5
Gnd
MemCS2\
MemCS5\
Gnd
MemCS0\
MemDQM7
Gnd
MemDQM2
MemDQM5
Gnd
MemDQM0
MemSDBA0
Gnd
MemSDMA2
MemSDMA3
Gnd
MemSDMA6
RamClk4
Gnd
MemSDMA8
MemSDMA9
Gnd
MemSDMA12
—
Gnd
MemID3\
MemID6\
Gnd
MemID1\
MemID4\
Gnd
MbxWrC\
MbxWrB\
Gnd
Even Row
Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Function
PpcDL23
PpcDL24
Vcc3V
PpcDL27
PpcDL28
Vcc3V
PpcDL31
MemRamWE
Vcc3V
RamRdClk
MemWE\
Vcc3V
MemCKE
MemCS7\
Vcc3V
RamClk1
MemCS6\
Vcc3V
MemCS1\
MemCS4\
Vcc3V
MemDQM3
MemDQM6
Vcc3V
MemDQM1
MemDQM4
Vcc3V
MemSDBA1
MemSDMA1
Vcc3V
MemSDMA4
MemSDMA5
Vcc3V
RamClk0
MemSDMA7
Vcc3V
MemSDMA10
MemSDMA11
Vcc3V
—
MemID7\
Vcc3V
MemID2\
MemID5\
Vcc3V
MemID0\
MbxWrD\
Vcc5V
MbxWrA\
MbxLE\
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Appendix A: Cables & Connectors
Wide Ultra SCSI connector (P264)
Wide Ultra SCSI connector
(P264)
A front panel, 68-pin, high-density D-connector provides the connection
to the optional onboard Wide Ultra SCSI port.
The drawing below shows this connector (P264) and its pin 1
orientation. The table that follows lists the P264 pinouts.
7
SMI
Rst
SBC Front Panel
SCSI
Wide Ultra SCSI
Front Panel Connector
Pin 1
A
Wide Ultra SCSI front panel connector (P264)
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253
Appendix A: Cables & Connectors
WIde Ultra SCSI connector (P264)
Wide Ultra SCSI connector, P264 pinouts
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
254
Function
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Term Power
Term Power
—
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Pin No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Function
Data12Data13Data14Data15Parity1Data0Data1Data2Data3Data4Data5Data6Data7Parity0Gnd
Gnd
Term Power
Term Power
—
Gnd
AtnGnd
BsyAckRstMsgSelC/DReqI/OData8Data9Data10Data11-
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Appendix A: Cables & Connectors
Fast Ethernet connector (P240)
Fast Ethernet connector (P240)
The VSS4 board’s Fast Ethernet port connects to the Ethernet
10/100Base-T network via the front panel RJ-45 jack as shown in the
figure below. This chapter lists the pinout for this connector.
The Ethernet connector provided on the VSS4 may be connected to a
hub using a standard (straight-wired) cable, or to another Ethernet port
using a crossover cable. A crossover cable has the Transmit and
Receive pairs swapped on one end.
SBC Front Panel
Serial
A
/
B
/
C
/
D
Ethernet
Fast Ethernet Port
(P240)
Fast Ethernet front panel cable connector
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255
Section A: Cables & Connectors
Fast Ethernet connector (P240)
The figure and table below identify the pinout numbers and signals for
the VSS4 front panel Fast Ethernet connector (P240).
The VSS4’s Fast Ethernet port supports 10Base-T and 100Base-TX. The
other two variations in the 100Base-T standard are not supported
(100Base-T4 and 100Base-FX).
For a 10Base-T Ethernet network, use a Category 3 or higher UTP
(unshielded twisted pair) cable to connect the VSS4 to the 10Base-T
hub.
For a 100Base-TX Ethernet network, use a Category 5 UTP or Type 1
STP (shielded twisted pair) cable to connect the VSS4 board to the Fast
Ethernet hub.
Pre-assembled, twisted-pair Ethernet cables in a variety of lengths and
colors are available from various electronic and computer supply
houses.
2 4 6 8
1 3 5 7
Ethernet 10/100Base-T connector pin numbering
Ethernet 10/100Base-T port (P240) pin assignments
Pin
256
Function
1
Transmit Data+
2
Transmit Data–
3
Receive Data+
4
Shield
5
Shield
6
Receive Data–
7
Shield
8
Shield
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Appendix A: Cables & Connectors
Asynchronous serial connector (P346)
Asynchronous serial connector
(P346)
The VSS4 board’s four asynchronous serial ports are brought out to a
single, 10-pin RJ-50/RJ-69 modular front panel connector as shown in
the figure below. This chapter lists the pinout for this connector. See the
next chapter in this appendix for serial interface cabling.
Async Serial I/O
Ports (P346)
SBC Front Panel
Serial
A
/
B
/
C
/
D
Serial Ports A, B, C & D
RS-232 only
Ethernet
Front panel serial I/O ports cable connector
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257
Appendix A: Cables & Connectors
Asynchronous serial connector (P346)
The figure and table identify the pin numbers and signals for the serial
port RJ-50/RJ-69 connector on the VSS4 front panel.
2 4 6 8 10
1 3 5 7 9
Asynchronous serial connector pin numbering
Serial Ports A, B, C, & D (P346) pin assignments
Pin
258
Function
1
Transmit Data, Serial Port D
2
Transmit Data, Serial Port C
3
Transmit Data, Serial Port B
4
Transmit Data, Serial Port A
5
Ground – (Gnd)
6
Ground – (Gnd)
7
Receive Data, Serial Port A
8
Receive Data, Serial Port B
9
Receive Data, Serial Port C
10
Receive Data, Serial Port D
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Appendix A: Cables & Connectors
Serial I/O cabling
Serial I/O cabling
As described in the previous chapter, the VSS4 provides a front panel
RJ-50/RJ-69 modular jack for connection of the four serial channels.
A single 10-conductor modular cable along with Synergy’s CRJ4 4-port
serial interface adapter breaks out the front panel connector to 4 RJ50/RJ-69 jacks. The external serial devices are connected as required to
these jacks.
The drawing below shows how the CRJ4 4-port serial interface adapter
is used in the system.
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259
Appendix A: Cables & Connectors
Usr
I
PC
Sts
Usr
VM
E
FA
IL
SC
Serial I/O cabling
7 6 5 4
3 2 1 0
X
0
CPU
Y
Z
W
7
SMI
Rst
SCSI
VSS4 Serial Interface Jack
(P346)
10-conductor straight-thru
flat cable with RJ-69/RJ-50
plug on both ends
Serial
A
/
B
/
C
/
D
Ethernet
Jack for VSS4 Connection
(P0)
PMC
CRJ4 Serial Interface Adapter
microsystems
Serial Port D
(P5)
Serial Port C
(P4)
Serial Port B
(P3)
Serial Port A
(P2)
Using the CRJ4 4-port serial interface adapter
260
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Appendix A: Cables & Connectors
Serial I/O cabling
2 4 6 8 10
1 3 5 7 9
P0, P2, P3, P4, P5 connector pin numbering
P0 (to/from SBC) pin assignments
Pin
Function
1
Transmit Data, Serial Port D
2
Transmit Data, Serial Port C
3
Transmit Data, Serial Port B
4
Transmit Data, Serial Port A
5
Ground – (Gnd)
6
Ground – (Gnd)
7
Receive Data, Serial Port A
8
Receive Data, Serial Port B
9
Receive Data, Serial Port C
10
Receive Data, Serial Port D
P2, P3, P4, P5 (to/from ext. serial device) pin assignments
Pin
Function
1
—
2
—
3
—
4
Transmit Data –
5
Ground – (Gnd)
6
Ground – (Gnd)
7
Receive Data –
8
—
9
—
10
—
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261
Appendix A: Cables & Connectors
Serial I/O cabling
262
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Appendix B,
Specifications
The VSS4 SBC conforms to the following set of specifications and
standards.
VMEbus compliance
IEEE 1014 VMEbus Specification; Rev C.1 & D.1
Master:
A32,A24,A16/D32,D16,D08(EO):RMW
RWD,ROR,FAIR:UAT,
BLT32, BLT64.
Slave:
A32,A24:D32,D16,D08(EO):RMW:UAT,
BLT32, BLT64.
Interrupter:
I (1-7):D08(O):ROAK.
Interrupt handler: IH(1-7):D08(O).
Physical dimensions
The VSS4 printed circuit board conforms to VME 6U requirements for
form factor, board spacing, and board thickness:
Board Size:
6U: 6.4"x 9.19"x 0.8" minus front panel
Board Thickness:
0.062 +/- 0.005 inches or 15.24 +/- 0.51 mm
Weight
VSS4:
19 ounces (539g)
Weight (approx.) for board with 512 MB RGS3 memory module and no
PMC card.
Power requirements
VSS4 typical power consumption with no PMC card installed:
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263
Appendix B
Specifications
Typical power consumption
G4 7400/466 MHz
+5.0V +/-5%, 15.7 A typical @ 5.00V (78.5 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
G4 7400/433 MHz
+5.0V +/-5%, 11.0 A typical @ 5.00V (55 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
G4 7400/366 MHz
+5.0V +/-5%, 9.5 A typical @ 5.00V (47.5 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
G4 7410/500 MHz
+5.0V +/-5%, 8.37 A typical @ 5.00V (41.9 W).
±12V ±5%, 50 mA for -12V, 150 mA for +12V
Notes:
1. Measured with board running SMon memory test, memory module = 256 MB, CPU
core voltage = 2.05V and L2 cache ratio = 2:1.
2. Measured with board running ‘powertest’ under Synergy Linux BSP 2.14.12-B,
memory module = 512 MB, CPU core voltage = 1.8V and L2 cache ratio = 2:1.
Voltages must be kept within these tolerances to ensure proper operation.
Operating environment
Temperature:
e
Not
Humidity:
Altitude:
Operating (@ sea level): 0 to +55 °C ambient
with forced air cooling minimum 400 LFM,;
recommended 600 LFM
Non-operating/Storage: -20 to +70 °C
Board configurations that provide a
wider operating temperature range are
available. Contact Customer Service for
a listing of Thermal Capability options.
10% to 90% RH, non-condensing
10,000 ft. max. with battery backup
50,000 ft. max. with capacitor backup option
Capacitor backup option
Time to charge:
Backup duration:
2 hours minimum (capacitor with residual
charge); 12 hours maximum (capacitor fully
discharged)
12 days @ 20 °C, typical
Number of VME slots used
1
Board layout
See drawings below for VSS4 and RGS3 board layout.
264
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Configuration
Jumpers (J02K)
(J02L, Rev. B or
lower)
Board
Stiffener
Clock/Cal/NVRAM
Battery
(soldered in)
Boot Flash
EPROM
(in socket under
EPROM)
DIP EPROM
Socket
EPROM
Configuration
Jumpers
(J902)
Gnd pins
(J602)
PMC Module Front
Panel Cutout
P2
Ethernet
Jack
PMC Sockets
Memory Module
Connectors
P0•PCI Connector (P0)
Wide, Ultra SCSI connector
ISP Prog. (P39U)
P0
Serial Ports
A, B, C & D
P1
CPU
SMI/Reset
Switch
PPC 750/7400
CPU-W
VMEbus Connectors
Monolithic
Heatsink
CPU-Z
CPU-W CPU-Z
CPU-X CPU-Y
CPU-Y CPU-X
Rev. B Rev. C
or lower or higher
Appendix B
Specifications
VSS4 board layout
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265
Appendix B
Specifications
PM1
PM2
Memory module RGS3 board layout
266
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Appendix C,
Board revision summary
This appendix summarizes some of the major changes made to the
VSS4 boards affecting form, fit, and/or function. The paragraphs below
list the changes pertaining to the revision shown.
e
Not
The revision levels for each feature
represents the revision level when the
listed feature was added to the standard
design. Some boards with older revision
levels may have had some of these
features added during previous
rework/upgrades.
Contact Synergy customer service for
upgrade information.
These paragraphs describe changes made to the VSS4 main board.
Revision F
Added power sequencing logic, CPU ICE support, NVRAM
powerdown ramp protection and more ground planes.
Revision E
Changed VME bus drivers to use pre-buffered 5V power.
power busses. Added tweaks for Universe IIB.
Revision D
Upgraded DC-DC power converter modules from DCDX to
DCMX type. Added full JTAG boundary scan capability,
support for 21555 PCI-PCI bridge, and circuitry to
synchronize the application of the 5V/3.3V/2V power busses.
Revision C
Added support for G4 PowerPC (7400), capacitor backup
option for RTC/NVRAM, watchdog timer, 5-row VME64x P1,
VME geographical addressing, and support for not
responding to own VME SysReset\.
Revision B
Improved CPU heatsink assembly. Added system controller
config. jumpers, pull-up and pull-downs for various signals,
Ethernet LEDs to lamp test, and P0-PCI interrupt masking
capabilitly. Changed Ethernet PHYceiver to LXT970 and
Flash registers to new standard. Changed interrupts to be
more compatible with VGM Series.
Revision A
Initial board release.
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267
Appendix C
Board revision summary
RGS3 memory module
These paragraphs describe changes made to recent versions of the
RGS3 memory module.
268
Revision B
PCB notched to clear DC-DC converter module.
Revision A
Initial board release.
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Appendix D,
PEX3 PMC expansion option
The Synergy Microsystems’ PEX3 is an optional 6U board that provides
PMC and memory expansion to certain model Synergy SBCs (using the
Grackle or Chaparral PCI bridge). PEX3 provides three single-width
PMC slots and up to 256 MB of SDRAM and up to 128 MB of Flash.
The PEX3 has PCI bus master capability for fast, direct communication
between the PMCs/onboard memory and devices on the host SBC.
The PEX3 option replaces the regular SBC front panel with a doublewide front panel to form a double-wide module assembly. The PEX3
connects to the host SBC through a stackable Synergy PMC card or
adapter. The stacking design lets the SBC use a PMC/memory
expansion solution without giving up the use of a PMC.
Features
•
Supports three single-width PMCs, one single-width and one
double-width PMC, or one triple-width PMC
•
SDRAM (capable of streaming data) up to 256 MB
•
Flash up to 128 MB
•
PCI bus mastering capability with 2 DMA channels
•
ESD protection
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269
Appendix D
PEX3 PMC expansion option
Block diagram
A functional block diagram of the optional PEX3 expansion board is
shown below.
Front Panel
Fnt. Pnl.
Cutout
Fnt. Pnl.
Cutout
Fnt. Pnl.
Cutout
Local (Internal) Bus, 32-bit @ 33 MHz
ESD
Protect
PCI 9080
PCI Bus Master
Interface
Memory
Controller
32-bit
SDRAM
Flash
Up to 128 MB
Up to 256 MB
Expansion PCI Bus, 64-bit @ 33 MHz
PMC
Expansion
Slot 1
PMC
Expansion
Slot 2
PMC
Expansion
Slot 3
XPMC 1
XPMC 2
XPMC 3
64
I/O Signals
46
I/O Signals
PCI-PCI
Bridge
21154
46
I/O Signals
SBC PMC Interface Connectors
VME User I/O P2 Connector
I/O
Signals
I/O
Signals
PCI
Signals
(via PMC stacking or PSTK/PSTR adapter)
Transition or PIM
Carrier Module
Transition or PIM
Carrier Module
SBC PCI Local Bus
00-0079
PEX3 functional block diagram
270
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P11
P12
P14
01-0114
P2
XPMC1 (PMC 1)
Front Panel
P13
PMC Sockets,
XPMC1 (PMC 1)
JG02
Flash Write
Protect Jumper
PMC Sockets,
XPMC2 (PMC 2)
P24
P23
Opt. Onboard
Flash
P22
P21
XPMC2 (PMC 2)
Front Panel
PMC Sockets,
XPMC3 (PMC 3)
P34
P33
P1
Opt. Onboard
DRAM
XPMC3 (PMC 3)
Front Panel
P32
P31
VMEbus Connectors
Board
Stiffener
PMC (x3)
Shown in
dash outline
Appendix D
PEX3 PMC expansion option
Board layout
The drawing below shows the PEX3 components and PMC modules.
PEX3 board layout
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271
Appendix D
PEX3 PMC expansion option
Front panel layout
The drawing below shows the VSS4/PEX3 front panel layout.
Sts
Usr
User LEDs (0-7)
Usr
E
7 6 5 4
3 2 1 0
X
0
CPU
Y
XPMC 3
8-bit User
Switch
I
VM
PC
Status LEDs
FA
IL
SC
Eject Lever,
upper
Z
W
7
SMI
CPU Halt/Run LEDs
CPU SMI/Reset Switch
Rst
Expansion PMC 3
Front Panel Cutout
(Filler Panel)
A
/
B
/
C
/
D
XPMC 2
Serial
Serial I/O A & B,
RJ-50/RJ-69 Jack
SCSI
Wide Ultra SCSI
Front Panel Connector
Fast Ethernet, RJ-45 Jack
Ethernet
Expansion PMC 2
Front Panel Cutout
(Filler Panel)
PMC
XPMC 1
PMC Module Front Panel
Cutout (Filler Panel)
Expansion PMC 2
Front Panel Cutout
(Filler Panel)
Eject Lever,
lower
03-0255
VSS4/PEX3 option front panel
272
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Appendix D
PEX3 PMC expansion option
Configuration
Flash write protect
Flash Write protect is the only configuration option for PEX3. After
programming the Flash, it can be protected from writes by installing a
.100" jumper shunt on JG02. Install this jumper as required for your
application. See drawing below.
Flash Write
Protect Jumper
ON = write protect
JG02
02-0141
PEX3 Flash write protect jumper, JG02
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273
Appendix D
PEX3 PMC expansion option
Installation
Installing PMC cards
The PEX3 expansion option lets the VSS4 use up to 3 additional singlewidth PMC cards. Perform the following steps to install a PMC card
onto a PEX3 expansion board. Refer to the PMC Card/PEX3 Expansion
Board Installation drawing below for details.
e
Not
The PEX3 expansion board and its PMC
cards are assembled as a sub-unit prior
to mating to the SBC. This allows the
PMC cards to be secured to the
expansion board.
The PEX3 option converts the SBC into
a double-wide module. Ensure that
space is available in the card cage for
your SBC/PEX3 combo.
PEX3 does not support the VITA 32
extension (Processor PCI Mezzanine
Cards, including Second Agent support)
to IEEE 1386.1. Therefore, PMCs that
use IDSelB (e.g., PMCs with two PCI
devices onboard) are not supported by
PEX3.
PMC/PEX3 installation — Required hardware
Item
locator
3
Quantity
Synergy part
in assy
number
4
Fas/HSM25F3S1HA
Item
description
Hex standoff, M2.5 thread, female, 3/16 OD, 1/2 inch long
4
8
Fas/SwM25PS12S
Screw, M2.5 thread, pan head, slotted, 12 mm long, steel
5
2
Fas/SwM25PS14S
Screw, M2.5 thread, pan head, slotted, 14 mm long, steel
6
16*
Fas/SwM25PS6S
Screw, M2.5 thread, pan head, slotted, 6 mm long, steel
* Qty. is 4 ea. per PMC card. Allow 2 ea. to secure the PSTK or PSTR adapter.
PSTK/PSTR adapters
The PEX3 expansion carrier board can stack on top of an installed
Synergy PMC for additional PMC expansion. The Synergy PSTK or PSTR
adapter lets the PEX3 connect to the SBC without the need for a
Synergy PMC. Refer to PMC stacking and P2 I/O routing (page 278)
for details on stacking and the use of the PSTK/PSTR adapter.
274
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Appendix D
PEX3 PMC expansion option
Slot 3 Position
PMC card front panel
(see Detail below)
PMC CARDS
(3 max.)
Slot 2 Position
Slot 1 Position
PEX3 EXPANSION BOARD
6
6
6
FR
O
N
T
6
PMC card
front panel
(see Detail below)
PMC CARD
Filler panel
(remove)
SBC
Bolt-on
type
5
Push-in
type
6
6
4
Front Panel Detail
O-ring
Gasket
B
A
4
6
C
K
6
5
-A
wA
4
Vie
6
Groove
4
PMC Connectors
6
Place o-ring gasket in front panel groove.
4
99-0031
PMC card/PEX3 expansion board installation
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275
Appendix D
PEX3 PMC expansion option
Rubber o-ring gasket in place
PMC Card
Screw, M2.5 thread,
12mm, pan head slot
(8 places)
Tilt PEX3/
PMC assy. to
engage front
panel(s) into
SBC
cutout(s)
PEX3 Expansion Board
PMC Card
Rubber o-ring gasket in place
VMEbus
connectors
Tilt front panel
into SBC cutout
SBC
PMC connectors
6 Screw, M2.5 thread, 6mm,
Eject Lever
pan head slot (4 places)
5 Screw, M2.5 thread, 14mm,
pan head slot (4 places)
4
Screw, M2.5 thread,
12mm, pan head slot
(4 places)
99-0033
View A-A, Side View, PMC card/PEX3 expansion board installation
➊
Power-down and remove SBC from card cage — Power-down
the system and remove the VSS4 SBC from the card cage.
Synergy SBCs contain static-sensitive
devices. Make sure you are properly
grounded (by putting on a ground-strap,
touching a system ground such as a
metallic chassis or case, etc.) before
removing and handling the board. Use
an ESD-protected workstation for
module removal and installation work.
➋
276
Remove PEX3 board from SBC — If not already removed,
remove the PEX3 from the SBC by removing 4 ea. screws (item
4) from PEX3’s VME connectors and 2 ea. screws (item 5) from
underneath the SBC at the front (eject lever).
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Appendix D
PEX3 PMC expansion option
➌
Mount PMC card(s) to PEX3 board (refer to installation
drawings above for assembly details):
a. Place PEX3 face-up on a flat surface of an ESD-protected
workstation.
b. If not already on, install PMC card’s front panel O-ring gasket
(included with PMC card) by slipping gasket into groove
around front panel.
c. Grasp PMC at sides and place card over PEX3 board’s PMC
connectors (at slot position A, B or C). Ensure both PMC and
PEX3 connectors are aligned then press down over PMC
connector area to fully engage PEX3 board connectors.
d. Turn PEX3 board assembly over.
e. Install four 6 mm M2.5 slot-head screws (item 6) from rear
(solder) side of PEX3 board. Two screws engage standoffs on
the PMC card. The other two screws engage threaded holes
in PMC card front panel.
f. Repeat steps ‘b’ through ‘e’ for each PMC card to be
installed on PEX3 board.
❹
Remove appropriate PMC filler panel(s) from SBC/PEX3 front
panel — The filler panel will be one of two types. The first type
simply snaps in place — remove by pushing from the inside. The
second type is an actual blank PMC front panel — remove 2 ea.
6 mm M2.5 slot head securing screws from solder side of board
to remove (see PMC card securing screws location drawing
above).
❺
Ensure that stackable Synergy PMC card or PSTK/PSTR adapter
is installed on SBC — The PEX3 board connects to the SBC via a
stackable Synergy PMC card or a Synergy PSTK/PSTR adapter.
Both of these items have connectors on the opposite side of the
SBC connectors for mating with the PEX3 board’s plug
connectors.
To install a PMC card onto the SBC, refer to the PMC card
installation instructions in Section 2 (page 41).
To install the PSTK/PSTR adapter, plug the adapter onto the SBC
PMC connectors, then secure with 2 ea. screws (item 6) as if
securing the connector portion of a PMC card. (See PMC
card/PEX3 board installation drawing.)
❻
Remove rear stiffener bar (if so equipped) — If the SBC is being
fitted with the PEX3 for the first time, a stiffener bar will be
installed over the VSS4 VME P1 and P2 connectors. Remove 4
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277
Appendix D
PEX3 PMC expansion option
ea. 16 mm securing screws from the VME P1 and P2
connectors. Set aside this hardware plus the 4 ea. 5 mm
standoffs and stiffener bar for possible future use. In place of the
removed hardware, install four ea. standoffs (item 3) on SBC’s
VME P1 and P2 connectors using 4 ea. screws (item 4).
❼
Mount PEX3 board assembly to SBC — Tilt PEX3 board
assembly to engage PMC front panel(s) to SBC front panel
cutout(s). Each O-ring gasket on PMC must engage chamfer in
front panel cutout. Once all front panels are in place, align PEX3
board connector at bottom of Expansion PMC Slot 1 with SBC’s
PMC (or PSTK/PSTR stacking adapter if no PMC is used), then
press down to seat connector.
Pre-existing installation — secure PEX3 board by using two ea.
screws (item 5) in front (underneath SBC) to engage PEX3
standoffs and four ea. screws (item 4) in back to engage
standoffs on SBC. See PMC card/PEX3 expansion board
installation drawing for details.
New installation — Remove screw and nut securing each SBC
eject handle to board. Replace removed hardware with two ea.
screws (item 5). Secure PEX3 in front by screwing in these
screws to PEX3 standoffs. Finish installation by securing rear of
PEX3 with four ea. screws (item 4) which engage standoffs on
SBC VME connectors. See PMC card/PEX3 expansion board
installation drawing for details.
PMC stacking and P2 I/O routing
The schematic below shows the onboard PMC and PMC expansion PCI
bus connections and the I/O routing through the VME P2 user I/O pins.
Use this diagram to plan your PMC installation and P2 I/O wiring.
PMC P2 I/O restriction
The Slot C (or XPMC 3) PMC card on the optional PEX3 expansion
module cannot use the host SBC’s P2 I/O if the onboard Synergy PMC
card uses extended P2 I/O pins (i.e., uses SBC P2 D & Z rows) or if the
PSTR adapter is used. The Slot C PMC card can use the SBC’s P2 I/O if
the onboard Synergy PMC uses standard P2 I/O (e.g., uses only rows A
and C) or if the PSTK (not PSTR) adapter is used.
Note that all PMC cards in the system are free to use front panel I/O
without restriction.
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Appendix D
PEX3 PMC expansion option
SBC
In lieu of a Synergy PMC, a PSTR/PSTK adapter
(diagram below) can be used to install
PEX3 onto the SBC.
PMC #1/PSTR/PSTK
Expansion
Connectors
Connectors
Synergy PMC #1
PCI Bus
SBC PMC
P11
P12
P13
Pass-through,
2nd Synergy PCI
Req, Gnt, Clk
for PEX3
Standard PCI
Req, Gnt, Clk
for PEX3
PCI Circuitry
PEX3
PMC PEX3
P11r
PCI-PCI
Bridge
P12r
P13r
I/O
VME P2,
SBC Slot
P15r
A&C
P14
D&Z
P15
(Signals not passed if
Synergy PMC #1 uses
“extra” I/O pins or if
PSTR adapter is used)
PmcIO 65-110
Expansion
PCI bus
Pass-through
PmcIO 65-110
(PMC C I/O)
PMC C *
P34
VME P2,
PEX3 Slot
UserIO 65-110
D&Z
UserIO 1-64
A&C
I/O
PMC B *
P24
I/O
PMC A *
P14
I/O
* Note: Third-party or Synergy PMC
Synergy PSTK
P11
P12
Synergy PSTR
Pass-through,
2nd Synergy PCI
Req, Gnt, Clk
for PEX3
P13
P11r
P11
P12r
P12
P13r
P13
P15r
P15
UserIO 65-110
P11r
Pass-through,
Standard PCI
Req, Gnt, Clk
for PEX3
P12r
P13r
Pass-through,
PmcIO 65-110
(PMC C I/O)
99-0132
PMC P2 I/O routing/stacking
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279
Appendix D
PEX3 PMC expansion option
Operation
Address map
The table below lists the PEX3 onboard memory and register addresses.
PEX3 memory address map
PCI 9080 Space
Space 0
Local Address
0x0000_0000 – 0x3FFF_FFFF
Device
Flash
Space 1
0x4000_0000 – 0x43FF_FFFF
SDRAM
Space 0
0xC000_0000
Board Type register
Space 0
0xC000_0004
Revision and ECO Level register
Space 0
0xC000_0008
Flash Configuration register
Space 0
0xC000_000C
DRAM Configuration register
*Note:
Flash write width depends on device type, mode, and address.
Access
D8, D16, D32 (R)
D32 (W*)
D8, D16, D32 (RW)
D8 (RO)
D8 (RO)
D8 (RO)
D8 (RO)
PMC PCI interrupts
A PEX3 PMC responds to and generates certain PCI interrupts
depending on the PMC slot in which it is installed. The table below lists
the PEX3 PMC slots’ associated PCI interrupt lines.
PEX3 PCI interrupts
Slot 1 (A)
IntD
IntA
IntB
IntC
Slot 2 (B)
IntC
IntD
IntA
IntB
Slot 3 (C)
IntB
IntC
IntD
IntA
SBC PCI Bus
IntA
Int B
IntC
IntD
For example, if a board in PEX3’s Slot #1 drives its IntA line, it will be
mapped to the SBC’s PCI IntB input. This is an interrupt rotation of 1.
Slot #2 rotates 2 (IntA assertion gets mapped to SBC’s PCI IntC input)
and Slot #3 rotates 3 (IntA assertion gets mapped to SBC’s PCI IntD
input).
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Appendix D
PEX3 PMC expansion option
PCI Type 0 configuration and address
The table below lists the PEX3’s PCI configuration.
PEX3 PCI Type 0 configuration
Device Number
0
1
2
3
Notes:
ID Select
16
17
18
19
Bus Master no.
0
1
2
3
Owner
PMC Slot 1 (A)
PMC Slot 2 (B)
PMC Slot 3 (C)
Flash
PCI Config. Address1
0x800n_0000
0x800n_0800
0x800n_1000
0x800n_1800
1. n = PCI Secondary Bus number for PEX3 21154 bridge.
PCI configuration
The PEX3’s 9080 PCI bus mastering interface chip is automatically
configured via PCI configuration accesses during system startup. The
board’s 9080 driver and the onboard serial EEPROM work in tandem to
set up the chip.
The table below shows the PCI 9080 configuration space.
PEX3, PCI 9080 PCI configuration registers
31
16 15
0
Device ID = 0x9080
Vendor ID = 0x10B5
0x001
Status
Command
0x042
Class Code = 0x0680001
BIST
Header Type
Rev. ID = 0x05
PCI Bus Latency
Timer
Cache Line Size
0x08
2
0x0C
PCI Base Addr 0, Memory Mapped Config. Registers (PCIBAR0)
0x102
PCI Base Addr 1, I/O Mapped Config. Registers (PCIBAR1)
0x142
PCI Base Addr 2, Local Address Space 0 (PCIBAR2, PEX3 Flash)
0x182
PCI Base Addr 3, Local Address Space 1 (PCIBAR3, PEX3 SDRAM)
0x1C2
Unused Base Address (PCIBAR4)
0x20
Unused Base Address (PCIBAR5)
0x24
Cardbus CIS Pointer (not supported)
0x28
Subsystem ID = 0x2321
0x2C1
Subsystem Vendor ID = 0x80F6
PCI Base Address for Local Expansion ROM
0x30
Reserved
0x34
Reserved
1
Max_Lat
Notes:
PCI Access
Min_Gnt
1
0x38
1
Interrupt Pin
1, 2
Interrupt Line
0x3C
Shaded = Register NOT USED for PEX3
1. EEPROM Writeable
2. PCI Writeable
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Appendix D
PEX3 PMC expansion option
PCI 9080 basic set up
The PCI 9080 set up for PEX3 is summarized below. Since PCI 9080
setup is done by Synergy’s SMon software and/or BSP OS (Linux,
VxWorks), the following is provided for information only.
The PEX3 PCI 9080 operates in C bus mode (separate nonmultiplexed
32-bit address & data busses) with no local masters, i.e.; no Req used
on the local bus.
e
Not
Refer to the PLX PCI 9080 datasheet for
detailed device information. The PCI
9080 datasheet is available as a PDF file
from the PLX Technology website:
www.plxtech.com
The PCI 9080 has three local address spaces of which two are used by
the PEX3, Space 0 and Space 1.
Space 0 is used for Flash memory in operation mode, and capability
register space at driver initialization time.
•
•
•
BTerm\ and Burst disabled and READY# Input enabled
(hardware wait states)
Read-ahead disabled during programming, enabled during
operation (if so configured)
Local base address = 0x0000_0000 for Flash; 0xC000_0000 for
registers
Space 1 is used for SDRAM memory.
•
•
•
282
BTerm\ and Burst enabled and READY# Input enabled
(hardware wait states)
Read-ahead enabled if so configured
Local base address = 0x4000_0000
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Appendix D
PEX3 PMC expansion option
Registers
In addition to the PCI configuration registers, the 9080 chip has these
groups of registers.
•
Local Configuration Registers
•
Runtime Registers (typically not used for PEX3)
•
DMA Registers
•
Messaging Queue Registers (typically not used for PEX3)
Refer to the PLX PCI 9080 documentation for detailed 9080 register
information.
The PEX3 is also provided with the following onboard capability
registers.
•
Board Type Register
•
Revision and ECO Level Register
•
Flash Configuration Register
•
SDRAM Configuration Register
The following describes PEX3’s onboard read-only registers. These
registers are intended to be read during driver initialization time using
Space 0. This information configures the driver accordingly.
The register bit description uses the notation listed below in each bit
position to show the register’s value after a board reset (i.e., power
cycling or system reset).
Register bit description notations for reset value
Notation
x
—
1
0
What it means
Unused bit; set to 0 for future compatibility
Read-only bit
Set to 1 upon reset
Set to 0 upon reset
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Appendix D
PEX3 PMC expansion option
Board type register, 0xC000_0000 (RO)
Bit 7
0
6
0
5
4
0
3
0
0
2
0
1
0
0
0
Reset value
Bit assignments:
Bit(s)
b7–b4
b3–b0
Function
Board Type
Reserved
Values
0x0 = PEX3
—
A byte read of this register indicates board type.
Revision and ECO level register, 0xC000_0004 (RO)
Bit 7
—
6
5
4
3
2
1
0
—
—
—
—
—
—
—
Reset value
Bit assignments:
Bit(s)
b7–b4
b3–b0
Function
Board Revision
ECO Level
Values
0x0 = a
0x1 = b
0x2 = c
↓
:
0xF = p
0x0 = none
0x1 = 1
0x2 = 2
↓
:
0xF = 15
A byte read of this register reveals the board revision level (higher order
nibble) and ECO level (lower order nibble).
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Appendix D
PEX3 PMC expansion option
Flash configuration register, 0xC000_0008 (RO)
Bit 7
0
6
0
5
4
x
x
3
2
0
0
1
x
0
x
Reset value
Bit assignments:
Bit(s)
b7–b6
b5–b3
Function
Reserved
Flash ROM Chip Size
b3–b2
b1–b0
Reserved
Number of Flash ROM banks installed
Values
—
0x0 = 2x16Mb chips or 4 MB per bank
0x1 = 2x32Mb chips or 8 MB per bank
0x2 = 2x64Mb chips or 16 MB per bank
0x3 = 2x128Mb chips or 32 MB per bank
—
0x0 = No Flash installed
0x1 = 1 bank installed
0x2 = 2 banks installed
0x3 = 4 banks installed
Init code is to read the contents of this register to determine how Flash
(if installed) is to be set up.
DRAM configuration register, 0xC000_000C (RO)
Bit 7
0
6
0
5
4
x
x
3
2
0
0
1
x
0
x
Reset value
Bit assignments:
Bit(s)
b7–b6
b5–b3
Function
Reserved
DRAM Chip Size
b3–b2
b1–b0
Reserved
Number of DRAM banks installed
Values
—
0x0 = 2x64Mb chips or 16 MB per bank
0x1 = 2x128Mb chips or 32 MB per bank
0x2 = 2x256Mb chips or 64 MB per bank
0x3 = Reserved for future use
—
0x0 = No DRAM installed
0x1 = 1 bank installed
0x2 = 2 banks installed
0x3 = 4 banks installed
Init code is to read the contents of this register to determine how
DRAM (if installed) is to be set up.
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Appendix D
PEX3 PMC expansion option
Using PEX3 memory
The PEX3’s Flash and SDRAM each have a PCI window pointed to by
the 9080’s PCI Base Address Registers (BAR) 2 and 3, respectively.
Upon reset, the device reads its configuration EEPROM to get the initial
values for all of its registers. The PCI windows are then normally
assigned to particular addresses by PCI auto-initialization code, such as
that run by SMon, the Synergy ROM monitor. Software can then
determine where the PCI windows have been allocated by issuing a
find-PCI-device (or similar) system call and reading the device’s BARs.
Once the memory is mapped into PCI space, it is accessible to the host
processor(s) and other PCI devices in the system. The dual DMA
channels of the PCI interface allows PCI bus mastering for fast memory
accesses. Typical uses include any combination of:
•
Expansion RAM
•
Expansion Flash
•
Buffer for a PMC I/O board with DMA
•
Buffer for a passive (target-only) PMC I/O board
If a given PCI window is at least as large as the memory behind it, no
windowing control is needed: all of the memory is directly accessible.
For smaller windows, the 9080’s Local Base Address register must be
adjusted.
Reading the Flash is similar to reading PEX3 SDRAM (i.e., both are
accessed through a window). Writing to Flash, however, requires
special code. The PowerPC Series SMon monitor includes a full set of
Flash commands. The Flash driver is also available from Synergy.
Contact Customer Service for more information.
VxWorks BSP PEX3 driver
Synergy’s VxWorks BSP includes a PEX3 driver named ‘exmem’. The
header file for it is exmem.h. To include the driver in the kernel, define
INCLUDE_EXMEM. The driver is initialized on startup.
The PEX3 Flash and DRAM are accessed through a PCI window. The
window size is stored in the PEX3’s PCI-configuration EEPROM. Use the
wrEEPEX3() SMon routine to change the size of this window as
required. Access the DRAM window by first calling exmemDRamAdr()
with a DRAM offset. This points the window to that section of DRAM
and returns the actual access address.
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Appendix D
PEX3 PMC expansion option
Note that if the DRAM needs to be accessed by multiple threads, use a
wrapper routine and a window-ownership semaphore to manage it.
PEX3 connector pinouts
Because the VME P2 connectors have
user-defined pins, make sure that your
backplane’s P2 connectors are
compatible with the PEX3’s P2 wiring
before powering up the board. Failure
to observe this warning can cause the
complete destruction of many onboard components and also voids the
product warranty.
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Appendix D
PEX3 PMC expansion option
VMEbus connectors (P1 & P2)
VMEbus P1 connector pinouts
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Notes:
288
Row Z 1
Row A
Row B
Row C
Row D 1
—
—
—
—
+5V
Gnd
—
—
—
Gnd
—
—
—
—
—
Gnd
—
BG0\
—
—
—
—
BG0\
—
—
Gnd
—
BG1\
—
—
—
—
BG1\
—
—
Gnd
—
BG2\
—
—
—
Gnd
BG2\
Gnd
—
Gnd
—
BG3\
—
—
—
Gnd
BG3\
—
—
Gnd
—
—
—
+3.3V
—
—
—
—
—
Gnd
—
—
—
+3.3V
—
Gnd
—
—
—
Gnd
—
—
—
+3.3V
—
Gnd
—
—
—
Gnd
—
—
—
+3.3V
—
Gnd
—
—
—
Gnd
—
Gnd
—
+3.3V
—
IAck\
—
—
—
Gnd
IAck\
—
—
+3.3V
—
—
Gnd
—
—
Gnd
—
—
—
+3.3V
—
—
—
—
—
Gnd
—
—
—
+3.3V
—
—
—
—
—
Gnd
—
—
—
+3.3V
—
—
—
—
—
Gnd
—
—
—
+3.3V
—
-12V
—
+12V
Gnd
Gnd
+5V
+5V
+5V
—
1. This row present only with optional wide (160-pin) VMEbus P1 & P2 connectors.
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Appendix D
PEX3 PMC expansion option
VMEbus P2 connector pinouts
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Notes:
Row Z 1,3
Row A 2
Row B
Row C 2
Row D 1,3
(UsrIO66)
(UsrIO2)
(UsrIO1)
(UsrIO65)
+5V
(UsrIO4)
(UsrIO3)
(UsrIO67)
Gnd
Gnd
(UsrIO69)
(UsrIO6)
(UsrIO5)
(UsrIO68)
—
(UsrIO8)
(UsrIO7)
(UsrIO70)
Gnd
—
(UsrIO72)
(UsrIO10)
(UsrIO9)
(UsrIO71)
—
(UsrIO12)
(UsrIO11)
(UsrIO73)
Gnd
—
(UsrIO75)
(UsrIO14)
(UsrIO13)
(UsrIO74)
—
(UsrIO16)
(UsrIO15)
(UsrIO76)
Gnd
—
(UsrIO78)
(UsrIO18)
(UsrIO17)
(UsrIO77)
—
(UsrIO20)
(UsrIO19)
(UsrIO79)
Gnd
—
(UsrIO81)
(UsrIO22)
(UsrIO21)
(UsrIO80)
—
(UsrIO24)
(UsrIO23)
(UsrIO82)
Gnd
Gnd
(UsrIO84)
(UsrIO26)
(UsrIO25)
(UsrIO83)
+5V
(UsrIO28)
(UsrIO27)
(UsrIO85)
Gnd
—
(UsrIO87)
(UsrIO30)
(UsrIO29)
(UsrIO86)
—
(UsrIO32)
(UsrIO31)
(UsrIO88)
Gnd
—
(UsrIO90)
(UsrIO34)
(UsrIO33)
(UsrIO89)
—
(UsrIO36)
(UsrIO35)
(UsrIO91)
Gnd
—
(UsrIO93)
(UsrIO38)
(UsrIO37)
(UsrIO92)
—
(UsrIO40)
(UsrIO39)
(UsrIO94)
Gnd
—
(UsrIO96)
(UsrIO42)
(UsrIO41)
(UsrIO95)
—
(UsrIO44)
(UsrIO43)
(UsrIO97)
Gnd
Gnd
(UsrIO99)
(UsrIO46)
(UsrIO45)
(UsrIO98)
—
(UsrIO48)
(UsrIO47)
(UsrIO100)
Gnd
—
(UsrIO102)
(UsrIO50)
(UsrIO49)
(UsrIO101)
—
(UsrIO52)
(UsrIO51)
(UsrIO103)
Gnd
—
(UsrIO105)
(UsrIO54)
(UsrIO53)
(UsrIO104)
—
(UsrIO56)
(UsrIO55)
(UsrIO106)
Gnd
—
(UsrIO108)
(UsrIO58)
(UsrIO57)
(UsrIO107)
—
(UsrIO60)
(UsrIO59)
(UsrIO109)
Gnd
—
(UsrIO110)
(UsrIO62)
(UsrIO61)
Gnd
Gnd
(UsrIO64)
(UsrIO63)
Gnd
+5V
—
1. Pins in this row connect to Expansion PMC 2’s P24 connector pin indicated in
parentheses. Space is provided in these columns to write in the assigned signals, if
desired. Refer to the applicable PMC module documentation for P2 pin assignments.
2. Pins in this row connect to Expansion PMC 1’s P14 connector pin indicated in
parentheses. Space is provided in these columns to write in the assigned signals, if
desired. Refer to the applicable PMC module documentation for P2 pin assignments.
3. This row present only with optional wide (160-pin) VMEbus P1 & P2 connectors.
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289
Appendix D
PEX3 PMC expansion option
PMC connectors
PMC connector, P11, P21, & P31 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Note:
290
Function (P11, P21, P31)
Pin
Function (P11, P21, P31)
Gnd
2
-12V
Gnd
4
(IntB\, IntC\, IntD\)1
1
(IntC\, IntD\, IntA\)
6
(IntD\, IntA\, IntB\) 1
—
8
+5V
(IntA\, IntB\, IntC\) 1
10
—
Gnd
12
—
Clk
14
Gnd
Gnd
16
Gnt\
Req\
18
+5V
VI/O
20
AD31
AD28
22
AD27
AD25
24
Gnd
Gnd
26
CBE3\
AD22
28
AD21
AD19
30
+5V
VI/O
32
AD17
Frame\
34
Gnd
Gnd
36
IRdy\
DevSel\
38
+5V
Gnd
40
Lock\
—
42
—
Par
44
Gnd
VI/O
46
AD15
AD12
48
AD11
AD9
50
+5V
Gnd
52
CBE0\
AD6
54
AD5
AD4
56
Gnd
VI/O
58
AD3
AD2
60
AD1
AD0
62
+5V
Gnd
64
Req64\
1. PMC interrupts set in hardware as follows: PEX3 PMC 1 Int rotates by 1 (e.g., IntA\ =
IntB\); PEX 3 PMC 2 rotates by 2 (e.g., IntA\ = IntC\); PEX 3 PMC 3 rotates by 3 (e.g.,
IntA\ = IntD\). See page 280.
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Appendix D
PEX3 PMC expansion option
PMC connector, P12, P22, & P32 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Function (P12, P22, P32)
+12V
+3.3V
+3.3V
Gnd
—
+3.3V
Rst\
+3.3V
—
AD30
Gnd
AD24
(AD16, AD17, AD18) IDSel
+3.3V
AD18
AD16
Gnd
TRdy\
Gnd
PErr\
+3.3V
CBE1\
AD14
Gnd
AD8
AD7
+3.3V
—
—
Gnd
Ack64\
Gnd
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Function (P12, P22, P32)
Gnd
—
Gnd
—
—
+3.3V
Gnd
Gnd
Gnd
AD29
AD26
+3.3V
AD23
AD20
Gnd
CBE2\
—
+3.3V
Stop\
Gnd
SErr\
Gnd
AD13
AD10
+3.3V
—
—
Gnd
—
—
+3.3V
—
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291
Appendix D
PEX3 PMC expansion option
PMC connector, P13, P23, & P33 pinouts
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
292
Function (P13, P23, P33)
—
Gnd
CBE6\
CBE4\
VI/O
AD63
AD61
Gnd
AD59
AD57
VI/O
AD55
AD53
Gnd
AD51
AD49
Gnd
AD47
AD45
VI/O
AD43
AD41
Gnd
AD39
AD37
Gnd
AD35
AD33
VI/O
—
—
Gnd
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Function (P13, P23, P33)
Gnd
CBE7\
CBE5\
Gnd
Par64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
Gnd
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
Gnd
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
—
Gnd
—
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Appendix D
PEX3 PMC expansion option
PMC connector, P14 pinouts (PMC 1)
Pin
Function 1
Pin
Function 1
1
UsrIO1
2
UsrIO2
3
UsrIO3
4
UsrIO4
5
UsrIO5
6
UsrIO6
7
UsrIO7
8
UsrIO8
9
UsrIO9
10
UsrIO10
11
UsrIO11
12
UsrIO12
13
UsrIO13
14
UsrIO14
15
UsrIO15
16
UsrIO16
17
UsrIO17
18
UsrIO18
19
UsrIO19
20
UsrIO20
21
UsrIO21
22
UsrIO22
23
UsrIO23
24
UsrIO24
25
UsrIO25
26
UsrIO26
27
UsrIO27
28
UsrIO28
29
UsrIO29
30
UsrIO30
31
UsrIO31
32
UsrIO32
33
UsrIO33
34
UsrIO34
35
UsrIO35
36
UsrIO36
37
UsrIO37
38
UsrIO38
39
UsrIO39
40
UsrIO40
41
UsrIO41
42
UsrIO42
43
UsrIO43
44
UsrIO44
45
UsrIO45
46
UsrIO46
47
UsrIO47
48
UsrIO48
49
UsrIO49
50
UsrIO50
51
UsrIO51
52
UsrIO52
53
UsrIO53
54
UsrIO54
55
UsrIO55
56
UsrIO56
57
UsrIO57
58
UsrIO58
59
UsrIO59
60
UsrIO60
61
UsrIO61
62
UsrIO62
63
UsrIO63
64
UsrIO64
Note: 1. The function of pins labeled ‘UsrIOxxx’ depends on the add-on card installed on the
board. Space is provided in these columns to write the assigned signals if desired.
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293
Appendix D
PEX3 PMC expansion option
PMC connector, P24 (PMC 2) & P34 (PMC 3) pinouts
Pin
Function (P24, P34)1
Pin
Function (P24, P34)1
1
UsrIO65
2
UsrIO66
3
UsrIO67
4
UsrIO68
5
UsrIO69
6
UsrIO70
7
UsrIO71
8
UsrIO72
9
UsrIO73
10
UsrIO74
11
UsrIO75
12
UsrIO76
13
UsrIO77
14
UsrIO78
15
UsrIO79
16
UsrIO80
17
UsrIO81
18
UsrIO82
19
UsrIO83
20
UsrIO84
21
UsrIO85
22
UsrIO86
23
UsrIO87
24
UsrIO88
25
UsrIO89
26
UsrIO90
27
UsrIO91
28
UsrIO92
29
UsrIO93
30
UsrIO94
31
UsrIO95
32
UsrIO96
33
UsrIO97
34
UsrIO98
35
UsrIO99
36
UsrIO100
37
UsrIO101
38
UsrIO102
39
UsrIO103
40
UsrIO104
41
UsrIO105
42
UsrIO106
43
UsrIO107
44
UsrIO108
45
UsrIO109
46
UsrIO110
47
—
48
—
49
—
50
—
51
—
52
—
53
—
54
—
55
—
56
—
57
—
58
—
59
—
60
—
61
—
62
—
63
—
64
—
Note: 1. The function of pins labeled ‘UsrIOxxx’ depends on the add-on card installed on the
board. Space is provided in these columns to write the assigned signals if desired.
294
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Glossary
The paragraphs below define and describe some of the terms used in
this manual. The definition entries observe the following conventions:
•
•
Terms in definitions that appear (in italics and in parentheses) are
related and/or alternative terms or acronym translations for the
term being defined.
Terms in definitions that appear in boldface in definitions are
defined elsewhere in the glossary.
10Base-T
a type of Ethernet that uses unshielded twisted-pair (UTP)
cable and modular RJ-45 connectors for LAN
connections in a star configuration (i.e., each network
node connects to a common hub). Data rate is the same
as standard Ethernet: 10 Mbps.
100Base-T
similar to 10Base-T except that the data rate is 100
Mbps. 100Base-TX uses two pairs of a Category 5 cable.
100Base-T4 uses 4 pairs of a Category 3 cable. Also
called Fast Ethernet.
A16/D16
specifies a microprocessor bus’ address and data bus
size. This value specifies a 16-bit wide address bus and
16-bit wide data bus.
A16/D32
specifies a 16-bit wide address bus and 32-bit wide data
bus
A24/D16
specifies a 24-bit wide address bus and 16-bit wide data
bus.
A24/D32
specifies a 24-bit wide address bus and 32-bit wide data
bus.
A32/D16
specifies a 32-bit wide address bus and 16-bit wide data
bus.
A32/D32
specifies a 32-bit wide address bus and 32-bit wide data
bus.
AM code bits
(Address Modifier) code bits, AM0–AM5, used by the
VMEbus to identify the size of address being expressed
(A16, A24, A32, A40 or A64) and the type of transfer
(Address-only, program, data, BLT32, BLT64 or IAck)
being performed.
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295
Glossary
296
banner
a message displayed on a CRT screen when a debug
monitor or operating system is starting.
base address
the lowest address in a range of addresses. Usually the
lowest address of a memory window, or of a set of
peripheral registers
BCD
(Binary Coded Decimal) a coding system in which four
binary (1s and 0s) digits represent each digit in a decimal
(0 through 9) value.
Big-Endian
see Endian.
bit
the smallest unit of data represented as either a 1 (ON or
true) or 0 (OFF or false).
BLT
(Block Transfer) a data transfer method for moving large
amounts (blocks) of data. A BLT cycle is faster and more
efficient than a regular R/W cycle because the address to
start the transfer of multiple bytes is presented only
once.
bridge
a chip that connects two different busses together. A
bridge may be either transparent, meaning that it does
not translate the addresses passing through it, or it may
be non-transparent, meaning that it translates addresses.
byte
a unit of data eight bits in length.
cache line
the amount of memory read into or out of cache in a
single operation. This is 32 bytes in 60x and 7xx
PowerPC processors.
cache memory
special RAM memory that provides the processor with
quicker, more direct access to data. The use of cache
memory increases performance as time is saved by not
having to access the relatively slower main memory
circuits for data. See also L1 cache and L2 cache.
category 3
unshielded twisted-pair cable specification that functions
at 10 Megabits per second on each pair.
category 5
unshielded twisted-pair cable specification that functions
at 100 Megabits per second on each pair.
clock/calendar
a device that records the progress of the time and date
and makes this information available to programs
running on the computer system.
collision
the simultaneous transmission of Ethernet packets by
two or more Ethernet nodes, resulting in a garbled
transmission. A collision occurs when two Ethernet
nodes attempt to send a packet at the same time.
Collisions are handled with the CSMA/CD protocol.
CPU
(Central Processing Unit) central controlling device in a
computer system.
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Glossary
CRT
(Cathode Ray Tube) normally refers to a viewing screen;
also used as a synonym for terminal.
data
broadcasting
a bus communications technique in which a single CPU
board can send data to multiple CPU boards at the same
time.
DB-9
a “D” shaped serial interface connector for I/O cabling
that provides access to up to 9 separate lines or pins on
a matching connector.
DB-25
a “D” shaped serial interface connector for I/O cabling
that provides access to up to 25 separate lines or pins on
a matching connector.
DCE
(Data Communications Equipment) the end of a serial
communications link that is, or mimics, a modem
(opposite of DTE).
differential
a method of signaling in which two wires are used, each
carrying opposite versions of the signal information. This
is done to increase maximum cable drive and to increase
noise immunity. For example, a pair of signals are called
SD0+ and SD0-. A 1 data bit may be represented by +5V
on SD0+ and 0V on SD0-, and a 0 bit by 0V on SD0+
and +5V on SD0-. See single-ended.
DMA
(Direct Memory Access) a data transfer method in which
data can pass between peripheral devices and memory
without intervention by the CPU.
DRAM
(Dynamic Random Access Memory) high density fast
access memory storage media that must be refreshed at
continuous intervals. Also simply referred to as RAM
DTE
(Data Terminal Equipment) the end of a serial
communications link that is, or mimics, a terminal or
printer (opposite of DCE).
DUART
(Dual Universal Asynchronous Receiver/ Transmitter) see
UART.
dual-ported
a memory architecture which allows more than one
access path to memory.
dynamic RAM
see DRAM.
ECO
(Engineering Change Order) an engineering document
that describes and orders a change to a released
product.
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297
Glossary
298
Endian
refers to the addressing of individual bytes within a 16,
32 or 64-bit number. Byte ordering that begins with the
highest order byte as Byte 0 is referred to as Big-Endian.
Byte ordering that begins with the lowest order byte as
Byte 0 is referred to as Little-Endian. The programming
community borrowed the Endian terms from the story
“Gulliver’s Travels” by Jonathan Swift. In Swift’s novel,
there were two ways of breaking eggs before eating
them. People who broke their eggs from the large end
were called Big-Endians; people who broke their eggs
from the small end were called Little-Endians.
EPROM
(Erasable Programmable Read Only Memory) a special
type of PROM whose programming can be erased by
exposure to ultraviolet light and then reprogrammed.
Ethernet
a high speed (10Mb/sec) communications protocol and
cable standard for computer networks.
Fast Ethernet
see 100BASE-T.
FIFO
(First-In-First-Out) a data storage technique in which the
first item stored in memory is also the first item on the
stack of items for retrieval. Also a piece of hardware that
stores data in such a manner.
Flash memory
a nonvolatile, random access, and rewritable solid-state
storage technology that is ideal for field-upgradeable
code storage. Flash memory is electrically erased and
programmed in-circuit.
floating point
method to represent numbers using the significant digits
(mantissa) multiplied by the base of the number raised to
the appropriate power (exponent). Values expressed in
floating point form are similar in structure to number
expressed in “scientific notation.”
FPU
(Floating Point Unit) a floating point co-processor.
GPS receiver
a radio receiver that locks onto the GPS (Global
Positioning System) satellites in orbit around the earth.
Using a GPS receiver, you can pinpoint your exact
location anywhere on earth and use the GPS satellite’s
onboard atomic clock as a time reference.
IAck\
(Interrupt Acknowledge) a VMEbus signal used by a
Master to indicate that an interrupt was received.
IBM
manufacturer of the Selectric typewriter and inventor of
the 80-column punched card. Collaborated with
Motorola and Apple Computer in 1991 to invent the
PowerPC based on IBM’s RISC design called POWER
(Performance Optimization With Enhanced RISC).
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Glossary
interrupter
a circuit that sources interrupts, usually at the behest of
peripherals. An interrupter must drive an interrupt line
and provide a vector number during an interrupt
acknowledge cycle. In VMEbus devices, it may cease
driving the interrupt line upon the interrupt being
acknowledged (ROAK) or wait until a register access to
the peripheral explicitly removes the request (RORA).
interrupt handler
a circuit (usually in conjunction with a CPU) that
acknowledges and handles interrupts.
I/O
(Input/Output)
ISP
(In-System Programmable logic) a high density
programmable logic device that can be programmed
while the device is in the circuit. ISP logic can be
upgraded easily in the field using a standard PC and a
simple adapter cable.
JEDEC
(Joint Electronic Device Engineering Council) a body that
sets standards for chip packages and pinouts.
L1 cache
a type of cache memory that is most closely coupled to
the CPU core. It is built into the processor chip and is
typically smaller and faster than L2 cache.
L2 cache
a type of cache memory that is external to the processor
chip inbetween the CPU core and main memory. It is
typically larger and slower than L1 cache.
LED
(Light Emitting Diode) a diode that emits light when
forward biased, commonly used for displays and
indicators.
Little-Endian
see Endian.
longword
a unit of data 32 bits in length.
mailbox
mechanism to allow any CPU or other Master to
interrupt any other CPU of its choice.
Master
a device that initiates and controls the transfer of
addresses and data across a bus. The opposite of Slave.
mem protect
(Memory protect) a bit that can be set or cleared in the
Mode register. It usually is set to disable write accesses
to the board and cleared to enable them, but its
meaning can be changed via PALs or ISPs.
MMU
(Memory Management Unit) a circuit that provides
address translation and access control services for a
CPU.
µs
(microsecond) one millionth (10-6) of a second.
ms
(millisecond) one thousandth (10-3) of a second.
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299
Glossary
300
multi-ported
a memory architecture in which the RAM can be
accessed from several busses.
MSB
(Most Significant Bit).
nibble
a unit of data four bits in length. Sometimes spelled
“nybble.”
ns
(nanosecond) one billionth (10-9) of a second.
NVRAM
(Non-Volatile RAM) RAM that retains its data even
without external power.
object code
output from a compiler or assembler that is in machine
language but still must be linked to other object code to
form an executable program.
P1
the mandatory 96-pin VMEbus connector. It carries all
the signals to allow transfers up to A24 and D16. On a
3U board, it is the only connector.
P2
the secondary 96-pin VMEbus connector on 6U of 9U
boards. Thirty two of its pins carry the signals necessary
to allow A32 and D32 transfers. The other 64 pins are
user definable.
page
the smallest unit of memory which is mapped by the
MMU.
P cable
a 68-pin, high density connector SCSI cable with 50 mil
(1.27mm) pin spacing. The P cable, which is defined in
the SCSI-3 specification, comes in two varieties: external
(MiniD68M connector) and internal (high density ribbon
cable).
PCI
(Peripheral Connect Interface) an electrical specification
describing a 32-bit wide multiplexed data/address bus,
which is commonly used to connect peripheral chips to
a processor through a bridge chip.
PMC
(PCI Mezzanine Card) a type add-on mezzanine I/O card
that plugs into a VMEbus Single Board Computer’s PCI
bus.
PowerPC
a microprocessor or architecture based
Motorola/IBM’s 32-bit, RISC design CPU core.
PROM
(Programmable Read-Only Memory) a memory storage
media that can be programmed using electrical pulses.
Once programmed, the PROM is read-only but does not
need power or refresh to maintain the stored data.
RAM
(Random Access Memory) high speed, randomly
accessible memory that can be easily read and written to
by the processor.
requester
a circuit that requests Mastership of a bus.
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on
Glossary
read-modifywrite
see RMW.
RMA
(Return Merchandise Authorization) a number assigned
by Synergy for returning defective products.
RMW
(Read-Modify-Write) a read memory access followed by a
write access performed in such a way that no other
access is allowed to the location between the read and
write.
ROAK
(Release On AcKnowledge) a type of VMEbus Interrupter
module that deasserts its Interrupt Request to the
VMEbus during reception of a valid IACK cycle for its
interrupt level.
ROR
(Release On Request) a requester strategy that once
granted the bus asserts continued Mastership of the bus
even if not currently needed, until another requestor
requests the bus. Opposite of RWD.
RORA
(Release On Register Access) a type of VMEbus
Interrupter module that deasserts its Interrupt Request to
the VMEbus during reception of a VME slave access
cycle to one of its (vendor-specific) control registers.
round robin
a bus sharing method that engages each device or
process in a group at its turn in a fixed cycle.
RS-232
an industry standard for serial communications using
±12V signals at up to 19.2 kb/sec for distances up to 50
ft.
RWD
(Release When Done) a requester strategy that once
granted the bus asserts Mastership only as long as
actually needed. Opposite of ROR.
SBC
(Single Board Computer) a printed circuit board
containing microprocessor and support devices that
provide CPU, ROM, RAM and peripheral interfaces.
SCSI
(Small Computer Systems Interface) an industry standard
parallel interface bus that provides host computers with
device independence of add-on peripherals such as disk
drives, tape drives, CD-ROM drives, etc. The standard
began as an 8-bit parallel data interface with a max.
transfer rate of 5 MB/S (SCSI-1). The next SCSI standard,
SCSI-2 (1994), doubled the 8-bit bus’ transfer rate to 10
MB/S. The SCSI Trade Organization (STA) has since
categorized higher performing, 16-bit SCSI types such as
Wide Ultra SCSI and Wide Ultra2 SCSI. The T10
standards committee expanded the scope of the SCSI
interface with SCSI-3 which is not a standard but a
collection of spec documents describing additional
connector and cabling options, protocol extensions, and
transmission schemes (high performance serial and fiber
data channel).
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301
Glossary
302
SDRAM
(Synchronous Dynamic Random Access Memory) a type
of DRAM that operates in step with the CPU clock
which allows the processor to perform more instructions
over a given time.
SIMD
(Single Instruction Multiple Data) a processor
performance enhancement that speeds multimedia
applications by letting one microinstruction operate at
the same time on multiple data items.
single-ended
a method of signaling in which one wire is used per
signal, referenced to a common Ground signal. This is
the most cost efficient signaling method for short cable
runs. See differential.
Slave
a device connected to a bus that responds to commands
from a Master.
SMI
(System Management Interrupt) for PowerPC, an
asynchronous, maskable exception that is signaled to the
processor by assertion of the SMI\ signal. On Synergy
PowerPC SBCs, this interrupt is asserted via the front
panel SMI switch.
spurious
interrupt
an interrupt whose acknowledge cycle received no
response. Usually caused by late acknowledgement of
periodic interrupters such as timers. But may be caused
by interrupt request that was aborted before being
acknowledged.
SRAM
(Static Random Access Memory) a memory storage
media that needs no refresh cycle. SRAM is faster and of
lower density than DRAM.
supervisor
(supervisor mode) a Motorola processor execution mode
in which the CPU enjoys all its privileges.
SysClk\
(System Clock) a signal driven by the system controller to
all boards of a Multibus or VMEbus system.
SysFail\
(System Failure) a signal that can be driven by any board
of a VMEbus system. Traditionally used to indicate a
failure to one or more boards or devices on a bus.
SysRes\
(System Reset) a signal driven by the system controller to
reset all the cards on the system bus.
system
controller
on VMEbus, a group of circuits on the #1 slot VMEbus
board that prioritize the bus-requests, provide a system
clock, and provide system timeouts.
terminal
a keyboard and display monitor (CRT) attached to a
computer to allow communications between the user
and a computer.
triple-access
(triple-access DRAM) see multi-ported.
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Glossary
UART
(Universal Asynchronous Receiver/Transmitter) a device
able to translate between parallel and asynchronous
serial communications signals for transmission and
reception between a parallel processor bus and a serial
communications port.
VMEbus
(Versa Module Eurocard bus) a microcomputer
architecture whose physical and electrical characteristics
are defined in the IEC 821 and IEEE 1014-1987
specifications. The VMEbus supports separate address
and data lines of up to 32 bits each. This bus uses a
backplane in which VMEbus modules are interconnected
using DIN-41612 connectors.
watchdog
an on-board timer that can automatically reset the board
if not accessed on a regular basis. Used to reset the
board in response to a software loop and/or malfunction
or a CPU halt.
window size
the range of contiguous addresses that the board
responds to is called the window. The number of
addresses in the window is called the window size. The
board will respond to addresses from base to
base+window size.
word
typically, a unit of data 16 bits in length. In the PowerPC
environment, however, a word is 32 bits while a halfword is 16 bits and a double-word is 64 bits.
WWV
call letters for the National Bureau of Standards radio
station in Ft. Collins, Colorado. WWV broadcasts
technical services including timing signals, audio
frequencies, and radio-propagation disturbance warnings
at the 2.5, 5, 10, 15, and 25 MHz carrier bands. Canada
provides similar services on CHU.
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303
Glossary
304
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Index
Index
µs
BLT
defined, 299
defined, 296
improving performance, 195
100BASE-T
board information registers, 114
defined, 295
10BASE-T
board layout
defined, 295
21554 PCI-PCI bridge
configuration, 221
general description, 217
register overview, 219
27C010, 29, 145
PEX3, 271
RGS3, 266
VSS4, 265
Boot Flash, 145, 148
additional write protection, 150
write protect, 149
boot ROM enable jumper, 25, 147
27C020, 29, 145
boot selection, 146, 147
27C040, 29, 145
bridge
28F020, 29, 145
defined, 296
29C040, 29, 145
byte swapping, 65
address map (PEX3), 280
cache line
address map, VSS4, 109
defined, 296
cache memory
AM code bits
defined, 296
defined, 295
capacitor backup option, specifications, 264
base address
category 3
defined, 296
battery, NVRAM/clock calendar, 144
defined, 296
category 5
BCD
defined, 296
defined, 296
bit numbering conventions, 10
CHRP address map, 105
block diagram
clock/calendar
21554 microarchitecture, 220
PCI-PCI bridge interface, 218
PEX3 optional expansion board, 270
PowerPC with AltiVec (G4), 91
reset sources, 160
Universe II PCI-VME bridge, 186
VMEbus interface, 59
VSS4, 6
calibrating, 140
defined, 296
collision
defined, 296
configuration
default hardware configuration, 23
connectors
CRJ4 serial adapter pinout, 261
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305
Index
P0
pinout, 247
P1, 13
P1 (motherboard)
defined, 300
P1, VME (PEX3)
pinout, 288
P11, P21, P31 (PEX3)
pinout, 290
P11–P15
pinout, 237
P12, P22, P32 (PEX3)
pinout, 291
P13, P23, P33 (PEX3)
pinout, 292
P14 (PEX3)
pinout, 293
P2, 14
P2 (motherboard)
defined, 300
P2, VME (PEX3)
pinout, 289
P24, P34 (PEX3)
pinout, 294
P240
pinout, 256
P264
pinout, 254
P346
pinout, 258
PM1
pinout, 251
PM2
pinout, 252
control/mode registers, 120
CPU
defined, 296
CRT
defined, 297
customer service, 230, 267
data broadcasting
defined, 297
dimensions (board), 263
DMA
defined, 297
DRAM
defined, 297
RGS3 installation, 33
DTE
defined, 297
dual-port
defined, 297
ECO
defined, 297
empty slot placement, managing, 51
Endian
defined, 298
endian issues, 65
EPROM
defined, 298
EPROM boot enable jumper, 146
EPROM type configuration, 31, 147
Ethernet
defined, 298
Ethernet interface
CSMA/CD, 80
data transmission, 79
Ethernet ID, 80
Ethernet network connections, 78
Interchange signals, 81
LED indicators, 82
Fast Ethernet connector (P240), 255
FIFO
defined, 297
defined, 298
DB-25
Flash
defined, 297
additional info, 151, 156
block organization, boot Flash, 149
block organization, User Flash, 154
boot ROM, 145
booting from, 146
User Flash memory, 153
write protect jumper (PEX3), 273
DB-9
defined, 297
DCE
defined, 297
306
differential
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Index
write protection, 25, 26, 149, 156
Flash memory
jumpers
J02L (configuration), 23
J902 (EPROM), 32
JG02 (PEX3 Flash Write Protect), 273
jumper functional summary, 25, 26
defined, 298
floating-point
defined, 298
L1 cache
FPU
defined, 299
defined, 298
L2 backside cache controller, 127
front panel
PEX3 layout, 272
front panel layout, 17
GPS receiver
L2 cache
defined, 299
lamp test, 22
LED
defined, 298
0–7 (application), 21
defined, 299
VSS4 status, 20
hardware configuration. (see configuration)
humidity specification, 264
M48T201Y, 138
I/O
mailbox, 129
defined, 299
defined, 299
IAck
main board (VSS4)
defined, 298
revisions, 267
IBM
master
defined, 298
defined, 299
ID switch (software readable), 18
memory module
installation
installing the RGS3 memory module, 33
minimum system requirements, 13
P0 overlay, 45
PMC, 41
slot recommendations, 51
revisions, 268
memory protection
defined, 299
MMU
defined, 299
installation notes
about, 9
Hybricon VME64x backplanes, 52
slot installation recommendations, 51
monitor PROM, installing, 29
MPC106 registers, 96
interrupt controller, 167
MPC106, general description, 93
interrupt handler
MPIC, 167
defined, 299
MPIC base address, 169
interrupter
ms
defined, 299
defined, 299
ISP
MSB
defined, 299
defined, 300
JEDEC
multi-port
defined, 299
defined, 300
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307
Index
ns
defined, 300
NVRAM
defined, 300
NVRAM space allocation, 144
object code
defined, 300
onboard registers, 113
physical address (Ethernet), 80
operating environment, 264
physical configuration, 5
operating notes
PMC
about, 9
P cable
defined, 300
P0 overlay. See P0•PCI™ interface
P0•PCI™ interface, 45, 217
overlay board, 45, 217
P0 overlay board models, 46
P0 overlay, typical component assembly, 49
software support, 223
P1, P2, etc.,. (see connectors)
card installation, 41
connectors
pinout, 237
defined, 300
overview, 62
PMC stacking details, 278
power
consumption, 15
power supply, 15
power monitor, 161
PowerPC
page
defined, 300
PCI
bus overview, 61
defined, 300
device base address, setting the, 101
PCI configuration and address
VSS4, 108
PCI Discovery. Also PCI Enumeration, PCI
Auto-Configuration
reset, 160
PCI configuration and address
PEX3, 281
PCI interface (PEX3)
configuration, 281
PCI 9080 basic setup, 282
PCI interrupts, PEX3 (PMC), 280
PEX3
about, 4, 269
address map, 280
block diagram, 270
board layout, 271
features, 269
308
Flash write protect jumper (JG02), 273
front panel layout, 272
installing PMCs, 274
onboard capability registers, 283
PCI configuration, 281
PCI Type 0 configuration, 281
PEX3 expansion board, 40
PMC PCI interrupts, 280
registers overview, 283
using memory, 286
architecture, 85
architecture overview, 85
defined, 300
G4 processor, 90
instruction set overview, 89
register set, 88
processor init register, MPIC, 172
programming notes
about, 9
MPC106, 101
SYM53C885, 213
Universe II, 199
PROM. (see also—monitor
PROM(EPROM))
defined, 300
RAM
defined, 300
registers
21554, 219
board information, 114
control/mode, 120
PCI configuration (PEX3), 281
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Index
PEX3, 283
board type (capability), 284
DRAM configuration (capability), 285
Flash configuration (capability), 285
revision & ECO level (capability), 284
PowerPC register set, 88
status, 118
VSS4 onboard, 113
repair, 230
requester
termination disable jumper, 25
SCSI/Ethernet controller interface, 201
SDRAM
defined, 302
serial interface, 131
connector, 136, 257
CRJ4 serial port adapter, 136, 259
ST16C654 registers, 131
SIMD
defined, 300
defined, 302
RESET, 19, 159
hard reset sources, 160
power monitor reset, 161
soft reset, 163, 172
software reset, 163
toggle (front panel), 19, 161
VME SysReset, 161
single-ended
defined, 302
slave
defined, 302
slave image, Universe II, 193, 194
rework/upgrades, 267
slot location, 51
RMA, 230
slot number, manual settings, 26
defined, 301
SMI, 19
RMW
defined, 302
defined, 301
sockets
ROAK
UE10, 145
defined, 301
soft reset, 163
ROR
software-readable switch. (see—switches: ID
switch)
defined, 301
round robin
specifications
defined, 301
dimensions, 263
environmental, 264
power requirements, 263
weight, 263
RS-232
defined, 301
RWD
spurious interrupt
defined, 301
defined, 302
SBC
SRAM
defined, 301
defined, 302
SCSI
SRAM, 128K x 8, 143
defined, 301
SCSI interface
ST16C654, 131
Bus communication control, 74
Bus terminations, 74
Data transfer options, 75
Electrical connections, 72
History, 67
Overview, 67
Physical topology, 73
registers, 131
start-up vectors, 147
status registers, 118
supervisor
defined, 302
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309
Index
switches
VMEbus
ID switch (software-readable), 18
RESET toggle, 19
SYM53C885, 203
general description, 203
registers, 205
SysClk
defined, 302
SysFail
defined, 302
SysRes
voltages, 15, 263
defined, 302
VSS4
system controller
defined, 302
system requirements, 13
temperature requirements, 264
terminal
defined, 302
Type 0 PCI configuration, 108, 222
Type 1 PCI configuration, 222
U2SPEC register, Universe II
adjustable VME timing parameters, 196
register bit assignments, 197
UART
block diagram, 6
dimensions, 263
minimum system requirements, 13
operating environment, 264
power requirements, 263
repair, 230
revision levels, 267
rework/upgrades, 267
VMEbus compliance, 263
voltages, 15
warranty, 227, 230
weight, 263
warranty, 227, 230
watchdog
defined, 303
defined, 303
watchdog timer, 162
Universe II
base address, 189
registers
access, 189
map, 190
overview, 189
slave image programming note, 199
U2SPEC, 195
user configuration jumpers, J02L, 24
weight, 263
window size
defined, 303
word
defined, 303
Write posting to ROM Space, 102
WWV
VME 6U, 263
310
compliance, 263
interrupt handler, 263
interrupter, 263
master interface, 263
slave interface, 263
connectors (on-board)
pinout, 233
defined, 303
overview, 57
SysReset, 161
VME64, 57
VSS4 implementation, 58
defined, 303
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