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U A H
CPE/EE 421
Microcomputers
Instructor: Dr Aleksandar Milenkovic
Lecture Note
S17
1
U A H
CPE/EE 421/521 Microcomputers
Course Administration
Alex Milenkovich
¾ Instructor:
Aleksandar Milenkovic
milenka@ece.uah.edu
www.ece.uah.edu/~milenka
EB 217-L
Mon. 5:30 PM – 6:30 PM,
Wen. 12:30 – 13:30 PM
¾ URL:
http://www.ece.uah.edu/~milenka/cpe421-05F
¾ TA:
Joel Wilder
¾ Labs:
Lab #4 is on. Hw #2 is posted.
¾ Test I:
Graded. Solutions are in scr/.
¾ Text:
Microprocessor Systems Design:
68000 Hardware, Software, and Interfacing
¾ Review:
M68K (Chapter 1; Chapter 2; Chapter 3),
MSP430 (Introduction, Arch., Basic Clock System,
WDT, Low Power Modes, Digital I/O)
¾ Today:
CPE/EE
421/521 I/O,
Microcomputers
MSP430
Digital
Timers, USART
2
1
U A H
Review: Digital I/O
all MSP430
Port1
Port2
Port3
…
Port6
Function Select Register PxSEL
yes
yes
Interrupt Edge Select Register PxIES
yes
no
Interrupt Enable Register PxIE
yes
no
Interrupt Flag Register PxIFG
yes
no
Direction Register PxDIR
yes
yes
Output Register PxOUT
yes
yes
yes
yes
Input Register PxIN
P1.
P2.
P3.
7
6
5
4
3
2
1
0
P4.
P5.
Chapter 9, User’s Manual
pages 9-1 to 9-7
CPE/EE 421/521 Microcomputers
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U A H
P6.
Digital I/O Introduction
¾ MSP430 family – up to 6 digital I/O ports implemented, P1-P6
¾ MSP430F14x – all 6 ports implemented
Ports P1 and P2 have interrupt capability.
Each interrupt for the P1 and P2 I/O lines can be individually enabled and
configured to provide an interrupt on a rising edge or falling edge of an input
signal.
The digital I/O features include:
¾ Independently programmable individual I/Os
¾ Any combination of input or output
¾ Individually configurable P1 and P2 interrupts
¾ Independent input and output data registers
The digital I/O is configured with user software
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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2
U A H
Digital I/O Registers Operation
Input Register PnIN
Each bit in each PnIN register reflects the value of the input signal
at the corresponding I/O pin when the pin is configured as I/O
function.
Do not write to PxIN. It will result
Bit = 0: The input is low
in increased current consumption
Bit = 1: The input is high
Output Registers PnOUT
Each bit in each PnOUT register is the value to be output on the
corresponding I/O pin when the pin is configured as I/O function
and output direction.
Bit = 0: The output is low
Bit = 1: The output is high
5
U A H
CPE/EE 421/521 Microcomputers
Digital I/O Operation
Direction Registers PnDIR
Bit = 0: The port pin is switched to input direction
Bit = 1: The port pin is switched to output direction
Function Select Registers PnSEL
Port pins are often multiplexed with other peripheral module
functions.
Bit = 0: I/O Function is selected for the pin
Bit = 1: Peripheral module function is selected for the pin
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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U A H
Digital I/O Operation
Interrupt Flag Registers P1IFG, P2IFG
(only for P1 and P2)
Bit = 0: No interrupt is pending
Bit = 1: An interrupt is pending
(Only transitions, not static levels, cause interrupts)
Interrupt Edge Select Registers P1IES, P2IES
(only for P1 and P2)
Each PnIES bit selects the interrupt edge for the corresponding I/O pin.
Bit = 0: The PnIFGx flag is set with a low-to-high transition
Bit = 1: The PnIFGx flag is set with a high-to-low transition
7
Timer_A MSP430x1xx
¾ Purpose
™ The Timer A and B systems on the MSP are a versatile means to measure
time intervals. The timers can measure the timing on incoming signals or
control the timing on outgoing signals. This function is necessary to meet
arbitrary timing requirements from outside components, and the ability is useful
in phase locking scenarios
U A H
CPE/EE 421/521 Microcomputers
¾ Features
™ 16-bit counter with 4 operating modes
™ Selectable and configurable clock sources
(internal - ACLK, SMCLK; external – INCLK, TBCLK)
™ Three (or five) independently configurable capture/compare registers
with configurable inputs
™ Three (or five) individually configurable output modules
with 8 output modes
™ Multiple, simultaneous, timings; multiple capture/compares;
multiple output waveforms such as PWM signals; and any
combination of these.
™ Interrupt capabilities
• each capture/compare block individually configurable
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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4
U A H
Timer_A3
9
U A H
CPE/EE 421/521 Microcomputers
Timer_A5 - MSP430x1xx Block Diagram
Page 11-3, User’s Manual
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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5
U A H
Capture and Compare Registers
¾ What is a capture?
™ A record of the timer count when a specific event occurs. The
capture modules of the timers are tied to external pins of the MSP.
When the control registers of timer A and the specific capture
compare module have been properly configured, then the capture
will record the count in the timer when the pin in question makes a
specific transition (either from low to high or any transition). This
capturing event can be used to trigger an interrupt so that the data
can be processed before the next event. In combination with the
rollover interrupt on Capture module 0, you can measure intervals
longer than 1 cycle.
¾ Compare
™ The inverse of a capture. While capture mode is used to measure
the time of an incoming pulse width modulation signal (a signal
whose information is encoded by the time variation between signal
edges), compare mode is used to generate a pulse width
modulation (PWM) signal. When the timer reaches the value in a
compare register, the module will give an interrupt and change the
state of an output according to the other mode bits. By updating
the compare register numbers, you change the timing of the signal
level transitions.
11
U A H
CPE/EE 421/521 Microcomputers
Timer_A Counting Modes
UP/DOWN Mode
Stop/Halt Mode
Timer counts between 0 and CCR0 and 0
Timer is halted with the next +CLK
0FFFFh
UP/DOWN Mode
CCR0
0h
UP Mode
Continuous Mode
Timer counts between 0 and CCR0
Timer continuously counts up
0FFFFh
Continuous Mode
0FFFFh
CCR0
0h
0h
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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6
U A H
Timer_A 16-bit Counter
15
0
Input
Select
unused
160h
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
Input
Divider
rw(0)
rw(0)
rw(0)
ID1
ID0
0
0
1
1
0
1
0
1
SSEL1 SSEL0
0
0
0
1
1
0
1
1
Page 11-12, User’s Manual
Mode
Control
unTAIE TAIFG
used CLR
rw(0)
rw(0)
MC1
MC0
0
0
1
1
rw(0)
0
1
0
1
(w)(0)
rw(0)
rw(0)
Stop Mode
Up Mode
Continuous Mode
Up/Down Mode
1/1, Pass
1/2
1/4
1/8
TACLK
ACLK
MCLK
INCLK
13
CPE/EE 421/521 Microcomputers
Timer_A Capture Compare Blocks
Overflow x
COVx
Logic
Capture Path
Timer Bus
Data Bus
CMPx
CCISx1 CCISx0
0
CCIxA
1
CCIxB
2
GND
3
VCC
CCMx1
0
0
1
1
15
1
Capture
Mode
Timer
Clock
CCMx0
0 Disabled
1 Pos. Edge
0 Neg. Edge
1 Both Edges
0
Capture/Compare Register
CCRx
Capture
0
Synchronize
Capture
U A H
TACTL
SCSx
15
0
Comparator
to Port0x
EQUx 0
CAPx
1
Compare Path
EN
A
CCIx
CCRx
0172h
to
017Eh
15
2
CCTLx
162h
to
16Eh
2
rw(0)
CAPTURE
MODE
rw(0)
rw(0)
rw(0)
rw(0)
INPUT
SELECT
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
SCS SCCI
unCAP
used
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
OUTMODx
rw(0)
rw(0)
CPE/EE 421/521 Microcomputers
Alex Milenkovich
SCCIx
0
15
rw(0)
15
Set_CCIFGx
Y
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
0
rw(0)
0
CCIE CCI
OUT COV CCIFG
rw(0)
rw(0)
r
rw(0)
rw(0)
14
7
U A H
Timer_A Output Units
Timer Clock
TAx
EQUx
OUTx (CCTLx.2)
Logic
Output
EQU0
D
Set
Output Signal Outx
Q
To Output Logic TAx
Timer Clock
Reset
POR
Output Mode 0
OUTx
OMx2 OMx1 OMx0
OMx2 OMx1 OMx0 Function
Operational Conditions
0
0
0
Output Mode
Outx signal is set according to Outx bit
0
0
1
Set
EQUx sets Outx signal clock synchronous with timer clock
0
1
0
PWM Toggle/Reset
EQUx toggles Outx signal, reset with EQU0, clock sync. with timer clock
0
1
1
PWM Set/Reset
EQUx sets Outx signal, reset with EQU0, clock synchronous with timer clock
1
0
0
Toggle
EQUx toggles Outx signal, clock synchronous with timer clock
1
0
1
Reset
EQUx resets Outx signal clock synchronous with timer clock
1
1
0
PWM Toggle/Reset
EQUx toggles Outx signal, set with EQU0, clock synchronous with timer clock
1
1
1
PWM Set/Reset
EQUx resets Outx signal, set with EQU0, clock synchronous with timer clock
15
U A H
CPE/EE 421/521 Microcomputers
Timer_A Continuous-Mode Example
0FFFh
0h
Px.x
TA0 Input
CCR0:
Capture Mode: Positive Edge
Px.y
TA1 Input
CCR1:
Capture Mode: Both Edges
Px.z
TA2 Input
CCR2:
Capture Mode: Negative Edge
CCR0
CCR0
CCR1 CCR1
CCR1
CCR1
CCR1 CCR1
Interrupts can be generated
CCR2
Example shows three independent HW event captures.
CCRx “stamps” time of event - Continuous-Mode is ideal.
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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U A H
Timer_A PWM Up-Mode Example
0FFFFh
CCR0
CCR1
CCR2
0h
TA1 Output
CCR1: PWM Set/Reset
Px.x
CCR2: PWM Reset/Set
TA2 Output
Px.y
CCR0: PWM Toggle
TA0 Output
Px.z
Auto
Re-load
EQU2
EQU0
EQU2
EQU1
EQU0
EQU1
EQU2
EQU0
Interrupts can be generated
Output Mode 4: PWM Toggle
Example shows three different asymmetric
PWM-Timings generated with the Up-Mode
17
U A H
CPE/EE 421/521 Microcomputers
Timer_A PWM Up/Down Mode Example
0FFFFh
thlfper
CCR0
CCR2
CCR1
CCR3
0h
TA1 Output
0 Degrees
(0.5xVmotor)
Px.x
tpw1
TA2 Output
+120 Degrees
tpw2
(0.93xVmotor)
Px.y
tpw3
-120 Degrees
TA0 Output
Px.z
(0.07xVmotor)
TIMOV
EQU0
TIMOV
EQU0
TIMOV
Interrupts can be generated
Example shows Symmetric PWM Generation Digital Motor Control
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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9
U A H
C Examples
//***************************************************************
#include <msp430x14x.h>
//
MSP-FET430P140 Demo - Timer_A Toggle P1.0,
//
CCR0 Contmode ISR, DCO SMCLK
//
Description; Toggle P1.0 using software and TA_0 ISR. Toggle rate is
void main(void)
//
set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
{
//
Durring the TA_0 ISR P0.1 is toggled and 50000 clock cycles are
added to
//
CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally
off and
//
used only durring TA_ISR.
//
ACLK = n/a, MCLK = SMCLK = TACLK = DCO~ 800k
WDTCTL = WDTPW + WDTHOLD;
// Stop WDT
P1DIR |= 0x01;
// P1.0 output
CCTL0 = CCIE;
// CCR0 interrupt enabled
CCR0 = 50000;
TACTL = TASSEL_2 + MC_2; // SMCLK, contmode
//
//
//
//
MSP430F149
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
---------------
//
/|\|
//
| |
//
--|RST
//
|
//
|
}
XIN||
XOUT|-
// Timer A0 interrupt service routine
|
interrupt[TIMERA0_VECTOR] void TimerA(void)
P1.0|-->LED
{
//
P1OUT ^= 0x01; // Toggle P1.0
//
M. Buccini
//
Texas Instruments, Inc
//
September 2003
//
Built with IAR Embedded Workbench Version: 1.26B
//
December 2003
//
Updated for IAR Embedded Workbench Version: 2.21B
CCR0 += 50000; // Add Offset to CCR0
}
//**********************************************************************
CPE/EE 421/521 Microcomputers
19
Serial Communication
Alex Milenkovich
10
U A H
Serial I/O Interface
Functional Units
Translates the TTLlevel signals processed
by the ACIA into a form
suitable for the
transmission path
CPE/EE 421/521 Microcomputers
21
U A H
Translates data between
the internal computer
form and the form in
which it is transmitted
over the data link
Asynchronous Serial Interface
¾ Asynchronous
™ Transmitted and received data are not synchronized over any
extended period
™ No synchronization between receiver and transmitter clocks
¾ Serial
™ Usually character oriented
™ Data stream divided into individual bits at the transmitter side
™ Individual bits are grouped into characters at the receiving side
¾ Information is usually transmitted as ASCII-encoded
characters
™ 7 or 8 bits of information plus control bits
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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U A H
Asynchronous Serial Interface, cont’d
¾ MARK level (or OFF, or 1-state, or 1-level)
™ This is also the idle state (before the transfer begins)
¾ SPACE level (or ON, or 0-state, or 0-level)
¾ One character:
Start bit: space level
Data bits
Optional parity bit
Optional stop bit
CPE/EE 421/521 Microcomputers
23
U A H
™
™
™
™
Asynchronous Serial Interface, cont’d
¾ 12 possible basic formats:
™ 7 or 8 bits of data
™ Odd, even, or no parity
™ 1 or 2 stop bits
™ Others exist also: no stop bits, 4/5/6 data bits, 1.5 stop bits,
etc.
Least significant bit
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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12
U A H
Receiver Clock Timing
¾ For N=9 bits (7 data + parity + stop) maximum tolerable error is 5%
(assume that the receiver clock is slow -- [T + δt] instead of T)
T/2 > (2N+1)δt/2
δt/2 < 1/(2N+1)
δt/T < 100/(2N+1) as a percentage
25
U A H
CPE/EE 421/521 Microcomputers
RS-232 Interface Standard
¾ Bi-polar:
™ +3 to +12V (ON, 0-state, or SPACE condition)
™ -3 to –12V (OFF, 1-state, or MARK condition)
¾ Modern computers accept 0V as MARK
¾ “Dead area” between –3V and 3V is designed to absorb line
noise
¾ Originally developed as a standard for communication
between computer equipment and modems
¾ From the point of view of this standard:
™ MODEM: data communications equipment (DCE)
™ Computer equipment: data terminal equipment (DTE)
¾ Therefore, RS-232C was intended for DTE-DCE links
(not for DTE-DTE links, as it is frequently used now)
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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13
¾ Each manufacturer may choose to implement only a subset
of functions defined by this standard
U A H
RS-232 Interface Standard
¾ Two widely used connectors: DB-9 and DB-25
¾ Three types of link
™ Simplex
™ Half-duplex
™ Full-duplex
¾ Basic control signals
™ RTS (Request to send):
DTE indicates to the DCE that it wants to send data
™ CTS (Clear to send):
DCE indicates that it is ready to receive data
™ DSR (Data set ready):
indication from the DCE (i.e., the modem) that it is on
™ DTR (Data terminal ready):
indication from the DTE that it is on
27
U A H
CPE/EE 421/521 Microcomputers
RS-232 Interface Standard, another example
™ DTR (Data terminal ready): indication from the DTE that it is on
CPE/EE 421/521 Microcomputers
Alex Milenkovich
28
14
¾ DB-25 connector is described in the book; let’s take a look at DB-9
U A H
29
CPE/EE 421/521 Microcomputers
RS-232 Interface Standard
Example: 9 to 25 pin cable layout for asynchronous data
Signal
9-pin
DTE
25-pin
DCE
Carrier Detect
CD
1
8
from Modem
Receive Data
RD
2
3
from Modem
Transmit Data
TD
3
2
from Terminal/Computer
DTR
4
20
from Terminal/Computer
SG
5
7
from Modem
Data Set Ready
DSR
6
6
from Modem
Request to Send
RTS
7
4
from Terminal/Computer
Clear to Send
CTS
8
5
from Modem
Ring Indicator
RI
9
22
from Modem
Description
Data Terminal Ready
Signal Ground
CPE/EE 421/521 Microcomputers
Alex Milenkovich
U A H
RS-232 Interface Standard
Source DTE or DEC
30
15
U A H
The Minimal RS-232 Function
DTE to DCE in simplex mode
DCE
2
2
7
7
DTE to DTE in simplex mode
DTE
DTE
2
3
7
7
31
CPE/EE 421/521 Microcomputers
U A H
DTE
The Minimal RS-232 Function
DTE to DCE in full-duplex mode
DTE
2
3
3
7
7
DTE to DTE in full-duplex mode
DTE
DTE
2
3
3
2
7
7
CPE/EE 421/521 Microcomputers
Alex Milenkovich
DCE
2
32
16
U A H
The Minimal RS-232 Function
DTE to DCE with remote control
TxD
RxD
RTS
CTS
2
3
7
4
5
DTE to DTE with remote control
DTE
TxD
RxD
RTS
CTS
DCE
2
3
7
4
5
CTS
RTS
DTE
2
3
7
4
5
2
3
7
4
5
RxD
TxD
CPE/EE 421/521 Microcomputers
TxD
RxD
RTS
CTS
33
U A H
DTE
Handshaking Between RTS and CTS
CPE/EE 421/521 Microcomputers
Alex Milenkovich
34
17
U A H
Null Modem
¾ Null-modem simulates a DTE-DCE-DCE-DTE circuit
35
USART Peripheral Interface
¾ Universal Synchronous/Asynchronous
Receive/Transmit (USART) peripheral interface
supports two modes
U A H
CPE/EE 421/521 Microcomputers
™ Asynchronous UART mode (User manual, Ch. 13)
™ Synchronous Peripheral Interface, SPI mode
(User manual, Ch. 14)
¾ UART mode:
™ Transmit/receive characters at a bit rate
asynchronous to another device
™ Connects to an external system via two external pins
URXD and UTXD (P3.4, P3.5)
™ Timing is based on selected baud rate
(both transmit and receive use the same baud rate)
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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18
U A H
UART Features
¾ 7- or 8-bit data width; odd, even, or non-parity
¾ Independent transmit and receive shift reg.
¾ Separate transmit and receive buffer registers
¾ LSB-first data transmit and receive
¾ Built-in idle-line and address-bit communication protocols
for multiprocessor systems
¾ Receiver start-edge detection for auto-wake up from
LPMx modes
¾ Programmable baud rate with modulation for fractional
baud rate support
¾ Status flags for error detection
¾ Independent interrupt capability for transmit and receive
37
U A H
CPE/EE 421/521 Microcomputers
USART Block Diagram: UART mode
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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19
¾ Initialization Sequence
U A H
Initialization Sequence & Character Format
™ Set SWRST bit
™ Initialize all USART registers with SWRST = 1
™ Enable USART module via the MEx SFRs
(URXEx and/or UTXEx)
™ Clear SWRST via software
(releases the USART for operation)
™ Optional: enable interrupts vie IEx SFRs
¾ Character format
CPE/EE 421/521 Microcomputers
Alex Milenkovich
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