advertisement
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
PSoC 64 "Secure Boot" MCU with
Bluetooth LE
General Description
PSoC
®
6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The PSoC 64 product line, based on the PSoC 6 MCU platform, features out-of-box security functionality, providing an isolated root-of-trust with true attestation and provisioning services. In addition, it delivers a pre-configured secured execution environment which supports system software of various IoT platforms; and enables TLS authentication, secured storage, and secured firmware management. PSoC 64 also includes a rich execution environment for application development, with RTOS support that communicates with the secured execution environment.
The PSoC 64 CYB06447BZI-BLDx product line provides wireless connectivity with Bluetooth LE 5.0 compliance.
Features
32-bit Dual CPU Subsystem
Note: In PSoC 64 the Cortex M0+ is reserved for system functions, and is not available for applications.
■ 150-MHz Arm
®
Cortex
®
-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU)
■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU
■ User-selectable core logic operation at either 1.1 V or 0.9 V
■
■
■
❐
❐
Active CPU current slope with 1.1-V core operation
Cortex-M4: 40 µA/MHz
Cortex-M0+: 20 µA/MHz
❐
❐
Active CPU current slope with 0.9-V core operation
Cortex-M4: 22 µA/MHz
Cortex-M0+: 15 µA/MHz
Two DMA controllers with 16 channels each
Memory Subsystem
■ 832-KB application flash, 32-KB auxiliary flash (AUXflash), and
32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU.
■ 176-KB SRAM with power and data retention control
■ One-time-programmable (OTP) 1-Kb eFuse array
Hardware-Based Root-of-Trust (RoT)
■ RoT based on immutable boot-up code, flash content hash, and Cypress public key that ensures firmware integrity prior to provisioning
■ Supports trusted RoT handover to maintain chain of trust and establish OEM trust anchor for secured boot
■ Device generates a unique device ID and a device secret key during the provisioning process, which can be used for attestation and signing
Immutable “Secure Boot” Support
■ Flexible chain of trust can use different signatures for different images
■
ECC-based image signature validation
Cypress Bootloader
■ Open Source MCUBoot
PSoC 64 family
based bootloader optimized for the
■ Pre-built bootloader binary capable of validating, launching and updating signed user application images
■ Tightly integrated with provisioned debug and boot policies to inherit and implement security policies
Bluetooth Low Energy Subsystem
■ 2.4-GHz RF transceiver with 50 antenna drive
■ Digital PHY
■ Link Layer engine supporting master and slave modes
■ Programmable TX power: up to 4 dBm
■ RX sensitivity: –95 dBm
■ RSSI: 4-dB resolution
■ 5.7-mA Tx (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V supply and internal SIMO Buck converter
■
■
Link Layer engine supports four connections simultaneously
Supports 2 Mbps data rate
Low-Power 1.7-V to 3.6-V Operation
■
■
■
■
Six power modes for fine-grained power management
Deep Sleep mode current of 7 µA with 64-KB SRAM retention
On-chip Single-In Multiple Out (SIMO) DC-DC buck converter,
<1 µA quiescent current
Backup domain with 64 bytes of memory and real-time clock
Flexible Clocking Options
■ 8-MHz Internal Main Oscillator (IMO) with ±2% accuracy
■ Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)
■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
■ Phase-locked loop (PLL) for multiplying clock frequencies
■ Frequency-locked loop (FLL) for multiplying IMO frequency
■ Integer and fractional peripheral clock dividers
Note
1. For details, refer to https://mcuboot.com/ .
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-28630 Rev. *I
• San Jose
,
CA 95134-1709 • 408-943-2600
Revised October 26, 2022
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Quad SPI (QSPI)/Serial Memory Interface (SMIF)
■
Execute-In-Place (XIP) from external quad SPI Flash
■
■
On-the-fly encryption and decryption
4-KB cache for greater XIP performance with lower power
■ Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps
Segment LCD Drive
■
Supports up to 83 segments and up to 8 commons
Serial Communication
■
■
Nine run-time configurable serial communication blocks
(SCBs)
❐
❐
Eight SCBs: configurable as SPI, I
2
C, or UART
One Deep Sleep SCB: configurable as SPI or I
2
C
USB full-speed device interface
Audio Subsystem
■ Two pulse density modulation (PDM) channels and one I channel with time division multiplexed ( TDM) mode
2
S
Timing and Pulse-Width Modulation
■
Thirty-two timer/counter/pulse-width modulators (TCPWM)
■
Center-aligned, edge, and pseudo-random modes
■
Comparator-based triggering of Kill signals
■
■
Programmable Analog
■
■
■
12-bit 1-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging
Two low-power comparators available in Deep Sleep and
Hibernate modes
Built-in temperature sensor connected to ADC
One 12-bit voltage-mode digital-to-analog converter ( DAC) with
< 2-µs settling time
Two opamps with low-power operation modes
Up to 84 Programmable GPIOs
■
■
■
Two Smart I/O™ ports (16 I/Os) enable Boolean operations on
GPIO pins; available during system Deep Sleep
Programmable drive modes, strengths, and slew rates
Six overvoltage-tolerant (OVT) pins
Capacitive Sensing
■
(
Cypress CapSense
®
provides best-in-class signal-to-noise ratio
SNR), liquid tolerance, and proximity sensing
■
Enables dynamic usage of both self and mutual sensing
■ Automatic hardware tuning (SmartSense™)
Cryptography Accelerator
■
Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions
■
True random number generation (TRNG) function
Programmable Digital
■
■
■
Twelve programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs)
Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog-programmable blocks
Cypress-provided peripheral component library using UDBs to implement functions such as communication peripherals (for example, LIN, UART, SPI, I
2
C, S/PDIF and other protocols),
Waveform Generators, Pseudo-Random Sequence (PRS) generation, and many other functions.
Profiler
■
Eight counters provide event or duration monitoring of on-chip resources
Packages
■ 124-BGA and 116-BGA
Device Identification and Revisions
■
Product line ID (12-bit): 0x100
■
Major/Minor Die Revision ID: 2/4
■
Firmware Revisions: Rom Boot: 4.1, Flash Boot: 4.0.2.1842
section)
This product line has a JTAG ID which is available through the
SWJ interface. It is a 32-bit ID, where:
■ The most significant digit is the device revision, based on the
Major Die Revision
■ The next four digits correspond to the part number, for example
"E4B0" as a hexadecimal number
■ The three least significant digits are the manufacturer ID, in this case "069" as a hexadecimal number
The Silicon ID system call can be used by firmware to get Silicon
ID and ROM Boot data. For more information, see the technical reference manual (TRM) .
The Flash Boot version can be read directly from a designated address 0x1600 2004. For more information, see the technical reference manual (TRM) .
Document Number: 002-28630 Rev. *I Page 2 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Contents
Development Ecosystem ................................................. 4
PSoC 6 MCU Resources............................................. 4
ModusToolbox Software.............................................. 5
Blocks and Functionality ................................................. 6
Functional Description..................................................... 8
CPU and Memory Subsystem ..................................... 8
System Resources .................................................... 11
Bluetooth LE Radio and Subsystem.......................... 14
Programmable Analog Subsystem............................ 15
Programmable Digital................................................ 17
Fixed-Function Digital................................................ 17
GPIO ......................................................................... 18
Special-Function Peripherals .................................... 19
PSoC 64 Security ...................................................... 22
Pinouts ............................................................................ 25
Power Supply Considerations....................................... 37
Electrical Specifications ................................................ 40
Absolute Maximum Ratings....................................... 40
Device-Level Specifications ...................................... 40
Analog Peripherals .................................................... 48
Digital Peripherals ..................................................... 57
Memory ..................................................................... 59
System Resources .................................................... 60
Bluetooth LE.............................................................. 68
Ordering Information...................................................... 73
PSoC 6 MPN Decoder .............................................. 74
Packaging........................................................................ 75
Acronyms........................................................................ 78
Document Conventions ................................................. 80
Unit of Measure ......................................................... 80
Revision History ............................................................. 81
Sales, Solutions, and Legal Information ...................... 83
Worldwide Sales and Design Support....................... 83
Products .................................................................... 83
PSoC® Solutions ...................................................... 83
Cypress Developer Community................................. 83
Technical Support ..................................................... 83
Document Number: 002-28630 Rev. *I Page 3 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Development Ecosystem
PSoC 6 MCU Resources
Cypress provides a wealth of data at www.cypress.com
to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 6 MCU:
■
■
■
■
■
Overview : PSoC Portfolio , PSoC Roadmap
Product Selectors : PSoC 6 MCU
❐
❐
❐
❐
❐
❐
Application Notes cover a broad range of topics, from basic to advanced level, and include the following:
AN221774 : Getting Started with PSoC 6 MCU
AN210781 : Getting Started with PSoC 6 MCU with Bluetooth
Low Energy Connectivity
AN218241 : PSoC 6 MCU Hardware Design Guide
AN213924 : PSoC 6 MCU Device Firmware Update Guide
AN219528 : PSoC 6 MCU Power Reduction Techniques
AN85951 : PSoC 4, PSoC 6 MCU CapSense Design Guide
Code Examples demonstrate product features and usage, and are also available on Cypress GitHub repositories .
Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC 6 MCU architecture and registers.
■
PSoC 6 MCU Programming Specification provides the information necessary to program PSoC 6 MCU nonvolatile memory.
■
Development Tools
❐
ModusToolbox
®
software enables cross platform code development with a robust suite of tools and software libraries.
❐
Secure Boot” SDK includes all required libraries, tools, and sample code to provision and develop applications for
PSoC 64 MCUs.
❐
❐
CY8CPROTO-064B0S1-BLE PSoC 64 “Secure Boot” Prototyping Kit: a low-cost hardware platform that enables design and debug of the PSoC 64 CYB06447BZI-BLDx product line
PSoC 6 CAD libraries provide footprint and schematic support for common tools. BSDL files and IBIS models are also available.
■ Training Videos are available on a wide range of topics including the PSoC 6 MCU 101 series .
■ Cypress Developer Community enables connection with fellow PSoC developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC 6 MCU Community.
Document Number: 002-28630 Rev. *I Page 4 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
ModusToolbox Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is:
■ Comprehensive - it has the resources you need
■ Flexible - you can use the resources in your own workflow
■ Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub . This includes:
■ Board Support Packages (BSPs) aligned with Cypress kits
■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)
■ Middleware enabling industry-leading features such as CapSense
®
, Bluetooth Low Energy, and mesh networks
■ An extensive set of thoroughly tested code example applications
Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained control.
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as
AN228571: Getting Started with PSoC 6 MCU on ModusToolbox .
Figure 1. ModusToolbox Software Tools
Document Number: 002-28630 Rev. *I Page 5 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Blocks and Functionality
where a block is still functional. For example, the SRAM is functional down to Deep Sleep mode.
Figure 2. Block Diagram
Color Key:
Power Modes and
Domains
System LP/ULP Mode
CPUs Active/Sleep
System
DeepSleep Mode
System
Hibernate Mode
Backup
Domain
PSoC 64 ““Secure Boot” MCU
CYB06447BZI -BLDx
System Resources
OVP
Power
LVD
POR BOD
Clocks
IMO ECO
FLL 2x PLL
Buck Regulator
XRES Reset
Backup Regs
2x MCWDT
PILO
ILO WDT
RTC WCO
PMIC Control
Programmable Analog
SAR ADC 12 bit
DAC 12 bit
2x Opamp
Temperature Sensor
CapSense
LCD
LP Comparator
Programmable Digital: 12x UDB
CPU Subsystem
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
2x DMA
Controller
Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator
Flash
1024 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM
288 KB
32x TCPWM
SCB
8x I2C, SPI,
UART, or LIN
I2C or SPI
Bluetooth LE
PSoC 6- BLE
Programmable
Link Layer
2 Mbps
Radio
Audio Subsystem
I2S
PDM - PCM
Profiler eFuse: 1024 bits
QSPI (SMIF) with OTF Encryption/Decryption
ROM
128 KB
USB - FS
USB
PHY
Document Number: 002-28630 Rev. *I Page 6 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
This product line has up to 1 MB of flash; however, 192 KB is reserved for system usage, leaving 832 KB for applications. It also has up to 288 KB of SRAM; however, 112 KB is reserved for system usage, leaving 176 KB for applications.
The PSoC 64 devices offer an immutable, RoT-based boot-up process, which allows only signed applications to be booted up. In addition, secured user assets such as keys and debug policies can be provisioned on the device in an HSM environment and made immutable PSoC 64 also allows for root-of-trust based cryptography services which can be accessed using System calls.
There are three debug access ports, one each for CM4 and CM0+, and a system port. All debug and test interfaces can be permanently disabled during final production provisioning to avoid any malicious reprogramming or reading of flash and register contents.
PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All device interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting and interrupting flash programming sequences. All programming, debug, and test interfaces can be disabled.
Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.
The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and
JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, PSoC 6 provides multiple levels of device security.
Document Number: 002-28630 Rev. *I Page 7 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Functional Description
The following sections provide an overview of the features, capabilities and operation of each functional block identified in the block diagram in
Figure 2 . For more detailed information,
refer to the following documentation:
■ Board Support Package (BSP) Documentation
BSPs are available on GitHub . They are aligned with Cypress kits and provide files for basic device functionality such as hardware configuration files, startup code, and linker files.
The BSP also includes other libraries that are required to support a kit. Each BSP has its own documentation, but typically includes an API reference such as the example here . This search link finds all currently available BSPs on the Cypress
GitHub site.
■ Hardware Abstraction Layer API Reference Manual
The Cypress Hardware Abstraction Layer (HAL) provides a high-level interface to configure and use hardware blocks on
Cypress MCUs. It is a generic interface that can be used across multiple product families. You can leverage the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained control. The HAL
API Reference provides complete details. Example applications that use the HAL download it automatically from the
GitHub repository.
■ Peripheral Driver Library (PDL) Application Programming
Interface (API) Reference Manual
The Peripheral Driver Library (PDL) integrates device header files and peripheral drivers into a single package and supports all PSoC 6 MCU product lines. The drivers abstract the hardware functions into a set of easy-to-use APIs. These are fully documented in the PDL API Reference . Example applications that use the PSoC 6 PDL download it automatically from the
GitHub repository.
■ Architecture Technical Reference Manual (TRM)
■
The architecture TRM provides a detailed description of each resource in the device. This is the next reference to use if it is necessary to understand the operation of the hardware below the software provided by PDL. It describes the architecture and functionality of each resource and explains the operation of each resource in all modes. It provides specific guidance regarding the use of associated registers.
Register Technical Reference Manual
The register TRM provides a complete list of all registers in the device. It includes the breakdown of all register fields, their possible settings, read/write accessibility, and default states. All registers that have a reasonable use in typical applications have functions to access them from within PDL.
Note that ModusToolbox and PDL may provide software default conditions for some registers that are different from and override the hardware defaults.
CPU and Memory Subsystem
PSoC 6 has multiple bus masters, as
shows. They are:
CPUs, DMA controllers, QSPI, USB, and a Crypto block.
Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer Arm AMBA high-performance bus (AHB) arbitration. Accesses between
CPUs can be synchronized using an inter-processor communication (IPC) block.
CPUs
There are two Arm Cortex CPUs:
The Cortex-M4 (CM4) has single-cycle multiply, a floating-point unit (FPU), and a memory protection unit (MPU). It can run at up to 150 MHz. This is the main CPU, designed for a short interrupt response time, high code density, and high throughput.
CM4 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the
Armv7-M Architecture
Reference Manual
).
The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU.
It can run at up to 100 MHz; however, for CM4 speeds above
100 MHz, CM0+ and bus peripherals are limited to half the speed of CM4. Thus, for CM4 running at 150 MHz, CM0+ and peripherals are limited to 75 MHz in system low power (LP) mode. In system ultra-low power (ULP) mode, CPU speeds are limited to 50 MHz and 25 MHz respectively.
In PSoC 64, the initial CM0+ frequency is set according to a provisioned security policy (see
). The frequency ranges from 8 MHz to 50 MHz. For more information, see the Architecture and Registers TRM .
CM0+ is the secondary CPU; it is used to implement system calls and device-level safety and protection features. CM0+ provides a secured, uninterruptible boot function. This helps ensure that post boot, system integrity is checked and memory and peripheral access privileges are enforced.
CM0+ implements the Armv6-M Thumb instruction set (defined in the
Armv6-M Architecture Reference Manual
).
The CPUs have the following power draw, at V
DDD using the internal buck regulator:
= 3.3 V and
Table 1. Active Current Slope at V
DDD
Internal Buck Regulator
= 3.3 V Using the
CPU
Cortex-M0+
Cortex-M4
System Power Mode
ULP
15 A/MHz
22 A/MHz
LP
20 A/MHz
40 A/MHz
The CPUs can be selectively placed in their Sleep and Deep
Sleep power modes as defined by Arm.
Both CPUs have nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, and wakeup interrupt controllers (WIC) for CPU wakeup from Deep Sleep power mode.
Document Number: 002-28630 Rev. *I Page 8 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
The CPUs have extensive debug support. PSoC 6 has a debug access port (DAP) that acts as the interface for device programming and debug. An external programmer or debugger
(the “host”) communicates with the DAP through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to restrictions), the host can access the device memory and peripherals as well as the registers in both CPUs.
Each CPU offers debug and trace features as follows:
■
CM4 supports six hardware breakpoints and four watchpoints,
4-bit embedded trace macrocell (ETM), serial wire viewer
(SWV), and printf()-style debugging through the single wire output (SWO) pin.
■
CM0+ supports four hardware breakpoints and two watchpoints, and a micro trace buffer (MTB) with 4-KB dedicated
RAM.
PSoC 6 also has an Embedded Cross Trigger for synchronized debugging and tracing of both CPUs.
Interrupts
This product line has 147 system and peripheral interrupt sources and supports interrupts and system exceptions on both
CPUs. CM4 has 147 interrupt request lines (IRQ), with the interrupt source ‘n’ directly connected to IRQn. CM0+ has 32 interrupts IRQ[31:0] with configurable mapping of one system interrupt source to any of the IRQ[31:0].
Each interrupt supports configurable priority levels (eight levels for CM4 and four levels for CM0+). One system interrupt can be mapped to each of the CPUs' non-maskable interrupts (NMI). Up to 41 interrupt sources are capable of waking the device from
Deep Sleep power mode using the WIC. Refer to the technical reference manual for details.
InterProcessor Communication (IPC)
In addition to the Arm SEV and WFE instructions, a hardware
InterProcessor Communication (IPC) block is included. It includes 16 IPC channels and 16 IPC interrupt structures. The
IPC channels can be used to implement data communication between the processors. Each IPC channel also implements a locking scheme which can be used to manage shared resources.
The IPC interrupts let one processor interrupt the other, signaling an event. This is used to trigger events such as notify and release of the corresponding IPC channels. Some IPC channels and
other resources are reserved, as Table 2
shows:
Table 2. Distribution of IPC Channels and Other Resources
Resources Available
IPC channels,
16 available
IPC interrupts,
16 available
Other interrupts
CM0+ NMI
Other resources: clock dividers, DMA channels, etc.
Resources Consumed
13 reserved
13 reserved
1 reserved
Reserved
4 CM0+ interrupt mux
DMA Controllers
There are two DMA controllers with 16 channels each, which support CPU-independent accesses to memory and peripherals.
The descriptors for DMA channels can be in SRAM or flash.
Therefore, the number of descriptors are limited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and destination. The size of data transfer per descriptor varies based on the type of DMA channel. Refer to the technical reference manual for detail.
Cryptography Accelerator (Crypto)
This subsystem consists of hardware implementation and acceleration of cryptographic functions and random number generators.
The Crypto subsystem supports the following:
■
■
■
❐
❐
❐
❐
❐
Encryption/Decryption Functions
Data Encryption Standard (DES)
Triple DES (3DES)
Advanced Encryption Standard (AES) (128-, 192-, 256-bit)
Elliptic Curve Cryptography (ECC)
RSA cryptography functions
❐
❐
❐
Hashing functions
Secure Hash Algorithm (SHA)
SHA-1
SHA-224/-256/-384/-512
Message authentication functions (MAC)
❐
❐
Hashed message authentication code (HMAC)
Cipher-based message authentication code (CMAC)
■
32-bit cyclic redundancy code (CRC) generator
■
Random number generators
❐
❐
Pseudo random number generator (PRNG)
True random number generator (TRNG)
Protection Units
This product line has multiple types of protection units to control erroneous or unauthorized access to memory and peripheral registers. CM4 and CM0+ have Arm MPUs for protection at the bus master level. Other bus masters use additional MPUs.
Shared memory protection units (SMPUs) help implement memory protection for memory resources that are shared among multiple bus masters. Peripheral protection units (PPU) are similar to SMPUs but are designed for protecting the peripheral register space.
Protection units support memory and peripheral access attributes including address range, read/write, code/data, privilege level, secured/non-secured, and protection context.
Some protection unit resources are reserved for system usage; see the technical reference manual (TRM) for details.
Up to eight protection contexts (boot is in protection context 0) allow access privileges for memory and system resources to be set by the boot process per protection context by bus master and code privilege level.
Document Number: 002-28630 Rev. *I Page 9 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
In PSoC 64, multiple protection contexts are used to isolate the different security levels within the device. The CM0+ makes use of several of them during the boot sequence, bootloading, system calls, etc. Protection context 6 is used for the user application code that runs on the CM4 CPU. The SMPUs are set up by default and cannot be modified by the user. See section 8 in the Architecture TRM for the protection context assignment.
Memory
PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks.
■ Flash
❐
❐
There is up to 1 MB of flash; however 192 KB is reserved for system usage, leaving 832 KB for applications, organized in
256-KB sectors. There are also two 32-KB flash sectors:
Auxiliary flash (AUXflash), typically used for EEPROM emulation
Supervisory flash (SFlash). Data stored in SFlash includes device trim values,
code, and encryption keys.
After the device transitions into the “Secure” lifecycle stage,
SFlash can no longer be changed.
The flash has 128-bit-wide accesses to reduce power. Write operations can be performed at the row level. A row is
512 bytes. Read operations are supported in both Low Power and Ultra-Low Power modes, however write operations may not be performed in Ultra-Low Power mode.
The flash controller has two caches, one for each CPU. Each cache is 8 KB, with 4-way set associativity.
■
SRAM
Up to 288 KB of SRAM is provided, however, 112 KB is reserved for system usage, leaving 176 KB for applications.
Power control and retention granularity is implemented in
32-KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode.
■ ROM
The 128-KB ROM, also referred to as the supervisory ROM
(SROM), provides code ( ROM Boot ) for several system func-
tions. The ROM contains device initialization, flash write, security, eFuse programming, and other system-level routines.
ROM code is executed only by the CM0+ CPU, in protection context 0. A system function can be initiated by either CPU, or through the DAP. This causes an NMI in CM0+, which causes CM0+ to execute the system function.
■ eFuse
A one-time-programmable (OTP) eFuse array consists of
1024 bits, all of which are reserved for system use. The bits are used for storing hash values, unique IDs, or other
PSoC 64 parameters.
Each fuse is individually programmed; once programmed (or
“blown”), its state cannot be changed. Blowing a fuse transitions it from the default state of 0 to 1. To program an eFuse,
V
DDIO0
must be at 2.5 V ±5%, at 14 mA.
Because blowing an eFuse is an irreversible process, programming is recommended only in mass production under controlled factory conditions. For more information, see
PSoC 6 MCU Programming Specifications .
Boot Code
Two blocks of code,
and
pre-programmed into the device and work together to provide device startup and configuration, basic security features, life-cycle stage management and other system functions.
■
ROM Boot
❐
❐
❐
❐
On a device reset, the boot code in ROM is the first code to execute. This code performs the following:
Integrity checks of flash boot code
Device trim setting (calibration)
Setting the device protection units
Setting device access restrictions for life-cycle states
ROM cannot be changed and acts as the Root of Trust in a secured system.
■
Flash Boot
Flash boot is a firmware module stored in SFlash and application flash. It ensures that only a validated application may run on the device. It also ensures that the firmware image has not been modified, such as by a malicious third party.
Flash boot:
❐
❐
❐
❐
❐
❐
❐
Is validated by ROM Boot
Runs after ROM Boot and before the user application
Enables system calls
Enables provisioning and device policy features
Implements RoT-based services for cryptography
Provides secured storage for keys and certificates
Validates and launches first image based on policies provisioned in the device
Uses mbed TLS v2.24
❐
If the user application cannot be validated, then flash boot ensures that the device is transitioned into a safe state. Refer
to PSoC 64 Security section for more details.
Document Number: 002-28630 Rev. *I Page 10 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Memory Map
Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided into the regions shown in
. Note that code can be executed from the Code and External RAM.
Table 3. Address Map for CM4 and CM0+
Address Range
0x0000 0000 – 0x1FFF FFFF
0x2000 0000 – 0x3FFF FFFF
0x4000 0000 – 0x5FFF FFFF Peripheral
0x6000 0000 – 0x9FFF FFFF
Name
Code
SRAM
External
RAM
Use
Program code region. Data can also be placed here. It includes the exception vector table, which starts at address 0.
Data region. This region is not supported in PSoC 6.
All peripheral registers.
Code cannot be executed from this region. CM4 bit-band in this region is not supported in PSoC 6.
SMIF or Quad SPI, (see the
section). Code can be executed from this region.
0xA000 0000 – 0xDFFF FFFF
0xE000 0000 – 0xE00F FFFF
0xE010 0A000 – 0xFFFF FFFF
External
Device
Private
Peripheral
Bus
Device
Not used.
Provides access to peripheral registers within the CPU core.
Device-specific system registers.
The device memory map shown in Table 4 applies to both CPUs.
That is, the CPUs share access to all PSoC 6 MCU memory and peripheral registers.
Table 4. Internal Memory Address Map for CM4 and CM0+
Address Range
0x0000 0000 – 0x0001 FFFF
0x0800 0000 – 0x0802 BFFF
0x0802 C000 - 0x0804 7FFF
0x1000 0000 - 0x100C FFFF
0x100D 0000 - 0x100F FFFF
Memory Type
ROM
Application SRAM
System SRAM
Application flash
Secured code flash
Used for secured boot, secured bootloader, and system calls
0x1400 0000 - 0x1400 7FFF Auxiliary flash, can be used for EEPROM emulation
0x1600 0000 - 0x1600 7FFF Supervisory flash, for secured access
Size
128 KB
Up to 176 KB
112 KB
832 KB
192 KB
32 KB
32 KB
Note that the SRAM is located in the Arm Code region for both
). There is no physical memory located in the
CPUs’ Arm SRAM regions.
System Resources
Power System
The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the reset occurring. There are no voltage sequencing requirements.
The V
DDD
supply (1.7 to 3.6 V) powers an on-chip buck regulator or a low-dropout regulator (LDO), selectable by the user. In addition, both the buck and the LDO offer a selectable (0.9 or
1.1 V) core operating voltage (V
CCD
). The selection lets users choose between two system power modes:
■ System Low Power (LP) operates V
CCD
at 1.1 V and offers high performance, with no restrictions on device configuration.
■ System Ultra Low Power (ULP) operates V speeds.
CCD
at 0.9 V for exceptional low power, but imposes limitations on clock
In addition, a backup domain adds an “always on” functionality using a separate power domain supplied by a backup supply
(V
BACKUP
) such as a battery or supercapacitor. It includes a real-time clock (RTC) with alarm feature, supported by a
32.768-kHz watch crystal oscillator (WCO), and power-management IC (PMIC) control. Refer to
for more details.
Power Modes
PSoC 6 MCU can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the application note, AN219528: PSoC 6 MCU Low-Power Modes and Power Reduction Techniques and the Architecture TRM,
Power Modes chapter .
Power modes supported by PSoC 6 MCUs, in the order of decreasing power consumption, are:
■ System Low Power (LP) – All peripherals and CPU power modes are available at maximum speed
■ System Ultra Low Power (ULP) – All peripherals and CPU power modes are available, but with limited speed
■ CPU Active – CPU is executing code in system LP or ULP mode
■ CPU Sleep – CPU code execution is halted in system LP or
ULP mode
■ CPU Deep Sleep – CPU code execution is halted and system
Deep Sleep is requested in system LP or ULP mode
■ System Deep Sleep – Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode
■ System Hibernate – Device and I/O states are frozen and the device resets on wakeup
Document Number: 002-28630 Rev. *I Page 11 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep and Hibernate modes are additional low-power modes supported by
PSoC 6 MCU.
The default clocking when the application starts is CLK_HF[0] being driven by the IMO and the FLL. CLK_HF[0], clk_fast, clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz
(ULP mode). All other clocks, including all peripheral clocks, are off.
Clock System
Figure 3 shows that the clock system consists of the following:
■
Internal main oscillator (IMO)
■
Internal low-speed oscillator (ILO)
■
Precision ILO (PILO)
■
Watch crystal oscillator (WCO)
■
External MHz crystal oscillators (ECOs) for the system and the
Bluetooth LE subsystem
■
External clock input
■
Phase-locked loop (PLL)
■
Frequency-locked loop (FLL)
Clocks may be buffered and brought out to a pin on a smart I/O port.
Internal Main Oscillator (IMO)
The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz and tolerance is ±2%.
Internal Low-speed Oscillator (ILO)
The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against a higher accuracy clock for better accuracy.
Precision ILO (PILO)
PILO is a 32.768-kHz clock that can provide a more accurate clock than ILO when periodically calibrated using a high-accuracy clock such as the ECO.
Figure 3. Clocking Diagram
Yellow multiplexers are glitch safe
Path Mux (FLL/PLL)
IMO
FLL
Root mux
Predivider
(1/2/4/8)
CLK_HF[0] dsi_in0
Divider clk_peri
EXTCLK
ECO
ALTHF dsi_out <1:0>
System LP/ULP Domain
System Deep Sleep /
Hibernate Domain
ILO*
WCO* *Works in Hibernate
PLL
CLK_PATH2
CLK_PATH3
CLK_PATH4
CLK_LF
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CLK_HF[1] dsi_in1
CLK_HF[2] dsi_in2
CLK_HF[3] dsi_in3
CLK_HF[4] dsi_in4
Divider
Audio
QSPI/SMIF
USB clk_ext
Divider
CM4
Peripheral
Clock Dividers
Peripheral clocks
TCPWM
SCB
CM0+
CapSense
AHB
UDB
DMA eFuse
MMIO
LCD
Analog
Subsystem
Smart I/O
PPU
Crypto
PILO
Document Number: 002-28630 Rev. *I Page 12 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
External Crystal Oscillators
TRM
Figure 4 shows all of the external crystal oscillator circuits
for this product line. The component values shown are typical; check the
for the crystal values, and the crystal datasheet for the load capacitor values. The ECO and
WCO require balanced external load capacitors. The Bluetooth
LE oscillator does not require external load capacitors. For more information, see the TRM and
Figure 4. Oscillator Circuits
AN218241, PSoC 6 MCU
Hardware Design Considerations .
PSoC 6
MHz XTAL 32.768 kHz XTAL
MHz XTAL for
Bluetooth LE
C
L
/ 2 C
L
/ 2 C
L
/ 2 C
L
/ 2
If the ECO is used, note that its performance is affected by GPIO switching noise. GPIO ports should be used as
shows.
See also
for additional restrictions for general analog subsystem use.
Table 5. ECO Usage Guidelines
Ports
DDD
≤ 2.7 V
Port 11 60 MHz for SMIF
(QSPI)
Drive Strength for V
DDD
> 2.7 V
DRIVE_SEL 2 DRIVE_SEL 3
Ports 12 and 13
Slow slew rate setting
No restrictions No restrictions
Watchdog Timers (WDT, MCWDT)
PSoC 6 MCU has one WDT and two multi-counter WDTs
(MCWDTs). The WDT has a 16-bit free-running counter. Each
MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event.
The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup generation in system LP/ULP and Deep Sleep power modes.
Clock Dividers
■
■
■
■
Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are:
Eight 8-bit clock dividers
Sixteen 16-bit integer clock dividers
Four 16.5-bit fractional clock dividers
One 24.5-bit fractional clock divider
Trigger Routing
PSoC 6 MCU contains a trigger multiplexer block. This is a collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between
GPIOs and peripheral blocks.
There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination. There are also hardwired switches called “one-to-one triggers”, which connect a specific source to a destination. The user can enable or disable the route.
Reset
PSoC 6 MCU can be reset from a variety of sources:
■
Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to function properly. POR activates automatically at power-up.
■
■
Brown-out detect (BOD) reset to monitor the digital voltage supply V
DDD
and generate a reset if V
DDD minimum required logic operating voltage.
falls below the
External reset dedicated pin (XRES) to reset the device using an external source. The XRES pin is active low. It can be connected either to a pull-up resistor to V
DDD
, or to an active
drive circuit, as Figure 5 shows. If a pull-up resistor is used,
select its value to minimize current draw when the pin is pulled low; 4.7 kΩ to 100 kΩ is typical.
Figure 5. XRES Connection Diagram
1.7 to 3.6 V
PSoC 6
V
DDD
4.7 kΩ typ.
XRES drive
XRES
Document Number: 002-28630 Rev. *I Page 13 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
■
■
■
■
Watchdog timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout period.
Software-initiated reset to reset the device on demand using firmware.
Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur; for example, reaching a debug breakpoint while executing privileged code.
Hibernate wakeup reset to bring the device out of the system
Hibernate low-power mode.
Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to determine the cause of the reset.
Bluetooth LE Radio and Subsystem
This product line incorporates a Bluetooth LE subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded security engine. Cypress also provides extensive driver library and middleware support for Bluetooth LE;
The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian frequency shift keying (GFSK) packets at 2 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth LE Specification 5.0.
The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine).
The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it through the antenna.
Key features, implemented in hardware and firmware, are as follows:
■
Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols
■
API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP
■
L2CAP connection-oriented channel (Bluetooth 4.1 feature)
■
❐
❐
GAP features
❐
❐
Broadcaster, Observer, Peripheral, and Central roles
Security Mode 1: Level 1, 2, 3, and 4; Security Mode 2: Level
1 and 2
User-defined advertising data
Multiple bond support
■
❐
❐
❐
GATT features
GATT Client and Server
Supports GATT sub-procedures
32-bit universally unique identifier (UUID) (Bluetooth 4.1
feature)
■
❐
❐
❐
Security Manager (SM)
Pairing methods: Just works, Passkey Entry, and Out of Band
LE Secure Connection Pairing model
Authenticated man-in-the-middle (MITM) protection and data signing
■
❐
❐
❐
❐
❐
❐
Link Layer (LL)
Master and Slave roles
128-bit AES engine
Low-duty cycle advertising
LE Ping
LL privacy 1.2 (Bluetooth 4.2 feature)
Data length extension (Bluetooth 4.2 feature)
■ Supports all SIG-adopted Bluetooth LE profiles
Power consumption for Advertisement (1.28s, 31-byte packets,
0 dBm TX output power) and Connection (300 ms, 0-byte packets, 0 dBm TX output power) are 42 µW and 70 µW respectively
Document Number: 002-28630 Rev. *I Page 14 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Programmable Analog Subsystem
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. One of three internal references may be used for the ADC reference voltage: V
V
DDA/2
DDA
,
, and an analog reference (AREF). AREF is nominally
1.2 V, trimmed to ±1%; see Table 23 . An external reference may
also be used, by driving the V
REF
pin. When using V
DDA/2
or
AREF as a reference, an external bypass capacitor may be
REF
pin to improve performance in noisy connected to the V conditions. These reference options allow ratio-metric readings or absolute readings at the accuracy of the reference used. The input range of the ADC is the full supply voltage between V and V
DDA
/V
DDIOA of single-ended and differential signals in the same configuration.
SS
. The SAR ADC may be configured with a mix
The SAR ADC’s sample-and-hold (S/H) aperture is programmable to allow sufficient time for signals with a high impedance to settle sufficiently, if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used and system noise levels permit it.
The SAR is connected to a fixed set of pins through an input multiplexer. The multiplexer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The result of each channel is buffered, so that an interrupt may be triggered only when a full scan of all channels is complete. Also, a pair of range registers can be set to detect and cause an interrupt if an input exceeds a minimum and/or maximum value. This allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR can also be connected, under firmware control, to most other GPIO pins via the Analog Multiplexer Bus (AMUXBUS). The SAR is not available in Deep Sleep and Hibernate modes as it requires a high -speed clock (up to 18 MHz). The SAR operating range is
1.71 to 3.6 V.
ADC accuracy is affected by GPIO switching noise. To improve
accuracy, implement the GPIO port restrictions listed in Table 6 .
In addition, there should be no switching outputs on ports 9 and
10.
Temperature Sensor
An on-chip temperature sensor is part of the SAR and may be scanned by the SAR ADC. It consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor may be connected directly to the SAR ADC as one of the measurement channels. The ADC digitizes the temperature sensor’s output and a Cypress-supplied software function may be used to convert the reading to temperature which includes calibration and linearization.
12-bit Digital-Analog Converter
There is a 12-bit voltage mode DAC on the chip, which can settle in less than 2 µs. The DAC may be driven by the DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output using an opamp in the CTBm block.
Continuous Time Block mini (CTBm) with Two Opamps
This block consists of two opamps, which have their inputs and outputs connected to pins and other analog blocks, as
shows. They have three power modes (high, medium, and low) and a comparator mode. The opamps can be used to buffer SAR inputs and DAC outputs. The non-inverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware.
The opamps also support operation in system Deep Sleep mode, with lower performance and reduced power consumption.
Low-Power Comparators
Two low-power comparators are provided, which can operate in all power modes. This allows other analog system resources to be disabled while retaining the ability to monitor external voltage levels during system Deep Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a comparator-switch event.
Document Number: 002-28630 Rev. *I Page 15 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Architecture TRM for detailed connectivity information.
Figure 6. Analog Subsystem
AMUXBUSA
AMUXBUSB
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
LPCOMP0 inp inn
LPCOMP1 inp inn
CSD shield_pad vref_ext csh cmod amuxbusa amuxbusb
V
DDA
CTDAC vref vout
S/H
Red dots indicate
AMUXBUS splitter switches
The DAC output is also routed directly to P9.6; not shown in this diagram.
See the Alternate Port
Pin Functionality table.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P14.0
P14.1
P9.3
P9.7
P9.5
P9.4
P9.0
P9.6
P9.1
P9.2
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
AREF, 1.2 V
TEMP temp
V
SS
OA1
+
-
10x comp out
1x
OA0
+
-
10x
1x comp out
Bold lines indicate direct connections from the opamp 10x ouputs directly to port pins.
SAR ADC vplus vminus vref
V
V
DDA
DDA
/ 2
SARREF
To V
REF pin, for bypass capacitor
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
Document Number: 002-28630 Rev. *I Page 16 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Programmable Digital
Smart I/O
Smart I/O is a programmable logic fabric that enables Boolean operations on signals traveling from device internal resources to the GPIO pins or on signals traveling into the device from external sources. A Smart I/O block sits between the GPIO pins and the high-speed I/O matrix (HSIOM) and is dedicated to a single port.
There are two Smart I/O blocks: one on Port 8 and one on Port 9.
When Smart I/O is not enabled, all signals on Port 8 and Port 9 bypass the Smart I/O hardware.
Smart I/O supports:
■ System Deep Sleep operation
■ Boolean operations without CPU intervention
■ Asynchronous or synchronous (clocked) operation
Each Smart I/O block contains a data unit (DU) and eight lookup tables (LUTs).
The DU:
■ Performs unique functions based on a selectable opcode.
■ Can source input signals from internal resources, the GPIO port, or a value in the DU register.
Each LUT:
■ Has three selectable input sources. The input signals may be sourced from another LUT, an internal resource, an external signal from a GPIO pin, or from the DU.
■ Acts as a programmable Boolean logic table.
■ Can be synchronous or asynchronous.
Universal Digital Blocks (UDBs)
This product line has 12 UDBs. Each UDB is a collection of uncommitted logic (PLD) and nano-CPU (datapath) optimized to create common embedded peripherals and custom functionality, as
Figure 7 shows. UDB datapaths are 8 bits wide, and can be
chained to form 16, 24, and 32-bit functions. Included with the
UDBs is the digital system interconnect (DSI), which routes signals among UDBs, fixed function peripherals, I/O pins and other system blocks to implement full featured device connectivity. The DSI enables routing between any digital function and any pin. Port adapter blocks extend the UDBs to provide an interface to the GPIOs through the HSIOM.
Figure 7. UDB Block Diagram
PLD
Chaining
Clock
and Reset
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Status and
Control Datapath
Datapath
Chaining
Fixed-Function Digital
Timer/Counter/Pulse-width Modulator (TCPWM) Block
■
■
■
■
■
■ The TCPWM supports the following operational modes:
❐ Timer-counter with compare
❐
Timer-counter with capture
❐ Quadrature decoding
❐
Pulse width modulation (PWM)
❐ Pseudo-random PWM
❐
PWM with dead time
Up, down, and up/down counting modes.
Clock prescaling (division by 1, 2, 4, ... 64, 128)
Double buffering of compare/capture and period values
Underflow, overflow, and capture/compare output signals
Supports interrupt on:
❐
Terminal count – Depends on the mode; typically occurs on overflow or underflow
❐
Capture/compare – The count is captured to the capture register or the counter value equals the value in the compare register
■ Complementary output for PWMs
■ Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state.
In this device there are:
■ Eight 32-bit TCPWMs
■ Twenty-four 16-bit TCPWMs
Serial Communication Blocks (SCB)
This product line has nine SCBs:
■ Eight can implement either I
2
C, UART, or SPI.
■ One SCB (SCB #8) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I slave.
2
C
I
2
C Mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I
2
C communication to reading from and writing to an array in the memory.The SCB supports a 256-byte
FIFO for receive and transmit.
I
The I
Mode, and Fast Mode Plus devices as defined in the NXP
2
2
C peripheral is compatible with I
2
C standard-mode, Fast
C-bus specification and user manual (UM10204). The I
I/O is implemented with GPIO in open-drain modes.
2
C bus
UART Mode: This is a full-feature UART operating at up to
8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated.
Routing Channel
Document Number: 002-28630 Rev. *I Page 17 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 25-MHz clock.
USB Full-Speed Device Interface
PSoC 6 incorporates a full-speed USB device interface. The device can have up to eight endpoints. A 512-byte SRAM buffer is provided and DMA is supported.
Note: If the USB pins are not used, connect V and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
DDUSB
to ground
GPIO
This product line has up to 84 GPIOs, which implement:
■
❐
❐
❐
❐
❐
❐
❐
❐
Eight drive strength modes:
Analog input mode (input and output buffers disabled)
Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL)
■ Hold mode for latching previous state (used for retaining the
I/O state in system Hibernate mode)
QSPI Interface Serial Memory Interface (SMIF)
A serial memory interface is provided, running at up to 80 MHz.
It supports single, dual, quad, dual-quad and octal SPI configurations, and supports up to four external memory devices.
It supports two modes of operation:
■
■
Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and FIFOs
Execute in Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers.
In XIP mode, the external memory is mapped into the PSoC 6
MCU internal address space, enabling code execution directly from the external memory. To improve performance, a 4-KB cache is included. XIP mode also supports AES-128 on-the-fly encryption and decryption, enabling secured storage and access of code and data in the external memory.
LCD
This block drives LCD commons and segments; routing is available to most of the GPIOs. One to eight of the GPIOs must be used for commons, the rest can be used for segments.
The LCD block has two modes of operation: high speed (8 MHz) and low speed (32 kHz). Both modes operate in system LP and
ULP modes. Low-speed mode operates with reduced contrast in system Deep Sleep mode - review the number of common and segment lines, viewing angle requirements, and prototype performance before using this mode.
■ Selectable slew rates for dV/dt-related noise control to improve
EMI
The pins are organized in logical entities called ports, which are up to 8 pins in width. Data output and pin state registers store, respectively, the values to be driven on the pins and the input states of the pins.
Every pin can generate an interrupt if enabled; each port has an interrupt request (IRQ) associated with it.
The port 1 pins are capable of overvoltage-tolerant (OVT) operation, where the input voltage may be higher than V
OVT pins are commonly used with I
2 chip OFF while maintaining a physical connection to an operating I
2
DDD
C, to allow powering the
.
C bus without affecting its functionality.
GPIO pins can be ganged to source or sink higher values of current. GPIO pins, including OVT pins, may not be pulled up
higher than the absolute maximum; see Electrical Specifications .
During power-on and reset, the pins are forced to the analog input drive mode, with input and output buffers disabled, so as not to crowbar any inputs and/or cause excess turn-on current.
A multiplexing network known as the high-speed I/O matrix
(HSIOM) is used to multiplex between various peripheral and analog signals that may connect to an I/O pin.
Analog performance is affected by GPIO switching noise. In order to get the best analog performance, the following frequency and drive mode constraints must be applied. The
DRIVE_SEL values (refer to
Table 6 ) represent drive strengths
(see the Architecture and Register TRMs for further detail).
See also
for additional restrictions for ECO use.
Table 6. DRIVE_SEL Values
Ports
Port 0
Port 1
Ports 5 to 10
Ports 11 to 13
Ports 9 and 10
Max Frequency
8 MHz
1 MHz; slow slew rate, 2 outputs max
16 MHz; 25 MHz for SPI
80 MHz for SMIF (QSPI).
8 MHz; slow slew rate setting for TQFP
Packages for ADC performance
Drive Strength for V
DDD
≤ 2.7 V Drive Strength for V
DDD
> 2.7 V
DRIVE_SEL 2 DRIVE_SEL 3
DRIVE_SEL 1
No restrictions
DRIVE_SEL 2
No restrictions
Document Number: 002-28630 Rev. *I Page 18 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Special-Function Peripherals
Audio Subsystem
This subsystem consists of the following hardware blocks:
■
One Inter-IC Sound (I
2
S) interface
■
Two pulse-density modulation (PDM) to pulse-code modulation
(PCM) decoder channels
The I
2
S interface implements two independent hardware FIFO buffers – TX and RX, which can operate in master or slave mode.
The following features are supported:
■
Multiple data formats – I
2
S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B
■
Programmable channel/word lengths – 8/16/18/20/24/32 bits
■
Internal/external clock operation. Up to 192 ksps
■
Interrupt mask events – trigger, not empty, full, overflow, underflow, watchdog
■
Configurable FIFO trigger level with DMA support
The I
2
S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones.
The PDM-to-PCM decoder implements a single hardware Rx
FIFO that decodes a stereo or mono 1-bit PDM input stream to
PCM data output. The following features are supported:
■ Programmable data output word length – 16/18/20/24 bits
■
Programmable gain amplifier (PGA) for volume control – from
–12 dB to +10.5 dB in 1.5 dB steps
■ Configurable PDM clock generation. Range from 384 kHz to
3.072 MHz
■
Droop correction and configurable decimation rate for sampling; up to 48 ksps
■ Programmable high-pass filter gain
■
Interrupt mask events – not empty, overflow, trigger, underflow
■ Configurable FIFO trigger level with DMA support
The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM Data line.
CapSense Subsystem
CapSense is supported in PSoC 6 MCU through a CapSense sigma-delta (CSD) hardware block. It is designed for high-sensitivity self-capacitance and mutual-capacitance measurements, and is specifically built for user interface solutions.
In addition to CapSense, the CSD hardware block supports three general-purpose functions. These are available when CapSense is not being used. Alternatively, two or more functions can be time-multiplexed in an application under firmware control. The four functions supported by the CSD hardware block are:
■ CapSense
■ 10-bit ADC
■ Programmable current sources (IDAC)
■ Comparator
Document Number: 002-28630 Rev. *I
CapSense
Capacitive touch sensors are designed for user interfaces that rely on human body capacitance to detect the presence of a finger on or near a sensor. Cypress CapSense solutions bring elegant, reliable, and simple capacitive touch sensing functions to applications including IoT, industrial, automotive, and home appliances.
The Cypress-proprietary CapSense technology offers the following features:
■
Best-in-class signal-to-noise ratio (SNR) and robust sensing under harsh and noisy conditions
■
Self-capacitance (CSD) and mutual-capacitance (CSX) sensing methods
■
Support for various widgets, including buttons, matrix buttons, sliders, touchpads, and proximity sensors
■
High-performance sensing across a variety of materials
■
Best-in-class liquid tolerance
■
SmartSense auto-tuning technology that helps avoid complex manual tuning processes
■
Superior immunity against external noise
■
Spread-spectrum clocks for low radiated emissions
■
Gesture and built-in self-test libraries
■
Ultra-low power consumption
■
An integrated graphical CapSense tuner for real-time tuning, testing, and debugging
CapSense sensitivity and accuracy are affected by GPIO switching noise. To improve sensitivity and accuracy, implement the GPIO port restrictions listed in
, and do the following:
■
Restrict CapSense pins to ports 6 and 7
■
There should be no other GPIO output activity on ports 6 and 7
■
There should be no more than two GPIO outputs on ports 5 and 8
■
Restrict GPIO output switching in ports 5 and 8 to 1 MHz, with slow slew rate setting
ADC
The CapSense subsystem slope ADC offers the following features:
■
Selectable 8- or 10-bit resolution
■
Selectable input range: GND to V
REF
GPIO input
and GND to V
DDA
on any
■
Measurement of V
DDA
against an internal reference without the use of GPIO or external components
IDAC
The CSD block has two programmable current sources, which offer the following features:
■
7-bit resolution
■
Sink and source current modes
■
A current source programmable from 37.5 nA to 609 A
■
Two IDACs that can be used in parallel to form one 8-bit IDAC
Page 19 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Comparator
The CapSense subsystem comparator operates in the system
Low Power and Ultra-Low Power modes. The inverting input is connected to an internal programmable reference voltage and the non-inverting input can be connected to any GPIO via the
AMUXBUS.
CapSense Hardware Subsystem
Figure 8 shows the high-level hardware overview of the
CapSense subsystem, which includes a delta sigma converter, internal clock dividers, a shield driver, and two programmable current sources.
The inputs are managed through analog multiplexed buses
(AMUXBUS A/B). The input and output of all functions offered by the CSD block can be provided on any GPIO or on a group of
GPIOs under software control, with the exception of the comparator output and external capacitors that use dedicated
GPIOs.
Self-capacitance is supported by the CSD block using
AMUXBUS A, an external modulator capacitor, and a GPIO for each sensor. There is a shield electrode (optional) for self-capacitance sensing. This is supported using AMUXBUS B and an optional external shield tank capacitor (to increase the drive capability of the shield driver) should this be required.
Mutual-capacitance is supported by the CSD block using
AMUXBUS A, two external integrated capacitors, and a GPIO for transmit and receive electrodes.
The ADC does not require an external component. Any GPIO that can be connected to AMUXBUS A can be an input to the
ADC under software control. The ADC can accept V voltage measurement).
DDA
as an input without needing GPIOs (for applications such as battery
The two programmable current sources (IDACs) in general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator resides in the delta-sigma converter. The comparator inverting input can be connected to the reference. Both comparator inputs can be connected to any GPIO using AMUXBUS B; see
Figure 8 . The reference has a direct connection to a dedicated
GPIO; see Table 9 .
The CSD block can operate in active and sleep CPU power modes, and seamlessly transition between system LP and ULP modes. It can be powered down in system Deep Sleep and
Hibernate modes. Upon wakeup from Hibernate mode, the CSD block requires re-initialization. However, operation can be resumed without re-initialization upon exit from Deep Sleep mode, under firmware control.
Figure 8. CapSense Hardware Subsystem
AMUXBUS
A B
GPIO Pin
GPIO
Cell
CSD Sensor 1
CS1
Clock Input
GPIO Pin
GPIO
Cell
CSD Sensor 2
CS2
CSD Hardware Block
CMOD Pin
C MOD Sense clock
Clock
Generator
C
SH_TANK
( optional )
GPIO Pin
Shield Drive
Circuit
Modulator
Clock
GPIO Pin
GPIO
Cell
Compensation
IDAC
CSHIELD
Shield Electrode
Modulator
IDAC
Tx
GPIO Pin
GPIO
Cell
IDAC control
CSX Sensor 3
CS3
Raw
Count
CINT
A
Rx
GPIO Pin
GPIO
Cell
CINTAPin
GPIO
Cell
VREF
Sigma Delta
Converter
CINT
B
CINTB Pin
GPIO
Cell
ADC Input
IDAC Outputs
Comp Input
Document Number: 002-28630 Rev. *I Page 20 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Figure 9 shows the high-level software overview. Cypress
provides middleware libraries for CapSense , ADC , and IDAC on
GitHub to enable quick integration. The Board Support Package for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
User applications interact only with middleware to implement functions of the CSD block. The middleware interacts with underlying drivers to access hardware as necessary. The CSD driver facilitates time-multiplexing of the CSD hardware if more than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
ModusToolbox Software provides a CapSense configurator to enable fast library configuration. It also provides a tuner for performance evaluation and real-time tuning of the system. The tuner requires an EZI2C communication interface in the application to enable real-time tuning capability. The tuner can update configuration parameters directly in the device as well as in the configurator.
CapSense and ADC middleware use the CSD interrupt to implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be managed in the application.
Refer to
Guide
AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
for more details on CSX sensing, CSD sensing, shield electrode usage and its benefits, and capacitive system design guidelines.
Refer to the API reference guides for available on GitHub.
Figure 9. CapSense Software/Firmware Subsystem
CapSense , ADC , and IDAC
Application Program
Software
Configurator
Middleware
Tuner
SCB Driver
(EZI2C)
SCB
CSD Driver
GPIO / Clock
Drivers
CSD Block
Hardware and Drivers
GPIOs / Clock
Document Number: 002-28630 Rev. *I Page 21 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
PSoC 64 Security
All PSoC 64 “Secure Boot” MCU product lines feature enhanced security functionality. They provide an isolated root of trust (RoT) with true attestation and provisioning services. Cypress also provides a “Secure Boot” SDK User Guide, which includes all required libraries, tools, and sample code to provision PSoC 64 devices. The SDK also provides provisioning scripts with sample keys and policies, a pre-built bootloader image, and tools for signing firmware images. For more information, see the “Secure
Boot” SDK User Guide .
The “Secure Boot” SDK also includes entrance exam scripts. An entrance exam can optionally be run on PSoC 64 devices before provisioning to help ensure that no device tampering has occurred.
The first step in using a PSoC 64 device is to inject the following information into the device - a process called provisioning:
■
■
■
A set of cryptographic public keys, which are used to:
❐
❐
Transfer the RoT from Cypress to the user/OEM, as
shows
Validate applications
A set of security policies that define how the device should behave
Certificates (optional) used to bind device identity or provide a chain of trust to a higher certifying authority
■ The Cypress bootloader
Provisioning is done before an application is programmed into the device.
Figure 10. PSoC 64 Usage Processes
Manufacture Take Over Root-of-Trust Setup chip security
Program
Application
Cy RoT
Public Key
PSoC 64
OEM RoT
Public Key
Unique Device
Identity
PSoC 64
User RoT
Public Key
Unique Device
Identity
Keys, Security
Policies, Certificates
Cypress Bootloader
User RoT
Public Key
Unique Device
Identity
Keys, Security
Policies, Certificates
Cypress Bootloader
PSoC 64
User Application
PSoC 64
Provisioning is done using a hardware security module (HSM). An HSM is a physical computing device, placed in a secured facility, that safeguards and manages digital keys for strong authentication, and provides cryptographic processing.
After the device is provisioned, it can be programmed with signed applications. The signature and authenticity of the application is verified before control is transferred to it.
Document Number: 002-28630 Rev. *I Page 22 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SRAM is also reserved for system usage.
Figure 11. PSoC 64 “Secure” MCU Asset Memory Map
0x1000:0000
User Application Space
Cypress Bootloader
“Secure Flash Boot”
0x101E:0000
OEM Asset storage
User Flash
“Secure Flash Boot” +
Cypress Public Key
Supervisory Flash
0x101F:BF00
0x101F:FFFF
0x1600:7FFF
Boot ROM
ROM
0x101D:0000
0x1600:0000
0x0001:FFFF
0x0000:0000
Typically immutable, can be updated if allowed by security policy during provisioning
Immutable after Cypress
Manufacturing
Typically immutable, can be partially updated if allowed by security policy during provisioning
Immutable after Cypress
Manufacturing
Document Number: 002-28630 Rev. *I Page 23 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Cypress Bootloader
The Cypress Bootloader is a port of the open source MCUBoot library. For more details about this library, refer to MCUBoot
Bootloader design . The current version of The Cypress
Bootloader for this device does not support the swap-based images feature as documented in the MCUBoot design document.
The Cypress Bootloader is included in the “Secure Boot” SDK as a pre-built hex image. This image acts as the first image launched by the PSoC 64 boot code. It parses the provisioned
Boot&Upgrade policy to launch an application image.
The Cypress Bootloader supports external memory over the
PSoC 64 Serial Memory Interface (SMIF). The bootloader currently supports only external memory vendors who support the Serial Flash Discovery Protocol (SFDP).
The Cypress Bootloader enforces protection contexts for the bootloader code, so code running in another protection context may be prohibited from overwriting/tampering with the bootloader code.
Cypress Bootloader:
Figure 12. Bootloader Launch Sequence
shows the launch sequence of the
Reads for setting access policies
Boot ROM +
“Secure Flash Boot”
Verifies & Launches
Address of Bootloader image and key for verification
Debug Policy
Cypress Bootloader
Boot Policy
Verifies & Launches
Bootloader Certificate
Address of User image and key for verification
Provisioned Policies
First User Image
Signed with OEM Pvt key
shows a typical application update scenario using the Cypress Bootloader.
Figure 13. Bootloader Application Update Sequence
New image available Bootloader verifies new image
Image
Written
Immutable Boot Code
Cypress Bootloader
Keys, Policies
Customer Application v1
Signed with User Privkey
Slot#0
New Image Customer
Application v2
Signed with User
Privkey
Immutable Boot Code
Cypress Bootloader
Keys, Policies
Customer Application v1
Signed with User Privkey
Slot#0
Verifies new image content and signature with provisioned keys
Bootloader updates current image
Immutable Boot Code
Cypress Bootloader
Keys, Policies
Update image, launches
Customer Application v2
Signed with User Privkey
Slot#0
Customer Application v2
Slot#1, empty
Slot#1, empty
Internal (or) External flash
Signed with User Privkey
Slot#1
Internal (or) External flash Internal (or) External flash
Document Number: 002-28630 Rev. *I Page 24 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Pinouts
Note: The CYB06447BZI-BLDx Datasheet web page contains a spreadsheet with a consolidated list of pinouts and pin alternate functions with HSIOM mapping.
GPIO ports are powered by V
DDx
pins as follows:
■ P0: V
BACKUP
■
■
P1: V
DDD
. Port 1 pins are overvoltage tolerant (OVT).
P5, P6, P7, P8: V
DDIO1
■
■
P9, P10: V
DDIOA
, V
DDA
(V
DDIOA
, when present, and V
DDA
must be connected together on the PCB)
P11, P12, P13: V
DDIO0
■ P14: V
DDUSB
Table 7. Packages and Pin Information
Pin
V
DDD
V
CCD
V
DDA
V
DDIOA
V
DDIO0
V
DDIO1
V
BACKUP
V
DDUSB
V
SS
V
SSR
V
DD_NS
V
IND1
V
IND2
V
BUCK1
V
RF
V
DCDC
V
DDR1
V
DDR2
V
DDR3
DV
DD
V
DDR_HVL
XRES
V
REF
ANT
XI
XO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
124-BGA
A13
B13
M13
N13
D11
M4
A10
A2
C11, D4, D10, K4, K10, M12
A1, B1, B2, C3, D1, E3, G2
A5
B5
B4
C4
A4
B9
A9
C8
B8
C7
C1
F1
E1
C9
F2
G3
A8
N12
F3
C2
E2
D2
Document Number: 002-28630 Rev. *I
Packages
116-BGA
B1
A2
A9
-
B3
G10
C1
-
B2, B9, D1, H2, H9
J1, K2, K3, K4, K5, L1, L3, L4, L5, M3, M8
H3
F1
G1
G2
H1
D3
E4
E3
F3
D2
K1
M4
M5
C2
M7
L2
M1
M2
M6
L7
E2
B10
Page 25 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 7. Packages and Pin Information
(continued)
Pin
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P5.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
N1
L4
N5
M5
N2
N3
M3
N4
L2
L1
M2
M1
K1
K2
K3
L3
124-BGA
B7
A7
C6
B6
A6
H1
J3
J2
J1
C5
G1
H3
H2
M8
L9
M9
N9
L8
N10
M10
L10
N7
M7
L7
N8
L5
N6
M6
L6
Packages
Document Number: 002-28630 Rev. *I
H7
H6
G9
G8
K10
J10
H10
H8
K9
J9
M10
L10
-
K8
J8
L9
116-BGA
G3
F2
J5
J4
J3
K7
J7
L8
M9
J2
L6
K6
J6
E7
D10
D9
D8
D7
C10
C9
C8
F7
G6
E9
E8
G7
F10
F9
F8
Page 26 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 7. Packages and Pin Information
(continued)
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P11.6
P11.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P13.6
P13.7
P14.0 / USBDP
P14.1 / USBDM
NC
P10.6
P10.7
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P9.7
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
Pin
E12
E11
D13
D12
A12
C13
C12
B12
H11
G13
G12
G11
F13
F12
F11
E13
124-BGA
N11
M11
L13
L12
L11
K13
K12
K11
J13
J12
J11
H13
H12
B11
A11
C10
B10
B3
A3
D3
Packages
116-BGA
C7
B8
A8
F6
E6
D6
B7
A7
-
F5
E5
D5
C6
B6
A6
B5
A5
A4
B4
C4
A3
C5
D4
G5
H5
H4
G4
-
-
-
-
F4
C3
-
-
-
Note: If the USB pins are not used, connect V
DDUSB
to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
Document Number: 002-28630 Rev. *I Page 27 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Each Port Pin has multiple alternate functions. These are defined in
.
Table 8. Multiple Alternate Functions
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P1.0
P1.1
tcpwm[0].li
ne[0]:0 tcpwm[0].li
ne_compl[
0]:0 tcpwm[0].li
ne[1]:0 tcpwm[0].li
ne_compl[
1]:0 tcpwm[0].li
ne[2]:0 tcpwm[0].li
ne_compl[
2]:0 tcpwm[0].li
ne[3]:0 tcpwm[0].li
ne_compl[
3]:0 tcpwm[0].li
ne[4]:4 tcpwm[1].lin
e[0]:0 tcpwm[1].lin
e_compl[0]:
0 tcpwm[1].lin
e[1]:0 tcpwm[1].lin
e_compl[1]:
0 tcpwm[1].lin
e[2]:0 tcpwm[1].lin
e_compl[2]:
0 tcpwm[1].lin
e[3]:0 tcpwm[1].lin
e_compl[3]:
0 tcpwm[1].lin
e[12]:1 srss.ext_
clk:0 srss.ext_
clk:1 scb[0].uart
_rx:0 scb[0].uart
_tx:0 scb[0].uart
_rts:0 scb[0].uart
_cts:0 scb[7].uart
_rx:0 scb[7].uart
_tx:0 scb[0].i2c
_scl:0 scb[0].i2c
_sda:0 scb[7].i2c
_scl:0 scb[7].i2c
_sda:0 scb[0].spi_
select1:0 scb[0].spi_
select2:0 scb[0].spi_
mosi:0 scb[0].spi_
miso:0 scb[0].spi_
clk:0 scb[0].spi_
select0:0 scb[7].spi_
mosi:0 scb[7].spi_
miso:0 peri.tr_io_in
put[0]:0 peri.tr_io_in
put[1]:0 peri.tr_io_in
put[2]:0 peri.tr_io_in
put[3]:0 peri.tr_io_
output[0]:2 peri.tr_io_
output[1]:2 cpuss.swj_
trstn
P1.2
scb[7].uart
_rts:0 scb[7].spi_
clk:0
P1.3
P1.4
P1.5
tcpwm[0].li
ne_compl[
4]:4 tcpwm[0].li
ne[5]:4 tcpwm[0].li
ne_compl[
5]:4 tcpwm[1].lin
e_compl[12
]:1 tcpwm[1].lin
e[13]:1 tcpwm[1].lin
e_compl[14
]:1 scb[7].uart
_cts:0 scb[7].spi_
select0:0 scb[7].spi_
select1:0 scb[7].spi_
select2:0
P5.0
tcpwm[0].li
ne[4]:0 tcpwm[1].lin
e[4]:0 scb[5].uart
_rx:0 scb[5].i2c
_scl:0 scb[5].spi_
mosi:0 audioss.clk
_i2s_if peri.tr_io_in
put[10]:0
P5.1
P5.2
tcpwm[0].li
ne_compl[
4]:0 tcpwm[0].li
ne[5]:0 tcpwm[1].lin
e_compl[4]:
0 tcpwm[1].lin
e[5]:0 scb[5].uart
_tx:0 scb[5].uart
_rts:0 scb[5].i2c
_sda:0 scb[5].spi_
miso:0 scb[5].spi_
clk:0 audioss.tx
_sck audioss.tx
_ws peri.tr_io_in
put[11]:0
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 28 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 8. Multiple Alternate Functions
[1]
(continued)
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
tcpwm[0].li
ne_compl[
5]:0 tcpwm[0].li
ne[6]:0 tcpwm[0].li
ne_compl[
6]:0 tcpwm[0].li
ne[7]:0 tcpwm[0].li
ne_compl[
7]:0 tcpwm[0].li
ne[0]:1 tcpwm[1].lin
e_compl[5]:
0 tcpwm[1].lin
e[6]:0 tcpwm[1].lin
e_compl[6]:
0 tcpwm[1].lin
e[7]:0 tcpwm[1].lin
e_compl[7]:
0 tcpwm[1].lin
e[8]:0 scb[8].i2
c_scl:0 scb[5].uart
_cts:0 scb[3].uart
_rx:0 scb[3].i2c
_scl:0 scb[5].spi_
select0:0 scb[5].spi_
select1:0 scb[5].spi_
select2:0 scb[5].spi_
select3:0 scb[3].spi_
select3:0 scb[3].spi_
mosi:0 audioss.tx
_sdo audioss.rx
_sck audioss.rx
_ws audioss.rx
_sdi cpuss.fault
_out[0] scb[8].spi
_mosi:0
P6.1
P6.2
P6.3
P6.4
tcpwm[0].li
ne_compl[
0]:1 tcpwm[0].li
ne[1]:1 tcpwm[0].li
ne_compl[
1]:1 tcpwm[0].li
ne[2]:1 tcpwm[1].lin
e_compl[8]:
0 tcpwm[1].lin
e[9]:0 tcpwm[1].lin
e_compl[9]:
0 tcpwm[1].lin
e[10]:0 scb[8].i2
c_sda:0 scb[8].i2
c_scl:1 scb[3].uart
_tx:0 scb[3].uart
_rts:0 scb[3].uart
_cts:0 scb[6].uart
_rx:2 scb[3].i2c
_sda:0 scb[6].i2c
_scl:2 scb[3].spi_
miso:0 scb[3].spi_
clk:0 scb[3].spi_
select0:0 scb[6].spi_
mosi:2 cpuss.fault
_out[1] peri.tr_io_in
put[12]:0 peri.tr_io_
output[0]:1 cpuss.swj_
swo_tdo scb[8].spi
_miso:0 scb[8].spi
_clk:0 scb[8].spi
_select0:0 scb[8].spi
_mosi:1
P6.5
P6.6
P6.7
tcpwm[0].li
ne_compl[
2]:1 tcpwm[0].li
ne[3]:1 tcpwm[0].li
ne_compl[
3]:1 tcpwm[0].li
ne[4]:1 tcpwm[1].lin
e_compl[10
]:0 tcpwm[1].lin
e[11]:0 tcpwm[1].lin
e_compl[11]
:0 tcpwm[1].lin
e[12]:0 scb[8].i2
c_sda:1 scb[6].uart
_tx:2 scb[6].uart
_rts:2 scb[6].uart
_cts:2 scb[6].i2c
_sda:2 scb[6].spi_
miso:2 scb[6].spi_
clk:2 scb[6].spi_
select0:2 peri.tr_io_in
put[13]:0 peri.tr_io_
output[1]:1 cpuss.swj_
swdoe_tdi cpuss.swj_
swdio_tms cpuss.swj_
swclk_tclk scb[8].spi
_miso:1 scb[8].spi
_clk:1 scb[8].spi
_select0:1
P7.0
scb[4].uart
_rx:1 scb[4].i2c
_scl:1 scb[4].spi_
mosi:1 peri.tr_io_in
put[14]:0 cpuss.trac
e_clock
P7.1
P7.2
tcpwm[0].li
ne_compl[
4]:1 tcpwm[0].li
ne[5]:1 tcpwm[1].lin
e_compl[12
]:0 tcpwm[1].lin
e[13]:0 scb[4].uart
_tx:1 scb[4].uart
_rts:1 scb[4].i2c
_sda:1 scb[4].spi_
miso:1 scb[4].spi_
clk:1 peri.tr_io_in
put[15]:0
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 29 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 8. Multiple Alternate Functions
[1]
(continued)
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P7.3
tcpwm[0].li
ne_compl[
5]:1 tcpwm[1].lin
e_compl[13
]:0 scb[4].uart
_cts:1 scb[4].spi_
select0:1
P7.4
P7.5
P7.6
tcpwm[0].li
ne[6]:1 tcpwm[0].li
ne_compl[
6]:1 tcpwm[0].li
ne[7]:1 tcpwm[1].lin
e[14]:0 tcpwm[1].lin
e_compl[14
]:0 tcpwm[1].lin
e[15]:0 scb[4].spi_
select1:1 scb[4].spi_
select2:1 scb[4].spi_
select3:1 bless.ext_lna_rx_ctl_out bless.ext_p
a_tx_ctl_out cpuss.trace_
data[3]:2 cpuss.trace_
data[2]:2 bless.ext_p
a_lna_chip_en_o ut cpuss.trace_
data[1]:2
P7.7
P8.0
P8.1
P8.2
tcpwm[0].li
ne_compl[
7]:1 tcpwm[0].li
ne[0]:2 tcpwm[0].li
ne_compl[
0]:2 tcpwm[0].li
ne[1]:2 tcpwm[1].lin
e_compl[15
]:0 tcpwm[1].lin
e[16]:0 tcpwm[1].lin
e_compl[16
]:0 tcpwm[1].lin
e[17]:0 scb[4].uart
_rx:0 scb[4].uart
_tx:0 scb[4].uart
_rts:0 scb[4].i2c
_scl:0 scb[4].i2c
_sda:0 scb[3].spi_
select1:0 scb[4].spi_
mosi:0 scb[4].spi_
miso:0 scb[4].spi_
clk:0 cpuss.clk_
fm_pump peri.tr_io_in
put[16]:0 peri.tr_io_in
put[17]:0 cpuss.trace_
data[0]:2
P8.3
P8.4
P8.5
P8.6
P8.7
tcpwm[0].li
ne_compl[
1]:2 tcpwm[0].li
ne[2]:2 tcpwm[0].li
ne_compl[
2]:2 tcpwm[0].li
ne[3]:2 tcpwm[0].li
ne_compl[
3]:2 tcpwm[0].li
ne[4]:2 tcpwm[1].lin
e_compl[17
]:0 tcpwm[1].lin
e[18]:0 tcpwm[1].lin
e_compl[18
]:0 tcpwm[1].lin
e[19]:0 tcpwm[1].lin
e_compl[19
]:0 tcpwm[1].lin
e[20]:0 scb[4].uart
_cts:0 scb[4].spi_
select0:0 scb[4].spi_
select1:0 scb[4].spi_
select2:0 scb[4].spi_
select3:0 scb[3].spi_
select2:0
P9.0
scb[2].uart
_rx:0 scb[2].i2c
_scl:0 scb[2].spi_
mosi:0 peri.tr_io_in
put[18]:0 cpuss.trace_
data[3]:0
P9.1
tcpwm[0].li
ne_compl[
4]:2 tcpwm[1].lin
e_compl[20
]:0 scb[2].uart
_tx:0 scb[2].i2c
_sda:0 scb[2].spi_
miso:0 peri.tr_io_in
put[19]:0 cpuss.trace_
data[2]:0
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 30 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 8. Multiple Alternate Functions
[1]
(continued)
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P10.0
tcpwm[0].li
ne[5]:2 tcpwm[0].li
ne_compl[
5]:2 tcpwm[0].li
ne[7]:5 tcpwm[0].li
ne_compl[
7]:5 tcpwm[0].li
ne[0]:6 tcpwm[0].li
ne_compl[
0]:6 tcpwm[0].li
ne[6]:2 tcpwm[1].lin
e[21]:0 tcpwm[1].lin
e_compl[21
]:0 tcpwm[1].lin
e[0]:2 tcpwm[1].lin
e_compl[0]:
2 tcpwm[1].lin
e[1]:2 tcpwm[1].lin
e_compl[1]:
2 tcpwm[1].lin
e[22]:0 scb[2].uart
_rts:0 scb[2].uart
_cts:0 scb[1].uart
_rx:1 scb[1].i2c
_scl:1 scb[2].spi_
clk:0 scb[2].spi_
select0:0 scb[2].spi_
select1:0 scb[2].spi_
select2:0 scb[2].spi_
select3:0 scb[1].spi_
mosi:1 pass.dsi_c
tb_cmp0:1 pass.dsi_c
tb_cmp1:1 peri.tr_io_in
put[20]:0 cpuss.trace_
data[1]:0 cpuss.trace_
data[0]:0 cpuss.trace_
data[3]:1
P10.1
P10.2
P10.3
P10.4
tcpwm[0].li
ne_compl[
6]:2 tcpwm[0].li
ne[7]:2 tcpwm[0].li
ne_compl[
7]:2 tcpwm[0].li
ne[0]:3 tcpwm[1].lin
e_compl[22
]:0 tcpwm[1].lin
e[23]:0 tcpwm[1].lin
e_compl[23
]:0 tcpwm[1].lin
e[0]:1 scb[1].uart
_tx:1 scb[1].uart
_rts:1 scb[1].uart
_cts:1 scb[1].i2c
_sda:1 scb[1].spi_
miso:1 scb[1].spi_
clk:1 scb[1].spi_
select0:1 scb[1].spi_
select1:1 audioss.p
dm_clk peri.tr_io_in
put[21]:0 cpuss.trace_
data[2]:1 cpuss.trace_
data[1]:1 cpuss.trace_
data[0]:1
P10.5
P10.6
P10.7
tcpwm[0].li
ne_compl[
0]:3 tcpwm[0].li
ne[1]:6 tcpwm[0].li
ne_compl[
1]:6 tcpwm[1].lin
e_compl[0]:
1 tcpwm[1].lin
e[2]:2 tcpwm[1].lin
e_compl[2]:
2 scb[1].spi_
select2:1 scb[1].spi_
select3:1 audioss.p
dm_data
P11.0
tcpwm[0].li
ne[1]:3 tcpwm[1].lin
e[1]:1 smif.spi_
select2 scb[5].uart
_rx:1 scb[5].i2c
_scl:1 scb[5].spi_
mosi:1 peri.tr_io_in
put[22]:0
P11.1
tcpwm[0].li
ne_compl[
1]:3 tcpwm[1].lin
e_compl[1]:
1 smif.spi_
select1 scb[5].uart
_tx:1 scb[5].i2c
_sda:1 scb[5].spi_
miso:1 peri.tr_io_in
put[23]:0
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 31 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 8. Multiple Alternate Functions
[1]
(continued)
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P11.2
P11.3
P11.4
P11.5
tcpwm[0].li
ne[2]:3 tcpwm[0].li
ne_compl[
2]:3 tcpwm[0].li
ne[3]:3 tcpwm[0].li
ne_compl[
3]:3 tcpwm[1].lin
e[2]:1 tcpwm[1].lin
e_compl[2]:
1 tcpwm[1].lin
e[3]:1 tcpwm[1].lin
e_compl[3]:
1 smif.spi_
select0 smif.spi_
data3 smif.spi_
data2 smif.spi_
data1 scb[5].uart
_rts:1 scb[5].uart
_cts:1 scb[5].spi_
clk:1 scb[5].spi_
select0:1 scb[5].spi_
select1:1 scb[5].spi_
select2:1 peri.tr_io_
output[0]:0 peri.tr_io_
output[1]:0
P11.6
P11.7
smif.spi_
data0 smif.spi_
clk smif.spi_
data4 scb[6].uart
_rx:0 scb[5].spi_
select3:1
P12.0
P12.1
P12.2
tcpwm[0].li
ne[4]:3 tcpwm[0].li
ne_compl[
4]:3 tcpwm[0].li
ne[5]:3 tcpwm[1].lin
e[4]:1 tcpwm[1].lin
e_compl[4]:
1 tcpwm[1].lin
e[5]:1 smif.spi_
data5 scb[6].uart
_tx:0 smif.spi_
data6 scb[6].uart
_rts:0 scb[6].i2c
_scl:0 scb[6].i2c
_sda:0 scb[6].spi_
mosi:0 scb[6].spi_
miso:0 scb[6].spi_
clk:0 peri.tr_io_in
put[24]:0 peri.tr_io_in
put[25]:0
P12.3
P12.4
P12.5
tcpwm[0].li
ne_compl[
5]:3 tcpwm[0].li
ne[6]:3 tcpwm[0].li
ne_compl[
6]:3 tcpwm[0].li
ne[7]:3 tcpwm[1].lin
e_compl[5]:
1 tcpwm[1].lin
e[6]:1 tcpwm[1].lin
e_compl[6]:
1 tcpwm[1].lin
e[7]:1 smif.spi_
data7 smif.spi_
select3 scb[6].uart
_cts:0 scb[6].spi_
select0:0 scb[6].spi_
select1:0 scb[6].spi_
select2:0 audioss.p
dm_clk audioss.p
dm_data
P12.6
scb[6].spi_
select3:0
P12.7
P13.0
tcpwm[0].li
ne_compl[
7]:3 tcpwm[0].li
ne[0]:4 tcpwm[1].lin
e_compl[7]:
1 tcpwm[1].lin
e[8]:1 scb[6].uart
_rx:1 scb[6].i2c
_scl:1 scb[6].spi_
mosi:1 peri.tr_io_in
put[26]:0
P13.1
tcpwm[0].li
ne_compl[
0]:4 tcpwm[1].lin
e_compl[8]:
1 scb[6].uart
_tx:1 scb[6].i2c
_sda:1 scb[6].spi_
miso:1 peri.tr_io_in
put[27]:0
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 32 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 8. Multiple Alternate Functions
[1]
(continued)
Port/
Pin
ACT #0 ACT #1 DS #2 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #12 ACT #13 ACT #14 ACT #15 DS #4 DS #5 DS #6
P13.2
P13.3
P13.4
tcpwm[0].li
ne[1]:4 tcpwm[0].li
ne_compl[
1]:4 tcpwm[0].li
ne[2]:4 tcpwm[1].lin
e[9]:1 tcpwm[1].lin
e_compl[9]:
1 tcpwm[1].lin
e[10]:1 scb[6].uart
_rts:1 scb[6].uart
_cts:1 scb[6].spi_
clk:1 scb[6].spi_
select0:1 scb[6].spi_
select1:1
P13.5
P13.6
P13.7
tcpwm[0].li
ne_compl[
2]:4 tcpwm[0].li
ne[3]:4 tcpwm[0].li
ne_compl[
3]:4 tcpwm[1].lin
e_compl[10
]:1 tcpwm[1].lin
e[11]:1 tcpwm[1].lin
e_compl[11]
:1 scb[6].spi_
select2:1 scb[6].spi_
select3:1
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisation of on-chip resources.
Document Number: 002-28630 Rev. *I Page 33 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
P14.1
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P0.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P14.0
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
Analog, Smart I/O, and DSI alternate Port Pin functionality is provided in
.
Table 9. Port Pin Analog, Smart I/O, and DSI Functions
Port/Pin
P0.0
P0.1
P0.2
P0.3
P0.4
Name
P0.0
P0.1
P0.2
P0.3
P0.4
Analog wco_in wco_out
Digital HV DSI dsi[0].port_if[0] dsi[0].port_if[1] dsi[0].port_if[2] dsi[0].port_if[3] dsi[0].port_if[4] pmic_wakeup_in hibernate_wakeup[1] pmic_wakeup_out
USBDM
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P0.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
USBDP
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
lpcomp.inp_comp0
lpcomp.inn_comp0
lpcomp.inp_comp1
lpcomp.inn_comp1
hibernate_wakeup[0] dsi[0].port_if[5] dsi[1].port_if[0] dsi[1].port_if[1] dsi[1].port_if[2] dsi[1].port_if[3] dsi[1].port_if[4] dsi[1].port_if[5] dsi[3].port_if[0] dsi[3].port_if[1] dsi[3].port_if[2] dsi[3].port_if[3] dsi[3].port_if[4] dsi[3].port_if[5] dsi[3].port_if[6] dsi[3].port_if[7] dsi[4].port_if[0] dsi[4].port_if[1] dsi[4].port_if[2] dsi[4].port_if[3] dsi[4].port_if[4]
P6.5
P6.5
dsi[4].port_if[5]
P6.6
P6.7
P7.0
P7.1
P6.6
P6.7
P7.0
P7.1
swd_data swd_clk dsi[4].port_if[6] dsi[4].port_if[7] dsi[5].port_if[0] dsi[5].port_if[1]
P7.2
P7.2
csd.cmodpadd
csd.cmodpads
csd.csh_tankpadd
csd.csh_tankpads
csd.vref_ext
dsi[5].port_if[2]
P7.3
P7.4
P7.5
P7.6
P7.7
P7.3
P7.4
P7.5
P7.6
P7.7
csd.cshieldpads
dsi[5].port_if[3] dsi[5].port_if[4] dsi[5].port_if[5] dsi[5].port_if[6] dsi[5].port_if[7]
SMARTIO USB usb.usb_dp_pad
usb.usb_dm_pad
Document Number: 002-28630 Rev. *I Page 34 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
Table 9. Port Pin Analog, Smart I/O, and DSI Functions
(continued)
Port/Pin
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
Name
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
Analog ctb_oa0+ ctb_oa0ctb_oa0_out
Digital HV
P9.3
P9.4
P9.5
P9.6
P9.7
P9.3
P9.4
P9.5
P9.6
P9.7
ctb_oa1_out ctb_oa1ctb_oa1+ ctb_oa0+ ctb_oa1+ or ext_vref sarmux[0] sarmux[1] sarmux[2] sarmux[3] sarmux[4] sarmux[5] sarmux[6] sarmux[7] eco_in eco_out
DSI SMARTIO dsi[11].port_if[0] smartio[8].io[0] dsi[11].port_if[1] smartio[8].io[1] dsi[11].port_if[2] smartio[8].io[2] dsi[11].port_if[3] smartio[8].io[3] dsi[11].port_if[4] smartio[8].io[4] dsi[11].port_if[5] smartio[8].io[5] dsi[11].port_if[6] smartio[8].io[6] dsi[11].port_if[7] smartio[8].io[7] dsi[10].port_if[0] smartio[9].io[0] dsi[10].port_if[1] smartio[9].io[1] dsi[10].port_if[2] smartio[9].io[2] dsi[10].port_if[3] smartio[9].io[3] dsi[10].port_if[4] smartio[9].io[4] dsi[10].port_if[5] smartio[9].io[5] dsi[10].port_if[6] smartio[9].io[6] dsi[10].port_if[7] smartio[9].io[7] dsi[9].port_if[0] dsi[9].port_if[1] dsi[9].port_if[2] dsi[9].port_if[3] dsi[9].port_if[4] dsi[9].port_if[5] dsi[9].port_if[6] dsi[9].port_if[7] dsi[8].port_if[0] dsi[8].port_if[1] dsi[8].port_if[2] dsi[8].port_if[3] dsi[8].port_if[4] dsi[8].port_if[5] dsi[8].port_if[6] dsi[8].port_if[7] dsi[7].port_if[0] dsi[7].port_if[1] dsi[7].port_if[2] dsi[7].port_if[3] dsi[7].port_if[4] dsi[7].port_if[5] dsi[7].port_if[6] dsi[7].port_if[7] dsi[6].port_if[0]
Document Number: 002-28630 Rev. *I
USB
Page 35 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 9. Port Pin Analog, Smart I/O, and DSI Functions
(continued)
Port/Pin
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
Name
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
Analog Digital HV DSI dsi[6].port_if[1] dsi[6].port_if[2] dsi[6].port_if[3] dsi[6].port_if[4] dsi[6].port_if[5] dsi[6].port_if[6] dsi[6].port_if[7]
SMARTIO USB
Document Number: 002-28630 Rev. *I Page 36 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Power Supply Considerations
The following power system diagrams show typical connections for power pins for all supported packages.
In these diagrams, the package pin is shown with the pin name, for example "V
DDA by that pin is also shown, for example "V
DDD
, A13; I/O port P1".
, M13". For V
DDx
pins, the I/O port that is powered
Figure 14. 124-BGA Power Connection Diagram
1.7 to 3.6 V
1 KΩ at
100 MHz
10 µF
1 µF
0.1 µF
0.1 µF
1 µF
1 µF
0.1 µF
0.1 µF
1 KΩ at
100 MHz
1 µF
10 µF
0.1 µF
0.1 µF
1 µF
1 µF
CYB06447BZI-BLDx, 124-BGA package
V
DD_NS
, A5 V
DDD
, A13; I/O port P1
V
BACKUP
, A10; I/O port P0
V
DDIO0
, D11; I/O ports P11, P12, P13
V
DDIO1
, M4; I/O ports P5, P6, P7, P8
V
DDUSB
, A2; I/O port P14
V
DDA
, M13
V
DDIOA
, N13; I/O ports P9, P10
V
BUCK1
, C4
V
CCD
, B13
V
IND1
, B5
V
IND2
, B4
DV
DD
, F2
V
DDR_HVL
, G3
V
RF
, A4
V
DCDC
, F3
V
DDR1
, C2
V
DDR2
, E2
V
DDR3
, D2
C11, D4, D10, K4, K10, M12
V
SS
A1, B1, B2, C3, D1, E3, G2
V
SSR
0.1 µF
1 KΩ at
100 MHz
10 µF
4.7 µF
2.2 µH
0.1 µF
0.1 µF
0.1 µF
10 µF
1 KΩ at
100 MHz
1 µF
1 µF
0.1 µF 1 µF
Document Number: 002-28630 Rev. *I Page 37 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Figure 15. 116-BGA Power Connection Diagram
1.7 to 3.6 V
1 KΩ at
100 MHz
10 µF
1 µF
1 µF
0.1 µF
0.1 µF
0.1 µF
1 KΩ at
100 MHz
1 µF
10 µF
0.1 µF
0.1 µF
1 µF
1 µF
CYB06447BZI-BLDx, 116-BGA package
V
DD_NS
, H3 V
DDD
, B1; I/O port P1
V
BACKUP
, C1; I/O port P0
V
DDIO0
, B3; I/O ports P11, P12, P13
V
DDIO1
, G10; I/O ports P5, P6, P7, P8
V
DDA
, A9; I/O ports P9, P10
V
BUCK1
, G2
V
CCD
, A2
V
IND1
, F1
V
IND2
, G1
0.1 µF
1 KΩ at
100 MHz
10 µF
4.7 µF
2.2 µH
0.1 µF
DV
V
DD
, M6
DDR_HVL
, L7
B2, B9, D1, H2, H9
V
SS
V
RF
, H1
V
DCDC
, M7
V
DDR1
, L2
V
DDR2
, M1
V
DDR3
, M2
J1, K2, K3, K4, K5, L1, L3, L4, L5, M3, M8
V
SSR
0.1 µF
0.1 µF
10 µF
1 KΩ at
100 MHz
1 µF
1 µF
0.1 µF 1 µF
There are as many as eight V package, and multiple V
SS
DDx
supply pins, depending on the
ground pins. The power pins are:
■
V
DDD
: the main digital supply. It powers the low dropout (LDO) regulator and I/O port 1.
.
■
V
CCD
: the main LDO output. It requires a 4.7-µF capacitor for regulation. The LDO can be turned off when V from the switching regulator (see V technical reference manual (TRM) .
BUCK1
CCD
is driven
below). For more information, see the power system block diagram in the device
■
V
DDA
: the supply for the analog peripherals. Voltage must be applied to this pin for correct device initialization and boot up.
■
V
DDIOA
: the supply for I/O ports 9 and 10. If it is present in the device package, it must be connected to V
DDA
.
■
V
DDIO0
: the supply for I/O ports 11, 12, and 13.
■
V
DDIO1
: the supply for I/O ports 5, 6, 7, and 8.
Document Number: 002-28630 Rev. *I Page 38 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
■
V
BACKUP
: the supply for the backup domain, which includes the
32-kHz WCO and the RTC. It can be a separate supply as low as 1.4 V, for battery or supercapacitor backup, as
shows. Otherwise it is connected to V
DDD
. It powers I/O port 0.
Figure 16. Separate Battery Connection to V
BACKUP
1.7 to 3.6 V
1.4 to 3.6 V
10 µF
1 µF
0.1 µF
0.1 µF
V
V
DDD
BACKUP
■ V
DDUSB
: the supply for the USB peripheral and the USBDP and
USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If
USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can be used as limited-capability GPIOs on I/O port 14.
shows a summary of the I/O port supplies:
Table 10. I/O Port Supplies
Port
0
1
5, 6, 7, 8
9, 10
11, 12, 13
14
Supply
V
BACKUP
V
DDD
V
DDIO1
V
DDIOA
V
DDIO0
V
DDUSB
Alternate Supply
V
DDD
-
-
V
DDA
-
-
Note: If the USB pins are not used, connect V nected.
DDUSB
to ground and leave the P14.0/USBDP and P14.1/USBDM pins uncon-
Voltage must be applied to the V
DDD
pin, and the V
DDA
pin as noted above, for correct device initialization and operation. If an
I/O port is not being used, applying voltage to the corresponding
V
DDx
pin is optional.
■
V
SS
and V
SSR
: ground pins for the above supplies. All ground pins should be connected together to a common ground.
In addition to the LDO regulator, a single input multiple output
(SIMO) switching regulator is included. It provides two regulated outputs using a single inductor. The regulator pins are:
■
V
DD_NS
: the regulator supply.
■
V
IND1
and V
IND2
: the inductor and capacitor connections.
■
V
BUCK1
V
CCD
: the first regulator output. It is typically used to drive
, see above
■
V
RF
: the second regulator output. It is typically used to drive the Bluetooth LE radio power pins: V
DCDC
and V
DDRx
.
A set of power pins for the Bluetooth LE radio are included. They are:
■
V
DCDC
: the radio digital supply.
■
V
DDR1
, V
DDR2
, and V
DDR3
: the radio analog supplies.
■
D
VDD
: the radio digital LDO output. It requires a 1-µF capacitor for regulation.
■
V
DDR_HVL
: the radio analog LDO output. It requires a 1-µF capacitor for regulation.
The various V
DD
power pins are not connected together on chip.
They can be connected off chip, in one or more separate nets. If separate power nets are used, they can be isolated from noise from the other nets using optional ferrite beads, as indicated in the diagrams.
No external load should be placed on V regulator is used.
CCD
, V
RF
, or any of the switching regulator power pins; whether or not the switching
There are no power pin sequencing requirements; power supplies may be brought up in any order. The power management system holds the device in reset until all power pins are at the voltage levels required for proper operation.
Note: If a battery is installed on the PCB first, V battery during product manufacture and storage.
DDD
must be cycled for at least 50 µs. This prevents premature drain of the
Bypass capacitors must be connected to a common ground from the V
DDx
and other pins, as indicated in the diagrams. Typical practice for systems in this frequency range is to use a 10-µF or
1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated for optimal bypassing.
All capacitors and inductors should be ±20% or better. The capacitor connected to V
IND2
should be 100 nF. The recommended inductor value is 2.2 µH ±20% (for example, TDK
MLP2012H2R2MT0S1).
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the applied voltage is a significant percentage of the rated working voltage.
For more information on pad layout, refer to PSoC 6 CAD libraries .
Document Number: 002-28630 Rev. *I Page 39 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Electrical Specifications
All specifications are valid for –40 °C ≤ T
A
≤ 85 °C and for 1.71 V to 3.6 V except where noted.
Note: These are preliminary and subject to change.
Absolute Maximum Ratings
Table 11. Absolute Maximum Ratings
Spec ID#
SID1
SID2
SID3
SID4
SID5
SID3A
SID3B
SID4A
SID4B
SID4C
SID5A
V
V
Parameter
DD_ABS
CCD_ABS
V
GPIO_ABS
I
GPIO_ABS
I
GPIO_injection
ESD_HBM
Description
Analog or digital supply relative to V
(V
SSD
= V
SSA
)
SS
Direct digital core voltage input relative to V
SSD
GPIO voltage; V
DDD
or V
DDA
Current per GPIO
GPIO injection current per pin
Electrostatic discharge Human Body
Model
ESD_HBM_ANT Electrostatic discharge Human Body
Model; Antenna Pin
Min
–0.5
–0.5
–0.5
–25
–0.5
2200
500
ESD_CDM Electrostatic discharge Charged
Device Model
ESD_CDM_ANT Electrostatic discharge Charged
Device Model; Antenna Pin
ESD_CDM_X
LU
500
200
Electrostatic discharge Charged
Device Model; XI, XO pins
200
Pin current for latchup-free operation –100
Typ
–
–
–
–
–
–
–
Max
4
1.2
Unit
V
V
– V
DD
+ 0.5
V
– 25 mA
– 0.5
mA
– – V
–
–
–
–
100
V
V
V
V mA
Details / Conditions
RF pin
RF pin
XI, XO Pins
Device-Level Specifications
provides detailed specifications of CPU current. Table 12
summarizes these specifications, for rapid review of CPU currents under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.
Table 12. CPU Current Specifications Summary
Condition
LP Mode, V
DDD
= 3.3 V, V
CCD
= 1.1 V, with buck regulator
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
Range
Across CPUs clock ranges: 8–150/100 MHz; Dhrystone with flash cache enabled
CM0+ sleep, CM4 off
Minimum regulator current mode Across CM4/CM0+ CPU active/sleep modes
ULP Mode, V
DDD
= 3.3 V, V
CCD
= 0.9 V, with buck regulator
CM4 active, CM0+ sleep
Typ Range
0.9–6.9 mA
0.8–3.8 mA
0.7–1.5 mA
0.7–1.3 mA
0.6–0.7 mA
Max Range
1.5–8.6 mA
1.3–4.5 mA
1.3–2.2 mA
1.3–2 mA
1.1–1.1 mA
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
Across CPUs clock ranges: 8 – 50/25 MHz; Dhrystone with flash cache enabled
0.65–1.6 mA 0.8–2.2mA
0.51–0.91 mA 0.72–1.25 mA
0.42–0.76 mA
0.41–0.62 mA
0.65–1.1 mA
0.6–0.9 mA
Minimum regulator current mode
Deep Sleep
Across CM4/CM0+ CPU active/sleep modes
Across SRAM retention
0.39–0.54 mA
7–9 µA
0.6–0.76 mA
-
Hibernate Across V
DDD
300–800 nA -
Note
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-28630 Rev. *I Page 40 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Figure 17. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode
8
7
6
5
4
3
CM4 Active, CM0+ Sleep 1/2 CM4
CM4 Active, CM0+ Sleep same as CM4
CM0+ Active, CM4 Sleep
2
1
0
0 25 50 75
CPU Clock, MHz
Power Supplies
Table 13. Power Supply DC Specifications
Spec ID# Parameter
SID6 V
DDD
Description
Internal regulator and Port 1 GPIO supply
SID7
SID7A
SID7B
SID7D
SID7F
V
V
V
V
V
DDA
DDIO1
DDIO0
DDIOA
DDUSB
Analog power supply voltage.
Shorted to V
DDIOA
on PCB.
GPIO supply for ports 5 to 8 when present
GPIO supply for ports 11 to 13 when present
GPIO supply for ports 9 and 10 when present. Must be connected to V on PCB.
DDA
Supply for port 14 (USB or GPIO) when present
SID6B
SID8
SID9
SID10
SID11
V
V
V
C
C
BACKUP
CCD1
CCD2
EFC
EXC
Min
1.7
1.7
1.7
1.7
1.7
1.7
Backup power and GPIO Port 0 supply when present
1.7
Output voltage (for core logic bypass) –
Output voltage (for core logic bypass) –
External regulator voltage (V
CCD bypass
)
Power supply decoupling capacitor
3.8
–
Typ
–
–
–
–
–
–
–
1.1
0.9
4.7
10
100
Max Unit
3.6
V –
3.6
3.6
3.6
3.6
3.6
3.6
–
–
5.6
–
µ
µ
V
V
Internally unregulated supply
Must be ≥ V
DDA
if the CapSense
(CSD) block is used in the application
V –
V
V
V
V
V
–
125
Details / Conditions
Min. supply is 2.85 V for USB
Min. is 1.4 V when V
System LP mode
150
DDD
is removed.
ULP mode. Valid for –20 to 85 °C.
F X5R ceramic or better;
F X5R ceramic or better
Note
3. CM4 Active, CM0+ Sleep 1/2 CM4 trace values are higher because above 100 MHz, the PLL must be used instead of the FLL.
Document Number: 002-28630 Rev. *I Page 41 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
CPU Current and Transition Times
Table 14. CPU Current and Transition Times
Spec ID# Parameter Description Min Typ Max Unit
LP RANGE POWER SPECIFICATIONS (for V
CCD
= 1.1 V with Buck and LDO)
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
2.3
3.2
SIDF1 I
DD1
Execute from Flash; CM4 Active
50 MHz,
CM0+ Sleep 25 MHz.
With IMO & FLL. While(1).
–
SIDF2 I
DD2
Execute from Flash; CM4 Active
8 MHz, CM0+ Sleep 8 MHz. With
IMO. While(1).
Execute with Cache Enabled
SIDC1
SIDC2
SIDC3
SIDC4 I
I
I
I
DD3
DD4
DD5
DD6
Execute from Cache; CM4 Active
150 MHz, CM0+ Sleep 75 MHz.
IMO & PLL. Dhrystone.
Execute from Cache;
CM4 Active 100 MHz, CM0+ Sleep
100 MHz. IMO & FLL. Dhrystone.
Execute from Cache; CM4 Active
50 MHz, CM0+ Sleep 25 MHz. IMO
& FLL. Dhrystone
Execute from Cache; CM4 Active
8 MHz, CM0+ Sleep 8 MHz. IMO.
Dhrystone.
–
–
–
–
–
–
–
–
–
–
–
–
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
–
–
–
–
–
SIDF3
SIDF4 I
I
DD7
DD8
Execute from Flash;
CM4 Off, CM0+ Active 50 MHz.
With IMO & FLL. While (1).
Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).
–
–
–
–
–
–
3.1
5.7
0.9
1.2
2.8
6.9
10.9
13.7
13.7
15.5
4.8
7.4
11.3
2.4
3.7
6.3
0.9
1.3
3
2.4
3.2
5.6
0.8
1.1
2.60
3.6
6.5
1.5
1.6
3.5
8.6
5.8
8.4
12
3.4
4.1
7.2
1.5
1.8
3.8
3.3
3.7
6.3
1.5
1.6
3.4
mA V
DDD
Details / Conditions mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD mA
V
V
DDD
DDD mA V
DDD mA V
DDD mA V mA V mA V
DDD
DDD
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
Document Number: 002-28630 Rev. *I Page 42 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 14. CPU Current and Transition Times
(continued)
Spec ID# Parameter
Execute with Cache Enabled
Description Min Typ Max Unit
3.8
4.5
SIDC5 I
DD9
Execute from Cache;
CM4 Off, CM0+ Active 100 MHz.
With IMO & FLL. Dhrystone.
–
SIDC6 I
DD10
Execute from Cache;
CM4 Off, CM0+ Active 8 MHz.
With IMO. Dhrystone.
Cortex M4. Sleep Mode
SIDS1
SIDS2
SIDS3 I
I
I
DD11
DD12
DD13
CM4 Sleep 100 MHz;
CM0+ Sleep 25 MHz. With IMO &
FLL.
CM4 Sleep 50 MHz;
CM0+ Sleep 25 MHz. With IMO &
FLL.
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
Cortex M0+. Sleep Mode
SIDS4
SIDS5 I
I
DD14
DD15
CM4 Off, CM0+ Sleep 50 MHz.
With IMO & FLL.
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
–
–
–
–
–
–
Cortex M4. Minimum Regulator Current Mode
SIDLPA1
SIDLPA2 I
I
DD16
DD17
Execute from Flash; CM4 LPA 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While (1).
Execute from Cache; CM4 LPA 8
MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
–
–
–
–
–
–
Cortex M0+. Minimum Regulator Current Mode
–
–
–
–
–
–
–
–
–
SIDLPA3 I
DD18
Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).
–
–
–
–
–
–
–
–
Document Number: 002-28630 Rev. *I
5.9
9
0.8
1.20
2.60
1.5
2.2
4
1.2
1.7
3.4
0.7
1
2.4
1.3
1.9
3.80
0.7
1
2.4
0.9
1.2
2.8
0.9
1.3
2.9
0.8
1.1
2.7
6.5
9.7
1.3
1.7
3.4
2.2
2.7
4.6
1.9
2.2
4.3
1.3
1.5
3.3
2
2.4
4.6
1.3
1.5
3.3
1.5
1.7
3.5
1.5
1.8
3.7
1.4
1.6
3.6
mA
V
V
DDD
DDD
Details / Conditions mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V mA V
DDD mA V
DDD mA V mA V
DDD mA V
DDD mA mA V
DDD mA V
DDD mA = 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C mA
V
V
DDD
DDD
DDD
DDD mA V
DDD mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
= 3.3 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 1.8 to 3.3 V, LDO, Max at 85 °C
Page 43 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 14. CPU Current and Transition Times
(continued)
Spec ID# Parameter
SIDLPA4 I
DD19
Description
Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
Min Typ Max Unit
–
–
–
0.8
1.2
2.7
1.4
1.7
3.6
mA V
DDD
Details / Conditions
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C
Cortex M4. Minimum Regulator Current Mode
SIDLPS1 I
DD20
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
–
–
–
0.7
1
2.4
1.1
1.5
3.3
mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C
Cortex M0+. Minimum Regulator Current Mode
SIDLPS3 I
DD22
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
–
–
0.6
0.9
1.1
1.5
mA V mA V
DDD
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
– 2.4
3.3
mA V
DDD
= 1.8 to 3.3 V, LDO, Max at 85 °C
ULP RANGE POWER SPECIFICATIONS (for V
CCD
= 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
SIDF5 I
DD3
Execute from Flash; CM4 Active 50
MHz, CM0+ Sleep 25 MHz.
With IMO & FLL. While(1).
– 1.7
2.2
SIDF6
Execute with Cache Enabled
SIDC8
I
I
DD4
DD10
Execute from Flash; CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While (1)
Execute from Cache; CM4 Active
50 MHz, CM0+ Sleep 25 MHz.
With IMO & FLL. Dhrystone.
–
–
–
–
2.1
0.56
0.75
1.6
2.4
0.8
1
2.2
mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C
–
–
–
2.4
0.65
0.8
2.7
0.8
1.1
mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C
SIDC9
SIDF7 I
I
DD11
DD16
Execute from Cache; CM4 Active 8
MHz, CM0+ Sleep 8 MHz.
With IMO. Dhrystone.
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
Execute from Flash; CM4 Off,
CM0+ Active 25 MHz. With IMO &
FLL. Write(1).
SIDF8 I
DD17
Execute from Flash; CM4 Off,
CM0+ Active 8 MHz. With IMO.
While(1).
Execute with Cache Enabled
SIDC10 I
DD18
Execute from Cache; CM4 Off,
CM0+ Active 25 MHz. With IMO &
FLL. Dhrystone.
SIDC11 I
DD19
Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
–
–
–
–
–
–
–
–
1
0.91
1.34
1.4
1.34
1.6
0.54
0.75
0.73
1
1.25
1.6
0.51
0.72
0.73
0.95
mA mA
V mA V mA V mA V
V mA V mA V mA V
DDD
DDD
DDD
DDD
DDD
DDD
DDD
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
Document Number: 002-28630 Rev. *I Page 44 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 14. CPU Current and Transition Times
(continued)
Spec ID# Parameter
Cortex M4. Sleep Mode
Description Min Typ Max Unit
SIDS7
SIDS8 I
I
DD21
DD22
CM4 Sleep 50 MHz, CM0+ Sleep
25 MHz. With IMO & FLL.
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
Cortex M0+. Sleep Mode
–
–
–
–
0.76
1.1
0.42
0.59
1.1
1.4
0.65
0.8
Details / Conditions mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C
SIDS9 I
DD23
CM4 Off, CM0+ Sleep 25 MHz.
With IMO & FLL.
–
–
–
–
0.62
0.88
0.41
0.58
0.9
1.1
0.6
0.8
mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C
SIDS10 I
DD24
CM4 Off, CM0+ Sleep 8 MHz.
With IMO.
Cortex M4. Minimum Regulator Current Mode
SIDLPA5 I
DD25
Execute from Flash. CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While(1).
SIDLPA6 I
DD26
Execute from Cache. CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
Cortex M0+. Minimum Regulator Current Mode
SIDLPA7 I
DD27
Execute from Flash. CM4 Off,
CM0+ Active 8 MHz. With IMO.
While (1).
–
–
–
–
–
–
–
–
0.52
0.76
0.78
0.75
1
0.54
0.76
1
0.51
0.75
0.75
0.48
0.7
1
0.7
0.95
mA mA V mA V mA V mA
V
V mA V
DDD
DDD
DDD
DDD
DDD
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C mA V
DDD
= 3.3 V, Buck ON, Max at 60 °C mA V
DDD
= 1.8 V, Buck ON, Max at 60 °C
SIDLPA8 I
DD28
Execute from Cache. CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
Cortex M4. Minimum Regulator Current Mode
SIDLPS5 I
DD29
CM4 Sleep 8 MHz, CM0 Sleep 8
MHz.
With IMO.
Cortex M0+. Minimum Regulator Current Mode
SIDLPS7 I
DD31
T
HIB_ACT
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
Deep Sleep Mode
SIDDS2 I
DD33B
With internal buck enabled and
160K SRAM retention
Hibernate Mode
SIDHIB1 I
DD34
SIDHIB2 I
DD34A
V
V
DDD
DDD
= 1.8 V
= 3.3 V
Power Mode Transition Times
SID12
T
LPACT_AC
T
Minimum regulator current to LP transition time
SID13 T
DS_LPACT
Deep Sleep to LP transition time
SID14 Hibernate to LP transition time
–
–
–
–
–
–
–
–
–
–
0.4
0.57
0.39
0.56
11
300
800
–
–
500
0.6
0.8
0.6
0.8
–
–
–
35
25
– mA mA
µA nA nA
µs
µs
µs
V mA V
V mA V
DDD
DDD
DDD
DDD
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
= 3.3 V, Buck ON, Max at 60 °C
= 1.8 V, Buck ON, Max at 60 °C
No clocks running
No clocks running
Including PLL lock time
Guaranteed by design
Including PLL lock time
Document Number: 002-28630 Rev. *I Page 45 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
XRES
Table 15. XRES DC Specifications
Spec ID# Parameter
SID17 T
XRES_IDD
SID17A T
XRES_IDD_1
SID77 V
IH
Description
IDD when XRES asserted
IDD when XRES asserted
Input voltage high threshold
SID78 V
IL
Input voltage low threshold
SID80
SID81
SID82
C
IN
V
HYSXRES
I
DIODE
Input capacitance
Input voltage hysteresis
Current through protection diode to
V
DD
/V
SS
Min Typ Max Unit
–
–
0.7 ×
V
DD
–
300
800
–
–
–
–
– nA V
DDD
= 1.8 V nA V
DDD
= 3.3 V
V CMOS Input
V
Details / Conditions
CMOS Input
–
–
3
100
0.3 ×
V
DD
–
– pF mV
–
–
– – 100 µA –
Table 16. XRES AC Specifications
Spec ID# Parameter
SID15 T
XRES_ACT
SID16 T
XRES_PW
Description
Time from XRES release to
Cortex-M0+ executing application code
XRES Pulse width
Min
–
5
Typ
750
–
GPIO
Table 17. GPIO DC Specifications
Spec ID#
SID57
SID57A
V
IH
I
IHS
Parameter
SID58 V
IL
Description
Input voltage high threshold
Input current when Pad > V
DDIO for OVT inputs
Input voltage low threshold
Min
0.7 × V
DD
–
–
Max
–
–
Typ
–
–
–
Unit
µs
Max
–
10
Not minimum regulator current mode; Cortex-M0+ executing at
50 MHz
µs –
Unit
V
Details / Conditions
CMOS Input
µA Per I
2
C Spec
V
Details / Conditions
CMOS Input
SID241
SID242
SID243
SID244
SID59
SID62A
SID63
SID64
SID65
SID65A
SID66
SID67
I
I
V
V
V
V
V
V
R
R
IH
IL
IH
IL
OH
OL
IL
PULLUP
PULLDOWN
IL_CTBM
C
IN
V
HYSTTL
LVTTL input, V
LVTTL input, V
SID68 V
HYSCMOS
Document Number: 002-28630 Rev. *I
DD
DD
< 2.7 V
< 2.7 V
LVTTL input, V
DD
≥ 2.7 V
LVTTL input, V
DD
≥ 2.7 V
Output voltage high level
Output voltage low level
Pull-up resistor
Pull-down resistor
Input leakage current (absolute value)
Input leakage on CTBm input pins
Input Capacitance
Input hysteresis LVTTL V
DD
2.7 V
>
Input hysteresis CMOS
0.7 × V
V
DD
–
2.0
–
–
3.5
3.5
–
–
–
100
DD
– 0.5
0.05 × V
DD
–
–
–
–
–
–
5.6
5.6
–
–
–
0
–
–
0.4
8.5
8.5
2
0.3 ×
V
DD
–
0.3 ×
V
DD
–
0.8
4
5
–
–
V
V
V
V
V
V kΩ nA mV
–
–
–
–
I
OH
= 8 mA
I
OL
= 8 mA kΩ –
– nA 25 °C, V
– pF – mV –
–
DD
= 3.0 V
Page 46 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 17. GPIO DC Specifications
(continued)
Spec ID#
SID69
SID69A I
I
Parameter
DIODE
TOT_GPIO
Description
Current through protection diode to V
DD
/V
SS
Maximum total source or sink
Chip Current
Min
–
–
Typ
–
–
Max
100
200
Unit
µ A – mA –
Details / Conditions
Table 18. GPIO AC Specifications
Spec ID#
SID70 T
Parameter
RISEF
SID71
SID72
T
T
FALLF
RISES_1
Description
Rise time in Fast Strong Mode.
10% to 90% of V
DD
Fall time in Fast Strong Mode.
10% to 90% of V
DD
Rise time in Slow Strong Mode.
10% to 90% of V
DD
SID72A T
RISES_2
Rise time in Slow Strong Mode.
10% to 90% of V
DD
SID73 T
FALLS_1
SID73A
SID73G
SID74
SID75
SID76
T
T
F
FALLS_2
FALL_I2C
GPIOUT1
F
GPIOUT2
F
GPIOUT3
Min
–
–
52
48
Fall time in Slow Strong Mode.
10% to 90% of V
DD
Fall time in Slow Strong Mode.
10% to 90% of V
DD
44
42
Fall time (30% to 70% of V
DD
Slow Strong mode
) in
GPIO Fout. Fast Strong mode.
20 × V
DDIO
5.5
/
–
GPIO Fout; Slow Strong mode.
GPIO Fout; Fast Strong mode.
–
–
Typ
–
–
–
–
–
–
–
–
–
–
SID245
SID246
F
GPIOUT4
F
GPIOIN
GPIO Fout; Slow Strong mode.
GPIO input operating frequency;1.71 V V
DD
3.6 V
–
–
–
–
Max
2.5
2.5
142
102
211
93
250
100
16.7
7
3.5
100
Unit Details / Conditions ns Cload = 15 pF, 8 mA drive strength ns Cload = 15 pF, 8 mA drive strength ns Cload = 15 pF, 8 mA drive strength,
V
DD
2.7 V ns Cload = 15 pF, 8 mA drive strength, 2.7 V <
V
DD
3.6 V ns Cload = 15 pF, 8 mA drive strength,
V
DD
2.7 V ns Cload = 15 pF, 8 mA drive strength,
2.7 V < V
DD
3.6 V ns Cload = 10 pF to 400 pF,
8-mA drive strength
MHz 90/10%, 15-pF load,
60/40 duty cycle
MHz 90/10%, 15-pF load,
60/40 duty cycle
MHz 90/10%, 25-pF load,
60/40 duty cycle
MHz 90/10%, 25-pF load,
60/40 duty cycle
MHz 90/10% V
IO
Document Number: 002-28630 Rev. *I Page 47 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SID288
SID288A
SID288B
SID290
SID290A
SID290B
SID291
SID292
SID65A
Analog Peripherals
Opamp
Table 19. Opamp Specifications
Spec ID#
SID269
SID270
SID271
SID272
SID273
SID274
SID275
SID276
SID277
SID278
SID279
SID280
I
I
I
Parameter
I
DD
I
DD_HI
I
DD_MED
I
DD_LOW
GBW
G
BW_HI
G
BW_MED
G
BW_LO
I
OUT_MAX
I
OUT_MAX_HI
I
OUT_MAX_MID
I
OUT_MAX_LO
I
OUT
OUT_MAX_HI
OUT_MAX_MID
OUT_MAX_LO
Description
Opamp block current. No load.
Power = Hi
Power = Med
Power = Lo
Load = 50 pF, 0.1 mA.
V
DDA
2.7 V
Power = Hi
Power = Med
Power = Lo
V
DDA
2.7 V, 500 mV from rail
Power = Hi
Power = Med
Power = Lo
V
DDA
= 1.71 V, 500 mV from rail
Power = Hi
Power = Med
Power = Lo
SID281 V
IN
Input voltage range
SID282
SID283
SID284
SID285
SID286
V
CM
V
OUT
V
OUT_1
V
OUT_2
V
OUT_3
V
OUT_4
V
OS_TR
V
OS_TR
V
OS_TR
V
OS_DR_TR
V
OS_DR_TR
V
OS_DR_TR
CMRR
PSRR
I
IL_CTBM
Input common mode voltage
V
DDA
≥ 2.7 V
Power = Hi, Iload = 10 mA
Power = Hi, Iload = 1 mA
Power = Med, Iload = 1 mA
Power = Lo, Iload = 0.1 mA
Offset voltage
Offset voltage
Offset voltage
Offset voltage drift
Offset voltage drift
Offset voltage drift
DC common mode rejection ratio
Power supply rejection ratio at
1 kHz, 10-mV ripple
Input leakage on CTBm input pins
10
10
–
–
6
3
1
–
4
4
–
0
Min
–
–
–
–
–
0
–
0.5
0.2
0.2
0.2
–
–
67
70
–
–1
–
–
–10
±10
±10
80
85
–
–
–
5
–
–
–
–
–
–
–
2
–
Typ
–
Max
–
1300 1500
450 600
250 350
– –
–
–
–
–
–
–
–
–
–
V
DDA
0.2
–
V
DDA
1.5
–
–
V
DDA
0.5
–
V
DDA
0.2
–
V
DDA
0.2
–
V
DDA
0.2
–
–
–
–
–
–
–
–
–
1 ±0.5
±1
±2
±3
–
–
–
–
–
–
10
4
Unit
–
µA –
µA –
µA –
–
Details / Conditions
MHz –
MHz –
MHz –
– mA – mA – mA –
– mA – mA – mA –
V
Charge pump ON
V
V
Charge pump OFF,
V
DDA
2.7 V
–
–
V
–
V
–
V
– mV
Power = Hi, 0.2 V < V
OUT
< (V
DDA
- 0.2 V) mV Power = Med mV Power = Lo
µV/°C
Power = Hi, 0.2 V < V
OUT
< (V
DDA
- 0.2 V)
µV/°C Power = Med
µV/°C Power = Lo dB V
DDA
≥ 2.7 V dB V
DDA
≥ 2.7 V nA –
Document Number: 002-28630 Rev. *I Page 48 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 19. Opamp Specifications
(continued)
Spec ID#
Noise
Parameter Description
SID293
SID294
SID295
SID296
SID297
VN1
VN2
VN3
VN4
CLOAD
Input-referred, 1 Hz – 1 GHz, power = Hi
Input-referred, 1 kHz, power = Hi
Input-referred, 10 kHz, power = Hi
Input-referred, 100 kHz, power = Hi
Stable up to max. load.
Performance specs at 50 pF.
SID298 SLEW_RATE Output slew rate
SID299
SID300
SID301
SID302
SID303
T_OP_WAKE
COMP_MODE
T
PD1
T
PD2
T
PD3
V
HYST_OP
From disable to enable, no external RC dominating
Comparator mode; 50-mV overdrive, Trise = Tfall (approx.)
Response time; power = Hi
Response time; power = Med
Response time; power = Lo
Hysteresis
Deep Sleep Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1 I
DD_HI_M1
SID_DS_2 I
DD_MED_M1
SID_DS_3 I
DD_LOW_M1
SID_DS_4 I
DD_HI_M2
SID_DS_5 I
DD_MED_M2
SID_DS_6 I
DD_LOW_M2
SID_DS_7 GBW_HI_M1
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
Mode 1, High current
SID_DS_8 GBW_MED_M1 Mode 1, Medium current
SID_DS_9 GBW_LOW_M1 Mode 1, Low current
SID_DS_10 GBW_HI_M2 Mode 2, High current
SID_DS_11 GBW_MED_M2 Mode 2, Medium current
SID_DS_12 GBW_LOW_M2 Mode 2, Low current
SID_DS_13 V
OS_HI_M1
SID_DS_14 V
OS_MED_M1
SID_DS_15 V
OS_LOW_M1
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Document Number: 002-28630 Rev. *I
Min
–
–
–
–
–
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ Max Unit Details / Conditions
100
180
–
–
µVrms – nV/rtHz –
70 – nV/rtHz –
38
–
–
25
150
400
2000
10
1300 1500
460 600
230
120
350
–
60
15
4
2
0.5
–
–
–
–
–
0.5
–
0.2
0.1
5
5
5
–
–
–
–
–
–
125
–
– nV/rtHz – pF
–
V/µs
µs
Cload = 50 pF,
Power = Hi, V
DDA
2.7 V
Refer to
.
–
–
–
–
–
–
– ns – ns – ns – mV –
Deep Sleep mode operation: V
V
IN
DDA
is 0.2 to V
DDA
≥ 2.7 V.
–1.5 V
µA Typ at 25 °C
µA Typ at 25 °C
µA Typ at 25 °C
µA 25 °C
µA 25 °C
µA 25 °C
MHz 25 °C
MHz 25 °C
MHz 25 °C
MHz
MHz
MHz mV
20-pF load, no DC load
0.2 V to V
DDA
– 1.5 V
20-pF load, no DC load
0.2 V to V
DDA
– 1.5 V
20-pF load, no DC load
0.2 V to V
DDA
– 1.5 V
25 °C, 0.2 V to V
DDA
1.5 V
– mV mV
25 °C, 0.2 V to V
DDA
1.5 V
–
25 °C, 0.2 V to V
DDA
1.5 V
–
Page 49 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 19. Opamp Specifications
(continued)
Spec ID# Parameter Description
SID_DS_16 V
OS_HI_M2
Mode 2, High current
Mode 2, Medium current SID_DS_17 V
OS_MED_M2
SID_DS_18 V
OS_LOW_M2
Mode 2, Low current
Mode 1, High current SID_DS_19 I
OUT_HI_M1
SID_DS_20 I
OUT_MED_M1
SID_DS_21 I
OUT_LOW_M1
SID_DS_22 I
OUT_HI_M2
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
SID_DS_23 I
OUT_MED_M2
SID_DS_24 I
OUT_LOW_M2
Mode 2, Medium current
Mode 2, Low current
Figure 18. Opamp Step Response, Rising
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.25
0
Input
Output, Power = Hi
Output, Power = Med
0.25
Time, µs
0.5
0.75
1
Min
–
–
–
–
–
–
–
–
–
Typ
5
5
5
10
10
4
1
1
0.5
Max
–
–
–
–
–
–
–
–
–
Unit mV mV mV mA mA mA mA mA mA
Details / Conditions
25 °C, 0.2 V to V
DDA
1.5 V
–
25 °C, 0.2 V to V
DDA
1.5 V
–
25 °C, 0.2 V to V
DDA
1.5 V
–
Output is 0.5 V to V
DDA
0.5 V
–
Output is 0.5 V to
V
DDA
– 0.5 V
Output is 0.5 V to V
DDA
0.5 V
–
Output is 0.5 V to V
DDA
0.5 V
–
Output is 0.5 V to V
DDA
0.5 V
–
Output is 0.5 V to V
DDA
0.5 V
–
Figure 19. Opamp Step Response, Falling
1.4
1.2
1
Input
Output, Power = Hi
Output, Power = Med
0.8
0.6
0.4
0.2
0
-0.25
0 0.25
Time. µs
0.5
0.75
1
Document Number: 002-28630 Rev. *I Page 50 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Low-Power (LP) Comparator
Table 20. LP Comparator DC Specifications
Spec ID#
SID84
SID85A
SID85B
SID86
SID86A
SID87
SID247
SID247A
SID88
SID89
SID248
SID259
SID90
I
I
I
V
V
V
V
V
V
V
V
Parameter
OFFSET1
OFFSET2
OFFSET3
HYST1
HYST2
ICM1
ICM2
ICM3
CMRR
CMP1
CMP2
CMP3
ZCMP
Description
Input offset voltage for COMP1.
Normal power mode.
Input offset voltage. Low-power mode.
Input offset voltage. Ultra low-power mode.
Hysteresis when enabled in
Normal mode
Hysteresis when enabled in
Low-power mode
Min
–10
–25
–25
–
–
Input common mode voltage in
Normal mode
Input common mode voltage in
Low power mode
0
0
Input common mode voltage in
Ultra low power mode
Common mode rejection ratio in
Normal power mode
Block Current, Normal mode –
Block Current, Low power mode –
Block Current in Ultra low-power mode
DC Input impedance of comparator
0
50
–
35
Typ
–
±12
±12
–
–
Max
10
–
–
–
0.3
– V
DDIO1
– 0.1
– V
DDIO1
– 0.1
– V
DDIO1
– 0.1
–
150
10
0.85
–
25
25
60
80
–
Unit Details / Conditions mV COMP0 offset is ±25 mV mV
– mV
– mV
– mV
–
V
–
V
–
V
– dB
MΩ
–
µA –
µA –
µA
–
–
Table 21. LP Comparator AC Specifications
Spec ID#
SID91
SID258
SID92
T
T
T
Parameter
RESP1
RESP2
RESP3
Description
Response time, Normal mode,
100 mV overdrive
Response time, Low power mode, 100 mV overdrive
Response time, Ultra-low power mode, 100 mV overdrive
SID92E
SID92F
T_CMP_EN1
T_CMP_EN2
Time from Enabling to operation
Time from Enabling to operation
Min
–
–
–
–
–
Typ
–
–
–
–
–
Table 22. Temperature Sensor Specifications
Spec ID#
SID93 T
Parameter
SENSACC
Description
Temperature sensor accuracy
Table 23. Internal Reference Specification
Spec ID#
SID93R V
Parameter
REFBG
Description
–
Document Number: 002-28630 Rev. *I
Min
–5
Min
1.188
Typ
±1
Typ
1.2
Max
100
1000
20
10
50
Max
5
Max
1.212
Unit
°C
Unit
–
Details / Conditions ns ns
–
µs
–
µs
Normal and Low-power modes
µs Ultra low-power mode
Details / Conditions
–40 to +85 °C
Unit
V –
Details / Conditions
Page 51 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SAR ADC
Table 24. 12-bit SAR ADC DC Specifications
Spec ID# Parameter
SID94 A_RES
SID95 A_CHNLS_S
Description
SAR ADC Resolution
Number of channels - single-ended
SID96 A-CHNKS_D
SID97 A-MONO
SID98 A_GAINERR
SID99 A_OFFSET
SID100 A_ISAR_1
SID100A A_ISAR_2
SID101 A_VINS
SID102 A_VIND
SID103 A_INRES
SID104 A_INCAP
Number of channels - differential
Monotonicity
Gain error
Input offset voltage
Min
–
–
Current consumption at 1 Msps –
Current consumption at 1 Msps.
Reference = V
DD
–
Input voltage range - single-ended V
SS
Input voltage range - differential V
SS
Input resistance –
Input capacitance –
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
Max
12
16
8
–
±0.2
2
1
1.25
V
DDA
V
DDA
2.2
10
Unit bits –
–
Details / Conditions
8 full speed.
–
Diff inputs use neighboring
I/O
Yes –
% With external reference.
mV Measured with 1-V reference mA mA
At 1 Msps. External Bypass
Cap.
At 1 Msps. External Bypass
Cap.
V
V kΩ – pF –
–
–
Table 25. 12-bit SAR ADC AC Specifications
Spec ID# Parameter Description
12-bit SAR ADC AC Specifications
SID106 A_PSRR Power supply rejection ratio
SID107 A_CMRR Common mode rejection ratio
One Megasample per second mode:
SID108 A_SAMP_1
SID108A
SID108B
SID109
A_SAMP_2
A_SAMP_3
A_SINAD
Sample rate with external reference bypass cap.
Sample rate with no bypass cap;
Reference = V
DD
Sample rate with no bypass cap.
Internal reference.
Signal-to-noise and Distortion ratio
(SINAD). V
1 Msps.
DDA
= 2.7 to 3.6 V,
SID111A A_INL
SID111B A_INL
Integral Non Linearity.
V
DDA
= 2.7 to 3.6 V, 1 Msps
Integral Non Linearity.
V
DDA
= 2.7 to 3.6 V, 1 Msps
Min
70
66
–
–
–
64
–2
–4
SID112A A_DNL –1
SID112B
SID113
A_DNL
A_THD
Differential Non Linearity.
V
DDA
= 2.7 to 3.6 V, 1 Msps
Differential Non Linearity.
V
DDA
= 2.7 to 3.6 V, 1 Msps
Total harmonic distortion.
V
DDA
= 2.7 to 3.6 V, 1 Msps.
–1
–
Document Number: 002-28630 Rev. *I
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
2
4
1.4
1.7
–65
Unit dB –
Details / Conditions dB Measured at 1 V.
1
250
100
–
Msps – ksps – ksps – dB Fin = 10 kHz
LSB dB
Measured with internal
V
V
REF
REF
= 1.2 V and bypass cap.
LSB Measured with external
≥ 1 V and V mode < 2 * Vref.
Fin = 10 kHz
IN
common
LSB Measured with internal
V
REF
= 1.2 V and bypass cap.
LSB Measured with external
V
REF
≥ 1 V and V
IN
common mode < 2 * Vref.
Page 52 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
DAC
Table 26. 12-bit DAC DC Specifications
Spec ID# Parameter
SID108D DAC_RES
SID111D DAC_INL
Description
DAC resolution
Integral non-linearity
SID112D DAC_DNL Differential non-linearity
SID99D DAC_OFFSET Output Voltage zero offset error
SID103D DAC_OUT_RES DAC Output Resistance
SID100D DAC_IDD DAC Current
SID101D DAC_QIDD DAC Current when DAC stopped
Min
–
–4
–2
–2
–
–
–
Typ
–
–
15
–
–
–
–
Max
12
4
2
1
–
125
1
Unit bits –
LSB –
Details / Conditions
LSB Monotonic to 11 bits.
mV For 000 (hex) k Ω –
µA –
µA –
Table 27. 12-bit DAC AC Specifications
Spec ID# Parameter
SID109D DAC_CONV
Description
DAC Settling time
SID110D DAC_Wakeup Time from Enabling to ready for conversion
CSD
Table 28. CapSense Sigma-Delta (CSD) Specifications
Spec ID# Parameter
CSD V2 Specifications
SYS.PER#3 V
DD_RIPPLE
Description
Max allowed ripple on power supply, DC to 10 MHz
Min
–
–
SYS.PER#16
SID308
SID308A
SID309
SID310
SID311
SID312
I
I
V
SID.CSD#15A V
V
DD_RIPPLE_1.8
SID.CSD.BLK I
CSD
SID.CSD#15 V
REF
REF_EXT
SID.CSD#16 I
DAC1IDD
SID.CSD#17 I
DAC2IDD
CSD
V
COMPIDAC
DAC1DNL
DAC1INL
I
DAC2DNL
I
DAC2INL
Max allowed ripple on power supply, DC to 10 MHz
Maximum block current
Voltage reference for CSD and
Comparator
External Voltage reference for
CSD and Comparator
IDAC1 (7-bits) block current
IDAC2 (7-bits) block current
Voltage range of operation
Voltage compliance range of
IDAC
DNL
INL
DNL
INL
Typ
–
–
Min Typ
–
–
0.6
0.6
–
–
1.7
0.6
–1
–3
–1
–3
Max
2
10
Max
Unit
µs
Unit
Details / Conditions
µs Driving through CTBm buffer;
25-pF load
–
Details / Conditions
–
–
±50
±25 mV V
DDA
> 2 V (with ripple), 25 °C
T
A
,
Sensitivity = 0.1 pF mV V
DDA
> 1.75 V (with ripple),
25 ° C T tance (C
≥ 0.4 pF
A
P
, Parasitic Capaci-
) < 20 pF, Sensitivity
µA –
V V
DDA
– V
REF
≥ 0.6 V
4500
1.2
V
DDA
0.6
–
V
DDA
0.6
–
–
–
1900
1900
–
–
– 3.6
– V
DDA
0.6
–
1
3
–
–
1
3
V
µA
µA
V
V
–
–
DDA
– V
REF
1.71 to 3.6 V
V V
DDA
– V
REF
≥ 0.6 V
≥ 0.6 V
LSB –
LSB If V
DDA
< 2 V then for LSB of
2.4 µA or less
LSB –
LSB If V
DDA
< 2 V then for LSB of
2.4 µA or less
Document Number: 002-28630 Rev. *I Page 53 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 28. CapSense Sigma-Delta (CSD) Specifications
(continued)
Spec ID# Parameter Description Min Typ Max Unit
SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization
SID313_1A SNRC_1 5 – –
Details / Conditions
Ratio 9.5-pF max. capacitance
SID313_1B SNRC_2
SRSS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity
SRSS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity
5 – – Ratio 31-pF max. capacitance
SID313_1C SNRC_3 5 – – Ratio 61-pF max. capacitance
SID313_2A
SID313_2B
SID313_2C
SNRC_4
SNRC_5
SNRC_6
SRSS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity
PASS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity
PASS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity
PASS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity
5
5
5
–
–
–
–
–
–
Ratio 12-pF max. capacitance
Ratio 47-pF max. capacitance
Ratio 86-pF max. capacitance
SID313_3A SNRC_7 5 – – Ratio 27-pF max. capacitance
SID313_3B
SID313_3C
SID314
SID314A
SID314B
SID314C
SID314D
SID314E
SID315 I
I
I
I
I
I
I
SNRC_8
SNRC_9
DAC1CRT1
DAC1CRT2
DAC1CRT3
DAC1CRT12
DAC1CRT22
DAC1CRT32
DAC2CRT1
PASS Reference. IMO + PLL
Clock Source. 0.1-pF sensitivity
PASS Reference. IMO + PLL
Clock Source. 0.3-pF sensitivity
PASS Reference. IMO + PLL
Clock Source. 0.6-pF sensitivity
Output current of IDAC1 (7 bits) in low range
Output current of IDAC1(7 bits) in medium range
Output current of IDAC1(7 bits) in high range
Output current of IDAC1 (7 bits) in low range, 2X mode
Output current of IDAC1(7 bits) in medium range, 2X mode
Output current of IDAC1(7 bits) in high range, 2X mode. V
2 V
DDA
>
Output current of IDAC2 (7 bits) in low range
5
5
4.2
33.7
270
8
67
540
4.2
–
–
–
–
5.7
45.6
365
11.4
91
730
5.7
Ratio 86-pF max. capacitance
Ratio 168-pF max. capacitance
µA
µA
µA
µA
µA
µA
µA
LSB = 37.5-nA typ
LSB = 300-nA typ.
LSB = 2.4-µA typ.
LSB = 37.5-nA typ.
2X output stage
LSB = 300-nA typ.
2X output stage
LSB = 2.4-µA typ.
2X output stage
LSB = 37.5-nA typ.
SID315A
SID315B
SID315C
SID315D
SID315E
SID315F I
I
I
I
I
I
DAC2CRT2
DAC2CRT3
DAC2CRT12
DAC2CRT22
DAC2CRT32
DAC3CRT13
Output current of IDAC2 (7 bits) in medium range
Output current of IDAC2 (7 bits) in high range
Output current of IDAC2 (7 bits) in low range, 2X mode
Output current of IDAC2(7 bits) in medium range, 2X mode
Output current of IDAC2(7 bits) in high range, 2X mode. V
2 V
DDA
>
Output current of IDAC in 8-bit mode in low range
33.7
270
8
67
540
8
45.6
365
11.4
91
730
11.4
µA LSB = 300-nA typ.
µA
µA
µA
µA
µA
LSB = 2.4-µA typ.
LSB = 37.5-nA typ.
2X output stage
LSB = 300-nA typ.
2X output stage
LSB = 2.4-µA typ.
2X output stage
LSB = 37.5-nA typ.
Document Number: 002-28630 Rev. *I Page 54 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 28. CapSense Sigma-Delta (CSD) Specifications
(continued)
Spec ID#
SID315G
SID315H
SID320
SID321
SID322
SID322A
SID322B
SID323
SID324
SID325
I
I
I
I
I
I
I
Parameter
DAC3CRT23
DAC3CRT33
DACOFFSET
I
DACGAIN
I
DACMISMATCH1
DACMISMATCH2
DACMISMATCH3
DACSET8
DACSET7
CMOD
Description
Output current of IDAC in 8-bit mode in medium range
Output current of IDAC in 8-bit mode in high range. V
DDA
> 2V
All zeroes input
Full-scale error less offset
Mismatch between IDAC1 and
IDAC2 in Low mode
Mismatch between IDAC1 and
IDAC2 in Medium mode
Mismatch between IDAC1 and
IDAC2 in High mode
Settling time to 0.5 LSB for 8-bit
IDAC
Settling time to 0.5 LSB for 7-bit
IDAC
External modulator capacitor.
Min Typ
67
540
–
–
–
–
–
–
–
–
–
–
–
–
2.2
–
–
–
6
5.8
10
10
–
Max Unit
91
Details / Conditions
µA LSB = 300-nA typ.
730
1
±15
9.2
µA LSB = 2.4-µA typ.
LSB Polarity set by Source or Sink
% LSB = 2.4-µA typ.
LSB LSB = 37.5-nA typ.
LSB LSB = 300-nA typ.
LSB LSB = 2.4-µA typ.
µs Full-scale transition.
No external load.
µs Full-scale transition.
No external load.
nF 5-V rating, X7R or NP0 cap.
Table 29. CSD ADC Specifications
Spec ID# Parameter
CSDv2 ADC Specifications
SIDA94 A_RES
Description
Resolution
SID95
SIDA97
SIDA98
A_CHNLS_S
A-MONO
Number of channels - single ended
Monotonicity
A_GAINERR_VREF Gain error
SIDA98A
SIDA99
SIDA99A
SIDA100
A_GAINERR_VDDA Gain error
A_OFFSET_VREF
A_OFFSET_VDDA
A_ISAR_VREF
Input offset voltage
Input offset voltage
Current consumption
Document Number: 002-28630 Rev. *I
Min Typ Max Unit
–
–
–
–
–
–
–
–
–
–
–
0.6
0.2
0.5
0.5
0.3
10
–
Yes
–
–
–
–
–
Details / Conditions bits Auto-zeroing is required every millisecond
16 –
– V
REF
mode
% Reference Source: SRSS
(V
(V
REF
REF
= 1.20 V, V
2.7 V), (V
REF
2.7 V)
DDA
< 2.2 V),
= 1.6 V, 2.2 V < V
= 2.13 V, V
DDA
<
DDA
>
% Reference Source: SRSS
(V
REF
= 1.20 V, V
DDA
< 2.2V),
(V
REF
2.2 V < V
(V
REF
= 1.6 V,
DDA
< 2.7 V),
= 2.13 V, V
DDA
> 2.7 V)
LSB After ADC calibration, Ref. Src
= SRSS, (V
REF
= 1.20 V,
V
DDA
< 2.2 V), (V
2.2 V < V
DDA
REF
< 2.7 V),
(V
REF
= 2.13 V, V
DDA
= 1.6 V,
> 2.7 V)
LSB After ADC calibration, Ref.
Src = SRSS, (V
REF
= 1.20 V,
V
DDA
(V
< 2.2 V),
REF
= 1.6 V, 2.2 V < V
2.7 V),
(V
REF
= 2.13 V, V
DDA
<
DDA
> 2.7 V) mA CSD ADC Block current
Page 55 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 29. CSD ADC Specifications
(continued)
Spec ID# Parameter
SIDA100A A_ISAR_VDDA
SIDA101 A_VINS_VREF
SIDA101A A_VINS_VDDA
SIDA103 A_INRES
SIDA104 A_INCAP
SIDA106
SIDA107
SIDA108
A_PSRR
A_TACQ
SIDA108A A_CONV10
SIDA109
SIDA109A A_SND_VDDA
SIDA111
SIDA111A
SIDA112
SIDA112A
A_CONV8
A_SND_VRE
A_INL_VREF
A_INL_VDDA
A_DNL_VREF
A_DNL_VDDA
Description
Current consumption
Input voltage range - single ended
Input voltage range - single ended
Input charging resistance
Input capacitance
Power supply rejection ratio
(DC)
Sample acquisition time
Conversion time for 8-bit resolution at conversion rate =
Fhclk/(2"(N+2)). Clock frequency = 50 MHz.
Conversion time for 10-bit resolution at conversion rate =
Fhclk/(2"(N+2)). Clock frequency = 50 MHz.
Signal-to-noise and Distortion ratio (SINAD)
Signal-to-noise and Distortion ratio (SINAD)
Integral non-linearity. 11.6 ksps
Integral non-linearity. 11.6 ksps
Differential non-linearity.
11.6 ksps
Differential non- linearity.
11.6 ksps
Min Typ Max Unit
– 0.3
–
Details / Conditions mA CSD ADC Block current
V
SSA
– V
REF
V
SSA
–
–
–
–
15
41
60
V
DDA
–
–
–
V (V
REF
(V
REF
= 1.20 V, V
DDA
< 2.2 V),
= 1.6 V, 2.2 V < V
DDA
<
2.7 V),
(V
REF
= 2.13 V, V
DDA
> 2.7 V)
V (V
REF
(V
REF
= 1.20 V, V
DDA
< 2.2 V),
= 1.6 V, 2.2 V < V
DDA
<
2.7 V),
(V
REF
= 2.13 V, V
DDA
> 2.7 V) kΩ – pF – dB –
–
–
10
25
–
–
µs Measured with 50-Ω source impedance. 10 µs is default software driver acquisition time setting. Settling to within
0.05%.
µs Does not include acquisition time.
–
–
–
–
–
–
–
60
57
52
–
–
–
–
–
–
–
2
2
1
1
µs dB dB
Does not include acquisition time.
Measured with 50-Ω source impedance
Measured with 50-Ω source impedance
LSB Measured with 50-Ω source impedance
LSB Measured with 50-Ω source impedance
LSB Measured with 50-Ω source impedance
LSB Measured with 50-Ω source impedance
Document Number: 002-28630 Rev. *I Page 56 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Digital Peripherals
Table 30. Timer/Counter/PWM (TCPWM) Specifications
Spec ID# Parameter
SID.TCPWM.1
I
TCPWM1
SID.TCPWM.2
I
TCPWM2
SID.TCPWM.2A I
TCPWM3
SID.TCPWM.2B I
TCPWM4
Description
Block current consumption at
8 MHz
Block current consumption at
24 MHz
Block current consumption at
50 MHz
Block current consumption at
100 MHz
SID.TCPWM.3
TCPWM
FREQ
Operating frequency
Min Typ Max Unit
– – 70 µA
Details / Conditions
All modes (TCPWM)
–
–
–
–
–
–
–
–
180 µA All modes (TCPWM)
270 µA All modes (TCPWM)
540 µA All modes (TCPWM)
SID.TCPWM.4
TPWM
ENEXT
Input Trigger Pulse Width for all Trigger Events
2 / Fc –
SID.TCPWM.5
TPWM
EXT
SID.TCPWM.5A TC
RES
SID.TCPWM.5B PWM
RES
SID.TCPWM.5C Q
RES
Output Trigger Pulse widths
Resolution of Counter
PWM Resolution
1.5 /
Fc
–
1 / Fc –
1 / Fc –
Quadrature inputs resolution 2 / Fc –
100 MHz Fc max = Fcpu
–
–
– ns ns ns
Trigger Events can be Stop, Start,
Reload, Count, Capture, or Kill depending on which mode of operation is selected. Fc is counter operating frequency.
Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) trigger outputs
Minimum time between successive counts
– ns Minimum pulse width of PWM Output
– ns
Minimum pulse width between
Quadrature phase inputs. Delays from pins should be similar.
Table 31. Serial Communication Block (SCB) Specifications
Spec ID# Parameter
Fixed I
2
C DC Specifications
SID149 I
I2C1
Description
SID150
SID151 I
I
I2C2
I2C3
Block current consumption at
100 kHz
Block current consumption at
400 kHz
Block current consumption at
1 Mbps
SID152 I
I2C4
I2C enabled in Deep Sleep mode
Fixed I
2
C AC Specifications
SID153 F
I2C1
Fixed UART DC Specifications
Bit Rate
SID160 I
UART1
SID161 I
UART2
Block current consumption at
100 kbps
Block current consumption at
1000 kbps
Min Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
1
30
180
30
80
180
1.7
Unit
µ A –
µ A –
µ A –
µ A At 60 °C
Mbps –
µ
µ
A
A
–
–
Details / Conditions
Document Number: 002-28630 Rev. *I Page 57 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 31. Serial Communication Block (SCB) Specifications
(continued)
Spec ID# Parameter
Fixed UART AC Specifications
Bit Rate SID162A
SID162B
F
UART1
F
UART2
Fixed SPI DC Specifications
SID163 I
SPI1
Description
Block current consumption at
1 Mbps
Min Typ
–
–
–
–
–
–
Max
3
8
220
SID164
SID165 I
I
SPI2
SPI3
Block current consumption at
4 Mbps
Block current consumption at
8 Mbps
–
–
–
–
340
360
SID165A I
SP14
Block current consumption at
25 Mbps
– –
Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
800
Unit
Mbps ULP Mode
µ
µ
µ
µ
A
A
A
A
LP Mode
–
–
–
–
Details / Conditions
SID166 F
SPI
SPI Operating Frequency
Master and Externally
Clocked Slave
– – 25 MHz 14-MHz max for ULP (0.9 V) mode
SID166A F
SPI_IC
SPI Slave Internally Clocked – – 15 MHz 5-MHz max for ULP (0.9 V) mode
SID166B F
SPI_EXT
SPI Operating Frequency
Master (F
SCB
is SPI Clock)
– – F
SCB
/4 MHz F
Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SCB
max is 100 MHz in LP mode, 25
MHz max in ULP mode
SID167 T
DMO
– – 12 ns 20-ns max for ULP (0.9 V) mode
SID168
SID169
SID169A
T
T
T
DSI
HMO
SSELMSCK1
MOSI Valid after SClock driving edge
MISO Valid before SClock capturing edge
MOSI data hold time
SSEL Valid to first SCK Valid edge
5
0
18
–
–
–
–
–
– ns ns ns
Full clock, late MISO sampling
Referred to Slave capturing edge
Referred to Master clock edge
SID169B T
SSELMSCK2
SSEL Hold after last SCK
Valid edge
18 – – ns
Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
Referred to Master clock edge
SID170 T
DMI
5 – – ns –
SID171A T
DSO_EXT
MOSI Valid before Sclock
Capturing edge
MISO Valid after Sclock driving edge in Ext. Clk. mode
– – 20 ns 35-ns max. for ULP (0.9 V) mode
SID171
SID171B
SID172
SID172A
SID172B
T
DSO
T
T
DSO
HSO
TSSEL
TSSEL
SCK1
SCK2
MISO Valid after Sclock driving edge in Internally Clk.
Mode
–
MISO Valid after Sclock driving edge in Internally Clk.
Mode with Median filter enabled.
–
Previous MISO data hold time 5
SSEL Valid to first SCK Valid edge
65
SSEL Hold after Last SCK
Valid edge
65 –
–
–
– T
DSO_EXT
+
3 × Tscb
– T
DSO_EXT
+
4 × Tscb
–
–
– ns Tscb is Serial Comm. Block clock period. ns ns ns ns
Tscb is Serial Comm. Block clock period.
–
–
Document Number: 002-28630 Rev. *I Page 58 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
LCD Specifications
Table 32. LCD Direct Drive DC Specifications
Spec ID# Parameter
SID154 I
LCDLOW
SID155 C
LCDCAP
Description
Operating current in low-power mode
LCD capacitance per segment/common driver
SID156 LCD
OFFSET
SID157
SID158 I
I
LCDOP1
LCDOP2
Long-term segment offset
PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.
PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.
Min Typ Max Unit
– 5 –
Details / Conditions
µA 16 × 4 small segment display at 50 Hz
– 500 5000 pF –
–
–
–
20
0.6
0.5
–
–
– mV – mA
32 × 4 segments
50 Hz
Table 33. LCD Direct Drive AC Specifications
Spec ID# Parameter
SID159 F
LCD
Description
LCD frame rate
Min
10
Typ
50
Max
150
Unit
Hz –
Details / Conditions
Memory
Flash
Table 34. Flash DC Specifications
Spec ID#
SID173A I
PE
Parameter Description
Erase and program current
Min
–
Typ
–
Max
6
Unit mA –
Details / Conditions
Table 35. Flash AC Specifications
Spec ID#
SID179S T
Parameter
SID174 T
ROWWRITE
SID175 T
ROWERASE
SID176 T
ROWPROGRAM
SID178 T
BULKERASE
SID179 T
SECTORERASE
SID178S T
SSERIAE
SSWRITE
Description
Row write time (erase & program)
Row erase time
Row program time after erase
Bulk erase time (1024 KB)
Sector erase time (256 KB)
Subsector erase time
Subsector write time; 1 erase plus 8 program times
Min
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
Max
16
11
5
11
11
11
51
Unit ms ms ms ms ms ms ms
–
–
–
Details / Conditions
Row = 512 bytes
512 rows per sector
8 rows per subsector
–
SID180S T
SID180
SID181 F
SID182
T
F
SID182A F
SID182B F
SWRITE
DEVPROG
END
RET1
RET2
RET3
Sector write time; 1 erase plus 512 program times
Total device write time
Flash Endurance
Flash Retention. T
A cycles
25 °C, 100 k P/E
Flash Retention. T cycles
A
85 °C, 10 k P/E
Flash Retention. T
A cycles
55 °C, 20 k P/E
–
–
100 k
10
10
20
–
–
–
–
–
–
2.6
15
–
–
–
– seconds – seconds – cycles – years years years
–
–
–
SID256 T
WS100
SID257 T
WS50
Number of Wait states at 100 MHz
Number of Wait states at 50 MHz
3
2
–
–
–
–
–
–
Note
4. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-28630 Rev. *I Page 59 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
System Resources
Power-on-Reset
Table 36. Power-On-Reset (POR) with Brown-out Detect (BOD) DC Specifications
Spec ID# Parameter
SID190
SID192
V
V
FALLPPOR
FALLDPSLP
Description
BOD trip voltage in system LP and
ULP modes.
BOD trip voltage in system Deep
Sleep mode.
Min
1.54
1.54
Typ
–
–
Max
–
–
Table 37. POR with BOD AC Specifications
Spec ID# Parameter
SID192A V
SID194A V
DDRAMP
DDRAMP_DS
Description
Maximum power supply ramp rate
(any supply)
Maximum power supply ramp rate
(any supply) in system Deep Sleep mode
Voltage Monitors
Table 38. Voltage Monitors DC Specifications
Spec ID# Parameter
SID195R V
HVD0
SID195 V
HVDI1
SID196 V
HVDI2
SID197 V
HVDI3
SID198 V
HVDI4
SID199 V
HVDI5
SID200 V
HVDI6
SID201 V
HVDI7
SID202 V
HVDI8
SID203 V
HVDI9
SID204 V
HVDI10
SID205 V
HVDI11
SID206 V
HVDI12
SID207 V
HVDI13
SID208 V
HVDI14
SID209 V
HVDI15
SID211 LVI_IDD
Description
Block current
Min
–
–
Typ
–
–
Min Typ
1.18
1.23
1.38
1.43
1.57
1.63
1.76
1.83
1.95
2.03
2.05
2.13
2.15
2.23
2.24
2.33
2.34
2.43
2.44
2.53
2.53
2.63
2.63
2.73
2.73
2.83
2.82
2.93
2.92
3.03
3.02
3.13
– 5
10
2.41
2.51
2.61
2.72
2.82
2.92
3.03
3.13
3.23
15
Max
1.27
1.47
1.68
1.89
2.1
2.2
2.3
Unit
V
Details / Conditions
Reset guaranteed for V levels below 1.54 V
DDD
V
Max Unit Details / Conditions
100 mV/µs System LP mode mV/µs BOD operation guaranteed
V –
V –
V –
V –
V –
V –
V –
V –
V –
µA –
Unit
V –
V –
V –
V –
V –
V –
V –
Details / Conditions
Table 39. Voltage Monitors AC Specification
Spec ID#
SID212 T
Parameter
MONTRIP
Description
Voltage monitor trip time
Min
–
Typ
–
Max
170
Unit ns –
Details / Conditions
Document Number: 002-28630 Rev. *I Page 60 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SWD and Trace Interface
Table 40. SWD and Trace Specifications
Spec ID# Parameter Description
SID214 F_SWDCLK2 1.7 V V
DDD
3.6 V
Min
–
SID214L F_SWDCLK2L 1.7 V V
DDD
3.6 V
SID215 T_SWDI_SETUP T = 1/f SWDCLK
SID216 T_SWDI_HOLD T = 1/f SWDCLK
SID217 T_SWDO_VALID T = 1/f SWDCLK
SID217A T_SWDO_HOLD T = 1/f SWDCLK
SID214T F_TRCLK_LP1 With Trace Data setup/hold times of
SID215T F_TRCLK_LP2 With Trace Data setup/hold times of
SID216T F_TRCLK_ULP
With Trace Data setup/hold times of
3/2 ns respectively
–
0.25 * T
0.25 * T
–
1
–
–
–
Internal Main Oscillator
Table 41. IMO DC Specifications
Spec ID#
SID218 I
Parameter
IMO1
Description
IMO operating current at 8 MHz
Table 42. IMO AC Specifications
Spec ID# Parameter
SID223
SID227
F
T
IMOTOL1
JITR
Description
Frequency variation centered on
8 MHz
Cycle-to-Cycle and Period jitter
Internal Low-Speed Oscillator
Table 43. ILO DC Specification
Spec ID#
SID231 I
Parameter
ILO2
Description
ILO operating current at 32 kHz
Table 44. ILO AC Specifications
Spec ID# Parameter Description
ILO startup time SID234 T
STARTILO1
SID236 T
LIODUTY
SID237 F
ILOTRIM1
ILO Duty cycle
ILO frequency
Min
–
Min
–
–
Min
–
Min
–
45
28.8
Typ
–
Typ
9
Typ
–
±250
Typ
0.3
Typ
–
50
32
–
–
–
–
–
–
–
–
Max
15
Max
±2
–
Max
0.7
Max
7
55
36.1
Max
25
12
–
–
0.5 * T
–
75
70
25
Unit Details / Conditions
MHz
MHz
LP mode.
V
CCD
= 1.1 V
ULP mode.
V
CCD
= 0.9 V ns – ns – ns – ns –
MHz
MHz
MHz
LP Mode.
V
DD
= 1.1 V
LP Mode.
V
DD
= 1.1 V
ULP Mode.
V
DD
= 0.9 V
Unit
µA
Unit
% ps
Unit
µA
Unit
µs
–
–
–
–
Details / Conditions
Details / Conditions
Details / Conditions
Details / Conditions
Startup time to 95% of final frequency
% – kHz Factory trimmed
Document Number: 002-28630 Rev. *I Page 61 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Crystal Oscillator
Table 45. ECO Specifications
Spec ID# Parameter
MHz ECO DC Specifications
SID318 I
DD_kHz
Description
SID316 I
DD_MHz
MHz ECO AC Specifications
SID317 F_MHz Crystal frequency range kHz ECO DC Specification
Block operating current with Cload up to
18 pF
Block operating current with 32-kHz crystal
SID321E ESR32K
SID322E PD32K kHz ECO AC Specification
SID319 F_kHz
Equivalent Series Resistance
Drive level
SID320 Ton_kHz
SID320E F
TOL32K
32-kHz frequency
Startup time
Frequency tolerance
Min
–
16
–
–
–
Typ
800
–
0.38
80
–
– 32.768
–
–
–
50
Max
1600
35
–
500
250
1
–
1
External Clock
Table 46. External Clock Specifications
Spec ID# Parameter
SID305 EXTCLK
FREQ
SID306 EXTCLK
DUTY
Description
External Clock input Frequency
Duty cycle; Measured at V
DD/2
PLL
Table 47. PLL Specifications
Spec ID# Parameter
SID304P PLL_IN
SID305P PLL_LOCK
SID306P PLL_OUT
SID307P PLL_IDD
SID308P PLL_JTR
Description
Input frequency to PLL block
Time to achieve PLL Lock
Output frequency from PLL Block
PLL Current
Period Jitter
Min
0
45
Min
4
–
–
Typ
–
–
Typ
–
16
10.625 –
– 0.55
–
Max
100
55
Max
64
35
150
1.1
150
Unit
µA
Max = 35 MHz,
Typ = 16 MHz
MHz –
µA
– k Ω –
µW – kHz ms – ppm –
Unit Details / Conditions
MHz –
% –
Unit
MHz
–
µs –
MHz –
Details / Conditions
Details / Conditions mA Typ at 100 MHz out.
ps 100-MHz output frequency
Clock Source Switching Time
Table 48. Clock Source Switching Time Specifications
Spec ID# Parameter
SID262 TCLK
SWITCH
Description
Clock switching from clk1 to clk2 in clock periods
Min
–
Typ
–
Max
4 clk1 +
3 clk2
Unit periods –
Details / Conditions
Note
Document Number: 002-28630 Rev. *I Page 62 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
FLL
Table 49. Frequency Locked Loop (FLL) Specifications
Spec ID#
SID450
Parameter
FLL_RANGE
Description
Input frequency range.
SID451 FLL_OUT_DIV2 Output frequency range.
V
CCD
= 1.1 V
24.00
SID451A FLL_OUT_DIV2 Output frequency range.
V
CCD
= 0.9 V
SID452
24.00
FLL_DUTY_DIV2 Divided-by-2 output; High or Low 47.00
SID454 FLL_WAKEUP Time from stable input clock to 1% of final value on deep sleep wakeup
–
SID455
SID456
FLL_JITTER Period jitter (1 sigma at 100 MHz)
FLL_CURRENT CCO + Logic current
Min Typ
0.001
–
–
–
–
–
–
–
–
–
Max
100
100.00
Unit Details / Conditions
MHz Lower limit allows lock to
USB SOF signal (1 kHz).
Upper limit is for External input.
MHz Output range of FLL divided-by-2 output
50.00
53.00
7.50
35.00
MHz Output range of FLL divided-by-2 output
% –
µs ps
With IMO input, less than
10 °C change in temperature while in Deep
Sleep, and Fout ≥ 50 MHz.
50 ps at 48 MHz, 35 ps at
100 MHz
5.50
µA/MHz –
UDB
Table 50. UDB AC Specifications
Spec ID# Parameter
Data Path Performance
SID249
SID250
SID251
F
F
F
MAX-TIMER
MAX-ADDER
MAX_CRC
Description
Max frequency of 16-bit timer in a
UDB pair
Max frequency of 16-bit adder in a
UDB pair
Max frequency of 16-bit CRC/PRS in a UDB pair
PLD Performance in UDB
SID252 F
MAX_PLD
Max frequency of 2-pass PLD function in a UDB pair
Clock to Output Performance
SID253 T
CLK_OUT_UDB1
Prop. delay for clock in to data out
UDB Port Adapter Specifications
Conditions: 10-pF load, 3-V V
DDIO
and V
DDD
SID263 T
LCLKDO
LCLK to Output delay
SID264
SID265
SID266
SID267
SID268
T
T
T
DINLCLK
DINLCLKHLD
T
LCLKHIZ
T
FLCLK
LCLKDUTY
Input setup time to LCLK rising edge
Input hold time from LCLK rising edge
Min
–
–
–
–
–
–
–
5
LCLK to Output tristated
LCLK frequency
–
–
LCLK duty cycle (percentage high) 40%
Typ
–
–
–
–
5
–
–
–
–
–
–
Max
100
100
100
100
–
11
7
–
28
33
60%
Unit
MHz –
MHz
–
MHz –
MHz – ns ns
%
–
–
MHz –
–
Details / Conditions ns LCLK is a selected clock; for more information see the TRM ns – ns –
Document Number: 002-28630 Rev. *I Page 63 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
USB
Table 51. USB Specifications (USB requires LP Mode 1.1-V Internal Supply)
Description Min Spec ID# Parameter
USB Block Specifications
SID322U Vusb_3.3
3.15
SID323U
SID325U
SID328
SID329
Vusb_3
Iusb_config
Iusb_suspend
Iusb_suspend
Device supply for USB operation
Device supply for USB operation
(functional operation only)
Block supply current in Active mode
Block supply current in suspend mode
Block supply current in suspend mode
2.85
–
–
–
Typ
–
–
8
0.5
0.3
28 – SID330U USB_Drive_Res USB driver impedance
SID331U USB_Pulldown
USB pull-down resistors in Host mode
SID332U USB_Pullup_Idle Idle mode range
SID333U USB_Pullup Active mode
14.25
900
1425
–
–
–
Max
3.6
3.6
–
–
–
44
24.8
1575
3090
QSPI
Table 52. QSPI Specifications
Spec ID# Parameter Description
SMIF QSPI Specifications. All specs with 15-pF load.
SID390Q Fsmifclock SMIF QSPI output clock frequency
SMIF QSPI output clock frequency SID390QU
SID397Q
SID398Q
SID391Q
SID392Q
SID393Q
SID394Q
SID395Q
SID396Q
Fsmifclocku
Idd_qspi
Idd_qspi_u
Tsetup
Tdatahold
Tdataoutvalid
Tholdtime
Tseloutvalid
Tselouthold
Block current in LP mode (1.1 V)
Block current in ULP mode (0.9 V)
Input data set-up time with respect to clock capturing edge
Input data hold time with respect to clock capturing edge
Output data valid time with respect to clock falling edge
Output data hold time with respect to clock rising edge
Output Select valid time with respect to clock rising edge
Output Select hold time with respect to clock rising edge
Min
–
–
–
–
4.5
0
–
3
–
0.5*
Tsclk
Typ
–
–
–
–
–
–
–
–
–
–
Max
Unit
V
V
Ω k Ω
Ω
Ω
Unit
Details / Conditions
USB Configured
USB Configured mA V
DDD
= 3.3 V mA
V
DDD
= 3.3 V, Device connected mA
V
DDD
= 3.3 V, Device disconnected
Series resistors are on chip
–
Bus idle
Upstream device transmitting
Details / Conditions
3.7
–
7.5
–
80
50
1900
590
–
–
MHz LP mode (1.1 V)
MHz
ULP mode (0.9 V).
Guaranteed by Char.
µA LP mode (1.1 V)
µA ULP mode (0.9 V) ns – ns ns
–
7.5-ns max for ULP mode (0.9 V) ns – ns ns
15-ns max for ULP mode (0.9 V)
Tsclk = Fsmifclk cycle time
Document Number: 002-28630 Rev. *I Page 64 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Audio Subsystem
Table 53. Audio Subsystem Specifications
Spec ID# Parameter
PDM Specifications
Description
SID400P
SID401
PDM_IDD1
PDM_IDD2
PDM Active current, Stereo operation, 1-MHz clock
PDM Active current, Stereo operation, 3-MHz clock
SID402
SID403
SID403A
SID403B
PDM_JITTER
PDM_CLK
RMS Jitter in PDM clock
PDM Clock speed
PDM_BLK_CLK PDM Block input clock
PDM_SETUP
Data input set-up time to
PDM_CLK edge
SID403C
SID404
SID405
SID406
PDM_HOLD
PDM_OUT
PDM_WL
PDM_SNR
Data input hold time to PDM_CLK edge
Audio sample rate
Word Length
Signal-to-Noise Ratio
(A-weighted)
SID407
PDM_DR Dynamic Range (A-weighted)
Min
–
–
–200
0.384
1.024
10
10
8
16
–
Typ
175
– 100
SID408
PDM_FR Frequency Response –0.2
–
SID409
SID410
SID411
PDM_SB
PDM_SBA
Stop Band
Stop Band Attenuation
–
–
PDM_GAIN Adjustable Gain –12
SID412
PDM_ST Startup time –
I2S Specifications. The same for LP and ULP modes unless stated otherwise.
SID415
SID413
I2S_IDD
I2S_WORD
Block current
Length of I2S Word
–
8
0.566
60
–
48
400
–
SID414 I2S_WS – –
SID414M
SID414A
I2S_WS_U
I2S_WS_TDM
Word Clock frequency in LP mode
Word Clock frequency in ULP mode
Word Clock frequency in TDM mode for LP
–
–
–
–
SID414X I2S_WS_TDM_U Word Clock frequency in TDM
I2S Slave Mode
SID430
SID430U
TS_WS
TS_WS
WS Setup Time to the Following
Rising Edge of SCK for LP Mode
WS Setup Time to the Following
Rising Edge of SCK for ULP Mode
SID430A TH_WS
WS Hold Time to the Following
Edge of SCK
–
5
11
TMCLK_SOC
+ 5
–
–
–
–
–
–
–
100
600
–
–
–
–
Notes
6. Guaranteed by design, not production tested.
7. TMCLK_SOC is the internal I2S master clock period.
Document Number: 002-28630 Rev. *I
Max
–
–
200
3.072
49.152
–
–
48
24
–
–
0.2
–
–
10.5
–
–
32
192
48
48
12
–
–
–
Unit Details / Conditions
µA 16-bit audio at 16 ksps
µA 24-bit audio at 48 ksps ps –
MHz –
MHz – ns – ns – ksps – bits – dB dB
PDM input, 20 Hz to
20 kHz BW
20 Hz to 20 kHz BW,
–60 dB FS dB f
DC to 0.45f. DC
Blocking filter off.
– dB – dB
PDM to PCM,
1.5 dB/step
WS (Word Select) cycles
µA bits – kHz Eight 32-bit channels kHz Eight 32-bit channels ns – ns – ns –
Page 65 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 53. Audio Subsystem Specifications
(continued)
Spec ID#
SID432
Parameter
TD_SDO
SID432U TD_SDO
SID433 TS_SDI
SID433U TS_SDI
SID434 TH_SDI
SID435 TSCKCY
I2S Master Mode
Description
Delay Time of TX_SDO Transition from Edge of TX_SCK for LP mode
Min
–
(TMCLK_SOC +
25)
Delay Time of TX_SDO Transition from Edge of TX_SCK for ULP mode
RX_SDI Setup Time to the
Following Edge of RX_SCK in Lp
Mode
–
(TMCLK_SOC +
70)
5
RX_SDI Setup Time to the
Following Edge of RX_SCK in
ULP mode
RX_SDI Hold Time to the Rising
Edge of RX_SCK
TX/RX_SCK Bit Clock Duty Cycle
11
TMCLK_SOC +
5
45
SID437
SID437U TD_WS_U
SID438
TD_WS
TD_SDO
SID438U TD_SDO
WS Transition Delay from Falling
Edge of SCK in LP mode
WS Transition Delay from Falling
Edge of SCK in ULP mode
SDO Transition Delay from
Falling Edge of SCK in LP mode
SDO Transition Delay from
Falling Edge of SCK in ULP mode
–10
–10
–10
–10
SID439 TS_SDI
SDI Setup Time to the Associated
Edge of SCK
5
SID440 TH_SDI
SDI Hold Time to the Associated
Edge of SCK
TMCLK_SOC +
5
SID443
SID445
TSCKCY
FMCLK_SOC
SCK Bit Clock Duty Cycle
MCLK_SOC Frequency in LP mode
SID445U FMCLK_SOC_U MCLK_SOC Frequency in ULP
SID446
SID447
TMCLKCY
TJITTER
MCLK_SOC Duty Cycle
MCLK_SOC Input Jitter
45
1.024
1.024
45
–100
Typ
–
–
Max
TMCLK_SOC +
25
TMCLK_SOC +
70
Unit Details / Conditions ns
Associated clock edge depends on selected polarity ns
Associated clock edge depends on selected polarity
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
55
20
40
20
40
–
–
55
98.304
24.576
55
100 ns – ns – ns –
% – ns – ns – ns – ns – ns ns
%
Associated clock edge depends on selected polarity
T is TX/RX_SCK Bit
Clock period.
Associated clock edge depends on selected polarity.
–
% – ps –
Document Number: 002-28630 Rev. *I Page 66 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Smart I/O
Table 54. Smart I/O Specifications
Spec ID#
SID420
SID421
Parameter
SMIO_BYP
SMIO_LUT
Description
Smart I/O Bypass delay
Smart I/O LUT prop delay
Min Typ Max
–
–
–
8
2
–
Unit ns ns
–
–
Details / Conditions
Precision ILO (PILO)
Table 55. PILO Specifications
Spec ID# Parameter
SID 430R I
PILO
SID431 F_PILO
SID432R ACC_PILO
Description
Operating current
PILO nominal frequency
Min
–
–
PILO accuracy with periodic calibration –500
Typ
1.2
32768
–
Max
4
–
500
Unit
µA
Hz ppm
–
Details / Conditions
T = 25 °C
–
JTAG Boundary Scan
Table 56. JTAG Boundary Scan
Spec ID#
JTAG Boundary Scan Parameters
Parameter Description Min Typ Max
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:
SID468 TCKLOW TCK LOW
SID469
SID470
TCKHIGH
TCK_TDO
TCK HIGH
TCK falling edge to output valid
SID471
SID472
SID473
SID474
TSU_TCK
TCk_THD
TCK_TDOV
TCK_TDOZ
Input valid to TCK rising edge
Input hold time to TCK rising edge
TCK falling edge to output valid
(High-Z to Active).
TCK falling edge to output valid (Active to High-Z).
JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468A TCKLOW TCK low
SID469A
SID470A
TCKHIGH
TCK_TDO
TCK high
TCK falling edge to output valid
SID471A
SID472A
SID473A
SID474A
TSU_TCK
TCk_THD
TCK_TDOV
TCK_TDOZ
Input valid to TCK rising edge
Input hold time to TCK rising edge
TCK falling edge to output valid (high-Z to active).
TCK falling edge to output valid (active to high-Z).
52
10
12
10
40
40
102
20
22
20
80
80
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40 ns –
–
–
–
–
–
–
–
– ns ns – ns ns ns ns ns ns ns ns
–
–
–
–
–
– ns –
80 ns –
–
– ns –
–
–
–
Units
Document Number: 002-28630 Rev. *I Page 67 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Bluetooth LE
Table 57. Bluetooth LE Subsystem Specifications
Spec ID# Parameter
RF Receiver Specifications (1 Mbps)
SID317R RXS,IDLE
SID317RR RXS,IDLE
Description
RX Sensitivity with Ideal Transmitter
RX Sensitivity with Ideal Transmitter
Min
–
–
SID318R RXS,DIRTY RX Sensitivity with Dirty Transmitter –
SID319R
SID320R
SID321R
SID322R
SID323R
SID324R
SID325R
PRXMAX
CI1
CI2
CI3
CI4
CI5
CI6
Maximum received signal strength at < 0.1% PER
Co-channel interference,
Wanted Signal at –67 dBm and
Interferer at FRX
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at FRX ± 1 MHz
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at FRX ± 2 MHz
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at ≥ FRX ± 3 MHz
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE)
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE ± 1 MHz)
RF Receiver Specifications (2 Mbps)
SID326 RXS,IDLE
RX Sensitivity with Ideal Transmitter
SID326R RXS,IDLE
RX Sensitivity with Ideal Transmitter
SID327 RXS,DIRTY
–
–
–
–
–
–
–
–
–
SID328R
SID329R
SID330
SID331
PRXMAX
CI1
CI2
CI3
RX Sensitivity with Dirty Transmitter –
Maximum received signal strength at < 0.1% PER
Co-channel interference,
Wanted Signal at –67 dBm and
Interferer at FRX
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at FRX ± 2 MHz
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at FRX ± 4 MHz
–
–
–
–
Typ
9
3
–26
–33
–20
–28
9
3
–26
–95
–93
–92
0
–92
–90
–89
0
–
–
–
–
21
Max Unit
–9
Details / Conditions
–
–
–
– dBm
Across RF Operating
Frequency Range
21
15
–17
–27 dBm
RF-PHY Specification
(RCV-LE/CA/06/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C)
–15
15
–17 dB
RF-PHY Specification
(RCV-LE/CA/03/C) dBm
255-byte packet length, across Frequency Range dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C) dB
RF-PHY Specification
(RCV-LE/CA/03/C)
Document Number: 002-28630 Rev. *I Page 68 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 57. Bluetooth LE Subsystem Specifications
(continued)
Spec ID#
SID332
SID333
SID334
SID341
SID342
CI4
CI5
CI6
Parameter
OBB4
IMD
Description
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at ≥ FRX ± 6 MHz
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE)
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
(FIMAGE ± 2MHz)
RF Receiver Specification (1 & 2 Mbps)
SID338 OBB1
Out of Band Blocking
Wanted Signal at –67 dBm and
Interferer at F = 30–2000 MHz
SID339
SID340
OBB2
OBB3
Out of Band Blocking
Wanted Signal at –67 dBm and
Interferer at F = 2003–2399 MHz
Out of Band Blocking,
Wanted Signal at –67 dBm and
Interferer at F= 2484–2997MHz
Out of Band Blocking
Wanted Signal at –67 dBm and
Interferer at F= 3000–12750 MHz
Intermodulation Performance
Wanted Signal at –64 dBm and
1 Mbps Bluetooth LE, 3rd, 4th, and
5th offset channel
Min
–
–
–
–30
–35
–35
–30
–50
SID343 RXSE1
Receiver Spurious emission
30 MHz to 1.0 GHz
–
SID344 RXSE2
Receiver Spurious emission
1.0 GHz to 12.75 GHz
RF Transmitter Specifications
SID345 TXP,ACC RF Power Accuracy
SID346
SID347
TXP,RANGE
TXP,0dBm
Frequency Accuracy
Output Power, 0 dB Gain setting
SID348
SID349
SID350
SID350R
SID351
TXP,MAX
TXP,MIN
F2AVG
F2AVG_2M
F1AVG
Output Power, Maximum Power
Setting
Output Power, Minimum Power
Setting
Average Frequency deviation for
10101010 pattern
Average Frequency deviation for
10101010 pattern for 2 Mbps
Average Frequency deviation for
11110000 pattern
–
185
370
225
–
–
–1
–
–
–
Typ
–33
–20
–28
–27
–27
–27
–27
–
–
–20
–
–
250
–
24
0
–
–
4
Max
–27
Unit dB
Details / Conditions
RF-PHY Specification
(RCV-LE/CA/03/C)
–9 dB
RF-PHY Specification
(RCV-LE/CA/03/C)
–15
–
–
–
– dB dBm
RF-PHY Specification
(RCV-LE/CA/03/C)
RF-PHY Specification
(RCV-LE/CA/04/C) dBm
RF-PHY Specification
(RCV-LE/CA/04/C)
–
275
–
–
–53
–
–
–
1
–
–
–57 dBm
RF-PHY Specification
(RCV-LE/CA/05/C) dBm dBm
100-kHz measurement bandwidth
ETSI EN300 328 V2.1.1
1-MHz measurement bandwidth
ETSI EN300 328 V2.1.1
– dB – dB –20 dBm to +4 dBm dBm – dBm – dBm – kHz kHz kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/05/C)
Document Number: 002-28630 Rev. *I Page 69 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 57. Bluetooth LE Subsystem Specifications
(continued)
Spec ID#
SID351R
Parameter
F1AVG_2M
Description
Average Frequency deviation for
11110000 pattern for 2 Mbps
Min
450
SID352 EO Eye opening = ∆F2AVG/∆F1AVG 0.8
SID353
SID354
FTX,ACC
FTX,MAXDR
Frequency Accuracy
Maximum Frequency Drift
–150
–50
–20
–20
SID355 FTX,INITDR Initial Frequency drift
SID356
SID357
SID358
SID359
FTX,DR
IBSE1
IBSE2
TXSE1
SID360 TXSE2
RF Current Specification
SID361 IRX1_wb
Maximum Drift Rate
In Band Spurious Emission at
2 MHz offset (1 Mbps)
In Band Spurious Emission at
4 MHz offset (2 Mbps)
In Band Spurious Emission at ≥
3 MHz offset (1 Mbps)
In Band Spurious Emission at ≥
6 MHz offset (2 Mbps)
Transmitter Spurious Emissions
(Averaging), < 1.0 GHz
Transmitter Spurious Emissions
(Averaging), > 1.0 GHz
Receive Current (1 Mbps)
SID362
SID363
SID364
IRX1_nb Receive Current (1 Mbps)
SID365 ITX1_nb_4dBm
TX Current at 4-dBm setting
(1 Mbps)
SID365R ITX1_wb_4dBm TX Current at 4-dBm setting
SID366
IRX2_wb Receive Current (2 Mbps) SID367
SID368
SID369
SID370
IRX2_nb Receive Current (2 Mbps)
SID371 ITX2_nb_4dBm
TX Current at 4-dBm setting
(2 Mbps)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7
5.7
11.3
10
13
6.7
5.7
11
10
13
8.5
7
–
–
–
–
Typ
500
–
150
50
20
20
Max
550
–
–20
–30
–
–
–
–
–
–
–
–
–
–
–
–
Unit kHz
– kHz kHz kHz kHz/
50 µs
Details / Conditions
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/05/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C)
RF-PHY Specification
(TRM-LE/CA/06/C) dBm
RF-PHY Specification
(TRM-LE/CA/03/C) dBm
–55.5
dBm FCC-15.247
–41.5
dBm FCC-15.247
mA mA mA mA
RF-PHY Specification
(TRM-LE/CA/03/C)
VDD_NS = V
DDD current with buck
= 3.3 V
VDD_NS = V
DDD current with buck
= 3.3 V mA V
DDD
current without buck mA V
DDD
V
DDD
current without buck mA V
DDD
current without buck
VDD_NS = V
DDD current with buck
= 3.3 V mA V
DDD
current without buck mA
VDD_NS = V
DDD current with buck
= 3.3 V mA
VDD_NS = V
DDD current with buck
= 3.3 V mA V
DDD
current without buck mA V
DDD
current without buck
current without buck
Document Number: 002-28630 Rev. *I Page 70 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 57. Bluetooth LE Subsystem Specifications
(continued)
Spec ID# Parameter Description Min
SID371R ITX2_wb_4dBm TX Current at 4-dBm setting
SID372 ITX2_nb_20dBm
TX Current at –20-dBm setting
(2 Mbps)
General RF Specification
SID373
SID374
SID375
SID376
SID377
SID378
FREQ
CHBW
DR1
DR2
TXSUP
RXSUP
RSSI Specification
RF operating frequency
Channel spacing
On-air Data Rate (1 Mbps)
On-air Data Rate (2 Mbps)
Transmitter Startup time
Receiver Startup time
–
–
2400
–
–
–
–
–
SID379 RSSI,ACC RSSI Accuracy
SID380
SID381
RSSI,RES
RSSI,PER
RSSI Resolution
RSSI Sample Period
System-Level Bluetooth LE Specifications
SID433R Adv_Pwr 1.28s, 32 bytes, 0 dBm
–4
–
–
–
SID434R Conn_Pwr_300 300 ms, 0 byte, 0 dBm –
Typ
8.5
7
–
2
1000
2000
80
80
–
1
6
42
70
SID435R Conn_Pwr_1S 1000 ms, 0 byte, 0 dBm
SID436R Conn_Pwr_4S 4000 ms, 0 byte, 0 dBm
–
–
30
4
Max
–
–
–
–
–
– mA V
DDD
2482
–
–
–
82
82
MHz –
MHz – kbps – kbps –
µs –
µs –
4
–
–
Unit mA dB dB –
µs –
µW
µW
µW
µW
Details / Conditions
VDD_NS = V
DDD current with buck
= 3.3 V
current without buck
–95 dBm to –20 dBm measurement range
3.3 V, Buck, w/o Deep Sleep current
3.3 V, Buck, w/o Deep Sleep current
3.3 V, Buck, w/o Deep Sleep current
3.3 V, Buck, w/o Deep Sleep current
Document Number: 002-28630 Rev. *I Page 71 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 58. Bluetooth LE ECO Specifications
Spec ID# Parameter
16-MHz Crystal Oscillator
SID382 FXO1
SID383 ESR1
Description
Crystal frequency
Equivalent series resistance
SID384 Txostart1 Startup time
SID385 IXO1
32-MHz Crystal Oscillator
SID386 FXO2
SID387 ESR2
SID388 Txostart2
Operating current
Crystal frequency
Equivalent series resistance
Startup time
SID389 IXO2 Operating current
16-MHz and 32-MHz Crystal Oscillator
SID390 FTOL
SID391 PD
Frequency tolerance
Drive level
Min Typ Max Unit Details / Conditions
–
–
–
–
16
100
400
300
–
250
–
–
MHz –
Ω –
µs
µA
Frequency Stable
(16 MHz ±50 ppm)
Includes crystal current,
LDO and BG
–
–
–
–
32
50
400
350
–
100
–
–
MHz –
Ω –
µs
Frequency Stable
(32 MHz ±50 ppm)
µA
Includes crystal current,
LDO and BG
–20
–
–
–
20
100 µW –
Document Number: 002-28630 Rev. *I Page 72 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Ordering Information
lists the CYB06447BZI-BLD5x part numbers and features. All devices include a Bluetooth LE radio, DC-DC converter, QSPI
SMIF, ADC, DAC, 9 SCBs, 32 TCPWMs, 2 PDM, and I2S. See also the product selector guide.
Table 59. Ordering Information
64
CYB06447BZI-BLD54 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 84
CYB06447BZI-BLD53 150/50 100/25 Dual FLEX 1024 288 1 12 Yes 78
Yes
Yes
Yes 124-BGA
No 116-BGA
Document Number: 002-28630 Rev. *I Page 73 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
PSoC 6 MPN Decoder
CY XX 6 A B C DD E - FF G H I JJ K L
Field Description Values
CY Cypress CY
Meaning
Cypress
XX Firmware
8C Standard
B0 “Secure Boot” v1
S0
“Standard Secure” -
AWS
6 Architecture
A Line
1
2
6
0
PSoC 6
Value
Programmable
Performance
B Speed
2
3
3
4
4
Connectivity
Secured
100 MHz
150 MHz
150/50 MHz
0-3 Reserved
C
Memory Size
(Flash/SRAM)
DD Package
4
5
6
256K/128K
512K/256K
512K/128K
9
A
7
8
1024K/288K
1024K/512K
Reserved
2048K/1024K
AZ, AX TQFP
LQ QFN
BZ BGA
FM M-CSP
FN, FD,
FT
WLCSP
Field
E
Description
Temperature Range
Values
C
I
Q
Meaning
Consumer
Industrial
Extended Industrial
FF
G
H
I
JJ
K
L
Feature Code
CPU Core
Attributes Code
GPIO count
Engineering sample
(optional)
Die Revision
(optional)
Tape/Reel Shipment
(optional)
Cypress internal
S2-S6
BL
F
D
Integrated Bluetooth LE
Single Core
Dual Core
0–9 Feature set
1
2
31–50
51–70
3
4
ES
71–90
91–110
Engineering samples or not
Base
A1–A9 Die revision
T Tape and Reel shipment
Document Number: 002-28630 Rev. *I Page 74 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Packaging
This product line is offered in two packages: 124-BGA and 116-BGA.
Table 60. Package Dimensions
Spec ID# Package Description
PKG_1 124-BGA 124-BGA, 9 mm 9 mm 1 mm height with 0.65-mm pitch
PKG_2 116-BGA 116-BGA, 5.2 „e 6.4 „e 0.70 mm height with 0.5-mm pitch
Table 61. Package Characteristics
Parameter
T
A
T
J
T
JA
T
JC
T
JA
T
JC
Description
Operating ambient temperature
Operating junction temperature
Package
JA
(124-BGA)
Package
JC
(124-BGA)
Package
JA
(116-BGA)
Package
JC
(116-BGA)
Table 62. Solder Reflow Peak Temperature
Package
All packages
Conditions
–
–
–
–
–
–
Maximum Peak Temperature
260 °C
Table 63. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
All packages
–
–
–
Min
–40
–40
–
Package Drawing Number
001-97718
002-16574
Typ
25
–
64.3
37
36.5
12
–
–
–
Max
85
100
–
Units
°C
°C
°C/watt
°C/watt
°C/watt
°C/watt
Maximum Time at Peak Temperature
30 seconds
MSL
MSL 3
Document Number: 002-28630 Rev. *I Page 75 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Figure 20. 116-BGA 5.2 × 6.4 × 0.70 mm
Document Number: 002-28630 Rev. *I
002-16574 *B
Page 76 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Figure 21. 124-BGA 9.0 × 9.0 ×1.0 mm
Document Number: 002-28630 Rev. *I
001-97718 *B
Page 77 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Acronyms
CMOS
CMRR
CPU
CRC
CSD
EMI
ESD
ETM
FIFO
FLL
FPU
CSX
DAC
DAP
DES
DMA
DNL
DSI
DU
ECC
ECO
EEPROM
Acronym
3DES
ADC
AES
AHB
AMUX
AMUXBUS
API
Arm
®
BGA
BOD
CAD
CCO
CM0+
CM4
CMAC
Description triple DES (data encryption standard) analog-to-digital converter advanced encryption standard
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus analog multiplexer analog multiplexer bus application programming interface advanced RISC machine, a CPU architecture ball grid array brown-out detect computer aided design current controlled oscillator
Cortex-M0+, an Arm CPU
Cortex-M4, an Arm CPU cipher-based message authentication code complementary metal-oxide-semiconductor, a process technology for IC fabrication common-mode rejection ratio central processing unit cyclic redundancy check, an error-checking protocol
CapSense Sigma-Delta
Cypress mutual capacitance sensing method. See also CSD digital-to-analog converter, see also IDAC, VDAC debug access port data encryption standard direct memory access, see also TD differential nonlinearity, see also INL digital system interconnect data unit elliptic curve cryptography external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference electrostatic discharge embedded trace macrocell first-in, first-out frequency locked loop floating-point unit
Document Number: 002-28630 Rev. *I
Acronym
FS
GND
GPIO
INL
IoT
IPC
IRQ
IDAC
IDE
ILO
IMO
HMAC
HSIOM
I/O
I
2
C, or IIC
I
2
S
IC
ISR
JTAG
LCD
LIN
Msps
MTB
MUL
NC
NMI
LP
LS
LUT
LVD
LVTTL
MAC
M-CSP
MCU
MCWDT
MISO
MMIO
MOSI
MPU
MSL
Description full-speed
Ground general-purpose input/output, applies to a PSoC pin
Hash-based message authentication code high-speed I/O matrix input/output, see also GPIO, DIO, SIO, USBIO
Inter-Integrated Circuit, a communications protocol inter-IC sound integrated circuit current DAC, see also DAC, VDAC integrated development environment internal low-speed oscillator, see also IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL internet of things inter-processor communication interrupt request interrupt service routine
Joint Test Action Group liquid crystal display
Local Interconnect Network, a communications protocol low power low-speed lookup table low-voltage detect, see also LVI low-voltage transistor-transistor logic multiply-accumulate molded chip scale package microcontroller unit multi-counter watchdog timer master-in slave-out memory-mapped input output master-out slave-in memory protection unit moisture sensitivity level million samples per second micro trace buffer multiplier no connect nonmaskable interrupt
Page 78 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
SPI
SRAM
SROM
SRSS
SWD
SWJ
RTC
RX
S/H
SAR
SARMUX
SCB
SFlash
SHA
SINAD
SNR
SOF
PSRR
PWM
QD
QSPI
RAM
RISC
RMS
ROM
Acronym
NVIC
OTP
OVT
PASS
PCB
PCM
PDM
PHY
PICU
PLL
PMIC
POR
PPU
PRNG
PSoC
®
RSA
Description nested vectored interrupt controller one-time programmable overvoltage tolerant programmable analog subsystem printed circuit board pulse code modulation pulse density modulation physical layer port interrupt control unit phase-locked loop power management integrated circuit power-on reset peripheral protection unit pseudo random number generator
Programmable System-on-Chip™ power supply rejection ratio pulse-width modulator quadrature decoder quad serial peripheral interface random-access memory reduced-instruction-set computing root-mean-square read-only memory
Rivest–Shamir–Adleman, a public-key cryptography algorithm real-time clock receive sample and hold successive approximation register
SAR ADC multiplexer bus serial communication block supervisory flash secure hash algorithm signal to noise and distortion ratio signal-to-noise ration start of frame
Serial Peripheral Interface, a communications protocol static random access memory supervisory read-only memory system resources subsystem serial wire debug, a test protocol serial wire JTAG
Document Number: 002-28630 Rev. *I
UART
UDB
ULP
USB
WCO
WDT
WIC
WLCSP
XIP
XRES
Acronym
SWO
SWV
TCPWM
TDM
TQFP
TRM
TRNG
TX
Description single wire output serial-wire viewer timer, counter, pulse-width modulator time division multiplexed thin quad flat package technical reference manual true random number generator transmit
Universal Asynchronous Transmitter Receiver, a communications protocol universal digital block ultra-low power
Universal Serial Bus watch crystal oscillator watchdog timer wakeup interrupt controller wafer level chip scale package execute-in-place external reset input pin
Page 79 of 83
Document Conventions
khr kHz k ksps
LSB
Mbps
MHz
M
Msps
µA
µF
Symbol
°C dB fF
Hz
KB kbps
Unit of Measure
Table 64. Unit of Measure degrees Celsius decibel
Unit of Measure femto farad hertz
1024 bytes kilobits per second kilohour kilohertz kilo ohm kilosamples per second least significant bit megabits per second megahertz mega-ohm megasamples per second microampere microfarad
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Table 64. Unit of Measure (continued) mV nA ns nV
pF
Symbol
µH
µs
µV
µW mA ms ppm ps s sps sqrtHz
V microhenry microsecond microvolt microwatt milliampere millisecond millivolt nanoampere
Unit of Measure nanosecond nanovolt ohm picofarad parts per million picosecond second samples per second square root of hertz volt
Document Number: 002-28630 Rev. *I Page 80 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Revision History
Description Title: PSoC 6 MCU: CYB06447BZI-BLDx Datasheet
Document Number: 002-28630
Revision
**
ECN
Submission
Date
6694857 10/10/2019 New datasheet
*A
*B
6756608
6848239
12/19/2019
04/07/2020
Description of Change
Updated Features .
Updated Blocks and Functionality and Functional Description .
Updated Pinouts and Power Supply Considerations .
Updated
Updated Functional Description .
Updated
Updated
*C
*D
6898008
7004924
06/25/2020
11/10/2020
Updated
Added
.
Updated Errata
Updated amount of available SRAM in Features ,
and Ordering Information . Updated
subsection. Updated
Updated
Updated
Universal Digital Blocks (UDBs)
,
Port Adapter Specifications Conditions.
Added
InterProcessor Communication (IPC) .
Updated
diagram.
Updated the XRES bullet in
, updated SID15 Description and Conditions, and
specifications table.
Updated
Updated
Updated
.
Added footnote to TMCLK_SOC specs.
Updated
Updated SID7A conditions, SID7D description, and SID8 conditions.
Added spec SID468 - SID474, and SID468A - SID474A.
Updated Audio Spec SID408.
Updated
.
Integrated ECO erratum into External Crystal Oscillators . Added ECO Usage Guidelines
table.
Added three errata items.
*E
*F
*G
*H
7094508 03/01/2021
Added
Updated conditions for SID316 and updated description of SID319.
Changed BLE references to Bluetooth LE.
Updated Security terminology to Infineon standards.
Incorporated GPIO-related errata into the GPIO, ADC, and CapSense sections.
7173987
06/30/2021 Added opamp graphs (
and
Updated Security terminology.
7231613
7508678
08/19/2021
12/13/2021
Updated SIDDS2 - Corrected Deep Sleep current values
Removed "System Deep Sleep power higher than specification" errata item.
Removed Errata and Preliminary tag.
Added note regarding unused USB pins in USB Full-Speed Device Interface
,
Updated SIDC1 description.
Updated
Figure 17 and added related footnote.
Updated details/conditions for SID7A.
Updated SID325U, SID328, and SID329 description.
Document Number: 002-28630 Rev. *I Page 81 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Description Title: PSoC 6 MCU: CYB06447BZI-BLDx Datasheet
Document Number: 002-28630
*I 7785319 10/26/2022
Added device identification and revision information in Features
.
Added spec SID415 and SID304P.
Added footnote "Guaranteed by design, not production tested" for specs SID402 - SID412.
Updated
and
specifications.
Updated
Document Number: 002-28630 Rev. *I Page 82 of 83
PSoC 6 MCU:
CYB06447BZI-BLDx Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .
Products
Arm
®
Cortex
®
Microcontrollers
Automotive
Clocks & Buffers
Interface
Internet of Things
Memory
Microcontrollers
PSoC
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory cypress.com/mcu cypress.com/psoc cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless
PSoC
®
Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
© Cypress Semiconductor Corporation, 2019-2022. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device" means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-28630 Rev. *I Revised October 27, 2022 Page 83 of 83
advertisement
Related manuals
advertisement
Table of contents
- 2 General Description
- 2 Features
- 2 32-bit Dual CPU Subsystem
- 2 Memory Subsystem
- 2 Hardware-Based Root-of-Trust (RoT)
- 2 Immutable “Secure Boot” Support
- 2 Cypress Bootloader
- 2 Bluetooth Low Energy Subsystem
- 2 Low-Power 1.7-V to 3.6-V Operation
- 2 Flexible Clocking Options
- 3 Quad SPI (QSPI)/Serial Memory Interface (SMIF)
- 3 Segment LCD Drive
- 3 Serial Communication
- 3 Audio Subsystem
- 3 Timing and Pulse-Width Modulation
- 3 Programmable Analog
- 3 Up to 84 Programmable GPIOs
- 3 Capacitive Sensing
- 3 Cryptography Accelerator
- 3 Programmable Digital
- 3 Profiler
- 3 Packages
- 3 Device Identification and Revisions
- 4 Contents
- 5 Development Ecosystem
- 5 PSoC 6 MCU Resources
- 6 ModusToolbox Software
- 7 Blocks and Functionality
- 9 Functional Description
- 9 CPU and Memory Subsystem
- 9 CPUs
- 10 Interrupts
- 10 InterProcessor Communication (IPC)
- 10 DMA Controllers
- 10 Cryptography Accelerator (Crypto)
- 10 Protection Units
- 11 Memory
- 11 Boot Code
- 12 Memory Map
- 12 System Resources
- 12 Power System
- 12 Power Modes
- 13 Clock System
- 13 Internal Main Oscillator (IMO)
- 13 Internal Low-speed Oscillator (ILO)
- 14 External Crystal Oscillators
- 14 Watchdog Timers (WDT, MCWDT)
- 14 Clock Dividers
- 14 Trigger Routing
- 14 Reset
- 15 Bluetooth LE Radio and Subsystem
- 16 Programmable Analog Subsystem
- 16 12-bit SAR ADC
- 16 Temperature Sensor
- 16 12-bit Digital-Analog Converter
- 16 Continuous Time Block mini (CTBm) with Two Opamps
- 16 Low-Power Comparators
- 18 Programmable Digital
- 18 Smart I/O
- 18 Universal Digital Blocks (UDBs)
- 18 Fixed-Function Digital
- 18 Timer/Counter/Pulse-width Modulator (TCPWM) Block
- 18 Serial Communication Blocks (SCB)
- 19 USB Full-Speed Device Interface
- 19 QSPI Interface Serial Memory Interface (SMIF)
- 19 LCD
- 19 GPIO
- 20 Special-Function Peripherals
- 20 Audio Subsystem
- 20 CapSense Subsystem
- 23 PSoC 64 Security
- 25 Cypress Bootloader
- 26 Pinouts
- 38 Power Supply Considerations
- 41 Electrical Specifications
- 41 Absolute Maximum Ratings
- 41 Device-Level Specifications
- 42 Power Supplies
- 43 CPU Current and Transition Times
- 47 XRES
- 47 GPIO
- 49 Analog Peripherals
- 49 Opamp
- 52 Low-Power (LP) Comparator
- 53 SAR ADC
- 54 DAC
- 54 CSD
- 58 Digital Peripherals
- 60 LCD Specifications
- 60 Memory
- 60 Flash
- 61 System Resources
- 61 Power-on-Reset
- 61 Voltage Monitors
- 62 SWD and Trace Interface
- 62 Internal Main Oscillator
- 62 Internal Low-Speed Oscillator
- 63 Crystal Oscillator
- 63 External Clock
- 63 PLL
- 63 Clock Source Switching Time
- 64 FLL
- 64 UDB
- 65 USB
- 65 QSPI
- 66 Audio Subsystem
- 68 Smart I/O
- 68 Precision ILO (PILO)
- 68 JTAG Boundary Scan
- 69 Bluetooth LE
- 74 Ordering Information
- 75 PSoC 6 MPN Decoder
- 76 Packaging
- 79 Acronyms
- 81 Document Conventions
- 81 Unit of Measure
- 82 Revision History
- 84 Sales, Solutions, and Legal Information
- 84 Worldwide Sales and Design Support
- 84 Products
- 84 PSoC® Solutions
- 84 Cypress Developer Community
- 84 Technical Support