null null

US008667204B2
(12) United States Patent
Fischer et a].
(54)
METHOD TO DIFFERENTIATE IDENTICAL
DEVICES ON A TWO-WIRE INTERFACE
US 8,667,204 B2
(10) Patent N0.:
(45) Date of Patent:
(56)
Mar. 4, 2014
References Cited
U.S. PATENT DOCUMENTS
(75) Inventors: Armin Fischer, Romerstein (DE);
Joachim Riexinger, Gammelshausen
(DE); Frank Kronmueller, Neudenau
(DE)
Notice:
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 128 days.
(21) Appl. No.: 12/931,063
12/1994
12/1998
7,444,453 B2
7,849,244 B2
10/2008 Ellison
12/2010 Huang et al.
Testin ......................... .. 710/105
Edde et al. ................... .. 340/42
2002/0190755 A1*
12/2002
Lee ............................... .. 326/86
2007/0064819 A1*
3/2007
Langer ........................ .. 375/257
2008/0288684 A1
(73) Assignee: RPX Corporation, San Francisco, CA
(Us)
(*)
5,376,928 A *
5,852,406 A *
2011/0102053 A1*
11/2008 Ellison
5/2011
Wang .......................... .. 327/365
OTHER PUBLICATIONS
Vassilevsky, Vladimir, et al. “Discussion Groups | Comp.Arch.Em
bedded | 12C trick?”. EmbeddedRelated.com forum. Dec. 28-30,
2007. Retrieved from Internet Jul. 18, 2013. <http://WWW.embed
dedIelatedcom/usenet/ embedded/ shoW/ 873 59-1 .php>.*
UM10204, 12C-bus speci?cation and user manual, Rev. 03-19 Jun.
2007, NXP B.V., pp. 1-50.
The 12C-bus speci?cation; version 2.1, Jan. 2000, Philips Semicon
(22)
Filed:
ductors, pp. 1-46.
Jan. 24, 2011
* cited by examiner
(65)
Prior Publication Data
US 2012/0191889 A1
Jul. 26, 2012
Primary Examiner * Thomas J Cleary
(74) Attorney, Agent, or Firm * HoWison & Arnott, L.L.P.
(57)
(51)
(52)
Int. Cl.
G06F 3/00
G06F 13/00
G06F 13/14
US. Cl.
(2006.01)
(2006.01)
(2006.01)
identical slave devices on a same 12C bus Without any hard
Ware (e.g. additional ID pins) or software overhead are dis
closed. Each identical slave device is connected to the SDA/
USPC ..... .. 710/305; 710/3; 710/8; 710/14; 710/110
(58)
ABSTRACT
Systems and methods for providing a differentiation of tWo
Field of Classi?cation Search
USPC ....... .. 710/3-4, 8-10, 14, 30(L302, 104-106,
710/110, 305, 316
See application ?le for complete search history.
SBA
SCL lanes by interchanging its SDA/SCL ports. It is up to the
slave device to detect its signal connectivity to the SDA/SCL
lanes of the 12C bus. The slave devices detect the signal
connectivity by interpreting the 12C transfer in normal and
interchanged connectivity.
Sla'ue ID decoder (ID A)
980A
13 Claims, 5 Drawing Sheets
v82
Device
$255:
120 Sla'ue
SDA
SCL
Slave ID decoder (ID B)
_9SDA
9SCL
Slave ID decoder (ID A)
980A
/|\
Decode
status
(
V83
30
V82
De'uice
Z'ZZ‘ZSZ
—9sc1,
12c Slave
a,
X
SDA
SCL
Slave ID decoder (ID B)
“95m
9801.
SCL
/|\
Decode
status
v83
80
US. Patent
Mar. 4, 2014
Sheet 1 of5
US 8,667,204 B2
SDA
126 Master
$04
120 Slave
SCL
SDA
SCL
SCL
FIG.
7
— Prior Art
VDD
m Pull up
'res'lsto'r
Bus Signal
PAD
Set enable
-
.
,
toelzzw-lo-
FIG.
SDA
'
'
Bus
‘1’ -
s1,
al
0
2
— PT'LO?" A'rt
/
X
\
SCL m
Data line
Change
stable and of data
data valid al lowed
FIG.
3
—- P'rio'r A’rt
US. Patent
Mar. 4, 2014
Sheet 2 of5
US 8,667,204 B2
SDA ———\
/_
SCL m
Start/
Stop
Restart
condition
FIG.
4
condition
— P'r'io'r AT't
aclcnzatledge
SDA_\
HEB X
SCL
1
X
\ACK /WB X
2
8
9
1
X
2
XACK X
acknowledge
8
9
géglta?
condition
FIG.
Stop 01'
Restart
condition
5
— P'r'zlo'r A'rt
MSB
LSB
R/W
V
Slave Address
FIG.
X
6
— Prior Art
US. Patent
Mar. 4, 2014
Sheet 3 of5
US 8,667,204 B2
SDA
12C Master
SDA
>l
[20 Stave
SCL
SDA/SCL
SCL/SDA
112 11/10 B
126‘ Slave
-<
SDA/S'CL
[email protected]/sm
m A/ID B
SC'L
SDA
Slave [0 decoder (ID A)
98014
v82
Device
253%:
SCL
12c Slave
8,
X
'<
S'DA
SCL
Slave 1D decoder (ID B)
DSign?
d
SPA
S'C'L
FfG.
801,
(
US. Patent
Mar. 4, 2014
Sheet 4 of5
US 8,667,204 B2
SDA
Device
Slave ID decoder (ID A) "'82
SD44
gigs:
SCL
12C Stave
/ 81
SDA
SCL
Stave 1D decoder (ID B)
SDA
SC'L
Slave ID decoder (ID A)
SDA
Decode
status
(
V83
80
v82
Device
23333:
SCL
f
K
?x
[20 Stave
81
SDA
SCL
Sla'ue ID decoder (ID B)
I
Decode
SDA
status
SCL
FIG.
8b
(
US. Patent
Mar. 4, 2014
Sheet 5 of5
US 8,667,204 B2
Start
J,
Providing a two-wire commmication system comprising
a SDA and a $61. lane, an 126' master and two identical
v90
[26 slave devices
Connecting physically the SDA and SCL lanes to each
slave device, wherein each slave is connected by
interchanging its SDA and SCL ports
v91
J2
Performing a signal cormectivity check: by detecting
signal connectivity by a slave device by interpreting
information transfer in normal and exchanged signal
v92
connectivity mode
l
Fixing a signal connectivity mode selection as soon as
the signal connectivity check results in detecting any
v93
correct slave device ID
i
Selecting detected correct slave 1D for conummication
FIG.
9
v94
US 8,667,204 B2
1
2
METHOD TO DIFFERENTIATE IDENTICAL
DEVICES ON A TWO-WIRE INTERFACE
The TWI or I2C control bus uses 2 lanes, a serial data lane
(SDA) and a serial clock lane (SCL). The data lane is used to
transfer the information Whereas the clock lane controls or
validates the data information How. It is realiZed as shoWn in
BACKGROUND
FIG. 1 prior art.
Master and slave are connected to the Serial Data Line
(1) Field of the Invention
This invention relates generally to electronic interfaces and
(SDA) and Serial Clock line (SCL) via an Open-Drain or
Open-Collector circuit. This alloWs that several devices can
access the bus in parallel. An Open-Drain/Open-Collector
circuit is shoWn in FIG. 2 prior art.
An Open-Drain/Open-Collector circuit is shoWn in FIG. 2
prior art. For the Open-Drain or Open-Collector circuit the
according bus line is pulled up to VDD via a pull-up resistor,
While the device does only drive ‘0’ on the bus. The resulting
signal level on the bus is an AND combination of the outputs
of all devices connected to the line.
FIG. 3 prior art shoWs different states of the SDA and SCL
lines i.e. When data line is stable and valid and When change
of data is alloWed. The data on the tWo serial lines of the I2C
relates more speci?cally to tWo Wire interfaces.
(2) Description of the Prior Art
The Inter-Integrated Circuit (I2C), also called tWo-Wire
interface (TWI) interface is a 2-Wire interface for loW speed
communication betWeen electrical components. The commu
nication is alWays initiated from the master component. The
destination of this communication or slave is selected by a
unique device address or device ID transmitted at the begin
ning of the communication. Only the selected slave is alloWed
to ansWer the request of the master.
In complex systems it often happens that 2 devices have the
same device address or are even equal components With the 20 bus are transferred bit by bit. The data bit on the SDA line is
same device address. In this case a master’s request has
valid during the SCL line is high. During this high period of
the SCL line the SDA data line must be stable. If the SCL line
is loW state a change of the SDA data line is alloWed and the
SDA value is not valid.
alWays more than one slave, Which is reacting. This causes
violations on the bus and makes a communication impossible.
Possible solutions to solve these violations are:
1. Device dependent, hard coded slave address selection:
25
The usage of an extra input or inputs to a device alloWs
selecting betWeen different slave addresses the device is
transfer. The Start condition signals a start of data transfer
Whereas the stop condition terminates the bus transfer. A start
reacting on. Using equal devices on the same bus are
then distinguishable if the slave address selection input
is set different.
As illustrated in FIG. 4 prior art the I2C bus de?nes special
conditions called Start (S) and Stop (P) additionally to the bit
condition occurs When there is a transition of the SDA line
30
from high to loW While the SCL line is high. A stop condition
Disadvantage:
occurs if the SDA line goes from loW to high While the SCL
a. There need to be an extra pin on the component in case
35
line is asserted.
The master device generates the Start and Stop conditions,
Whereas data transfer can happen in both directions (read/
Write). Instead of termination a bus transfer With the stop
devices cannot be exchanged; e. g. having a stereo cam
era system With 2 identical cameras there is a need to 40
command an immediate neW transfer can be started by the
master With a repeated Start (SR) command as shoWn in FIG.
4 prior art. The repeated start command has the same charac
teristics as the normal Start condition.
The data transfer on the I2C bus, shoWn in FIG. 5 prior art,
the slave address selection is controlled from the system.
As these devices are getting smaller and smaller addi
tional pins/pads are not desirable.
b. There is no extra input pin to the device in case the slave
address selection input is hard Wired in the device (eg
chip bonding option). Having this scenario, identical
is done in byte packets (8 bit). The number of bytes that can be
separate the cameras during manufacturing. The cam
eras need to be held separately and cannot be exchanged.
transmitted in a transfer cycle is not restricted. Each byte is
transmitted With the most signi?cant bit (MSB) ?rst and each
This increase the logistic overhead for the system builds.
2. Programmable device address during startup:
This mechanism alloWs programming the device
45
byte is folloWed by an acknowledge toggle bit (ACK). The
device receiving the data bits sets the acknowledge bit (master
address of a slave via softWare. Possible implementa
sends data and the slave acknoWledges or slave sends data and
tions are:
master acknoWledges).
For the acknoWledge clock cycle the receiver of the data
a. Non-volatile memory in the device or component that
contain the slave address selection. The slave address
selection is read out by the device/ component by its oWn
byte must pull doWn the SDA line so that it is stable loW
50
at start up.
Disadvantage: Need for none-volatile memory compo
If a slave is not able to process a transfer or additional bytes
it leaves the SDA line in high state (not acknoWledge). In case
nent in the device. In addition same disadvantage as
under l.b)
b. Special startup strategy.
of a Write access the master has to start a neW transfer to Write
55
To avoid that 2 slaves react on a given device ID the
system could poWer up one device ?rst and reprogram
the device address (needs to be foreseen to alloW
reprogramming of slave address With the given con
trol bus). The second device With the same slave
during the high period of SCL. The acknoWledge cycle occurs
after each transmitted byte.
the data byte that Was not acknoWledged. If the slave trans
mits data to the master (read access) the master has to not
acknoWledge the last byte of the transfer to signal the slave to
release the data line. This alloWs the master to set a Stop or
Restart condition. AnyWay a not acknoWledged byte is fol
60
loWed by a stop or restart condition of the master device in any
address is not able to react on this request because it is
not yet poWered on. Thus no violation on the control
case.
bus can happen. After reprogramming the slave
nology is mentioned as 7-bit addressing in the speci?cation.
This invention can also be expanded to other addressing
FIG. 6 prior art illustrates a possible data transfer termi
address of the ?rst device the second one can be
poWered up. After this special startup the 2 devices
can be differentiated.
TWo Wire InterfaceiOvervieW
65
modes like the ones also mentioned in [l] and [2]. In this
mode a 7-bit address is sent by the master after the start/restart
condition. This 7-bit address selects the slave to be accessed.
US 8,667,204 B2
4
3
The eighth bit of the ?rst byte speci?es the data transfer
A further object of the invention is to achieve a method to
direction. A ‘0’ represent a Write access Whereas a ‘1’ indi
differentiate identical devices on a tWo-Wire interface Without
cates a read. Only the addressed slave, i.e. the slave With a
requiring any hardWare overhead.
transmitted and unique slave address is assigned to and is
A further object of the invention is to achieve a method to
allowed to react or ansWer the access.
differentiate identical devices on a tWo-Wire interface Without
It is a challenge for engineers to differentiate identical
requiring any softWare overhead.
devices on a tWo-Wire interface.
Moreover an object of the invention is to achieve a system
There are known patents or patent publications dealing
With master/ slave communication of tWo Wire interfaces:
US. Patent Publication (US 2009/ 0234999 to Huang et al.)
teaches an apparatus for resolving con?icts happening
to differentiate identical devices on a tWo -Wire interface With
out requiring any softWare or hardWare overhead.
In accordance With the objects of this invention a method to
differentiate identical devices on a tWo-Wire interface has
betWeen tWo I2C slave devices With the same addressed
devices, so as to achieve a purpose of loWering a cost for
been achieved. The method invented comprising, ?rstly, the
steps of: (1) providing a tWo-Wire communication system
address. The apparatus is composed by all cheap electronic
design. In addition, in the apparatus for resolving con?icts
comprising a SDA and a SCL lane, an I2C master and tWo
happened betWeen tWo I2C slave devices With the same
addressed address of the invention, all the I2C slave devices
are addressed by an I2C master device to perform the data
identical I2C slave devices, (2) connecting physically the
is connected by interchanging its SDA and SCL ports, and (3)
transmission subsequently before a basic input/output system
(BIOS) completes a poWer-on self-test (POST), but all the
I2C slave devices are addressed by a system chip (for
example, a baseboard management controller (BMC)) to per
performing signal connectivity check by detecting signal
SDA and SCL lanes to each slave device, Wherein each slave
20
connectivity by a slave device by interpreting information
transfer in normal and exchanged signal connectivity modes.
Furthermore the method comprises the steps of: (4) ?xing a
form the data transmission subsequently after the BIOS com
signal connectivity mode selection as soon as any correct
pletes the POST. Therefore, the purpose of performing the
slave device ID is detected, and (5) selecting detected correct
data transmission for all the I2C slave devices on real time is
achieved.
US. Patent Publication (US 2008/0288684 to Ellison) dis
closes a design structure to facilitate I2C communication
betWeen a host device and a slave device Where the slave
device shares a common physical address With another slave
device on the I2C bus. The design structure includes an appa
ratus, Which includes a detection module to detect an incom
25
been achieved. The system invented comprises, ?rstly: an I2C
30
nents, and complexities traditionally associated With
dynamic addressing techniques and other prior art solutions
control bus comprising a serial data line (SDA) lane and a
serial clock line (SCL) lane and at least tWo identical slave
devices. Each of the identical slave devices comprises: an I2C
slave module having a (SDA) port and a (SCL) port Wherein
ing address on the I2C bus, a translation module to translate
the incoming address to an outgoing address, and a commu
nication module to communicate data betWeen the host
device and the slave device Where the outgoing address
matches the physical address of the slave device. In this
manner, address con?icts betWeen commonly addressed
slave devices can be avoided While reducing costs, compo
slave ID for communication.
In accordance With the objects of this invention an I2C
interface system With slave devices connected to a tWo-Wire
control bus enabled to differentiate identical slave devices has
35
the SDA port is connected to a ?rst input port of a circuitry
interchanging SDA/SCL connections and the SCL port is
connected to a second input of said circuitry, said circuitry
connecting said ?rst input port to the SCL lane, to a SCL port
of a ?rst slave ID decoder, and to a SDA port of a second slave
ID decoder, and connecting said second input port to the SDA
lane, to a SDA port of a ?rst slave ID decoder, and to a SCL
40
to address con?icts.
port of a second slave ID decoder, said ?rst slave ID decoder,
and said second slave ID decoder.
US. Patent (US. Pat. No. 7,444,453 to Ellison) discloses a
method to facilitate I2C communication betWeen a host
device and a slave device Where the slave device shares a
common physical address With another slave device on the
BRIEF DESCRIPTION OF THE DRAWINGS
45
I2C bus. The method includes detecting an incoming address
on the I2C bus, translating the incoming address to an outgo
FIG. 1 prior art shoWs an I2C control bus using 2 lanes, a
data lane (SDA) and a clock lane (SCL).
FIG. 2 prior art shoWs an Open-Drain/Open-Collector cir
ing address, and communicating data betWeen the host device
and the slave device Where the outgoing address matches the
physical address of the slave device. In this manner, the
present invention avoids address con?icts betWeen com
In the accompanying draWings forming a material part of
this description, there is shoWn:
50
monly addressed slave devices While reducing costs, compo
nents, and complexities traditionally associated With
dynamic addressing techniques and other prior art solutions
cuit of an I2C bus.
FIG. 3 prior art shoWs different states of the SDA and SCL
lines of an I2C bus, i.e. When data line is stable and valid and
describe addressing
When change of data is alloWed.
FIG. 4 prior art illustrates that the I2C bus de?nes special
conditions called Start (S) and Stop (P) additionally to the bit
transfer
[1] UM10204, I2C-bus speci?cation and user manual, Rev.
03-19 June 2007, NXP B.V,
FIG. 5 prior art shoWs the data transfer on the I2C bus.
FIG. 6 prior art shoWs a 7-bit address sent by the master
after the start/restart condition.
to address con?icts.
55
Furthermore tWo publications
schemes of tWo Wire interfaces:
[2] The I2C-bus speci?cation; version 2.1, January 2000,
Philips Semiconductors.
60
FIG. 7 illustrates basic principles of the present invention,
namely the device invented alloWing connecting tWo slave
devices to the 2 lines SDA and SCL interchanged.
SUMMARY
A principal object of the present invention is to achieve a
FIG. 8a shoWs a schematic of a preferred embodiment of
the device invented.
65
FIG. 8b illustrates the state of 2 identical devices on the
method to differentiate identical devices on a tWo -Wire inter
same bus after decoding the connectivity and assignment of
face.
the selected device ID.
US 8,667,204 B2
6
5
At star‘tup the switch position of switching circuitry 81 is
FIG. 9 illustrates a ?owchart of a method invented to dif
ferentiate identical devices on a two-wire interface.
unknown. The decoders 82 and 83 decode interchangeably
the transfer sequence on both SDA/SCL lanes with transmis
sion of the slave address and forward the decode status to the
slave module 80. Both decoders check if they see a correct
device ID transmission sequence on the bus. If one of the
decoders detects this sequence the device locks and will have
DESCRIPTION OF THE PREFERRED
EMBODIMENTS
Methods and systems to differentiate identical devices on a
the device ID A (or ID B depending on which decoder has
two-wire interface are disclosed. The present invention dis
closes a way to differentiate those identical devices on one
seen the sequence). As soon as one of the decoders detects the
control bus without any additional hardware, as eg addi
tional ID pins) or software overhead.
correct sequence the switching circuitry 81 is set and ?xed.
This means that the connectivity of the device to the I2C
bus lines SDA and SCL decides whether the device reacts on
device ID A or device ID B.
FIG. 8b illustrates the state of two identical devices 80 on
FIG. 7 illustrates basic principles of the present invention.
The device invented allows connecting two slave devices to
the 2 lines SDA and SCL interchanged. It is up to the slaves to
the same bus after decoding the connectivity and assignment
detect the signal connectivity to be used for communication
with the master. Based on the detected signal connectivity the
slave address can be selected by the slave device itself. This
allows a signal connectivity of two identical devices. FIG. 7
shows possible connections of such devices in a system. Each
of the selected device ID.
The switching circuitry 81 needs to know which slave
decoder has seen the correct sequence on the bus and need to
switch the connectivity to circuitry 80 accordingly.
20
I2C slave has two Slave ID decoders, signi?ed by IDA and ID
B.
The slave devices detect the signal connectivity by inter
preting the I2C transfer in normal and interchanged connec
tivity as illustrated also in FIG. 8.
25
The I2C slave circuitry 80 is not able to react on accesses
until the correct connectivity is evaluated. The correct con
nectivity is evaluated after the ?rst device ID is transmitted on
the bus. If the ?rst device ID on the I2C bus is the one which
is assigned to this device the circuitry 80 has to react imme
diately (send acknowledge) although it does not know which
device ID was transmitted. This information needs to be
As soon as any correct device ID transmission is detected
in one of the modes, i.e. normal or interchanged, the signal
forwarded from the decoder to circuitry 80 to allow proper
connectivity is known and the signal connectivity selection is
?xed. Up from this point of time the connection for the I2C
reaction also for the case that the ?rst access on the I2C bus
lanes is known and the correct slave is selected. The trans
targets this device.
30
mitted slave device ID for the signal connectivity check does
not need to be one of the IDs intended for that device; fur
thermore any valid slave device ID even from other connected
components can be used for the signal connectivity check
detection.
35
Both slaves establish the communication at the same time.
All slaves see the I2C communication while only one slave
reacts on master requests. Thus, if there is any device ID
transmission on the bus, both slaves detect the connectivity
and know which device ID is assigned to it (but only the
Any device decoding this sequence with interchanged
SDA/SCL lane connections is recognizing either a star‘t/ stop
event within the transmission and needs to restart its internal
state machine or the correct connected decoder is seeing a
valid sequence. Because any valid sequence freeZes the con
nectivity selection a long-term accumulation of events emu
lating a slave address transmission on the interchanged
changed connection is avoided.
Thus 2 identical devices or components can be connected
to the same bus without any hardware or software (power up
40
strategy) overhead. The devices can be used immediately
device, which has the transmitted device ID, assigned
with their device ID assigned and selected by the connectivity
answers/reacts on the access. The other devices do not react
of the I2C lanes.
on the access but they also know their connectivity/assigned
FIG. 9 illustrates a ?owchart of a method invented to dif
ferentiate identical devices on a two-wire interface.
device ID from this point of time).
This mechanism is su?icient to establish a correct commu
45
nication as described by the following process steps describ
ing a valid I2C transfer sequence with transmission of the
slave address
SCL lane, an I2C master and two identical I2C slave devices.
Step 91 depicts connecting physically the SDA and SCL lanes
1. Start condition (restart condition)
2. 7 bit slave address transmission
3. R/W bit transmission
50
connectivity by a slave device by interpreting information
transfer in normal and exchanged connectivity modes. Step
It should be noted that a valid I2C transfer sequence is not
limited to 7 bit addressing, e.g. there is also a 10 bit addressing
55
10 bits) are transmitted in the same way.
FIG. 8a shows a schematic of a preferred embodiment of
the device invented. The device invented comprises a slave
device 80 as eg a camera being a part of a stereo camera
system, a switching circuitry 81 interchanging the connec
tions between the slave device 80 and the SDA/SCL lines, a
slave ID decoder A 82 and a slave ID decoder B 83. Each
decoder has two inputs, a SDA input and a SCL input. The
SDA input of the decoderA 82 is connected to the SDA line
and to the SCL input of the decoder B 83. The SCL input of
the decoderA 82 is connected to the SCL line and to the SDA
input of the decoder B 83.
to each slave device, wherein each slave is connected by
interchanging its SDA and SCL ports. Step 92 illustrates
performing signal connectivity check by detecting signal
4. ACK cycle
given in the I2C speci?cation. But there the ?rst 7 bits (of the
Step 90 of the method of FIG. 9 illustrates the provision of
a two-wire communication system comprising a SDA and a
60
93 shows ?xing a signal connectivity mode selection as soon
as any correct slave device ID is detected and, ?nally, step 94
illustrates selecting detected correct slave ID for communi
cation.
While the invention has been particularly shown and
described with reference to the preferred embodiments
thereof, it will be understood by those skilled in the art that
various changes in form and details may be made without
departing from the spirit and scope of the invention.
65
What is claimed is:
1. A method to differentiate identical devices having a
same device address on a two-wire interface, comprising the
following steps:
US 8,667,204 B2
8
7
(1) providing a tWo-Wire communication system compris
ing a SDA lane and a SCL lane, an 12C master and tWo
an 12C control bus including a serial data line (SDA) lane
and a serial clock line (SCL) lane;
identical I2C slave devices having the same device
a ?rst and second slave devices each associated With a same
?rst device address and having a ?rst and second slave
address;
device inputs, the ?rst slave device having the ?rst slave
device input connected to the SDA lane and the second
slave device input connected to the SCL lane, the second
slave device having the ?rst slave device input connected
(2) connecting physically the SDA and SCL lanes to each
slave device, Wherein a SDA port of a ?rst slave device
is connected to the SDA lane and a SCL port of the ?rst
slave device is connected to the SCL lane and a SDA port
of a second slave device is connected to the SCL lane and
a SCL port of the second slave device is connected to the
to the SCL lane and the second slave device input con
nected to the SDA lane, each of the ?rst and second slave
devices, comprising:
SDA lane;
a ?rst slave decoder having a ?rst SDA input connected
to the ?rst slave device input and a ?rst SCL input
connected to the second slave device input and a ?rst
decode output, the ?rst slave decoder detecting a ?rst
signal connectivity on the SDA lane and the SCL lane
and generating a ?rst decode status output on the ?rst
(3) performing signal connectivity check by detecting sig
nal connectivity on the SDA lane and the SCL lane With
the ?rst and second slave devices by interpreting infor
mation transfer in normal and exchanged signal connec
tivity modes; and
(4) connecting a ?rst 12C slave module in the ?rst slave
decode output responsive to detection of the ?rst sig
device and a second I2C slave module in the second slave
device to the SDA lane and the SCL lane in a ?rst
con?guration responsive to detecting the information
nal connectivity;
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transfer in the normal signal connectivity mode and in a
SCL input connected to the ?rst slave device input and
second con?guration responsive to detecting the infor
mation transfer in the exchange signal connectivity
mode.
2. The method of claim 1 Wherein the signal connectivity
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check is performed by transmitting slave device IDs.
SDA lane and a second input connected to the SCL
the signal connectivity check detection.
30
5. The method of claim 1 Wherein the information transfer
comprises an 12C transfer sequence With transmission of the
?rst decode status output and the second decode status
35
output;
an I2C slave module having the ?rst device address asso
ciated thereWith and having an SDA input port con
nected to the ?rst output of the sWitching circuitry and an
(2) at least a 7 bit slave address transmission;
(3) Read/ Write bit transmission; and
(4) acknowledgement (ACK) cycle.
SCL input port connected to the second output of the
6. The method of claim 5 Wherein any Wrongly connected
slave device decoding the 12C transfer sequence recogniZes a
start/ stop event Within the information transfer and restarts its
internal state machine.
7. The method of claim 5 Wherein a correctly connected
decoder of a slave device recogniZes the information transfer.
8. The method of claim 5 Wherein any valid information
lane, the sWitching circuitry further having ?rst and
second outputs, Wherein the ?rst input and the second
input are selectively connected to the ?rst output and
the second outputs, respectively, responsive to the
lish communication at the same time.
slave address comprising:
(1) a start/restart condition;
a second decode output, the second slave decoder
detecting a second signal connectivity on the SDA
lane and the SCL lane and generating a second decode
status output on the second decode output responsive
to detection of the second signal connectivity;
sWitching circuitry having a ?rst input connected to the
3. The method of claim 2 Wherein any valid slave device
ID, even from other connected components, can be used for
4. The method of claim 1 Wherein both slave devices estab
a second slave decoder having a second SDA input con
nected to the second slave device input and a second
sWitching circuitry.
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11. The system of claim 10 Wherein both ?rst and second
decoder decode interchangeably the transfer sequence on
both SDA/SCL lanes With transmission of the slave device
address and forWard the decode status to the slave module.
12. The system of claim 10 Wherein at startup the sWitch
transfer detected freeZes the signal connectivity selection.
position of sWitching circuitry is unknown.
9. The method of claim 5 Wherein a 10-bit slave address
transmission is used.
10. An 12C interface system for use With slave devices
having a same device address, comprising:
decoders detects the ?rst or the second signal connectivity, the
sWitching circuitry is set and ?xed.
13. The system of claim 10 Wherein, as soon as one of the
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