LCD Module User Manual - Solar LED lighting,LED lighting,LCD

LCD Module User Manual - Solar LED lighting,LED lighting,LCD

LCD Module User Manual

Customer :

MASS PRODUCTION CODE : TC1602J-01WD0

DRAWING NO. : m-TC1602J-01WD0_A00

Approved By Customer:

Date:

Approved By Checked By Prepared By

Vatronix Holdings Limited

ADD:5F,No.10 Blg,WenGuang Industrial Zone,XiLi,Nanshan District,Shenzhen,China

TEL:0086-755-83234801 33207538 FAX:0086-755-33207539

E-mail:[email protected] Http://www.vatronix.com

TC1602J-01WD0_A00 Page 1 of 29

Contents

1. Precautions in Use of LCD Module-----------------------------------P3

2. General Specification-------------------------------------------------------P3

3. Absolute Maximum Ratings----------------------------------------------P3

4. Electrical Characteristics--------------------------------------------------P4

5. Backlight Information-------------------------------------------------------P4

6. Optical Characteristics-----------------------------------------------------P5

7. Interface Description--------------------------------------------------------P6

8. Contour Drawing & Block Diagram--------------------------------------P7

9. Application circuit-----------------------------------------------P8

10. LCM Function Description-----------------------------------------------P8

11. User instruction Definitions--------------------------------------------P10

11.1 Instruction table----------------------------------------------------P10

11.2 Instruction description --------------------------------------------P12

12. Interfacing to the MPU ----------------------------------------------P17

13. Timing Characteristics -------------------------------------------------P20

14. Reset Function -----------------------------------------------------------P24

15. Initializing flow chart ----------------------------------------------------P25

16. Standard Character pattern--------------------------------------------P28

17.Revision records------------------------------------------------------P29

TC1602J-01WD0_A00 Page 2 of 29

1. Precautions in Use of LCD Module

(1) Avoid applying excessive shocks to the module or making any alterations or modifications to it.

Module.

(6) Soldering: only to the I/O terminals.

(7) Storage: please storage in anti-static electricity container and clean environment.

2. General Specification

ITEM STANDARD VALUE UNIT

Number of dots

Outline dimension

View area

Active area

16X2 CHARs

84.0(W)X44.0(H)X12.8MAX.(T)

65.0(W)X16.0(H)

56.21(W)X11.5(H)

Dots mm mm mm

Dot size

Dot pitch

LCD type

View direction

0.56(W)X0.66(H)

0.60(W)X0.70(H) mm mm

STN, Yellow-green,positive,Transflective

Backlight

MPU interface

DC-DC invertor

3. Absolute Maximum Ratings

ITEM SYMBOL

Operating Temperature

Storage Temperature

Input Voltage

Supply Voltage For Logic

Supply Voltage For LCD

LED, White

4-SPI (Default status) Option:Parallel or 3-SPI

None

T

OP

T

ST

V

I

V

DD

V

DD

-V

EE

MIN.

-20

-30

0

0

0

TYP.

-

-

-

-

-

MAX.

+30

+80

V

DD

5.5

5

UNIT

V

V

V

TC1602J-01WD0_A00 Page 3 of 29

4. Electrical Characteristics

ITEM SYMBOL CONDITION MIN. TYP. MAX. UNIT

Logic Voltage V

DD

-V

SS

Supply Volt.For LCD V

DD

-V

O

-

4.7

---

5.0 5.2

---

V

V

Input High Volt.

Input Low Volt.

V

IH

V

IL

Ta=25℃

-

-

2.0

-0.3

4.5

-

-

V

DD

0.8

V

V

Output High Volt. V

OH

I oH

=-0.2mA

2.4

-

Output Low Volt. V

OL

I oL

=1.6mA

0

-

Supply Current I

DD

-

--- 1.0

5. Backlight Information

Absolute Maximum ratings

(

Ta=25

℃)

Item Symbol Conditions

Reverse voltage

Reverse Current

Vr

I r

-

Vr=5.0V

Absolute maximum forward Current Ifm

Peak forward current Ifp

I msec plus 10% Duty Cycle

Power dissipation

Operating Temperature Range

P d

T oper

Storage Temperature Range Tst

Electrical/Optical Characteristics (Ta=25

0

C,If=40mA)

Color

Wavelength

λp(nm)

Spectral line half widthΔλ(nm)

Operating

Voltage(V)

(±0.15V)

White --- --- 3.1

V

DD

0.4

---

Rating Unit

5.0

80

100

240

V uA mA mA

340 mW

-30~+70 ℃

-40~+80

Forward

Current (mA)

30

V

V mA

TC1602J-01WD0_A00 Page 4 of 29

6. Optical Characteristics

ITEM SYMBOL CONDITION MIN TYP MAX

View Angle (V)θ

(H)φ

Contrast Ratio CR

CR≧2

CR≧2

10

-45

120

45

5

Response

Time

T rise

T fall

200 300

150 200

UNIT deg. deg.

- ms ms

TC1602J-01WD0_A00 Page 5 of 29

7.Interface Description

Parallel mode(Jps shorted to “P”)

Pin No. Symbol

1

2

3

4

V

V

SS

DD

V

O

RS(D/I,A0)

5

6

RW

E

7~14 DB0~DB7

15 A(LED+)

16 K(LED-)

17

18

/RST

PSB

Level Description

0V Ground

+5.0V Power supply for Logic

(Variable) Driving voltage for LCD

H/L H:Data L :Instruction

H/L

H/L

H:Read L:Write

Enable signal

H/L Data bus. DB7 is used for Busy Flag .

+5.0V Anode of LED Backlight

0V Cathode of LED Backlight

L

H

Active low

Interface type selection,H: Parallel interface

4-SPI mode(Jps shorted to “S”, Default status )

Pin No. Symbol

1

2

V

V

SS

DD

3

4

5

6~11

12

13

14

15

16

17

18

V

O

RS(D/I,A0)

V

SS

VDD

CS(DB5)

SCL(DB6)

SID(DB7)

A(LED+)

K(LED-)

/RST

PSB

Level

0V

+5.0V

(Variable)

H/L

0V

+5.0V

L

H/L

H/L

+5V

0V

L

L

Description

Ground

Power supply for Logic

Driving voltage for LCD

H:Data L :Instruction

Ground

VDD

Chip select, active low

Serial clock input

Serial data input

Anode of LED Backlight

Cathode of LED Backlight

Active low

Interface type selection,L: Serial interface

3-SPI mode(Jps shorted to “S”,Default status)

Pin No.

1

2

3

4~5

6~11

12

13

14

15

16

17

18

Symbol

V

SS

V

DD

V

O

V

SS

VDD

CS(DB5)

SCL(DB6)

SID(DB7)

A(LED+)

K(LED-)

/RST

PSB

Level

0V

+5.0V

(Variable)

0V

+5.0V

L

H/L

H/L

+5.0V

0V

L

L

Description

Ground

Power supply for Logic

Driving voltage for LCD

Ground

VDD

Chip select, active low

Serial clock input

Serial data input

Anode of LED Backlight

Cathode of LED Backlight

Active low

Interface type selection,L: Serial interface

TC1602J-01WD0_A00 Page 6 of 29

8. Contour Drawing & Block Diagram

TC1602J-01WD0_A00 Page 7 of 29

9.Application circuit

10. LCM Function Description

The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR).

The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from

DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected.

Various Kinds of Operations according to RS and R/W Bits

RS R/W Operation

0

0

0 IR write as an internal operation (display clear, etc.)

1 Read busy flag (DB7) and address counter (DB6 to DB0)

1 0 Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)

1 1 Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)

Busy Flag (BF)

When the BF= "High", it indicates that the LCM internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.

Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.

After writing into (reading from) DDRAM/CGRAM, AC is automatically increased

(decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 -

DB6 ports.

TC1602J-01WD0_A00 Page 8 of 29

Display Data RAM (DDRAM)

This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80x8 bits,or 80 charcters.Below figure is the relationships between

DDRAM addresses and positions on the liquid crystal display.

High bits Low bits

Example: DDRAM addresses 4E

AC (Hexadecimal)

AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0

LCM DDRAM Address(In HEX)

16 Chars X 2 Lines Display

No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 st

Line 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

2 nd

Line 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

Character Generator ROM (CGROM)

The CGROM generate 5×8 dot or 5×10 dot character patterns from 8-bit character codes.

See “Standard Character pattern”.

Character Generator RAM (CGRAM)

In CGRAM, the user can rewrite character by program. Relationship between Character

Code (DDRAM) and Character Pattern (CGRAM) shown below

Char Code(DDRAM data) CGRAM address CGRAM data

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0 X 0 0 0 0 0 0 0 0 0 X X X 0 1 1 1 0

.

.

.

.

.

.

.

.

.

.

.

.

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

.

.

.

.

.

.

1 0 0 0 1

1 0 0 0 1

1 1 1 1 1

1 0 0 0 1

1 0 0 0 1

1 0 0 0 1

.

.

.

.

.

.

.

.

1 1 1

.

.

.

.

0 0 0 0 0

.

.

.

0 0 0 0 X 1 1 1 1 1 1 0 0 0 X X X 1 0 0 0 1

0 0 1

0 1 0

1 0 0 0 1

1 0 0 0 1

.

.

.

.

.

.

.

.

.

.

.

.

.

. 0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

.

.

.

.

.

.

. 1 1 1 1 1

1 0 0 0 1

1 0 0 0 1

1 0 0 0 1

0 0 0 0 0

Pattern number

Pattern 1

.

.

.

Pattern 8

“X”: don’t care

TC1602J-01WD0_A00 Page 9 of 29

11. User instruction Definitions

11.1 Instruction table

This LCM can select basic or extended instruction set by “Function set” Instruction,see detail in “Function set” description.When EXT=0,only basic instruction can be executed,

When EXT=0,only basic instruction can be executed,

When EXT=1,only extended instruction can be executed,

Instruction

Instruction Code

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Execution time f

OSC

=270KHz)

EXT=0 or EXT=1(Can be executed both in basic or extended instruction mode)

Clear

Display

Return

Home

Display

ON/OFF

Cursor or

Display Shift

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

D

S/C R/L

0

1

C

X

1

X

B

X

Write “20H” to DDRAM and set DDRAM address to “00H” from AC.

Set DDRAM address to

“00H” from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed.

Set display(D), cursor(C), and blinking of cursor(B) on/off control bit.

Set cursor moving and display shift control bit, and the direction, without changing DDRAM data.

Function Set 0

Read Busy

Flag and

Address

Write Data to

RAM

0 0 0 1 DL N F X X

Set interface data length(DL:4-bit/8-bit), numbers of display line(N:

1-line/2-line), display font type(F: 5X8 dots/ 5X11 dots)

Whether during internal operation or can not be

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. The

1 0 D7 D6 D5 D4 D3 D2 D1 D0 contents of address counter can also be read.

Write data into internal

RAM DDRAM/CGRAM).

1.52ms

0µ s

37µ s

37µ s

37µ s

0µ s

37µ s

Read Data from RAM

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read data from internal

RAM (DDRAM/CGRAM).

37µ s

EXT=0 (Can be executed in basic instruction mode only)

Entry Mode

Set

0 0 0 0 0 0 0 1 I/D SH

Sets cursor move direction and specifies display shift.

These operations are performed during data write and read.

37µ s

Set CGRAM

Address

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Set CGRAM address in address counter.

37µ s

Set DDRAM

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM address in address counter.

37µ s

Address

Remark:‘X’don’ t care

TC1602J-01WD0_A00 Page 10 of 29

Instruction

Instruction Code

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

EXT=1 (Can be executed in extended instruction mode only)

Bias resistor select

COM,SEG direction select

Set display data length

Used internal resister only provide 1/5 bias mode

0 0 0 0 0 0 0 1 Rb1 Rb0

Rb[1:0]=00-> External

Resister.

Rb[1:0]=01~11->Internal

Resister

0

0

0

0

0

1

0

L6

0

L5

0

L4

C1 C2 S1 S2

L3 L2 L1 L0

C1:COM1~8-> COM8~1

C2:COM9~16-> COM16~9

S1:SEG1~40->SEG40~1

C2:SEG41~80->SEG80~41

To specify the number ofdata bytes(3-wire SPI mode)

Execution time f

OSC

=270KHz)

37µ s

37µ s

37µ s

Note:

In the parallel Interface,be sure the LCM is not in the busy state (BF = 0) before sending an instruction from the MPU to the LCM. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time.

TC1602J-01WD0_A00 Page 11 of 29

11.2 Instruction Description

EXT=0 or EXT=1(Can be executed in basic or extended instruction mode)

1)Clear Display

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set

DDRAM address to "00H" into AC (address counter). Return cursor to the original status.

Namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1").

2) Return Home

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 1

-

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM do not change.

3) Display ON/OFF

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 1 D C B

Control display / cursor / blink ON / OFF 1 bit register.

D: Display ON / OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C: Cursor ON / OFF control bit

When C = "High", cursor is turned on.

When C = "Low", Cursor is disappeared in current display, but I/D register remains its data.

B: Cursor Blink ON / OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position.

When B = "Low", blink is off.

4) Cursor or Display Shift

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 S/C R/L - -

Shifting of right/left cursor position or display Without Writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data.

(refer to Table 4) During 2-line mode display, cursor moves to the 2nd line after 40th digit of

1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed.

S/C R/L Operation

0

0

1

1

0 Shift the cursor to the left, AC is decreased by 1.

1 Shift the cursor to the right, AC is increased by 1.

0 Shift all the display to the left, cursor moves according to the display.

1 Shift all the display to the right, cursor moves according to the display.

5) Function Set

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 DL N EXT - -

TC1602J-01WD0_A00 Page 12 of 29

DL: Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

N: Display line number control bit

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

EXT: Select basic or extended instruction set

Entry Mode Set’ Set CGRAM address’

DDRAM address’ can be performed , when EXT=”H” the commands ‘Bias resistor select’ , ‘COM、SEG direction select’ and ‘Set display data length’ can be performed.

Other command can be executed in both cases.

6) Read Busy Flag & Address

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

This instruction shows whether LCM is in internal operation or not. If the resultant BF is

High, it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter.

7) Write data to RAM

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction:

DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.

8) Read data from DDRAM or CGRAM

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without

RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer

RAM data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly.

* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.

TC1602J-01WD0_A00 Page 13 of 29

EXT=0 (Can be executed in basic instruction mode only)

9)Entry Mode Set

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 1 I/D SH

Set the moving direction of cursor and display.

I/D: Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM operates the same as DDRAM, when read from or write to CGRAM.

SH: Shift of entire display

When DDRAM read (CGRAM read / write) operation or SH = "Low", shift of entire display is not performed. If SH = "High" and DDRAM write operation, shift of entire display is performed according to I/D value:

I/D ="1" : shift left,

I/D = "0" : shift right.

10) Set CGRAM Address

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1

AC5 AC4 AC3 AC2 AC1 AC0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

11) Set DDRAM Address

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0),

DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address is the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to

"67H".

TC1602J-01WD0_A00 Page 14 of 29

EXT=1 (Can be executed in extended instruction mode only)

12) Bias resistor select

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

0 0 0 1 Rb1

Rb0

This LCM controller built-in internal bias resistor,set by follow table

Rb1 Rb0

0 0

Description

External bias resistor select.

0

1

1

0

Build-in resistor select (R=2.2K).

Build-in resistor select (R=6.8K).

1 1 Build-in resistor select (R=9.0K).

13) COM,SEG direction select

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

0 0 C1 C2 S1

S2

The SEG and COM output in this LCM all have bi-direction control by the register.

COM output:

COM output

C1

0

1

COM1------------COM8

COM1->Common address->COM8

COM8->Common address->COM1

COM output

C2

0

1

COM9------------COM16

COM19->Common address->COM16

COM16->Common address->COM9

SEG output:

SEG output

S1

0

1

SEG output

S2

0

1

SEG1------------SEG40

SEG1-> Segment Address->SEG40

SEG40-> Segment Address->SEG1

SEG41------------SEG80

SEG41-> Segment Address->SEG80

SEG80-> Segment Address->SEG41

14) Set display data length(Only in 3line-SPI interface)

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 L6 L5 L4 L3 L2 L1

L0

L6 L5 L4

0

0

0

0

0

0

L3

0

0

L2

0

0

L1

0

0

L0

0

1

… … … … … …

1 0 0 1 1 1

0

1 0 0 1 1 1

1

Data length

1

2

79

80

TC1602J-01WD0_A00 Page 15 of 29

Only in 3line-SPI interface will use the register to set the number of display data(Max=4F).

To write data to DDRAM , send Data Direction Command in 3-pin SPI . Data is latched at the rising edge of SCLK . And the DDRAM column address pointer will be increased by one automatically.

TC1602J-01WD0_A00 Page 16 of 29

12.Interfacing to the MPU

The LCM can send data in either two 4-bit operations or one 8-bit operation or serial operation, thus allowing interfacing with 4- or 8-bit or serial MPU. l For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer.

Bus lines DB0 to DB3 are disabled. The data transfer between the ST7070 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data.

Example of busy flag check timing sequence

Intel 8051 interface

TC1602J-01WD0_A00 Page 17 of 29

l For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

Example of Busy Flag check timing sequence

Intel 8051 interface

TC1602J-01WD0_A00 Page 18 of 29

l For serial interface data, bus lines (DB5 to DB7) are used. 4-Pin SPI

Example of timing sequence

Intel 8051 interface

l For serial interface data, bus lines (DB5 to DB7) are used. 3-Pin SPI

Example of timing sequence

Intel 8051 interface

TC1602J-01WD0_A00 Page 19 of 29

13. Timing Characteristics

l Parallel Interface Write/Read by MPU l Writing data from MPU to LCM (Serial)

TC1602J-01WD0_A00 Page 20 of 29

TC1602J-01WD0_A00 Page 21 of 29

TC1602J-01WD0_A00 Page 22 of 29

TC1602J-01WD0_A00 Page 23 of 29

14. Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the LCM when the power is turned on or hardware reset pin has low. The following instructions are executed during the initialization.

The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V.

1.Display clear

2.Function set:

DL = 1; 8-bit interface data

N = 1; 2-line display

EXT=0;disable extension instruction.

3. Display on/off control:

D = 0; Display off

C = 0; Cursor off

P = 0; Page 1 of font table(DDRAM data b8=0)

4. Entry mode set:

I/D = 1; Increment by 1

S = 0; No shift

5. Bias resistor select:

Rb1=0;Rb2=0 select external bias resistor.

6. COM、SEG direction select:

C1=0;C2=0;S1=0;S2=0 not reverse.

Note:

If the electrical characteristics conditions listed under the table Power Supply Conditions

Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the LCM. For such a case, initialization must be performed by the

MPU as explain by the following figure.

Note: l t

OFF

compensates for the power oscillation period caused by momentary power supply oscillations. l Specified at 4.5V for 5V operation,and at 2.7V for 3V operation. l For if 4.5V is not reached during 5V operation,teh internal reset circuit will not operate normally.

TC1602J-01WD0_A00 Page 24 of 29

15.Initializing flow chart

l 8-bit interface mode(fosc=270KHz)

TC1602J-01WD0_A00 Page 25 of 29

l

TC1602J-01WD0_A00 Page 26 of 29

l Serial Interface (fosc=270KHz)

TC1602J-01WD0_A00 Page 27 of 29

16. Standard Character pattern

TC1602J-01WD0_A00 Page 28 of 29

17. Revision records

Version Ref.pages

A00

Reversion

Items

All Pages New release

Date

2010.08.25

TC1602J-01WD0_A00 Page 29 of 29

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