` E: *
USOO5802318A
.
Umted States Patent [19]
[11] Patent Number:
5,802,318
Murray et al.
[45] Date of Patent:
Sep. 1, 1998
[54] UNIVERSAL SERIAL BUS KEYBOARD
Microprocessor and Peripheral Handbook vol. 11 Peripheral
SYSTEM
by Intel®, 1988, pp. 5—55 to 5-74.
[75] Inventors: David E. Murray, Houston; David R.
Wooten, Spring; Randall L. Hess,
Universal Serial Bus Speci?cation by Compaq, Digital
Equipment Corporation, IBM PC Company, Intel,
Microsoft, NBC, Northern Telecom, Revision 0.9, Apr. 13,
1995_
CYPWSS; Christopher C- Wanner,
Tomball; Je?' W. Wolford, Spring, all
of Tex.
ACCESS.bus TM microcontroller 83C542/87C542 Phillips
[73] Assigllec! Compaq Compute!‘ Corpom?o?,
Semiconductors Objective Speci?cation, pp. 1-22, Apr. 3,
Houston, Tex.
1995_
[21] Appl. No.: 506,884
[22] H1 4
Jul 25 1995
e :
.
[51] Int. 01.6
[52] US. Cl.
soar 3100-, G06F 9/46
395/280; 395/868; 395/133;
395,500
395/280, 828,
A keyboard system according to me Present invention
395/733’ 866* 868’ 500’ 835» 838
,
References Cm“!
includes a serial bus host controller coupled to a serial bus
keyboard. The keyboard includes both keyboard scan logic
and scan code conversion logic for passing to the host
[58] Field of Search
[561
Primary Examiner—Glenn A. Auve
Attorney Agent, or Firm-Pravel, Hewitt, Kimball &
,
Krieger
[57]
U,S, PA'I'ENT DOCUMENTS
ABSTRACT
controller ova’ the serial bus. The host controller includes
circuitry for processing the data between the serial bus and
131327);
MK".was
a host bus. The host controller further includes 8042 emu
s,s90,31s 12/1996 Hess et al.
395/500
M0" 1°89: f0‘ Pmvlding ‘1 hardware °°mPanbl° Mm ‘1°
the keyboard controlla. The 8042 emulation logic also
OTHER PUBLICATIONS
Pentiumm Processor User’s Manual voL 3: Architecture and
includes circuitry for communicating over the serial bus
mg m“ when the 561m bus has not Yet bccn "Immed
Programming Manual by Intel®, 1993 (Chapters 1-4, 9-15,
20 and 22).
33 Claims, 10 Drawing Sheets
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US. Patent
Sep.1,1998
Sheet 2 of 10
5,802,318
KEYBOARD&
MDUSEIRUs
4:410
PCIHF
“200
J
/130
204
HOST
‘202
8042
?grgsglg?
EMULATION
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cnuvsnsmu
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PORTS '’216
MOUSE
FIG. 2
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SCAN
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US. Patent
Sep.1,1998
Sheet 8 of 10
530“ i
HOST CONTROLLER
RECEIVES PACKET
632
TO
KAR OR MAR
6363
PROCESS OTHER
PACKETS
FIG. 6A
550-\ i
CPU READS SM!
STATUS REGISTER
655-\
PLACE DATA INTO
KOB; SET KSRI
SIMULATE
IRO WITH INT
FIG. 6B
PROCESS OTHER
INTERRUPTS
5,802,318
US. Patent
Sep. 1, 1998
5,802,318
Sheet 9 0f 10
603 \
OTHER
SMI
OPERATIONS
608 \
606 \
WRITE PORT
DATA TO
HARDWARE
PORTS
510 -\
A
SET KSR
FIG. 6C
WRITE KEYBOARD
OR MOUSE DATA
TO HOST
CONTROLLER
US. Patent
Sep. 1, 1998
Sheet 10 0f 10
5,802,318
HOST
CONTROLLER
BENERATES
INTERRUPT
6 72
CPU READS
HIE INTERRUPT
STATUS
674
676‘
PLACE DATA
mm KOB: SET
KSR; SIMULATE
Inn wnu INT
FIG. 60
f‘ 678
PROCESS
OTHER
INTERRUPTS
5,802,318
1
2
UNIVERSAL SERIAL BUS KEYBOARD
SYSTEM
Information is broadcast over the serial bus system from
the host controller in a series of packets, with the host
controller acting as the bus master and hubs and devices only
responding upon request or polling access of the host
BACKGROUND OF THE INVENTION
controller. The packet types include data packets, token
1. Field of the Invention
packets for use from host to device, a handshake packet and
a special conn'ol packet. Data packets are the isochronous,
The invention relates to a keyboard and pointing device
system in the serial bus environment, and more speci?cally
to a serial bus host controller having an 8042 compatible
asynchronous block, and asynchronous control types. Token
packets allow transfer of data packets. Handshake packets
interface and special control logic for communicating with
are used to perform a ready handshake after transfer of a data
a serial bus keyboard and pointing device prior to the
initialization of serial bus services.
2. Description of the Related Art
Computer systems are becoming ever more powerful with
each passing moment. Many new advanced bus structures
such as the PCI or Pm'ipheral Component Interchange bus
have been developed to allow greater performance of the
or control packet to acknowledge successful receipt or
indicate unsuccessful receipt. Special control packets are
used for logical reset and status request transfers. Each
function or device has a logical address. Packets are sched
uled into queues for n'ansmission over the serial bus in a
time division multiplexed fashion.
Each device and port on a hub or the host controller
computer system Additionally, new devices and uses are
includes the capabilities to handle the low level bus transfer
being developed for the computer systems. In the past the
protocol between the particular node of the appropriate hub
and the device itself. Thus, a relatively simple transfer
protocol, with a limited number of packet types is de?ned.
computer has been essentially a stand-alone device or net
worked with othm' computer systems. However, today the
modern personal computer is becoming a much more con
nected and multimedia oriented system. For example, now
high speed video and audio functions are becoming com
The hubs act as wiring concentrators and enable the
attachment of multiple serial bus devices to the serial bus. A
hub repeats incoming tra?c from any enabled port by
broadcasting the tra?ic transparently to all other enabled
monplace and the integration with the telephone system has
already begun.
ports on the hub. As a result, the tree structured interconnect
topology appears as a ?at “virtual bus” with no store-and
However, many of these new features and existing
devices such as the keyboard, mouse and serial and parallel
ports are well below the ultimate bandwidth or capability of
the advanced buses such as the PCI bus. Therefore, it is not
forward type delays. More details on the serial bus archi
tecture are provided in the Universal Serial Bus Speci?ca
tion 0.9, dated Mar. 20, 1995, available from Intel Corp. This
ei?cient to conned each one of the functions and devices to
speci?cation is hereby incorporated by reference.
the PCI bus directly, as this would impact bus loading and
greatly increase overall costs. Additionally, many of these
Of particular interest for the serial bus architecture is to
consolidate the external peripheral devices so as to require
new functions are essentially serial in nature, with the data
transferred in a bit stream rather than over a parallel bus
structure. This is provided for many reasons, such as reduced
only one PCI slot and provide a high level of ease of use.
wiring costs, and can be done because of the lower data rates
which are required.
Thm'efore, it has been proposed to develop a serial bus
architecture to connect all of these various lower bandwidth
devices. The serial bus is organized with a host controller
having a series of ports, which can then be connected either
diredly to devices or functions or to further hubs which have
below them further devices or functions. A hub or the host
controller may in addition incorporate functions if desired.
One particular problem arising from consolidation is that the
interfacing methodology used before the advent of the serial
bus is not compatible with the interfacing methodology of
the serial bus. For example, the 8042 keyboard controller
provides a well known register and command set for com
municating with a pointing device and a keyboard via
45
keyboard controller ports at 110 addresses 60h and 64h.
Once the keyboard and pointing device functions are con
solidated into the serial bus architecture, the keyboard and
pointing device will no longer be found at 110 addresses 60]:
and 641: and communications to the keyboard and pointing
Inthis manneratree structurecanbedevelopedtoallowa
device will be handled through the common serial bus
reasonable number of functions or devices to be attached to
the serial bus system. The host controller connects to a bus
interface. However, since the serial bus requires certain
software drivers to be loaded, until the bus is fully opera
tional there is a period of time when the keyboard and
in the computer system, for example the PCI bus, through
the host controller. By having the host controller act as a
concentrator, only a single connection to the PCI bus is
necessary. The connection is bettm‘ able to utilize the per
formance of the PCI bus without requiring numerous con
nections.
The host controller, each hub, and each function or port
pointing device are unavailable. This could create undesir
able results if a bootable device, such as SCSI disk or
CD-ROM, powa' on system password, keyboard locking, or
55
contain particular control registers for doing set up and
initialization operations. In addition, three basic types of
data transfer are de?ned in the smial bus system. The ?rst
type is isochronous, which is effectively a continuous real
system con?guration utilities wire to require the user to
input a keyboard or pointing device command before pro
ceeding with the booting of the device. Thus, it is desirable
to eliminate this problem.
One adt?tional problem that is pervasive in die PC world
involves the direct accessing of hardware by certain soft
ware. For example, game software is notorious for side
time transfer, such as telephony information or audio infor
stepping the BIOS calls and accessing the keyboard and
mation. The second type is asynchronous block transfers,
such as printer operations and conventional serial port
video registers directly to gain the highest performance
possible ?'om the computer. Once the keyboard function is
consolidated into the serial bus, the register compatibility
will no longer be present. Thus, to maintain compatibility
operations, while the third type is asynchronous interactive
device transfers, such as keyboard, mouse, pointing device,
pen interfaces, and the con?guration and status information,
generally referred to as the control information, of the
various devices.
65
with a relatively large base of software applications access
ing the keyboard hardware directly, it is desirable to ?nd a
solution to this problem
5,802,318
3
4
SUMMARY OF THE PRESENT INVENTION
FIG. 6A is a ?ow diagram illustrating a received keyboard
packet sequence according to the FIG. 4 embodiment;
FIGS. 6B and 6C are ?ow diagrams illustrating processes
A keyboard and pointing device system according to the
present invention includes a serial bus host controller
coupled to a serial bus keyboard and pointing device. The
keyboard includes both keyboard scan logic and scan code
conversion logic for passing to the host controller over the
serial bus. The host controller includes circuitry for process
ing the data between the serial bus and a host bus. The host
handled by system mangement mode; and
FIG. 6D is a ?ow diagram illustrating an alternative
method of moving data from packets to the 8042 emulation
logic.
controller further includes 8042 emulation logic for provid
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENT
ing a hardware compatible interface to the keyboard con
troller. In one embodiment the 8042 emulation logic also
includes circuitry for communicating over the serial bus
during times when the serial bus has not yet been initialized
When the computer system is ?rst powered on, the serial
Referring now to FIG. 1, the computer system C accord
ing to the preferred embodiment is generally shown. The
computer system C includes a processor 100 such as a
Pentium® or 486 processor by Intel or their equivalents. It
bus resources are not yet available since he software drivers
is understood that other processors could of course be
utilized. The processa' 100 is connected to a second level or
have not been loaded. During this initialization period, the
8042 emulation logic handles communications to the serial
bus keyboard and pointing device. After the serial bus
L2 cache 102 and to a memory and L2 cache controller and
services are initialized, data written to the 8042 emulation
logic will be routed through the standard serial bus services.
The 8042 emulation logic also includes a means for
locating the address of the keyboard and pointing device on
the serial bus. Once located, the address is placed into a
keyboard address register or pointing device address register
for future reference.
25
In another embodiment the keyboard and pointing device
are located using conventional serial bus operations and the
8042 emulation logic provides direct entries into the serial
bus scheduling queue. In a furthu' embodiment, write opera
tions to the 8042 ports trigga' interrupts to special software
code, which interprets the written information and, based on
emulating the 8042 keyboard controlla', provides the proper
high performance back bone of the computer system C. A
PCI to ISA (Industry Standard Architecture) bridge 110 is
data to the serial bus host controller. Read operations in this
embodimentarepa'formedeitherbyhavingtheserialbus
host controller directly provide the data to emulated 8042
ports andprovidethe rroperinterrupt orbyhaving simpli
?ed serial bus driver software receive the keyboard or
pointing device packet normally, translate the packet data
and then provide this data to simulated 8042 ports and
provide the proper interrupt.
PCI bridge 104 and address and data bu?er 106. The main
memory 108 of the computer systemC is connected between
the memory and L2 cache controller 104 and the address and
data buffer 106. It is understood that the processor 100,
cache 102, memory and cache controller 104, address and
data butfer 106 and main memory 108 form the processor
system and processor to PCI bus bridge according to a PCI
system. It is understood of course that alta'nate processor
systems and high speed bus architectures could be utilized if
desired. Further, the address buffering could be included in
the PCI bridge 104.
The PCI bridge 104 and address and data bulfu' 106 are
conneaed to a PCI bus 110 which performs the high speed
35
connected between the PCI bridge 110 and an ISA bus 114.
A ?oppy disk controller 116 is connected to the ISA bus 114,
as is the system ROM (read only memory) 118. The ROM
118 contains BIOS (basic input/output services) code for
testing and
the computer system C and the serial
bus. Additionally, there may be a plurality of ISA slots
connected to the ISA bus 114 for receiving interchangeable
obtained when the following detailed description of the
prefured
t is considered in conjunction with ?re
cards.
The majority of the devices are connected to the PCI bus
110. For example, a SCSI or IDE (Intelligent Drive
Electronics) controlla' 122 is connected to the PCI bus 110
and to the associated disk drives and other devices (not
following drawings, in which:
FIG. 1 is ablockdiagramofacomputer systemincor
nectedtothePCIbus llltoallowhighperfa'mance
BRIEF DESCRIPTION OF THE DRAWINGS
A bette- unda'standing of the present invention can be
porating a sa-ial bus system according to the preferred
nt;
FIG. 2 is a block diagram illustrating a keyboard and
shown). A network interface card (MC) 124 is also con
network connections. Furtha, a video graphics system 126
is connectedtothePCIbus 110 andtcanassociatedmonitor
128. A fax/modem DSP (digital signal processor) 138 can
alsobeconnectedtothePCIbus 110forfax andmodemdata
mouse coupled to a su'ial bus host controller according to
processing. As noted, this is an exemplary computa- system
one embodiment;
architecture and is provided for explanation, variations
FIG. 3A is a detailed block diagram of 8042 emulation
being readily apparent to one skilled in the art.
block of the host controller according to the
nt of 55
Of interest to the present description, a serial bus host
FIG. 2;
controlla' 130 is also connected to the PCI bus 110. The
FIG. 3B is a detailed block diagram of simpli?ed 8042
emulation logic of the host controller according to a varia
tion of the embodiment of FIG. 3A;
FIG. 3C is a detailed block diagram of the queue accord
ing to FIG. 3B;
FIG. 4 is a block diagram illustrating a keyboard and
serial bus host controller 130 of the illustrated embodiment
acts as both a host controller and a hub, with various hubs
and functions connected to the host bus controlla' 130. For
example, a printer 132 is connected to one port of the serial
bus host controller 130, while an expansion hub 134 is
mouse coupled to a serial bus host controller according to an
connected to a second port. The expansion hub 134 provides
further expansion capabilities, such as connecting to a
alternative embodiment;
FIG. 5 is a detailed block diagram illustrating system
management interrupt logic according to the FIG. 4 embodi
boardl40furtheractsasahubitselfandanode,inthatit
meat;
keyboard 140 according to the present invention. The key
is connected to the monitor hub but furtha‘ contains ports to
connect to the mouse 142 and a pen or stylus pointing device
5,802,318
5
6
interface 144. This further physical connection is appropri
host controller 130 receives the processed scan codes for
ate as those are the primary input devices and they are in
most cases generally relatively near the keyboard 140 to
case use of operation. The keyboard interface will be
described in more detail below. A telephony interface 136
placement into the keyboard buffer of main memory 108.
The host controller 130 contains serial bus interface logic
206 for transmitting the packets over the serial bus cable.
Communication over the serial bus is processed by host
containing the necessary CODEC and DAA components is
controller services 202. In addition, 8042 emulation logic
connected to a third port and also receives a telephone line.
The telephone line can be any of the available types such as
an analog line, an ISDN line, a PBX connection and so on.
204 is also included in the host controller 130 and connected
to the serial bus interface logic 206 for providing hardware
level compatibility to the keyboard 140 and a mouse 142.
Host system communications for both the host controller
services 202 and the 8042 emulation logic 204 are handled
In the illustrated embodiment, the monitor 128 further
acts as a hub and as a node. The monitor 128 is thus
connected to one port of the serial bus host controller 130.
The node or device function of the monitor 128 allows
by the PCI interface logic 200 which couples to the PCI bus
110. Additionally, the 8042 emulation logic 204 provides the
conventional keyboard and mouse interrupts.
In many protected mode operating systems such as Win
dows 3.1, Windows 95 and 08/2, device drivers are respon
sible for communicating with low level hardware. In the
case of these operating systems, 8042 register level com
con?guration of the monitor 128 independent from the high
speed data utilized in the video system 126. The monitor 128
preferably ads as a hub because of the conventional physical
arrangement of a modern computer system. Preferably, the
system unit which contains the other devices is located
under the desk or in a relatively remote location, with only
the monitor 128, a keyboard 140, a pointing device such as
a mouse 142 or pen 144, a telephone handset 146, and
patibility is not as important as it is with DOS mode
operations, since the device drivers can be adapted to
different hardware con?gurations. When these operating
systems are operational, the device drivu's handle the key
microphone and speakers relatively accessible to the user.
As the monitor 128 effectively forms the central core of this
unit, it is logically a proper location for a hub. It is noted
board communications via the host controller hardware 402
(FIG. 4). Howeva', DOS application software and the boot
operations often communicate directly with hardware.
Therefore, the host controller 130 contains register level
compatibility for a DOS mode application or boot operations
that, although, preferably the keyboard is coupled to the
monitor for physical convenience, for simplicity of expla
nation herein the keyboard is shown coupled directly to the
host controller 130. The telephone handset 146 could be
connected to one port of the monitor hub to receive digitized
analog information ei?ra' directly from the telephony inter
to read from emulated 8042 registers and write to emulated
8042 registm's.
In the operation of the keyboard 140 in conjunction with
the serial bus and the host controller 130, keystrokes gen
erated at the keyboard 140 are transferred upstream to the
host controller 130. Data received from the keyboard 140
face 136 or as otherwise available, such as from an answer
ing machine or voice mail function. The microphone is part
of audio input circuitry 148 which is connected to a second
port of the monitor hub, while audio output circuitry 150
contains the speaka’s used for audio output. In all cases,
35
and mouse 142 are placed in a data output queue of the host
system.
controller services 202 if the 8042 logic emulation 204 is
disabled and in a data register of the 8042 emulation logic
204 if the 8042 emulation logic 204 is enabled
Now referring to FIG. 3A, the host controller 130 is
described in more detail. The 8042 emulation logic 204
consists of the logic necessary to emulate an 8042 keyboard
controller to the computer system C. References to an 8042
in this speci?cation generally refer to an 8042 used as a
Now referring to FIG. 2, the host controller 130 is shown
connected to the keyboard 140. As described above, the
details on the operation of the 8042 itself can be found in
each one of the particular devices connected over the serial
bus system includes control ports and con?guration registers
which need to be accessed by the processor 100 via the serial
bus host controller 130 to allow control and setup of the
individual devices. Thus it can be seen that in the computer,
the relatively lower data rate functions are connected to the
serial bus host controller 130 according to the serial bus
keyboard controller in a PC-compatible computer. Further
datasheets from Intel Corporation and details of operation in
lmyboard 140 contains sa'ial bus interface logic 208 for
a PC-compatible computer can be found in various books on
the subject and are well known to those skilled in the art. In
communicating with upstream ports and interface logic 216
for communicating with downstream ports, such as the
mouse 142. The serial bus interface logic 208 provides the
the present invention, the 8042 emulation logic 204 consists
of interface logic 306 for decoding bus operations, a key
necessary functionality for encoding and decoding of pack
board input bu?a- (1GB) 308, keyboard output buffer (KOB)
ets to be transferred between the keyboard 140 and the host
controller 130. Also included in the keyboard 140 is the
keyboard matrix 214 for interacting with a computer user.
Keyboard scan circuitry 212 is connected to the keyboard
matrix 214 in typical fashion for generating scan codes when
310 and a keyboard status register (KSR) 312. For
compatibility, these regista's are generally the same as in the
55
to the computer system C as would an actual 8042 keyboard
controllm'. The 8042 interface logic 306 is therefore respon
the keys of the matrix 214 are depressed. The scan codes are
passed from the keyboard scan circuitry 212 to scan code
sible generating an interrupt signal, responding to reading
and writing port data and responding to various other 8042
commands. The ports P0 and P1 are supported for compat
ibility with the enable address line 20 (A20) and system reset
conversion circuitry 210 also residing on the keyboard 140.
Although the functionality of scanning and conversion is
illustrated separately, it is contemplated that both functions
can be easily handled by a single microcontroller. Because
the keyboard scan logic 212 and the scan code conversion
logic 210 are consolidated onto the keyboard 140, the host
controller 130 is required to do little or no processing of the
keystroke data. Thus, most processing of the scan codes and
subsequent conversion into system scan codes or ASCII
codes can easily be handled singly by the keyboard 140. The
8042.
The 8042 interface logic 306 presents the same interface
signals and other proprietary 8042 output signals, howevu',
since the A20 and reset signals are customarily mimicked or
65
trapped by other logic on the system board, it is contem
plated that those signals may not be provided.
The keyboard status register 312 is a read-only register
residing at 110 address 64h. When the processor 100 per
5,802,318
7
8
forms a read operation to I/O address 64h and the 8042
computer system C is initialized and the drivers and soft
ware for control of the serial bus have been loaded. the
hardware queue and scheduler 318 is disabled in favor of the
main host controller services 202.
When the computer system C is ?rst powered on, the host
controller services 202 of the host controller 130 are not yet
available since the drivers have not been loaded by the
processor 100. During this time transmissions over the serial
bus to the keyboard 140 are handled by the 8042 emulation
logic 204, and more particularly the hardware queue and
scheduler 318.
However, before any packet transmissions can take place
between the host controller 130 and the keyboard 140, the
host controller 130 must know the serial bus address of the
keyboard 140. After the host controller 130 receives power,
the hardware queue and scheduler 318 polls the serial bus
looking for a device having a device type of keyboard. Once
the keyboard 140 is located, the serial bus address of the
emulation logic 204 is enabled, the host controller 130
places the contents of the keyboard status register 312 onto
the PCI bus 110. As in the actual 8042, no ?ag or interrupt
changes occur as a result of the read operation. The bit
de?nitions for the keyboard status register 312 are shown in
Table 1.
TABLE 1
Contents
output bu?'er mu ?ag (can)
input buifer full a»; (nap)
inptnbutfercontents?agm)
output bu?er contents ?ag (OBC)
keyboard is placed into a keyboard address regista (KAR)
314. Similar operations are performed to locate the mouse
142, with its address being placed in a mouse address
The output bu?’er empty ?ag is set when the keyboard output
bulfer310is emptyandmaybeloadedwithanew byte.'I‘he
register (MAR) 315. These addresses are used by the 8042
emulation logic 204 in all future communications widi the
input bull’er full ?ag is set when the keyboard input bu?'er
308 contains either a command or data byte. The input buifer
contents ?ag is set when the keyboard input bu?’er 308
contains a command and is reset when the keyboard input
bu?u' 308 contains data. The output bu?'er content ?ag is set
when the keyboard output buifer 310 contains mouse data
and is reset when the keyboard output butfer 310 contains
keyboard 140 and mouse 142.
25
keyboard data.
The keyboard input butler 308 is a write-only register
during the next frame period. By default, dtu'ing each frame
when no commands are sent to the keyboard 140, the
residing at V0 addresses 60h and 64h. Data is written to I/O
address 60b and commands are written to I10 address 641:.
Awrite to I/O address 60): will:
1) set the keyboard input butfer full ?ag;
2) clear the input butler contents ?ag; and
3) generate an input bu?er full intu'rupt to the 8042
hardware queue and scheduler 318 generates packets
requesting the keyboard 140 to send data. If data is returned,
itisplacedinthe keyboardoutputbulfer310 andtheproper
35
host controller 130, the keyboard 140 will not acknowledge
(NACK) the packet. However, if the 8042 emulation logic
204 still contains a byte of data from the previous frame, the
host controller 130 will not request an additional byte from
the keyboard 140 until the previous byte has been read by
the processor 100, but instead may query the keyboard
Subsequently, the data written to the keyboard input buifer
308 will be sent to the keyboard 140. Keyboard commands
are written to the keyboard input buffer 308 residing at V0
address 64h. Commands written to this register are compat
ible with standard 8042 commands. A write to I/O address
64h:
status.
45
3) causes the 8042 emulation logic 204 to send the data to
the keyboard 140.
The keyboard output bu?‘er 310 is a read-only register
residing at IIO address 60h. When a key is pressed at the
100. Also, the output bu?‘er full ?ag is set and an interrupt
is issued. A read to I10 address 60h will:
1) clear the output butler full ?ag in the keyboard status
register; and
2) clear any interrupt requests to the processor 100.
Atthetimeofinitialization ofthecomputasystemqin
Once the said bus software and drivers are loaded by the
processor 100, the enable bit is set to disable the hardware
queue and scheduler 318. From this time forward, data is
received from the keyboard 140 into a data receive queue of
the queue 302. The host controller 130 then issues an
interrupt to indicate data availability. The serial bus drive‘
then causes theprocessor l00toremovethedatafromthe
queue and trocess it accordingly. Similarly, when the enable
bit is set, data is provided to the keyboard 140 and mouse
keyboard 140 or the mouse 142 is moved or a button
depressed the data representing the pressed key is received
into keyboard output bu?er 310 for reading by the processor
interrupt is issued. The pocessor 100 then reads the data
from the keyboard output bulfer 310 as if it where read from
an actual 8042. If no data is ready to be transfen'ed to the
keyboard controller.
1) sets the keyboard input buffa- ?ag in the keyboard
status register;
2) sets the input buifer contents ?ag in the keyboard status
register; and
During initialization, once data is written into the key
board input bu?ier 308 and the command is given, a packet
is generated by the hardware queue and scheduler 318. The
packet includes the keyboard address, data and the com
mand given. The packet will be sent to the keyboard 140
55
142 through me host controller services 202 in a normal
manna. Thus, the 8042 emulation logic 204 is used when
8042 hardware level emulation is desired and the standard
host controller services 202 is used at othm times when full
driver support is available.
Thus, while the host controller of the preferred embodi
ment primarily serves as the main interface to the serial bus,
the host controller 130 an enable register 316 is cleared so
it also provides backward compatibility with the keyboard
and pointing device for communication during the initial
that during the initialization period a hardware queue and
scheduler 318 is enabled. Also during this time it is noted
ization process when othm'wise there would be none.
It is contemplated that a variation on the embodiment
that the host controller services 202 are not yet enabled so
illustrated in FIG. 3A could also provide the disclosed
bene?ts. As shown in FIG. 3B, the 8042 emulation logic 204
that the 8042 emulation logic 204 is the only means avail
able for communicating with the keyboard 140. Once the
does not include a separate hardware queue and schedula,
5,802,318
9
10
but instead the queue 302 and scheduler 304 of the host
pointing devices. If they are located, the serial bus address
of the keyboard 140 is placed into a keyboard address
register (KAR) 314 and the serial bus address of the pointing
device 142 is placed into a mouse address register (MAR)
controller services 202 are utilized to provide the same
functionality.
The enable register 316 enables the 8042 emulation logic
for accessing the registers at I/O address 60h and 64h. As
shown in FIG. 3C, the queue 302 includes a number of data
queues, 338 and 340, and control queues, 342 and 344, for
320. These registers 314 and 320 are accessible for all serial
bus communications to these devices. The BIOS will also
initialize the host controller 130 for polling the devices for
data availability using the conventional serial bus
transmitting and receiving packets over the serial bus. Pack
ets generally contain a serial bus address, serial bus com
mand and data if a write command. Commands can include
techniques, queues and schedulms, though operation will be
read, write and status or polling commands.
In this embodiment, when the computer system C is ?rst
initialized, the 8042 emulation logic 204 is disabled. At this
time, the BIOS constructs a packet and provides a series of
packets to the control transmit queue 342 for querying the
serial bus for a keyboard 140 and pointing device. When the
device(s) are located, the addresses are stored in the key
board address register 314 and mouse address register 315.
devices will be controlled or monitored. This allows user
simpli?ed as the operations will be very simple and very few
interaction at the early stages of computer initialization and
before the serial bus device drivers have loaded.
When the host controller 130 receives a packet from the
serial bus, as illustrated in FIG. 6A, step 630, it ?rst checks
the packet to determine whether dre packet contains key
board or mouse data, as shown in step 632. If so, at step 634
the host controller issues a system management interrupt
using logic illustrated in FIG. 5. If not so, at step 636 the host
controller processes the packets as conventional in serial bus
Since the addresses are now contained within the host
controller 130 hardware, the BIOS enables the 8042 emu
lation logic 204. At this point, communications between the
keyboard 140 or pointing device and the processor 100, via
the 8042 emulation logic 204, is enabled.
When the 8042 emulation logic 204 is enabled, the queues
are stuffed with packets built according to the 8042 registers,
as shown in FIG. 3C. If data is present in the keyboard input
bu?’er 308, an output data packet 330 is provided to the data
opm'ations.
FIG. 6B illustrates the SMM code in response to the
above generated SMI. At step 650, the processor 100 reads
the SMI status register to determine if keyboard data caused
25
the interrupt, as shown at step 652. If so, at step 654 the
30
processor 100 obtains the keyboard data and places it into
the keyboard output bu?er 310, using an alternate address.
The keyboard status register 312 is properly set in response
to data being placed into the keyboard output buffer 310 and
the hardware interrupt to the processor 100 is simulated with
transmit queue 338 for transmission to the device on the next
frame. If a command is present in the keyboard input buffer
308, a output command packet 334 is provided to the control
transmit queue 342 for transmission to the device on the next
frame. If no data or commands are present, then the output
an [NT instruction so that the keyboard data may be read at
I/O address 60h and the status may be read from 110 address
control packet 334 polls the keyboard 140 and pointing
64h. Alternatively, the processor 100 could direct alternate
circuits (not shown) to provide the proper interrupt signal.
device 142 for data availability. If a device has data
available, it may respond with a data packet, which is
received into the data receive queue and subsequently trans
ferred to the keyboard output bu?’er 310 and the proper
35
Alternate addresses are used to prevent operation of the
write trapping logic described below. Once the interrupt is
simulated, or provided, the keyboard interrupt service rou
interrupt is provided. The keyboard status register 312 is
tine then proceeds as normal to read the keyboard status
again constructed as described above with reference to FIG.
3A.
When the 8042 emulation logic 204 is disabled, the
registu' 312 using conventional operations to further deter
mine the source of the keyboard inten'upt and ?nally reading
packets are built and controlled as normal. For more details
652 the processor determines that the SMI interrupt: was not
on queues and packet construction and handling are
caused by the keyboard controller 140, then control pro
the keyboard output bu?er 310 if data is present. If at step
ceeds to step 655 where the other interrupts are processed as
descrmed in patent application Scr. No. 08/346,097, entitled
“Arbiter Organization for Serial Bus Transfers”, ?led Nov.
29, 1994, which is hm'eby incorporated by refu'ence. The
remaining operations are handled as described in FIG. 3A
above.
An alternate embodiment to the foregoing keyboard and
pointing device system of FIGS. 3A and 3B is illustrated in
FIG. 4. The host controller 130 includes a PCI interface 400
for communicating PCI bus operations to the host controlle
130 and the various serial bus devices. The host controlla
130 also includes decode logic 322 for accessing a keyboard
45
normal Data received from the pointing device or mouse
142 is handled in a similar manner.
An alternative to using the system management mode is
to use the normal hardware interrupt provided for use by the
host controller 130. This alternate does not require a KAR
314 or MAR 320 but may not be compatible with applica
tions which disable interrupts and poll die KSR 312. When
the host controller 130 receives a scan code from the
input buffer (KB) 308, a keyboard output buffer (KOB) 310
keyboard 140 or data from the pointing device 142 it
generates a host controlla' interrupt to the processor 100, as
illustrated in FIG. 6D, step 670, as conventional in serial bus
and a keyboard status register (KSR) 312. It is noted that the
I018 308, KOB 310, KSR 312 and decode logic 322 can be
driver located in the BIOS, the processor 100 reads the host
operations. Next, at step 672, using a simpli?ed serial bus
controller interrupt status to determine the source of the
serial bus interrupt. As shown at step 674, the processor 100
and need not be located in the host controller 130. The
keyboard 140 and pointing device 142 use the same 8042 60 determines if the host conu'oller interrupt is caused by
receipt of a keyboard scan code. If so, then control procwds
registers to communicate with the processor 100. A host
to step 676 where alternate addresses are used to place the
controller hardware block 402 is also coupled to the PCI
conveniently located anywhere in the computer system C
interface 400 for handling the serial bus opa‘ations on the
serial bus.
Upon initialization of the computer system C, the BIOS or
initialization code of the computer system C will cause the
host controller 130 to search the serial bus for keyboard or
received data into the keyboard output butter 310 and the
keyboard status register 312 is properly set. Alternate
addresses are used to prevent operation of the writing
trapping logic described below. After the butter 310 and
register 312 are prepared, an 8042 interrupt, IRQl, is
5,802,318
11
12
simulated in software with the INT command. The keyboard
interrupt service routine then proceeds as normal to read the
keyboard status register 312 using conventional operations
C, while an other input of the OR gate 560 is received from
the output of an AND gate 502. The output of the AND gate
502 is generated when the computer is in DOS emulation
to further determine the source of the keyboard interrupt and
mode so that emulation of the 8042 is active and a write
?nally reading the keyboard output bulfer 310 if data is
operations are processed as normal. Data received from the
operation is attempted to I10 address 60h or 64h, as illus
trated by OR~gate 504. If emulation mode is not active, no
SMI is generated and the written data is ignored. When
emulation is not active, the host controller services 202 must
be used to provide commands to the keyboard 140 and
In an alternative embodiment, if the 1GB 308, KOB 310,
and KSR 312 are located in the host controller 130, the host
The output from the AND gate 502 also provides a clock
signal for a D ?ip-?op 506. The output from the D ?ip-?op
present. If at step 674 the processor determines that the host
controller interrupt was not caused by the keyboard control
ler 140, then control proceeds to step 678 where the other
pointing device or mouse 142 is handled in a similar manner. 10 mouse 142.
controller 130 could directly place the data in the keyboard
output buifm' 310, set the status regista' 312, and provide the
keyboard interrupt, but additional circuitry is required for
15
this embodiment to decode the packets and to place the data
and generate the interrupt and so is not preferred.
interrupt and process the interrupt accordingly.
Write operations to I/O addresses 60b and 64h are handled
by the host controller 130 in conjunction with software, as
described below. FIG. 6C illustrates processing of a write
operation to I/O address 60h or 64h. A write to I/O address
60h or 6411 of the K18 308 causes a system management
The OR gate 500 also receives the output of an AND gate
510, which receives the DOS MODE signal and the indi
cation ?rom the host controller 130 that a keyboard or mouse
packet has been received. This provides the SMI needed in
that case, unless emulation is not active. The output of AND
interrupt (SMI) to be generated. This circuitry is shown in
gate 510 is provided to the clock input of a D ?ip-?op 512,
which has its D input connected high and its output provided
to the SMI status registu' 508. The ?ip-?op 512 is cleared
more detail in FIG. 5. When the system management inter
mpt is generated, the processor 100 entas system manage
ment mode. Operation of the system management mode
code is shown in FIG. 6C. First in step 600 the processor 100
reads a system management interrupt status register to
when the status register is read.
determine the source of the interrupt. In step 602 the
processor 100 deta-minesifawritetoI/Oports 60hor64h
had caused the interrupt. If not, processing of the other SMI
operations proceeds atstep 603. Ifawriteto 60hor64hhad
occln'red, the SMI code decodes the value written to the KIB
308 to determine the requested 8042 operation, as shown at
step 604. Registers are actually provided at 1/0 addresses 60
and64toreceivethedataorcommand. The SMIcodereads
506 is provided to one bit of an SMI status register 508 for
providing SMI status to the processor 100. When the pro
cessor reads the status from the SMI status register 508 the
status bit is cleared. From reading the SM] status register
508 the processor 100 can We the source of the SMI
35
The DOS mode signal is provided from an arbitrary
con?guration register which is not shown. When emulation
mode is inactive, the serial bus interrupt provided by the host
controllu' 130 will activate a loaded, complete serial bus
device driver, rather than the simpli?ed serial bus driver
provided in the BIOS, which simpli?ed driver is aware when
emulation mode is active and can provide the data to the
K03 310 and KSR 312 and into-rupt as desu'ibed above.
This complae driver will not provide data to the keyboard
output buifer 310 or the keyboard status register 312 or set
those registers using alternate addresses to prevent possible
reentry in SMM. To perform the decoding function the SMI
code effectively emulates or replicates the majority of the
8042 keyboard controller command logic. At step 605 the
keyboard data packet receipt, the DOS MODE signal blocks
processor 100 determines if the decoded operation was a
the generation of the SM! signal when emulation is inactive
the 8042 interrupt, but will instead operate according to
standard serial bus operations.
In the alternative where the SMI signal is provided on
commandtothe keyboard l40<rmouse l42orawritetoan
and a conventional serial bus interrupt is provided as the
8042 output port. If a keyboard 140 or mouse 142 command,
packet checking logic is also disabled.
atstep606theprocessor100writesanykeyboardor
pointing device data to the host controller 130 ft: forward
ing to the respective device over the serial bus. This opu'a
45
ibility in exchange for great: software complexity. Both
methods provide the desired 8042 compatibility for times
tion is done using conventional, albeit simpli?ed, saial bus
services provided in the BIOS. If the I/O operation was a
write operation to one of the 0th: output bits of the 8042
when the complete serial bus device drivers are not avail
able.
The foregoing disclosure and description of the invention
are illustrative and explanatory thereof, and various changes
ports, thenat stepmthatdatais transmittedtohardware
compatible ports contained elsewhere to emulate the desired
output bit. Otha signals formerly generated or sensed by the
8042 port logic are supported in the system at other available
in the size, shape, materials, components, circuit elements,
addresses or ports as one skilled in the art would appreciate.
A?ersteps606and608theSMIcodemoperlysets?zeKSR
55
312 in step 610 and then after steps 603 or 610 operation of
the SMI code ends.
It is understood that FIGS. 6A and 6B are combined into
a single routine, if the host controller 130 according to FIG.
4 which provides an SMI upon receipt of a keyboard or
mouse data packet is utilized. FIG. 6B has been illustrated
separately for clarity with the various alternatives.
FIG. 5 illustrates a functional block diagram of system
management interrupt logic for the keyboard system. The
system management interrupt (SMI) signal is provided to the
processor 100 by an OR gate 500. One input to the OR gate
500 is from the other SMI sources of the computer system
Therefore, as compared to the ?rst alternative shown in
FIGS. 2 and 3, this alternative illustrated in FIGS. 4-6
includes a reduced level of 8042 hardware level compat
65
wiring connections and contaas, as well as in the details of
the illustrated circuitry and construction and method of
operation may be made without departing from the spirit of
the invention.
We claim:
1. A serial bus host controller for coupling a saial bus
keyboard to a computer system via a standardized serial bus
which transfers data in a packetized protocol, the serial bus
host controller for sending and receiving serial bus packets,
the serial bus host eonirollu' comprising:
a keyboard controller emulator for gene-sting and receiv
ing data, status and commands pertaining to the serial
bus keyboard, said keyboard controller emulator
including:
5,802,318
14
13
a serial bus address register for storing the serial bus
address of the serial bus keyboard;
a data input bu?’er;
a serial bus address register for storing the serial bus
address of the serial bus keyboard;
a data bulfer; and
a status register;
a detector for detecting when said data bu?er and said
status register are accessed; and
a data output butfer, said keyboard controller providing
an interrupt when said data output bu?'er is changed;
and
a status register; and
a detector for detecting when the data bu?’ers and said
status register are accessed;
an interrupt generator for providing a system management
interrupt to the computer system when said data buffer
packet parsing logic for determining if a packet is
and said status register are accessed.
2. The serial bus host controller of claim 1, wherein said
detector further detects if a packet is received from said
received ?om the serial bus keyboard;
data output buffer writing logic for writing into said data
serial bus keyboard, and wherein said interrupt generator
provides a system management interrupt to the computer
system if a packet is received from said serial bus keyboard.
output bu?er a data value extracted from a packet
received from said serial bus keyboard; and
data input buffer reading logic for reading from said data
input butfer a data value written therein by the com
3. The serial bus host controller of claim 2, wherein said
interrupt causes the computer system to place the serial bus
keyboard data into said data butTer and causes said status
bu?er to be updated if a packet is received from said serial
bus keyboard.
4. The serial bus host controller of claim 1, further
puter system for said serial bus keyboard and devel
oping a packet for transmission to said serial bus
keyboard,
20
including a switch for enabling and disabling said keyboard
controller emulator.
5. The serial bus host controlla' of claim 1 wherein said
serial bus keyboard includes a serial bus mouse.
6. A computer system for coupling to a suial bus key
wherein when said data value is written into said data
output buffer a keyboard controller interrupt is gener
ated.
12. The serial bus host controller of claim 11 wherein said
serial bus keyboard includes a serial bus mouse.
13. The serial bus host controller of claim 11 wherein said
interrupt is a system management interrupt.
14. The serial bus host controller of claim 11, further
board via a standardized serial bus which transfers data in a
including a switch for enabling and disabling said keyboard
packetized protocol, the computer system comprising:
a said bus keyboard; and
a serial bus host controller coupled to said serial bus
controller emulator.
15. A computer system for coupling to a serial bus
keyboard via a standardized serial bus which transfers data
keyboard for sending and receiving serial bus packets,
in a packetized protocol, the computer system comprising:
comprising:
a keyboard controller emulator for generating and
receiving data, status and commands pertaining to
the serial bus keyboard, said keyboard controller
emulatru' including:
a serial bus address register for storing the serial bus
a serial bus keyboard; and
a serial bus host controller coupled to said serial bus
keyboard for sending and receiving serial bus packets”
35
address of the serial bus keyboard;
a serial bus address register for storing the serial bus
address of the serial bus keyboard;
a data input bu?er;
a data output bu?’er, said keyboard controller pro
viding an interrupt when said data output buffer is
a data bu?'er; and
a status registu';
a detector for detecting when said data bu?'er and said
status register are accessed; and
an interrupt generator for providing a system manage
ment interrupt to the compute‘ system when said
data boiler and said status register are accessed.
changed; and
45
packet parsing logic for determining if a packet is
keyboard, and wherein said interrupt genu'ator provides a
system management interrupt to the computer system if a
packet is received from said saial bus keyboard.
8. The computer system of claim 7, wherein said interrupt
causes the computer system to place the saial bus keyboard
received from the serial bus keyboard;
data output buffer writing logic for writing into said data
output butfer a data value extracted from a packet
received from said serial bus keyboard; and
data input buifer reading logic for reading from said
data into said data bu?a' and causes said status bulfer to be
55
data input bu?er a data value written therein by the
computer system for said serial bus keyboard and
developing a packet for transmission to said serial
60
wherein when said data value is written into said data
output butfer a keyboard controller interrupt is gen
erated.
16. The computer system of claim 15 wha'ein said serial
bus keyboard includes a serial bus mouse.
17. The computer system of claim 15 wherein said
65
interrupt is a system management interrupt.
18. The computer system of claim 15, further including a
switch for enabling and disabling said keyboard controller
switch for enabling and disabling said keyboard controller
emulator.
10. The computer system of claim 6 wherein said serial
bus keyboard includes a serial bus mouse.
11. A serial bus host controller for coupling a serial bus
keyboard to a compute system via a standardized serial bus
bus keyboard,
which transfers data in a packetized protocol, the serial bus
host controller for sending and receiving serial bus packets,
the serial bus host controller comprising:
a keyboard controller emulator for generating and receiv
ing data, status and commands pertaining to the serial
bus keyboard, including:
a status regista'; and
a detector for detecting when the data bullets and said
status registm' are accessed;
7. The computer system of claim 6, wherein said detector
further detects if a packet is received from said serial bus
updated if a packet is received from said serial bus keyboard.
9. The computer system of claim 6, further including a
comprising:
a keyboard controller emulator for generating and
receiving data, status and commands pertaining to
the serial bus keyboard, including:
emulator.
5,802,318
15
16
19. A method of communicating with a serial bus key
2A. The method of claim 22, wherein said keyboard
controller emulator includes a data output buifer, the method
further comprising the steps of:
(k) the BIOS placing keyboard data into said data output
board over a standardized serial bus in a computer system
having a serial bus host controller, said host controller
including a keyboard controller emulator, the keyboard
controller emulator including a queue and scheduler for
5
communicating directly with the serial bus, the method
comprising the steps of:
(a) powering on the computer system;
(b) enabling a keyboard controller queue and scheduler;
(c) said keyboard controller queue and scheduler polling
bu?er if a packet is received from said serial bus
keyboard before said device driver is loaded; and
(l) generating an interrupt to said computm' system if data
is placed into said data output buifer.
25. A method of communicating with a serial bus key
board over a standardized serial bus in a computer system
the serial bus for a serial bus keyboard;
having a serial bus host controller, said host controller
including a keyboard controller emulator, the method com
(d) determining an -address of said serial bus keyboard;
(e) storing said serial bus keyboard address in a register;
prising the steps of:
(a) powering on the computer system;
(f) said keyboard controller emulator processing packets,
if any, with the serial bus keyboard until the host
controller is
(b) polling the serial bus for a serial bus keyboard;
(c) deta'mining an address of said serial bus keyboard;
(d) storing said sa'ial bus keyboard address in a register;
(e) loading a host controlla- keyboard device driver;
(I) generating a system management interrupt (SMI) if
keyboard data is received by the host controllu'; and
(g) loading a host controller device driver; and
(h) disabling said keyboard controller queue and sched
ula' after said host controller device driver is loaded
20. The method of claim 19, wherein said keyboard
controller emulator includes a data input build‘, the method
further comprising the steps of:
(i) said keyboard controller queue and schedulu gener
ating a packet for said serial bus keyboard if data is
received into said data input buifer before said device
driver is loaded; and
(i) said keyboard controller queue and scheduler trans
mining said packet for said serial bus keyboard utiliz
26. The method of claim 25, wherein step (1) frn‘ther
comprises the steps of:
(h) receiving a serial bus packet; and
ing the stored address if data is received into said data
input bu?er before said device driver is loaded.
21. The method of claim 19, wherein said keyboard
controller emulator includes a data output hu?’er, the method
27. The method ofclaim 25, wherein step (g) is performed
in system management mode.
28. The method of claim 25, wherein the keyboard
(g) processing the keyboard data.
(i) determining if said serial bus packet contains keyboard
data
emulator includes a data output bull": and a status register,
further comprising the steps of:
and wha'ein step (g) further comprises the steps of:
(k) placingkeyboarddatainto saiddataoutputbufferifa
(j) writing the keyboard data into the keyboard output
packet is received from said serial bus keyboard before
said device drive‘ is loaded; and
(1) gena'ating an interrupt to said computer system if data
is placed into said data output buffer.
22. A method of communicating with a serial bus key
bu?’er if keyboard data is received by the host control
la;
(k) setting the status register to re?ect the data written to
the keyboard output bu?'er; and
(1) providing a keyboard controlla' intarupt.
board over a standardized serial bus in a computer system
having a suial bus host controller and a basic input/output
system (BIOS) for controlling device initialization, said host
controller including a keyboard controller emulator, the
method comprising the steps of:
(a) powering on the computer system;
29. The method of claim 28, wherein the computa- system
further includes an SMI status regista', the medrod furthm'
45
(n) deta'mining a source of the system management
(b) disabling the keyboard controller emulator;
interrupt ?'om said SMI status register.
30. The method of claim 28, wherein said keyboard
controller intcrupt is simulated with an INT instruction.
31. The method of claimZS, wherein the computer system
(c) the BIOS polling the serial bus for a serial bus
(d) the BIOS determining an address of said serial bus
fm‘therincludesanSMIstatusregisterandwherein the
keyboard;
keyboard emulator includes a data input bulfer, the method
further comprising the steps of:
(e) the BIOS storing said serial bus keyboard address in
a register;
(1) die BIOS enabling the keyboard controller emulata';
(g) the BIOS handling any communications between the
computer system and the serial bus keyboard until a
host controller device driva' is loaded;
(h) loading a host controller device driver; and
(i) disabling the keyboard controller emulator.
23. The method of claim 22, whu'ein said keyboard
controller emulator includes a data input buifer, the method
further comprising the step of:
(j) ?re BIOS generating a packet for said serial bus
keyboard if data is received into said data input buifer
before said device drivu is loaded.
comprising the steps of:
(m) reading the SMI status register before step (j); and
55
(o) generating a system management inten-upt (SMI) if
data is written to the keyboard input bull'er;
(p) reading the SMI status register;
(q) determining a source of a system management into‘
rupt from said SMI status registm';
(r) reading the keyboard input bu?’er if the source is the
keyboard emulator; and
(s) forwarding the keyboard input bu?er data to the host
controllu' fcr transmission to the serial bus keyboard if
the source is the keyboard emulator.
32. A method of communicating with a serial bus key
board over a standardized serial bus in a compute’ system
5,802,318
17
18
having a serial bus host controller, the host controller
including a keyboard controller emulator, the keyboard
controller emulator having a data output buffer and a status
register, the method comprising the steps of:
(d) writing packet data into the data output buffer if the
packet Source is the Serial bus keyboard;
(C) updating the Status register if data is Written into the
data Output buffer; and
<a>
(b) gc§arcztigg t;
thehgst tcongroul?
mminterrupt if a Pimkct is 5 controller
92 gs?asmestseeisizess
interrupt is simulated with an INT instruction.
rece1v
y
e
0s co
0 er;
(c) determining a source of the packet;
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