Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data
STM8S103K3
STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Features
Core
■
■
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
Extended instruction set
Memories
■
■
■
Program memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Data memory: 640 bytes true data EEPROM; endurance 300 kcycles
RAM: 1 Kbytes
■
■
Clock, reset and supply management
■
■
■
2.95 to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
Clock security system with clock monitor
Power management:
– Low power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
Permanently active, low consumption poweron and power-down reset
Interrupt management
■
■
Nested interrupt controller with 32 interrupts
Up to 27 external interrupts on 6 vectors
Timers
■
Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
LQFP32 7x7 VFQFPN32 5x5
TSSOP20 UFQFPN20 3 x 3
■
■
■
■
16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
2 watchdog timers: Window watchdog and independent watchdog
Communications interfaces
■
■
■
UART with clock output for synchronous operation, Smartcard, IrDA, LIN master mode
SPI interface up to 8 Mbit/s
I
2
C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■
10-bit,
±
1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog
I/Os
■
■
■
Up to 28 I/Os on a 32-pin package including 21 high sink outputs
Highly robust I/O design, immune against current injection
Development support
– Embedded single wire interface module
(SWIM) for fast on-chip programming and non intrusive debugging
Unique ID
■
96-bit unique key for each device
June 2009 15441 Rev 3
www.st.com
1/95
1
Contents
Contents
STM8S103x
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/95 15441 Rev 3
STM8S103x
Contents
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 60
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 62
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
VFQFPN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
UFQFPN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 90
15441 Rev 3 3/95
Contents
STM8S103x
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 92
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4/95 15441 Rev 3
STM8S103x
List of tables
List of tables
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15
Total current consumption with code execution in run mode at V
DD
= 5 V. . . . . . . . . . . . . 51
Total current consumption with code execution in run mode at V
DD
= 3.3 V . . . . . . . . . . . 52
Total current consumption in wait mode at V
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Total current consumption in wait mode at V
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Total current consumption in active halt mode at V
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in active halt mode at V
DD
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in halt mode at V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in halt mode at V
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AIN
AIN
< 10 k
Ω , V
< 10 k
Ω R
DD
AIN
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
, V
DD
= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
15441 Rev 3 5/95
List of tables STM8S103x
20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
6/95 15441 Rev 3
STM8S103x
List of figures
List of figures
versus V
DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DD(RUN)
vs. V
DD
HSE user external clock, f
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . 57
DD(RUN)
DD(RUN)
vs. f
CPU
vs. V
DD
HSE user external clock, V
HSI RC osc, f
CPU
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . 57
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DD(WFI)
vs. V
DD
HSE user external clock, f
CPU
= 16 MHz . . . . . . . . . . . . . . . . . . . . . 58
DD(WFI)
DD(WFI)
vs. f
CPU
vs. V
DD
HSE user external clock, V
HSI RC osc, f
CPU
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 58
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DD
= 5 V vs 5 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical HSI frequency variation vs V
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical LSI frequency variation vs V
DD
@ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 63
and V
IH
vs V
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical pull-up resistance vs V
DD
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
OL
@ V
DD
= 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
OL
@ V
DD
= 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OL
@ V
DD
= 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OL
@ V
DD
= 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OL
@ V
DD
= 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
OL
@ V
DD
= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DD
DD
- V
- V
OH
OH
@ V
@ V
DD
DD
= 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
= 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DD
DD
- V
- V
OH
OH
@ V
@ V
DD
DD
= 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
= 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
IL
and V
IH
vs V
DD
@ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical NRST pull-up resistance vs V
DD
@ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 71
Typical NRST pull-up current vs V
@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI timing diagram - master mode
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
15441 Rev 3 7/95
List of figures STM8S103x
8/95 15441 Rev 3
STM8S103x
1 Introduction
Introduction
This datasheet contains the description of the STM8S103x access line features, pinout, electrical characteristics, mechanical data and ordering information.
● For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
●
●
For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
15441 Rev 3 9/95
10/95
Description
2 Description
STM8S103x
Table 1.
●
●
The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
● Reduced system cost
– Integrated true data EEPROM for up to 300 k write/erase cycles
– High system integration level with internal clock oscillators, watchdog and brownout reset.
●
Performance and robustness
– 16 MHz CPU clock frequency
– Robust I/O, independent watchdogs with separate clock source
– Clock security system
Full documentation and a wide choice of development tools
Advanced core and peripherals made in a state-of-the art technology
STM8S103xx access line features
Device Peripheral set
STM8S103K3
STM8S103F3
STM8S103F2
32
20
20
28
16
16
27
16
16
7
7
7
3
0
0
4
5
5
21
12
12
8K
8K
4K
640
(1)
1K
1K
1K
Multipurpose timer (TIM1),
SPI, I
2
C, UART window WDG, independent WDG,
ADC
PWM timer (TIM2)
8-bit timer (TIM4)
1.
No read-while-write (RWW) capability
15441 Rev 3
STM8S103x Block diagram
Figure 1.
Block diagram
Reset
Single wire debug interf.
400 Kbit/s
8 Mbit/s
LIN master
SPI emul.
Up to 5 channels
1/2/4 kHz beep
Reset block
POR
Reset
BOR
Clock controller
Detector
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I
2
C
SPI
UART1
ADC1
Beeper
Clock to peripherals and core
Window WDG
Independent WDG
8 Kbytes program
Flash
640 bytes data EEPROM
1 Kbytes
RAM
16-bit advanced control
timer (TIM1)
16-bit general purpose
Timer (TIM2)
8-bit basic timer
(TIM4)
Up to
4 CAPCOM channels
+ 3 complementary outputs
Up to
3 CAPCOM channels
AWU timer
15441 Rev 3 11/95
Product overview STM8S103x
4.1
The following section intends to give an overview of the basic features of the STM8S103x access line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
●
●
●
●
Architecture and registers
●
●
●
●
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
●
●
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
●
●
●
●
●
●
●
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
12/95 15441 Rev 3
STM8S103x
4.2
Product overview
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.
Debug module
●
●
●
●
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
●
●
●
●
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 27 external interrupts on six vectors including TLI
Trap and reset interrupts
15441 Rev 3 13/95
Product overview
4.4
STM8S103x
Flash program and data EEPROM memory
●
●
●
8 Kbytes of Flash program single voltage Flash memory
640 bytes true data EEPROM
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to
.
The size of the UBC is programmable through the UBC option byte (
of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
●
●
Main program memory: Up to 8 Kbytes minus UBC
User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2.
Flash memory organisation
Data
EEPROM memory
Data memory area ( 640 bytes)
Option bytes
UBC area
Remains write protected during IAP
Programmable area from 64 bytes
(1 page) up to 8 Kbytes
(in 1 page steps)
Low density
Flash program memory
(8 Kbytes)
Program memory area
Write access possible for IAP
14/95 15441 Rev 3
STM8S103x Product overview
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
The clock controller distributes the system clock (f
MASTER)
coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
Features
●
●
●
●
●
●
●
Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master clock:
– 1-16 MHz high-speed external crystal (HSE)
– Up to 16 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the application.
Table 2.
Bit
PCKEN17
PCKEN16
PCKEN15
PCKEN14
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral clock
Bit
Peripheral clock
Bit
Peripheral clock
Bit
Peripheral clock
TIM1
TIM2
TIM3
TIM4
PCKEN13 UART1 PCKEN27 Reserved PCKEN23
PCKEN12 Reserved PCKEN26 Reserved PCKEN22
PCKEN11
PCKEN10
SPI
I
2
C
ADC
AWU
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
15441 Rev 3 15/95
Product overview STM8S103x
For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.
●
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
● Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
●
●
Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.
Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.
The watchdog system is based on two independent timers providing maximum security to the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application perfectly.
The application software must refresh the counter before time-out and during a limited time window.
A reset is generated in two situations:
1.
Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.
16/95 15441 Rev 3
STM8S103x Product overview
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter
●
●
●
Used for auto wakeup from active halt mode
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
4.10 TIM1 - 16-bit advanced control timer
●
●
●
●
●
●
●
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver
16-bit up, down and up/down autoreload counter with 16-bit prescaler
Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output
Synchronization module to control the timer with external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2 - 16-bit general purpose timer
●
●
●
●
●
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
3 individually configurable capture/compare channels
PWM mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
15441 Rev 3 17/95
Product overview STM8S103x
4.12 TIM4 - 8-bit basic timer
●
●
●
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Table 3.
Timer
Counter size (bits)
TIM1 16
TIM2 16
TIM4
TIM timer features
8
Prescaler
Counting mode
CAPCOM channels
Complem. outputs
Ext. trigger
Timer synchronization/ chaining
Any integer from
1 to 65536
Any power of 2 from 1 to 32768
Up/down
Up
Any power of 2 from 1 to 128
Up
4
3
0
3
0
0
Yes
No
No
No
4.13 Analog-to-digital converter (ADC1)
●
●
●
●
●
●
●
●
●
●
STM8S103x products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed input channels and the following main features:
Input voltage range: 0 to V
DD
Conversion time: 14 clock cycles
Single and continuous and buffered continuous conversion modes
Buffer size (n x 10 bits) where x = number of input channels
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
●
●
The following communication interfaces are implemented:
●
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.1 master capability
SPI : Full and half-duplex, 8 Mbit/s
I²C: Up to 400 Kbit/s
18/95 15441 Rev 3
STM8S103x Product overview
4.14.1 UART1
Main features
●
●
●
●
●
●
●
One Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN master mode
Single wire half duplex mode
●
●
●
●
Asynchronous communication (UART mode)
●
●
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
CPU
/16) and capable of following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
●
●
●
●
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
CPU
/16)
LIN master mode
●
●
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
4.14.2 SPI
●
●
●
●
●
●
●
Maximum speed: 8 Mbit/s (f
MASTER
/2) both for master and slave
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
15441 Rev 3 19/95
Product overview
4.14.3 I
2
C
●
●
●
●
I
2
C master features:
– Clock generation
– Start and stop generation
I
2
C slave features:
– Programmable I
2
C address detection
– Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)
STM8S103x
20/95 15441 Rev 3
STM8S103x
5 Pinout and pin description
Figure 3.
STM8S103K VFQFPN32/LQFP32 pinout
Pinout and pin description
NRST
OSCIN/PA1
OSCOUT/PA2
V
SS
VCAP
V
DD
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
5
6
7
8
3
4
1
2
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
9 10 11 12 13 14 1516
17
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to V
DD
not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function).
15441 Rev 3 21/95
Pinout and pin description STM8S103x
Table 5.
Pin no.
Table 4.
Type
Level
Legend/abbreviations
I= Input, O = Output, S = Power supply
Input CM = CMOS
Output speed
Port and control configuration
Output
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Input
Output
HS = High sink float = floating, wpu = weak pull-up
T = True open drain, OD = Open drain, PP = Push pull
Reset state
Bold X
VFQFPN32/LQFP32 pin description
Input Output
Pin name
Default alternate function
Alternate function after remap
[option bit]
1 NRST
2 PA1/OSCIN
3
4 V
5
6
7
8
9
10
11
12
13
VCAP
V
SS
DD
PA3/TIM2_CH3
[SPI_NSS]
PF4
PB7
PB6
PB5/I2C_SDA
PB4/I2C_SCL
PB3/AIN3/TIM1_
ETR
(2)
PA2/OSCOUT
14
PB2/AIN2/TIM1_CH
3N
S
S
S
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X HS
Reset
O1 X X
Port A1
Resonator/crystal in
O1 X X
Port A2
Resonator/crystal out
Digital ground
1.8 V regulator capacitor
Digital power supply
O3 X X
Port A3
Timer 2 channel 3
SPI master/ slave select
[AFR1]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
O1 X X
Port F4
O1 X X
Port B7
O1 X X
Port B6
O1 T
O1 T
(3)
Port B5
I
2
C data
Port B4
I
2
C clock
O3
O3
X
X
X
X
Port B3
Port B2
Analog input 3/
Timer 1 external trigger
Analog input 2/
Timer 1 - inverted channel 3
22/95 15441 Rev 3
STM8S103x Pinout and pin description
Table 5.
VFQFPN32/LQFP32 pin description (continued)
Input Output
Pin no.
Pin name
Default alternate function
Alternate function after remap
[option bit]
15
PB1/AIN1/TIM1_CH
2N
16
PB0/AIN0/TIM1_CH
1N
17
18
19
20
21
22
23
24
PE5/SPI_NSS
PC1/TIM1_CH1/
UART1_CK
PC2/TIM1_CH2
PC3/TIM1_CH3
PC4/TIM1_CH4/
CLK_CCO
PC5/SPI_SCK
PC6/SPI_MOSI
PC7/SPI_MISO
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port B1
Port B0
Analog input 1/
Timer 1 - inverted channel 2
Analog input 0/
Timer 1 - inverted channel 1
I/O
X
X X HS O3 X X
Port E5
SPI master/slave select
I/O
X
X X HS O3 X X
Port C1
Timer 1 - channel 1
UART1 clock
I/O
X
X X HS O3 X X
Port C2
Timer 1 - channel 2
I/O
X
X X HS O3 X X
Port C3
Timer 1 - channel 3
I/O
X
X X HS O3 X X
Port C4
Timer 1 - channel 4
/configurable clock output
I/O
X
X X HS O3 X X
Port C5
SPI clock
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port C6
Port C7
SPI master out/ slave in
SPI master in/ slave out
25
26
27
PD0/TIM1_BKIN
[CLK_CCO]
PD1/SWIM
PD2[TIM2_CH3]
I/O
X
X X HS O3 X X
Port D0
Timer 1 - break input
I/O X
X
X HS O4 X X
Port D1
SWIM data interface
Configurable clock output
[AFR5]
I/O
X
X X HS O3 X X
Port D2
Timer 2 - channel 3
[AFR1]
28
30
PD3/TIM2_CH2/
ADC_ETR
PD5/UART1_TX
I/O
X
X X HS O3 X X
Port D3
29
PD4/BEEP/TIM2_CH
1
I/O
X
X X HS O3 X X
Port D4
I/O
X
X X HS O3 X X
Port D5
Timer 2 - channel
2/ADC external trigger
Timer 2 - channel
1/BEEP output
UART1 data transmit
15441 Rev 3 23/95
24/95
Pinout and pin description STM8S103x
Table 5.
VFQFPN32/LQFP32 pin description (continued)
Input Output
Pin no.
Pin name
Default alternate function
Alternate function after remap
[option bit]
31 PD6/UART1_RX I/O
X
X X HS O3 X X
Port D6
UART1 data receive
32 PD7/TLI (TIM1_CH4) I/O
X
X X HS O3 X X
Port D7
Top level interrupt
Timer 1 - channel 4
[AFR6]
1.
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see
Table 16: Current characteristics
.
2.
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
3.
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V
DD implemented)
are not
Figure 4.
STM8S103F TSSOP20-pin pinout
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
UART1_RX/AIN6/(HS) PD6
NRST
OSCIN/PA1
OSCOUT/PA2
V
SS
VCAP
V
DD
[SPI_NSS] TIM2_CH3/(HS) PA3
1
2
3
4
5
8
9
6
7
10
20
19
18
17
16
15
14
13
12
11
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2 (HS) [AIN3] [TIM2_CH3]
PD1(HS)/SWIM
PC7 (HS)/SPI_MISO [TIM1_CH2]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
PB4 (T)/I
2
C_SCL [ADC_ETR]
PB5 (T)/ I
2
C_SDA [TIM1_BKIN]
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to V
DD
not implemented).
3.
[ ] alternate function remapping option.
15441 Rev 3
STM8S103x
Figure 5.
STM8S103F UFQFPN20-pin pinout
Pinout and pin description
NRST
OSCIN/PA1
OSCOUT/PA2
V
SS
VCAP
1
2
3
4
5
20 19 18 17 16
15
14
13
12
11
6 7 8
9 10
PD1(HS)/SWIM
PC7 (HS)/SPI_MISO [TIM1_CH2]
PC6 (HS)/SPI_MOSI [TIM1_CH1]
PC5 (HS)/SPI_SCK [TIM2_CH1]
PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to V
DD
not implemented).
3.
[ ] alternate function remapping option.
15441 Rev 3 25/95
Pinout and pin description STM8S103x
Table 6.
Pin no.
STM8S103F pin description
Pin name
Input Output
Default alternate function
Alternate function after remap
[option bit]
1 18
PD4/BEEP/TIM2_CH1
/UART1_CK
I/O
X
X X HS O3 X X
Port D4
Timer 2 - channel
1/BEEP output/
UART1 clock
2 19 PD5/AIN5/UART1_TX I/O
X
X X HS O3 X X
Port D5
Analog input 5/
UART1 data transmit
3 20 PD6/AIN6/UART1_RX I/O
X
X X HS O3 X X
Port D6
Analog input 6/
UART1 data receive
4 1 NRST I/O
X
Reset
5 2 PA1/OSCIN
(2)
I/O
X
X X O1 X X
Port A1
Resonator/crystal in
6 3 PA2/OSCOUT
7 4 V
8
9
10
11
12
13
5
6
7
8
9
10
SS
VCAP
V
DD
PA3/TIM2_CH3
[SPI_NSS]
PB5/I2C_SDA
[TIM1_BKIN]
PB4/I2C_SCL
PC3/TIM1_CH3 [TLI]
[TIM1_CH1N]
I/O
S
S
X
X X O1 X X
Port A2
Resonator/crystal out
Digital ground
1.8 V regulator capacitor
S Digital power supply
I/O
X
X X HS O3 X X
Port A3
Timer 2 channel 3
SPI master/ slave select
[AFR1]
I/O
I/O
X
X
X
X
O1 T
(3)
Port B5
Port B4
I
I
2
2
C data
C clock
Timer 1 - break input
[AFR4]
ADC external trigger
[AFR4]
I/O
X
X X HS O3 X X
Port C3
Timer 1 - channel
3
Top level interrupt
[AFR3]
Timer 1 - inverted channel 1
[AFR7]
26/95 15441 Rev 3
STM8S103x Pinout and pin description
Table 6.
Pin no.
STM8S103F pin description (continued)
Input Output
Pin name
Default alternate function
Alternate function after remap
[option bit]
14
15
16
17
18
19
20
11
12
13
14
15
16
17
PC4/CLK_CCO/
TIM1_CH4 [AIN2]
[TIM1_CH2N]
PC5/SPI_SCK
[TIM2_CH1]
PC6/SPI_MOSI
[TIM1_CH1]
PC7/SPI_MISO
[TIM1_CH2]
PD1/SWIM
PD2 [AIN3]
[TIM2_CH3]
PD3/AIN4/TIM2_CH2/
ADC_ETR
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C4
Port C5
Configurable clock output/Timer 1 - channel 4
SPI clock
Analog input 2
[AFR2]
Timer 1 - inverted channel 2
[AFR7]
Timer 2 - channel 1
[AFR0]
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C6
Port C7
SPI master out/ slave in
SPI master in/ slave out
Timer 1 - channel 1
[AFR0]
Timer 1 - channel 2
[AFR0]
I/O
X
X X HS O4 X X
Port D1
SWIM data interface
I/O
X
X X HS O3 X X
Port D2
I/O
X
X X HS O3 X X
Port D3
Analog input 4/
Timer 2 - channel
2/ADC external trigger
Analog input 3
[AFR2]
Timer 2 - channel 3
[AFR1]
1.
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see
Table 16: Current characteristics
.
2.
When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.
3.
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V
DD implemented).
are not
15441 Rev 3 27/95
Pinout and pin description STM8S103x
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function
. When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
28/95 15441 Rev 3
STM8S103x
6 Memory and register map
Figure 6.
Memory map
0x00 0000
RAM
(1 Kbyte)
513 bytes stack
0x00 03FF
0x00 0800
Reserved
0x00 3FFF
0x00 4000
0x00 427F
0x00 4280
0x00 47FF
0x00 4800
0x00 480A
0x00 480B
0x00 4864
0x00 4865
0x00 4870
0x00 4871
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
640 bytes data EEPROM
Reserved
Option bytes
Reserved
Unique ID
Reserved
GPIO and periph. reg.
(see
and
)
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
0x00 9FFF
0x00 A000
CPU/SWIM/debug/ITC registers
(see
)
32 interrupt vectors
Flash program memory
(8 Kbytes)
Memory and register map
0x02 7FFF
15441 Rev 3
Reserved
29/95
Memory and register map STM8S103x
Table 7.
Address
I/O port hardware register map
Block Register label
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
Port A
Port B
Port C
Port D
Port E
Port F
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PA_ODR
PA_IDR
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
Register name
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E control register 2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
Port F control register 2
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
30/95 15441 Rev 3
STM8S103x Memory and register map
0x00 505F
0x00 5060 to
0x00 5061
0x00 5062
0x00 5063
0x00 5064
0x00 5065 to
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2 to
0x00 50B2
0x00 50B3
0x00 50B4 to
0x00 50BF
0x00 50C0
0x00 50C1
0x00 50C2
0x
Table 8.
Address
General hardware register map
Block Register label
0x00 501E to
0x00 5059
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
Flash
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
FLASH _IAPSR
Register name
Reserved area (60 bytes)
Flash control register 1
Flash control register 2
Flash complementary control register 2
Flash protection register
Flash complementary protection register
Flash in-application programming status register
Flash
Flash
ITC
RST
CLK
Reserved area (2 bytes)
Reset status
0x00
FLASH _PUKR
Flash program memory unprotection register
Reserved area (1 byte)
FLASH _DUKR Data EEPROM unprotection register
0x00
0x00
EXTI_CR1
EXTI_CR2
RST_SR
Reserved area (59 bytes)
External interrupt control register 1
External interrupt control register 2
Reserved area (17 bytes)
Reset status register
Reserved area (12 bytes)
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x00
0x00 xx
0x01
0x00
0x00
0x00
0xFF
0x00
0xFF
15441 Rev 3 31/95
Memory and register map STM8S103x
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
0x00 50CE to
0x00 50D0
0x00 50D1
0x00 50D2
0x00 50D3 to
00 50DF
0x00 50E0
0x00 50E1
0x00 50E2
0x00 50E3 to
0x00 50EF
0x00 50F0
Table 8.
Address
General hardware register map (continued)
0x00 50C3
0x00 50C4
0x00 50C5
Block
CLK
Register label
CLK_CMSR
CLK_SWR
CLK_SWCR
Register name
Clock master status register
Clock master switch register
Clock switch control register
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK_CCOR
Clock divider register
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
CLK_PCKENR2
CLK_CANCCR
Peripheral clock gating register 2
CAN clock control register
CLK_HSITRIMR HSI clock calibration trimming register
CLK_SWIMCCR SWIM clock control register
Reset status
0xE1
0xE1
0bxxxx
0000
0x18
0xFF
0x00
0x00
0xFF
0x00 xx x0
WWDG
IWDG
WWDG_CR
WWDG_WR
IWDG_KR
IWDG_PR
IWDG_RLR
AWU_CSR1
Reserved area (3 bytes)
WWDG control register
WWDR window register
Reserved area (13 bytes)
IWDG key register
IWDG prescaler register
IWDG reload register
Reserved area (13 bytes)
0x7F
0x7F
-
0x00
0xFF
0x00
0x00 50F1
0x00 50F2
0x00 50F3
0x00 50F4 to
0x00 50FF
AWU
BEEP
AWU_APR
AWU_TBR
BEEP_CSR
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
Reserved area (12 bytes)
0x3F
0x00
0x1F
32/95 15441 Rev 3
STM8S103x Memory and register map
Table 8.
Address
General hardware register map (continued)
Block Register label Register name
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
0x00 5208 to
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
0x00 521F to
0x00 522F
SPI
I
2
C
SPI_CR1
SPI_CR2
SPI_ICR
SPI_SR
SPI_DR
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
I2C_CR1
I2C_CR2
I2C_FREQR
I2C_OARL
I2C_OARH
I2C_DR
I2C_SR1
I2C_SR2
I2C_SR3
I2C_ITR
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
SPI data register
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
Reserved area (8 bytes)
I
2
C control register 1
I
2
C control register 2
I
2
C frequency register
I
2
C Own address register low
I
2
C Own address register high
Reserved
I
2
C data register
I
2
C status register 1
I
2
C status register 2
I
2
C status register 3
I
2
C interrupt control register
I
2
C Clock control register low
I
2
C Clock control register high
I
2
C TRISE register
I
2
C packet error checking register
Reserved area (17 bytes)
Reset status
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0x
0x00
0x00
0x00
0x02
0x00
15441 Rev 3 33/95
Memory and register map STM8S103x
Table 8.
Address
General hardware register map (continued)
Block Register label Register name
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
0x00 523B to
0x00 523F
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
UART1
UART1_SR
UART1_DR
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
TIM1
UART1 status register
UART1 data register
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
Reserved area (21 bytes)
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1 control register 1
TIM1 control register 2
TIM1 slave mode control register
TIM1 external trigger register
TIM1 interrupt enable register
TIM1 status register 1
TIM1 status register 2
TIM1 event generation register
TIM1 capture/compare mode register
1
TIM1 capture/compare mode register
2
TIM1 capture/compare mode register
3
TIM1 capture/compare mode register
4
TIM1 capture/compare enable register
1
TIM1 capture/compare enable register
2
TIM1 counter high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
00h
00h
00h
00h
C0h xxh
00h
00h
00h
00h
00h
34/95 15441 Rev 3
STM8S103x Memory and register map
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
0x00 5270 to
0x00 52FF
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
Table 8.
Address
General hardware register map (continued)
Block
TIM1 cont’d
Register label Register name
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1 counter low
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1_ARRL
TIM1_RCR
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1_CCR1H TIM1 capture/compare register 1 high
TIM1_CCR1L TIM1 capture/compare register 1 low
TIM1_CCR2H TIM1 capture/compare register 2 high
TIM1_CCR2L TIM1 capture/compare register 2 low
TIM1_CCR3H TIM1 capture/compare register 3 high
TIM1_CCR3L TIM1 capture/compare register 3 low
TIM1_CCR4H TIM1 capture/compare register 4 high
TIM1_CCR4L TIM1 capture/compare register 4 low
TIM1_BKR
TIM1_DTR
TIM1_OISR
TIM1 break register
TIM1 dead-time register
TIM1 output idle state register
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5307
0x00 5308
0x00 5309
0x00 530A
TIM2
Reserved area (147 bytes)
TIM2_CR1
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2 control register 1
Reserved
Reserved
TIM2 Interrupt enable register
TIM2 status register 1
TIM2 status register 2
TIM2 event generation register
TIM2 capture/compare mode register
1
TIM2 capture/compare mode register
2
TIM2 capture/compare mode register
3
TIM2 capture/compare enable register
1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
15441 Rev 3 35/95
Memory and register map STM8S103x
00 530C0x
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
0x00 5317 to
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
0x00 5349 to
0x00 53DF
0x00 53E0 to
0x00 53F3
0x00 53F4 to
0x00 53FF
Table 8.
Address
General hardware register map (continued)
0x00 530B
Block
TIM2 cont’d
Register label Register name
Reset status
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2 capture/compare enable register
2
TIM2 counter high
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2_ARRL TIM2 auto-reload register low
TIM2_CCR1H TIM2 capture/compare register 1 high
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2_CCR3H TIM2 capture/compare register 3 high
TIM2_CCR3L TIM2 capture/compare register 3 low
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM4
ADC1
TIM4_CR1
TIM4_IER
TIM4_SR
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
ADC _DBxR
Reserved area (43 bytes)
TIM4 control register 1
Reserved
Reserved
TIM4 interrupt enable register
TIM4 status register
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
Reserved area (153 bytes)
ADC data buffer registers
Reserved area (12 bytes)
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
36/95 15441 Rev 3
STM8S103x Memory and register map
Table 8.
Address
General hardware register map (continued)
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
0x00 540D
0x00 540E
0x00 540F
Block
ADC1 cont’d
Register label
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC_TDRH
ADC_TDRL
ADC_HTRH
ADC_HTRL
ADC_LTRH
ADC_LTRL
ADC_AWSRH
ADC_AWSRL
ADC _AWCRH
ADC_AWCRL
Register name
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
ADC data register low
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
ADC analog watchdog status register high
ADC analog watchdog status register low
ADC analog watchdog control register high
ADC analog watchdog control register low
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00 5410 to 0x00
57FF
Reserved area (1008 bytes)
15441 Rev 3 37/95
Memory and register map
Table 9.
Address
CPU/SWIM/debug module/interrupt controller registers
Block Register label Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
CPU
(1)
0x00 7F08
0x00 7F09
0x00 7F0A
0x00 7F0B to 0x00
7F5F
0x00 7F60
0x00 7F70
CPU
0x00 7F71
0x00 7F72
0x00 7F73
ITC
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
0x00 7F78 to
0x00 7F79
0x00 7F80 SWIM
0x00 7F81 to
0x00 7F8F
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
XH
XL
YH
YL
A
PCE
PCH
PCL
SPH
SPL
CCR
SWIM_CSR
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
Stack pointer low
Condition code register
Reserved area (85 bytes)
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
STM8S103x
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
38/95 15441 Rev 3
STM8S103x Memory and register map
Table 9.
Address
CPU/SWIM/debug module/interrupt controller registers (continued)
Block Register label Register name
Reset status
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
0x00 7F9B to
0x00 7F9F
DM
1.
Accessible by debug module only
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
Reserved area (5 bytes)
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
15441 Rev 3 39/95
Interrupt vector mapping
7 Interrupt vector mapping
STM8S103x
9
10
6
7
4
5
8
2
3
0
1
17
18
19
20
21
12
13
14
15
16
Table 10.
Interrupt mapping
IRQ no.
Source block
Description
11
22
23
24
RESET Reset
TRAP Software interrupt
TLI
AWU
External top level interrupt
Auto wake up from halt
CLK
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
Clock controller
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Reserved
SPI
TIM1
Reserved
End of transfer
TIM1 update/overflow/underflow/ trigger/break
TIM1 capture/compare TIM1
TIM2
TIM2
TIM2 update /overflow
TIM2 capture/compare
Reserved
Reserved
UART1 Tx complete
UART1 Receive register DATA FULL
I
2
C I
2
C interrupt
ADC1
TIM4
Reserved
Reserved
ADC1 end of conversion/analog watchdog interrupt
TIM4 update/overflow
Flash EOP/WR_PG_DIS
Reserved
1.
Except PA1
-
-
-
Yes
-
-
-
-
-
-
-
Wakeup from halt mode
Wakeup from active-halt mode
Yes
Yes
Yes
Yes
-
Yes
-
-
-
-
Yes
(1)
-
Yes
Yes
Yes
Yes
Yes
-
Yes
-
-
Yes
-
Yes
-
Yes
-
-
-
-
-
-
-
-
-
Yes
-
-
-
-
-
-
-
Vector address
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8060
0x00 8064
0x00 806C to
0x00 807C
40/95 15441 Rev 3
STM8S103x Option bytes
Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in
below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.
Table 11.
Option bytes
Addr.
Option name
Option byte no.
0x4800
Read-out protection
(ROP)
0x4801
User boot code(UBC)
0x4802
0x4803 Alternate
0x4804 function remapping
(AFR)
OPT0
OPT1
NOPT1
OPT2
NOPT2
7
AFR7
6
AFR6
5
AFR5
NAFR7 NAFR6 NAFR5
4
Option bits
3
ROP[7:0]
UBC[7:0]
AFR4
NUBC[7:0]
AFR3
NAFR4 NAFR3
2
AFR2
NAFR2
1
AFR1
NAFR1
0
AFR0
NAFR0
Factory default setting
00h
00h
FFh
00h
FFh
0x4805h
0x4806
OPT3
Miscellaneous option
NOPT3
0x4807
0x4808
Clock option
0x4809
0x480A
HSE clock startup
OPT4
NOPT4
OPT5
NOPT5
Reserved
Reserved
Reserved
Reserved
HSITRIM
NHSI-
TRIM
LSI
_EN
NLSI
_EN
EXT
CLK
NEXT
CLK
HSECNT[7:0]
NHSECNT[7:0]
IWDG
_HW
WWDG
_HW
NIWDG_H
W
NWWDG
_HW
CKAWU
SEL
NCKAWUS
EL
PRS
C1
NPR
SC1
WWDG
_HALT
NWWG
_HALT
PRS
C0
NPR
SC0
00h
FFh
00h
FFh
00h
FFh
15441 Rev 3 41/95
42/95
Option bytes STM8S103x
Table 12.
Option byte description
Option byte no.
OPT0
OPT1
OPT2
OPT3
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and
1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory write-protected
Note: Refer to the family reference manual (RM0016) section on Flash write protection for more details.
AFR[7:0]
Refer to
respectively for alternate function
remapping descriptions for 32-pin and 20-pin devices.
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
15441 Rev 3
STM8S103x Option bytes
Table 12.
Option byte description (continued)
Option byte no.
Description
OPT4
OPT5
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
Table 13.
STM8S103K alternate function remapping bits for 32-pin devices
Option byte no.
Description
(1)
OPT2
AFR7 Alternate function remapping option 7
Reserved.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function
(2)
.
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function
.
1: Port D0 alternate function = CLK_CCO.
AFR[4:2] Alternate function remapping options 4:2
Reserved.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions
1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0
Reserved.
1.
Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0.
2.
Refer to pinout description.
15441 Rev 3 43/95
Option bytes STM8S103x
Table 14.
STM8S103F alternate function remapping bits for 20-pin devices
Option byte no.
Description
OPT2
AFR7Alternate function remapping option 7
0: AFR7 remapping option inactive: Default alternate functions
(1)
.
1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
Reserved.
AFR5 Alternate function remapping option 5
Reserved.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate functions
.
1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
0: AFR2 remapping option inactive: Default alternate functions
.
1: Port C4 alternate function = AIN2; port D2 alternate function = AIN3.
AFR1 Alternate function remapping option 1
(2)
0: AFR1 remapping option inactive: Default alternate functions
.
1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate functions
.
1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1; port C7 alternate function = TIM1_CH2.
1.
Refer to pinout description.
2.
Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0.
44/95 15441 Rev 3
STM8S103x Unique ID
0x4865
0x4866
0x4867
0x4868
0x4869
0x486A
0x486B
0x486C
0x486D
0x486E
0x486F
0x4870
STM8S103x devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user.
The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
●
●
The unique device identifier is ideally suited:
For use as serial numbers
For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory.
● To activate secure boot processes
Table 15.
Unique ID registers (96 bits)
Unique ID bits
Address
Content description
X co-ordinate on the wafer
Y co-ordinate on the wafer
Wafer number
Lot number
7 6 5 4 3
U_ID[7:0]
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
2 1 0
15441 Rev 3 45/95
Electrical characteristics STM8S103x
Unless otherwise specified, all voltages are referred to V
SS
.
10.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at T
A
= 25 °C and T
A
= T
Amax
(given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3
Σ).
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
= 5 V. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2
Σ)
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
The loading conditions used for pin parameter measurement are shown in
.
Figure 7.
Pin loading conditions
STM8 PIN
50 pF
46/95 15441 Rev 3
STM8S103x Electrical characteristics
10.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 8.
Pin input voltage
STM8 PIN
V
IN
10.2 Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 16.
Voltage characteristics
V
Symbol
DDx
V
- V
IN
SS
Ratings
Supply voltage
(1)
Input voltage on true open drain pins
(2)
Input voltage on any other pin
|V
DDx
- V
DD
| Variations between different power pins
|V
SSx
- V
SS
| Variations between all the different ground pins
V
ESD
Electrostatic discharge voltage
Min Max
-0.3
6.5
V
SS
- 0.3
6.5
V
SS
- 0.3
V
DD
+ 0.3
50
50
Absolute maximum ratings (electrical sensitivity) on page 81
Unit
V mV
1.
All power (V
DD
) and ground (V
SS
) pins must always be connected to the external power supply
2.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V
IN injection is induced by V
IN
>V
DD there is no positive injection current, and the corresponding V
IN
maximum is respected. If V
IN cannot be respected, the injection current must be limited externally to the I
INJ(PIN)
while a negative injection is induced by V
IN
<V
SS
maximum
value. A positive
. For true open-drain pads,
maximum must always be respected
15441 Rev 3 47/95
Electrical characteristics STM8S103x
Table 17.
Current characteristics
Symbol Ratings Max.
(1)
Unit
I
I
VDD
VSS
Total current into V
DD power lines (source)
(2)
Total current out of V
SS
Output current sunk by any I/O and control pin
100
80
20
I
IO
Output current source by any I/Os and control pin - 20 mA
Injected current on NRST pin ± 4
I
INJ(PIN)
(3)(4)
Injected current on OSCIN pin
Injected current on any other pin
(5)
Total injected current (sum of all I/O and control pins)
± 4
± 4
ΣI
± 20
1.
Data based on characterization results, not tested in production.
2.
All power (V
DD
) and ground (V
SS
) pins must always be connected to the external supply.
3.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V
IN injection is induced by V
IN
>V
DD there is no positive injection current, and the corresponding V
IN
maximum is respected. If V
IN cannot be respected, the injection current must be limited externally to the I
INJ(PIN)
while a negative injection is induced by V
IN
<V
SS
maximum
value. A positive
. For true open-drain pads,
maximum must always be respected
4.
Negative injection disturbs the analog performance of the device. See note in
Section 10.3.10: 10-bit ADC characteristics on page 77
.
5.
When several inputs are submitted to a current injection, the maximum
Σ
I
INJ(PIN)
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with
Σ
I
INJ(PIN)
maximum current injection on four I/O port pins of the device.
Table 18.
Thermal characteristics
Symbol Ratings
T
STG
T
J
Storage temperature range
Maximum junction temperature
Value
-65 to +150
150
Unit
°C
48/95 15441 Rev 3
STM8S103x Electrical characteristics
Table 19.
General operating conditions
Symbol Parameter Conditions Min Max Unit
f
CPU
V
DD
C
EXT
P
D
(2)
T
A
T
J
Internal CPU clock frequency
Standard operating voltage
VCAP external capacitor
(1)
0.05
≤ ESR ≤ 0.2 Ω at
1 MHz
LQFP32
Power dissipation at
T
A
= 85 °C for suffix 6
Power dissipation at
T
A
= 125 °C for suffix 3
VFQFPN32
TSSOP20
UFQFPN20
LQFP32
VFQFPN32
TSSOP20
UFQFPN20
Ambient temperature for 6 suffix version
Ambient temperature for 3 suffix version
Maximum power dissipation
Maximum power dissipation
0
2.95
470
-40
-40
16
5.5
3300
330
550
227
220
83
110
59
55
85
125
Junction temperature range
3 suffix version
-40
-40 130
(3)
MHz
V nF mW
°C
1.
Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on temperature, DC bias and frequency in addition to other factors
2.
To calculate P
Dmax
(T
A
), use the formula P
Jmax
Dmax
= (T
- T
A
)/
Θ
JA
and the value for
Θ
JA given in
3.
T
Jmax is given by the test limit. Above this value the product behavior is not guaranteed.
15441 Rev 3 49/95
Electrical characteristics
Figure 9.
f
CPUmax
versus V
DD
f
CPU
[MHz]
STM8S103x
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
12
8
4
0
FUNCTIONALITY
GUARANTEED
@ T
A
-40 to 125 ¬
2.95
4.0
5.0
SUPPLY VOLTAGE [V]
5.5
Table 20.
Operating conditions at power-up/power-down
Symbol Parameter Conditions Min
V t t
VDD
TEMP
V
V
IT+
IT-
HYS(BOR)
V
DD
rise time rate
V
DD
fall time rate
(1)
Reset release delay
Power-on reset threshold
Brown-out reset threshold
Brown-out reset hysteresis
V
DD
rising
2
2
2.6
2.5
Typ
2.7
2.65
70
Max
∞
∞
1.7
2.85
2.8
1.
Reset is always generated after a t
TEMP
delay. The application must ensure that V
DD minimum ooperating voltage (V
DD
min) when the t
TEMP
delay has elapsed.
is still above the
Unit
µs/V ms
V mV
10.3.1 VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
EXT
to the
V
CAP
pin. C
EXT
. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 10.
External capacitor C
EXT
ESR C ESL
Rleak
1.
ESR is the equivalent series resistance and ESL is the equivalent inductance.
50/95 15441 Rev 3
STM8S103x Electrical characteristics
10.3.2 Supply current characteristics
The current consumption is measured as described in
.
Total current consumption in run mode
The MCU is placed under the following conditions:
●
●
All I/O pins in input mode with a static value at V or V
SS
(no load)
All peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned.
DD
Subject to general operating conditions for V
DD
and T
A
.
Table 21.
Total current consumption with code execution in run mode at V
DD
= 5 V
Symbol Parameter Conditions Typ Max
(1)
Unit
f
CPU
= f
MASTER
=
16 MHz
Supply current in run mode, code executed from
RAM
f
CPU
= f
MASTER
/128 =
125 kHz
f
CPU
= f
MASTER
/128 =
15.625 kHz
f
CPU
= f
MASTER
=
128 kHz
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
2.3
2
1.7
HSE user ext. clock (16 MHz) 0.86
HSI RC osc. (16 MHz) 0.7
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.41
I
DD(RUN)
f
CPU
= f
16 MHz
MASTER
=
HSE crystal osc. (16 MHz) 4.5
HSE user ext. clock (16 MHz) 4.3
HSI RC osc. (16 MHz) 3.7
Supply current in run mode, code executed from
Flash
f
CPU
= f
MASTER
=
2 MHz
f
CPU
= f
MASTER
/128 =
125 kHz
f
CPU
= f
MASTER
/128 =
15.625 kHz
f
CPU
= f
MASTER
=
128 kHz
HSI RC osc. (16 MHz/8)
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
1.
Data based on characterization results, not tested in production.
2.
Default clock configuration measured with all peripherals off.
(2)
0.84
0.72
0.46
0.42
2.35
2
0.87
0.58
0.55
4.75
4.5
1.05
0.9
0.58
0.57
mA
15441 Rev 3 51/95
Electrical characteristics STM8S103x
Table 22.
Total current consumption with code execution in run mode at V
DD
= 3.3 V
Symbol Parameter Conditions Typ Max
(1)
HSE crystal osc. (16 MHz)
f
CPU
= f
MASTER
=
16 MHz
HSE user ext. clock (16 MHz)
Supply current in run mode, code executed from RAM
f
CPU kHz
= f
MASTER
/128 = 125
f
CPU
= f
MASTER
/128 =
15.625 kHz
HSI RC osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
f
CPU
= f
MASTER
=
128 kHz
LSI RC osc. (128 kHz)
I
DD(RUN)
f
CPU
= f
MASTER
=
16 MHz
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
f
CPU
= f
MASTER
=
128 kHz
HSI RC osc. (16 MHz)
Supply current in run mode, code executed from Flash
f
CPU
= f
MASTER
=
2 MHz
f
CPU kHz
= f
MASTER
/128 = 125
HSI RC osc. (16 MHz/8)
HSI RC osc. (16 MHz)
(2)
f
CPU
= f
MASTER
/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
1.
Data based on characterization results, not tested in production.
2.
Default clock configuration measured with all peripherals off.
1.8
2
1.5
0.81
0.7
0.46
0.41
4
3.9
3.7
0.84
0.72
0.46
0.42
2.3
2
0.87
0.58
0.55
4.7
4.5
1.05
0.9
0.58
0.57
Unit
mA
52/95 15441 Rev 3
STM8S103x
Total current consumption in wait mode
Table 23.
Total current consumption in wait mode at V
DD
= 5 V
Symbol Parameter Conditions
f
CPU
= f
16 MHz
MASTER
=
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
I
DD(WFI)
Supply current in wait mode f
CPU
= f
MASTER
/128 =
125 kHz
f
CPU
= f
MASTER
/128 =
15.625 kHz
f
CPU
= f
MASTER
=
128 kHz
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
1.
Data based on characterization results, not tested in production.
2.
Default clock configuration measured with all peripherals off.
(2)
Table 24.
Total current consumption in wait mode at V
DD
= 3.3 V
Symbol Parameter Conditions
f
CPU
= f
16 MHz
MASTER
=
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
I
DD(WFI)
Supply current in wait mode f
CPU
= f
125 kHz
MASTER
/128 =
f
CPU
= f
MASTER
/128 =
15.625 kHz
f
CPU
= f
MASTER
=
128 kHz
HSI RC osc. (16 MHz)
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
1.
Data based on characterization results, not tested in production.
2.
Default clock configuration measured with all peripherals off.
(2)
Electrical characteristics
Typ
1.6
1.1
0.89
0.7
0.45
0.4
Max
(1)
Unit
1.3
1.1
0.88
0.57
0.54
mA
Typ
1.1
1.1
0.89
0.7
0.45
0.4
Max
(1)
Unit
1.3
1.1
0.88
0.57
0.54
mA
15441 Rev 3 53/95
Electrical characteristics STM8S103x
Total current consumption in active halt mode
Table 25.
Total current consumption in active halt mode at V
DD
= 5 V
Conditions
Symbol Parameter
Main voltage regulator
(MVR)
(2)
Flash mode
(3)
Clock source
I
DD(AH)
Supply current in active halt mode
On
Off
Operating mode
HSE crystal osc.
(16 MHz)
LSI RC osc.
(128 kHz)
Power-down mode
HSE crystal osc.
(16 MHz)
LSI RC osc.
(128 kHz)
Operating mode
Power-down mode
LSI RC osc.
(128 kHz)
1.
Data based on characterization results, not tested in production
2.
Configured by the REGAH bit in the CLK_ICKR register.
3.
Configured by the AHALT bit in the FLASH_CR1 register.
Typ
1030
200
970
150
66
10
Max at 85
°C
(1)
Max at
125 °C
Unit
260
200
85
20
300
230
110
40
µA
Table 26.
Total current consumption in active halt mode at V
DD
= 3.3 V
Conditions
Symbol Parameter
Main voltage regulator
(MVR)
(2)
Flash mode
(3)
Clock source
I
DD(AH)
Supply current in active halt mode
On
Off
HSE crystal osc.
(16 MHz)
Operating mode
LSI RC osc.
(128 kHz)
Power-down mode
HSE crystal osc.
(16 MHz)
LSI RC osc.
(128 kHz)
Operating mode
Power-down mode
LSI RC osc.
(128 kHz)
1.
Data based on characterization results, not tested in production
2.
Configured by the REGAH bit in the CLK_ICKR register.
3.
Configured by the AHALT bit in the FLASH_CR1 register.
Typ
550
200
970
150
66
10
Max at
85 °C
(1)
Max at
125 °C
Unit
260
200
80
18
290
230
105
35
µA
54/95 15441 Rev 3
STM8S103x Electrical characteristics
Total current consumption in halt mode
Table 27.
Total current consumption in halt mode at V
DD
= 5 V
Symbol Parameter Conditions
I
DD(H)
Flash in operating mode, HSI clock after wakeup
Supply current in halt mode
Flash in power-down mode, HSI clock after wakeup
1.
Data based on characterization results, not tested in production
Typ
63
Max at
85 °C
(1)
Max at
125 °C
Unit
75 105
µA
6.0
15 35
Table 28.
Total current consumption in halt mode at V
DD
= 3.3 V
Symbol Parameter Conditions Typ
Max at
85 °C
(1)
Max at
Unit
I
DD(H)
Supply current in halt mode
Flash in operating mode, HSI clock after wakeup 60
Flash in power-down mode, HSI clock after wakeup 4.5
1.
Data based on characterization results, not tested in production
75
12
100
30
µA
Low power mode wakeup times
Table 29.
Wakeup times
Symbol Parameter Conditions Typ Max
(1)
Unit
See note
(2) t t t
WU(WFI)
WU(AH)
WU(H)
Wakeup time from wait mode to run mode
f
CPU
= f
MASTER
= 16 MHz.
Flash in operating mode
(5)
MVR voltage regulator on
(4)
Flash in powerdown mode
Wakeup time active halt mode to run mode
(3)
Flash in operating mode
MVR voltage regulator off
Flash in powerdown mode
Flash in operating mode
Wakeup time from halt mode to run mode
Flash in power-down mode
HSI
(after wakeup)
1.
Data guaranteed by design, not tested in production.
2.
t
WU(WFI)
= 2 x 1/f master
+ 6 x 1/f
CPU.
3.
Measured from interrupt event to interrupt vector fetch.
4.
Configured by the REGAH bit in the CLK_ICKR register.
5.
Configured by the AHALT bit in the FLASH_CR1 register.
6.
Plus 1 LSI clock depending on synchronization.
0.56
1
3
(6)
52
54
2
µs
15441 Rev 3 55/95
56/95
Electrical characteristics STM8S103x
Total current consumption and timing in forced reset state
Table 30.
Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Max
(1)
I
DD(R)
Supply current in reset state
(2)
V
DD
= 5 V
V
DD
= 3.3 V
400
300 t
RESETBL
Reset pin release to vector fetch
1.
Data guaranteed by design, not tested in production.
2.
Characterized with all I/Os tied to V
SS
.
150
Unit
µA
µs
Current consumption of on-chip peripherals
Subject to general operating conditions for V
DD
and T
A
.
HSI internal RC/f
CPU
= f
MASTER
= 16 MHz, V
DD
= 5 V
Table 31.
Peripheral current consumption
Symbol Parameter Typ.
Unit
I
DD(TIM1)
I
DD(TIM2)
I
DD(TIM4)
I
DD(UART1)
I
DD(SPI)
I
DD(I
2
C)
I
DD(ADC1)
TIM1 supply current
TIM2 supply current
SPI supply current
I
2
(1)
UART1 supply current
(2)
ADC1 supply current when converting
(3)
210
130
50
120
45
65
1000
µA
1.
Data based on a differential I
DD
measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2.
Data based on a differential I
DD
measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production.
3.
Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions. Not tested in production.
15441 Rev 3
STM8S103x Electrical characteristics
Current consumption curves
show typical current consumption measured with code executing in
RAM.
Figure 11.
Typ I
DD(RUN)
vs. V
DD
HSE user external clock, f
CPU
= 16 MHz
2.3
2.25
25˚C
85˚C
125˚C
-45˚C
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
2 2.5
3 3.5
TBD
4
V
DD
(V)
4.5
5 5.5
6
Figure 12.
Typ I
DD(RUN)
vs. f
CPU
HSE user external clock, V
DD
= 5 V
2.5
25˚C
85˚C
125˚C
-45˚C
2
1.5
1
0.5
TBD
0
2 4 6 8 10
F
CPU
(MHz)
12 14 16 18
15441 Rev 3 57/95
Electrical characteristics
Figure 13.
Typ I
DD(RUN)
vs. V
DD
HSI RC osc, f
CPU
= 16 MHz
2
1.95
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
2 2.5
3
TBD
3.5
4
V
DD
(V)
4.5
5 5.5
6
25˚C
85˚C
125˚C
-45˚C
Figure 14.
Typ I
DD(WFI)
vs. V
DD
HSE user external clock, f
CPU
= 16 MHz
1.8
1.6
25˚C
85˚C
125˚C
-45˚C
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2 2.5
3 3.5
TBD
4
V
DD
(V)
4.5
5 5.5
6
Figure 15.
Typ I
DD(WFI)
vs. f
CPU
HSE user external clock, V
DD
= 5 V
1.2
1
0.8
0.6
1.8
1.6
1.4
0.4
0.2
0
2 4 6 8
TBD
10
F
CPU
(MHz)
12 14 16 18
25˚C
85˚C
125˚C
-45˚C
STM8S103x
58/95 15441 Rev 3
STM8S103x Electrical characteristics
Figure 16.
Typ I
DD(WFI)
vs. V
DD
HSI RC osc, f
CPU
= 16 MHz
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2 2.5
3
TBD
3.5
4
F
CPU
(MHz)
4.5
5 5.5
6
25˚C
85˚C
125˚C
-45˚C
15441 Rev 3 59/95
Electrical characteristics STM8S103x
HSE user external clock
Subject to general operating conditions for V
DD
and T
A
.
Table 32.
HSE user external clock characteristics
Symbol Parameter Conditions
f
V
HSE_ext
HSEH
(1)
User external clock source frequency
OSCIN input pin high level voltage
V
HSEL
OSCIN input pin low level voltage
I
LEAK_HSE
OSCIN input leakage current V
SS
< V
IN
< V
DD
1.
Data based on characterization results, not tested in production.
Min
0
Max
16
Unit
MHz
0.7 x V
DD
V
DD
+ 0.3 V
V
SS
-1
0.3 x V
DD
+1
V
µA
Figure 17.
HSE external clock source
V
HSEH
V
HSEL
External clock source
OSCIN f
HSE
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
60/95 15441 Rev 3
STM8S103x Electrical characteristics
Table 33.
HSE oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE
R
F
C
(1)
External high speed oscillator frequency
Feedback resistor
Recommended load capacitance
(2)
C = 20 pF, f
OSC
= 16 MHz
1
220
16
20
6 (startup)
1.6
(stabilized)
(3)
MHz k
Ω pF
I
DD(HSE)
HSE oscillator power consumption
C = 10 pF, f
OSC
=16 MHz
6 (startup)
1.2
(stabilized)
mA g m t
SU(HSE)
(4)
Oscillator transconductance
Startup time V
DD
is stabilized
5
1 mA/V ms
1.
C is approximately equivalent to 2 x crystal Cload.
2.
The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R m
Refer to crystal manufacturer for more details
value.
3.
Data based on characterization results, not tested in production.
4.
t
SU(HSE)
is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18.
HSE oscillator circuit diagram
R m
L m
C
O
C m
Resonator
C
L1
OSCIN
R
F g m f
HSE
to core
Consumption control
Resonator
STM8
OSCOUT
C
L2
HSE oscillator critical g m
formula
g mcrit
=
(
2
× Π × f
HSE
)
2
×
R m
(
2Co + C
)
2
R m
: Notional resistance (see crystal specification)
L m
: Notional inductance (see crystal specification)
C m
: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
C
L1
= C
L2
= C: Grounded external capacitance g m
>> g mcrit
15441 Rev 3 61/95
Electrical characteristics STM8S103x
10.3.4 Internal clock sources and timing characteristics
Subject to general operating conditions for V
DD
and T
A
.
High speed internal RC oscillator (HSI)
Table 34.
HSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max
f
HSI
Frequency 16
ACC
HSI t su(HSI)
Accuracy of HSI oscillator
Accuracy of HSI oscillator
(factory calibrated)
User-trimmed with
CLK_HSITRIMR register for given V conditions
DD
(1)
and T
A
V
DD
= 5 V, T
A
= 25°C
(2)
V
DD
= 5 V,
25 °C
≤ T
A
≤ 85 °C
2.95
≤ V
DD
-40 °C
≤ T
A
≤ 5.5 V,
≤ 125 °C
HSI oscillator wakeup time including calibration
-2.5
-2.5
4.5
-
(3)
I
DD(HSI)
HSI oscillator power consumption
170
3
2
1
(4)
1.
Refer to application note.
2.
Data based on characterization results, not tested in production
3.
Subject to further characterization to give better results
4.
Guaranteeed by design, not tested in production.
Unit
MHz
%
%
%
%
µs
µA
Figure 19.
Typical HSI accuracy at V
DD
= 5 V vs 5 temperatures
3.00%
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
-40 0
TBD
25 85 125 max min
62/95 15441 Rev 3
STM8S103x Electrical characteristics
Figure 20.
Typical HSI frequency variation vs V
DD
@ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
1.00%
0.50%
0.00%
-0.50%
TBD
-1.00%
-1.50%
-2.00%
2.5
3 3.5
4
V
DD
(V)
4.5
5 5.5
6
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V
DD
and T
A
.
Table 35.
LSI oscillator characteristics
Symbol Parameter
f
LSI t su(LSI)
I
DD(LSI)
Min
Frequency 110
LSI oscillator wake-up time
LSI oscillator power consumption
Typ
128
5
Max
150
7
Figure 21.
Typical LSI frequency variation vs V
DD
@ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
2 2.5
3 4.5
5 5.5
6 3.5
4
V
DD
(V)
Unit
kHz
µs
µA
15441 Rev 3 63/95
Electrical characteristics STM8S103x
RAM and hardware registers
Table 36.
RAM and hardware registers
Symbol Parameter Conditions Min Unit
V
RM
Data retention mode
(1)
Halt mode (or reset) V
IT-max
(2)
1.
Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
2.
for the value of V
IT-max
V
Flash program memory/data EEPROM memory
Table 37.
Flash program memory/data EEPROM memory
Symbol Parameter Conditions Min
(1)
Typ Max Unit
t t prog erase
N t
V
I
DD
RW
RET
DD
Operating voltage
(all modes, execution/write/erase)
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/64 bytes)
Fast programming time for 1 block (64 bytes)
Erase time for 1 block (64 bytes)
Erase/write cycles
(2)
(program memory)
Erase/write cycles
Data retention (program and data memory) after 10k erase/write cycles at T
A
= +55 °C
Data retention (data memory) after
300k erase/write cycles at T
A
= +125 °C
Supply current (Flash programming or erasing for 1 to 128 bytes) f
CPU
T
T
T
T
A
A
≤
= +85 °C
= +125 °C
RET
RET
= 55°C
= 85°C
2.95
10 k
300 k
20
1
6
3
3
1 M
2
5.5
6.6
3.33
3.33
1.
Data based on characterization results, not tested in production.
2.
The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
V ms cycles years mA
64/95 15441 Rev 3
STM8S103x Electrical characteristics
10.3.6 I/O port pin characteristics
General characteristics
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.
Table 38.
I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
V
IH
V hys
R pu t
R
, t
F
I lkg
I lkg ana
I lkg(inj)
Input low level voltage
Input high level voltage
Hysteresis
(1)
V
DD
= 5 V
Pull-up resistor V
DD
= 5 V, V
IN
= V
SS
Fast I/Os
Load = 50 pF
Rise and fall time
(10% - 90%)
Analog input leakage current
Standard and high sink I/Os
Load = 50 pF
Digital input leakage current
V
SS
≤
V
IN
≤
V
DD
V
SS
≤
V
IN
≤
V
DD
Leakage current in adjacent I/O
Injection current ±4 mA
-0.3 V
0.7 x V
DD
30
0.3 x V
DD
V
DD
+ 0.3 V
700
45 60
20
125
±1
±250
±1
V
V mV k
Ω ns ns
µA
1.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
15441 Rev 3 65/95
Electrical characteristics
Figure 22.
Typical V
IL
and V
IH
vs V
DD
@ 4 temperatures
6
5
4
3
2
1
0
2.5
3 3.5
TBD
4
V
DD
[V]
4.5
5 5.5
6
-40˚C
25˚C
85˚C
125˚C
Figure 23.
Typical pull-up resistance vs V
DD
@ 4 temperatures
60
55
-40˚C
25˚C
85˚C
125˚C
50
45
TBD
40
35
30
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6
Figure 24.
Typical pull-up current vs V
DD
@ 4 temperatures
140
120
100
80
60
40
20
0
0 1
Alain to send
2 3
V
DD
[V]
4 5
-40˚C
25˚C
85˚C
125˚C
6
STM8S103x
66/95 15441 Rev 3
STM8S103x Electrical characteristics
Table 39.
Output driving current (standard ports)
Symbol Parameter Conditions
V
V
OL
OH
Output low level with 8 pins sunk
Output low level with 4 pins sunk
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 4 mA, V
DD
= 3.3 V
Output high level with 8 pins sourced I
IO
= 10 mA, V
DD
= 5 V
Output high level with 4 pins sourced I
IO
= 4 mA, V
DD
= 3.3 V
1.
Data based on characterization results, not tested in production
Table 40.
Output driving current (true open drain ports)
Symbol Parameter Conditions
V
OL
Output low level with 2 pins sunk
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V
I
IO
= 20 mA, V
DD
= 5 V
1.
Data based on characterization results, not tested in production
Min
2.8
2.1
Max
1
1.5
(1)
Max
2
1
(1)
Table 41.
Output driving current (high sink ports)
Symbol Parameter Conditions
V
OL
Output low level with 8 pins sunk
Output low level with 4 pins sunk
Output low level with 4 pins sunk
Output high level with 8 pins sourced
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V
I
IO
= 20 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 5 V
I
IO
= 10 mA, V
DD
= 3.3 V V
OH
Output high level with 4 pins sourced
Output high level with 4 pins sourced I
IO
= 20 mA, V
DD
= 5 V
1.
Data based on characterization results, not tested in production
Min
4.0
2.1
3.3
Max
0.8
1
(1)
1.5
Figure 25.
Typ. V
OL
@ V
DD
= 5 V (standard ports)
1.5
1.25
1
0.75
0.5
0.25
0
0
-40˚C
25˚C
85˚C
125˚C
TBD
2 4 6
I
OL
[mA]
8 10 12
Unit
V
Unit
V
Unit
V
15441 Rev 3 67/95
Electrical characteristics
Figure 26.
Typ. V
OL
@ V
DD
= 3.3 V (standard ports)
1.5
1.25
1
0.75
0.5
0.25
0
0 1
-40˚C
25˚C
85˚C
125˚C
TBD
2 3
I
OL
[mA]
4 5 6 7
Figure 27.
Typ. V
OL
@ V
DD
= 5 V (true open drain ports)
2
1.75
1.5
1.25
0.75
1
TBD
-40˚C
25˚C
85˚C
125˚C
0.5
0.25
0
0 5 10
I
OL
[mA]
15
Figure 28.
Typ. V
OL
@ V
DD
= 3.3 V (true open drain ports)
2
1.75
1.5
1.25
-40˚C
25˚C
85˚C
125˚C
20 25
0.75
0.5
0.25
0
0 2 4 6
I
OL
[mA]
8 10 12 14
STM8S103x
68/95 15441 Rev 3
STM8S103x
Figure 29.
Typ. V
OL
@ V
DD
= 5 V (high sink ports)
1.5
1.25
1
0.75
0.5
0.25
0
0
-40˚C
25˚C
85˚C
125˚C
5
Alain to send
10
I
OL
[mA]
15 20 25
Figure 30.
Typ. V
OL
@ V
DD
= 3.3 V (high sink ports)
1.5
1.25
1
0.75
0.5
0.25
0
0 2
-40˚C
25˚C
85˚C
125˚C
TBD
4 6
I
OL
[mA]
8 10 12 14
Figure 31.
Typ. V
DD
- V
OH
@ V
DD
= 5 V (standard ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
-40˚C
25˚C
85˚C
125˚C
2
TBD
4 6
I
OH
[mA]
8 10 12
Electrical characteristics
15441 Rev 3 69/95
Electrical characteristics
Figure 32.
Typ. V
DD
- V
OH
@ V
DD
= 3.3 V (standard ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 1
-40˚C
25˚C
85˚C
125˚C
2
TBD
3
I
OH
[mA]
4 5 6 7
Figure 33.
Typ. V
DD
- V
OH
@ V
DD
= 5 V (high sink ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
-40˚C
25˚C
85˚C
125˚C
5
Alain to send
10
I
OH
[mA]
15 20 25
Figure 34.
Typ. V
DD
- V
OH
@ V
DD
= 3.3 V (high sink ports)
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 2
-40˚C
25˚C
85˚C
125˚C
Alain to send
4 6
I
OH
[mA]
8 10 12 14
STM8S103x
70/95 15441 Rev 3
STM8S103x Electrical characteristics
Subject to general operating conditions for V
DD
and T
A
unless otherwise specified.
Table 42.
NRST pin characteristics
Symbol
V
IL(NRST)
Parameter
NRST Input low level voltage
(1)
Conditions
V
IH(NRST)
NRST Input high level voltage
V
OL(NRST)
R
PU(NRST) t
IFP(NRST) t
INFP(NRST) t
OP(NRST)
NRST Output low level voltage
NRST Pull-up resistor
(2)
NRST Input filtered pulse
(3)
NRST Input not filtered pulse
I
OL
=2 mA
1.
Data based on characterization results, not tested in production.
2.
The R
PU
pull-up equivalent resistor is based on a resistive transistor
3.
Data guaranteed by design, not tested in production.
Min
-0.3 V
0.7 x
V
DD
30
500
20
Typ
40
Max Unit
0.3 x V
DD
V
DD
+
0.3
0.5
60
75
V k
Ω ns ns
µs
Figure 35.
Typical NRST V
IL
and V
IH
vs V
DD
@ 4 temperatures
6
5
4
3
2
1
0
2.5
3 3.5
TBD
4
V
DD
[V]
4.5
5 5.5
-40˚C
25˚C
85˚C
125˚C
6
Figure 36.
Typical NRST pull-up resistance vs V
DD
@ 4 temperatures
60
55
-40˚C
25˚C
85˚C
125˚C
50
45
TBD
40
35
30
2.5
3 3.5
4
V
DD
[V]
4.5
5 5.5
6
15441 Rev 3 71/95
Electrical characteristics
Figure 37.
Typical NRST pull-up current vs V
DD
@ 4 temperatures
STM8S103x
140
120
100
80
60
40
20
0
0
TBD
-40˚C
25˚C
85˚C
125˚C
1 2 3
V
DD
[V]
4 5 6
protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the V
IL
max. level specified in
. Otherwise the reset is not taken into account internally.
Figure 38.
Recommended reset pin protection
V
DD
STM8
R
PU
External reset circuit
(optional)
0.01 µF
NRST
Filter
Internal reset
72/95 15441 Rev 3
STM8S103x Electrical characteristics
10.3.8
SPI serial peripheral interface
Unless otherwise specified, the parameters given in
are derived from tests performed under ambient temperature, f
MASTER
frequency and V
DD
supply voltage conditions. t
MASTER
= 1/f
MASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 43.
SPI characteristics
Symbol Parameter Conditions
(1)
Min Max Unit
1/t f
SCK c(SCK)
SPI clock frequency
Master mode
Slave mode
0
0
8
7
(2)
MHz t r(SCK) t f(SCK) t su(NSS)
(3) t h(NSS)
t t w(SCKH)
w(SCKL)
t t su(MI)
su(SI)
SPI clock rise and fall time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode
Master mode
4 x t t
MASTER
SCK
70
/2 - 15 t
5
SCK
25
/2 +15
Slave mode 5 t t
h(SI) t a(SO)
t dis(SO)
t v(SO)
t
t h(SO)
t
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Master mode
Slave mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
7
10
25
27
11
3 x t
MASTER
30
1.
Parameters are given by selecting 10 MHz I/O output frequency.
2.
Data characterization in progress.
3.
Values based on design simulation and/or characterization results, and not tested in production.
4.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
ns
15441 Rev 3 73/95
74/95
Electrical characteristics
Figure 39.
SPI timing diagram - slave mode and CPHA = 0
NSS input tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1 tw(SCKH) tw(SCKL)
MISO ta(SO)
OUT P UT tsu(SI)
MOSI
I NPUT tc(SCK) tv(SO)
MS B O UT
M SB IN th(SI) th(SO)
BI T6 OUT
B I T1 IN
Figure 40.
SPI timing diagram - slave mode and CPHA = 1
th(NSS) tr(SCK) tf(SCK)
LSB OUT tdis(SO)
LSB IN
NSS input tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 tw(SCKH) tw(SCKL)
MISO
OUT P UT ta(SO) tsu(SI)
MOSI
I NPUT tc(SCK) tv(SO)
MS B O UT th(SI)
M SB IN B I T1 IN th(SO)
BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)
LSB OUT
LSB IN
STM8S103x
ai14134 ai14135
1.
Measurement points are done at CMOS levels: 0.3V
DD
and 0.7 V
DD.
15441 Rev 3
STM8S103x
Figure 41.
SPI timing diagram - master mode
(1)
High
NSS input tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO
INP UT
MOSI
OUTUT tsu(MI) tw(SCKH) tw(SCKL)
MS BIN th(MI)
M SB OUT tv(MO)
1.
Measurement points are done at CMOS levels: 0.3V
DD
and 0.7 V
DD.
BI T6 IN
B I T1 OUT th(MO)
Electrical characteristics
tr(SCK) tf(SCK)
LSB IN
LSB OUT ai14136
15441 Rev 3 75/95
Electrical characteristics STM8S103x
10.3.9 I
2
C interface characteristics
Table 44.
I
2
C characteristics
Symbol Parameter
Standard mode I
2
C Fast mode I
2
C
(1)
Min
(2)
Max
Max
Unit
t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time t h(STA) t su(STA) t su(STO)
START condition hold time
Repeated START condition setup time
STOP condition setup time t w(STO:STA)
STOP to START condition time (bus free)
4.7
4.0
250
0
(3)
4.0
4.7
4.0
4.7
1000
300
1.3
0.6
100
0
(4)
0.6
0.6
0.6
1.3
300
300
µs ns
µs
µs
µs
C b
Capacitive load for each bus line 400
1.
f
MASTER
, must be at least 8 MHz to achieve max fast I
2
C speed (400kHz)
2.
Data based on standard I
2
C protocol requirement, not tested in production
400
3.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low time
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL pF
76/95 15441 Rev 3
STM8S103x Electrical characteristics
Subject to general operating conditions for V
DD
, f
MASTER
, and T
A
unless otherwise specified.
Table 45.
ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
DD
= 2.95 to 5.5 V 1
4
f
ADC
ADC clock frequency MHz
V
DD
= 4.5 to 5.5 V 1
6
V
C
AIN
ADC
Conversion voltage range
(1)
Internal sample and hold capacitor
V
SS
3
V
DD
V pF t
S
Minimum sampling time f
ADC
= 4 MHz f
ADC
= 6 MHz
0.75
0.5
µs t t
STAB
CONV
Wake-up time from standby
Minimum total conversion time
(including sampling time, 10-bit resolution) f f
ADC
ADC
= 4 MHz
= 6 MHz
7
3.5
2.33
µs
µs
µs
14 1/f
ADC
1.
During the sample time the input capacitance C
AIN
(3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t
S.
After the end of the sample time t
S
, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t
S
depend on programming.
15441 Rev 3 77/95
Electrical characteristics STM8S103x
Table 46.
ADC accuracy with R
AIN
< 10 k
Ω , V
DD
= 5 V
Symbol Parameter Conditions Typ Max
(1)
Unit
|E
|E
|E
|E
T
O
G
D
|E
L
|
|
|
|
|
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
(2)
f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 6 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz
1.6
2.2
2.4
1.1
1.5
1.8
1.5
2.1
2.2
0.7
0.7
0.7
0.6
0.8
3.5
4
4.5
2.5
3
3
3
3
4
1.5
1.5
1.5
1.5
2
LSB f
ADC
= 6 MHz 0.8
2
1.
Data characterization in progress.
2.
ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I
ΣI
INJ(PIN)
in
does not affect the ADC accuracy.
INJ(PIN)
and
Table 47.
ADC accuracy with R
AIN
< 10 k
Ω R
AIN
, V
DD
= 3.3 V
Symbol Parameter Conditions Typ
|E
T
|
|E
O
|
|E
G
|
|E
D
|
|E
L
|
Total unadjusted error
Offset error
Integral linearity error
f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz f
ADC
= 2 MHz f
ADC
= 4 MHz
1.6
1.9
1
1.5
1.3
2
0.7
0.7
0.6
0.8
1.
Data characterization in progress.
Max
(1)
3.5
4
2.5
2.5
3
3
1
1.5
1.5
2
Unit
LSB
78/95 15441 Rev 3
STM8S103x Electrical characteristics
Figure 42.
ADC accuracy characteristics
E
G
1023
1022
1021
1LSB
IDEAL
=
V
DDA
– V
1024
7
6
5
4
3
2
1
E
O
E
T
1 LSB
E
L
IDEAL
0
V
SSA
1 2 3 4 5 6 7
(2)
E
D
(3)
(1)
1021102210231024
V
DD
1.
Example of an actual transfer curve.
2.
The ideal transfer curve
3.
End point correlation line
E
T
= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
E
E
E
O
G
D
E
L
= Offset error: deviation between the first actual transition and the first ideal one.
= Gain error: deviation between the last ideal transition and the last actual one.
= Differential linearity error: maximum deviation between actual steps and the ideal one.
= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.
Figure 43.
Typical application with ADC
V
DD
V
T
0.6V
STM8
R
AIN AINx
V
AIN
10-bit A/D conversion
C
AIN
V
T
0.6V
I
L
¬
C
ADC
15441 Rev 3 79/95
Electrical characteristics STM8S103x
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
● FTB: A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 48.
EMS data
Symbol Parameter
V
FESD
V
EFTB
Conditions
Voltage limits to be applied on any I/O pin to induce a functional disturbance
V
DD
= 3.3 V, T f
MASTER
A
= 25 °C,
= 16 MHz (HSI clock), conforming to IEC 1000-4-2
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V
SS pins to induce a functional disturbance
V
DD
= 3.3 V, T f
MASTER
A
= 25 °C ,
= 16 MHz (HSI clock), conforming to IEC 1000-4-4
Level/class
2/B
4/A
80/95 15441 Rev 3
STM8S103x Electrical characteristics
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 49.
EMI data
Conditions
Symbol Parameter
General conditions
Monitored frequency band
S
EMI
Peak level
SAE EMI level
V
T
DD
A
= 5 V
= 25 °C
LQFP32 package
Conforming to SAE J 1752/3
0.1MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI level
1.
Data based on characterization results, not tested in production.
Max f
HSE
/f
CPU
(1)
16 MHz/
8 MHz
16 MHz/
16 MHz
2
10
5
2.5
3
10
7
2.5
Unit
dBµV
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU, and DLU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 50.
ESD absolute maximum ratings
Symbol Ratings Conditions Class
Maximum value
(1)
Unit
V
V
ESD(HBM)
ESD(CDM)
Electrostatic discharge voltage
(Human body model)
Electrostatic discharge voltage
(Charge device model)
T
A
= 25°C, conforming to
JESD22-A114
T
A
LQFP32 package
=
25°C, conforming to
SD22-C101
1.
Data based on characterization results, not tested in production
A
IV
4000
1000
V
15441 Rev 3 81/95
Electrical characteristics STM8S103x
Static latch-up
●
●
Two complementary static tests are required on 10 parts to assess the latch-up performance:
A supply overvoltage (applied to each power supply pin)
A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Table 51.
Electrical sensitivities
Symbol Parameter Conditions Class
(1)
LU Static latch-up class
T
A
= 25 °C
T
A
= 85 °C
T
A
= 125 °C
A
A
A
1.
Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).
82/95 15441 Rev 3
STM8S103x Package characteristics
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at
www.st.com
.
ECOPACK
®
is an ST trademark.
15441 Rev 3 83/95
Package characteristics
11.1 Package mechanical data
11.1.1 LQFP package mechanical data
Figure 44.
32-pin low profile quad flat package (7 x 7)
ccc C
D
D1
D3
A
A2
24 17
16
25 b
E3
E1 E
32
Pin 1 identification
1 8
9 c
A1
L1
STM8S103x
L
K
Table 52.
32-pin low profile quad flat package mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ
A
A1 0.050
1.600
0.150 0.0020
5V_ME
Max
0.0630
0.0059 b 0.300 0.370 0.450 0.0118 0.0177 c 0.090 0.200 0.0035 0.0079
D3 5.600 0.2205
84/95
E3 5.600 0.2205 e 0.800 0.0315
L 0.450 0.600 0.750 0.0177 0.0295
L1 1.000 0.0394
0.0039 ccc 0.100
1.
Values in inches are converted from mm and rounded to 4 decimal digits
15441 Rev 3
STM8S103x Package characteristics
11.1.2 VFQFPN package mechanical data
Figure 45.
32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C ddd C
A
A3
A1
D
9 e
16
8
17
E2 b E
1
24
L
32
Pin # 1 ID
R = 0.30
D2
Bottom view
L
42_ME
Table 53.
32-lead very thin fine pitch quad flat no-lead package mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ Max
D
D2
E
E2
A
A1
A3 b
0.80
0
0.18
4.85
3.20
4.85
3.20
0.90
0.02
0.20
0.25
5.00
3.45
5.00
3.45
1.00
0.05
0.30
5.15
3.70
5.15
3.70
0.0315
0.0071
0.1909
0.1260
0.1909
0.1260
e
L 0.30
0.50
0.40
0.50
0.0118
ddd 0.08
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
0.0354
0.0008
0.0079
0.0098
0.1969
0.1969
0.1358
0.0197
0.0157
0.0394
0.0020
0.0118
0.2028
0.1457
0.2028
0.1457
0.0197
0.0031
15441 Rev 3 85/95
Package characteristics
11.1.3 TSSOP package mechanical data
Figure 46.
20-pin, 4.40 mm body, 0.65 mm pitch
D
STM8S103x
20 11 c
E1 E
1 10 k aaa
CP
A A2
A1
L1
L b e
YA_ME
Table 54.
20-pin, 4.40 mm body, 0.65 mm pitch mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ
A 1.200
Max
0.0472
86/95 e 0.650 0.0256
L 0.450 0.600 0.750 0.0177 0.0295
L1 1.000 0.0394 aaa 0.100
1.
Values in inches are converted from mm and rounded to 4 decimal digits
0.0039
15441 Rev 3
STM8S103x Package characteristics
11.1.4 UFQFPN package mechanical data
Figure 47.
20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)
L4 b
5
1
20
L3
D e
10
11
L1 e
L2
E
15
16
A3
A1
A ddd
103_A0A5_ME
1.
Drawing is not to scale
Table 55.
20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
mechanical data mm inches
(1)
Dim.
Min Typ Max Min Typ Max
A3 e
L1
L2
D
E
A
A1
L3
L4 b ddd
0.500
0.000
0.500
0.300
0.180
0.050
3.000
3.000
0.550
0.020
0.152
0.500
0.550
0.350
0.150
0.200
0.250
0.600
0.050
0.600
0.400
0.300
0.0197
0.0000
0.0197
0.0118
0.0071
0.0020
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
0.1181
0.1181
0.0217
0.0008
0.0060
0.0197
0.0217
0.0138
0.0059
0.0079
0.0098
0.0236
0.0020
0.0236
0.0157
0.0118
15441 Rev 3 87/95
Package characteristics
Figure 48.
Recommended footprint for on-board emulation
0.5mm
0.8mm
[0.032"]
4mm
[0.157"]
0.5mm
1.65mm [0.065"]
0.3mm [0.012"]
4mm [0.157"]
0.9mm
[0.035"]
ai15319
Bottom view
1.
Drawing is not to scale
Figure 49.
Recommended footprint without on-board emulation
STM8S103x
88/95
1.
Drawing is not to scale
2.
Dimensions are in millimeters
15441 Rev 3
STM8S103x Package characteristics
The maximum chip junction temperature (T
Jmax
) must never exceed the values given in
Table 19: General operating conditions on page 49
The maximum chip-junction temperature, T
Jmax
, in degrees Celsius, may be calculated using the following equation:
T
Jmax
= T
Amax
+ (P
Dmax
x
Θ
JA
)
Where:
●
●
T
Amax
is the maximum ambient temperature in
° C
Θ
JA
is the package junction-to-ambient thermal resistance in
° C/W
●
●
P
Dmax
is the sum of P
INTmax
and P
I/Omax
(PDmax = P
INTmax
+ P
I/Omax
)
P
INTmax
is the product of I
DD and V
DD
, expressed in Watts. This is the maximum chip internal power.
●
P
I/Omax
represents the maximum power dissipation on output pins
Where:
P
I/Omax
=
Σ (V
OL
*I
OL
) +
Σ((V
DD
-V
OH)
*I
OH
), taking into account the actual V
OL
/I
OL and
V
OH
/I
OH the application.
of the I/Os at low and high level in
Table 56.
Thermal characteristics
(1)
Symbol Parameter Value
Θ
Θ
JA
JA3
Θ
Θ
JA
JA
Thermal resistance junction-ambient
LQFP32 - 7 x 7 mm
Thermal resistance junction-ambient
VFQFPN32 - 5 x 5 mm
Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
Thermal resistance junction-ambient
UFQFPN20 - 3 x 3 mm
60
22
84
90
1.
Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
Unit
°C/W
°C/W
°C/W
°C/W
JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.
15441 Rev 3 89/95
Package characteristics STM8S103x
11.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Section 12: Ordering information on page 91
The following example shows how to calculate the temperature range needed for a given application.
Assuming the following application conditions:
●
●
●
Maximum ambient temperature T
I
DDmax
= 8 mA, V
DD
= 5 V
Amax
= 75 °C (measured according to JESD51-2)
Maximum 20 I/Os used at the same time in output at low level with
I
OL
= 8 mA, V
OL
= 0.4 V
P
INTmax =
8 mA x 5 V = 400 mW
P
IOmax = 20
x 8 mA x 0.4 V = 64 mW
This gives: P
INTmax
= 400 mW and P
IOmax
64 mW:
P
Dmax =
400
mW +
64 mW
Thus: P
Dmax
= 464 mW
Using the values obtained in
Table 56: Thermal characteristics on page 89
, T
Jmax
is calculated as follows for LQFP32 59°C/W:
T
Jmax
= 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
This is within the range of the suffix 6 version parts (-40 < T
J
< 105° C).
In this case, parts must be ordered at least with the temperature range suffix 6.
90/95 15441 Rev 3
STM8S103x Ordering information
Figure 50.
STM8S103x access line ordering information scheme
Example:
STM8 S 103 K 3 T 6 C TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
103 = Access line 103 sub-family
Pin count
K = 32 pins
F = 20 pins
Program memory size
3 = 8 Kbytes
2 = 4 Kbytes
Package type
P = TSSOP
T = LQFP
U = VFQFPN or UFQFPN
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm
B = 0.65 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1.
For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to
www.st.com
or contact the ST Sales Office nearest to you.
15441 Rev 3 91/95
STM8 development tools
13 STM8 development tools
STM8S103x
Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
13.1 Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module
(SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.
STice key features
●
●
●
●
●
●
●
●
●
●
●
Occurrence and time profiling and code coverage (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on the fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
92/95 15441 Rev 3
STM8S103x STM8 development tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code.
STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes:
●
●
●
●
●
●
ST Visual Develop – Full-featured integrated development environment from ST, featuring
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.
13.2.2 C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface.
Available toolchains include:
●
Cosmic C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
● Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
●
STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code.
During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
15441 Rev 3 93/95
94/95
Revision history STM8S103x
Table 57.
Document revision history
Date Revision
02-Mar-2009
10-Apr-2009
10-Jun-2009
1
2
3
Changes
Initial revision
Added
Updated
Section 4.8: Auto wakeup counter on page 17
.
Modified description of PB4 and PB5 (removed X in PP column) and
added footnote concerning HS I/Os in
.
Removed TIM3 and UART from
Updated VCAP specifications in
.
Table 37: Flash program memory/data
Updated
Section 10: Electrical characteristics
Updated
Table 56: Thermal characteristics
.
Document status changed from “preliminary data” to “datasheet”.
Replaced WFQFPN20 package with UFQFPN package.
Replaced ‘VFQFN’ with ‘VFQFPN’.
Added bullet point on the unique identifier to
Updated
Section 4.8: Auto wakeup counter on page 17
.
Updated wpu and PP status of PB5/12C_SDA and PB4/12C_SCL pins in
Removed
Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices .
Updated
Updated reset status of port D CR1 register in
Updated alternate function remapping descriptions in
and
.
Added
.
Updated
Table 19: General operating conditions
Figure 19: Typical HSI accuracy at VDD = 5 V vs 5 temperatures
.
Updated
and added TBD data.
in the
.
Updated
Section 10.3.11: EMC characteristics
15441 Rev 3
STM8S103x
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15441 Rev 3 95/95
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