Graphics system interface

Graphics system interface
US006411301B1
(12)
(54)
(75)
United States Patent
(10) Patent N0.:
Parikh et al.
(45) Date of Patent:
GRAPHICS SYSTEM INTERFACE
Inventors: Vimal Parikh, Santa Clara, CA (US);
Robert Moore, Heathrow, FL (Us);
Howard Cheng, Sammamish, WA (Us)
US 6,411,301 B1
Jun. 25, 2002
5,392,393 A
2/1995 Deering
5,404,445 A
4/1995 Matsumoto
5,421,028 A
5,432,900 A
5,438,663 A
5/1995 Swanson
7/1995 Rhodes et al.
8/1995 Matsumoto et al.
(L'15t Con t'mue d on neX t page).
(73) Assignee: Nintendo Co., Ltd., Kyoto (JP)
FOREIGN PATENT DOCUMENTS
(*)
Notice:
Subject to any disclaimer, the term of this
patent
U.S.C. is154(b)
extended
by 0 or
days.
adjusted under 35
(21) Appl. No.: 09/886,034
(22) Filed:
Jun. 22, 2001
EP
1 075 146
EP
1 081 649
3/2001
JP
JP
9_33_23O
11053580
12/1997
2/1999
11076614
3/1999
JP
Related US. Application Data
(63)
20001
(List Continued on next page‘)
Continuation of application No. 09/723,336, ?led on Nov.
OTHER PUBLICATIONS
28,2000.
_
(60)
Provisional application N0. 60/161,915, ?led On oct. 28,
1999-
(51)
Int. Cl.7 ........................ .. G06F 15/16; G06T 15/10
Photograph of Sony PlayStanon II System.
Photograph of Sega Dreamcast System.
Photograph of Nintendo 64 System.
Whitepaper: 3D Graphics Demysti?ed, Nov. 11, 1999,
(52)
US. Cl. ..................... .. 345/522; 345/427; 345/567;
WWW.nvidia.com.
Whitepaper: “Z
709/328; 712/208
(58)
Field of Search ............................... .. 345/427, 501,
345/503, 520, 522, 559, 565, 567; 709/328;
712/208
(56)
1/1984 Sherman
2/1986 Yan et al.
More
a.com.
Primary Examiner—Ulka J. Chauhan
(74) Attorney, Agent, or Firm—Nixon & Vanderhye P.C.
6/1983 Sherman
4,425,559 A
and
(List continued on next page.)
US. PATENT DOCUMENTS
4,570,233 A
Interpolation
Whitepaper: Using GLiNVivertexiarray and GLiNVi
fence, posted Aug. 1, 2000, WWW.nvidia.com.
References Cited
4,388,620 A
Buffering,
W—Buffering”, Doug Rogers, Jan. 31, 2000, WWW.nvidi
(57)
ABSTRACT
4,658,247 A
4/1987 Gharachorloo
An interface for a graphics system includes simple yet
4,725,831 A
4,829,295 A
2/1988 Coleman
5/ 1989 HiTPYuki
powerful constructs that are easy for an application pro
grammer to use and learn. Features include a unique vertex
4,862,392 A
8/1989 Stem“
representation alloWing the graphics pipeline to retain vertex
2
g°nZ_a1eZ'L°peZ et a1‘
state information and to mix indexed and direct vertex
4’914’729 A
4/199O oifilrrilget a1
values and attributes; a projection matrix value set com
4’945’500 A
5:136j664 A
7/199O Deming '
8/1992 Bersack et a1_
mand; a display list call object command; and an embedded
frame buffer clear/set command.
5,170,468 A
12/1992 Shah 6161.
5,392,385 A
2/1995 Evangelisti et al.
4 Claims, 21 Drawing Sheets
1 14
Memnry
0x FIFO
M
Fm‘
f
Gk set Pmieellon ()
FlFO
|E
Ulsplay use
&
1t DliS
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21 hliS
Vertex Arrays
y
20.....1615.
_
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,
.
,
.
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.
.
.
.
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.
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.
address in XF (EglS1ElS
N+l (0:>1,Ux?=> 1a)
32 bl! words wllllclluw.
In \l'llS specllic example lllc pmiection matrlx
IS @ address OxtUZO and 7 32-bit words
Wlll lalluw.
Hence,
Texture
EXAMPLE GRAPHICS PROCESSOR FLOW
32-bits
value
value
value
value
value
Pro] A
Proi e
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Pml F
Pro] G
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US 6,411,301 B1
Page 2
U.S. PATENT DOCUMENTS
5,457,775
5,504,917
5,594,854
5,608,424
5,687,357
5,701,444
5,721,947
5,727,192
5,751,295
5,758,182
5,764,243
5,768,626
5,768,629
5,774,133
5,777,629
5,798,770
5,801,706
5,801,716
5,805,868
5,815,166
5,821,949
5,870,587
5,874,969
5,917,496
5,920,326
5,920,876
5,936,641
5,940,086
5,949,424
5,949,440
5,969,726
5,995,121
5,999,196
6,002,409
6,023,738
6,025,853
6,028,611
6,037,949
6,052,133
6,057,852
6,057,863
6,092,124
6,151,602
6,173,367
6,177,944
6,181,352
6,192,384
6,198,488
6,226,012
6,243,732
6,247,113
10/1995
4/1996
1/1997
3/1997
11/1997
12/1997
2/1998
3/1998
5/1998
5/1998
6/1998
6/1998
6/1998
6/1998
7/1998
8/1998
9/1998
9/1998
9/1998
9/1998
10/1998
2/1999
2/1999
6/1999
7/1999
7/1999
8/1999
8/1999
9/1999
9/1999
10/1999
11/1999
12/1999
12/1999
2/2000
2/2000
2/2000
3/2000
4/2000
5/2000
5/2000
7/2000
11/2000
Johnson, Jr. et al.
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Priem
Baldwin
Priem et al.
Baldwin
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Wise et al.
Neave et al.
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3, 2000, www.nvidia.corn.
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2000, www.nvidia.corn.
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www.nvidia.corn.
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Fujita et al.
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Technical Brief: Transform and Lighting, Nov. 10, 1999,
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Murphy
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B1
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B1
1/2001 Aleksic et al.
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B1 *
B1 *
2/2001 Dally et al. .......... ..
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B1
5/2001 Priem et al.
B1 *
B1 *
6/2001 Arakawa et al. ..
6/2001 Jaggar ................ .. .... ..
11161819
11203500
11226257
11259671
11259678
2000-66985
2000-92390
2000-132704
2000-132706
2000-149053
2000-156875
2000-182077
2000-207582
2000-215325
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Baldwin
Baldwin
FOREIGN PATENT DOCUMENTS
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
W0
OTHER PUBLICATIONS
6/1999
7/1999
8/1999
9/1999
9/1999
3/2000
3/2000
5/2000
5/2000
5/2000
6/2000
6/2000
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8/2000
4/ 1994
Enthusiast
Enthusiast
Enthusiast
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Mar. 19, 1999.
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Oct. 20, 1999.
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708/200
345/418
29, 1999.
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708/501
@1999.
712/200
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into Wholly—Owned Subsidiaries”, Mar. 9, 1999.
AM News: Japanese Developers Not All Sold on PS2, Next
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Sony To Turn PlayStation Maker Into Wholly Owned
Unit—Nikkei, Dow Jones News Service, Mar. 8, 1999.
Yumiko Ono, Sony Antes Up Its Chips In Bet On Game
System, Dow Jones News Service, Mar. 4, 1999.
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ference, Feb. 16, 1999.
US 6,411,301 B1
Page 3
Dreamcast Instruction Manual, Sega Enterprises, Ltd.,
Technical Presentation: Per—Pixel Lighting (by S. Dietrich)
©1998.
“Sega To Launch Video Camera for Dreamcast”, Reuters
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Technical Presentation: GeForce 256 and RIVA TNT Com
Business NeWs, Feb. 16, 2000.
David PescovitZ, “Dream On”, Wired, Aug. 1999.
Randy Nelson, “Dreamcast 101: Everything You Ever
Wanted To KnoW About Sega’s Powerful NeW Console”,
Of?cial Sega Dreamcast MagaZine, Jun. 1999.
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biners, Dec. 8, 1999, WWW.nvidia.com.
1998.
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David Sheff, “Sony Smackage: Test Driving The PlayStation
II”, Wired, Nov. 1999.
Introducing The Next Generation PlayStation, Sony Com
nputer Entertainment Inc., ©1999.
Leadtek GTS, Aug. 3, 2000, WWW.hexus.net.
Technical Presentation: Vertex Cache Optimization, Nov.
12, 1999, WWW.nvidia.com.
Technical Presentation: Vertex Blending, Nov. 12, 1999,
WWW.nvidia.com.
Technical Presentation: HardWare Transform and Lighting,
Nov. 12, 1999, WWW.nvidia.com.
Technical Presentation: GeForce 256 OvervieW, Nov. 12,
1999, WWW.nvidia.com.
Technical Presentation: DirectX 7 and Texture Management,
Nov. 12, 1999 WWW.nvidia.com.
Technical Presentation: Dot Product Lighting, Nov. 12,
1999, WWW.nvidia.com.
Technical Presentation: Texture Coordinate Generation,
Nov. 3, 1999, WWW.nvidia.com.
us.net.
Technical Presentation: Phong Shading and Lightmaps, Nov.
3, 1999, WWW.nvidia.com.
Technical Presentation: The ARBimultitexture Extension,
Microsoft Xbox—The Future of Gaming, Microsoft Xbox
Performance Sheet, WWW.xbox.com.
Nov. 3, 1999 WWW.nvidia.com.
Technical Presentation: Multitexture Combiners, Nov. 3,
Robert L. Cook, “Shade Trees”, Computer Graphics, vol. 18,
1999, WWW.nvidia.com.
Technical Presentation: Emboss Bump Mapping, Nov. 3,
1999, WWW.nvidia.com.
Technical Presentation: HardWare Accelerated Anisotropic
Lighting, Nov. 3, 1999 WWW.nvidia.com.
Technical Presentation: Guard Band Clipping, Nov. 3, 1999,
Voodoo 5 5500 RevieW, Ju. 26, 2000, WWW.hexus.net.
ATI Radeon 64 Meg DDR OEM, Aug., 19, 2000, WWW.hex
No. 3, Jul. 1984.
Wang et al., “Second—Depth ShadoW Mapping”, Depart
ment of Computer Science, Univ. N.C, Chapel Hill, NC. pp.
1—7.
Peercy et al., “Ef?cient Bump Mapping HardWare”, Com
puter Graphics Proceedings, Annual Conference Series,
1997
Gustavo Oliveira, “Refractive Texture Mappig, Part One”,
WWW.gamasutr.com, Nov., 10, 2000.
WWW.nvidia.com.
The RenderMan Interface, Stephan R. Keith, version 3.1,
Pixar Animation Studios, Sep. 1989.
The RenderMan Interface, Version 3.2, Pixar Animation
John Schlag, Fast Embossing Effects on Raster Image Data,
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Science Department, Carnegie Mellon University, Academic
Press, Inc., 1994,pp. 433—437.
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James F. Blinn, “Simulationof Wrinkled Surfaces,” Caltech/
JPL, pp. 286—292, SIGGRAPH 78 (1978)
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Peters, Ltd., @1999, pp. 127—142.
Technical Presentation: Vertex Buffers, posted Jun. 12,
2000, WWW.nvidia.com.
Technical Presentation: HardWare Transform and Lighting,
RevieW, Sega, 2/99, WWW.game—revolution.com.
Corporation, Aug. 21, 2000, WWW.nvidia.com.
Duke, “Dreamcast Technical Specs”, Sega Dreamcast
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2000, WWW.g256.com.
WWW.nvidia.com, posted Jun. 12, 2000.
“Dreamcast: The Full Story”, Next Generation, Sep. 1998.
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tion, 1995—1999 (as part of the DirectX 7.0 SDK in the
Companion CD included With “Inside Direct3D”, Microsoft
Programming Series, Peter J. Kovach, Microsoft Press,
Technical Presentation: HardWare Bump—mapping Choices
and Concepts, Jun. 7, 2000, WWW.nvidia.com.
“Inside Direct3D”, Microsoft Programming Series, Peter J.
Technical Presentation: HoW to Bump Map a Skinned
Polygonal Model, Jun. 7, 2000, WWW.nvidia.com.
Technical Presentation: Computations for HardWare Light
ing and Shading, Mar. 17, 2000, WWW.nvidia.com.
Technical Presentation: Practical Bump—mapping for
Today’s GPUs, Mar. 17, 2000 WWW.nvidia.com.
Technical Presentation: ShadoWs, Transparency, & Fog,
Mar. 17, 2000 WWW.nvidia.com.
Technical Presentation: GeForce 256 Register Combiners,
Mar. 17, 2000,WWW.nvidia.com.
Technical Presentation: TexGen & The Texture Matrix, Mar.
15, 2000 WWW.nvidia.com.
Technical Presentation: Toon Shading, Mar. 15, 2000,
1999 .
Kovach, Microsoft Press, 1999.
“OpenGL Programming Guide, The Of?cial Guide to Learn
ing OpenGL, Release 1”, Jackie Nieder, Tom David, Mason
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“Procedural Elements for Computer Graphics,” Second Edi
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“Real—Time Rendering,” Tomas Molleir, Eric Haines, AK
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tion, The Systems Programming Series, Foley, van Dam,
Fiener, Hughes, Addison Wesley, 1990.
“Principles of Three—Dimensional Computer Animation”,
Revised Edition, Michael O’Rourke, W.W. Norton & Com
WWW.nvidia.com.
Technical Presentation: D3D 7 Vertex Lighting, Mar. 15,
pany, 1998.
2000, WWW.nvidia.com.
* cited by examiner
U.S. Patent
Jun. 25,2002
615’
\HI
(
Sheet 1 0121
US 6,411,301 B1
50
U.S. Patent
Jun. 25, 2002
US 6,411,301 B1
Sheet 6 0f 21
610
BOOT SYSTEM
7/
II
INITIALIZE OPERATING SYSTEM (05)
AND GRAPHICS SYSTEM (ex)
"
612
M
614
__,/
———>
SETUP GAME LOGIC
v
Bi
SETUP GRAPHICS (ex) STATE
"
PROVIDE VERTEX INFORMATION
616
"/
618
"/
v
FRAME LOOP
COPY FRAME FROM EMBEDDED
J20
FRAME BUFFER TO MAIN MEMORY
(GX COPY DISP (I)
V
DISPLAY FRAME
Flg- 6
EXAMPLE GRAPHICS
PROCESSING LOOP
J22
U.S. Patent
Jun. 25,2002
Sheet 7 0f 21
INITIALIZE 05 AND ex
US 6,411,301 B1
612
GXINIT ()
IT
GAME LOGIC
6,4
VERTEX ARRAYS —-/
DISPLAY LISTS
)
TEXTURE MATERIALS
TEXTURES
POSITION AND NORMAL MATRICES
"
616
ex STATE
COMMAND PROCESSING
62¢
GXSetVtxDesc ()
BLEND
COLOR CHANNELS
AND LIGHTING
TRANSFORM
GXSetVMA?rFmI I)
Z COMPARE
_/
CLIPPING AND CULLING
TEXTURE ENVIRONMENT
BUMP
FOG
INDIRECT TEXTURE
V
618
._/
VERTEX INFORMATION
GXBegin () —-—>VERTEX ATTRIBUTES ———> GXEnd ()
FRAME LOOP
EX COPY
620
-—"/
GXCopyDisp ()
EXAMPLE MORE DETAILED GRAPHIC
Fig. 7
PROCESSING LOOP
U.S. Patent
Jun. 25,2002
Sheet 8 of 21
0 initiaiize
GXInit( )
/
US 6,411,301 B1
1002
V
' Define and Align Vertex Arrays
' Define Projection and View Matrices
/ 1004
GXSetProjection ()
I
' Initialize Vertex Attribute Format
GXClearVtxDesc( )
GXSetVtxDesc( )
GXSetVtxAttrFmt( )
/
1006
0 Set array pointers and strides for
the indexed data
GXSetArray()
0 Set lighting, Texgen and TEV
GXSetNumchans( )
GXSetNumTexGens( )
GXSetTev0rder( )
GXSetTev0p( )
I
a
0 Create Vertex Format
GXPosition1x8 (v)
GXCoIor1x8(c)
. Draw model(Quads)
GXBegin()
Vertex Attributes
GXEnd( )
EXAMPLE SIMPLE GRAPHIC
APPLICATION
Fig. 8
1008
U.S. Patent
Jun. 25,2002
Sheet 9 0f 21
US 6,411,301 B1
EXAMPLE GX SET COPY CLEAR (BLACK,0XO0FFFFFF)Z
f
Alpha/red
61
(CP_CMD__SU_BYPASS)
4F
PAD ALPHA
61
(CP_CMD_SU_BYPASS)
50
PAD
copy clear
command
RED
(PE_COPY_CLEAR_AR)
\
r
Green/Blue
copy clear
*
command
GREEN
BLUE
(PE_COPY_CLEAR_GB)
k
f
Z
copy clear
Command
61
(CP_CMD_SU_BYPASS)
{
51
2 (24-bit)
(PE_COPY_CLEAR_Z)
U.S. Patent
Jun. 25, 2002
Sheet 12 0f 21
US 6,411,301 B1
l
CP_CMD_LOADREG
ARRAY_BASE
POS
NRM
CLRO
CLR1
TEX 0
‘TEX 7
general purpose
6 bits
26 b'ts
I
Address to array in memory
El
EX] ARRAY_STRIDE
POS
NRM
CLRO
CLR1
TEX 0
Ex 7
general purpose
HE
lcoIC-?Qm"’lbIwOméDcj
bits
8 bits
m
Stride for array
Fig_ 1 1 ex SET ARRAY ( ex me, me, VOID + BASE APTR, .8 STRIDE)
U.S. Patent
Jun. 25,2002
Sheet 13 0f 21
US 6,411,301 B1
1E1 -
@ CP_VCD_LO
15-13115
17-bitS
bits (615141312111098765432171
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F15141B12|11109
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4.32710|
slot
20
19
18 1716151413
Fig. 12
ex SETVTXATTR ATTR
U.S. Patent
Jun. 25,2002
Sheet 14 0f 21
US 6,411,301 B1
GX SET \rrx ATTR FMT( );
® 1'
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|
U.S. Patent
08
90
Jun. 25, 2002
US 6,411,301 B1
Sheet 15 0f 21
ll
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14
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23
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31
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.
Tex7 Coord
Fig. 138
Tex 4 Coord
U.S. Patent
GX L%EWRX01234567
Jun. 25,2002
Sheet 16 0f 21
US 6,411,301 B1
,m m aV .& Z e
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nm mmamumm9Se
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v.
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v_
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Fig. 1 4 (VERTEX ATTRIBUTE FORMAT TABLE)
2
1
1
U.S. Patent
Jun. 25,2002
Sheet 17 0f 21
US 6,411,301 B1
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