SIS3350 500 MHz 12-bit VME Digitizer User Manual

SIS3350 500 MHz 12-bit VME Digitizer User Manual
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
SIS3350
500 MHz 12-bit
VME Digitizer
User Manual
SIS GmbH
Harksheider Str. 102A
22399 Hamburg
Germany
Phone: ++49 (0) 40 60 87 305 0
Fax:
++49 (0) 40 60 87 305 20
email: [email protected]
http://www.struck.de
Version: sis3350-M-0101-1-v102 as of 28.01.2009
Page 1 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Revision Table:
Revision
0.00TH
0.01
0.02
0.03
0.04
0.05
0.06
1.00
1.01
1.02
Page 2 of 79
Date
27.04.07
24.09.07
26.10.07
28.10.07
29.10.07
30.10.07
26.11.07
04.09.08
29.09.08
28.01.09
Modification
Generation
Power Consumption
Front panel, silk, DAC registers
VGA Gain registers, update frequency synthesizer register
On Board
JP80 Vision drawing
Temporary release
Initial release for 0x0101 firmware
Bug fix in ring/DDR memory diagram, gate chaining diagram
N Divider frequency range setting table
ADC DAC Data register explanation
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
- Table of contents
1
Table of contents..............................................................................................................3
Introduction .....................................................................................................................5
1.1
2
Related documents............................................................................................................................. 5
Technical Properties/Features...........................................................................................6
2.1
Key functionality............................................................................................................................... 6
2.2
Module design................................................................................................................................... 7
2.2.1
Dual channel group .................................................................................................................... 8
2.2.2
Memory philosophy ................................................................................................................... 8
2.2.3
Internal memory handling .......................................................................................................... 9
2.3
Modes of Operation ......................................................................................................................... 10
2.3.1
Ring buffer asynchronous Mode............................................................................................... 10
2.3.2
Ring buffer synchronous Mode................................................................................................. 11
2.3.3
Direct Memory Gate asynchronous Mode................................................................................. 11
2.3.4
Direct Memory Gate synchronous Mode................................................................................... 12
2.3.5
Direct Memory Stop Mode....................................................................................................... 13
2.3.6
Direct Memory Start Mode....................................................................................................... 13
2.4
Clock sources .................................................................................................................................. 14
2.4.1
Internal clock ........................................................................................................................... 14
2.4.2
External clock (BNC analog or LVDS)..................................................................................... 14
2.5
Trigger control (pre/post, start/stop and gate mode) .......................................................................... 14
2.6
Internal Trigger generation............................................................................................................... 14
2.7
VME Interrupts ............................................................................................................................... 15
3
VME Addressing ...........................................................................................................16
3.1
4
Address Map ................................................................................................................................... 17
Register Description.......................................................................................................20
4.1
Control/Status Register(0x0, write/read)........................................................................................... 20
4.2
Module Id. and Firmware Revision Register (0x4, read) ................................................................... 22
4.2.1
Major revision numbers............................................................................................................ 22
4.3
Interrupt configuration register (0x8) ............................................................................................... 23
4.3.1
IRQ mode ................................................................................................................................ 23
4.4
Interrupt control register (0xC)......................................................................................................... 24
4.5
Acquisition control register (0x10, read/write).................................................................................. 25
4.6
Direct Memory Trigger Delay register (0x14, read/write) ................................................................. 27
4.7
Direct Memory Start Mode Sample Length register (0x18, read/write).............................................. 27
4.8
Frequency Synthesizer register (0x1C, read/write)............................................................................ 27
4.9
MultiEvent Max Nof Events register (0x20, read/write).................................................................... 29
4.10 MultiEvent Event_Counter (0x24, read).......................................................................................... 29
4.11 Gate Synch Mode Event Length Limit register (0x28, read/write)..................................................... 30
4.12 Gate Synch Mode Event Length Extend register (0x2C, read/write).................................................. 30
4.13 CBLT/Broadcast setup register ........................................................................................................ 31
4.14 ADC Memory Page register............................................................................................................. 33
4.15 Trigger Output Select register 0x38.................................................................................................. 35
4.16 External Clock/Trigger Input DAC Control Registers....................................................................... 36
4.16.1 Clock/Trigger DAC Control/Status register (0x50 read/write) ................................................... 36
4.16.2 Clock/Trigger DAC Data register (0x 54 read/write)................................................................ 37
4.16.3 DAC load sequence.................................................................................................................. 38
4.16.4 XILINX JTAG_TEST register.................................................................................................. 39
4.16.5 XILINX JTAG_DATA_IN register .......................................................................................... 39
4.16.6 XILINX JTAG_CONTROL register......................................................................................... 39
4.17 Temperature register (0x70, read/only)............................................................................................. 40
4.18 ADC Serial Interface (SPI) register (0x74, read/write)...................................................................... 41
4.19 Key address general reset (0x400 write only) ................................................................................... 42
4.20 Key address VME arm sampling logic (0x410 write only) ................................................................ 42
4.21 Key address VME disarm sampling logic (0x414 write only)............................................................ 42
4.22 Key address VME Trigger ............................................................................................................... 42
4.23 Key address VME Timestamp Clear ................................................................................................ 42
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SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.24 Event configuration registers(0x01000000, 0x02000000, 0x03000000 read/write) ............................ 43
4.25 Direct Memory Stop Mode Sample Wrap Length register................................................................. 44
4.26 Sample Start address register ........................................................................................................... 45
4.27 ADC Next Sample address register .................................................................................................. 46
4.28 Ringbuffer Sample Length register................................................................................................... 47
4.29 Ringbuffer Pre Delay register........................................................................................................... 48
4.30 End Address Threshold registers...................................................................................................... 48
4.31 Trigger setup register registers (0x02000030, 0x02000038, 0x03000030, 0x03000038) .................... 49
4.32 Threshold registers (0x02000034, 0x0200003C, 0x03000034, 0x0300003C) .................................... 50
4.32.1 Threshold Trigger .................................................................................................................... 50
4.32.2 Threshold FIR Trigger.............................................................................................................. 51
4.32.3 Threshold Gate......................................................................................................................... 52
4.33 ADC Input tap delay registers (0x2000030, 0x2000034, 0x3000030 0x3000034).............................. 52
4.34 VGA/gain registers (0x2000048, 0x200004C, 0x3000048 0x300004C) ............................................ 53
4.35 ADC DAC Control Registers ........................................................................................................... 54
4.35.1 ADC DAC Control/Status registers (0x0x2000050, 0x0x3000050 read/write) ........................... 54
4.35.2 ADC DAC Data registers (0x0x2000054, 0x0x3000054 read/write).......................................... 55
4.35.3 ADC Sample Counter TN setup register (0x2000070, 0x2000074, 0x20000078, 0x200007C,
0x3000070, 0x3000074, 0x30000078, 0x300007C read/write) ................................................................. 56
4.36 ADC memory .................................................................................................................................. 57
4.36.1 Event Data format 1: ................................................................................................................ 57
4.36.2 Event Data format 2: ................................................................................................................ 58
4.36.3 Extra Header............................................................................................................................ 59
5
6
Board layout ..................................................................................................................60
Front panel.....................................................................................................................61
6.1
Control In/Outputs........................................................................................................................... 62
6.1.1
Trigger (Gate) Lemo input........................................................................................................ 62
6.1.2
Trigger (Gate) Lemo output...................................................................................................... 62
6.1.3
Clock BNC input ..................................................................................................................... 63
6.1.4
Clock BNC output.................................................................................................................... 64
6.1.5
LVDS in/output ....................................................................................................................... 65
6.2
LED's .............................................................................................................................................. 66
6.3
Channel LED's L1-L4...................................................................................................................... 66
6.4
PCB LEDs....................................................................................................................................... 67
7
Jumpers/Configuration ...................................................................................................68
7.1
7.2
7.3
7.4
7.5
8
JP80 VME addressing mode/reset behaviour .................................................................................... 68
CON100B JTAG ............................................................................................................................. 68
JP101 JTAG chain........................................................................................................................... 69
SW1 and SW2, VME base address................................................................................................... 70
JTAG source ................................................................................................................................... 70
Getting started................................................................................................................71
8.1
8.2
9
SIS3350 base program..................................................................................................................... 71
SIS3350 visual start ......................................................................................................................... 72
Appendix .......................................................................................................................73
9.1
Power consumption ......................................................................................................................... 73
9.2
Operating conditions........................................................................................................................ 73
9.2.1
Cooling.................................................................................................................................... 73
9.2.2
Hot swap/live insertion............................................................................................................. 73
9.3
Connector types............................................................................................................................... 74
9.4
P2 row A/C pin assignments ............................................................................................................ 74
9.5
Row d and z Pin Assignments.......................................................................................................... 75
9.6
Firmware upgrade............................................................................................................................ 76
9.6.1
Upgrade over CON100............................................................................................................. 76
9.6.2
Upgrade over VME.................................................................................................................. 76
10
Index ..........................................................................................................................77
Page 4 of 79
SIS Documentation
1
SIS3350
500 MHz 12-bit Digitizer
Introduction
The SIS3350 is the extension of our 12-bit digitizer family (so far consisting of the 100 MHz SIS3300
and the 250 MHz SIS3320-250) towards higher sampling speed and deeper memory. The unit has 4
digitizer channels sampling at up to 500 MSamples/s each, and a default memory depth of 128
MSamples per channel (i.e. acquisition of ¼ s at full sampling rate). The use of 512 MSamples per
channel (allowing for 1s acquisition at full sampling speed) is prepared also.
An offset DAC per channel in combination with a variable gain amplifier (VGA) gives you
oscilloscope like input stage behaviour in combination with superior resolution.
The module was designed in a fashion, that it can be operated in any 6U standard VME
enclosure/crate, i.e. no non standard voltages going beyond +5, -12V and +12 V are required. The card
is a single slot (4TE) design which is available with standard and VME64x lever handles.
Besides VME bus readout functionality a 4 GBit optical link and a 10/100/1000 raw Ethernet are
available as data transfer options with given interest in the corresponding firmware implementation.
The 4 GBit LC-LC SFF (small form factor) link medium connection is foreseen to be used in
combination with the SIS1100-eCMC PCI Express card.
Applications comprise but are not limited to:
digitization of fast detector signals
accelerator/machine controls
As we are aware, that no manual is perfect, we appreciate your feedback and will try to incorporate
proposed changes and corrections as quickly as possible. The most recent version of this manual can
be obtained by email from [email protected], the revision dates are online under
http://www.struck.de/manuals.htm.
1.1 Related documents
A list of available firmware designs can be retrieved from http://www.struck.de/sis3350firm.htm
Page 5 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2 Technical Properties/Features
2.1 Key functionality
Find below a list of key features of the SIS3350 digitizer.
4 channels
12-bit resolution
128 MSamples/channel memory
special clock modes (clock prescaling, external “arbitrary” clock)
Variable gain amplifiers (VGA)
offset DACs
external/internal clock
external random clock
multi event mode
read on the fly (actual sample value)
pre/post trigger option
readout in parallel to acquisition
trigger generation (FIR trigger)
4 NIM control inputs/4 NIM control outputs
A32 D32/BLT32/MBLT64/2eVME
Hot swap (in conjunction with VME64x backplane)
VME64x Connectors
VME64x Front panel
VME64x extractor handles (on request)
F1002 compatible P2 row A/C assignment
+5 V, +12V and –12 V VME standard voltages
Optical 4-Gigabit link connection
Ethernet connection
Note: The SIS3350 shall not be operated on P2 row A/C extensions, like VSB e.g. due to the
compatibility to the F1001 FADC modules clock and start/stop distribution scheme. The P2
row A/C connections can be removed on request.
Page 6 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.2 Module design
The SIS3350 consists of two identical groups of 2 ADC channels each and a control section
as shown in the simplified block diagram below.
System
Clock
Front Panel
Control I/O
Clock
Distribution
VME Interface
and
Control FPGA
Address
Data
Dual Channel Group 2 (Channels 3 and 4)
Dual Channel Group 1 (Channels 1 and 2)
Page 7 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.2.1 Dual channel group
Two ADC channels form a group, which memory is handled by one Field Programmable
Gate Array (FPGA). A dual channel group has block memory, which resides in the FPGA,
and external DDR2 memory (128 MSamples/channel default). The block memory holds a
ring buffer with a “length” of 16 K samples per channel.
DAC
Memory
PRE
AMP
VGA
ADC
LED
Memory
ADC
FPGA
LED
PRE
AMP
VGA
ADC
Memory
Memory
Memory
Memory
Memory
DAC
2.2.2 Memory philosophy
The DDR2 memory of the SIS3350 is controlled by the sample start address during
acquisition. The default memory of 128 MSamples/channel is divided into 16 pages of 16
MByte each. The memory page register defines which page can be accessed over the VME
bus. Full memory is accessible during acquisition however with the option to restrict the use
to part of the memory, or to divide the memory into smaller events.
Page 8 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.2.3 Internal memory handling
The stream of digitized data from the ADC chips is always recorded to the block memory of
the FPGA chips. This mechanism facilitates DDR2 memory refresh handling and the
implementation of parallel acquisition and readout.
We distinguish two basic memory modes
Ring buffer acquisition
Direct memory acquisition
Ring buffer acquisition is limited to events that fit completely into the 16K block memory and
the complete event is transferred to DDR2 memory upon completion. In direct memory
acquisition blocks of data are streamed to DDR2 memory during acquisition.
This internal memory handling implementation enables on board data rearrangement prior to
readout in all modes of operation except for “Direct Memory Trigger Stop”.
16 K Samples FPGA
Ring Buffer Block Memory
(not user accessible)
128 M Samples
DDR2 Memory
(user/VME accessible)
Event N
Trigger
Next Event
Acquisition
Empty or old data
Post Trigger
Pre Trigger
Header Information
Note: please refer to the PDF in case of black print
Page 9 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.3 Modes of Operation
The implemented modes of operation of this generic SIS3350 firmware implementation are
listed in this section.. The FPGA based design of the card allows to meet the requirements of
many readout applications with dedicated firmware designs in the future.
6 modes of operation are implemented
Ring buffer asynchronous
Ring buffer synchronous
Direct memory gate asynchronous
Direct memory gate synchronous
Direct memory stop
Direct memory start
Note: the individual channels acquire data asynchronously in the two asynchronous modes of
operation. This implies, that the user will want to use the address counter and/or the address
threshold to decide on which channel(s) has/have to be read out.
2.3.1 Ring buffer asynchronous Mode
Trigger sources:
- internal Threshold Trigger (each channel individual)
- internal FIR Trigger Trigger (each channel individual)
- no external Trigger !
- no Trigger delay !
Used Parameters:
- programmable Ringbuffer PRE length (up to 16380 in steps of 2 samples)
- programmable Ringbuffer Sample length (up to 16384 in steps of 8 samples)
End of acquisition condition:
- Address Threshold
No explicit Multievent
Page 10 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.3.2 Ring buffer synchronous Mode
Trigger source:
- internal Threshold Trigger (or of all channels)
- internal FIR Trigger (or of all channels)
- internal VME Key
- external Trigger (LEMO, LVDS)
- no Trigger delay !
End of acquisition condition:
- Single Event
- Multi Event (programmable nof_events)
- (Address Threshold !)
- Address Counter
Used Parameters:
- programmable Ringbuffer PRE length (up to 16380 in steps of 2 samples)
- programmable Ringbuffer Sample length (up to 16384 in steps of 8 samples)
2.3.3 Direct Memory Gate asynchronous Mode
Gate source:
- internal Threshold Gate (On,Off) (each channel individual)
- no Gate (Trigger) delay !
Used Parameters:
- programmable Ringbuffer PRE length (up to 16380 in steps of 2 samples)
- programmable Max Length
- programmable Gate Extend Length
End of acquisition condition:
- Address Threshold !
- Address Counter
Page 11 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.3.4 Direct Memory Gate synchronous Mode
Gate source:
- internal Threshold Gate (On,Off) (or of all channels)
- external Gate (Trigger) (LEMO, LVDS)
- no Gate (Trigger) delay !
Used Parameters:
- programmable Ringbuffer PRE length (up to 16380 in steps of 2 samples)
- programmable Max Length
- programmable Gate Extend Length
End of acquisition condition:
- Single Event
- Multi Event (programmable nof_events)
- Address Threshold
Find below a illustration for gate mode. Besides gate chaining you can see the effect of the
pre length (pre) and gate extend length (extend) parameters. This mode of operation can be
used for sparsified data acquisition also.
Page 12 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.3.5 Direct Memory Stop Mode
Trigger source:
- internal Threshold Trigger (or of all channels)
- internal FIR Trigger (or of all channels)
- internal VME Key
- external Trigger (LEMO, LVDS)
- Trigger delay
End of acquisition condition:
- Single Event
- Multi Event (programmable nof_events)
- Address Threshold
Used Parameters:
- programmable Ringbuffer PRE length (up to 16380 in steps of 2 samples)
2.3.6 Direct Memory Start Mode
Trigger source:
- internal Threshold Trigger (or of all channels)
- internal FIR Trigger (or of all channels)
- internal VME Key
- external Trigger (LEMO, LVDS)
- Trigger delay
End of acquisition condition:
- Single Event
- Multi Event (programmable nof_events)
- Address Threshold
Used Parameters:
- Tbd.
Page 13 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.4 Clock sources
The SIS3350 features following clock modes
Internal fixed clock
Internal frequency synthesizer
External analog
External LVDS
2.4.1 Internal clock
The internal clock is generated from an on board 100 MHz quartz or a frequency synthesizer.
Internal clock speeds
100 MHz fixed
Synthesizer 31.25 – 500 MHz
2.4.2 External clock (BNC analog or LVDS)
A analog (symmetric) external clock (ratio between 45:55 and 55:45) can be fed to the
module through the BNC connector. The clock that is distributed to the digitizer chips is
derived with the clock DAC and a comparator. The BNC clock output can be used to verify
that the resulting meets symmetry requirements.
Alternatively a LVDS clock can be fed to the module over the HDMI connector (Pins 1-3).
Min. sym. clock
1 MHz
Max sym. clock
500 MHz
2.5 Trigger control (pre/post, start/stop and gate mode)
The SIS3350 features pre/post trigger capability as well as start/stop mode acquisition and a
gate mode (in which start and stop are derived from the leading and trailing edge of a single
control input signal).
2.6
Internal Trigger generation
The trigger output of the SIS3350 can be either used to interact with external trigger logic or
to base start/stop on a threshold (i.e. one individual threshold per ADC channel) of the
digitized data.
The user can select between triggering on the conditions above and below threshold
A FIR trigger mode is implemented as second trigger alternative..
Page 14 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
2.7 VME Interrupts
Two registers, the Interrupt configuration and the Interrupt control register, are implemented
for interrupt setup and control.
Four interrupt sources are implemented:
Reached End Address Threshold (level sensitive)
Reached End Address Threshold (edge sensitive)
End of event
End of last event in multi event mode
Page 15 of 79
SIS Documentation
3
SIS3350
500 MHz 12-bit Digitizer
VME Addressing
As the SIS3350 VME FADC features memory options with up to 4 times 512 MSamples,
A32 addressing was implemented as the only option for the time being. The module occupies
an address space of 0x7FFFFFF Bytes, i.e. 128 MBytes are used by the module.
The base address is defined by the selected addressing mode, which is selected by jumper
array JP80 and SW1 and SW2 (in non geographical mode).
The table below summarises the possible base address settings.
JP80 Setting
A32 A16 GEO
x
x
x
Not implemented in this design
x
Shorthand
SW1/SW2
Bits
31 30 29 28 27
SW1
SW2=0...7
Bit 27=0
SW1
SW2=8...F
Bit 27=1
Not implemented in this design
Explanation
Setting of rotary switch SW1 or SW2 respective
Notes:
This concept allows the use of the SIS3350 in standard VME as well as in VME64x
environments, i.e. the user does not need to use a VME64x backplane.
The factory default setting is EN_A32 closed, SW1=3, SW2=0 (i.e. the module will react
to A32 addressing under address 0x30000000). With more than one unit shipped in one
batch a set of addresses (like 0x10000000, 0x20000000, 0x30000000,...) may be used
also.
The A16 jumper allows for a future changed addressing scheme with different resource
allocation
Page 16 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
3.1 Address Map
The SIS3350 resources and their locations are listed in the table below.
Note: Write access to a key address (KA)with arbitrary data invokes the respective action
Offset
Size in
Bytes
BLT
Access
0x00000000
0x00000004
0x00000008
0x0000000C
4
4
4
4
-
W/R
R only
R/W
R/W
0x00000010
0x00000014
0x00000018
0x0000001C
4
4
4
4
-
R/W
R/W
R/W
R/W
R/W
R only
R/W
R/W
0x00000020
0x00000024
0x00000028
0x0000002C
Function
Control/Status Register (J-K register)
Module Id. and Firmware Revision register
Interrupt configuration register
Interrupt control register
Acquisition control/status register (J-K register)
Direct Memory Trigger Delay register
Direct Memory Start Mode Sample Length register
Frequency Synthesizer register
MultiEvent Max Nof Events register
MultiEvent Event Counter
Gate Synch Mode Event Length Limit register
Gate Synch Mode Event Length Extend register
0x00000030
0x00000034
0x00000038
4
4
4
-
R/W
R/W
R/W
CBLT/Broadcast Setup register
ADC Memory Page register
Trigger Output Select register
0x00000050
4
-
R/W
0x00000054
4
-
R/W
Clock and Trigger Input DAC Control Status register
(input threshold)
Clock and Trigger Input DAC Data register
(input threshold)
0x00000060
0x00000064
R/W
W only
XILINX JTAG_TEST/JTAG_DATA_IN
XILINX JTAG_CONTROL
0x00000070
0x00000074
R only
W only
Temperature Register
ADC Serial Interface (SPI) register
0x00000400
4
-
KA
General Reset
0x00000410
0x00000414
0x00000418
0x0000041C
4
4
4
4
-
KA
KA
KA
KA
Arm Sampling Logic
Disarm Sampling Logic
Trigger
Timestamp Clear
Page 17 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Event information all ADC groups
0x01000000
4
0x01000004
4
0x01000008
4
-
W
Event configuration register (all ADCs)
Direct Memory Stop Mode Sample Wrap Length register
(all ADCs)
Sample Start address register (all ADCs)
0x01000020
0x01000024
0x01000028
4
4
4
-
W
W
W
Ringbuffer Sample Length (all ADCs)
Ringbuffer PRE Delay (all ADCs)
End Address Threshold (all ADCs)
-
R/W
R/W
Event information ADC group 1
0x02000000
4
0x02000004
4
W
W
Event configuration register (ADC1, ADC2)
Direct Memory Stop Mode Sample Wrap Length register
(ADC1, ADC2)
Sample Start address register (ADC1, ADC2)
0x02000008
4
-
R/W
0x02000010
0x02000014
4
4
-
R
R
0x02000020
0x02000024
0x02000028
4
4
4
-
R/W
R/W
R/W
Ringbuffer Sample Length (ADC1, ADC2)
Ringbuffer PRE Delay (ADC1, ADC2)
End Address Threshold (ADC1, ADC2)
0x02000030
0x02000034
0x02000038
0x0200003C
4
4
4
4
R/W
R/W
R/W
R/W
ADC1 Trigger setup register
ADC1 Trigger Threshold register
ADC2 Trigger setup register
ADC2 Trigger Threshold register
0x02000040
0x02000044
4
4
R/W
R/W
ADC1 Input Tap Delay register
ADC2 Input Tap Delay register
0x02000048
0x0200004C
0x02000050
0x02000054
4
4
4
4
R/W
R/W
R/W
R/W
ADC1 VGA register
ADC2 VGA register
ADC1/ADC2 DAC Control Status register
ADC1/ADC2 DAC Data register
0x02000070
0x02000074
0x02000078
0x0200007C
4
4
4
4
R/W
R/W
R/W
R/W
ADC1 Sample Counter
ADC1 Sample Counter
ADC2 Sample Counter
ADC2 Sample Counter
Page 18 of 79
-
Next Sample address register ADC1
Next Sample address register ADC2
T1/T2 setup register
T3/T4 setup register
T1/T2 setup register
T3/T4 setup register
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Event information ADC group 2
0x03000000
4
0x03000004
4
-
R/W
R/W
Event configuration register (ADC3, ADC4)
Direct Memory Stop Mode Sample Wrap Length register
(ADC3, ADC4)
Sample Start address register (ADC3, ADC4)
0x03000008
4
-
R/W
0x03000010
0x03000014
4
4
-
R
R
0x03000020
0x03000024
0x03000028
4
4
4
-
R/W
R/W
R/W
Ringbuffer Sample Length (ADC3, ADC4)
Ringbuffer PRE Delay (ADC3, ADC4)
End Address Threshold (ADC3, ADC4)
0x03000030
0x03000034
0x03000038
0x0300003C
4
4
4
4
R/W
R/W
R/W
R/W
ADC3 Trigger setup register
ADC3 Trigger Threshold register
ADC4 Trigger setup register
ADC4 Trigger Threshold register
0x03000040
0x03000044
4
4
R/W
R/W
ADC3 Input Tap Delay register
ADC4 Input Tap Delay register
0x03000048
0x0300004C
0x03000050
0x03000054
4
4
4
4
R/W
R/W
R/W
R/W
ADC3 VGA register
ADC4 VGA register
ADC3/ADC4 DAC Control Status register
ADC3/ADC4 DAC Data register
0x03000070
0x03000074
0x03000078
0x0300007C
4
4
4
4
R/W
R/W
R/W
R/W
ADC3 Sample Counter
ADC3 Sample Counter
ADC4 Sample Counter
ADC4 Sample Counter
ADC memory pages
0x04000000
16 MByte
0x05000000
16 MByte
0x06000000
16 MByte
0x07000000
16 MByte
-
X
X
X
X
R
R
R
R
Next Sample address register ADC3
Next Sample address register ADC4
T1/T2 setup register
T3/T4 setup register
T1/T2 setup register
T3/T4 setup register
ADC 1 memory page
ADC 2 memory page
ADC 3 memory page
ADC 4 memory page
Note 2: MBLT64 read access is supported from memory (i.e. not from register space) only.
Page 19 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4 Register Description
The function of the individual registers is described in detail in this section.
The first line after the subsection header (in Courier font) like:
#define SIS3350_CONTROL_STATUS
0x0
/* read/write; D32 */
refers to the SIS3350.h header file.
4.1 Control/Status Register(0x0, write/read)
#define SIS3350_CONTROL_STATUS
0x0
/* read/write; D32 */
The control register is implemented as a selective J/K register, a specific function is enabled
by writing a 1 into the set/enable bit, the function is disabled by writing a 1 into the
clear/disable bit (which location is 16-bit higher in the register). An undefined toggle status
will result from setting both the enable and disable bits for a specific function at the same
time. The only function at this point in time is user LED on/off.
On read access the same register represents the status register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
write Function
Clear reserved 15 (*)
Clear reserved 14 (*)
Clear reserved 13 (*)
Clear reserved 12 (*)
Clear reserved 11 (*)
Clear reserved 10 (*)
Clear reserved 9 (*)
Clear reserved 8 (*)
Clear reserved 7 (*)
Clear reserved 6 (*)
Clear reserved 5 (*)
Clear Invert Bit for external Lemo TRG IN (*)
Clear reserved 3 (*)
Clear reserved 2 (*)
Clear reserved 1 (*)
Switch off user LED (*)
Set reserved 15
Set reserved 14
Set reserved 13
Set reserved 12
Set reserved 11
Set reserved 10
Set reserved 9
Set reserved 8
Set reserved 7
Set reserved 6
Set reserved 5
Set Invert Bit for external Lemo TRG IN
read Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Status reserved 15
Status reserved 14
Status reserved 13
Status reserved 12
Status reserved 11
Status reserved 10
Status reserved 9
Status reserved 8
Status reserved 7
Status reserved 6
Status reserved 4
Status Set Invert bit for external Lemo TRG IN
3
2
1
0
Set reserved 3
Set reserved 2
Set reserved 1
Switch on user LED
Status reserved 3
Status reserved 2
Status reserved 1
Status User LED (1=LED on, 0=LED off)
(*) denotes power up default setting
Page 20 of 79
SIS Documentation
Invert bit
for external Lemo TRG IN
SIS3350
500 MHz 12-bit Digitizer
function
0
Don’t invert:
Use for high active TTL signal (rising edge)
1
Invert:
Use for low active TTL signals (falling edge)
Use for NIM signals (leading edge)
Page 21 of 79
SIS Documentation
4.2
SIS3350
500 MHz 12-bit Digitizer
Module Id. and Firmware Revision Register (0x4, read)
#define SIS3350_MODID
0x4
/* read only; D32 */
This register reflects the module identification of the SIS3350 and its minor and major
firmware revision levels. The major revision level will be used to distinguish between
substantial design differences and experiment specific designs, while the minor revision level
will be used to mark user specific adaptations.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function
Module Id. Bit 15
Module Id. Bit 14
Module Id. Bit 13
Module Id. Bit 12
Module Id. Bit 11
Module Id. Bit 10
Module Id. Bit 9
Module Id. Bit 8
Module Id. Bit 7
Module Id. Bit 6
Module Id. Bit 5
Module Id. Bit 4
Module Id. Bit 3
Module Id. Bit 2
Module Id. Bit 1
Module Id. Bit 0
Major Revision Bit 7
Major Revision Bit 6
Major Revision Bit 5
Major Revision Bit 4
Major Revision Bit 3
Major Revision Bit 2
Major Revision Bit 1
Major Revision Bit 0
Minor Revision Bit 7
Minor Revision Bit 6
Minor Revision Bit 5
Minor Revision Bit 4
Minor Revision Bit 3
Minor Revision Bit 2
Minor Revision Bit 1
Minor Revision Bit 0
Reading
4.2.1 Major revision numbers
Find below a table with major revision numbers used to date
Major revision number
0x01
Page 22 of 79
Application/user
Generic designs
3
3
5
0
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.3 Interrupt configuration register (0x8)
#define SIS3350_IRQ_CONFIG
0x8
/* read/write; D32 */
This read/write register controls the VME interrupt behaviour of the SIS3350 ADC. Four
interrupt sources are foreseen, for the time being three of them are associated with an interrupt
condition, the fourth condition is reserved for future use.
The interrupter type is DO8 .
4.3.1 IRQ mode
In RORA (release on register access) mode the interrupt will be pending until the IRQ
source is cleared by specific access to the corresponding disable VME IRQ source bit. After
the interrupt is serviced the source has to be activated with the enable VME IRQ source bit
again.
In ROAK (release on acknowledge) mode , the interrupt condition will be cleared (and the
IRQ source disabled) as soon as the interrupt is acknowledged by the CPU. After the interrupt
is serviced the source has to be activated with the enable VME IRQ source bit again.
Bit
31
...
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function
RORA/ROAK Mode (0: RORA; 1: ROAK)
VME IRQ Enable (0=IRQ disabled, 1=IRQ enabled)
VME IRQ Level Bit 2
VME IRQ Level Bit 1
VME IRQ Level Bit 0 (0 always)
IRQ Vector Bit 7; placed on D7 during VME IRQ ACK cycle
IRQ Vector Bit 6; placed on D6 during VME IRQ ACK cycle
IRQ Vector Bit 5; placed on D5 during VME IRQ ACK cycle
IRQ Vector Bit 4; placed on D4 during VME IRQ ACK cycle
IRQ Vector Bit 3; placed on D3 during VME IRQ ACK cycle
IRQ Vector Bit 2; placed on D2 during VME IRQ ACK cycle
IRQ Vector Bit 1; placed on D1 during VME IRQ ACK cycle
IRQ Vector Bit 0; placed on D0 during VME IRQ ACK cycle
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The power up default value reads 0x 00000000
Page 23 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.4 Interrupt control register (0xC)
#define SIS3350_IRQ_CONTROL
0xC
/* read/write; D32 */
This register controls the VME interrupt behaviour of the SIS3350 ADC. Eight interrupt
sources are foreseen, for the time being two of them are associated with an interrupt
condition, the others are reserved for future use.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function (w)
Update IRQ Pulse
unused
unused
unused
unused
unused
unused
unused
Disable/Clear IRQ source 7
Disable/Clear IRQ source 6
Disable/Clear IRQ source 5
Disable/Clear IRQ source 4
Disable/Clear IRQ source 3
Disable/Clear IRQ source 2
Disable/Clear IRQ source 1
Disable/Clear IRQ source 0
unused
unused
unused
unused
unused
unused
unused
unused
Enable IRQ source 7
Enable IRQ source 6
Enable IRQ source 5
Enable IRQ source 4
Enable IRQ source 3
Enable IRQ source 2
Enable IRQ source 1
Enable IRQ source 0
(r)
Status IRQ source 7 (reserved)
Status IRQ source 6 (reserved)
Status IRQ source 5 (reserved)
Status IRQ source 4 (reserved)
Status IRQ source 3 (End Address Threshold Flag; level sensitive)
Status IRQ source 2 (End Address Threshold Flag; edge sensitive)
Status IRQ source 1 (End of last Event; edge sensitive)
Status IRQ source 0 (End of Event; edge sensitive)
Status flag source 7
Status flag source 6
Status flag source 5
Status flag source 4
Status flag source 3
Status flag source 2
Status flag source 1
Status flag source 0
Status VME IRQ
Status internal IRQ
0
0
0
0
0
0
Status enable source 7 (read as 1 if enabled, 0 if disabled)
Status enable source 6 (read as 1 if enabled, 0 if disabled)
Status enable source 5 (read as 1 if enabled, 0 if disabled)
Status enable source 4 (read as 1 if enabled, 0 if disabled)
Status enable source 3 (read as 1 if enabled, 0 if disabled)
Status enable source 2 (read as 1 if enabled, 0 if disabled)
Status enable source 1 (read as 1 if enabled, 0 if disabled)
Status enable source 0 (read as 1 if enabled, 0 if disabled)
The power up default value reads 0x 00000000
IRQ source 3:
IRQ source 2:
IRQ source 1:
IRQ source 0:
Page 24 of 79
reached Address Threshold (level sensitive)
reached Address Threshold (edge sensitive)
end of last event (disarm)
end of event
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIS Documentation
4.5
SIS3350
500 MHz 12-bit Digitizer
Acquisition control register (0x10, read/write)
#define SIS3350_ACQUISTION_CONTROL
0x10
/* read/write; D32 */
The acquisition control register is in charge of most of the settings related to the actual
configuration of the digitization process.
Like the control register it is implemented in a J/K fashion.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Write Function
Clear reserved 15 (*)
Clear reserved 14 (*)
Clear Clock Source Bit1
Clear Clock Source Bit0
Clear reserved 11 (*)
Clear reserved 10 (*)
Clear external LVDS TRG IN as Gate/Trigger (*)
Disable external Lemo TRG IN as Gate/Trigger (*)
Clear reserved 7 (*)
Disable internal trigger as Gate/Trigger (*)
Disable Multi Event mode (*)
Clear reserved 4 (*)
Clear reserved 3 (*)
Clear Operation Mode Bit 2 (*)
Clear Operation Mode Bit 1 (*)
Clear Operation Mode Bit 0 (*)
Set reserved 15
Set reserved 14
Set clock source Bit 1
Set clock source Bit 0
Set reserved 11
Set reserved 10
Enable external LVDS TRG IN as Gate/Trigger
Enable external Lemo TRG IN as Gate/Trigger
Set reserved 7
Enable internal channel triggers as Gate/Trigger
5
4
3
2
1
0
Enable Multi Event mode
Set reserved 4
Set reserved 3
Set Mode of Operation Bit 2
Set Mode of Operation Bit 1
Set Mode of Operation Bit 0
Read
0
0
0
0
0
0
0
0
0
0
0
0
Status of End Address Threshold Flag
0
ADC Sampling Busy
ADC Sampling Logic Armed
Status reserved 15
Status reserved 14
Status clock source Bit 1
Status clock source Bit 0
Status reserved 11
Status reserved 10
Status reserved 9
Status reserved 8
Status reserved 7
Status enable internal channel triggers
as Gate/Trigger
Status Multi Event mode
Status reserved 3
Status Mode of Operation Bit 2
Status Mode of Operation Bit 1
Status Mode of Operation Bit 0
The power up default value reads 0x0
Page 25 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Operation Mode bit setting table:
Mode of
Mode of
Mode of
Mode of Operation
Operation Operation Operation
Bit 2
Bit 1
Bit 0
0
0
0
Ringbuffer Asynchronous Mode
0
0
1
Ringbuffer Synchronous Mode
0
0
1
1
0
1
Direct Memory Gate Asynchronous Mode
Direct Memory Gate Synchronous Mode
1
1
0
0
0
1
Direct Memory Trigger Stop Mode
Direct Memory Trigger Start Mode
1
1
1
1
0
1
reserved
reserved
Multi Event mode bit:
0 : Sampling Logic Armed state will be cleared at end of event
1 : Sampling Logic Armed state will be cleared at end of
last event (defined with MultiEvent Max Nof Events register)
Clock source bit setting table:
Clock Source
Bit1
0
0
1
1
Page 26 of 79
Clock Source
Bit0
0
1
0
1
Clock Source
Frequency Synthesizer (up to 500 MHz)
internal 100 MHz
external LVDS
external BNC
SIS Documentation
4.6
SIS3350
500 MHz 12-bit Digitizer
Direct Memory Trigger Delay register (0x14, read/write)
#define SIS3350_TRIGGER_DELAY
0x14
/* read/write; D32 */
The external trigger signals (LVDS, LEMO) and the internal trigger signal will be delayed by
the value of the trigger delay register (in samples) in conjunction with the modes of operation
“Direct Memory Trigger Stop Mode” and “Direct Memory Trigger Start Mode”.
The maximum programmable delay is 64M samples (i.e. half memory depth).
(Pretrigger function!)
Bit
31
...
26
25
..
..
1
0
unused, read as 0
unused, read as 0
TRIGGER_DELAY_BIT25
TRIGGER_DELAY_BIT1
“0”
The power up default value is 0
4.7
Direct Memory Start Mode Sample Length register (0x18, read/write)
#define SIS3350_DIRECT_MEMORY_SAMPLE_LENGTH
0x18
/* read/write; D32 */
This register defines the number of samples in conjunction with the mode of operation
“Direct Memory Trigger Start Mode”.
The maximum programmable sample length is 128M - 8 .
Bit
31
...
27
26
..
..
3
2
1
0
unused, read as 0
unused, read as 0
SAMPLE_LENGTH_BIT26
SAMPLE_LENGTH_BIT3
“0”
“0”
“0”
The power up default value is 0
4.8 Frequency Synthesizer register (0x1C, read/write)
#define SIS3350_FREQUENCE_SYNTHESIZER
0x1C
/* read/write; D32 */
This register defines the sampling frequency of the SIS3350 in frequency synthesizer clock
mode
Page 27 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
The frequency is defined by the expression: Frequency = 25 MHz * M / 2N
Bit
31
...
11
10
9
8
..
0
Function
unused, read as 0
unused, read as 0
N1 (bit 1 of N Divider)
N0 (bit 0 of N Divider)
M8 (bit 8 of M)
M0 (bit 0 of M)
The power up default value is 0x14 (20 -> 20 x 25MHz = 500MHz)
Note: The N Divider setting has to be chosen in accordance with the frequency limits
specified in the table below
Valid N Divider frequency range setting table
Inputs
N1
0
0
1
1
Page 28 of 79
N0
0
1
0
1
N Divider
Value
1
2
4
Output Frequency (MHz)
Minimum
Maximum
250
500
125
350
62.5
175
31.25
87.5
SIS Documentation
4.9
SIS3350
500 MHz 12-bit Digitizer
MultiEvent Max Nof Events register (0x20, read/write)
#define SIS3350_MULTIEVENT_MAX_NOF_EVENTS
*/
0x20
/* read/write; D32
The Sampling Logic will be disarmed in Multi Event mode as soon as the Event counter
reaches the value of the MultiEvent_Max_Nof_Events register.
Bit
31
...
20
19
..
..
0
unused, read as 0
unused, read as 0
MAX NOF Events Bit19
MAX NOF Events Bit 0
The power up default value is 0
4.10 MultiEvent Event_Counter (0x24, read)
#define SIS3350_MULTIEVENT_EVENT_COUNTER
0x24
/* read; D32 */
This register holds the actual number of events in multi event mode.
The Event Counter is cleared when the Sampling Logic is armed and it is incremented with
every start sampling.
Bit
31
...
20
19
..
..
0
unused, read as 0
unused, read as 0
Actual Event counter Bit 19
Actual Event counter Bit 0
The power up default value is 0
Page 29 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.11 Gate Synch Mode Event Length Limit register (0x28, read/write)
#define SIS3350_GATE_SYNCH_LIMIT_LENGTH
0x28
/* read/write; D32 */
This register defines the maximum number of samples in conjunction with the mode of
operation “Direct Memory Gate Synchronous Mode”.
The maximum programmable limit length is 64M - 8 .
The limit logic is disabled if the value is 0.
Bit
31
...
26
25
..
3
2
1
0
unused, read as 0
unused, read as 0
GATE_LIMIT_LENGTH_BIT25
GATE_LIMIT_LENGTH _BIT3
“0”
“0”
“0”
The power up default value is 0
4.12 Gate Synch Mode Event Length Extend register (0x2C, read/write)
#define SIS3350_GATE_SYNCH_EXTEND_LENGTH
0x2C
/* read/write; D32 */
This register defines the additional sample length to the the gate length in conjunction with
the mode of operation “Direct Memory Gate Synchronous Mode”.
In combination with the ringbuffer Delay register it is possible program the PreGate and
PostGate length.
The maximum programmable extend length is 248 .
Bit
31
...
26
7
..
3
2
1
0
unused, read as 0
unused, read as 0
GATE_EXTEND_LENGTH_BIT7
GATE_ EXTEND _LENGTH _BIT3
“0”
“0”
“0”
The power up default value is 0
Page 30 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.13 CBLT/Broadcast setup register
#define SIS3350_CBLT_BROADCAST_SETUP
0x30
/* read/write; D32 */
This read/write register defines, whether the SIS3350 will participate in a Broadcast. The
configuration of this register and the registers of other participating modules is essential for
proper Broadcast behaviour.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function
CBLT/Broadcast address bit 31
CBLT/Broadcast address bit 30
CBLT/Broadcast address bit 29
CBLT/Broadcast address bit 28
CBLT/Broadcast address bit 27
CBLT/Broadcast address bit 26
CBLT/Broadcast address bit 25
CBLT/Broadcast address bit 24
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0
0
0
0
0
Enable Broadcast Master
Enable Broadcast
0
reserved
reserved
reserved
Page 31 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Broadcast functionality is implemented for all Key address cycles.
Modules which are supposed to participate in a broadcast have to get the same broadcast
address. The broadcast address is defined by the upper 8 bits of the broadcast setup register.
One module has to be configured as broadcast master, the enable broadcast bit has to be set
for the others as illustrated below.
Broadcast setup example (broadcast address 0x34000000):
Module
1
2
3
4
Broadcast Setup Register
0x34000020
0x34000010
0x34000010
0x34000010
Comment
Broadcast Master
Broadcast enable
Broadcast enable
Broadcast enable
All 4 modules will participate in a key reset (A32/D32 write) to address 0x34000400.
Note: Do not use a broadcast address that is an existing VME address of a VME card in the
crate.
Page 32 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.14 ADC Memory Page register
#define SIS3350_ADC_MEMORY_PAGE_REGISTER
0x34
/* read/write; D32 */
The SIS3350 default memory size per channel is 256 MByte (i.e. 128 MSample).
The VME address space window per ADC is limited to 16 MByte (8 MSample) however. The
read/write ADC memory page register is used to select one of the 16 memory subdivisions
(pages).
Bit
31
..
..
4
3
2
1
0
Function
Reserved
reserved
Page register bit 3
Page register bit 2
Page register bit 1
Page register bit 0
Example: readout routine for 128MSample readout
(see CVI/…./sis3350_configuration_readout_lib.c)
int sis3350_DMA_Read_MBLT64_ADC_DataBuffer(
unsigned int module_address,
unsigned int adc_channel,
unsigned int adc_buffer_sample_start_addr,
unsigned int adc_buffer_sample_length,
unsigned int* dma_got_no_of_words,
unsigned int* uint_adc_buffer)
/*
/*
/*
/*
/*
/*
VME Base address */
0 to 3 */
16-bit word start address */
16-bit word sample length */
read length of 32-bit words */
read buffer pointer*/
Page 33 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
ADC Memory Sample Address table:
Samples / Bytes
0/0
1/2
..
8 MSample - 1 / 16 MByte -2
8 MSample / 16 MByte
8 MSample + 8 / 16 MByte + 0x10
...
Sample
Address
0
1
..
Page register / VME Offset
Address
0
0 / 0x2
..
16 MSample / 32 MByte
0x007F FFFF 0 / 0x00FF FFFE
0x0080 0000 1 / 0x0
0x0080 0008 1 / 0x10
...
1 / 0x00FF FFFE
0x0100 0000 2 / 0x0
24 MSample / 48 MByte
0x0180 0000
3 / 0x0
32 MSample / 64 MByte
0x0200 0000
4 / 0x0
40 MSample / 80 MByte
0x0280 0000
5 / 0x0
48 MSample / 96 MByte
0x0300 0000
6 / 0x0
56 MSample / 112MByte
0x0380 0000
7 / 0x0
64 MSample / 128 MByte
0x0400 0000
8 / 0x0
72 MSample / 144 MByte
0x0480 0000
9 / 0x0
80 MSample / 160 MByte
0x0500 0000
10 / 0x0
88 MSample / 176 MByte
0x0580 0000
11 / 0x0
96 MSample / 192 MByte
0x0600 0000
12 / 0x0
104 MSample / 208 MByte
0x0680 0000
13 / 0x0
112 MSample / 224 MByte
0x0700 0000
14 / 0x0
120 MSample / 240 MByte
0x0780 0000
..
15 / 0x0
..
128 MSample - 1 / 256 MByte - 2
0x07FF FFFF 15 / 0x00FF FFFE
Page 34 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.15 Trigger Output Select register 0x38
#define SIS3350_LEMO_OUTPUT_SELECT_REGISTER
0x38
/* read/write; D32 */
This register is used to program on board trigger routing.
Bit
31
..
16
15
meaning
reserved
..
reserved
ADC4 _Trigger
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC3 _Trigger
ADC2 _Trigger
ADC1 _Trigger
reserved
reserved
LVDS _Trigger_IN
LEMO_Trigger_IN
ADC4 _Trigger
ADC3 _Trigger
ADC2 _Trigger
ADC1 _Trigger
reserved
reserved
LVDS _Trigger_IN
LEMO_Trigger_IN
Function
no
1: ADC4 _Trigger is ored to LVDS Trigger OUT
(EXTERNAL_CONTROL2_LVDS_OUT)
1: ADC3 _Trigger is ored to LVDS Trigger OUT
1: ADC2 _Trigger is ored to LVDS Trigger OUT
1: ADC1 _Trigger is ored to LVDS Trigger OUT
1: LVDS_Trigger_IN is ored to LVDS Trigger OUT
1: LEMO_Trigger_IN is ored to LVDS Trigger OUT
1: ADC4 _Trigger is ored to LEMO OUT
1: ADC3 _Trigger is ored to LEMO OUT
1: ADC2 _Trigger is ored to LEMO OUT
1: ADC1 _Trigger is ored to LEMO OUT
1: LVDS_Trigger_IN is ored to LEMO OUT
1: LEMO_Trigger_IN is ored to LEMO OUT
Page 35 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.16 External Clock/Trigger Input DAC Control Registers
The external clock and trigger inputs of the SIS3350 accept analog input signals for maximum
flexibility. The internal logic signals are generated on the card by comparing the input signal
to a digital to analog converter (DAC) output value.
Example routine:
(see CVI/…./sis3350_configuration_readout_lib.c)
int sis3350_write_dac_offset(unsigned int module_dac_control_status_addr,
unsigned int dac_select_no,
unsigned int dac_value )
;
4.16.1 Clock/Trigger DAC Control/Status register (0x50 read/write)
#define SIS3350_EXT_CLOCK_TRIGGER_DAC_CONTROL_STATUS 0x50
Bit
31
..
..
16
15
14
...
8
7
6
5
4
3
2
1
0
Write Function
None
..
..
None
None
None
None
None
None
None
DAC Selection Bit
..
none
DAC Command Bit 1
DAC Command Bit 0
DAC Selection Bit
Bit
0
1
Page 36 of 79
Function
Clock Input DAC
Trigger Input DAC
/* read/write; D32 */
Read Function
0
..
..
0
DAC Read/Write/Clear Cycle BUSY
0
...
0
0
0
0
status of DAC selection Bit
..
0
DAC Command Bit 1 Status
DAC Command Bit 0 Status
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
DAC Command Bit
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function
No function
Load shift register of selected DAC
Load selected DAC
Clear all DACs
A “Clear DAC” command sets the value of all DACs to analog ground
4.16.2 Clock/Trigger DAC Data register (0x 54 read/write)
#define SIS3350_EXT_CLOCK_TRIGGER_DAC_DATA
Bit
31
..
..
16
15
..
..
0
Write Function
none
..
..
none
DAC Output Register Bit 15
..
..
DAC Output Register Bit 0
0x54
/* read/write; D32 */
Read Function
DAC Input Register Bit 15 (from DAC)
..
..
DAC Input Register Bit 0
DAC Output Register Bit 15
0
0
DAC Output Register Bit 0
The table below lists a set of DAC values and their corresponding threshold voltage.
The table below lists a set of DAC values and their corresponding threshold voltage.
The maximum positive threshold value is +4,00V and the maximum negative
threshold value is -2,75 V.
Clock and Trigger Input threshold setting table.
Value
23700
30000
31500
37500
40000
46500
Threshold Voltage
- 2,75 V
- 836 mV
- 370 mV (NIM)
+ 1,45 V (TTL)
+ 2,2 V
+ 4,00 V
Page 37 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.16.3 DAC load sequence
The load sequence for the Analog Devices AD5570 DAC chip (please refer to the
documentation of the chip for more details) is illustrated below. The sequence is identical for
trigger/clock and ADC offset DACs (i.e. the same component is used in all places).
Sequence to load offset of channel N,
N=[0,1] (Clock, Trigger), (ADC offset 1, 2 /3, 4 respective)
dacdata=dacdatum[N]
daccontrol=1 (shift) + N << 4
read dacstatus
until busy==0
daccontrol=2 (load) + N << 4
read dacstatus
until busy==0
Page 38 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.16.4 XILINX JTAG_TEST register
#define SIS3350_XILINX_JTAG_TEST
0x60
/* write only; D32 */
This register is used in the firmware upgrade process over VME only. A TCK is generated
upon a write cycle to the register.
Bit
31
...
4
3
2
1
0
write Function
none
...
none
none
none
TMS
TDI
4.16.5 XILINX JTAG_DATA_IN register
#define SIS3350_XILINX_JTAG_DATA_IN
0x60
/* read only; D32 */
This register is used in the firmware upgrade process over VME only. It is at the same address
as the JTAG_TEST register and is used in read access. It operates as a shift register for TDO.
The contents of the register is shifted to the right by one bit with every positive edge of TCK
and the status of TDO is transferred to Bit 30. Bit 31 reflects the current value of TDO during
a read access.
4.16.6 XILINX JTAG_CONTROL register
#define SIS3350_XILINX_JTAG_CONTROL
0x64
/* write only; D32 */
This register is used in the firmware upgrade process over VME only.
Bit
31
...
4
3
2
1
Function
31
...
4
3
2
MUX_CMC_JTAG
0
JTAG_OUT_EN
write
none
...
none
none
none
0: tbd for VME/JTAG over CON100
1: tbd for VME/JTAG over CON100
0: Disable JTAG output
1: Enable JTAG output
Page 39 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.17 Temperature register (0x70, read/only)
The SIS3350 is equipped with a serial 10-bit Analog Devices AD7314 temperature sensor.
The temperature reading is stored in twos complement format.
Refer to the AD7314 data sheet for more detailed information.
#define SIS3350_INTERNAL_TEMPERATURE_REG
Bit
31
...
...
10
9
..
1
0
0x70
/* read; D32 */
unused, read as 0
unused, read as 0
Data Bit 9 (MSB)
Data Bit 1
Data Bit 0 (LSB)
The operating temperature ranges from -35 OC to +85 OC and is covered by the table below
Temperature
–50 OC
–25 OC
–0.25 OC
0 OC
+0.25 OC
+10 OC
+25 OC
+50 OC
+75 OC
+100 OC
Data Bit 9 . . . Bit 0
11 0011 1000
11 1001 1100
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
Note: The Celsius temperature reading is obtained by casting the read data to signed short and
dividing the obtained value by 4.0 after float conversion.
Page 40 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.18 ADC Serial Interface (SPI) register (0x74, read/write)
#define SIS3350_ADC_SERIAL_INTERFACE_REG
0x74
/* write; D32 */
Several parameters of the 12-bit 500 MS/s ADC AT85AS001 chip (like duty cycle
stabilization e.g.) can be configured with the SPI (serial Peripheral Interface). The SPI register
is the interface between the SIS3350 front end FPGAs and the ADC SPIs.
Please refer to the documentation of the AT85AS001 ADC chip for details.
Bit
31
...
...
24
23
22
21
20
19
18
17
16
15
14
..
1
0
unused, read as 0
unused, read as 0
reserved
reserved
ADC Select Bit 1
ADC Select Bit 0
reserved
Address Bit 2
Address Bit 1
Address Bit 0
Data Bit 15 (MSB)
Data Bit 14
Data Bit 1
Data Bit 0 (LSB)
The power up default value is 0x0
Page 41 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.19 Key address general reset (0x400 write only)
#define SIS3350_KEY_RESET
0x400
/* write only; D32 */
A write with arbitrary data to this register (key address) resets the SIS3350 to it’s power up
state.
4.20 Key address VME arm sampling logic (0x410 write only)
#define SIS3350_KEY_ARM
0x410
/* write only; D32 */
A write with arbitrary data to this register (key address) will arm the sampling logic.
4.21 Key address VME disarm sampling logic (0x414 write only)
#define SIS3350_KEY_DISARM
0x414
/* write only; D32 */
A write with arbitrary data to this register (key address) will disarm the sampling logic.
4.22 Key address VME Trigger
#define SIS3350_KEY_TRIGGER
0x418
/* write only; D32 */
A write with arbitrary data to this register (key address) will generate an trigger.
4.23 Key address VME Timestamp Clear
#define SIS3350_KEY_TIMESTAMP_CLEAR
0x41C
/* write only; D32 */
A write with arbitrary data to this register (key address) will clear the 48-bit timestamp
counter.
Page 42 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.24 Event configuration registers(0x01000000, 0x02000000, 0x03000000
read/write)
#define SIS3350_EVENT_CONFIG_ALL_ADC
0x01000000
/* write only;D32 */
#define SIS3350_EVENT_CONFIG_ADC12
#define SIS3350_EVENT_CONFIG_ADC34
0x02000000
0x03000000
/* read/write;D32 */
/* read/write;D32 */
This register is implemented for each channel group and it has to be written with the same
value, the best way is to make use of the address SIS3350_EVENT_CONFIG_ALL_ADC to write
to the registers of all channel groups simultaneously.
Bit
31
…
25
24
23
...
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Function
unused; read 0
…
unused; read 0
ADC group (0=group 0 [ADC 1 and 2], 1=group 1 [ADC 3 and 4])
unused; read 0
...
unused; read 0
ADC Memory Write via VME Test Enable
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
unused; read 0
Extra Header Enable bit
Page 43 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.25 Direct Memory Stop Mode Sample Wrap Length register
#define SIS3350_DIRECT_MEMORY_SAMPLE_WRAP_LENGTH_ALL_ADC
#define SIS3350_DIRECT_MEMORY_SAMPLE_WRAP_LENGTH_ADC12
#define SIS3350_DIRECT_MEMORY_SAMPLE_WRAP_LENGTH_ADC34
0x01000004
0x02000004
0x03000004
This register defines the number of samples of each event in conjunction with the mode of
operation “Direct Memory Trigger Stop Mode”.
The maximum programmable sample wrap length is 128M - 8 .
Bit
31
...
25
26
..
3
2
1
0
unused, read as 0
unused, read as 0
Sample Wrap Length Register BIT26
Sample Wrap Length Register BIT3
Unused
Unused
Unused
The power up default value is 0
Page 44 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.26 Sample Start address register
#define SIS3350_SAMPLE_START_ADDRESS_ALL_ADC
0x01000008
#define SIS3350_SAMPLE_START_ADDRESS_ADC12
#define SIS3350_SAMPLE_START_ADDRESS_ADC34
0x02000008
0x03000008
These registers define the memory start address.
The value is given in samples (i.e. number of 16-bit words)
Only Sample Start addresses on a 8 16-bit (sample) boundary (i.e. 16 bytes) are valid.
Bit
31
...
25
26
..
3
2
1
0
unused, read as 0
unused, read as 0
Sample Start Address Register Bit 26
Sample Start Address Register Bit 3
unused
unused
unused
The power up default value is 0
Explanation (sample start address)
The contents of the start sample register is assigned as memory data storage address with the
arm command (key address arm sampling).
Page 45 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.27 ADC Next Sample address register
#define
#define
#define
#define
SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC1
SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC2
SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC3
SIS3350_ACTUAL_SAMPLE_ADDRESS_ADC4
0x02000010
0x02000014
0x03000010
0x03000014
These 4 read only registers hold the next sampling address for the given channel.
Bit
31
...
25
26
..
3
2
1
0
Function
unused, read as 0
unused, read as 0
Sample Address Bit 26
Sample Address Bit 3
0
0
0
The power up default value is 0
Page 46 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.28 Ringbuffer Sample Length register
#define SIS3350_RINGBUFFER_SAMPLE_LENGTH_ALL_ADC
#define SIS3350_RINGBUFFER_SAMPLE_LENGTH_ADC12
#define SIS3350_RINGBUFFER_SAMPLE_LENGTH_ADC34
0x01000020
0x02000020
0x03000020
This register defines the number of samples in conjunction with the modes of operation
“Ringbuffer Asynchronous Mode” and “Ringbuffer Synchronous Mode”.
The maximum programmable sample length is 16376 (16K – 8) .
It defines also the additional sample length to the the gate length in conjunction with the mode
of operation “Direct Memory Gate Asynchronous Mode”.
In combination with the Ringbuffer Delay register it is possible program the PreGate and
PostGate length.
The maximum programmable sample length is 65328 (64K – 8) .
Bit
31
...
16
15
14
13
..
3
2
1
0
unused, read as 0
unused, read as 0
RINGBUFFER_SAMPLE_LENGTH_BIT15*
RINGBUFFER_SAMPLE_LENGTH_BIT14*
RINGBUFFER_SAMPLE_LENGTH_BIT13
RINGBUFFER_SAMPLE_LENGTH_BIT3
“0”
“0”
“0”
The power up default value is 0
* only in conjunction with the mode of operation “Direct Memory Gate Asynchronous Mode”
Page 47 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.29 Ringbuffer Pre Delay register
#define SIS3350_RINGBUFFER_PRE_DELAY_ALL_ADC
#define SIS3350_RINGBUFFER_PRE_DELAY_ADC12
#define SIS3350_RINGBUFFER_PRE_DELAY_ADC34
0x01000024
0x02000024
0x03000024
This register defines the number of pre trigger delay samples in conjunction with all modes !
The maximum pretrigger delay is 16376 (16K – 8) .
Bit
31
...
14
13
..
1
0
unused, read as 0
unused, read as 0
RINGBUFFER_PRETRIGGER_DELAY_BIT13
RINGBUFFER_PRETRIGGER_DELAY_BIT1
“0”
The power up default value is 0
4.30 End Address Threshold registers
#define SIS3350_END_ADDRESS_THRESHOLD_ALL_ADC
0x01000004
#define SIS3350_END_ADDRESS_THRESHOLD_ADC12
#define SIS3350_END_ADDRESS_THRESHOLD_ADC34
0x02000004
0x03000004
These registers define the “End Address Threshold” values for the ADC channel groups.
The value of the Actual Next Sample address counter will be compared with value of the End
Address Threshold register.
The value is given in samples (i.e. number of 16-bit words)
Bit
31
...
24
23
..
2
1
0
unused, read as 0
unused, read as 0
Sample Start Address Register Bit 23
Sample Start Address Register Bit 2
unused, read as 0
unused, read as 0
The power up default value is 0
Page 48 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.31 Trigger setup register registers (0x02000030, 0x02000038, 0x03000030,
0x03000038)
#define
#define
#define
#define
SIS3350_TRIGGER_SETUP_ADC1
SIS3350_TRIGGER_SETUP_ADC2
SIS3350_TRIGGER_SETUP_ADC3
SIS3350_TRIGGER_SETUP_ADC4
0x02000030
0x02000038
0x03000030
0x03000038
These read/write registers hold the 8-bit wide trigger pulse length (in samples).
These read/write registers hold the Peaking and Gap Time of the trapezoidal FIR filter.
(Gap Time = SumG Time – Peaking Time)
Bit
Function
31
Reserved
..
..
26
Enable Trigger
25
GT trigger condition
24
FIR Trigger Mode
23
Puls Length bit 7
22
Puls Length bit 6
21
Puls Length bit 5
20
Puls Length bit 4
19
Puls Length bit 3
18
Puls Length bit 2
17
Puls Length bit 1
16
Puls Length bit 0
15
reserved
14
reserved
13
reserved
12
SumG bit 4
11
SumG bit 3
10
SumG bit 2
9
SumG bit 1
8
SumG bit 0
7
reserved
6
reserved
5
reserved
4
P bit 4
3
P bit 3
2
P bit 2
1
P bit 1
0
P bit 0
The power up default value reads 0x 00000000
Trigger Pulse Length
SumG time (only FIR trigger)
(time between both sums)
Peaking time P (only FIR trigger)
x+P
Si
i=x
Si:
Sum of ADC input sample stream from x to x+P
P:
Peaking time (number of values to sum)
SumG: SumGap time (distance in clock ticks of the two running sums)
The maximum SumG time:
The minimun SumG time:
Values > 16 will be set to 16
Value = 0 will be set to 1
16 (clocks)
1 (clocks)
The maximum Peaking time:
The minimun Peaking time:
Values > 16 will be set to 16
Value = 0 will be set to 1
16 (clocks)
1 (clocks)
Page 49 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.32 Threshold registers (0x02000034, 0x0200003C, 0x03000034, 0x0300003C)
#define
#define
#define
#define
SIS3350_TRIGGER_THRESHOLD_ADC1
SIS3350_TRIGGER_THRESHOLD_ADC2
SIS3350_TRIGGER_THRESHOLD_ADC3
SIS3350_TRIGGER_THRESHOLD_ADC4
0x02000034
0x0200003C
0x03000034
0x0300003C
These read/write registers hold the threshold values for the 4 ADC channels.
4.32.1 Threshold Trigger
Bit
Function
31-28
None
default after Reset:
27-16
none
15-12
None
11-0
Threshold value
0x0
A Trigger Output pulse is generated on two conditions:
GT is set (GT) in trigger setup register:
the Trigger Out Pulse will be issued if the actual sampled ADC value goes above the
threshold value
GT is cleared (LT) in trigger setup register:
the Trigger Out Pulse will be issued if the actual sampled ADC value goes below the
threshold value.
GT: greater than
LT: lower than
Page 50 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.32.2 Threshold FIR Trigger
Bit
Function
31-28
None
default after Reset:
27-16
none
15-0
Trapezoidal threshold value
0x0
The value of the Sum (trapezoidal value) depends on the peaking time P. Therefore the
selection of the value of the Trapezoidal threshold depends on P also.
Trapezoidal value calculation:
Trapezoidal value = (SUM2 – SUM1)
Where
x+P
Si
SUM1 =
i=x
x+P+sumG
SUM2 =
Sj
j = x+sumG
The FIR Filter logic generates the Trapezoidal by subtraction of the two running sums.
This implies, that the internal value of the trapezoid is on average 0.
A Trigger Output pulse is generated:
1GT is set (GT=1):
GT is set (GT):
the Trigger Out Pulse will be issued if the actual trapezoidal value goes above the
programmable trapezoidal threshold value
GT is cleared (LT):
the Trigger Out Pulse will be issued if the actual trapezoidal value goes below the
negative programmable trapezoidal threshold value
Page 51 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.32.3 Threshold Gate
Bit
Function
31-28
None
default after Reset:
27-16
Threshold value OFF
15-12
None
11-0
Threshold value ON
0x0
A valid Gate Output is generated on two conditions:
GT is set (GT) in trigger setup register:
the Gate output signal will be set if the actual ADC value goes above the programmable
threshold value ON and OFF and it is valid until the actual ADC value goes below the
threshold value OFF .
GT is cleared (LT) in trigger setup register:
the Gate output signal will be set if the actual ADC value goes below the programmable
threshold value ON and OFF and it is valid until the actual ADC value goes above the
threshold value OFF .
4.33 ADC Input tap delay registers (0x2000030, 0x2000034, 0x3000030
0x3000034)
Internal use only.
#define
#define
#define
#define
SIS3350_ADC_INPUT_TAP_DELAY_ADC1
SIS3350_ADC_INPUT_TAP_DELAY_ADC2
SIS3350_ADC_INPUT_TAP_DELAY_ADC3
SIS3350_ADC_INPUT_TAP_DELAY_ADC4
Page 52 of 79
0x02000040
0x02000044
0x03000040
0x03000044
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.34 VGA/gain registers (0x2000048, 0x200004C, 0x3000048 0x300004C)
These 4 read/write registers are used to set the gain of the four variable gain amplifiers
(VGA).
The VGA setting is 7-bit wide.
#define
#define
#define
#define
Bit
31
..
..
7
6
…
1
0
SIS3350_ADC_VGA_ADC1
SIS3350_ADC_VGA_ADC2
SIS3350_ADC_VGA_ADC3
SIS3350_ADC_VGA_ADC4
Write Function
None
..
..
None
VGA setting Bit 6
…
VGA setting Bit 1
VGA setting Bit 0
0x02000048
0x0200004C
0x03000048
0x0300004C
Read Function
0
..
..
0
VGA setting Bit 6
…
VGA setting Bit 1
VGA setting Bit 0
Note: The resulting ADC input range depends on stuffing options and the offset DAC setting.
Find below a coarse range table with default stuffing .
VGA setting
10
11
12
13
14
15
22
31
47
63
79
95
111
127
162
178
194
210
226
242
Input range in V
7,992
7,414
6,884
6,554
6,113
6,068
4,000
2,960
1,940
1,430
1,160
0,950
0,816
0,720
0,376
0,260
0,200
0,160
0,130
0,110
Note: The maximum input voltage is 8V
Page 53 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.35 ADC DAC Control Registers
This set of 4 registers is used to shift the input of the 4 ADC channels.
Example routine:
int sis3350_write_dac_offset(unsigned int module_dac_control_status_addr, unsigned int
dac_select_no, unsigned int dac_value )
;
The sequence to load the DACs can be found in section 4.16.3
Note: The actual sample registers provide a good way to monitor offset shift during a DAC
ramp
4.35.1 ADC DAC Control/Status registers (0x0x2000050, 0x0x3000050 read/write)
#define SIS3350_ADC12_DAC_CONTROL_STATUS
#define SIS3350_ADC34_DAC_CONTROL_STATUS
Bit
31
..
..
16
15
14
...
8
7
6
5
4
3
2
1
0
Write Function
None
..
..
None
None
None
None
None
None
None
DAC Selection Bit
..
none
DAC Command Bit 1
DAC Command Bit 0
DAC Selection Bit
Bit
0
1
Page 54 of 79
Function
ADC 1/3 respective
ADC 2/4 respective
0x02000050
0x03000050
/* read/write; D32 */
/* read/write; D32 */
Read Function
0
..
..
0
DAC Read/Write/Clear Cycle BUSY
0
...
0
0
0
0
status of DAC selection Bit
..
0
DAC Command Bit 1 Status
DAC Command Bit 0 Status
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.35.2 ADC DAC Data registers (0x0x2000054, 0x0x3000054 read/write)
#define SIS3350_ADC12_DAC_DATA
#define SIS3350_ADC34_DAC_DATA
0x02000054
0x03000054
/* read/write; D32 */
/* read/write; D32 */
These registers are used to hold the data send the offset DACs of the 4 ADC channels. The
DAC is selected via the DAC Selection Bit in the ADC DAC Control registers.
Bit
31
..
..
16
15
..
..
0
Write Function
none
..
..
none
DAC Output Register Bit 15
..
..
DAC Output Register Bit 0
Read Function
DAC Input Register Bit 15 (from DAC)
..
..
DAC Input Register Bit 0
DAC Output Register Bit 15
0
0
DAC Output Register Bit 0
Page 55 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.35.3 ADC Sample Counter TN setup register (0x2000070, 0x2000074,
0x20000078, 0x200007C, 0x3000070, 0x3000074, 0x30000078, 0x300007C
read/write)
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T2T1_ADC1
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T4T3_ADC1
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T2T1_ADC2
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T4T3_ADC2
0x02000070
0x02000074
0x02000078
0x0200007C
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T2T1_ADC3
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T4T3_ADC3
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T2T1_ADC4
#define SIS3350_SAMPLE_COUNTER_THRESHOLD_T4T3_ADC4
0x03000070
0x03000074
0x03000078
0x0300007C
Five 12-bit counters named T1 to T5 counter are implemented for the individual ADC
channel. The table below illustrates under which condition the 5 counters are incrementing
their content with every sampling clock tick. The output of the counter values to the event
data stream is activated by setting bit 0 (extra header enable bit) of the event configuration
register.
The thresholds T1 through T4 are defined in the ADC sample counter Tn/Tm registers as
shown in the table below..
Register
THRESHOLD_T2T1_ADCN
THRESHOLD_T4T3_ADCN
Counter
1
2
3
4
5
Bit [31:16]
Threshold T2
Threshold T4
Bit [15:0]
Threshold T1
Threshold T3
Count Condition
ADC value less than or equal T1
T1 < ADC value T2
T2 < ADC value T3
T3 < ADC value T4
T4 < ADC value 4095
4095
T4
T3
T2
T1
0
Samples
T1 Counter
Page 56 of 79
T2 Counter
T3 Counter
T4 Counter
T5 Counter
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.36 ADC memory
#define
#define
#define
#define
SIS3350_ADC1_OFFSET
SIS3350_ADC2_OFFSET
SIS3350_ADC3_OFFSET
SIS3350_ADC4_OFFSET
0x04000000
0x05000000
0x06000000
0x07000000
The 256 MByte ADC memory per channel can be address in pages of 16 MByte. The page is
selected with the ADC Memory page register. One 32-bit word holds 2 ADC samples as
shown in the table below.
4.36.1 Event Data format 1:
(used for all modes except “Direct Memory Trigger Stop Mode”)
31
16 15
0
0000
Timestamp [47:36]
0000
Timestamp [35:24]
0000
Timestamp [23:12]
0000
Timestamp [11:0]
0000
Information [47:36]
0000
Sample Length*[26:24]
0000
Sample Length* [23:12]
0000
Sample Length* [11:0]
ADC raw data buffer
sample 2
sample 1
sample 4
sample 3
sample N
sample N-1
N = Sample Length
Note: The data representation of the ADC is shown below
Digitized Value
0xFFF
…
0x000
Analog input voltage
Highest input voltage (+2.5 V e.g.)
Lowest input voltage (-2.5 V e.g.)
Page 57 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
4.36.2 Event Data format 2:
(used in “Direct Memory Trigger Stop Mode” only)
Information bit table_
Bit
Function
47
46
Wrap reserved
45-44
Stop delay counter
43-40
Trigger counter
39-36
Extra Header words
Trigger counter:
Counts the internal triggers.
Stop delay counter:
The Sample Stop Address stops on an 8 sample boundary.
With the help of the Stop delay counter (multipy by 2) it is possible to rearange the trigger
point.
see CVI/…./sis3350_configuration_readout_lib.c:
int rearange_WrapRawDataOneChannelAllEvents(….)
Page 58 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
Wrap (around) bit:
This bit is cleared at start of sampling and it is set when the number of samples reached the
value of the Sample Wrap Length register.
See also “Direct Memory Stop Mode Sample Wrap Length register”.
Wrap = 0: data are only valid from offset 0 to (Sample_Stop_Addr – 2).
4.36.3 Extra Header
An extra header consisting of four 32-bit words is generated with bit 0 of the event
configuration register set to 1. The extra header holds the 12-bit wide T1-T5 counter
information as illustrated below.
Page 59 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
5 Board layout
A printout of the silk screen of the component side of the PCB is shown below.
Page 60 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6 Front panel
The SIS3350 is a single width (4TE) 6U VME module. A sketch of the SIS3350 front panel
(without handles) is shown below.
Trigger In (programmable threshold)
Trigger Out (NIM)
Page 61 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.1 Control In/Outputs
6.1.1 Trigger (Gate) Lemo input
The trigger (gate) input is a LEMO00 connector (CON60A) with programmable threshold
level. The programmable threshold level range is from -2.75V to +4.0V and an input
impedance of 50 Ohm.
6.1.2 Trigger (Gate) Lemo output
The trigger (gate) output is a LEMO00 connector (CON70A) with NIM logic level.
Page 62 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.1.3 Clock BNC input
The clock input is a BNC connector (CON50A) with programmable threshold level.
The programmable threshold level range is from -2.75V to +4.0V and the input impedance is
50 Ohm.
Page 63 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.1.4 Clock BNC output
The clock output signal is available on a BNC connector for diagnosis purposes.
The output level in DC-coupling mode is 300mVpp and the offset is DC 1.1V into 50 Ohm
termination.
The output level in AC-coupling mode is 560mVpp without an offset into 50 Ohm
termination.
DC coupling mode
(R700G stuffed with 50 Ohm resistor)
DC coupling is factory default
Note: the footprint of R700G is 0603
Page 64 of 79
AC coupling mode
(R700G stuffed with 100 nF capacitor)
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.1.5 LVDS in/output
The control I/O section features one HDMI connector with LVDS levels.
PIN
1
2
3
4
5
6
Input Signal
EXTERN_CONTROL1_LVDS_IN_L
DGND
EXTERN_CONTROL1_LVDS_IN_H
EXTERN_CONTROL2_LVDS_IN_L
DGND
EXTERN_CONTROL2_LVDS_IN_H
Function
PIN
7
8
9
10
11
12
13
14
15
16
17
18
..
23
Output Signal
EXTERNAL_CONTROL1_LVDS_OUT_H
DGND
EXTERNAL_CONTROL1_LVDS_OUT_L
EXTERNAL_CONTROL2_LVDS_OUT_H
DGND
EXTERNAL_CONTROL2_LVDS_OUT_L
Function
EXTERNAL_CONTROL3_LVDS_OUT_H
EXTERNAL_CONTROL3_LVDS_OUT_L
DGND
N/C
..
N/C
BUSY Output
Clock Input
Trigger (Gate) Input
Clock Output
Trigger (Gate) Output
Page 65 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.2 LED's
The SIS3350 has 6 front panel LEDs to visualise part of the modules status. The access LED
is a good way to check first time communication/addressing with the module.
Color
Yellow
Red
Green
Yellow
Red
Green
Designator
A
P
R
U1
U2
U3
Function
Access to SIS3350 VME slave port
Power
Ready, on board logic configured
Sample Logic armed
Sample Logic Busy
User, to be set/cleared under program control
The on duration of the access, sample logic armed and sample logic busy LEDs is stretched to
guarantee visibility even under low rate conditions.
6.3 Channel LED's L1-L4
The 4 card edge surface mounted LEDs L1, ..., L4 can be seen through the corresponding
holes in the front panel. They visualize the trigger status of the corresponding channel. The on
duration is stretched for better visibility of short pulses.
Page 66 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
6.4 PCB LEDs
Surface mounted red LEDs are used to signal power status, trigger status and FPGA debug
information (the use of the debug LEDs is firmware design dependent).
A table with the SMD LEDs is given below.
Designator
D140A
D140B
D140C
D140D
D140E
D140F
D140G
D140H
D141A
D141B
D141C
D141D
D141E
D141F
D141G
D141H
D300A
D301A
D309A
D309B
D400A
D410A
D500B
D600B
Function
Front panel trigger LED L1
Front panel trigger LED L2
Front panel trigger LED L3
Front panel trigger LED L4
VME_FPGA_DEBUG_INTERN_LED1
VME_FPGA_DEBUG_INTERN_LED2
VME_FPGA_DEBUG_INTERN_LED3
VME_FPGA_DEBUG_INTERN_LED4
FPGA1_DEBUG_INTERN_LED1
FPGA1_DEBUG_INTERN_LED2
FPGA1_DEBUG_INTERN_LED3
FPGA1_DEBUG_INTERN_LED4
FPGA2_DEBUG_INTERN_LED1
FPGA2_DEBUG_INTERN_LED2
FPGA2_DEBUG_INTERN_LED3
FPGA2_DEBUG_INTERN_LED4
Power D+2.5V
Power D+3.3V
Power_Fault_Sequencer
Power_Sequence_OK
Power A+12V
Power A-12V
Power D+1,8V
Power D+1,2V
Page 67 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
7 Jumpers/Configuration
7.1 JP80 VME addressing mode/reset behaviour
This 8 position jumper array is used to select the addressing mode and the reset behaviour of
the SIS3350.
Pos
1
2
3
4
5
6
7
8
Function
A32
A16 (not supported)
GEO (not supported)
VIPA (not supported)
connect VME SYSRESET IN to FPGA reset
unused
unused
connect VME SYSRESET to board reset
Factory default
closed
open
open
open
closed
open
open
closed
The enable watchdog jumper has to be removed during (initial) JTAG firmware load.
NOTE: avoid a power up deadlock situation by not setting Pos. 5 and 8 at the same time
7.2 CON100B JTAG
The SIS3350 on board logic can load its firmware from a serial PROMs , via the JTAG port
on connector CON100B or over VME. A list of firmware designs can be found under
http://www.struck.de/sis3350firm.htm.
Hardware like the HW-USB-II-G-JTAG in connection with the appropriate software will be
required for in field JTAG firmware upgrades. The JTAG chain configuration is selected with
jumper JP101, Xilinx JTAG control register is used to select VME or CON100B as JTAG
source.
CON100B is a 2mm (i.e. metric) 14 pin header that allows you to reprogram the firmware of
the SIS3350 with a JTAG programmer. The pinout is shown in the schematic below. It is
compatible with the cable that comes with the XILINX HW-USB platform cable.
Note: The SIS3350 has to be powered for reprogramming over JTAG.
Page 68 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
7.3 JP101 JTAG chain
The JTAG chain on the SIS3350 can be configured to comprise the serial PROM only (short
JTAG chain) or to comprise the serial PROM and the 3 Virtex FPGAs (long chain). The
configuration is selected with the 6-pin array JP101 as sketched below:
Long Chain (1-3 and 2-4 closed):
JP101
In the Impact software you will see:
Short Chain (3-5 and 4-6 closed, factory default):
JP101
In the Impact software you will see:
Page 69 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
7.4 SW1 and SW2, VME base address
These 2 rotary switches are used to define 2 nibbles of the VME base address in non
geographical addressing (refer to section base address also).
Switch
SW1
SW2
Function
ADR_LO
ADR_UP
7.5 JTAG source
The JTAG chain can be connected to VME or to the JTAG connector CON100B
The source is programmable via the XILINX JTAG Control register
Page 70 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
8 Getting started
The directory SIS3350\software of the Struck Innovative Systeme DVD holds example code
for VisualC++ and National Instruments Labwindows CVI. The source code can be used as a
base for ports to other environments.
The SIS3350.h header file can be found in the directory SIS3350\software.
The routine ConfigurationSetup_SIS3350_Adc(void) in the file
SIS3350_adc_test1.c (CVI directory) can be used as starting point for a setup routine
for the SIS3350.
8.1 SIS3350 base program
The runtime version of the SIS3350 base program in combination with a SIS3150 USB to
VME interface provides access to all implemented SIS3350 features without the need for
coding in the first step under Windows. Feel free to inquire about the possibility for a loaner
in case you are working with another VME master.
An example screen shot of the SIS3350 base program (a signal acquired in ring buffer
synchronous mode of operation).
Page 71 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
8.2 SIS3350 visual start
A minimum VisualC++ program to see first data can be found in the directory
software\visual\application
The board is set up without VGA and DAC setting, what results in an input range of about
-2.5, …,+2.5 V and operated in VME triggered mode in the example. Typical screen output is
shown below.
Page 72 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
9 Appendix
9.1 Power consumption
The SIS3350 uses standard VME voltages only.
Voltage
+ 5V
+12 V
- 12 V
Current
9A
100 mA
400 mA
9.2 Operating conditions
9.2.1 Cooling
Although the SIS3350 is mainly a 2.5 and 3.3 V low power design, substantial power is
consumed by the Analog to Digital converter chips and linear regulators however. Hence
forced air flow is required for the operation of the board. The board may be operated in a non
condensing environment at an ambient temperature between 10 and 25 Celsius. A power up
warm up time of some 10 minutes is recommended to ensure equilibrium on board
temperature conditions.
9.2.2 Hot swap/live insertion
Please note, that the VME standard does not support hot swap by default. The SIS3350 is
configured for hot swap in conjunction with a VME64x backplane. In non VME64x
backplane environments the crate has to be powered down for module insertion and removal.
Page 73 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
9.3 Connector types
The table below lists the connectors used on the SIS3350.
Connector/Purpose
Analog in 1-4
Ethernet
External Clock
JTAG
LVDS bus
Optical Link
Trigger input
Trigger output
VME (P1/P2) 160 pin zabcd
Part number
Tyco 5413631-1
HFJ11-1G01E-L12RL
Tyco 5413631-1
87831-1420
HDMI-19-02-S-SM-R
FTLF8524E2KNL
EPL.00.250.NTN
EPL.00.250.NTN
02 01 160 2101
Manufacturer
TYCO
HALO
TYCO
Molex
SAMTEC
FINISAR
LEMO
LEMO
HARTING
9.4 P2 row A/C pin assignments
The P2 connector of the SIS3350 has several connections on rows A and C for the F1002
compatible use at the DESY H1 FNC subdetector. This implies, that the module can not be
operated in a VME slot with a special A/C backplane, like VSB e.g.. The pin assignments of
P2 rows A/C of the SIS3350 is shown below:
P2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
...
31
Function
not connected
not connected
not connected
not connected
not connected
DGND
P2_CLOCK_H
DGND
P2_START_H
P2_STOP_H
P2_TEST_H
DGND
DGND
not connected
not connected
not connected
...
not connected
P2C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Function
not connected
not connected
not connected
not connected
not connected
DGND
P2_CLOCK_L
DGND
P2_START_L
P2_STOP_L
P2_TEST_L
DGND
DGND
not connected
not connected
not connected
...
not connected
Note: The P2 ECL signals are bussed and terminated on the backplane of F1002 crates. The
user has to insure proper termination if a cable backplane or add on backplane is used.
Page 74 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
9.5 Row d and z Pin Assignments
The SIS3350 is prepared for the use with VME64x and VME64xP backplanes. Foreseen
features include geographical addressing and live insertion (hot swap). The prepared pins on
the d and z rows of the P1 and P2 connectors are listed below.
Position
P1/J1
Row z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
P2/J2
Row d
VPC (1)
GND (1)
Row z
GND
GND
GND
GND
GND
GND
GND
RESP*
GND
Row d
GND
GAP*
GA0*
GA1*
GND
GND
GA2*
GND
GND
GA3*
GND
GND
GA4*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND (1)
VPC (1)
GND
GND (1)
VPC (1)
Note: Pins designated with (1) are so called MFBL (mate first-break last) pins on the installed 160 pin
connectors, VPC(1) pins are connected via inductors.
Page 75 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
9.6 Firmware upgrade
The firmware of the SIS3350 can be upgraded over JTAG. The upgrade options are VME (on
units that have intact firmware) and the JTAG connector CON100. The VME upgrade option
is not tested for the current firmware release yet.
9.6.1 Upgrade over CON100
The firmware can be upgraded with the Xilinx Impact software, which is part of the Webpack
that can be downloaded from the Xilinx web page for free.
A Xilinx JTAG parallel cable or USB (Xilinx part number HW-USB) cable can be used to
roll in the firmware.
Configure the SIS3350 for short JTAG chain (refer to section 7.3 JP101). CON 100 is JTAG
source by default (unless programmed for VME with the Xilinx JTAG control register.
With your hard- and software properly set up you should see a screen as illustrated below
after executing the initialize chain command.
Load the mcs file to the serial PROM (shown as xcf32p).
9.6.2 Upgrade over VME
Not supported with current SIS3350 firmware yet (i.e. JTAG source hard coded to CON100)
Page 76 of 79
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
10 Index
0603 .................................................................. 64
2eVME................................................................ 6
4TE ................................................................5, 61
6U ..................................................................5, 61
A/C ..................................................................... 6
A16 ................................................................... 16
A32 ................................................................6, 16
AD5570............................................................. 38
AD7314............................................................. 40
Address Map ..................................................... 17
address space ..................................................... 16
addressing
geographical .................................................... 6
arm......................................................... 17, 42, 45
AT85AS001 ...................................................... 41
backplane .......................................................6, 73
BLT32................................................................. 6
board layout....................................................... 60
broadcast
address........................................................... 32
CBLT ................................................................ 31
clock.................................................................... 6
external BNC............................................14, 26
external LVDS..........................................14, 26
external random ............................................... 6
frequency synthesizer................................14, 26
internal .......................................................... 14
clock input......................................................... 63
clock mode ........................................................ 27
clock output ....................................................... 64
clock source............................................ 14, 25, 26
Clock/Trigger DAC data .................................... 37
CON100 ............................................................ 76
CON100B.......................................................... 68
configuration ..................................................... 68
connector............................................................. 6
connector types.................................................. 74
control
input .............................................................. 14
output ............................................................ 62
control input ...................................................... 62
cooling .............................................................. 73
counter
stop delay ...................................................... 58
trigger............................................................ 58
Counter.............................................................. 56
crate .................................................................... 5
CVI ................................................................... 71
D32 ..................................................................... 6
DAC.................................................................5, 6
ADC.............................................................. 54
clock.............................................................. 36
load sequence................................................. 38
offset ............................................................. 53
selection bit...............................................54, 55
trigger............................................................ 36
data format ...................................................57, 58
data representation ............................................. 57
DESY ................................................................ 74
DO8................................................................... 23
duty cycle .......................................................... 41
DVD.................................................................. 71
edge
leading ........................................................... 14
trailing ........................................................... 14
extra header ....................................................... 59
FIR
trigger .............................................................. 6
FIR trigger ......................................................... 14
firmware ............................................................ 68
firmware upgrade............................................... 76
FNC................................................................... 74
format.......................................................... 57, 58
FPGA ............................................................ 8, 10
frequency range.................................................. 28
frequency synthesizer......................................... 26
front panel ..................................................... 6, 61
GA..................................................................... 16
gain ................................................................... 53
gate.................................................................... 12
gate chaining...................................................... 12
gate input ........................................................... 62
gate mode .......................................................... 14
gate output ......................................................... 62
geographical addressing ..................................... 75
getting started .................................................... 71
GND.................................................................. 68
H1 ..................................................................... 74
HDMI .......................................................... 14, 65
header................................................................ 59
hot swap ...................................................... 73, 75
HW-USB ..................................................... 68, 76
input
clock ........................................................ 63, 65
control ........................................................... 62
gate................................................................ 62
LVDS ............................................................ 65
trigger ............................................................ 62
trigger (gate) .................................................. 65
input range......................................................... 53
internal trigger ................................................... 25
interrupter mode................................................. 23
interrupter type................................................... 23
introduction ......................................................... 5
Invert Bit for external Lemo TRG IN............ 20, 21
IRQ
bank full......................................................... 24
End Address Threshold .................................. 24
end of event ................................................... 24
IRQ mode .......................................................... 23
ROAK ........................................................... 23
RORA............................................................ 23
J/K..................................................................... 25
JP101........................................................... 68, 69
Page 77 of 79
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SIS3350
500 MHz 12-bit Digitizer
JP80 .............................................................16, 68
JTAG ...........................................................68, 76
JTAG chain ....................................................... 69
JTAG source...................................................... 70
jumper
reset............................................................... 68
KA
arm sampling ................................................. 42
disarm sampling............................................. 42
general reset................................................... 42
Timestamp Clear............................................ 42
Trigger........................................................... 42
key address...................................................17, 32
L1...................................................................... 66
LC-LC................................................................. 5
LED
A 66
access ............................................................ 66
P 66
PCB............................................................... 67
R 66
U1 ................................................................. 66
U2 ................................................................. 66
U3 ................................................................. 66
user................................................................ 20
LEDs
channel .......................................................... 66
front panel ..................................................... 66
PCB............................................................... 67
live insertion.................................................73, 75
LVDS input ....................................................... 65
LVDS output ..................................................... 65
M 49
MBLT64 ........................................................6, 19
memory ................................................ 6, 8, 19, 57
internal handling .............................................. 9
mode
start/stop ........................................................ 14
module design...................................................... 7
Multi Event mode .............................................. 26
N Divider .......................................................... 28
NIM .................................................................. 37
offset DAC ........................................................ 53
operating conditions........................................... 73
operation mode .................................................. 26
operation modes................................................. 10
output
busy............................................................... 65
clock.........................................................64, 65
gate................................................................ 62
LVDS ............................................................ 65
trigger.......................................................14, 62
trigger (gate) .................................................. 65
P 49
P1...................................................................... 75
P2...................................................................6, 75
pin assignments.............................................. 74
termination .................................................... 74
PCI Express......................................................... 5
power consumption............................................ 73
Page 78 of 79
programmable.................................................... 70
PROM ......................................................... 68, 76
R700G ............................................................... 64
register
acquisition control.......................................... 25
actual address register..................................... 46
actual sample ................................................. 54
ADC DAC control.................................... 54, 55
ADC DAC data .............................................. 55
ADC IOB delay.............................................. 52
ADC memory page................................... 33, 57
ADC Sample Counter setup............................ 56
ADC serial interface....................................... 41
broadcast setup............................................... 32
CBLT/broadcast setup.................................... 31
Clock /Trigger DAC control ........................... 36
Clock/Trigger DAC control ............................ 36
control ........................................................... 22
DAC status..................................................... 36
description ..................................................... 20
direct memory sample length.......................... 27
end address threshold ..................................... 48
event configuration................................... 43, 56
firmware revision ........................................... 22
frequency synthesizer ..................................... 27
gate synch mode event extend length register.. 30
gate synch mode event length limit register..... 30
interrupt configuration.............................. 23, 24
JTAG_CONTROL ......................................... 39
JTAG_DATA_IN........................................... 39
JTAG_TEST. ................................................. 39
module Id....................................................... 22
MultiEvent event counter ............................... 29
MultiEvent max nof events............................. 29
ringbuffer pretrigger delay.............................. 48
ringbuffer sample length................................. 47
sample start address........................................ 45
sample wrap length................................... 44, 59
temperature .................................................... 40
threshold ........................................................ 50
trigger delay................................................... 27
Trigger output select....................................... 35
trigger setup ........................................49, 50, 52
VGA/gain ...................................................... 53
Xilinx JTAG control................................. 68, 76
reset................................................................... 68
ROAK ............................................................... 23
RORA ............................................................... 23
serial PROM ...................................................... 69
SFF...................................................................... 5
SIS1100-eCMC.................................................... 5
SIS3150USB...................................................... 71
SIS3300............................................................... 5
SIS3350............................................................... 5
SIS3350 base program ....................................... 71
SIS3350 visual start ........................................... 72
sparsify.............................................................. 12
SPI..................................................................... 17
SW1 ............................................................ 16, 70
SW2 ............................................................ 16, 70
SIS Documentation
SIS3350
500 MHz 12-bit Digitizer
T1.................................................................56, 59
counter........................................................... 59
T2...................................................................... 56
T3...................................................................... 56
T4...................................................................... 56
T5...................................................................... 56
TCK .................................................................. 68
TDI ..............................................................39, 68
TDO.................................................................. 68
Technical Properties/Features............................... 6
termination
P2.................................................................. 74
threshold............................................................ 14
TMS.............................................................39, 68
trigger
FIR .............................................................6, 14
post................................................................ 14
pre ................................................................. 14
trigger control .................................................... 14
trigger generation............................................... 14
trigger input ....................................................... 62
trigger output ..................................................... 62
TTL................................................................... 37
USB................................................................... 68
user
LED............................................................... 20
VCC .................................................................. 68
VGA...........................................................5, 6, 53
Virtex ................................................................ 69
VME.................................................................. 73
interrupt ......................................................... 15
VME addressing ................................................ 16
VME bus ............................................................. 5
VME64x............................................... 5, 6, 73, 75
VME64xP.......................................................... 75
VSB............................................................... 6, 74
wrap ............................................................ 44, 59
wrap bit ............................................................. 59
XILINX ............................................................. 68
Page 79 of 79
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