USER`S MANUAL ERRATA

USER'S MANUAL ERRATA

This document contains the corrections of errors, typos and omissions in the following document.

Samsung 8-bit CMOS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Microprocessor User's Manual

Document Number: 21.1-S3-C80A4/C80A8/C80A5/C80B4/C80B8/C80B5-082005

Publication: August 2005

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 USER’S MANUAL ERRATA

ERRATA (

VER 1.1)

Samsung 8-bit CMOS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Microprocessor User’s Manual

Document Number: 21.1-S3-C80A4/C80A8/C80A5/C80B4/C80B8/C80B5-082005

Publication: August 2005

1. FEATURES (PAGE 1-2)

Operating Temperature Range

•

–25

°

C to + 85

°

C

Operating Voltage Range

•

S3C80B4/C80B8/C80B5

1.7 V to 3.6 V at 4 MHz f

OSC

•

S3C80A4/C80A8/C80A5


OSC

2. TABLE 13-1. ABSOLUTE MAXIMUM RATINGS (PAGE 13-2)

(T

A

= 25

°

C)

Parameter

Operating temperature

Symbol

T

A

Conditions

–

Rating

– 25 to + 85

Unit

°

C

1

USER’S MANUAL ERRATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

3. Table 13-2. D.C. Electrical Characteristics (PAGE 13-2)

(T

A

= – 25

°

C to + 85

°

C, V

DD

= 1.7V( 2.0 V) to 3.6V( 5.5 V))

Parameter

Operating voltage

Output high voltage

Symbol

V

DD

V

OH1

V

OH2

V

OH3

Conditions

S3C80A4/C80A8/C80A5 f

OSC

= 8 MHz

(Instruction clock = 1.33 MHz)

S3C80B4/C80B8/C80B5 f

OSC

= 4 MHz


V

DD

= 2.4 V, I

OH

= – 6 mA

Port 2.1 only

V

DD

= 2.4 V, I

OH

= – 2.2mA

Port 2.0, 2.2

V

DD

= 2.4 V, I

OH

= – 1 mA

All output pins except Port2

Min

2.0

1.7

V

DD

– 0.7

V

DD

-

0.7

V

DD

-

1.0

Typ

–

–

–

–

Max

5.5

3.6

–

–

Unit

V

V

NOTE: S3C80A4/C80A8/C80A5 ‘s operating voltage : 2.0V~5.5V.

S3C80B4/C80B8/C80B5 ‘s operating voltage : 1.7V~3.6V.

4. Table 13-2. D.C. Electrical Characteristics (PAGE 13-3)

(T

A

= – 25

°

C to + 85

°

C, V

DD

= 1.7V( 2.0 V) to 3.6V( 5.5 V))

Parameter

Output low voltage

Supply current

(note)

Symbol

V

OL1

V

V

I

I

I

OL2

OL3

DD1

DD2

DD3

Conditions

V

DD

= 2.4 V, I

OL

= 12 mA, port

2.1 only

V

DD

= 2.4 V, I

OL

= 5 mA

Port 2.0,2.2

I

OL

= 1 mA

Ports 0 and 1

V

DD

= 5.5 V

8-MHz crystal

4-MHz crystal, V

DD

= 3.6 V

Idle mode;

V

DD

= 5.5 V

8-MHz crystal

4-MHz crystal, V

DD

= 3.6 V

Stop mode; T

A

= 25

°

C

V

DD

= 3.6V (5.5V)

Min

–

–

–

–

Typ

0.4

0.4

0.4

5

2.6

2

0.7

1

Max

0.5

0.5

1.0

9

5

4

2.0

6

Unit

V mA mA uA

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.

2. S3C80A4/C80A8/C80A5 ‘s operating voltage : 2.0V~5.5V.


2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 USER’S MANUAL ERRATA

5. Table 13-3. Characteristics of Low Voltage Detect circuit (PAGE 13-4)

(T

A

= 25

°

C)

6. Table 13-4. Data Retention Supply Voltage in Stop Mode (PAGE 13-4)

(T

A

= – 25

°

C to + 85

°

C)

Parameter

Data retention supply voltage

Symbol

V

DDDR

Conditions

–

Min

1.0

Typ

–

Max

3.6

(5.5V)

Unit

V

7. Table 13-5. Input/output Capacitance (PAGE 13-4)

(T

A

= – 25

°

C to + 85

°

C, V

DD

= 0 V)

8. Table 13-6. A.C. Electrical Characteristics (PAGE 13-4)

(T

A

= – 25

°

C to + 85

°

C)

Parameter

Interrupt input, High,

Low width

Symbol

t

INTH

, t

INTL

Conditions

P0.0–P0.7, V

DD

=

3.6

V

(5.5V)

Min

200

Typ

300

Max

–

Unit

ns

3

USER’S MANUAL ERRATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

9. Table 13-7. Oscillation Characteristics (PAGE 13-5)

(T

A

= – 25

°

C + 85

°

C)

Oscillator

Crystal

Clock Circuit

C1

X

IN

Conditions

CPU clock oscillation frequency

Ceramic

C2

C1

X

OUT

XT

IN


External clock

C2

External

Clock

Open Pin

XT

OUT

X

IN

X

IN input frequency

X

OUT

NOTES :

1. S3C80A4/C80A8/C80A5 ‘s operating frequency : 1~8 MHz.

2. S3C80B4/C80B8/C80B5 ‘s operating frequency : 1~4 MHz.

10. Table 13-8. Oscillation Stabilization Time (PAGE 13-6)

(T

A

= – 25

°

C + 85

°

C, V

DD

= 3.6 V (5.5V))

Min

1

1

Typ

–

–

Max

8

(1)

4

(2)

Unit

MHz

1

1

1

1

–

–

–

–

8

(1)

4

(2)

MHz

8

(1)

4

(2)

MHz

4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

11. Figure 13-2. Operating Voltage Range (PAGE 13-6)

USER’S MANUAL ERRATA

Instruction

Clock

1.33 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

A

B

Instruction

Clock

8 MHz

6 MHz

4 kHz

8.32 kHz 400 kHz

1 2 3 4 5 6 7

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

A 1.7 V: 4 MHz (S3C80B4/C80B8/C80B5)

B 2.0 V: 8 MHz (S3C80A4/C80A8/C80A5)

5

S3C80A4/C80A8/C80A5/

C80B4/C80B8/C80B5

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1.1

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 8-Bit CMOS Microcontrollers

User's Manual, Revision 1.1

Publication Number: 21.1-S3C-80A4/C80A8/C80A5/C80AB4/C80B8/C80B5-082005

© 2005 Samsung Electronics

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and

objectives.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Kiheung-Gu

Yongin-City, Kyunggi-Do, Korea

C.P.O. Box #37, Suwon 446-711

TEL: (82)-(31)-209-5238

FAX: (82)-(31)-209-6494

Home-Page URL: Http://www.intl.samsungsemi.com

Printed in the Republic of Korea

"Typical" parameters can and do vary in different applications. All operating parameters, including

"Typicals" must be validated for each customer application by the customer's technical experts.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the

Samsung product could create a situation where personal injury or death may occur.

Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold

Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that

Samsung was negligent regarding the design or manufacture of said product.

Preface

The S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 microcontroller for application development. It is organized in two main parts:

Part I Programming Model Part II Hardware Descriptions

Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:

Chapter 1

Chapter 2

Chapter 3

Product Overview

Address Spaces

Addressing Modes

Chapter 4

Chapter 5

Chapter 6

Control Registers

Interrupt Structure

Instruction Set

Chapter 1, "Product Overview," is a high-level introduction to S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the

S3C8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in

Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part

II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters

4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 microcontroller. Also included in Part II are electrical, mechanical,

OTP, and development tools data. It has eight chapters:

Chapter 7

Chapter 8

Chapter 9

Chapter 10

Clock Circuit

RESET and Power-Down

I/O Ports

Basic Timer and Timer 0

Chapter 11

Chapter 12

Chapter 13

Chapter 14

Timer 1

Counter A

Electrical Data

Mechanical Data

Two order forms are included at the back of this manual to facilitate customer order for

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 microcontrollers: the Mask ROM Order Form, and the Mask Option

Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales

Representative.

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER iii

Table of Contents

Part I — Programming Model

Chapter 1 Product Overview

Overview .............................................................................................................................................1-1

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 Microcontroller..............................................................1-1

Features .............................................................................................................................................1-2

CPU...................................................................................................................................................1-2

Block Diagram ....................................................................................................................................1-3

Pin Assignments.................................................................................................................................1-4

Pin Descriptions ..................................................................................................................................1-5

Pin Circuits.........................................................................................................................................1-6

Chapter 2 Address Spaces

Overview .............................................................................................................................................2-1

Program Memory (ROM) ......................................................................................................................2-2

Register Architecture ...........................................................................................................................2-3

Register Page Pointer (PP) ..........................................................................................................2-5

Register Set 1.............................................................................................................................2-6

Register Set 2.............................................................................................................................2-6

Prime Register Space..................................................................................................................2-7

Working Registers .......................................................................................................................2-8

Using The Register Pointers .........................................................................................................2-9

Register Addressing ............................................................................................................................2-11

Common Working Register Area (C0H–CFH) .................................................................................2-13

4-Bit Working Register Addressing................................................................................................2-14

8-Bit Working Register Addressing................................................................................................2-16

System and User Stacks .....................................................................................................................2-18

Chapter 3 Addressing Modes

Overview .............................................................................................................................................3-1

Register Addressing Mode (R) ......................................................................................................3-2

Indirect Register Addressing Mode (IR)..........................................................................................3-3

Indexed Addressing Mode (X) .......................................................................................................3-7

Direct Address Mode (DA)............................................................................................................3-10

Indirect Address Mode (IA)...........................................................................................................3-12

Relative Address Mode (RA).........................................................................................................3-13

Immediate Mode (IM) ...................................................................................................................3-14

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER v


(Continued)

Chapter 4 Control Registers

Overview .............................................................................................................................................4-1

Chapter 5 Interrupt Structure

Overview .............................................................................................................................................5-1

Interrupt Types ............................................................................................................................5-2

Interrupt Structure........................................................................................................................5-3

Interrupt Vector Addresses ...........................................................................................................5-5

Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-7

System-Level Interrupt Control Registers .......................................................................................5-7

Interrupt Processing Control Points ...............................................................................................5-8

Peripheral Interrupt Control Registers ............................................................................................5-9

System Mode Register (SYM) ......................................................................................................5-10

Interrupt Mask Register (IMR) .......................................................................................................5-11

Interrupt Priority Register (IPR) .....................................................................................................5-12

Interrupt Request Register (IRQ) ...................................................................................................5-14

Interrupt Pending Function Types ..................................................................................................5-15

Interrupt Source Polling Sequence ................................................................................................5-16

Interrupt Service Routines.............................................................................................................5-16

Generating Interrupt Vector Addresses ..........................................................................................5-17

Nesting of Vectored Interrupts.......................................................................................................5-17

Instruction Pointer (IP) .................................................................................................................5-17

Fast Interrupt Processing .............................................................................................................5-17

Chapter 6 Instruction Set

Overview .............................................................................................................................................6-1

Data Types .................................................................................................................................6-1

Register Addressing ....................................................................................................................6-1

Addressing Modes.......................................................................................................................6-1

Flags Register (FLAGS)...............................................................................................................6-6

Flag Descriptions ........................................................................................................................6-7

Instruction Set Notation................................................................................................................6-8

Condition Codes ..........................................................................................................................6-12

Instruction Descriptions................................................................................................................6-13

vi S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER


(Continued)

Part II Hardware Descriptions

Chapter 7 Clock Circuit

Overview .............................................................................................................................................7-1

System Clock Circuit...................................................................................................................7-1

Clock Status During Power-Down Modes .......................................................................................7-2

System Clock Control Register (CLKCON).....................................................................................7-3

Chapter 8 RESET and Power-Down

System Reset .....................................................................................................................................8-1

LVD Reset ..................................................................................................................................8-1

Interrupt with Reset (INTR)............................................................................................................8-2

Watch-Dog Timer Reset ...............................................................................................................8-2

Power-on Reset (POR).................................................................................................................8-2

System Reset Operation..............................................................................................................8-3

Hardware Reset Values................................................................................................................8-4

Power-Down Modes .............................................................................................................................8-6

Stop mode..................................................................................................................................8-6

Using POR to Release Stop Mode ................................................................................................8-6

Using an INTR to Release Stop Mode............................................................................................8-6

Idle Mode....................................................................................................................................8-9

Summary Table of Stop Mode, and Idle Mode ................................................................................8-10

Chapter 9 I/O Ports

Overview .............................................................................................................................................9-1

Port Data Registers .....................................................................................................................9-2

Pull-Up Resistor Enable Registers ................................................................................................9-2

Port 0.........................................................................................................................................9-3

Port 0 Interrupt Enable Register (P0INT) ........................................................................................9-4

Port 0 Interrupt Pending Register (P0PND).....................................................................................9-4

Port 1.........................................................................................................................................9-6

Port 2.........................................................................................................................................9-8

Chapter 10 Basic Timer and Timer 0

Module Overview..................................................................................................................................10-1

Basic Timer Control Register (BTCON) ..........................................................................................10-1

Basic Timer Function Description..................................................................................................10-3

Timer 0 Control Register (T0CON) .................................................................................................10-3

Timer 0 Function Description ........................................................................................................10-5

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER vii


(Concluded)

Chapter 11 Timer 1

Overview .............................................................................................................................................11-1

Timer 1 Overflow Interrupt .............................................................................................................11-2

Timer 1 Match Interrupt ................................................................................................................11-2

Timer 1 Control Register (T1CON) .................................................................................................11-4

Chapter 12 Counter A

Overview .............................................................................................................................................12-1

Counter A Control Register (CACON) ............................................................................................12-3

Counter A Pulse Width Calculations..............................................................................................12-4

Chapter 13 Electrical Data

Overview .............................................................................................................................................13-1

Chapter 14 Mechanical Data

Overview .............................................................................................................................................14-1

viii S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER

Figure

Number

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

2-9

2-10

2-11

2-12

2-13

2-14

2-15

3-9

3-10

3-11

3-12

3-13

3-14

4-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

1-1

1-2

1-3

1-4

1-5

1-6

1-7

List of Figures

Title Page

Number

Block Diagram ....................................................................................................1-3

Pin Assignment Diagram (24-Pin SOP/SDIP Package) ...........................................1-4

Pin Circuit Type 1 (Port 0) ....................................................................................1-6

Pin Circuit Type 2 (Port 1) ....................................................................................1-7

Pin Circuit Type 3 (P2.0) ......................................................................................1-7



Program Memory Address Space .........................................................................2-2

Internal Register File Organization.........................................................................2-4

Register Page Pointer (PP) ..................................................................................2-5

Set 1, Set 2, and Prime Area Register Map ...........................................................2-7

8-Byte Working Register Areas (Slices).................................................................2-8

Contiguous 16-Byte Working Register Block..........................................................2-9

Non-Contiguous 16-Byte Working Register Block ...................................................2-10

16-Bit Register Pair .............................................................................................2-11

Register File Addressing ......................................................................................2-12

Common Working Register Area...........................................................................2-13

4-Bit Working Register Addressing........................................................................2-15

4-Bit Working Register Addressing Example..........................................................2-15

8-Bit Working Register Addressing........................................................................2-16

8-Bit Working Register Addressing Example..........................................................2-17

Stack Operations ................................................................................................2-18

Register Addressing ............................................................................................3-2

Working Register Addressing ...............................................................................3-2

Indirect Register Addressing to Register File..........................................................3-3

Indirect Register Addressing to Program Memory ...................................................3-4

Indirect Working Register Addressing to Register File.............................................3-5

Indirect Working Register Addressing to Program or Data Memory...........................3-6

Indexed Addressing to Register File ......................................................................3-7

Indexed Addressing to Program or Data Memory with Short Offset ...........................3-8

Indexed Addressing to Program or Data Memory ....................................................3-9

Direct Addressing for Load Instructions..................................................................3-10

Direct Addressing for Call and Jump Instructions ....................................................3-11

Indirect Addressing..............................................................................................3-12

Relative Addressing .............................................................................................3-13

Immediate Addressing .........................................................................................3-14

Register Description Format .................................................................................4-4

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER ix

Figure

Number

9-4

9-5

9-6

9-7

9-8

9-9

8-1

8-2

8-3

9-1

9-2

9-3

5-9

6-1

7-1

7-2

7-3

7-4

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

List of Figures

(Continued)

Title Page

Number

S3C8-Series Interrupt Types .................................................................................5-2

Interrupt Structure................................................................................................5-4

ROM Vector Address Area...................................................................................5-5

Interrupt Function Diagram ...................................................................................5-8

System Mode Register (SYM) ..............................................................................5-10

Interrupt Mask Register (IMR) ...............................................................................5-11

Interrupt Request Priority Groups ..........................................................................5-12

Interrupt Priority Register (IPR) .............................................................................5-13

Interrupt Request Register (IRQ) ...........................................................................5-14

System Flags Register (FLAGS)...........................................................................6-6

Main Oscillator Circuit (External Crystal or Ceramic Resonator)...............................7-1

External Clock Circuit ..........................................................................................7-1

System Clock Circuit Diagram..............................................................................7-2

System Clock Control Register (CLKCON).............................................................7-3

Reset Block Diagram...........................................................................................8-1

Power-on Reset Circuit ........................................................................................8-2

Timing Diagram for Power-on Reset Circuit ............................................................8-3

I/O Port Data Register Format ..............................................................................9-2

Port 0 High-Byte Control Register (P0CONH) .........................................................9-3

Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-4

Port 0 External Interrupt Control Register (P0INT) ...................................................9-5

Port 0 External Interrupt Pending Register (P0PND)................................................9-5

Port 1 High-Byte Control Register (P1CONH) .........................................................9-6

Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-7

Port 2 Control Register (P2CON)...........................................................................9-8

Port 2 Data Register (P2) .....................................................................................9-9

x S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER

Figure

Number

11-3

11-4

12-1

12-2

12-3

12-4

10-1

10-2

10-3

10-4

10-5

11-1

11-2

13-1

13-2

14-1

14-2

List of Figures

(Concluded)

Title Page

Number

Basic Timer Control Register (BTCON) ..................................................................10-2

Timer 0 Control Register (T0CON) .........................................................................10-4

Simplified Timer 0 Function Diagram: Interval Timer Mode .......................................10-5

Simplified Timer 0 Function Diagram: PWM Mode ..................................................10-6

Basic Timer and Timer 0 Block Diagram ................................................................10-7

Simplified Timer 1 Function Diagram: Interval Timer Mode .......................................11-2

Timer 1 Block Diagram.........................................................................................11-3

Timer 1 Control Register (T1CON) .........................................................................11-4

Timer 1 Registers ................................................................................................11-5

Counter A Block Diagram.....................................................................................12-2

Counter A Control Register (CACON) ....................................................................12-3

Counter A Registers ............................................................................................12-4

Counter A Output Flip-Flop Waveforms in Repeat Mode ..........................................12-5

Input Timing for External Interrupts (Port 0) ............................................................13-5

Operating Voltage Range ....................................................................................13-6

24-Pin SOP Package Mechanical Data .................................................................14-1

24-Pin SDIP Package Mechanical Data.................................................................14-2

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER xi

Table

Number

13-2

13-3

13-4

13-5

13-6

13-7

13-8

8-1

8-2

9-1

9-2

13-1

5-3

6-1

6-2

6-3

6-4

6-5

6-6

1-1

2-1

4-1

5-1

5-2

List of Tables

Title Page

Number

Pin Descriptions ..................................................................................................1-5

Register Type Summary.......................................................................................2-3

Mapped Registers (Set1)......................................................................................4-2

Interrupt Vectors..................................................................................................5-6

Interrupt Control Register Overview ........................................................................5-7

Interrupt Source Control and Data Registers...........................................................5-9

Instruction Group Summary ..................................................................................6-2

Flag Notation Conventions ....................................................................................6-8

Instruction Set Symbols.......................................................................................6-8

Instruction Notation Conventions ...........................................................................6-9

Opcode Quick Reference .....................................................................................6-10

Condition Codes ..................................................................................................6-12

Set 1 Register Values After Reset.........................................................................8-4

Summary of Each Mode.......................................................................................8-10

Port Configuration Overview ..................................................................................9-1

Port Data Register Summary ................................................................................9-2

Absolute Maximum Ratings..................................................................................13-2

D.C. Electrical Characteristics..............................................................................13-2

Characteristics of Low Voltage Detect circuit .........................................................13-4

Data Retention Supply Voltage in Stop Mode.........................................................13-4

Input/Output Capacitance.....................................................................................13-4

A.C. Electrical Characteristics..............................................................................13-4

Oscillation Characteristics....................................................................................13-5

Oscillation Stabilization Time................................................................................13-6

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER xiii

List of Programming Tips

Description

Chapter 2: Address Spaces

Page

Number

Setting the Register Pointers ............................................................................................................2-9

Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-10

Addressing the Common Working Register Area ................................................................................2-14

Standard Stack Operations Using PUSH and POP.............................................................................2-19

Chapter 8: RESET and Power-Down

To Divide STOP Mode Releasing and POR ........................................................................................8-7

Chapter 10: Basic Timer and Timer 0

Configuring the Basic Timer..............................................................................................................10-8

Programming Timer 0.......................................................................................................................10-9

Chapter 12: Counter A

To Generate 38 kHz, 1/3duty Signal Through P2.1..............................................................................12-6

To Generate a One Pulse Signal Through P2.1...................................................................................12-7

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER xv

Register

Identifier

BTCON

CACON

CLKCON

EMT

FLAGS

IMR

IPH

IPL

IPR

IRQ

P0CONH

P0CONL

P0INT

P0PND

P0PUR

P1CONH

P1CONL

P1PUR

P2CON

PP

RP0

RP1

SPL

STOPCON

SYM

T0CON

T1CON

List of Register Descriptions

Full Register Name Page

Number

Basic Timer Control Register ................................................................................4-5

Counter A Control Register...................................................................................4-6

System Clock Control Register.............................................................................4-7

External Memory Timing Register .........................................................................4-8

System Flags Register ........................................................................................4-9

Interrupt Mask Register........................................................................................4-10

Instruction Pointer (High Byte) .............................................................................4-11

Instruction Pointer (Low Byte) .............................................................................4-11

Interrupt Priority Register......................................................................................4-12

Interrupt Request Register....................................................................................4-13

Port 0 Control Register (High Byte) .......................................................................4-14

Port 0 Control Register (Low Byte) ........................................................................4-15

Port 0 Interrupt Control Register............................................................................4-16

Port 0 Interrupt Pending Register ..........................................................................4-17

Port 0 Pull-up Resistor Enable Register.................................................................4-18

Port 1 Control Register (High Byte) .......................................................................4-19

Port 1 Control Register (Low Byte) ........................................................................4-20

Port 1 Pull-up Resistor Enable Register ...............................................................4-21

Port 2 Control Register.........................................................................................4-22

Register Page Pointer..........................................................................................4-23

Register Pointer 0................................................................................................4-24

Register Pointer 1................................................................................................4-24

Stack Pointer (Low Byte) .....................................................................................4-25

Stop Control Register...........................................................................................4-25

System Mode Register ........................................................................................4-26

Timer 0 Control Register.......................................................................................4-27

Timer 1 Control Register.......................................................................................4-28

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER xvii

List of Instruction Descriptions

Instruction

Mnemonic

COM

CP

CPIJE

CPIJNE

DA

DEC

DECW

DI

DIV

DJNZ

EI

ENTER

EXIT

IDLE

INC

INCW

ADC

ADD

AND

BAND

BCP

BITC

BITR

BITS

BOR

BTJRF

BTJRT

BXOR

CALL

CCF

CLR

IRET

JP

JR

LD

LDB

Full Register Name

S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER

Page

Number

Add with Carry ....................................................................................................6-14

Add....................................................................................................................6-15

Logical AND........................................................................................................6-16

Bit AND..............................................................................................................6-17

Bit Compare........................................................................................................6-18

Bit Complement ..................................................................................................6-19

Bit Reset ............................................................................................................6-20

Bit Set................................................................................................................6-21

Bit OR................................................................................................................6-22

Bit Test, Jump Relative on False...........................................................................6-23

Bit Test, Jump Relative on True.............................................................................6-24

Bit XOR ..............................................................................................................6-25

Call Procedure ....................................................................................................6-26

Complement Carry Flag .......................................................................................6-27

Clear ..................................................................................................................6-28

Complement .......................................................................................................6-29

Compare.............................................................................................................6-30

Compare, Increment, and Jump on Equal...............................................................6-31

Compare, Increment, and Jump on Non-Equal........................................................6-32

Decimal Adjust....................................................................................................6-33

Decrement ..........................................................................................................6-35

Decrement Word .................................................................................................6-36

Disable Interrupts ................................................................................................6-37

Divide (Unsigned).................................................................................................6-38

Decrement and Jump if Non-Zero ..........................................................................6-39

Enable Interrupts .................................................................................................6-40

Enter..................................................................................................................6-41

Exit ....................................................................................................................6-42

Idle Operation......................................................................................................6-43

Increment ...........................................................................................................6-44

Increment Word...................................................................................................6-45

Interrupt Return ...................................................................................................6-46

Jump..................................................................................................................6-47

Jump Relative......................................................................................................6-48

Load...................................................................................................................6-49

Load Bit..............................................................................................................6-51

xix

List of Instruction Descriptions

(Continued)

Instruction

Mnemonic

LDC/LDE

LDCD/LDED

LDCI/LDEI

LDCPD/LDEPD

LDCPI/LDEPI

LDW

MULT

NEXT

NOP

OR

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

RCF

RET

RL

RLC

RR

RRC

SB0

SB1

SBC

SCF

SRA

SRP/SRP0/SRP1

STOP

SUB

SWAP

TCM

TM

WFI

XOR

Full Register Name Page

Number

Load Memory ......................................................................................................6-52

Load Memory and Decrement ...............................................................................6-54

Load Memory and Increment ................................................................................6-55

Load Memory with Pre-Decrement ........................................................................6-56

Load Memory with Pre-Increment ..........................................................................6-57

Load Word..........................................................................................................6-58

Multiply (Unsigned)..............................................................................................6-59

Next...................................................................................................................6-60

No Operation.......................................................................................................6-61

Logical OR..........................................................................................................6-62

Pop from Stack ...................................................................................................6-63

Pop User Stack (Decrementing)............................................................................6-64

Pop User Stack (Incrementing) .............................................................................6-65

Push to Stack.....................................................................................................6-66

Push User Stack (Decrementing)..........................................................................6-67

Push User Stack (Incrementing) ...........................................................................6-68

Reset Carry Flag .................................................................................................6-69

Return ................................................................................................................6-70

Rotate Left ..........................................................................................................6-71

Rotate Left through Carry .....................................................................................6-72

Rotate Right........................................................................................................6-73

Rotate Right through Carry ...................................................................................6-74

Select Bank 0.....................................................................................................6-75

Select Bank 1.....................................................................................................6-76

Subtract with Carry ..............................................................................................6-77

Set Carry Flag.....................................................................................................6-78

Shift Right Arithmetic...........................................................................................6-79

Set Register Pointer ............................................................................................6-80

Stop Operation....................................................................................................6-81

Subtract .............................................................................................................6-82

Swap Nibbles ......................................................................................................6-83

Test Complement under Mask ..............................................................................6-84

Test under Mask .................................................................................................6-85

Wait for Interrupt..................................................................................................6-86

Logical Exclusive OR...........................................................................................6-87

xx S3C80A4/C80A8/C80A5/C80AB4/C80B8/C80B5 MICROCONTROLLER

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

1

PRODUCT OVERVIEW

OVERVIEW

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MICROCONTROLLER

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture.

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is the microcontroller which has mask-programmable ROM.

The S3P80A4/P80A8/P80A5/P80B4/P80B8/P80B5 is the microcontroller which has one-time-programmable

EPROM.

Using a proven modular design approach, Samsung engineers developed the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 by integrating the following peripheral modules with the powerful

SAM87 RC core:

— Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins.

— Internal LVD circuit and eight bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

— One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP package.

1-1

PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

FEATURES

CPU

•

SAM87RC CPU core

Memory

•

Program memory (ROM)

– S3C80A4/C80B4: 4-Kbyte

(0000H–0FFFH)

– S3C80A8/C80B8: 8-Kbyte

(0000H–1FFFH)

– S3C80A5/C80B5: 15,872 byte

(0000H–3E00H)

•

Data memory: 272-byte RAM

Instruction Set

•

78 instructions

•

IDLE and STOP instructions added for powerdown modes

Instruction Execution Time

•

500 ns at 8-MHz f

OSC

(minimum)

Interrupts

•

13 interrupt sources with 10 vector.

•

5 level, 10 vector interrupt structure

I/O Ports

•

Two 8-bit I/O ports (P0-P1) and one 3-bit port

(P2) for a total of 19 bit-programmable pins

•

Eight input pins for external interrupts

Carrier Frequency Generator

•

One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A)

Back-up mode

•

When V

DD

is lower than V

LVD

, the chip enters

Back-up mode to block oscillation and reduce the current consumption.

Timers and Timer/Counters

•

One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer function

•

One 8-bit timer/counter (Timer 0) with two operating modes; Interval mode and PWM mode.

•

One 16-bit timer/counter with one operating modes; Interval mode

Low Voltage Detect Circuit

•

Low voltage detect for reset or Back-up mode.

•

Low level detect voltage

– S3C80A4/C80A8/C80A5:

2.20 V (Typ)

± 200 mV

– S3C80B4/C80B8/C80B5:

1.90 V (Typ)

± 200 mV

Auto Reset Function

•

Reset occurs when stop mode is released by P0.

•

When a falling edge is detected at Port 0 during

Stop mode, system reset occurs.

Operating Temperature Range

• –25°C to + 85°C

Operating Voltage Range

-

S3C80B4/C80B8/C80B5

•


OSC

- S3C80A4/C80A8/C80A5

•


OSC

Package Type

•

24-pin SOP/SDIP

1-2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

BLOCK DIAGRAM

X

IN

X

OUT

LVD

TEST

Main

OSC

P0.0-P0.7/INT0-INT4

Port 0(INTR)

Internal Bus

P1.0-P1.7

Port 1

Port I/O and Interrupt

Control

8-bit

Basic

Timer

SAM87RI CPU

8-bit

Timer/

Counter

15-Kbyte ROM

256-Byte

Register File

16-bit

Timer/

Counter

Port 2

Carrier

Generator

(Counter A)

P2.0/T0PWM

P2.1/REM

P2.2

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

PIN ASSIGNMENTS

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

V

SS

X

IN

X

OUT

TEST

P0.0/INT0/INTR

P0.1/INT1/INTR

RESET/P0.2/INT2/INTR

P0.3/INT3/INTR

P0.4/INT4/INTR

P0.5/INT4/INTR

P0.6/INT4/INTR

P0.7/INT4/INTR

5

6

7

3

4

1

2

8

9

10

11

12

S3C80A4/C80A8/C80A5

C80B4/C80B8/C80B5

24-SOP/SDIP

(TOP VIEW)

24

23

22

21

20

19

18

17

16

15

14

13

V

DD

P2.2/SCLK

P2.1/REM/SDAT

P2.0/T0PWM/T0CK

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)

1-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

PIN DESCRIPTIONS

Pin

Names

P0.0–P0.7

P1.0–P1.7

P2.0

P2.1

P2.2

X

IN

V

V

SS

, X

TEST

DD

OUT

Table 1-1. Pin Descriptions

Pin

Type

Pin

Description

I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. Interrupt with Reset(INTR) is assigned to Port 0.

I/O I/O port with bit-programmable pins.

Configurable to input mode or output mode.

Pin circuits are either push-pull or n-channel open-drain type. Pull-up resistors are assignable by software.

Circuit

Type

1

24-Pin

Number

5–12

2 13–20

Shared

Functions

INT0 – INT4/INTR

I/O

–

3-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors are assignable by software. The two pins of port 2 have high current drive capability.

System clock input and output pins

3

4

5

–

21–23 REM/T0CK

2, 3 –

I

–

Test signal input pin (for factory use only; must be connected to V

SS

).

Power supply input pin

– 4

– 24

–

–

– 1 –

1-5


PIN CIRCUITS

V

DD

Pull-up

Resistor

Pull-up

Enable

V

DD

Data

Input/Output

Output

Disable

V

SS

External

Interrupt

Noise filter

INTR (Interrupt with RESET)

Stop

Figure 1-3. Pin Circuit Type 1 (Port 0)

NOTE

Interrupt with reset (INTR) is assigned to port 0 of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port

0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs automatically. It is designed for a application which are using “stop mode” like remote controller. If stop mode is not used, INTR do not operates and it can be discarded.

1-6

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

V

DD

Pull-up

Resistor

Pull-up

Enable

V

DD

Data

Open-drain

Output Disable

Normal

Input

Noise filter

V

SS

Figure 1-4. Pin Circuit Type 2 (Port 1)

Input/Output

V

DD

Pull-up Resistor

(Typical 21k

Ω)

Pull-up

Enable

P2CON.0

Port 2.0 Data

T0_PWN

Open-drain

Output

Disable

M

U

X

Data

P2.0 Input

V

DD

V

SS

P2.0/T0PWN

Figure 1-5. Pin Circuit Type 3 (P2.0)

1-7


CAOF(CACON.0)

Carrier On/Off (P2.5)

Pull-up

Enable

Port 2.1 Data

P2CON.1

M

U

X

Data

Open-Drain

Output

Disable

P2.1 Input

T0CK Noise filter

V

DD

V

SS


V

DD

Pull-up

Resistor

(Typical 21K

Ω)

P2.1/REM/T0CK

V

DD

Pull-up Resistor

(Typical 21K

Ω)

Pull-up

Enable

V

DD

Data

Open-drain

Output

Disable

Normal Input

V

SS


In/Out

1-8

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESS SPACES

2

ADDRESS SPACES

OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller has two types of address space:

— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

The S3C80A5/C80B5 has an internal 15,872 byte programmable ROM, the S3C80A8/C80B8 has an internal 8-Kbyte programmable ROM, and the S3C80A4/C80B4 has an internal 4-Kbyte programmable ROM. An external memory interface is not implemented. The 256-byte physical RAM space is expanded into an addressable area of 320 bytes by the use of addressing modes.

There are 312 mapped registers in the internal register file. Of these, 272 are for general-purpose use. (This number includes a 16-byte working register common area that is used as a " scratch area" for data operations, a 256 prime register area that is used for general purpose and stack operation). Eighteen 8-bit registers are used for CPU and system control and 22 registers are mapped peripheral control and data registers.

2-1

ADDRESS SPACES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

PROGRAM MEMORY (ROM)

Program memory stores program code or table data. The S3C80A5/C80B5 has 15, 872 bytes of internal programmable program memory, and the program memory address range is therefore 0000H-3E00H of ROM . The

S3C80A8/C80B8 has 8-Kbyte(0000H-1FFFH) of internal programmable program memory and the S3C80A4/C80B4 has 4-Kbyte(0000H-0FFFH) of internal programmable program memory (see Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you do use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations.

The ROM address at which program execution starts after a reset is 0100H.

(Decimal)

15,872

(HEX)

3E00H

15-Kbyte

ROM

8,191

8-Kbyte

ROM

4,095

255

0

4-Kbyte

ROM

Interrupt

Vector Area

S3C80A5/C80B5

1FFFH

S3C80A8/C80B8

0FFFH

0FFH

S3C80A4/C80B4

0H

Figure 2-1. Program Memory Address Space

2-2


REGISTER ARCHITECTURE

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 register file has 312 registers. The upper 64 bytes register files are addressed as system control register and working register. The lower 192-byte area of the physical register file(00H–BFH) contains freely-addressable, general-purpose registers called prime registers. It can be also used for

stack operation.

The extension of register space into separately addressable sets is supported internally by addressing mode restrictions.

Specific register types and the area (in bytes) they occupy in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 internal register space are summarized in Table 2-1.

Table 2-1. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Register Type Summary

Register Type

General-purpose registers (including the 16-byte common working register area, the 256-byte prime register area.)

CPU and system control registers

Mapped clock, peripheral, and I/O control and data registers

Total Addressable Bytes

Number of Bytes

272

18

22

312

2-3


Set 1

FFH

64-Bytes

E0H

DFH

D0H

CFH

System and Peripheral

Control Registers

(Register Addressing

Mode)

System Registers

(Register Addressing

Mode)

Working Registers

(Working Register

Addressing Mode)

C0H

FFH

Set 2

General-Purpose

Data Register

(Indirect Register or

Indexed addressing modes or stack operations)

C0H

BFH

256-Bytes

192-Bytes

~

~

Prime Data Registers

(All Addressing Modes)

~

00H

Figure 2-2. Internal Register File Organization

2-4


REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an

8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to "page 0."

Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always

'0000', automatically selecting page 0 as the source and destination page for register addressing. These page pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.

MSB .7

.6

Register Page Pointer (PP)

DFH, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Dectination register page selection bits:

0 0 0 0 Destination: page 0

Source register page selection bits:

0 0 0 0 Source: page 0

NOTE: In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, only pate 0 is implemented.

A hardware reset operation writes the 4-bit destination and source values shown above to the register pate pointer. These values should not be modified.

Figure 2-3. Register Page Pointer (PP)

2-5


REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two

32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, bank 1 is not implemented.

A hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.

The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The lower

32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–C0H).

You can use the common working register area as a "scratch" area for data operations being performed in other areas of the register file.

Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte working register area can only be accessed using working register addressing. (For more information about working register addressing, please refer to Section 3, "Addressing Modes," .)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH) are addressed as part of page 0 in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 register space.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only

Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-6


PRIME REGISTER SPACE

The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All registers in prime area locations are addressable immediately following a reset.

Set 1

FFH

FCH

E0H

D0H

C0H

FFH

C0H

Set 2

CPU and system registers

General-purpose registers

Peripheral control registers

Prime

Register

Space

00H

Figure 2-4. Set 1, Set 2 and Prime Area Register Map

2-7


WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When

4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of

32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)

All of the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block.

0 0 0 0 0 X X X

RP0 (Registers R0-R7)

~

Slice 32

Slice 31

Slice 2

Slice 1

~

10H

FH

8H

7H

0H

FFH

F8H

F7H

F0H

Set 1

Only

CFH

C0H

Figure 2-5. 8-Byte Working Register Areas (Slices)

2-8


USING THE REGISTER POINTERS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see

Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set

2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see

Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can define the working register area very flexibly to support program requirements.

F

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

LD

#70H

#48H

#0A0H

RP0

RP1,#0F8H

; RP0

→

70H, RP1

→

78H

; RP0

→

no change, RP1

→

48H,

; RP0

→

A0H, RP1

→

no change

; RP0

→

00H, RP1

→

no change

; RP0

→

no change, RP1

→

0F8H

Register File

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

0 0 0 0 0 X X X

RP0

8-Byte Slice

8-Byte Slice

FH (R15)

8H

7H

0H (R0)

Figure 2-6. Contiguous 16-Byte Working Register Block

16-Byte

Contiguous

Working

Register block

2-9


8-Byte Slice

F7H (R7)

F0H (R0)

1 1 1 1 0 X X X

RP0

0 0 0 0 0 X X X

RP1

Register File

Contains 32

8-Byte Slices

8-Byte Slice

7H (R15)

0H (R0)

16-Byte

Contiguous working

Register block

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

F

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

ADD

ADC

ADC

ADC

ADC

#80H

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

; RP0

→

80H

; R0

→

R0 + R1

; R0

→

R0 + R2 + C

; R0

→

R0 + R3 + C

; R0

→

R0 + R4 + C

; R0

→

R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

ADC

ADC

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

; 80H

→

(80H) + (81H)

; 80H

→

(80H) + (82H) + C

; 80H

→

(80H) + (83H) + C

; 80H

→

(80H) + (84H) + C

; 80H

→

(80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.

2-10


REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing because it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

Rn+1 n = Even address

Figure 2-8. 16-Bit Register Pair

2-11


Special-Purpose Registers

Set 1

FFH

Control

Registers

System

Registers

D0H

C0H

BFH

D7H

D6H

RP1

RP0

Register

Pointers

CFH

Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file

(other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH

(that is, to the common working register area).

NOTE:

Only page 0 is implemented. Page 0

Contains all of the addressable registers in the internal register file.

General-Purpose Register

FFH

Prime

C0H

Registers

Set 2

00H

Register Addressing Only

Can be Pointed by Register Pointer

Page 0

All

Addressing

Modes

Page 0

Indirect

Register,

Indexed

Addressing

Modes

Figure 2-9. Register File Addressing

2-12


COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–

CFH, as the active 16-byte working register block:

RP0

→

C0H–C7H

RP1

→

C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.

Set 1

Page 0

FFH FFH

FCH

E0H

DFH

CFH

C0H

Set 2

C0H

BFH

Register a hardware reset, register pointers RP0 and RP1 point to the commom working register area, locations C0H-CfH.

RP0 =

1 1 0 0 0 0 0 0

RP1 = 1 1 0 0 1 0 0 0

00H

~

Prime

Area

~

Figure 2-10. Common Working Register Area

2-13


F

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only.

Example 1:

LD 0C2H,40H ; Invalid addressing mode!

Use working register addressing instead:

SRP

LD

#0C0H

R2,40H

Example 2:

ADD 0C3H,#45H

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R2 (C2H)

; Invalid addressing mode!

; R3 (C3H)

←

←

the value in location 40H

R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);

— The five high-order bits in the register pointer select an 8-byte slice of the register space;

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing: The high-order bit of the instruction

'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-14


Selects

RP0 or RP1

Address OPCODE

RP0

RP1

Register Pointer

Provides Five

High-order Bits

4-bit Address

Provides Three

Low-order Bits

Together They Create an

8-bit Register Address

Figure 2-11. 4-Bit Working Register Addressing

RP0

0 1 1 1 0 0 0 0

0 1 1 1 0 1 1 0

Register

Address

(76H)

Selects RP0

RP1

0 1 1 1 1 0 0 0

R6

0 1 1 0

OPCODE

1 1 1 0

Instruction:

'INC R6'

Figure 2-12. 4-Bit Working Register Addressing Example

2-15


8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B.

This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing: The four high-order bits of the instruction address

(1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1

(10101B) become the five high-order bits of the register address. The three low-order bits of the register address

(011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).

These Address

Bits Indicate 8-bit

Working Register

Addressing

RP0

RP1

Selects

RP0 or RP1

1 1 0 0

Register Pointer

Provides Five

High-order Bits

Address

8-bit Logical

Address

Three loworder Bits

8-bit Physical Address

Figure 2-13. 8-Bit Working Register Addressing

2-16

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RP0

0 1 1 0 0 0 0 0

Selects RP1

RP1

1 0 1 0 1 0 0 0

R11

1 1 0 0 1 0 1 1

8-bit Address

Form Instruction

'LD R11, R2'

Specifies Working

Register Addressing

Register Address (0ABH)

1 0 1 0 1 0 1 1

Figure 2-14. 8-Bit Working Register Addressing Example

ADDRESS SPACES

2-17


SYSTEM AND USER STACKS

S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations.

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15.

High Address

Top of

Stack

PCL

PCH

Top of

Stack

PCL

PCH

FLAGS

Stack Contents

After an Interrupt

Stack Contents

After a Call

Instruction

Low Address

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL)

Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5, the SPL must be initialized to an 8-bit value in the range 00H–FFH.

2-18


F

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions:

LD SPL,#0FFH ; SPL

←

FFH

; (Normally, the SPL is set to 0FFH by the initialization

; routine)

•

•

•

PUSH

PUSH

PUSH

PUSH

•

•

•

POP

POP

POP

POP

PP

RP0

RP1

R3

R3

RP1

RP0

PP

; Stack address 0FEH

; Stack address 0FDH

; Stack address 0FCH

; Stack address 0FBH

; R3

; PP

←

; RP1

; RP0

←

←

←

←

←

PP

RP0

RP1

R3

Stack address 0FBH

←

←

Stack address 0FCH

Stack address 0FDH

Stack address 0FEH

2-19

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

3-1

ADDRESSING MODES S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).

Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory Register File

8-bit Register

File Address

One-Operand

Instruction

(Example) dst

OPCODE

OPERAND

Point to One

Register in Register

File

Value used in

Instruction Execution

Sample Instruction:

DEC CNTR ; Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

MSB Points to

RP0 ot RP1

Register File

RP0 or RP1

4-bit

Working Register

Two-Operand

Instruction

(Example)

Program Memory dst src

OPCODE

3 LSBs

Points to the

Working Register

(1 of 8)

OPERAND

Sample Instruction:

ADD R1, R2 ; Where R1 and R2 are registers in the currently

selected working register area.

Figure 3-2. Working Register Addressing

Selected

RP Points to Start of Working

Register

Block

3-2


INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be accessed using

Indirect Register addressing mode.

8-bit Register

File Address

One-Operand

Instruction

(Example)

Program Memory dst

OPCODE

Point to One

Register in

Register File

Address of Operand used by Instruction

Register File

ADDRESS

Value used in

Instruction Execution

OPERAND

Sample Instruction:

RL @SHIFT ; Where SHIFT is the label of an 8-bit register address.

Figure 3-3. Indirect Register Addressing to Register File

3-3


INDIRECT REGISTER ADDRESSING MODE (Continued)

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Register File

Example

Instruction

References

Program

Memory

Program Memory dst

OPCODE

Points to

Register Pair

Sample Instructions:

CALL

JP

@RR2

@RR2

Register Pair

Value used in

Instruction

Program Memory

OPERAND

16-Bit

Address

Points to

Program

Memory

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5



Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4-bit

Working

Register

Address


OPCODE

~ ~

3 LSBs

Point to the

Working Register

(1 of 8)

~

ADDRESS

~

Sample Instruction:

OR R3, @R6

Value used in

Instruction

OPERAND

Selected

RP Points to Start of

Woking

Register

Block

Figure 3-5. Indirect Working Register Addressing to Register File

3-5



S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB Points to

RP0 or RP1

Register File

RP0 or RP1

4-bit Working

Register Address

Example Instruction

References either

Program Memory or

Data Memory


OPCODE

Next 2-bit Point

to Working

Register Pair

(1 of 4)

LSB Selects

Register

Pair

Program Memory or

Data Memory

Value used in

Instruction

OPERAND

Selected


Working

Register

Block

16-Bit

Address

Points to

Program

Memory or

Data

Memory


LDC

LDE

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

; External data memory access

; External data memory access

NOTE:

LDE command is not available, because an external interface is not implemented for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6


INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in set 1 using Indexed addressing.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to

+127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see

Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).

The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory (if implemented).

Register File

MSB Points to

RP0 or RP1

Sample Instruction:

LD R0, #BASE[R1]

RP0 or RP1

Two-Operand

Instruction

Example

Value used in

Instruction

~

OPERAND

~

Selected RP

Points to

Start of

Working

Register

Block

+

Program Memory

Base Address dst/src x

OPCODE

3 LSBs

Point to One of the

Working Register

(1 of 8)

~

INDEX

~

; Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7


INDEXED ADDRESSING MODE (Continued)

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4 Bit Working

Register Address

Program Memory

OFFSET dst/src

OPCODE x

Next 2 Bits

Point to Working

Register Pair

(1 of 4)

LSB Selects

~

Register

Pair

Program Memory or

Data Memory

~

Selected


Working

Register

Block

16-Bit

Address

Added to

Offset

8 Bits

+

16 Bits

OPERAND

Value used In

Instruction

16 Bits


LDC

LDE

R4, #04H[RR2]

R4,#04H[RR2]

; The values in the program address (RR2 + 04H) are

loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

NOTE:


Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

INDEXED ADDRESSING MODE (Continued)


Register File

MSB Points to

RP0 or RP1

RP0 or RP1

4 Bit Working

Register Address

Program Memory

OFFSET

OFFSET dst/src x

OPCODE

~ ~

Selected


Working

Register

Block

Next 2 Bits

Point to Working

Register Pair

Register

Pair

LSB Selects

16 Bit

Address

Added to

Offset

Program Memory or

Data Memory

8-Bits

+

16-Bits

16-Bits

OPERAND

Value used in

Instruction


LDC

LDE

R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H)

are loaded into register R4.

R4, #1000H[RR2] ; Identical operation to LDC example, except that


NOTE:


Figure 3-9. Indexed Addressing to Program or Data Memory

3-9


DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Program Memory

Memory

Address

Used

Upper Address Byte

Lower Address Byte dst/src "0" or "1"

OPCODE

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

NOTE:


LDC

LDE

R5,1234H; The values in the program address (1234H)

are loaded into register R5.

R5,1234H; Identical operation to LDC example, except that



Figure 3-10. Direct Addressing for Load Instructions

3-10

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

DIRECT ADDRESS MODE (Continued)


Program Memory

Next OPCODE

Program Memory

Address Used

Lower Address Byte

Upper Address Byte

OPCODE


JP

CALL

C,JOB1 ; Where JOB1 is a 16 bit immediate address

DISPLAY ; Where DISPLAY is a 16 bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11


INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

Current

Instruction dst

OPCODE

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H ; The 16 bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12


RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current Instruction

Displacement

OPCODE

Current

PC Value

+

Signed Displacement

Value


JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13


IMMEDIATE MODE (IM)

In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CONTROL REGISTERS

4

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part

II of this manual.

Data and counter registers are not described in detail in this reference section. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual.

4-1

CONTROL REGISTERS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Table 4-1. Mapped Registers (Set 1)

Timer 0 counter

Register Name

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

Register pointer 1

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

Port 0 data register



Port 0 pull-up resistor enable register

Port 0 control register (high byte)

Port 0 control register (low byte)



Port 1 pull-up resistor enable register

Port 2 control register

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Mnemonic

T0CNT

Decimal

208

T0DATA

T0CON

BTCON

CLKCON

FLAGS

209

210

211

212

213

RP0

RP1

Locations D8H is not mapped.

214

215

SPL

IPH

IPL

IRQ

217

218

219

220

IMR

SYM

221

222

PP

P0

P1

P2

223

224

225

226

Location E3H–E6H is not mapped.

P0PUR

P0CONH

P0CONL

231

232

233

P1CONH

P1CONL

234

235

P1PUR 236

Location EDH–EFH is not mapped.

P2CON 239

P0INT

P0PND

CACON

CADATAH

CADATAL

T1CNTH

241

242

243

244

245

246

T1CNTL

T1DATAH

247

248

R/W

R/W

R/W

R

(note)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

(note)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

(note)

R

(note)

R/W

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

E7H

E8H

E9H

EAH

EBH

ECH

4-2


Register Name

Timer 1 data register (low byte)


STOP Control register

Basic timer counter

External memory timing register

Interrupt priority register

Table 4-1. Mapped Registers (Continued)

Mnemonic

T1DATAL

T1CON

STOPCON

Decimal

249

250

251

Locations FCH is not mapped.

BTCNT 253

EMT

IPR

254

255

Hex

F9H

FAH

FBH

FDH

FEH

FFH

NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

R/W

R/W

R/W

W

R

(note)

R/W

R/W

4-3


Bit number(s) that is/are appended to the register name for bit addressing

Register ID Register name

Name of individual bit or related bits

Register address

(hexadecimal)

Register location in the internal register file

FLAGS - System Flags Register

Bit Identifier

RESET Value

Read/Write

Bit Addressing Mode

.7

x

R/W

.6

x

R/W

.5

x

R/W

Register addressing mode only

.4

x

R/W

D5H

.3

x

R/W

.2

x

R/W

Set 1

.1

x

R/W

.0

0

R/W

.7

.6

.5

Carry Flag (C)

0 Operation does not generate a carry or borrow condition

0 Operation generates carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

0

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

0

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

'-' = Not used

Addressing mode or modes you can use to modify register values

Description of the effect of specific bit settings

Figure 4-1. Register Description Format

RESET value notation:

'-' = Not used

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

Bit number:

MSB = Bit 7

LSB = Bit 0

4-4


BTCON

— Basic Timer Control Register D3H Set 1

Bit Identifier

RESET Value

Read/Write

Bit Addressing

.7–.4

.3–.2

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

.2

0

R/W

Watchdog Timer Function Disable Code (for System Reset)

1 0 1

Any other value

0 Disable watchdog timer function

Enable watchdog timer function

.1

0

R/W

.0

0

R/W

Basic Timer Input Clock Selection Bits

0 0 f

OSC

/4096

0 1 f

OSC

/1024

1 0 f

OSC

/128

1 1 Invalid setting; not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

.0

.1

Basic Timer Counter Clear Bit

0

1

No effect

(1)

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0

(2)

0 No effect

1 Clear both clock frequency dividers

NOTES:

1. When you write a "1" to BTCON.1, the basic timer counter value is cleared to '00H'. Immediately following the write operation, the BTCON.1 value is automatically cleared to "0".

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".

4-5


.2

.1

.3

.0

CACON

— Counter A Control Register F3H Set 1

.5–.4

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7 .6 .5

0

R/W

0

R/W

0

R/W


.4

0

R/W

Counter A Input Clock Selection Bits

0 0 f

OSC

0 1 f

OSC

/2

1 0 f

OSC

/4

1 1 f

OSC

/8

.3

0

R/W

.2

0

R/W

Counter A Interrupt Timing Selection Bits

0 0 Elapsed time for Low data value

0 1 Elapsed time for High data value

1 0 Elapsed time for combined Low and High data values

1 1 Invalid setting; not used for

S3C80A4/C80A8/C80A5/C80B4/C80B8/C800B8.

.1

0

R/W

.0

0

R/W

Counter A Interrupt Enable Bit

0 Disable interrupt

1 Enable interrupt

Counter A Start Bit

0 Stop counter A

1 Start counter A

Counter A Mode Selection Bit

0 One-shot mode

1 Repeating mode

Counter A Output flip-flop Control Bit

0 Flip-flop Low level (T-FF = Low)

1 Flip-flop High level (T-FF = High)

4-6


CLKCON

— System Clock Control Register D4H Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.6–.5

.4–.3

.7

0

R/W

.6

0

R/W

.5

0

R/W


R/W

Oscillator IRQ Wake-up Function Enable Bit

Not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

Main Oscillator Stop Control Bits

.4

0

.3

0

R/W

.2

0

R/W


.1

0

R/W

.0

0

R/W

CPU Clock (System Clock) Selection Bits

(1)

0 0 f

OSC

/16

0 1 f

OSC

/8

1 0 f

OSC

/2

1 1 f

OSC

(non-divided)

.2–.0

Subsystem Clock Selection Bit

(2)

1 0 1 Invalid setting for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

Other value Select main system clock (MCLK)

NOTES:

1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.

2. These selection bits are required only for systems that have a main clock and a subsys tem clock. The

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 uses only the main oscillator clock circuit. For this reason, the setting

'101B' is invalid.

4-7


EMT

— External Memory Timing Register

(note)

FEH Set 1

.0

.1

.5–.4

.3–.2

.6

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

0

0

1

1

.7

0

R/W

0

1

0

1

.6

1

R/W

No wait

.5

1

R/W


External WAIT Input Function Enable Bit

0

1

Slow Memory Timing Enable Bit

0

1

Disable WAIT input function for external device

Enable WAIT input function for external device

Program Memory Automatic Wait Control Bits

WAIT one cycle

WAIT two cycles

WAIT three cycles

Data Memory Automatic Wait Control Bits

0

0

1

1

0

1

0

1

No wait

WAIT one cycle

WAIT two cycles

WAIT three cycles

Stack Area Selection Bit

0

1

R/W

Select internal register file area

.4

1

Select external data memory area

.3

1

R/W

Disable WAIT input function for external device

Enable WAIT input function for external device

.2

1

R/W

.1

0

R/W

.0

–

–


NOTE: The EMT register is not used for S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5, because an external peripheral interface is not implemented in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT values during normal operation may cause a system malfunction.

4-8


FLAGS

— System Flags Register D5H Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

.7

x

.6

x

.5

x

R/W R/W R/W


.4

x

R/W

.3

x

R/W

.2

x

R/W

.1

0

R

.0

0

R/W

Carry Flag (C)

0 Operation does not generate a carry or borrow condition

1 Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

0 Operation result is a non-zero value

1 Operation result is zero

Sign Flag (S)

0 Operation generates a positive number (MSB = "0")

1 Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0 Operation result is

≤

+127 or

≥

–128

1 Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0 Add operation completed

1 Subtraction operation completed

Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)

1 Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0 Bank 0 is selected

(normal setting for S3C80A48C80A8/C80A5/C80B4/C80B8/C8085)

1 Invalid selection (bank 1 is not implemented)

4-9

4-10

.1

.4


IMR

— Interrupt Mask Register

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

.7

x

.6

x

.5

x

R/W R/W R/W


.4

x

R/W

.3

x

R/W

DDH

.2

x

R/W

.1

x

R/W

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4

Set 1

.0

x

R/W


IPH

— Instruction Pointer (High Byte)

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.0

.7

x

.6

x

.5

x

R/W R/W R/W


.4

x

R/W

.3

x

R/W

DAH

.2

x

R/W

.1

x

R/W

Set 1

.0

x

R/W

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).

IPL

— Instruction Pointer (Low Byte)

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.0

.7

x

.6

x

.5

x

R/W R/W R/W


.4

x

R/W

.3

x

R/W

DBH

.2

x

R/W

.1

x

R/W

.0

x

R/W

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).

Set 1

4-11

CONTROL REGISTERS

IPR

— Interrupt Priority Register

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

FFH Set 1

4-12


IRQ

— Interrupt Request Register DCH Set 1

.1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

.6

.4

.7

0

R

.6

0

R

.5

0

R


.4

0

R

.3

0

R

.2

0

R

.1

0

R

.5

.3–.2

Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4

0 Not pending

1 Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0

0 Not pending

1 Pending


Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt

0 Not pending

1 Pending


Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow

0 Not pending

1 Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow

0 Not pending

1 Pending

.0

NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure.

.0

0

R

4-13


P0CONH

— Port 0 Control Register (High Byte)

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

E8H

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

.3–.2

4-14


P0CONL

— Port 0 Control Register (Low Byte)

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

E9H

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

.3–.2

4-15


P0INT

— Port 0 External Interrupt Enable Register

Bit Identifier

RESET Value

Read/Write

.1

.0

.3

.2

.4

.5

.6

Addressing Mode

.7

.7 .6

.5

0 0

0

R R

R


.4

0

R

P0.7 External Interrupt (INT4) Enable Bit

0 Disable interrupt

1 Enable interrupt

.3

0

R


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt


0 Disable interrupt

1 Enable interrupt

F1H

.2

0

R

.1

0

R

Set 1

.0

0

R

4-16


P0PND

— Port 0 External Interrupt Pending Register F2H Set 1

.3

.2

.5

.4

.6

.1

.0

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

P0.7 External Interrupt (INT4) Pending Flag

(note)

0

1


0 No P0.6 external interrupt pending (when read)

1 P0.6 external interrupt is pending (when read)


0

1

.7

0

R/W

.6

0

R/W

.5

0

R/W


.4

0

R/W R/W





0

1

.3

0

No P0.3 external interrupt pending (when read)

P0.3 external interrupt is pending (when read)


0

1










.2

0

R/W

.1

0

R/W

.0

0

R/W




NOTE: To clear an interrupt pending condition, write a "0" to the appropriate pending flag. Writing a "1" to an inte rrupt pending flag (POND.0 –7) has no effect.

4-17


P0PUR

— Port 0 Pull-up Resistor Enable Register

Bit Identifier

RESET Value

Read/Write

.3

.2

.1

.0

.5

.4

.6

Addressing Mode

.7

.7 .6 .5

0

R/W

0

R/W

0

R/W


.4

0

R/W

P0.7 Pull-up Resistor Enable Bit

0 Disable pull-up resistor

1 Enable pull-up resistor






















.3

0

R/W

E7H

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

4-18


P1CONH

— Port 1 Control Register (High Byte)

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.5–.4

.3–.2

.1–.0

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

P1.7 Mode Selection Bits

0 0 C-MOS input mode

0 1 Open-drain output mode

1 0 Push-pull output mode

1 1 Invalid setting





1 1 Invalid setting





1 1 Invalid setting





1 1 Invalid setting

.3

0

R/W

EAH

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

4-19


P1CONL

— Port 1 Control Register (Low Byte)

.5–.4

.3–.2

.1–.0

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7 .6 .5

0

R/W

0

R/W

0

R/W


.4

0

R/W





1 1 Invalid setting





1 1 Invalid setting





1 1 Invalid setting





1 1 Invalid setting

.3

0

R/W

EBH

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

4-20


P1PUR

— Port 0 Pull-up Resistor Enable Register

Bit Identifier

.0

.1

.2

.5

.4

.6

.3

RESET Value

Read/Write

Addressing Mode

.7

.7 .6 .5

0 0 0

R/W R/W R/W


.4

0

R/W

























.3

0

R/W

ECH

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

4-21


P2CON

— Port 2 Control Register

.0

.1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.5–.4

.3–.2

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W





1 1 C-MOS input with pull up mode











P2.1 Alternative Function Selection Bits

0 Normal I/O function

0 REM/T0CK function

P2.0 Alternative Function Selection Bits

0 Normal I/O function

0 T0PWN function

.3

0

R/W

F0H

.2

0

R/W

.1

0

R/W

Set 1

.0

0

R/W

4-22


PP

— Register Page Pointer DFH Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.4

.3–.0

.7

0

R/W

.6

0

R/W

.5

0

R/W


.4

0

R/W

Destination Register Page Selection Bits

0 0 0 0

Destination: page 0

(note)

Source Register Page Selection Bits Bits

0 0 0 0

Source: page 0

(note)

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

NOTE: In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to '0000B' following a hardware reset.

These values should not be changed during normal operation.

4-23


RP0

— Register Pointer 0

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.3

.7

1

.6

1

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

D6H

.2

–

–

.1

–

–

Set 1

.0

–

–

Destination Register Page Selection Bits

Register pointer 0 can independently point to one of the 24 8-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two

8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice

C0H–C7H.

.2–.0


RP1

— Register Pointer 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.3

.7 .6 .5

1

R/W

1

R/W

0

R/W


.4

0

R/W

.3

1

R/W

D7H

.2

–

–

.1

–

–

Set 1

.0

–

–

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 24 8-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two

8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice

C8H–CFH.

.2–.0


4-24


SPL

— Stack Pointer (Low Byte) D9H Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.0

.7 .6 .5

x

R/W x

R/W x

R/W


.4

x

R/W

Stack Pointer Address (Low Byte)

The SP value is undefined following a reset.

.3

x

R/W

.2

x

R/W

.1

x

R/W

.0

x

R/W

STOPCON

— Stop Control Register FBH Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.0

.7

0

W

.6

0

W

.5

0

W


.4

0

W

.3

0

W

.2

0

W

Stop Control Register enable bits

1 0 1 0 0 1 0 1 Enable STOPCON

NOTES:

1. To get into STOP mode, stop control register must be enabled just before STOP instruction.

2. When STOP mode is released, stop control register (STOPCON) value is cleared automatically.

3. It is prohibited to write another value into STOPCON.

.1

0

W

.0

0

W

4-25


SYM

— System Mode Register DEH Set 1

.1

.6–.5

.4–.2

.0

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7

.7

0

R/W

.6

–

–

Fast Interrupt Level Selection Bits

0 0 0 IRQ0

0 0 1 IRQ1

0

1

1

1

1

1

0

0

1

Not used for

IRQ7

(2)

0 1 1 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

1 0 0

1 0 1

IRQ6

.5

–

–


Fast Interrupt Enable Bit

0

1

(3)

.4

Disable fast interrupt processing

Enable fast interrupt processing x

R/W

Tri-State External Interface Control Bit

0

1

(1)

.3

x

R/W

Normal operation (disable tri-state operation)

.2

x

R/W

Set external interface lines to high impedance (enable tri-state operation)


.1

0

R/W

.0

0

R/W

Global Interrupt Enable Bit

(4)

0 Disable global interrupt processing

1 Enable global interrupt processing

NOTES:

1. Because an external interface is not im plemented for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5,

SYM.7 must always be "0".

2. You can select only one interrupt level at a time for fast interrupt processing.

3. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

4. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.0).

4-26


T0CON

— Timer 0 Control Register D2H Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

Timer 0 Input Clock Selection Bits

0 0 f

OSC

/4096

0 1 f

OSC

/256

1 0 f

OSC

/8

1 1

External clock input (at the T0CK pin, P2.1)

.5–.4

.3

.2

Timer 0 Operating Mode Selection Bits

0 0

Interval timer mode (counter cleared by match signal)

0 1

Overflow mode(OVF interrupt can occur)

1

1

0

1

Overflow mode( OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

Timer 0 Counter Clear Bit

0

1

No effect (when write)

Clear T0 counter, T0CNT (when write)

.1

.0

Timer 0 Overflow Interrupt Enable Bit

(note)

0

1

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Match Interrupt Enable Bit

0 Disable T0 match interrupt

1 Enable T0 match interrupt

Timer 0 Match Interrupt Pending Flag

0 No T0 match interrupt pending (when read)

0

Clear T0 match interrupt pending condition (when write)

1 T0 match interrupt is pending (when read)

1

No effect (when write)

NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/ capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.

.0

0

R/W

4-27


T1CON

— Timer 1 Control Register FAH Set 1

Bit Identifier

RESET Value

Read/Write

Addressing Mode

.7–.6

.7

0

.6

0

.5

0

R/W R/W R/W


.4

0

R/W

.3

0

R/W

.2

0

R/W

.1

0

R/W

.0

0

R/W

.0

.1

.2

.3

.5–.4

Timer 1 Input Clock Selection Bits

0 0 f

OSC

/4

0 1 f

OSC

/8

1 0 f

OSC

/16

1 1

Internal clock (counter a flip-flop, T-FF)

Timer 1 Operating Mode Selection Bits

0 0

Interval timer mode (counter cleared by match signal)

0 1

Overflow mode (OVF interrupt can occur)

1 0

Overflow mode (OVF interrupt can occur)

1 1

Overflow mode(OVF interrupt can occur)

Timer 1 Counter Clear Bit

0

1

0

1

No effect (when write)

Clear T1 counter, T1CNT (when write)

Timer 1 Overflow Interrupt Enable Bit

Disable T1 overflow interrupt

Enable T1 overflow interrupt

Timer 1 Match/Capture Interrupt Enable Bit

0

1

Disable T1 match interrupt

Enable T1 match interrupt

(note)

Timer 1 Match/Capture Interrupt Pending Flag

0 No T1 match interrupt pending (when read)

0

Clear T1 match interrupt pending condition (when write)

1 T1 match interrupt is pending (when read)

1


NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/ capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

4-28

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 INTERRUPT STRUCTURE

5

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM87 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0 – level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure recognizes five interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are simply identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used for S3C8-series devices is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 uses ten vectors. One vector address is shared by four interrupt sources.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for example. Each vector can have several interrupt sources. In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure, there are thirteen possible interrupt sources.

When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must be cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method is used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

INTERRUPT TYPES

The three components of the S3C8 interrupt structure described above — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.

The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1: One level (IRQn) + one vector (V

1

) + one source (S

1

)

Type 2: One level (IRQn) + one vector (V

1

) + multiple sources (S

1

– S n

)

Type 3: One level (IRQn) + multiple vectors (V

1

– V n

) + multiple sources (S

1

– S n

, S n+1

– S n+m

)

In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, all three interrupt types are implemented.

Type 1:

Type 2:

Type 3:

Levels

IRQn

IRQn

IRQn

Vectors

V

V

V

V

V

V

1

1

1

2

3 n

Sources

S

3

S n

S

1

S

2

S

1

S

1

S

2

S

3

S n

S n +

1

S n +

2

S n + m

NOTES:

1. The number of S n

and V n

value is expandable.

2. In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 implementation,

interrupt types 1, 2, and 3 is used.

Figure 5-1. S3C8-Series Interrupt Types

5-2



The S3P80A4/P80A8/P80A5/P80B4/P80B8/P80B5 microcontroller supports two kinds interrupt structure

— Non vectored interrupt (Reset interrupt): INTR

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller supports thirteen interrupt sources. Nine of the interrupt sources have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. (The relative priorities of multiple interrupts within a single level are fixed in hardware.)

When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the program counter value and state flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller supports non vectored interrupt - Interrupt with Reset(INTR) - to occur interrupt with system reset. The Interrupt with

Reset(INTR) has nothing to do with interrupt levels, vectors and the registers that are related to interrupt setting. It

occurs only according to the “P0” during “ STOP ” regardless any other things. Namely, only when a falling/rising edge occurs at any pin of Port 0 during STOP status, this INTR and a system reset occurs even though SYM.0 is

“0”(Disable interrupt). But it dose not occurs while the oscillation - “IDLE” or “OPERATING” status- even though a falling/rising edge occurs at port 0.

Following is the sequence that occurs Interrupt with Reset(INTR).

1. The oscillation status is “freeze” : STOP mode

2. A falling/rising edge is detected to any pin of Port 0.

3. INTR occurs and it makes system reset.

4. STOP mode is released by this system reset.

NOTE

Because H/W reset occurs whenever INTR occurs. A user should aware of the each ports, system register, control register etc.”

5-3


Levels

RESET

IRQ0

IRQ1

IRQ4

IRQ6

IRQ7

Vectors

100H

FCH

FAH

F6H

F4H

ECH

E6H

E4H

E2H

E0H

1

0

1

0

1

0

3

2

E8H

Sources

Basic timer overflow/INTR/POR

Timer 0 match

Timer 0 overflow

Timer 1 match

Timer 1 overflow

Counter A

P0.3 external interrupt








Reset/Clear

H/W

S/W

S/W

S/W

H/W

S/W

H/W

S/W

H/W

S/W

S/W

S/W

S/W

S/W

NOTE:

For interrupt levels with two or more vectors, the lowest vector address usually the highest priority. For example, FAH has the higher priority (0) than FCH (1) within level IRQ0. These priorities are fixed in hardware.

Figure 5-2. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Interrupt Structure

5-4


INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH. You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses. (Table 5-2 lists all vector addresses.)

The program reset address in the ROM is 0100H.

(Decimal)

15,872

(HEX)

3E00H

15-Kbyte

ROM

S3C80A4/C80B4

8,191

8-Kbyte

ROM

4,095

255

0

4-Kbyte

ROM

Interrupt

Vector Area

1FFFH

S3C80A8/C80B8

0FFFH

0FFH

S3C80A5/C80B5

0H

Figure 5-3. ROM Vector Address Area

5-5


Vector Address

Decimal

Value

Hex

Value

254

252

100H

FCH

250

246

244

236

232

232

232

232

230

228

226

224

Table 5-1. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Interrupt Vectors

FAH

F6H

F4H

ECH

E8H

E8H

E8H

E8H

E6H

E4H

E2H

E0H

Interrupt Source

Basic timer overflow

Timer 0 (match)

Timer 0 overflow

Timer 1 (match)

Timer 1 overflow

Counter A









Level

RESET

IRQ0

IRQ1

IRQ4

IRQ7

IRQ6

Request

Level

–

1

0

1

0

–

–

–

–

–

3

0

Reset/Clear

H/W S/W

√

NOTES:

1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.

√

√

√

√

√

√

√

√

√

√

√

5-6


ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur, and according to the established priorities.

NOTE

The system initialization routine that is executed following a reset must always contain an EI instruction to globally enable the interrupt structure.

During normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions instead.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented).

Control Register



Interrupt request register


Table 5-2. Interrupt Control Register Overview

ID

IMR

IPR

IRQ

SYM

R/W Function Description

R/W Bit settings in the IMR register enable or disable interrupt processing for each of the five interrupt levels: IRQ0, IRQ1,

IRQ4, and IRQ6–IRQ7.

R/W Controls the relative processing priorities of the interrupt levels.

The five levels of the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ4, and group C is IRQ6, and IRQ7.

R This register contains a request pending bit for each interrupt level.

R/W Dynamic global interrupt processing enable/ disable, fast interrupt processing, and external interface control (An external memory interface is not implemented in the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller).

5-7


INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are, therefore:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing the part of your application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information.

EI

RESET

S

R

Q

IRQ0, IRQ1,

IRQ4 and IRQ6- IRQ7

Interrupts

Interrupt Priority

Register

Interrupt Request

Register (Read-only)

Polling

Cycle

Interrupt Mask

Register

Global Interrupt Control

(EI, DI, or SYM.0

manipulation)

Figure 5-4. Interrupt Function Diagram

Vector

Interrupt

Cycle

5-8


PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (see Table 5-3).

Interrupt Source

Timer 0 match or timer 0 overflow

Timer 1 match or timer 1 overflow

Counter A

Table 5-3. Interrupt Source Control and Data Registers

IRQ0

Interrupt Level

IRQ1

IRQ4

Register(s)

T0CON

(note)

T0DATA

T1CON

(note)

T1DATAH, T1DATAL

CACON

CADATAH, CADATAL

Location(s) in Set 1

D2H

D1H

FAH

F8H, F9H

F3H

F4H, F5H









P0INT

P0PND

P0INT

P0PND

F1H

F2H

F1H

F2H

NOTES:

1. Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending bits for the timer 0 and timer 1 match interrupts, respectively.

2. If a interrupt is un-mask(Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt should be written after a DI instruction is executed.

5-9


SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5).

A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this purpose.

MSB

.7

.6

System Mode Register (SYM)

DEH, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

External interface tri-state enable bit:

0 = Normal (Tri-state)

1 = High (Tri-state)

Global interrupt enable bit:

0 = Disable all interrupts

1 = Enable all interrupts

Fast interrupt enable bit:

0 = Disable fast interrupt

1 = Enable fast interrupt

Not used for the S3C80A4/C80A8/

C80A8/C80B4/C80B8/C80B5.

Fast interrupt level selection bits:

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

IRQ0

IRQ1

Not used

Not used

Not used

Not used

IRQ6

IRQ7

NOTE:

An external memory interface is not implemented.

Figure 5-5. System Mode Register (SYM)

5-10


INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's

IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode.

MSB

.7

.6

Interrupt Mask Register (IMR)

DDH, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

IRQ7 IRQ0

IRQ6

Not used Not used

IRQ1

IRQ4

Not used

Interrupt level enable bits (7-6, 4, 1, 0):

0 = Disable (mask) interrupt

1 = Enable (un-mask) interrupt

NOTE:

Before IMR register is changed to any value, all interrupts must be disable.

Using DI instruction is recommended.

Figure 5-6. Interrupt Mask Register (IMR)

5-11


INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels used in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

When more than one interrupt source is active, the source with the highest priority level is serviced first. If both sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7):

Group A IRQ0, IRQ1

Group C IRQ6, IRQ7

IPR

Group A

A1 A2

IPR

Group B

IPR

Group C

C1 C2

IRQ0 IRQ1 IRQ4 IRQ6 IRQ7

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B' would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3, and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 implementation, interrupt levels 2 and 3 are not used.

Therefore, IPR.2 and IPR.3 settings are not evaluated, as IRQ4 is the only remaining level in the group.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12


MSB .7

.6

Interrupt Priority Register (IPR)

FFH, Set 1, Bank 0, R/W

.5

.4

.3

.2

.1

.0

LSB

Group priority:

D7 D4 D1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

= Undefined

= B > C > A

= A > B > C

= B > A > C

= C > A > B

= C > B > A

= A > C > B

= Undefined

Group A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

Group B

(note)

0 = IRQ4

1 = IRQ4

Subgroup B

(note)

0 = IRQ4

1 = IRQ4

Group C

(note)

0 = IRQ6, IRQ7

1 = IRQ6, IRQ7

Subgroup C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

NOTE: In this device interrupt structure, only levels IRQ0, IRQ1, IRQ4, IRQ6-IRQ7 are used. Settings for group/subgroup B, which control relative priorities for levels IRQ2, IRQ3 and IRQ5, are therefore not evaluated.

Figure 5-8. Interrupt Priority Register (IPR)

5-13


INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level; a "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the

IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to "0".

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled.

MSB .7

.6

Interrupt Request Register (IRQ)

DCH, Set 1, Read-only

.5

.4

.3

.2

.1

.0

LSB

IRQ7

IRQ6

Not used

IRQ4

Not used

Not used

IRQ1

IRQ0

Interrupt level request pending bits:

0 = Interrupt level is not pending

1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

5-14


INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software.

In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1), and the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit must be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source's mode or control register.

In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure, pending conditions for all interrupt sources except the timer 0 and timer 1 overflow interrupts and the counter A borrow interrupt, must be cleared by the interrupt service routine.

5-15


INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one level is currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The

CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request.

5-16


GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs).

4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the above procedure to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is used by all S3C8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The IP register names are

IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to "1".

5-17


FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime").

NOTE

For the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller, the service routine for any one of the five interrupt levels: IRQ0, IRQ1, IRQ4 or IRQ6–IRQ7, can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' ("FLAGS prime") register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back.

6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed, and the other type must be cleared by the application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type of pending condition clear function — by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends.

5-18

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 INSTRUCTION SET

6

INSTRUCTION SET

OVERVIEW

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."


There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative

(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section

3, "Addressing Modes."

6-1

INSTRUCTION SET S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Mnemonic

Load Instructions

CLR

LD

LDB

LDE

LDC

LDED

LDCD

LDEI

LDCI

LDEPD

LDCPD

LDEPI

LDCPI

LDW

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI dst dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst dst, src dst, src

Src dst, src dst, src

Table 6-1. Instruction Group Summary

Operands Instruction

Clear

Load

Load bit

Load external data memory

Load program memory

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

Load word

Pop from stack

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

Push user stack (decrementing)

Push user stack (incrementing)

6-2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Mnemonic

Table 6-1. Instruction Group Summary (Continued)


ADC

ADD

CP

DA

DEC

DECW

DIV

INC

INCW

MULT

SBC

SUB

Arithmetic Instructions

dst,src dst,src dst,src dst dst dst dst,src dst dst dst,src dst,src dst,src

Add with carry

Add

Compare

Decimal adjust

Decrement

Decrement word

Divide

Increment

Increment word

Multiply

Subtract with carry

Subtract

Logic Instructions

AND

COM

OR

XOR dst,src dst dst,src dst,src

Logical AND

Complement

Logical OR

Logical exclusive OR

INSTRUCTION SET

6-3


BAND

BCP

BITC

BITR

BITS

BOR

BXOR

TCM

TM

Mnemonic

Table 6-1. Instruction Group Summary (Continued)


Program Control Instructions

EXIT

IRET

JP

JP

JR

NEXT

RET

WFI

BTJRF

BTJRT

CALL

CPIJE

CPIJNE

DJNZ

ENTER

Bit Manipulation Instructions

dst,src dst,src dst dst,src dst,src r,dst cc,dst dst cc,dst

Bit test and jump relative on false

Bit test and jump relative on true

Call procedure

Compare, increment and jump on equal

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit

Interrupt return

Jump on condition code

Jump unconditional

Jump relative on condition code

Next

Return

Wait for interrupt dst,src dst,src dst dst dst dst,src dst,src dst,src dst,src

Bit AND

Bit compare

Bit complement

Bit reset

Bit set

Bit OR

Bit XOR

Test complement under mask

Test under mask

6-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

CCF

DI

EI

IDLE

NOP

RCF

SB0

SB1

SCF

SRP

SRP0

SRP1

STOP

Mnemonic

Table 6-1. Instruction Group Summary (Concluded)


Rotate and Shift Instructions

RL

RLC

RR dst dst dst

RRC

SRA

SWAP

CPU Control Instructions

dst dst dst

Rotate left

Rotate left through carry

Rotate right

Rotate right through carry

Shift right arithmetic

Swap nibbles src src src

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

INSTRUCTION SET

6-5


FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits,

FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.

MSB

Carry flag (C)

Zero flag (Z)

.7

.6

System Flags Register (FLAGS)

D5H, Set 1, R/W

.5

.4

.3

.2

.1

Sign flag (S)

.0

LSB

Bank address status flag (BA)

First interrupt status flag (FIS)

Half-carry flag (H)

Overflow (V) Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6


FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

S

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.

V

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than –

128. It is also cleared to "0" following logic operations.

D

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition.

H

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program.

FIS

Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed.

BA

Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.

6-7


INSTRUCTION SET NOTATION

Flag

H

0

1

*

– x

C

Z

S

V

D

Table 6-2. Flag Notation Conventions

Description

Carry flag

Zero flag

Sign flag

Overflow flag

Decimal-adjust flag

Half-carry flag

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

Symbol

dst src

@

PC

IP

FLAGS

RP

#

H

D

B opc

Table 6-3. Instruction Set Symbols

Description

Destination operand

Source operand

Indirect register address prefix

Program counter

Instruction pointer

Flags register (D5H)

Register pointer

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

Opcode

6-8


Table 6-4. Instruction Notation Conventions

Notation

rr

R

Rb

RR cc r rb r0

IA

Ir

IR

Irr

IRR

X

XS xl da ra im iml

Description Actual Operand Range

Condition code

Working register only

Bit (b) of working register

Bit 0 (LSB) of working register

Working register pair

Register or working register

Bit 'b' of register or working register

Register pair or working register pair

See list of condition codes in Table 6-6.

Rn (n = 0–15)

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0–255, n = 0–15) reg.b (reg = 0–255, b = 0–7) reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14)

Indirect addressing mode

Indirect working register only

Direct addressing mode

Relative addressing mode

Immediate addressing mode

Immediate (long) addressing mode addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Indirect working register pair only @RRp (p = 0, 2, ..., 14)

Indirect register pair or indirect working register pair

Indexed addressing mode

Indexed (short offset) addressing mode

@RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14)

#reg [Rn] (reg = 0–255, n = 0–15)

Indexed (long offset) addressing mode

#addr [RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14)

#addr [RRp] (addr = range 0–65535, where p = 0, 2, ..., 14) addr (addr = range 0–65535) addr (addr = number in the range +127 to –128 that is an offset relative to the address of the next instruction)

#data (data = 0–255)

#data (data = range 0–65535)

6-9


H

E

E

X

B

L

I

B

N

E

R

U

P

P

A

B

C

D

E

F

8

9

6

7

1

2

–

0

3

4

5

DECW

RR1

RL

R1

INCW

RR1

CLR

R1

DA

R1

POP

R1

COM

R1

PUSH

R2

RRC

R1

SRA

R1

RR

R1

SWAP

R1

0

DEC

R1

RLC

R1

INC

R1

JP

IRR1

DECW

IR1

RL

IR1

INCW

IR1

CLR

IR1

DA

IR1

POP

IR1

COM

IR1

PUSH

IR2

1

DEC

IR1

RLC

IR1

INC

IR1

SRP/0/1

IM

RRC

IR1

SRA

IR1

RR

IR1

SWAP

IR1

Table 6-5. Opcode Quick Reference

OR r1,r2

AND r1,r2

TCM r1,r2

TM r1,r2

PUSHUD

IR1,R2

POPUD

IR2,R1

CP r1,r2

XOR r1,r2

CPIJE

Ir,r2,RA

CPIJNE

Irr,r2,RA

LDCD r1,Irr2

LDCPD r2,Irr1

OPCODE MAP

LOWER NIBBLE (HEX)

2

ADD r1,r2

3

ADD r1,Ir2

4

ADD

R2,R1

ADC r1,r2

SUB r1,r2

SBC r1,r2

ADC r1,Ir2

SUB r1,Ir2

SBC r1,Ir2

ADC

R2,R1

SUB

R2,R1

SBC

R2,R1

OR r1,Ir2

AND r1,Ir2

TCM r1,Ir2

TM r1,Ir2

PUSHUI

IR1,R2

POPUI

IR2,R1

CP r1,Ir2

XOR r1,Ir2

LDC r1,Irr2

LDC r2,Irr1

LDCI r1,Irr2

LDCPI r2,Irr1

LDW

RR2,RR1

CALL

IA1

LD

R2,R1

CALL

IRR1

OR

R2,R1

AND

R2,R1

TCM

R2,R1

TM

R2,R1

MULT

R2,RR1

DIV

R2,RR1

CP

R2,R1

XOR

R2,R1

OR

IR2,R1

AND

IR2,R1

TCM

IR2,R1

TM

IR2,R1

MULT

IR2,RR1

DIV

IR2,RR1

CP

IR2,R1

XOR

IR2,R1

LDW

IR2,RR1

5

ADD

IR2,R1

ADC

IR2,R1

SUB

IR2,R1

SBC

IR2,R1

LD

R2,IR1

LD

IR2,R1

7

BOR r0–Rb

BCP r1.b, R2

BXOR r0–Rb

BTJR r2.b, RA

LDB r0–Rb

BITC r1.b

BAND r0–Rb

BIT r1.b

LD r1, x, r2

LD r2, x, r1

LDC r1, Irr2, xL

LDC r2, Irr2, xL

LD r1, Ir2

LD

Ir1, r2

LDC r1, Irr2, xs

LDC r2, Irr1, xs

MULT

IM,RR1

DIV

IM,RR1

CP

R1,IM

XOR

R1,IM

OR

R1,IM

AND

R1,IM

TCM

R1,IM

TM

R1,IM

6

ADD

R1,IM

ADC

R1,IM

SUB

R1,IM

SBC

R1,IM

LDW

RR1,IML

LD

IR1,IM

LD

R1,IM

CALL

DA1

6-10


E

R

U

P

P

B

B

L

N

I

E

H

E

X

B

C

D

E

F

8

9

A

3

4

5

6

7

1

2

–

0

↓

↓

LD r1,R2

8

LD r1,R2

↓

↓

LD r2,R1

↓

Table 6-5. Opcode Quick Reference (Continued)

9

OPCODE MAP

LOWER NIBBLE (HEX)

A B C D

LD r2,R1

↓

DJNZ r1,RA

↓

JR cc,RA

↓

LD r1,IM

↓

JP cc,DA

↓

↓ ↓ ↓ ↓

↓

DJNZ r1,RA

↓

JR cc,RA

↓

LD r1,IM

↓

JP cc,DA

↓

E

INC r1

↓

↓

INC r1

F

NEXT

IRET

RCF

SCF

DI

EI

RET

CCF

NOP

ENTER

EXIT

WFI

SB0

SB1

IDLE

STOP

6-11


CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions.

Binary

0000

1000

0111

(note)

1111

(note)

0110

(note)

1110

(note)

1101

0101

0100

1100

0110

(note)

1110

(note)

1001

0001

1010

0010

1111

(note)

0111

(note)

1011

0011

F

T

C

NC

Z

NZ

PL

MI

OV

NOV

EQ

NE

GE

LT

GT

LE

UGE

ULT

Mnemonic

UGT

ULE

Table 6-6. Condition Codes

Always false

Always true

Carry

No carry

Zero

Not zero

Plus

Minus

Overflow

No overflow

Equal

Not equal

Description

Greater than or equal

Less than

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

–

–

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

Flags Set

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12


INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

6-13


ADC

— Add with carry

ADC

dst,src

Operation:

dst

←

dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise.

Format:

opc opc opc dst | src src dst dst src

Bytes Cycles Opcode

(Hex)

2 4

6

12

13

3 6

6

14

15

3 6 16

R

R

R

Addr Mode dst src

r r r lr

R

IR

IM

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:

ADC R1,R2

→

R1 = 14H, R2 = 03H

ADC R1,@R2

→

R1 = 1BH, R2 = 03H

ADC 01H,02H

→

Register 01H = 24H, register 02H = 03H

ADC 01H,@02H

→

Register 01H = 2BH, register 02H = 03H

ADC 01H,#11H

→

Register 01H = 32H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-14


ADD

— Add

ADD

dst,src

Operation:

dst

←

dst + src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if a carry from the low-order nibble occurred.

Format:



(Hex)

2 4 02

6 03

3

3

6

6

6

04

05

06

R

R

R


r r r lr

R

IR

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD R1,R2

→

R1 = 15H, R2 = 03H

ADD R1,@R2

→

R1 = 1CH, R2 = 03H

ADD 01H,02H

→


ADD 01H,@02H

→

Register 01H = 2BH, register 02H = 03H

ADD 01H,#25H

→

Register 01H = 46H

In the first example, destination working register R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register

R1.

6-15


AND

— Logical AND

AND

dst,src

Operation:

dst

←

dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.

Flags:

C: Unaffected.


S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:



(Hex)

2 4 52

6 53

3

3

6

6

6

54

55

56

R

R

R


r r r lr

R

IR

IM

Examples:


AND R1,R2

→

R1 = 02H, R2 = 03H

AND R1,@R2

→

R1 = 02H, R2 = 03H

AND 01H,02H

→


AND 01H,@02H

→


AND 01H,#25H

→

Register 01H = 21H

In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-16


BAND

— Bit AND

BAND

dst,src.b

BAND

Operation:

Flags:

Format:

dst.b,src dst(0)

←

dst(0) AND src(b) or dst(b)

←

dst(b) AND src(0)

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected. opc opc dst | b | 0 src | b | 1 src dst


(Hex)

3 6 67

3 6 67


r0 Rb

Rb r0

NOTE: In the second byte of the 3-byte instruction formats, the destinati on (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND R1,01H.1

→

R1 = 06H, register 01H = 05H

BAND 01H.1,R1

→

Register 01H = 05H, R1 = 07H

In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value

06H (00000110B) in register R1.

6-17


BCP

— Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.

Flags:

C: Unaffected.

Z: Set if the two bits are the same; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

opc dst | b | 0 src


(Hex)

3 6 17


r0 Rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, a nd the LSB address value is one bit in length.

Example:


BCP R1,01H.1

→


If destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18


BITC

— Bit Complement

BITC

Operation:

Flags:

dst.b dst(b)

←

NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other bits in the destination.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:


(Hex)

2 4 57

Addr Mode dst

rb opc dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four b its, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H

BITC R1.1

→

R1 = 05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.

6-19


BITR

— Bit Reset

BITR

Operation: dst.b dst(b)

←

0

The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination.

No flags are affected.

Flags:

Format:

opc dst | b | 0


(Hex)

2 4 77

Addr Mode dst

rb

NOTE: In the second byte of the ins truction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITR R1.1

→

R1 = 05H

If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).

6-20


BITS

— Bit Set

BITS

Operation: dst.b dst(b)

←

1

The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination.


Flags:

Format:

opc dst | b | 1


(Hex)

2 4 77

Addr Mode dst

rb

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b ' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITS R1.3

→

R1 = 0FH

If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).

6-21


BOR

— Bit OR

BOR

BOR

Operation:

Flags:

Format:

dst,src.b dst.b,src dst(0)

←

dst(0) OR src(b) or dst(b)

←

dst(b) OR src(0)

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.



(Hex)

3 6 07

3 6 07


r0

Rb

Rb r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:


BOR R1, 01H.1

→


BOR 01H.2, R1

→


In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically

ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H.

6-22


BTJRF

— Bit Test, Jump Relative on False

BTJRF

Operation:

Flags:

dst,src.b

If src(b) is a "0", then PC

←

PC + dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed.


Format:

(Note 1) src | b | 0


(Hex)

3 10 37


RA rb opc dst

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRF SKIP,R1.3

→

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-23


BTJRT

— Bit Test, Jump Relative on True

BTJRT

Operation: dst,src.b

If src(b) is a "1", then PC

←

PC + dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed.


Flags:

Format:

opc

(Note 1) src | b | 1 dst


(Hex)

3 10 37


RA rb

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRT SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-24


BXOR

— Bit XOR

BXOR

BXOR

Operation:

Flags:

Format:


←

dst(0) XOR src(b) or dst(b)

←

dst(b) XOR src(0)

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

C: Unaffected.


S: Cleared to "0".

V: Undefined.

D: Unaffected.



(Hex)

3 6 27

3 6 27


r0

Rb

Rb r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

BXOR R1,01H.1

→


BXOR 01H.2,R1

→


In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.

6-25


CALL

— Call Procedure

CALL

Operation: dst

SP

←

@SP

←

SP

←

@SP

←

PC

←

SP – 1

PCL

SP –1

PCH dst

The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter.


Flags:

Format:

opc opc opc dst dst dst


(Hex)

3 14 F6

2 12 F4

2 14 D4

Addr Mode dst

DA

IRR

IA

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

CALL 3521H

→

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where

4AH is the address that follows the instruction.)

CALL @RR0

→

SP = 0000H (0000H = 1AH, 0001H = 49H)

CALL #40H

→

SP = 0000H (0000H = 1AH, 0001H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the value

0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location

0001H (because the two-byte instruction format was used). The PC is then loaded with the value

3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement

"CALL #40H" produces the same result as in the second example.

6-26


CCF

— Complement Carry Flag

CCF

Operation:

Flags:

C

←

NOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

C: Complemented.

No other flags are affected.

Format:

opc


(Hex)

1 4 EF

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.

6-27


CLR

— Clear

CLR

Operation: dst dst

←

"0"

The destination location is cleared to "0".


Flags:

Format:

opc dst


(Hex)

2 4

4

B0

B1

Addr Mode dst

R

IR

Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR 00H

→

Register 00H = 00H

CLR @01H

→


In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.

6-28


COM

— Complement

COM

Operation:

Flags:

Format:

dst dst

←

NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa.

C: Unaffected.



V: Always reset to "0".

D: Unaffected.

H: Unaffected. opc dst


(Hex)

2 4

4

60

61

Addr Mode dst

R

IR

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM R1

→

R1 = 0F8H

COM @R1

→

R1 = 07H, register 07H = 0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29


CP

— Compare

CP

Operation:

Flags:

Format:

dst,src dst – src

The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.

C: Set if a "borrow" occurred (src > dst); cleared otherwise.



V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected. opc opc opc dst | src src dst dst src


(Hex)

2 4 A2

6 A3

3

3

6

6

6

A4

A5

A6

R

R

R


r r r lr

R

IR

IM

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2

→

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value

03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value

(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".

2. Given: R1 = 05H and R2 = 0AH:

CP R1,R2

JP UGE,SKIP

INC R1

SKIP LD R3,R1

In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.

6-30


CPIJE

— Compare, Increment, and Jump on Equal

CPIJE

Operation: dst,src,RA

If dst – src = "0", PC

←

PC + RA

Ir

←

Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed.


Flags:

Format:

opc src dst RA


(Hex)

3 12 C2


r Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

CPIJE R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H

(00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-31


CPIJNE

— Compare, Increment, and Jump on Non-Equal

CPIJNE

Operation: dst,src,RA

If dst – src "0", PC

←

PC + RA

Ir

←

Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction.


Flags:

Format:

opc src dst RA


(Hex)

3 12 D2


r Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

CPIJNE R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value 03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H

(00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-32


DA

— Decimal Adjust

DA


←

DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits):

Instruction

ADD

ADC

SUB

SBC

Carry

Before DA

0

0

0

0

0

0

1

1

1

0

0

1

1

Bits 4–7

Value (Hex)

0–9

0–8

0–9

A–F

9–F

A–F

0–2

0–2

0–3

0–9

0–8

7–F

6–F

H Flag

Before DA

0

0

1

0

0

1

0

0

1

0

1

0

1

Bits 0–3

Value (Hex)

0–9

A–F

0–3

0–9

A–F

0–3

0–9

A–F

0–3

0–9

6–F

0–9

6–F

Number Added to Byte

00

06

06

60

66

66

60

66

66

00 = – 00

FA = – 06

A0 = – 60

9A = – 66

Carry

After DA

0

0

0

1

1

1

1

1

1

0

0

1

1

Flags:

Format:

C: Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z: Set if result is "0"; cleared otherwise.

S: Set if result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.



(Hex)

2 4

4

40

41

Addr Mode dst

R

IR

6-33


DA

— Decimal Adjust

DA

Example:

(Continued)

Given: Working register R0 contains the value 15 (BCD), working register R1 contains

27 (BCD), and address 27H contains 46 (BCD):

ADD

DA

R1,R0

R1

;

;

C

←

"0", H

←

"0", Bits 4–7 = 3, bits 0–3 = C, R1

←

3CH

R1

←

3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic:

0 0 0 1 0 1 0 1

+ 0 0 1 0 0 1 1 1

15

27

0 0 1 1 1 1 0 0 = 3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1 1 1 0 0

+ 0 0 0 0 0 1 1 0

0 1 0 0 0 0 1 0 = 42

Assuming the same values given above, the statements

SUB 27H,R0 ; C

←

"0", H

←

"0", Bits 4–7 = 3, bits 0–3 = 1

DA @R1 ; @R1

←

31–0 leave the value 31 (BCD) in address 27H (@R1).

6-34


DEC

— Decrement

DEC

Operation:

Flags:

Format:

dst dst

←

dst – 1

The contents of the destination operand are decremented by one.

C: Unaffected.


S: Set if result is negative; cleared otherwise.


D: Unaffected.



(Hex)

2 4

4

00

01

Addr Mode dst

R

IR

Examples:


DEC R1

→

R1 = 02H

DEC @R1

→

Register 03H = 0FH

In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.

6-35


DECW

— Decrement Word

DECW

Operation:

Flags:

Format:

dst dst

←

dst – 1

The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.

C: Unaffected.




D: Unaffected.



(Hex)

2 8

8

80

81

Addr Mode dst

RR

IR

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW RR0

→

R0 = 12H, R1 = 33H

DECW @R2

→

Register 30H = 0FH, register 31H = 20H

NOTE:

In the first example, destination register R0 contains the value 12H and register R1 the value 34H.

The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H.

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example:

LOOP: DECW RR0

LD R2,R1

OR R2,R0

JR NZ,LOOP

6-36


DI

— Disable Interrupts

DI

Operation: SYM (0)

←

0

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.


Flags:

Format:

opc


(Hex)

1 4 8F

Example:

Given: SYM = 01H:

DI

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing.

Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

6-37


DIV

— Divide (Unsigned)

DIV

dst,src

Operation: dst ÷ src dst (UPPER) dst (LOWER)

←

←

REMAINDER

QUOTIENT

Flags:

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is

≥

2

8

, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers.

C: Set if the V flag is set and quotient is between 2

8

and 2

Z: Set if divisor or quotient = "0"; cleared otherwise.

S: Set if MSB of quotient = "1"; cleared otherwise.

9

–1; cleared otherwise.

V: Set if quotient is

≥

2

8 or if divisor = "0"; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

opc src dst


(Hex)

3 26/10 94

26/10

26/10

95

96

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.


RR

RR

RR

R

IR

IM

Examples:

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

DIV RR0,R2

→

R0 = 03H, R1 = 40H

DIV RR0,@R2

→

R0 = 03H, R1 = 20H

DIV RR0,#20H

→

R0 = 03H, R1 = 80H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H

(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value

03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register

RR0 (R0) and the quotient in the lower half (R1).

6-38


DJNZ

— Decrement and Jump if Non-Zero

DJNZ

Operation: r,dst r

←

r – 1

If r

≠

0, PC

←

PC + dst

The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is

+127 to –128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

Flags:

Format:

No flags are affected. r | opc dst

Bytes

2

Cycles

8 (jump taken)

8 (no jump)

Opcode

(Hex)

rA r = 0 to F

Addr Mode dst

RA

Example:

Given: R1 = 02H and LOOP is the label of a relative address:

SRP #0C0H

DJNZ R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.

6-39


EI

— Enable Interrupts

EI

Operation: SYM (0)

←

1

An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.


Flags:

Format:

opc


(Hex)

1 4 9F

Example:

Given: SYM = 00H:

EI

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement

"EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.)

6-40


ENTER

— Enter

ENTER

Operation: SP

←

SP – 2

@SP

←

IP

IP

←

PC

PC

←

@IP

IP

←

IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two.


Flags:

Format:

opc


(Hex)

1 14 1F

Example:

The diagram below shows one example of how to use an ENTER statement.

Address

IP

0050

Data

PC

SP

0040

0022

Before

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

22 Data

Stack

Memory

Address

IP

0043

Data

After

PC

SP

0110

0020

Address

40

41

42

43

Enter

Address H

Address L

Address H

Data

1F

01

10

20

21

22

IPH

IPL

Data

Stack

00

50

110 Routine

Memory

6-41


EXIT

— Exit

EXIT

Operation: IP

←

@SP

SP

←

SP + 2

PC

←

@IP

IP

←

IP + 2

This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.


Flags:

Format:

opc

Bytes

1

Cycles

14 (internal stack)

16 (internal stack)

Opcode (Hex)

2F

Example:

The diagram below shows one example of how to use an EXIT statement.

Before

Address

IP

0050

Data

Address

PC 0040

Data

50

51

PCL old

PCH

60

00

SP

0022

140 Exit 2F

20

21

22

IPH

IPL

Data

Stack

00

50

Memory

Address

IP

0052

Data

After

Address

PC 0060

60 Main

SP

0022

22 Data

Stack

Memory

Data

6-42


IDLE

— Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.


Flags:

Format:

opc


(Hex)

1 4 6F


– –

Example:

The instruction

IDLE stops the CPU clock but not the system clock.

6-43


INC

— Increment

INC

Operation:

Flags:

Format:

dst dst

←

dst + 1

The contents of the destination operand are incremented by one.

C: Unaffected.




D: Unaffected.

H: Unaffected. dst | opc opc dst


(Hex)

1 4 rE r = 0 to F

2 4

4

20

21

Addr Mode dst

r

R

IR

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC R0

→

R0 = 1CH

INC 00H

→

Register 00H = 0DH

INC @R0

→

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.

6-44


INCW

— Increment Word

INCW

Operation:

Flags:

Format:

dst dst

←

dst + 1

The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

C: Unaffected.




D: Unaffected.



(Hex)

2 8

8

A0

A1

Addr Mode dst

RR

IR

Examples:

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

INCW RR0

→

R0 = 1AH, R1 = 03H

INCW @R1

→


NOTE:

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value

03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 00H and register

02H from 0FH to 10H.

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example:

LOOP: INCW

LD

OR

JR

RR0

R2,R1

R2,R0

NZ,LOOP

6-45


IRET

— Interrupt Return

IRET

Operation:

IRET (Normal) IRET (Fast)

FLAGS

←

@SP

SP

←

SP + 1

PC

←

@SP

SP

←

SP + 2

SYM(0)

←

1

PC

FIS

↔

FLAGS

←

IP

←

0

FLAGS'

This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Flags:

Format:

Bytes Cycles Opcode (Hex)

IRET

(Normal) opc

IRET

(Fast) opc

1

Bytes

1

10 (internal stack)

12 (internal stack)

Cycles

6

BF

Opcode (Hex)

BF

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H.

0H

FFH

100H

IRET

Interrupt

Service

Routine

JP to FFH

NOTE:

FFFFH

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the IPR register).

6-46


JP

— Jump

JP

JP

Operation:

Flags:

Format:

(1)

cc,dst (Conditional) dst (Unconditional)

If cc is true, PC

←

dst

The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC.


(2) cc | opc opc dst dst


(Hex)

3 8 ccD cc = 0 to F

2 8 30

Addr Mode dst

DA

IRR

NOTES:

1. The 3-byte format is used for a conditional jump and the 2 -byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

JP

JP

C,LABEL_W

→

LABEL_W = 1000H, PC = 1000H

@00H

→

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47


JR

— Jump Relative

JR

Operation: cc,dst

If cc is true, PC

←

PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes).

The range of the relative address is +127, –128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement.


Flags:

Format:

(1) cc | opc dst


(Hex)

2 6 ccB cc = 0 to F

Addr Mode dst

RA

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

JR C,LABEL_X

→

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.

6-48


LD

— Load

LD

Operation: dst,src dst

←

src

The contents of the source are loaded into the destination. The source's contents are unaffected.


Flags:

Format:

opc opc opc opc opc dst | opc src | opc opc src dst dst | src src dst src dst | src src | dst dst src x x dst


(Hex)

2

2

2

3

3

3 rC r8 r9 r = 0 to F

C7

D7

E4

E5

E6

D6

F5

6

6

6

6

6

4

4

4

4

4

3

3

6

6

87

97


R

IR

IR

R

R r

Ir r r

R r x [r] x [r] r

IM

IM

R

R

IR lr r

IM

R r

6-49


LD

— Load

LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

LD R0,#10H

→

R0 = 10H

LD R0,01H

→


LD 01H,R0

→


LD R1,@R0

→

R1 = 20H, R0 = 01H

LD @R0,R1

→

R0 = 01H, R1 = 0AH, register 01H = 0AH

LD 00H,01H

→


LD 02H,@00H

→


LD 00H,#0AH

→

Register 00H = 0AH

LD @00H,#10H

→


LD @00H,02H

→

Register 00H = 01H, register 01H = 02, register 02H = 02H

LD R0,#LOOP[R1]

→

R0 = 0FFH, R1 = 0AH

LD #LOOP[R0],R1

→

Register 31H = 0AH, R0 = 01H, R1 = 0AH

6-50


LDB

— Load Bit

LDB

LDB

Operation:

Flags:

Format:


←

src(b) or dst(b)

←

src(0)

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected.

No flags are affected. opc opc dst | b | 0 src | b | 1 src dst


(Hex)

3 6 47

3 6 47


r0 Rb

Rb r0

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

LDB

LDB

R0,00H.2

→

00H.0,R0

→



In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H.

6-51


LDC/LDE

— Load Memory

LDC/LDE


←

src

This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.


Flags:

Format:

1. opc

2. opc

3. opc

4. opc

5. opc

6.

7.

8.

9.

10. opc opc opc opc opc dst | src src | dst dst | src src | dst dst | src src | dst dst | 0000 src | 0000 dst | 0001 src | 0001

DA

L

DA

L

DA

L

XS

XS

XL

L

XL

L

DA

L

XL

H

XL

H

DA

H

DA

DA

DA

H

H

H


(Hex)

2 10 C3

2

3

10

12

D3

E7

3

4

12

14

F7

A7

4

4

4

4

4

14

14

14

14

14

B7

A7

B7

A7

B7


r Irr

Irr r

XS [rr] r

XL [rr] r

DA r

DA r

XS [rr] r

XL [rr]

DA r r

DA r

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0 –1.

2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.

3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.

6-52


LDC/LDE

— Load Memory

LDC/LDE

Examples:

(Continued)

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations

0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations

0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

LDC R0,@RR2 ; R0

←

contents of program memory location 0104H

; R0 = 1AH, R2 = 01H, R3 = 04H

LDE R0,@RR2 ; R0

←

contents of external data memory location 0104H

; R0 = 2AH, R2 = 01H, R3 = 04H

LDC

(note)

@RR2,R0 ; 11H (contents of R0) is loaded into program memory

; location 0104H (RR2),

; working registers R0, R2, R3

→

no change

LDE

LDC

LDE

LDC

@RR2,R0

R0,#01H[RR2]

; 11H (contents of R0) is loaded into external data memory

; location 0104H (RR2),

; working registers R0, R2, R3

→

no change

; R0

←


; (01H + RR2),

; R0 = 6DH, R2 = 01H, R3 = 04H

; R0

←


; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDE R0,#01H[RR2]

LDC

(note)

#01H[RR2],R0

LDE

LDC

LDE

; 11H (contents of R0) is loaded into program memory location

; 0105H (01H + 0104H)

#01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory

; location 0105H (01H + 0104H)

R0,#1000H[RR2] ; R0

←


; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

R0,#1000H[RR2] ; R0

←


; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

R0,1104H

R0,1104H

; R0

←

contents of program memory location 1104H, R0 = 88H

; R0

←

contents of external data memory location 1104H,

; R0 = 98H

LDC

(note)

1105H,R0

LDE 1105H,R0

; 11H (contents of R0) is loaded into program memory location

; 1105H, (1105H)

←

11H

; 11H (contents of R0) is loaded into external data memory

; location 1105H, (1105H)

←

11H

NOTE: These instructions are not supported by masked ROM type devices.

6-53


LDCD/LDED

— Load Memory and Decrement

LDCD/LDED

dst,src

Operation: dst

←

src rr

←

rr – 1

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory.


Flags:

Format:

opc dst | src


(Hex)

2 10 E2


r Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH:

LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6

←

RR6 – 1)

LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6

←

RR6 – 1)

; R8 = 0DDH, R6 = 10H, R7 = 32H

6-54


LDCI/LDEI

— Load Memory and Increment

LDCI/LDEI


←

src rr

←

rr + 1

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory.


Flags:

Format:

opc dst | src


(Hex)

2 10 E3


r Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

←

RR6 + 1)

; R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

←

RR6 + 1)

; R8 = 0DDH, R6 = 10H, R7 = 34H

6-55


LDCPD/LDEPD

— Load Memory with Pre-Decrement

LDCPD/

LDEPD

Operation: dst,src rr

←

rr – 1 dst

←

src

These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory.


Flags:

Format:

opc src | dst


(Hex)

2 14 F2


Irr r

Examples:

LDEPD @RR6,R0

;

6-56


LDCPI/LDEPI

— Load Memory with Pre-Increment

LDCPI/

LDEPI

Operation: dst,src rr

←

rr + 1 dst

←

src

These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes

'Irr' an even number for program memory and an odd number for data memory.


Flags:

Format:

opc src | dst


(Hex)

2 14 F3


Irr r

Examples:

LDEPI @RR6,R0

6-57


LDW

— Load Word

LDW


←

src

The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected.


Flags:

Format:

opc opc src dst dst src


(Hex)

3 8 C4

8 C5

4 8 C6


RR RR

RR IR

RR IML

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH:

LDW

LDW

LDW

LDW

LDW

LDW

RR6,RR4

00H,02H

RR2,@R7

04H,@01H

RR6,#1234H

02H,#0FEDH

→

→

→

→

→

→

R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH

R2 = 03H, R3 = 0FH,

Register 04H = 03H, register 05H = 0FH

R6 = 12H, R7 = 34H

Register 02H = 0FH, register 03H = 0EDH

In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and formats.

6-58


MULT

— Multiply (Unsigned)

MULT

Operation:

Flags:

Format:

dst,src dst

←

dst

×

src

The 8-bit destination operand (even register of the register pair) is multiplied by the source operand

(8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.

Both operands are treated as unsigned integers.

C: Set if result is

>

255; cleared otherwise.


S: Set if MSB of the result is a "1"; cleared otherwise.

V: Cleared.

D: Unaffected.

H: Unaffected. opc src dst


(Hex)

3 22 84

22

22

85

86


RR R

RR

RR

IR

IM

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT

MULT

MULT

00H, 02H

→

Register 00H = 01H, register 01H = 20H, register 02H = 09H

00H, @01H

→

Register 00H = 00H, register 01H = 0C0H

00H, #30H

→


In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59


NEXT

— Next

NEXT

Operation: PC

←

@ IP

IP

←

IP + 2

The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.


Flags:

Format:

opc


(Hex)

1 10 0F

Example:

The following diagram shows one example of how to use the NEXT instruction.

Before

Address

IP

0043

Data

PC 0120

Address

43

44

45

Address H

Address L

Address H

01

10

Address

IP

0045

Data

After

PC 0130

Address

43

44

45

Address H

Address L

Address H

Data

120 Next

Memory

130 Routine

Memory

6-60


NOP

— No Operation

NOP

Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.


Flags:

Format:

opc


(Hex)

1 4 FF

Example:

When the instruction

NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.

6-61


OR

— Logical OR

OR

Operation:

Flags:

Format:

dst,src dst

←

dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored.

C: Unaffected.




D: Unaffected.



(Hex)

2 4 42

6 43

3

3

6

6

6

44

45

46

R

R

R


r r r lr

R

IR

IM

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH:

OR

OR

OR

OR

OR

R0,R1

R0,@R2

→

→

00H,01H

→

01H,@00H

→

00H,#02H

→

R0 = 3FH, R1 = 2AH

R0 = 37H, R2 = 01H, register 01H = 37H

Register 00H = 3FH, register 01H = 37H

Register 00H = 08H, register 01H = 0BFH

Register 00H = 0AH

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes and formats.

6-62


POP

— Pop From Stack

POP


←

@SP

SP

←

SP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.

No flags affected.

Flags:

Format:

opc dst


(Hex)

2 8

8

50

51

Addr Mode dst

R

IR

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H:

POP

POP

00H

@00H

→

→

Register 00H = 55H, SP = 00FCH

Register 00H = 01H, register 01H = 55H, SP = 00FCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH.

6-63


POPUD

— Pop User Stack (Decrementing)

POPUD


←

src

IR

←

IR – 1

This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.


Flags:

Format:

opc src dst


(Hex)

3 8 92


R IR

Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H:

POPUD 02H,@00H

→

Register 00H = 41H, register 02H = 6FH, register 42H = 6FH

If general register 00H contains the value 42H and register 42H the value 6FH, the statement

"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H.

6-64


POPUI

— Pop User Stack (Incrementing)

POPUI


←

src

IR

←

IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.


Flags:

Format:

opc src dst


(Hex)

3 8 93


R IR

Example:

Given: Register 00H = 01H and register 01H = 70H:

POPUI 02H,@00H

→


If general register 00H contains the value 01H and register 01H the value 70H, the statement

"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65


PUSH

— Push To Stack

PUSH

Operation: src

SP

←

SP – 1

@SP

←

src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.


Flags:

Format:

Bytes Cycles

opc src 2 8 (internal clock)

8 (external clock)

8 (internal clock)

8 (external clock)

Opcode

(Hex)

70

71

Addr Mode dst

R

IR

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

PUSH

PUSH

40H

@40H

→

→

Register 40H = 4FH, stack register 0FFH = 4FH,

SPH = 0FFH, SPL = 0FFH

Register 40H = 4FH, register 4FH = 0AAH, stack register

0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack.

6-66


PUSHUD

— Push User Stack (Decrementing)

PUSHUD

Operation: dst,src

IR

←

IR – 1 dst

←

src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.


Flags:

Format:

opc dst src


(Hex)

3 8 82


IR R

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:

PUSHUD @00H,01H

→


If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.

6-67


PUSHUI

— Push User Stack (Incrementing)

PUSHUI

Operation: dst,src

IR

←

IR + 1 dst

←

src

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.


Flags:

Format:

opc dst src


(Hex)

3 8 83


IR R

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:

PUSHUI @00H,01H

→


If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.

6-68

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RCF

— Reset Carry Flag

RCF

Operation:

Flags:

Format:

RCF

C

←

0

The carry flag is cleared to logic zero, regardless of its previous value.

C: Cleared to "0".

No other flags are affected. opc


(Hex)

1 4 CF

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

INSTRUCTION SET

6-69


RET

— Return

RET

Operation: PC

←

@SP

SP

←

SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value.


Flags:

Format:

Example:

opc

Bytes

1

Cycles

8 (internal stack)

10 (internal stack)

Opcode (Hex)

AF

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET

→

PC = 101AH, SP = 00FEH

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH.

6-70


RL

— Rotate Left

RL

Operation: dst

C

←

dst (7) dst (0)

←

dst (7) dst (n + 1)

←

dst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".




D: Unaffected.

H: Unaffected.

C

7 0

Flags:

Format:

Examples:

opc dst


(Hex)

2 4 90

4 91

Addr Mode dst

R

IR

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

RL

RL

00H

@01H

→

→

Register 00H = 55H, C = "1"

Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.

6-71


RLC

— Rotate Left Through Carry

RLC

Operation: dst dst (0)

←

C

C

←

dst (7) dst (n + 1)

←

dst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".



V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

C

7 0

Flags:

Format:

Examples:

opc dst


(Hex)

2 4

4

10

11

Addr Mode dst

R

IR

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

RLC

00H

@01H

→

→


Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC

00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The

MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-72


RR

— Rotate Right

RR

Operation: dst

C

←

dst (0) dst (7)

←

dst (0) dst (n

) ←

dst (n + 1), n = 0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit zero

(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

C

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".




D: Unaffected.

H: Unaffected.

7 0

Flags:

Format:

Examples:

opc dst


(Hex)

2 4

4

E0

E1

Addr Mode dst

R

IR

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

RR

RR

00H

@01H

→

→


Register 01H = 02H, register 02H = 8BH, C = "1"

In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR

00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the

C flag to "1" and the sign flag and overflow flag are also set to "1".

6-73


RRC

— Rotate Right Through Carry

RRC


←

C

C

←

dst (0) dst (n)

←

dst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7

(MSB).

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.



D: Unaffected.

H: Unaffected.

C

7 0

Flags:

Format:

Examples:

opc dst


(Hex)

2 4

4

C0

C1

Addr Mode dst

R

IR

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

RRC

00H

@01H

→

→

Register 00H = 2AH, C = "1"

Register 01H = 02H, register 02H = 0BH, C = "1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH

(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

6-74


SB0

— Select Bank 0

SB0

Operation: BANK

←

0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.


Flags:

Format:

opc


(Hex)

1 4 4F

Example: The statement

SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.

6-75


SB1

— Select Bank 1

SB1

Operation: BANK

←

1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontrollers.)


Flags:

Format:

opc


(Hex)

1 4 5F

Example:

The statement

SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

6-76


SBC

— Subtract With Carry

SBC

Operation:

Flags:

dst,src dst

←

dst – src – c

The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

C: Set if a borrow occurred (src

>

dst); cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow".

Format:



(Hex)

2 4 32

6 33

3

3

6

6

6

34

35

36

R

R

R


r r r lr

R

IR

IM

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

SBC

SBC

SBC

SBC

SBC

R1,R2

R1,@R2

→

→

01H,02H

→

01H,@02H

→

01H,#8AH

→

R1 = 0CH, R2 = 03H

R1 = 05H, R2 = 03H, register 03H = 0AH

Register 01H = 1CH, register 02H = 03H

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

Register 01H = 95H; C, S, and V = "1"

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.

6-77


SCF

— Set Carry Flag

SCF

Operation:

Flags:

Format:

C

←

1

The carry flag (C) is set to logic one, regardless of its previous value.

C: Set to "1".

No other flags are affected. opc


(Hex)

1 4 DF

Example:

The statement

SCF sets the carry flag to logic one.

6-78


SRA

— Shift Right Arithmetic

SRA


←

dst (7)

C

←

dst (0) dst (n)

←

dst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.

7 6 0

C

C: Set if the bit shifted from the LSB position (bit zero) was "1".




D: Unaffected.

H: Unaffected.

Flags:

Format:

Examples:

opc dst


(Hex)

2 4

4

D0

D1

Addr Mode dst

R

IR

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

SRA

00H

@02H

→

→

Register 00H = 0CD, C = "0"

Register 02H = 03H, register 03H = 0DEH, C = "0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value

0CDH (11001101B) in destination register 00H.

6-79


SRP/SRP0/SRP1

— Set Register Pointer

SRP

SRP0

SRP1

Operation: src src src

If src (1) = 1 and src (0) = 0 then: RP0 (3–7)

← src (3–7)


← src (3–7)


← src (4–7),

RP0 (3)

←

0

RP1 (4–7)

← src (4–7),

RP1 (3)

←

1

The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.


Flags:

Format:

opc src


(Hex)

2 4 31

Addr Mode src

IM

Examples:

The statement

SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H.

6-80


STOP

— Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed.


Flags:

Format:

opc


(Hex)

1 4 7F


– –

Example:

The statement

STOP halts all microcontroller operations.

6-81


SUB

— Subtract

SUB

Operation:

Flags:

dst,src dst

←

dst – src

The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

C: Set if a "borrow" occurred; cleared otherwise.



V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow".

Format:



(Hex)

2 4 22

6 23

3

3

6

6

6

24

25

26

R

R

R


r r r lr

R

IR

IM

Examples:


SUB

SUB

SUB

SUB

SUB

SUB

R1,R2

R1,@R2

→

→

01H,02H

→

01H,@02H

→

01H,#90H

→

01H,#65H

→

R1 = 0FH, R2 = 03H

R1 = 08H, R2 = 03H

Register 01H = 1EH, register 02H = 03H


Register 01H = 91H; C, S, and V = "1"

Register 01H = 0BCH; C and S = "1", V = "0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value

(12H) and stores the result (0FH) in destination register R1.

6-82


SWAP

— Swap Nibbles

SWAP

Operation: dst dst (0 – 3)

↔

dst (4 – 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

7 4 3 0

Flags:

Format:

C: Undefined.



V: Undefined.

D: Unaffected.

H: Unaffected.

Examples:

opc dst


(Hex)

2 4

4

F0

F1

Addr Mode dst

R

IR

Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:

SWAP

SWAP

00H

@02H

→

→

Register 00H = 0E3H

Register 02H = 03H, register 03H = 4AH

In the first example, if general register 00H contains the value 3EH (00111110B), the statement

"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value

0E3H (11100011B).

6-83


TCM

— Test Complement Under Mask

TCM

Operation:

Flags:

Format:

dst,src

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.

C: Unaffected.




D: Unaffected.



(Hex)

2 4 62

6 63

3

3

6

6

6

64

65

66

R

R

R


r r r lr

R

IR

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

TCM

TCM

TCM

TCM

TCM

R0,R1

R0,@R1

→

→

00H,01H

→

00H,@01H

→

00H,#34

→

R0 = 0C7H, R1 = 02H, Z = "1"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "1"

Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1"

Register 00H = 2BH, Z = "0"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a

"1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.

6-84


TM

— Test Under Mask

TM

Operation:

Flags:

Format:

dst,src dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.

C: Unaffected.




D: Unaffected.



(Hex)

2 4 72

6 73

3

3

6

6

6

74

75

76

R

R

R


r r r lr

R

IR

IM

Examples:


TM

TM

TM

TM

TM

R0,R1

R0,@R1

→

→

00H,01H

→

00H,@01H

→

00H,#54H

→

R0 = 0C7H, R1 = 02H, Z = "0"

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "0"

Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, Z = "1"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.

6-85


WFI

— Wait For Interrupt

WFI

Operation:

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .


Flags:

Format:

opc


(Hex)

1 4n

(

n = 1, 2, 3, … )

3F

Example:

The following sample program structure shows the sequence of operations that follow a "WFI" statement:

.

.

.

Main program

EI

WFI

.

.

.

(Next instruction)

Interrupt occurs

.

.

.

Interrupt service routine

Clear interrupt flag

IRET

(Enable global interrupt)

(Wait for interrupt)

Service routine completed

6-86


XOR

— Logical Exclusive OR

XOR

Operation:

Flags:

Format:

dst,src dst

←

dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

C: Unaffected.




D: Unaffected.



(Hex)

2 4 B2

6 B3

3

3

6

6

6

B4

B5

B6

R

R

R


r r r lr

R

IR

IM

Examples:


XOR

XOR

XOR

XOR

XOR

R0,R1

R0,@R1

→

→

00H,01H

→

00H,@01H

→

00H,#54H

→

R0 = 0C5H, R1 = 02H

R0 = 0E4H, R1 = 02H, register 02H = 23H



Register 00H = 7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

6-87

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 CLOCK CIRCUITS

7

CLOCK CIRCUITS

OVERVIEW

The clock frequency generated for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 by an external crystal, or supplied by an external clock source, can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register settings, is 8 MHz. The X

IN

and X

OUT

pins connect the external oscillator or clock source to the on-chip clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal or ceramic resonator oscillation source (or an external clock)

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (f

OSC

divided by 1, 2, 8, or 16)

— Clock circuit control register, CLKCON

C1 X

IN

C2 X

OUT

Figure 7-1. Main Oscillator Circuit

(External Crystal or Ceramic Resonator)

External

Clock

X

IN

Open Pin

X

OUT

Figure 7-2. External Clock Circuit

7-1

CLOCK CIRCUITS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by Power On

Reset operation or by a non-vectored interrupt - interrupt with reset (INTR). To enter the Stop mode, STOPCON

(STOP Control register) has to be loaded with value, #0A5H before STOP instruction execution. After recovering from the Stop mode by reset or interrupt, STOPCON register is automatically cleared.

— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (external or internally generated).

STOPCON

STOP

Instruction

CLKCON.3,.4

Oscillator

Stop

Main

OSC

Oscillator

Wake-up

Noise filter

1/2

1/8

1/16

M

U

X

CPU

Clock

INT Pin

(1)

NOTES:

1. An external interrupt with an RC-delay noise filter (for S3C80A4/C80A8/

C80A5/C80B4/C80B8/C80B5, INT0-4) is fiexed to release

Stop mode and "wake up" the main oscillator.

2. Because the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 has

no subsystem clock, the 3-bit CLKCON signature code (CLKCON.2-

CLKCON.0) is no meaning.

Figure 7-3. System Clock Circuit Diagram

7-2

S3C80A4/80A8/80A5/80B4/80B8/80B5 CLOCK CIRCUITS

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and has the following functions:

— Oscillator frequency divide-by value

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release.

(This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5.

After a reset, the main oscillator is activated, and the f

OSC

/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to f

OSC

, f

OSC

/2, or f

OSC

/8.

MSB .7

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Not used Not used

Not used

Divide-by selection bits for

CPU clock frequency:

00 = f

OSC

/16

01 = f

OSC

/8

10 = f

OSC

/2

11 = f

OSC

(non-divided)

Figure 7-4. System Clock Control Register (CLKCON)

7-3

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RESET

and POWER-DOWN

8

RESET and POWER-DOWN

SYSTEM RESET

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 has four different system reset sources as followings:

— Low Voltage Detect (LVD)

— Internal POR circuit

— INTR (Interrupt with RESET)

— Basic Timer (Watchdog timer)

LVD

Enable/Disable

Noise

Filter

Stop

STOPCON

INTR

POR

BT(WDT)

Figure 8-1. Reset Block Diagram

LVD RESET

The Low Voltage detect circuit is built on the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 product for system reset not in stop mode. When the operating status is not stop mode it detects a slope of V

DD

by comparing the voltage at V

DD

with V

LVD

(Low level Detect Voltage). The reset pulse is generated by the rising slope of V

DD

. While the voltage at V

DD

is rising up and passing V

LVD

, the reset pulse is occurred at the moment ”V

DD

>=

V

LVD

". This function is disabled when the operating state is "stop mode" to reduce the current consumption under 1 uA instead of 6 uA.

8-1

RESET

and POWER-DOWN S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

INTERRUPT WITH RESET(INTR)

A non vectored interrupt called Interrupt with reset (INTR) is built in

S3C80A4/C80A8/C80A5 /C80B4/C80B8/C80B5 to release stop status with system reset. When a falling/rising edge occurs at Port 0 during stop mode, INTR signal is generated and it makes the system reset pulse. An INTR signal is generated relating to interaction between Port 0 and operating status. It is enabled by STOP status and occurs by falling/rising edge at port0. So only when the chip status is "STOP", it is available. If the operating status is not stop status INTR does not occurs.

NOTE

This INTR is supplementary function to make system reset for an application which is using " stop mode" like remote controller. If an application which is not using "stop mode" , INTR function can be discarded.

WATCHDOG TIMER RESET

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 build a watch-dog timer that can recover to normal operation from abnormal function. Watchdog timer generates a system reset signal if not clearing a BT-Basic Counter within a specific time by program. System reset can return to the proper operation of chip.

POWER-ON RESET(POR)

The power-on reset circuit is built on the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 product. During a power-on reset, the voltage at V

DD

goes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High level. The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the Schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal capacitor, and a Schmitt trigger input transistor.

V

DD

R : On-Chip Resistor

C : On-Chip Capacitor

C

Schmitt Trigger Inverter

System Reset

V

SS

Figure 8-2. Power-on Reset Circuit

8-2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RESET

and POWER-DOWN

Voltage [V]

If Va voltage is under the 0.4 V

DD

, Reset pulse signal is gernerated.

If Va voltage is over than 0.4 VDD, Reset pulse is not gernerated.

TV

DD

(V

DD

Rising Time)

V

DD

Va

V

IH

= 0.85 V

DD

V

DD

V

IL

= 0.4 V

DD

Reset Pulse Width

Figure 8-3. Timing Diagram for Power-on Reset Circuit

Reset pulse

Time

SYSTEM RESET OPERATION

System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance. The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are then reset to their default hardware values (see Tables 5-1).

In summary, the following sequence of events occurs during a reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1 and 2 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see Table 5-

1).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location

0100H (and 0101H) is fetched and executed.

8-3

RESET


HARDWARE RESET VALUES

Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An 'x' means that the bit value is undefined after a reset.

— A dash ('-') means that the bit is either not used or not mapped (but a 0 is read from the bit position)

Register Name

Timer 0 counter (read-only)

Timer 0 data register


Basic timer control register

Clock control register

System flags register

Register pointer 0

Register pointer 1

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register (read-only)



Register page pointer




Port 0 pull-up enable register



Table 8-1. Set 1 Register Values After Reset

Mnemonic

T0CNT

T0DATA

Address

Dec

208

209

Hex

D0H

D1H

7

0

1

6

0

1

Bit Values After Reset

5

0

1

4

0

1

3

0

1

2

0

1

1

0

1

0

0

1

T0CON 210 D2H 0 0 0 0 0 0 0 0

BTCON 211 D3H 0 0 0 0 0 0 0 0

CLKCON 212 D4H 0 0 0 0 0 0 0 0

FLAGS 213 D5H

× × × × × ×

0 0

RP0 214 D6H 1 1 0 0 0 – – –

RP1 215 D7H 1 1 0 0 1 – – –

Location D8H (SPH) is not mapped.

SPL

IPH

IPL

217 D9H

× × × × × × × ×

218 DAH

× × × × × × × ×

219 DBH

× × × × × × × ×

IRQ

IMR

SYM

PP

220 DCH 0 0 0 0 0 0 0 0

221 DDH

× × × × × × × ×

222 DEH 0 – –

× × ×

0 0

223 DFH 0 0 0 0 0 0 0 0

P0

P1

224

225

E0H

E1H

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

P2 226 E2H 0 0 0 0 0 0 0 0

Location E3H–E6H is not mapped.

P0PUR 231 E7H 0 0 0 0 0 0 0 0

P0CONH 232 E8H 0 0 0 0 0 0 0 0

P0CONL 233 E9H 0 0 0 0 0 0 0 0

8-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RESET

and POWER-DOWN

Port 2 control register

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)


Stop control register

Basic timer counter

External memory timing register


Table 8-1. Set 1 Register Values After Reset (Continued)

Register Name



Port 1 pull-up enable register

Mnemonic

P1CONH

P1CONL

P1PUR

Address

Dec

234

235

Hex

EAH

7

0

Location EDH–EFH is not mapped.

P2CON

P0INT

P0PND

CACON

6

0

Bit Values After Reset

5

0

4

0

3

0

2

0

1

0

0

0

236 ECH 0 0 0 0 0 0 0 0

240

241

242

243

EBH

F0H

F1H

F2H

F3H

0

–

0

0

0

0

–

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

CADATAH 244 F4H 1 1 1 1 1 1 1 1

CADATAL 245 F5H 1 1 1 1 1 1 1 1

T1CNTH

T1CNTL

246 F6H 0 0 0 0 0 0 0 0

247 F7H 0 0 0 0 0 0 0 0

T1DATAH 248 F8H 1 1 1 1 1 1 1 1

T1DATAL 249 F9H 1 1 1 1 1 1 1 1

T1CON 250 FAH 0 0 0 0 0 0 0 0

STOPCON 251 FBH 0 0 0 0 0 0 0 0

Locations FCH is not mapped.

BTCNT 253 FDH

× × × × × × × ×

EMT

IPR

254 FEH 0 1 1 1 1 1 0 –

255 FFH

× × × × × × × ×

NOTES:

1. Although the SYM register is not used for the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 , SYM.5 should always be "0". If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur.

2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are

read/write addressable.

3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

4. Interrupt pending flags are noted by shaded table cells.

8-5

RESET


POWER-DOWN MODES

STOP MODE

Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 uA at 5.5 V. All system functions stop when the clock "freezes,"

Stop mode can be released of two ways : by an INTR (Interrupt with Reset) or by a POR (Power On Reset).

USING POR TO RELEASE STOP MODE

Stop mode is released when the reset signal goes active by power on reset (POR): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are unknown states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H.

USING AN INTR TO RELEASE STOP MODE

Stop mode is released when INTR (Interrupt with Reset) occurs. INTR occurs when falling/rising edge is detected at

P0 during stop mode and it make system reset.

NOTE

1. Do not use stop mode if you are using an external clock source because X

IN

input must be cleared

internally to V

SS

to reduce current leakage.

2. STOP mode always be released by the system reset (INTR or POR) so the system register value and

control register value are initialized as reset value. And when the reset occurs from INTR, the prime

register value will be retained but it will be unknown states if it occurs from POR. So an application

which is using stop mode should be added specific S/W which divide the system reset into STOP

mode releasing or power on reset. Following Programming Tip can be useful for more

understanding.

8-6

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RESET

and POWER-DOWN

F

PROGRAMMING TIP — To Divide STOP Mode Releasing and POR.

This example shows how to enter the stop mode and how to know it is stop mode releasing or power on RESET.

START

ORG

DI

LD

LD

CLR

CLR

CLR

CLR

•

•

•

•

LD

LD

LD

•

0100H

BTCON,#03h

SPL,#0FFH

SYM

PP

EMT

IPR

P0CONH,#00H

P0CONL,#00H

P0PUR,#0FFH

; Reset address

;

; enable basic timer counter.

; Initialize the system register

; Initialize the control register

; Check the RAM data whether it is stop mode releasing

; or Power On RESET

; If Power On Reset , go to POR_RESET

;

CHECK_RAM:

LD

CHK_R CP

JR

DEC

CP

JR

STOP_RESET:

JR

POR_RESET LD

RAM_CLR CLR

DJNJ

LD

R0,#0BFH

R0,@R0

NE,POR_RESET

R0

R0,#0B0H

UGE, CHK_R

MAIN

R0,#0FFH

@R0

R0,RAMCLR

R0,#0BFH

; STOP mode releasing.

;

; Power On Reset

; CHECK RAM data are failed so clear all RAM data.

; Initialize the CHECK RAM data as default value.

8-7

MAIN:

ENT_STOP

RESET


F

PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. (Continued)

CHK_W LD

DEC

CP

JR

@R0,R0

R0

R0,#0B0H

UGE,CHK_W

CP

JR

•

•

•

JP

•

•

LD

STOP

NOP

NOP

JP

•

P0,#0FFH

EQ,ENT_STOP

T,MAIN

STOPCON,#0A5H

RESET

;

; Enter the STOP mode.

8-8

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

RESET

and POWER-DOWN

IDLE MODE

Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active:

— Interrupt logic

— Timer 0

— Timer 1

— Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock because of the hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only way you can release Idle mode.

2. Activate any enabled interrupt ; internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode without reset. To release Idle mode, you can use either an external interrupt or an internally-generated interrupt.

8-9

RESET


SUMMARY TABLE OF STOP MODE, AND IDLE MODE

Item/Mode

Approach Condition

Release Source

Table 8-2. Summary of Each Mode

IDLE

V

DD

is higher than V

LVD

(V

LVD

<

V

DD

).

IDLE (instruction).

Interrupt

T0/T1 interrupt

Counter A interrupt

Ext. interrupt (Port0)

RESET

POR

LVD

WDT

RESET

INTR

POR

STOP

V

DD

is higher than V

LVD

(V

LVD

<

V

DD

).

STOPCON

≤

A5H

STOP instruction

8-10

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 I/O PORTS

9

I/O PORTS

OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller has three bit-programmable I/O ports, P0–P2.

Two ports, P0-P1, are 8-bit ports and P2 is a 3-bit port. This gives a total of 19 I/O pins in the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5"s 24-pin package. Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.

For IR universal remote controller applications, ports 0, and1 are usually configured to the keyboard matrix and port 2 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a LED.

Table 9-1 gives you a general overview of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 I/O port functions.

Port

0

1

2

Table 9-1. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 Port Configuration Overview

Configuration Options

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable

(P0INT) and pending control (P0PND); Pull-up resistors can be assigned to individual P0 pins using P0PUR register settings. Specially Interrupt with Reset(INTR) is assigned to release stop mode with system reset.

8-bit general-purpose I/O port; Input, open-drain output, or push-pull output. Pull-up resistors can be assigned to individual P1 pins using P1PUR register settings.

3-bit I/O port; input mode with or without pull-up, push-pull or open-drain output mode. REM and

T0PWM can be assigned. Port 2 pins have high current drive capability to support LED applications. The port 2 data register contains three status bits: three for P2.0, P2.1 and P2.2 and one for remote controller carrier signal on/off status.

9-1

I/O PORTS S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all three S3C80A4/C80A8/C80A5/C80B4/ C80B8/C80B5 port data registers. Data registers for ports 0, and 1 have the general format.

NOTE

The data register for port 2, P2, contains three bits for P2.0, P2.1 and P2.2, and an additional status bit for carrier signal on/off.

Register Name




Table 9-2. Port Data Register Summary

Mnemonic

P0

P1

P2

Decimal

224

225

226

Hex

E0H

E1H

E2H

R/W

R/W

R/W

R/W

Because port 2 is a 3-bit I/O port, the port 2 data register only contains values for P2.0, P2.1 and P2.2. The P2 register also contains values for P2.0, P2.1 and P2.2. The P2 register also contains a special carrier on/off bit(P2.5).

See the port 2 description for details. All other S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 I/O ports are 8-bit.

PULL-UP RESISTOR ENABLE REGISTERS

MSB

Pull-up Resistor Enable Register (PnPUR, where n = 0, 1)

(E7H, ECH), R/W

.7

.6

.5

.4

.3

.2

.1

.0

LSB

NOTE:

Pn.7

Pn.6

Pn.5

Pn.4

Pn.3

Pn.2

Pn.1

Pn.0

Pull-up resistor enable bit:

0 = Disable pull-up resistor

1 = Enable pull-up resistor

Pull-up resistors can be assigned to the port 2 pins, P2.0, P2.1 and P2.2

by marking the appropriate the port 2 control register, P2CON.

Figure 9-1. S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 I/O Port Data Register Format

9-2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 I/O PORTS

PORT 0

Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment using

P0PUR register settings and all pins have noise filters for external interrupt inputs.

Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins, P0.7–

P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3–P0.0. Each control register byte contains four bit-pairs and each bit-pair configures one pin (see Figures 9-2 and 9-3). A hardware reset clears all P0 control and data registers to '00H'.

A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable external interrupt input. You can poll the port 0 interrupt pending register, P0PND to detect and clear pending conditions for these interrupts.

The lower-nibble pins, P0.3–P0.0, are used for INT3–INT0 input (IRQ6), respectively. The upper nibble pins, P0.7–

P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed using the same vector address (E8H).

Port 0 , P0.0–P0.7, is assigned interrupt with reset(INTR) to release stop mode with system reset.

MSB .7

Port 0 Control Register, High Byte (P0CONH)

E8H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P0CONH Pin Configureation Settings:

00

01

10

11

Input mode; interrupt on falling edges

Input mode; interrupt on rising and falling edges

Push-pull output mode

Input mode; interrupt on rising edges

Figure 9-2. Port 0 High-Byte Control Register (P0CONH)

9-3


MSB .7

Port 0 Control Register, Low Byte (P0CONL)

E9H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0CONL Pin Configureation Settings:

00

01

10

11

Input mode; interrupt on falling edges

Input mode; interrupt on rising and falling edges


Input mode; interrupt on rising edges

Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)

PORT 0 INTERRUPT ENABLE REGISTER (P0INT)

The port 0 interrupt control register, P0INT, is used to enable and disable external interrupt input at individual P0 pins

(see Figure 10-5). To enable a specific external interrupt, you set its P0INT.n bit to "1". You must also be sure to make the correct settings in the corresponding port 0 control register (P0CONH, P0CONL).

PORT 0 INTERRUPT PENDING REGISTER (P0PND)

The port 0 interrupt pending register, P0PND, contains pending bits (flags) for each port 0 interrupt (see Figure 10-6).

When a P0 external interrupt is acknowledged by the CPU, the service routine must clear the pending condition by writing a "0" to the appropriate pending flag in the P0PND register (Writing a "1" to the pending bit has no effect).

NOTE

A hardware reset(INTR, POR) clears the P0INT and P0PND registers to '00H'. For this reason, the application program's initialization routine must enable the required external interrupts for port 0, and for the other I/O ports.

9-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB .7

Port 0 Interrup Enable Register (P0INT)

F1H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.6/INT4

P0.7/INT4

P0.4/INT4

P0.5/INT4

P0.2/INT2

P0.3/INT3

P0.0/INT0

P0.1/INT1

Port 0 Interrupt Enable Bits:

0

1

Disable interrupt

Enable interrupt

Figure 9-4. Port 0 External Interrupt Control Register (P0INT)

MSB .7

Port 0 Interrup Pending Register (P0PND)

F2H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P0.6/INT4

P0.7/INT4

P0.4/INT4

P0.5/INT4

P0.2/INT2

P0.3/INT3

P0.0/INT0

P0.1/INT1

Port 0 Interrupt Pending Bits:

0

0

1

1

Interrupt not pending

Clear P0.n pending condition (when write)

P0.n interrupt is pending


Figure 9-5. Port 0 External Interrupt Pending Register (P0PND)

I/O PORTS

9-5


PORT 1

Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1 data register, P1 (set 1, E1H).

To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers: P1CONH

(set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins, P1.3–P1.0.

Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see Figures 9-6 and 9-

7).

Following a hardware reset, the port 1 control registers are cleared to '00H', configuring port 0 initially to Input mode.

To assign pull-up resistors to P1 pins, you make the appropriate settings to the port 1 pull-up resistor enable register, P1PUR.

MSB .7

Port 1 Control Register, High Byte (P1CONH)

EAH, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P1.4

P1.5

P1.6

P1.7

P1CONH Pin Configureation Settings:

00

01

10

11

Input mode

Open-drain output mode


Invalid setting

Figure 9-6. Port 1 High-Byte Control Register (P1CONH)

9-6

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB .7

Port 1 Control Register, Low Byte (P1CONL)

EBH, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

P1.0

P1.1

P1.2

P1.3

P1CONL Pin Configureation Settings:

00

01

10

11

Input mode



Invalid setting

Figure 9-7. Port 1 Low-Byte Control Register (P1CONL)

I/O PORTS

9-7


PORT 2

Port 2 is a bit-programmable 3-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2 data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode, or push-pull output mode.

P2.0, P2.1 and P2.2 are configured by writing 6-bit data value to the port 2 control register, P2CON. You can configure these pins to support input functions (Input mode, with or without pull-up, for T0CK) or output functions

(push-pull or open-drain output mode for REM and timer 0 PWM).

Port 2 pins have high current drive capability to support LED applications.

A reset operation clears P2CON to '00H', selecting Input mode as the initial port 2 function.

MSB .7

.6

Port 2 Control Register (P2CON)

F0H, R/W

.5

.4

.3

.2

.1

P1.0

.0

LSB

P2.2

P2.1

P2.2

P2.1 Alternative Function Enable

0

1

Normal I/O Function

REM/T0CK

P2.0 Alternative Function Enable

0

1

Normal I/O Function

T0PWM

P2CON Pin Configuration Setting:

00

01

10

11

C-MOS input mode



C-MOS input mode with pull-up

Figure 9-8. Port 2 Control Register (P2CON)

9-8

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB .7

.6

Port 2 Data Register (P2)

E2H, R/W

.5

.4

.3

.2

.1

.0

LSB

Not used for S3C80A5

P2.0/T0_PWM

Carrier on/off for Remote Controller

P2.2

Not used for S3C80A5

P2.1/REM/TOCK

Figure 9-9. Port 2 Data Register (P2)

I/O PORTS

9-9

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 BASIC TIMER AND TIMER 0

10

BASIC TIMER and TIMER 0

MODULE OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or

— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode.

A system reset clears BTCON. This enables the watchdog function and selects a basic timer clock frequency of f

OSC

/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer register control bits BTCON.7–BTCON.4. For more reliability, we recommend to use the Watch-dog timer function in remote controller and hand-held product application.

10-1

BASIC TIMER and TIMER 0 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB .7

Basic Timer Control Register (BTCON)

D3H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Watchdog function enable bits:

1010B = Disable watchdog timer

Other value = Enable watchdog timer

Divider clear bit for basic timer and timer 0:

0 = No effect

1 = Clear both dividers

Basic timer input clock selection bits:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00

01

10

11 f

OSC

/4096 f

OSC

/1024 f

OSC

/128

Invalid selection

Figure 10-1. Basic Timer Control Register (BTCON)

10-2


BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by enabling the watchdog function. A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting),divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match interrupt

— Clear timer 0 match interrupt pending conditions

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of f

OSC

/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a match interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a timer 0 match interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

10-3


MSB .7

.6

Timer 0 Control Register (T0CON)

D2H, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = f

OSC

/4096

01 = f

OSC

/256

10 = f

OSC

/8

11 = External clock (P2.1/T0CK)

Timer 0 match interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (write)

1 = Interrupt is pending

Timer 0 operating mode selection bits:

00 = Interval mode

01 = Overflow mode (OVF interrupt can occur)


11 = PWM mode (OVF interrupt can occur)

Timer 0 match interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 10-2. Timer 0 Control Register (T0CON)

10-4


TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. The

T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a "0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH) and clears the counter.

If, for example, you write the value ‘10H’ to T0DATA and ‘0BH’ to T0CON, the counter will increment until it reaches

‘10H’. At this point, the T0 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

IRQ0(INT)

Pending

(T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

R (Clear)

CLK Counter

Comparator

Buffer Register

Match

CTL

T0CON.5

T0CON.4

P2.0

Match Signal

T0CON.3

Data Register

Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-5


Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data value is less than or equal to (

≤

) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t

CLK

×

256 (see Figure 11-4).

IRQ0(T0INT)

PND (T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

CLK Counter

Comparator

Buffer Register

IRQ0 (T0OVF)

Match

CTL

T0CON.5

T0CON.4

Match Signal

T0CON.3

T0OVF

P2.0/

T0PWM

High level when data > counter;

Low level when

Data Register

NOTE: Interrupts are usually not used when timer 0 is configurared to operate in PWM mode

Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode

10-6


X

IN

Bits 3,2

1/4096

DIV

1/1024

1/128

R

MUX

Bit 1

RESET or Stop

Data Bus

Clear

8-Bit Basic Counter

(Read-Only)

Basic Timer Control Register

(Write '1010xxxxB' to disable)

OVF

RESET

Bit 0

Bits 7,6

R

1/4096

DIV

1/1024

1/128

MUX

P2.1/T0CK

Bit 2

Data Bus

8-Bit Up-Counter

(Read-Only)

R

OVF

Bit 3

Clear

8-Bit Comparator

Timer 0 Buffer Reg

Timer 0 Data Register

(Read/Write)

Match

(2)

Bit 1

T0CON.0

PND

T0PWM

P2.0

T0INT

Bits 5,4

Match Signal

T0CON.3

T0OVF

Basic Timer Control Register

Timer 0 Control Register

Data Bus

NOTES:

1.

2.

During a power-on reset operation, the CPU is idle during the required oscillation stabilizatiin interval (until bit 4 of the basic timer counter overflows).

It is available only in using interval mode.

Figure 10-5. Basic Timer and Timer 0 Block Diagram

10-7


F

PROGRAMMING TIP — Configuring the Basic Timer

LD

•

•

•

JP

•

NOP

NOP

•

•

•

•

DI

LD

LD

CLR

CLR

•

•

•

SRP

EI

•

This example shows how to configure the basic timer to sample specifications:

ORG 0100H

MAIN

RESET

BTCON,#03H

CLKCON,#18H

SYM

SPL

#0C0H

BTCON,#02H

T,MAIN

; Disable all interrupts

; Enable the watchdog timer

; Non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte

←

"0"

; Stack area starts at 0FFH

; Set register pointer

; Enable interrupts

←

0C0H

; Enable the watchdog timer

; Basic timer clock: f

OSC

/4096

; Clear basic timer counter

10-8


F

Programming Tip — Programming Timer 0

RESET

LD

LD

CLR

CLR

•

•

•

LD

LD

SRP

EI

•

•

•

This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds

— Oscillation frequency is 6 MHz

— General register 60H (page 0)

←

60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt

ORG 0FAH

VECTOR T0OVER

ORG 0FCH

VECTOR T0INT

ORG 0100H

; Timer 0 overflow interrupt

; Timer 0 match/capture interrupt

DI

SYM

SPL

#0C0H

BTCON,#0AAH

CLKCON,#18H

T0CON,#4BH ;

T0DATA,#5DH

; Disable all interrupts

; Disable the watchdog timer

; Select non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte

←

"0"

; Stack area starts at 0FFH

Write '01001011B'

; Input clock is f

OSC

/256

; Interval timer mode

; Enable the timer 0 interrupt

; Disable the timer 0 overflow interrupt

; Set timer interval to 4 milliseconds

; (6 MHz/256)

÷

(93 + 1) = 0.25 kHz (4 ms)

; Set register pointer

; Enable interrupts

←

0C0H

10-9


F

PROGRAMMING TIP — Programming Timer 0 (Continued)

T0INT

CP

NO_200MS_SET:

LD

POP

T0OVER IRET

PUSH

SRP0

INC

ADD

ADC

ADC

R0,#32H

JR

BITS

RP0

#60H

R0

R2,R0

R3,R2

R4,R0

ULT,NO_200MS_SET

R1.2

T0CON,#42H

RP0

; Save RP0 to stack

; RP0

←

60H

; R0

←

R0 + 1

; R2

←

R2 + R0

; R3

←

R3 + R2 + Carry

; R4

←

R4 + R0 + Carry

; 50

×

4 = 200 ms

; Bit setting (61.2H)

; Clear pending bit

; Restore register pointer 0 value

; Return from interrupt service routine

10-10

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 TIMER 1

11

TIMER 1

OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller has a 16-bit timer/counter called timer 1 (T1). For universal remote controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has the following components:

— One control register, T1CON (set 1, FAH, R/W)

— Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)

— Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)

— A 16-bit comparator

You can select one of the following clock sources as the timer 1 clock:

— Oscillator frequency (f

OSC

) divided by 4, 8, or 16

— Internal clock input from the counter A module (counter A flip/flop output)

You can use Timer 1 in two ways:

— As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time intervals.

— To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the 16-bit value written to the reference data registers.

In the S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1 match.

11-1

TIMER 1 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

TIMER 1 OVERFLOW INTERRUPT

Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can clear/reset the 16-bit counter value at any time during program operation.

TIMER 1 MATCH INTERRUPT

Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.

In match mode, program software can poll the timer 1 match interrupt pending bit, T1CON.0, to detect when a timer

1 match interrupt pending condition exists (T1CON.0 = "1"). When the interrupt request is acknowledged by the

CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a “0” to T1CON.0.

IRQ1(T1INT)

Pending

(T1CON.0)

Interrupt

Enable/Disable

(T1CON.2)

CLK

16-Bit UP Counter

(Read-Only)

R (Clear)

16-Bit Comparator

Match

CTL

T1CON.5

T1CON.4

Timer 1 High/Low

Buffer Register

Match Signal

T1CON.3

Timer 1 Data High/Low

Buffer Register

Figure 11-1. Simplified Timer 1 Function Diagram: Interval Timer Mode

11-2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 TIMER 1

T1CON.7-.6

CAOF (T-F/F) f

OSC

/4 f

OSC

/8 f

OSC

/16

MUX

T1CON.2

OVF

16-Bit Up-Counter

(Read-Only)

R

T1CON.3

Clear

16-Bit Comparator

Match

(note)

M

U

X

T1CON.1

Timer 1 High/Low

Buffer Register

T1CON.5-.4

T1CON.0

T1CON.3

Match Signal

T1OVF

Timer 1 Data

High/Low Register

IRQ1

IRQ1

Data Bus

NOTES:

Match signal is occured only in interval mode.

Figure 11-2. Timer 1 Block Diagram

11-3

TIMER 1 S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains control settings for the following T1 functions:

— Timer 1 input clock selection

— Timer 1 operating mode selection

— Timer 1 16-bit down counter clear

— Timer 1 overflow interrupt enable/disable

— Timer 1 match interrupt enable/disable

— Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to ‘00H’, selecting f

OSC divided by 4 as the T1 clock, configuring timer 1 as a normal interval timer, and disabling the timer 1 interrupts.

MSB .7

.6

Timer 1 Control Register (T1CON)

FAH, R/W

.5

.4

.3

.2

.1

.0

LSB

Timer 1 input clock selection bits:

00 = f

OSC

/4

01 = f

OSC

/8

10 = f

OSC

/16

11 = Internal clock (T-F/F)

Timer 1 match interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (write)

1 = Interrupt is pending

Timer 1 operating mode selection bits:

00 = Interval mode




Timer 1 match interrupt enable bit:



Timer 1 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 1 counter (when write)

Figure 11-3. Timer 1 Control Register (T1CON)

11-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MSB .7

Timer 1 Counter High-Byte Register (T1CNTH)

F6H, Set 1, R

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : 00H

MSB .7

Timer 1 Counter Low-Byte Register (T1CNTL)

F7H, Set 1, R

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : 00H

MSB .7

Timer 1 Data High-Byte Register (T1DATAH)

F8H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : FFh

MSB .7

Timer 1 Data Low-Byte Register (T1DATAL)

F9H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : FFh

Figure 11-4. Timer 1 Registers

TIMER 1

11-5

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 COUNTER A

12

COUNTER A

OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller has an 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (see Figure 12-1):

— Counter A control register, CACON

— 8-bit down counter with auto-reload function

— Two 8-bit reference data registers, CADATAH and CADATAL

Counter A has two functions:

— As a normal interval timer, generating a counter A interrupt (IRQ4, vector ECH) at programmed time intervals.

— To supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow interrupt.

12-1

COUNTER A S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

f

OSC

CACON.6-.7

DIV 1

DIV 2

DIV 4

DIV 8

MUX

CLK 8-Bit

Down Counter

CACON.2

Repeat

Control

Interrupt

Control

CACON.4-.5

CACON.0

(CAOF)

MUX

Counter A Data

Low Byte Register

Counter A Data

High Byte Register

INT.GEN.

CACON.3

To Other Block

(P3.1/REM)

IRQ4

(CAINT)

Data Bus

NOTES:

The value of the CADATAL register is loaded into the 8-bit counter when the operaion of the counter A

Starts. If a borrow occurs in the counter, the value of the CADATAH register is loaded into the 8-bit counter. However, if the next borrow ovvurs, the value of the CADATAL register is loaded into the 8-bit counter.

Figure 12-1. Counter A Block Diagram

12-2


COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON contains control settings for the following functions (see Figure 12-2):

— Counter A clock source selection

— Counter A interrupt enable/disable

— Counter A interrupt pending control (read for status, write to clear)

— Counter A interrupt time selection

MSB .7

Counter A Control Register (CACON)

F3H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Counter A input clock Counter A output flip-flop selection bits:

00 = f

OSC

01 = f

OSC

/2

10 = f

OSC

/4

11 = f

OSC

/8 control bit:

0 = T-FF is Low

1 = T-FF is High

Counter A mode selection bit:

0 = One-shot mode

1 = Repeating mode

Counter A interrupt selection bits:

00 = Elapsed time for Low data value

01 = Elapsed time for High data value

10 = Elapsed time for Low and High

data values

11 = Invalid setting

Counter A start/stop bit:

0 = Stop counter A

1 = Start counter A

Counter A interrupt enable bit:



Figure 12-2. Counter A Control Register (CACON)

12-3


MSB .7

Counter A Data High-Byte Register (CADATAH)

F4H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : FFh

MSB .7

Counter A Data Low-Byte Register (CADATAL)

F5H, Set 1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : FFh

Figure 12-3. Counter A Registers

COUNTER A PULSE WIDTH CALCULATIONS

t

HIGH t

LOW t

LOW

To generate the above repeated waveform consisted of low period time, t

LOW

, and high period time, t

HIGH

.

When CAOF = 0,

t

LOW

= (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

t

HIGH

= (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

When CAOF = 1,

t

LOW

= (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

t

HIGH

= (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

To make t

LOW

= 24 us and t

HIGH

= 15 us. f

OSC

= 4 MHz, fx = 4 MHz/4 = 1 MHz

[Method 1] When CAOF = 0, t

LOW

= 24 us = (CADATAL + 2) /fx = (CADATAL + 2)

×

1us, CADATAL = 22. t

HIGH

= 15 us = (CADATAH + 2) /fx = (CADATAH + 2)

×

1us, CADATAH = 13.

[Method 2] When CAOF = 1, t

HIGH

= 15 us = (CADATAL + 2) /fx = (CADATAL + 2)

×

1us, CADATAL = 13. t

LOW

= 24 us = (CADATAH + 2) /fx = (CADATAH + 2)

×

1us, CADATAH = 22.

12-4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

0H

Counter A

Clock

CAOF = '0'

CADATAL = 01-FFH

CADATAH = 001H

CAOF = '0'

CADATAL = 00H

CADATAH = 01-FFH

CAOF = '0'

CADATAL = 00H

CADATAH = 00H

CAOF = '1'

CADATAL = 00H

CADATAH = 00H

High

Low

Low

High

0H

Counter A

Clock

CAOF = '0'

CADATAL = DEH

CADATAH = 1EH

CAOF = '0'

CADATAL = DEH

CADATAH = 1EH

CAOF = '1'

CADATAL = 7EH

CADATAH = 7EH

CAOF = '0'

CADATAL = 7EH

CADATAH = 7EH

80H

80H

E0H

E0H

80H

20H

20H

80H

Figure 12-4. Counter A Output flip-flop Waveforms in Repeat Mode

COUNTER A

12-5


F

PROGRAMMING TIP — To Generate 38 kHz, 1/3duty Signal Through P2.1

This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and

CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are:

8.795

µ s

17.59

µ s

37.9 kHz 1/3 Duty

— Counter A is used in repeat mode

— Oscillation frequency is 4 MHz (0.25

µ s)

— CADATAH = 8.795

µ s / 0.25

µ s = 35.18, CADATAL = 17.59

µ s / 0.25

µ s = 70.36

— Set P2.1 C-MOS push-pull output and CAOF mode.

START

ORG

DI

•

•

•

LD

LD

LD

LD

•

•

LD

•

0100H

CADATAL,#(70-2)

CADATAH,#(35-2)

P2CON,#10101010B

CACON,#00000110B

P2,#20H

; Reset address

; Set 17.5

; Set 8.75

;

µ

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

; Clock Source

← f

OSC

; Disable Counter A interrupt.

; Select repeat mode for Counter A.

; Start Counter A operation.

; Set Counter A Output Flip-flop(CAOF) high.

;

; Set P2.5(Carrier On/Off) to high.

; This command generates 38 kHz, 1/3duty pulse signal

; through P2.1

;

µ s s

12-6


F

PROGRAMMING TIP — To Generate a One Pulse Signal Through P2.1

This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40

µ s width pulse. The program parameters are:

40

µ s

— Counter A is used in one shot mode

— Oscillation frequency is 4 MHz (1 clock = 0.25

µ s)

— CADATAH = 40

µ s / 0.25

µ s = 160, CADATAL = 1

— Set P2.1 C-MOS push-pull output and CAOF mode.

0100H ; Reset address

START

Pulse_out: LD

•

•

•

ORG

DI

•

•

LD

LD

LD

LD

•

•

LD

•

CADATAH,# (160-2)

CADATAL,# 1

P2CON,#10101010B

CACON,#00000001B

P2,#20H

CACON,#00000101B

; Set 40

µ s

; Set any value except 00H

;

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

; Clock Source

← f

OSC

; Disable Counter A interrupt.

; Select one shot mode for Counter A.

; Stop Counter A operation.

; Set Counter A Output flip-flop (CAOF) high

; Set P2.5(Carrier On/Off) to high.

; Start Counter A operation

; to make the pulse at this point.

; After the instruction is executed, 0.75

µ s is required

; before the falling edge of the pulse starts.

12-7

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

13

ELECTRICAL DATA

OVERVIEW

In this section, S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 electrical characteristics are presented in tables and graphs. The information is arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by a Reset

— A.C. electrical characteristics

— Input timing for external interrupts (port 0)

— Oscillation stabilization time

13-

1

ELECTRICAL DATA S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

(T

A

= 25

°

C)

Parameter Symbol

Supply voltage

Input voltage

Output voltage

V

DD

V

IN

V

O

Table 13-1. Absolute Maximum Ratings

Conditions

All output pins

–

–

Output current high

Output current low

I

OH

I

OL

One I/O pin active

All I/O pins active

One I/O pin active

Operating temperature

Storage temperature T

T

A

STG

Total pin current for ports 0, 1, and 2

Total pin current for port 3

–

–

Rating Unit

– 0.3 to + 6.5 V

– 0.3 to V

DD

+ 0.3

– 0.3 to V

DD

+ 0.3

– 18

V

V mA

– 60

+ 30 mA

+ 100

+ 40

– 25 to + 85

°

C

– 65 to + 150

°

C

Table 13-2. D.C. Electrical Characteristics

(T

A

= –25

°

C to +85

°

C, V

DD

= 1.7V(2.0V) to 3.6 V(5.5V))


Operating voltage

Input high voltage

Input Low voltage

Output high voltage

V

DD

V

V

V

IL1

V

V

V

V

IH1

IH2

IL2

OH1

OH2

OH3

Conditions

S3C80A4/C80A8/C80A5 f

OSC

=

8 MHz


S3C80B4/C80B8/C80B5 f

OSC

=

4 MHz


All input pins except V

IH2 and

V

IH3

X

IN

All input pins except V

IL2 and V

IL3

X

IN

V

DD

= 2.4 V, I

OH

= – 6 mA

Port 2.1 only

V

DD

= 2.4 V, I

OH

= – 2.2mA

Port 2.0, 2.2

V

DD

= 2.4 V, I

OH

= – 1 mA

All output pins except Port2

V

V

V

V

Min Typ Max Unit

2.0 – 5.5 V

1.7 – 3.6

0.8 V

DD

DD

DD

-

DD

-

DD

– 0.3

– 0.7

0.7

1.0

–

V

V

DD

DD

0.2 V

DD

V

V

0.3

– – V

13-

2

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

Table 13-2. D.C. Electrical Characteristics (Continued)

(T

A

= –25

°

C to +85

°

C, V

DD

= 1.7V(2.0V) to 3.6 V(5.5V))

Parameter Symbol Conditions Min Typ Max Unit

Output low voltage

Input high leakage current

V

OL1

V

DD

= 2.4 V, I

OL

= 12 mA, port

2.1 only

V

OL2

V

DD

= 2.4 V, I

OL

= 5 mA

Port 2.0,2.2

V

OL3

I

OL

= 1 mA

Ports 0 and 1

I

LIH1

V

IN

= V

DD

All input pins except X

IN and

X

OUT

I

LIH2

V

IN

= V

DD

, X

IN and X

OUT

0.4 0.5

0.4 1.0

20

Input low leakage current

Output high leakage current

Output low leakage current

I

LIL1

V

IN

= 0 V

All input pins except X

IN

, X

OUT

I

LIL2

V

IN

= 0 V

X

IN and X

OUT

I

LOH

V

OUT

= V

DD

All output pins

I

LOL

V

OUT

= 0 V

All output pins

–

– 20

–

µA

µA

Pull-up resistors 44 55 95 k

Ω

Supply current

(note)

R

L1

V

DD

= 2.4V, V

IN

= 0 V;

T

A

= 25

°

C , Ports 0-2

I

DD1

V

DD

= 5.5V

8-MHz crystal

4-MHz crystal, V

DD

= 3.6 V

I

DD2

Idle mode;

V

DD

= 5.5 V

8-MHz crystal

4-MHz crystal, V

DD

= 3.6 V

I

DD3

Stop mode; T

A

= 25

°

C

V

DD

= 3.6 V (5.5 V)

2.6 5

– 2 4

0.7 2.0

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.


13-

3


Table 13-3. Characteristics of Low Voltage Detect circuit

(T

A

= 25

°

C)

Parameter

Hysteresys voltage of LVD

(Slew Rate of LVD)


(S3C80A4/C80A8/C80A5)


(S3C80B4/C80B8/C80B5)

Symbol Conditions Min Typ Max Unit

V

V

∆V

LVD

LVD

Table 13-4. Data Retention Supply Voltage in Stop Mode

(T

A

= –25

°

C to +85

°

C)

Parameter Symbol Conditions

Data retention supply voltage

V

DDDR

Data retention supply current

I

DDDR

V

DDDR

= 1.0 V

Stop mode

V

(5.5V)

– – 1 µA

(T

A

= –25

°

C to +85

°

C, V

DD

= 0 V)

Table 13-5. Input/output Capacitance

Min Typ Max Unit Parameter Symbol

Input capacitance

C

IN

Conditions

f = 1 MHz; unmeasured pins are connected to V

SS

Output capacitance

C

OUT

I/O capacitance C

IO

Table 13-6. A.C. Electrical Characteristics

(T

A

= –25

°

C to +85

°

C)


Interrupt input,

High, Low width t

INTH

, t

INTL

Conditions

P0.0–P0.7, V

DD

= 3.6V (5.5V)

200 300 – ns

13-

4

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

t

INTL t

INTH

0.8 V

DD

0.2 V

DD

NOTE: The unit t

CPU

means one CPU clock period.

Figure 13-1. Input Timing for External Interrupts (Port 0)

Table 13-7. Oscillation Characteristics

(T

A

= –25

°

C +85

°

C)

Crystal

C1

Ceramic

External clock

NOTES:

C2

X

IN

Conditions Min


1 – 8

(1)

X

OUT

1 – 4

(2)

MHz

1 – 8

(1)

MHz

C1

C2

XT

IN

XT

OUT


External

Clock

Open Pin

X

IN

X

OUT

X

IN input frequency

1 – 4

(2)

1 – 8

(1)

MHz

1 – 4

(2)

13-

5


Table 13-8. Oscillation Stabilization Time

(T

A

= –25

°

C +85

°

C, V

DD

= 3.6 V(5.5V))

Main crystal

Main ceramic f

OSC

> 400 kHz

Oscillation stabilization occurs when V

DD

is equal to the minimum oscillator voltage range.

X

IN input High and Low width (t

XH

, t

XL

)

– – 20 ms

External clock

(main system)

Oscillator stabilization wait time t t

WAIT

when released by a reset

(1)

WAIT

when released by an interrupt

(2)

–

2

16

/ f

OSC

– ms

NOTES:

1. f

OSC

is the oscillator frequency.

2. The duration of the oscillation stabilization time (t

WAIT

) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.

Instruction

Clock

1.33 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

A

B

Instruction

Clock

8 MHz

6 MHz

4 kHz

8.32 kHz 400 kHz

1 2 3 4 5 6 7

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

A 1.7 V: 4 MHz (S3C80B4/C80B8/C80B5)

B 2.0 V: 8 MHz (S3C80A4/C80A8/C80A5)

Figure 13-2. Operating Voltage Range of S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

13-

6

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MECHANICAL DATA

14

MECHANICAL DATA

OVERVIEW

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 microcontroller is currently available in a 24-pin SOP and SDIP package.

0-8

#24 #13

24-SOP-375

#1 #12

0.15

+ 0.10

- 0.05

15.74 MAX

15.34

± 0.20

(0.69)

1.27

0.38

+ 0.10

- 0.05

NOTE : Dimensions are in millimeters.

Figure 14-1. 24-Pin SOP Package Mechanical Data

0.10 MAX

14-1

MECHANICAL DATA

#24

24-SDIP-300

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

#13

0-15

+ 0.10- 0.05

0.25

#1 #12

23.35 MAX

22.95

± 0.20

(1.70)

0.46 ±

0.10

0.89 ±

0.10

NOTE: Dimensions are in millimeters.

1.778

Figure 14-2. 24-Pin SDIP Package Mechanical Data

14-2

S3C8 SERIES MASK ROM ORDER FORM

Product description:

Device Number: S3C80A4 S3C80A8 S3C80A5 S3C80B4 S3C80B8 S3C80B5

S3C__________- ___________(write down the ROM code number)

(note)

Package Type: __________ Product Order Form:

SEC

@ YWW

Device Name

Package Pellet Wafer

Package Marking (Check One):

Standard Custom A

(Max 10 chars)

@ YWW

Device Name

Custom B

(Max 10 chars each line)

@ YWW

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

Delivery Dates and Quantities:

Deliverable

ROM code

Customer sample

Risk order

Required Delivery Date

–

Quantity

Not applicable

Comments

See ROM Selection Form

See Risk Order Sheet

Please answer the following questions:

F

For what kind of product will you be using this order?

New product Upgrade of an existing product

Replacement of an existing product Other

If you are replacing an existing product, please indicate the former product name

( )

F

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price Product quality Features and functions

Development system Technical support Delivery on time

Used same micom before Quality of documentation Samsung reputation

Mask Charge (US$ / Won): ____________________________

Customer Information:

Company Name:___________________ Telephone number _________________________

Signatures:________________________

(Person placing the order)

__________________________________

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C8 SERIES

REQUEST FOR PRODUCTION AT CUSTOMER RISK

Customer Information:

Company Name:

Department:

Telephone Number:

Date:

________________________________________________________________

________________________________________________________________

__________________________ Fax: _____________________________

__________________________

Risk Order Information:

Device Number: S3C80A4 S3C80A8 S3C80A5 S3C80B4 S3C80B8 S3C80B5

S3C8__________- ___________(write down the ROM code number)

(note)

Package: Number of Pins: ____________ Package Type: _____________________

Intended Application:

Product Model Number:

________________________________________________________________

________________________________________________________________

Customer Risk Order Agreement:

We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved.

Order Quantity and Delivery Schedule:

Risk Order Quantity: _____________________ PCS

Delivery Schedule:

Delivery Date (s) Quantity Comments

Signatures:

_______________________________ _______________________________________

(Person Placing the Risk Order) (SEC Sales Representative)



S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

MASK OPTION SELECTION FORM

Device Number: S3C80A4 S3C80A8 S3C80A5 S3C80B4 S3C80B8 S3C80B5

S3C8__________- ___________(write down the ROM code number)

(note)

Attachment (Check one): Diskette PROM

Customer Checksum:

Company Name:

Signature (Engineer):

________________________________________________________________

________________________________________________________________

________________________________________________________________

Please answer the following questions:

F

Application (Product Model ID: _______________________)

Audio

LCD Databank

Video

Caller ID

Industrials Home Appliance

Remocon

Please describe in detail its application

Other

Telecom

LCD Game

Office Automation



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